Hello! I am new at veditor, I searched on discussion forums and google but can't find the answer, how to build my VHDL code?
I created a Verilog/VHDL Project.
Created two .vhd files (GenericMUX.vhd and MUX.vhd)
There is also a .project file created automatically
How do I build my project? See the schematic view? Simulate it? I installed FreeHDL from here http://www.freehdl.seul.org/index.html (I am using Ubuntu 12.04 x64).
Can I call Xilinx ISE compiler/debugger from veditor?
Thank you very much in advance
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
VEditor is not a compiler or a schematics viewer. You will have to launch those tools externally via "Project Build". You can use the error parser feature to link lines of code with error messages from your compiler/simulator.
It does support code completion, folding and many other features that makes the editing of your code easier.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Hello! I am new at veditor, I searched on discussion forums and google but can't find the answer, how to build my VHDL code?
How do I build my project? See the schematic view? Simulate it? I installed FreeHDL from here http://www.freehdl.seul.org/index.html (I am using Ubuntu 12.04 x64).
Can I call Xilinx ISE compiler/debugger from veditor?
Thank you very much in advance
VEditor is not a compiler or a schematics viewer. You will have to launch those tools externally via "Project Build". You can use the error parser feature to link lines of code with error messages from your compiler/simulator.
It does support code completion, folding and many other features that makes the editing of your code easier.