Eclipse Verilog editor / News: Recent posts

Vesion 1.2.2 Released

Version 1.2.2 is same with the development build 1.2.1.c on November 2015.

This release includes some Verilog features:
- Add AutoEditStrategy for Verilog multi-line comment.
- Exactly matching for occurrence marker in Verilog.
- Add write occurrence marker in Verilog.
- Update outline database when selection is changed for occurrence marker.

Posted by KOBAYASHI Tadashi 2016-05-04

Vesion 1.2.1 Released

Version 1.2.1 was built and tested on Eclipse Luna SR2.

This release includes:
- Added some Verilog syntax checks.

From Sjors Hettinga:
- Ignoring encrypted Verilog code, based on the protected pragma.
- Using the used VHDL packages in a file, when jumping to a declaration of this value in a package.
- Upon VHDL detection of multiple implementations of the item you want to jump to.
- VHDL various syntax checks.... read more

Posted by KOBAYASHI Tadashi 2015-05-05

Vesion 1.2.0 Released

Version 1.2.0 is here. As of this release, all official builds will use Java 7.

This release includes:
From Illian Dinev:
Added support for subtype definition jumping.
Improved code info hit popup
Autocomplete of "use" with common ieee libraries
New templates for record, array and subtype

From Maximilian Girlich:
Improved New File Template selection (for Verilog and VHDL)
Improved formatting in VHDL (alignment on => := and directional directives)

Posted by aghoras 2013-07-01

VEditor 1.2 (Testing)

VEditor 1.2 is available via the testing update site. See the bottom of You can also put the main wiki page ( for information on how to get the latest testing version.

New Features:
+ Better association of build errors with source files
+ Better handling of direct VHDL instantiations in the outline
+ Ability to use variables in the compile/simulate/build commands

Posted by aghoras 2013-04-24

VEditor 1.1.1

The new version fixed some bugs and improved Verilog semantics checker.

  • Fixed format bug(ID 3553659)
  • Debug evaluation of parameter expression.
  • Stricter bit width checking of assignment and operation.
  • Checking input or output port connection.
Posted by KOBAYASHI Tadashi 2013-04-10

VEditor 1.1.0

The new version improves Verilog parser.

New Features:
* Verilog syntax check more strictly.
* Add waring preference page.
* Add waring annotation about the followings:
"never used", "never assigned", "cannot be resolved", "assignment bit width mismatch" and "blocking and non-blocking assignment"
* Calculate parameter and localparam value in annotation hover.

Posted by KOBAYASHI Tadashi 2012-11-03

VEditor 1.0.0

It's time for another release of the VEditor. Even though, the version is reved to 1.0.0, this is a routine release. It will however, make future test releases easier by not wasting an extra digit. If the Linux kernel can do it, so can we :). Thanks to Stijn and Silvio for their contributions.
Here’s the list of bug fixes:
* Multi-line tabbing problem (ID 2726346)
* VHDL parser hangs (BUG ID 2952670)
* when using autocompletion, files often get mixed line endings
* mismatch between the classes RecordElement and TypeDecl, making autocompletion of record members to malfunction
* Fixed VHDL parser errors (3034727, and 1835772)... read more

Posted by aghoras 2011-09-12

VEditor update and Testing Site

The VEditor update and testing sites are operational again. See the Download section of the main page for details.

Posted by aghoras 2011-09-12

VEditor 0.7.1 Released

It's time for another version release. Bug fixes:
* When opening a very large VHDL file, the program may freeze or run out of memory.

* Type definitions did not show properly in the file outline.

Posted by aghoras 2010-04-09

Version 0.7.0 Released

Version 0.7.0 is released. Thanks to Stijn Last and his team for submitting most of the new features. Here's a list of what's new:

* Goto Definition now also searches in packages of other files, not only in current file.
* Solved few bugs, added alignment on :,=> and <= (e.g. if <= is present on multiple lines under each other this operator is aligned)
* Hoovering over the formal part of a component instatiation will now show the port's type.
* Implementation of Record member auto completion (when pressing "." after record instance name)
* Functionality to show matching parenthesis.
* Hoovering over a constant will show its value.
* Outline now also shows record declaration and members.
* Changed the way comments are added to signal declarations.
Now you have 2 options:... read more

Posted by aghoras 2009-10-27

Wiki support is discontinued

Due to its multiple weaknesses, the wiki was constantly being hacked. Therefore, I have decided to revert back to the original html version of the web page.

Posted by aghoras 2009-02-18

Version 0.6.2 Release

Incorporated changes from Stijn Last. These improved the VHDL side of the house.

Here's the list of fixes/enhancements:

*The editor of Eclipse can be set to use spaces as tabs, the insertion of code templates and automatic component instantiations should be according to this setting

* Some altera generated files are encrypted. = binary file, but with .vhd extension. The internal VHDL parser gives on error on this.... read more

Posted by aghoras 2009-02-17

VEditor Wiki

The VEditor wiki is back online again. Recently, Sourceforge revamped their entire ssh shell access and that caused our wiki to get very confused.
Also,nightly backups of the wiki are implemented. The backups are currently held on my computer and will facilitate the restoration of wiki data in case of future hacks/spam attacks.

Posted by aghoras 2008-12-02

Version 0.6.1 released

You can download new veditor runtime and source package.

Posted by KOBAYASHI Tadashi 2008-05-18

Subversion Migration

All the source code is now migrated to Subversion.

Posted by aghoras 2007-12-12

New and Improved Wiki

After experimenting and being very disappointed by the wiki, I created our own MoinMoin based Wiki hosted on This wiki will also serve as the project's main webpage. You can find it at:

Posted by aghoras 2007-12-12

VEditor Wiki Operation

The VEditor Wiki is now operational! You should be able to access it from the main menu in the project page. Currently, the Wiki is a little a short on content but hopefully it will eventually serve as the central documentation for the project.

Posted by aghoras 2007-09-12

Eclipse VEditor 0.6.0 Released

Eclipse Verilog editor is a plugin for the Eclipse IDE. It provides Verilog(IEEE-1364) and VHDL language specific code viewer, contents outline, code assist etc. It helps coding and debugging in hardware development based on Verilog or VHDL.

Eclipse VEditor 0.6.0 had been released. This release includes several new features such as:
* Complete VHDL parser
* Revamped File Outline
* Revamped Module Hierarchy
* Back-ground parser
* Document section collapsing
* VHDL comment continuation
* Multiple Build Configuration
* Error/Warning/Info Regex developer helper
* Improved VHDL auto-completion and Go-to-definition
* VHDL code formatter
* Other general usage improvements and code clean-ups.

Posted by aghoras 2007-09-11

Eclipse Verilog editor 0.5.2 released

The version 0.5.2 supports preference page for Verilog code formatter and fixes some bugs.

Posted by KOBAYASHI Tadashi 2007-06-10

Eclipse Verilog editor 0.5.1 released

The version 0.5.1 adds block comment and uncomment command, and supports custom code template.

Posted by KOBAYASHI Tadashi 2007-01-14

Eclipse Verilog editor 0.5.0 released

The version 0.5.0 changed license from GPL to EPL, and supported text hover of signals.

Posted by KOBAYASHI Tadashi 2006-08-27

Eclipse Verilog editor 0.4.1 released

The version 4.1.0 has custom error parser and log viewer. It can support any Verilog/VHDL compilers.

Posted by KOBAYASHI Tadashi 2006-05-14

Eclipse Verilog editor 0.4.0 released

The version 0.4.0 has Verilog/VHDL perspective, new module wizard and simulator builder in new Verilog/VHDL project. It supports Cver and FreeHDL compilers.

Posted by KOBAYASHI Tadashi 2006-04-16

Eclipse Verilog editor 0.3.2 released

The version 0.3.2 supported Verilog 2001. It added generate/endgenerate template and instantiation with parameter.

Posted by KOBAYASHI Tadashi 2006-01-15

Eclipse Verilog editor 0.3.1 released

The version 0.3.1 fixed some bugs.

Posted by KOBAYASHI Tadashi 2005-12-04

Get latest updates about Open Source Projects, Conferences and News.

Sign up for the SourceForge newsletter:

JavaScript is required for this form.

No, thanks