Incorporated changes from Stijn Last. These improved the VHDL side of the house.
Here's the list of fixes/enhancements:
*The editor of Eclipse can be set to use spaces as tabs, the insertion of code templates and automatic component instantiations should be according to this setting
* Some altera generated files are encrypted. = binary file, but with .vhd extension. The internal VHDL parser gives on error on this.
*Altera SOPC generates a file with a more then 10000 characters on one line! The internal VHDL parser hangs
* The comment/uncomment introduces a useless space after the -- and does not work well if comment was not originally insterted by the comment action
* If you compile a file with the "compile command", the errors are parsed and added to the Problems Page. When you compile it again without saving, the same errors are added twice to this list
*Format problems with:comment lines,statements written over multiple lines, alias is : the is causes a shift to the right,signal <= '0' when flag else '1'; when is expected to be the "case-when" nested case constructions block
* No in/out in comment, because most of the time right-hand signals are changed afterwards Correct indentation
* Double clicking on VHDL instantiation takes the user to the architecture definition
* Added VHDL semantic warnings
* Make block/process collapsible
* If you hoover over a signal, the type is shown. For std_logic_vector also the range should be shown
* Automatically create a testbench for a certain component (with correct signals and component instantiation)
* Improve the new file template
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