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|
From: openocd-gerrit <ope...@us...> - 2024-03-16 14:42:53
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 1d076d6ce1908d5c154bfc6ee2ccd8a629853ef1 (commit)
from e9df8a5102106de5a13956759ae52eb72ff68113 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 1d076d6ce1908d5c154bfc6ee2ccd8a629853ef1
Author: Antonio Borneo <bor...@gm...>
Date: Sat Mar 2 14:01:07 2024 +0100
openocd: dump full command line in the debug log
When receiving an OpenOCD debug log to investigate about errors or
issues, the first question is often about providing the complete
command line to better understand the use context.
Plus, when OpenOCD is lunched by an IDE, its command line is kept
hidden inside the IDE, adding troubles to the user to recover it.
Add the full command line directly inside the debug log.
It could have been useful to also search and add in the log the
full path of the OpenOCD executable, but this is not an immediate
task due to portability among OS's. See, for example:
https://stackoverflow.com/questions/933850
This part could be handled in a future change, if really needed.
Change-Id: Ia6c5b838b9b7208bf1ecac7f95b5efc319aeabf5
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8170
Tested-by: jenkins
Reviewed-by: Paul Fertser <fer...@gm...>
diff --git a/src/helper/options.c b/src/helper/options.c
index 05cde6709..61a101469 100644
--- a/src/helper/options.c
+++ b/src/helper/options.c
@@ -341,6 +341,10 @@ int parse_cmdline_args(struct command_context *cmd_ctx, int argc, char *argv[])
exit(0);
}
+ /* dump full command line */
+ for (int i = 0; i < argc; i++)
+ LOG_DEBUG("ARGV[%d] = \"%s\"", i, argv[i]);
+
/* paths specified on the command line take precedence over these
* built-in paths
*/
-----------------------------------------------------------------------
Summary of changes:
src/helper/options.c | 4 ++++
1 file changed, 4 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2024-03-16 14:42:25
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via e9df8a5102106de5a13956759ae52eb72ff68113 (commit)
from 4c0a2cf42ea0a0b48a948be1ff825629265bbf21 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit e9df8a5102106de5a13956759ae52eb72ff68113
Author: Antonio Borneo <bor...@gm...>
Date: Wed Feb 28 13:41:34 2024 +0100
target: aarch64: add support for 32 bit MON mode
Extend the existing code to support Monitor mode in AArch32.
Change-Id: Ia43df98d1497baac48aea67b92d81344c24f0635
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8169
Tested-by: jenkins
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 36bcddc31..2e4d0b5c0 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -93,6 +93,7 @@ static int aarch64_restore_system_control_reg(struct target *target)
case ARM_MODE_HYP:
case ARM_MODE_UND:
case ARM_MODE_SYS:
+ case ARM_MODE_MON:
instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
break;
@@ -172,6 +173,7 @@ static int aarch64_mmu_modify(struct target *target, int enable)
case ARM_MODE_HYP:
case ARM_MODE_UND:
case ARM_MODE_SYS:
+ case ARM_MODE_MON:
instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
break;
@@ -1043,6 +1045,7 @@ static int aarch64_post_debug_entry(struct target *target)
case ARM_MODE_HYP:
case ARM_MODE_UND:
case ARM_MODE_SYS:
+ case ARM_MODE_MON:
instr = ARMV4_5_MRC(15, 0, 0, 1, 0, 0);
break;
-----------------------------------------------------------------------
Summary of changes:
src/target/aarch64.c | 3 +++
1 file changed, 3 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2024-03-16 14:38:51
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 4c0a2cf42ea0a0b48a948be1ff825629265bbf21 (commit)
from 31af18e9d1807d442885d0254ff5b13a66ea3a65 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 4c0a2cf42ea0a0b48a948be1ff825629265bbf21
Author: Tomas Vanek <va...@fb...>
Date: Thu Feb 15 10:05:21 2024 +0100
target/adi_v5_swd: fix DP registers banking
ADIv6 brought more complicated rules for DP reg 0 banking.
Neither the original implementation [1] nor the later
modification [2] respected that the DP reg 0 is banked
for read only, not for write. Enforcing of an useless
SELECT write before a write to ABORT register may trigger
FAULT (CTRL/STAT bits ORUNDETECT and STICKYORUN are set)
or WAIT (DP is stalled by an outstanding previous operation)
and therefore make ABORT register virtually unusable
on some adapters (bitbang, CMSIS-DAP).
There are DP ABORT specific functions swd_queue_ap_abort()
and swd_clear_sticky_errors() which worked around the problem
using the lowest level swd->write_reg(). Using a specific
write procedure for a single DP register was error prone
(there are other DP_ABORT writes using swd_queue_dp_write_inner())
and also the Tcl command 'xx.dap dpreg 0 value' suffered
from unwanted SELECT write.
Other smaller discords in DP banking probably do not
influence normal DP operation however they may complicate
debugging in corner cases.
Adhere strictly to the DP banking rules for both ADI versions.
Fixes: [1] commit 72fb88613f02 ("adiv6: add low level swd transport")
Fixes: [2] commit ee3fb5a0eacb ("target/arm_adi_v5: fix DP SELECT logic")
Signed-off-by: Tomas Vanek <va...@fb...>
Change-Id: I3328748c1c3e0661c5ecd6eb070ac519b190ace2
Reviewed-on: https://review.openocd.org/c/openocd/+/8154
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c
index 6d6f287b0..67706f35b 100644
--- a/src/target/adi_v5_swd.c
+++ b/src/target/adi_v5_swd.c
@@ -105,14 +105,13 @@ static inline int check_sync(struct adiv5_dap *dap)
static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned int reg)
{
/* Only register address 0 (ADIv6 only) and 4 are banked. */
- if ((reg & 0xf) > 4)
+ if (is_adiv6(dap) ? (reg & 0xf) > 4 : (reg & 0xf) != 4)
return ERROR_OK;
uint32_t sel = (reg >> 4) & DP_SELECT_DPBANK;
- /* DP register 0 is not mapped according to ADIv5
- * whereas ADIv6 ensures DPBANKSEL = 0 after line reset */
- if ((dap->select_valid || ((reg & 0xf) == 0 && dap->select_dpbanksel_valid))
+ /* ADIv6 ensures DPBANKSEL = 0 after line reset */
+ if ((dap->select_valid || (is_adiv6(dap) && dap->select_dpbanksel_valid))
&& (sel == (dap->select & DP_SELECT_DPBANK)))
return ERROR_OK;
@@ -146,7 +145,7 @@ static int swd_queue_dp_read_inner(struct adiv5_dap *dap, unsigned int reg,
static int swd_queue_dp_write_inner(struct adiv5_dap *dap, unsigned int reg,
uint32_t data)
{
- int retval;
+ int retval = ERROR_OK;
const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
assert(swd);
@@ -167,7 +166,11 @@ static int swd_queue_dp_write_inner(struct adiv5_dap *dap, unsigned int reg,
if (reg == DP_SELECT1)
dap->select = ((uint64_t)data << 32) | (dap->select & 0xffffffffull);
- retval = swd_queue_dp_bankselect(dap, reg);
+ /* DP_ABORT write is not banked.
+ * Prevent writing DP_SELECT before as it would fail on locked up DP */
+ if (reg != DP_ABORT)
+ retval = swd_queue_dp_bankselect(dap, reg);
+
if (retval == ERROR_OK) {
swd->write_reg(swd_cmd(false, false, reg), data, 0);
-----------------------------------------------------------------------
Summary of changes:
src/target/adi_v5_swd.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2024-03-16 14:37:56
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 31af18e9d1807d442885d0254ff5b13a66ea3a65 (commit)
from f7f4fa84f1466036ebec80b3143fdd32ce181344 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 31af18e9d1807d442885d0254ff5b13a66ea3a65
Author: Tomas Vanek <va...@fb...>
Date: Sat Feb 17 13:14:01 2024 +0100
jtag/drivers/bitbang: limit SWD WAIT retries by timeout
The bitbang driver kept retrying a SWD command as long as
the debugged device had been responding by SWD WAIT.
If the DP stalled in WAIT permanently, OpenOCD hanged.
Check 0.5 sec timeout in WAIT retry loop.
While on it insert a short alive_sleep() if the command
is retried 20 or more times.
Signed-off-by: Tomas Vanek <va...@fb...>
Change-Id: I744e56e21a5a2dc2c4494cc0d7bbcb4be14ddb23
Reviewed-on: https://review.openocd.org/c/openocd/+/8153
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/jtag/drivers/bitbang.c b/src/jtag/drivers/bitbang.c
index f0236848b..3d839e65d 100644
--- a/src/jtag/drivers/bitbang.c
+++ b/src/jtag/drivers/bitbang.c
@@ -20,6 +20,11 @@
#include <jtag/interface.h>
#include <jtag/commands.h>
+#include <helper/time_support.h>
+
+/* Timeout for retrying on SWD WAIT in msec */
+#define SWD_WAIT_TIMEOUT 500
+
/**
* Function bitbang_stableclocks
* issues a number of clock cycles while staying in a stable state.
@@ -474,6 +479,7 @@ static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay
return;
}
+ int64_t timeout = timeval_ms() + SWD_WAIT_TIMEOUT;
for (unsigned int retry = 0;; retry++) {
uint8_t trn_ack_data_parity_trn[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)];
@@ -496,8 +502,11 @@ static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay
(cmd & SWD_CMD_A32) >> 1,
data);
- if (ack == SWD_ACK_WAIT) {
+ if (ack == SWD_ACK_WAIT && timeval_ms() <= timeout) {
swd_clear_sticky_errors();
+ if (retry > 20)
+ alive_sleep(1);
+
continue;
}
if (retry > 1)
@@ -530,6 +539,8 @@ static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay
return;
}
+ int64_t timeout = timeval_ms() + SWD_WAIT_TIMEOUT;
+
/* Devices do not reply to DP_TARGETSEL write cmd, ignore received ack */
bool check_ack = swd_cmd_returns_ack(cmd);
@@ -569,8 +580,11 @@ static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay
(cmd & SWD_CMD_A32) >> 1,
buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32));
- if (check_ack && ack == SWD_ACK_WAIT) {
+ if (check_ack && ack == SWD_ACK_WAIT && timeval_ms() <= timeout) {
swd_clear_sticky_errors();
+ if (retry > 20)
+ alive_sleep(1);
+
continue;
}
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/bitbang.c | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2024-03-16 14:37:39
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via f7f4fa84f1466036ebec80b3143fdd32ce181344 (commit)
from b63e065f23807cdf6da44d03def4c416686695f5 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit f7f4fa84f1466036ebec80b3143fdd32ce181344
Author: Tomas Vanek <va...@fb...>
Date: Sat Feb 17 12:48:46 2024 +0100
jtag/drivers/bitbang: use LOG_CUSTOM_LEVEL() macro for SWD
Log SWD commands with not OK response but WAIT retries at debug level.
For commands responded OK and WAIT retries use debug io level
not to flood the log.
Signed-off-by: Tomas Vanek <va...@fb...>
Change-Id: Idf658e82ed970061c155945df55d06908ed25e09
Reviewed-on: https://review.openocd.org/c/openocd/+/8152
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/bitbang.c b/src/jtag/drivers/bitbang.c
index 8df51764b..f0236848b 100644
--- a/src/jtag/drivers/bitbang.c
+++ b/src/jtag/drivers/bitbang.c
@@ -474,7 +474,7 @@ static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay
return;
}
- for (;;) {
+ for (unsigned int retry = 0;; retry++) {
uint8_t trn_ack_data_parity_trn[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)];
cmd |= SWD_CMD_START | SWD_CMD_PARK;
@@ -488,16 +488,22 @@ static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay
uint32_t data = buf_get_u32(trn_ack_data_parity_trn, 1 + 3, 32);
int parity = buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 32, 1);
- LOG_DEBUG_IO("%s %s read reg %X = %08" PRIx32,
- ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
- cmd & SWD_CMD_APNDP ? "AP" : "DP",
- (cmd & SWD_CMD_A32) >> 1,
- data);
+ LOG_CUSTOM_LEVEL((ack != SWD_ACK_OK && (retry == 0 || ack != SWD_ACK_WAIT))
+ ? LOG_LVL_DEBUG : LOG_LVL_DEBUG_IO,
+ "%s %s read reg %X = %08" PRIx32,
+ ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
+ cmd & SWD_CMD_APNDP ? "AP" : "DP",
+ (cmd & SWD_CMD_A32) >> 1,
+ data);
if (ack == SWD_ACK_WAIT) {
swd_clear_sticky_errors();
continue;
- } else if (ack != SWD_ACK_OK) {
+ }
+ if (retry > 1)
+ LOG_DEBUG("SWD WAIT: retried %u times", retry);
+
+ if (ack != SWD_ACK_OK) {
queued_retval = swd_ack_to_error_code(ack);
return;
}
@@ -529,7 +535,7 @@ static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay
/* init the array to silence scan-build */
uint8_t trn_ack_data_parity_trn[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)] = {0};
- for (;;) {
+ for (unsigned int retry = 0;; retry++) {
buf_set_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32, value);
buf_set_u32(trn_ack_data_parity_trn, 1 + 3 + 1 + 32, 1, parity_u32(value));
@@ -554,22 +560,26 @@ static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay
bitbang_swd_exchange(false, trn_ack_data_parity_trn, 1 + 3 + 1, 32 + 1);
int ack = buf_get_u32(trn_ack_data_parity_trn, 1, 3);
+ LOG_CUSTOM_LEVEL((check_ack && ack != SWD_ACK_OK && (retry == 0 || ack != SWD_ACK_WAIT))
+ ? LOG_LVL_DEBUG : LOG_LVL_DEBUG_IO,
+ "%s%s %s write reg %X = %08" PRIx32,
+ check_ack ? "" : "ack ignored ",
+ ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
+ cmd & SWD_CMD_APNDP ? "AP" : "DP",
+ (cmd & SWD_CMD_A32) >> 1,
+ buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32));
+
+ if (check_ack && ack == SWD_ACK_WAIT) {
+ swd_clear_sticky_errors();
+ continue;
+ }
- LOG_DEBUG_IO("%s%s %s write reg %X = %08" PRIx32,
- check_ack ? "" : "ack ignored ",
- ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
- cmd & SWD_CMD_APNDP ? "AP" : "DP",
- (cmd & SWD_CMD_A32) >> 1,
- buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 1, 32));
-
- if (check_ack) {
- if (ack == SWD_ACK_WAIT) {
- swd_clear_sticky_errors();
- continue;
- } else if (ack != SWD_ACK_OK) {
- queued_retval = swd_ack_to_error_code(ack);
- return;
- }
+ if (retry > 1)
+ LOG_DEBUG("SWD WAIT: retried %u times", retry);
+
+ if (check_ack && ack != SWD_ACK_OK) {
+ queued_retval = swd_ack_to_error_code(ack);
+ return;
}
if (cmd & SWD_CMD_APNDP)
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/bitbang.c | 56 +++++++++++++++++++++++++++-------------------
1 file changed, 33 insertions(+), 23 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2024-03-16 14:37:24
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit b63e065f23807cdf6da44d03def4c416686695f5
Author: Tomas Vanek <va...@fb...>
Date: Fri Feb 16 17:40:22 2024 +0100
helper/log: add LOG_CUSTOM_LEVEL() macro
Allow logging at a changeable level.
Add an example of usage in ftdi driver.
Log SWD commands with not OK response at debug level (3).
For commands which responded OK use debug io level (4)
not to flood the log.
Signed-off-by: Tomas Vanek <va...@fb...>
Change-Id: I67a472b293f7ed9ee84cadb7c081803e9eeb1ad0
Reviewed-on: https://review.openocd.org/c/openocd/+/8151
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/helper/log.h b/src/helper/log.h
index ee71bf03f..818716a9d 100644
--- a/src/helper/log.h
+++ b/src/helper/log.h
@@ -114,6 +114,15 @@ extern int debug_level;
expr); \
} while (0)
+#define LOG_CUSTOM_LEVEL(level, expr ...) \
+ do { \
+ enum log_levels _level = level; \
+ if (debug_level >= _level) \
+ log_printf_lf(_level, \
+ __FILE__, __LINE__, __func__, \
+ expr); \
+ } while (0)
+
#define LOG_INFO(expr ...) \
log_printf_lf(LOG_LVL_INFO, __FILE__, __LINE__, __func__, expr)
diff --git a/src/jtag/drivers/ftdi.c b/src/jtag/drivers/ftdi.c
index 2bde93169..58f83af59 100644
--- a/src/jtag/drivers/ftdi.c
+++ b/src/jtag/drivers/ftdi.c
@@ -1088,7 +1088,8 @@ static int ftdi_swd_run_queue(void)
/* Devices do not reply to DP_TARGETSEL write cmd, ignore received ack */
bool check_ack = swd_cmd_returns_ack(swd_cmd_queue[i].cmd);
- LOG_DEBUG_IO("%s%s %s %s reg %X = %08"PRIx32,
+ LOG_CUSTOM_LEVEL((check_ack && ack != SWD_ACK_OK) ? LOG_LVL_DEBUG : LOG_LVL_DEBUG_IO,
+ "%s%s %s %s reg %X = %08" PRIx32,
check_ack ? "" : "ack ignored ",
ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
swd_cmd_queue[i].cmd & SWD_CMD_APNDP ? "AP" : "DP",
-----------------------------------------------------------------------
Summary of changes:
src/helper/log.h | 9 +++++++++
src/jtag/drivers/ftdi.c | 3 ++-
2 files changed, 11 insertions(+), 1 deletion(-)
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From: openocd-gerrit <ope...@us...> - 2024-03-16 14:35:55
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 263dbc1472efa5f24e636e95f8c71a6f83b4097a
Author: Tomas Vanek <va...@fb...>
Date: Sun Feb 11 17:22:38 2024 +0100
target/arm_adi_v5: introduce adiv5_jim_configure_ext()
Allow direct pointer to struct adiv5_private_config
for targets with adiv5_private_config inside of a bigger
private config container. Use it instead of the private_config
pointer toggling hack in aarch64.c
Allow optional use of -dap parameter and use it instead
of the static variable hack in xtensa_chip.c
Signed-off-by: Tomas Vanek <va...@fb...>
Change-Id: I7260c79332940adfa49d57b45cae39325cdaf432
Reviewed-on: https://review.openocd.org/c/openocd/+/8138
Tested-by: jenkins
Reviewed-by: Ian Thompson <ia...@ca...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 1c056a015..36bcddc31 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -2891,13 +2891,8 @@ static int aarch64_jim_configure(struct target *target, struct jim_getopt_info *
* options, JIM_OK if it correctly parsed the topmost option
* and JIM_ERR if an error occurred during parameter evaluation.
* For JIM_CONTINUE, we check our own params.
- *
- * adiv5_jim_configure() assumes 'private_config' to point to
- * 'struct adiv5_private_config'. Override 'private_config'!
*/
- target->private_config = &pc->adiv5_config;
- e = adiv5_jim_configure(target, goi);
- target->private_config = pc;
+ e = adiv5_jim_configure_ext(target, goi, &pc->adiv5_config, ADI_CONFIGURE_DAP_COMPULSORY);
if (e != JIM_CONTINUE)
return e;
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index ff12658c8..9129acecf 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -2424,23 +2424,26 @@ err_no_param:
return JIM_ERR;
}
-int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi)
+int adiv5_jim_configure_ext(struct target *target, struct jim_getopt_info *goi,
+ struct adiv5_private_config *pc, enum adiv5_configure_dap_optional optional)
{
- struct adiv5_private_config *pc;
int e;
- pc = (struct adiv5_private_config *)target->private_config;
if (!pc) {
- pc = calloc(1, sizeof(struct adiv5_private_config));
+ pc = (struct adiv5_private_config *)target->private_config;
if (!pc) {
- LOG_ERROR("Out of memory");
- return JIM_ERR;
+ pc = calloc(1, sizeof(struct adiv5_private_config));
+ if (!pc) {
+ LOG_ERROR("Out of memory");
+ return JIM_ERR;
+ }
+ pc->ap_num = DP_APSEL_INVALID;
+ target->private_config = pc;
}
- pc->ap_num = DP_APSEL_INVALID;
- target->private_config = pc;
}
- target->has_dap = true;
+ if (optional == ADI_CONFIGURE_DAP_COMPULSORY)
+ target->has_dap = true;
e = adiv5_jim_spot_configure(goi, &pc->dap, &pc->ap_num, NULL);
if (e != JIM_OK)
@@ -2455,11 +2458,17 @@ int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi)
}
target->tap = pc->dap->tap;
target->dap_configured = true;
+ target->has_dap = true;
}
return JIM_OK;
}
+int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi)
+{
+ return adiv5_jim_configure_ext(target, goi, NULL, ADI_CONFIGURE_DAP_COMPULSORY);
+}
+
int adiv5_verify_config(struct adiv5_private_config *pc)
{
if (!pc)
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 60c161f3c..92c3dbc3a 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -788,6 +788,15 @@ struct adiv5_private_config {
};
extern int adiv5_verify_config(struct adiv5_private_config *pc);
+
+enum adiv5_configure_dap_optional {
+ ADI_CONFIGURE_DAP_COMPULSORY = false,
+ ADI_CONFIGURE_DAP_OPTIONAL = true
+};
+
+extern int adiv5_jim_configure_ext(struct target *target, struct jim_getopt_info *goi,
+ struct adiv5_private_config *pc,
+ enum adiv5_configure_dap_optional optional);
extern int adiv5_jim_configure(struct target *target, struct jim_getopt_info *goi);
struct adiv5_mem_ap_spot {
diff --git a/src/target/xtensa/xtensa_chip.c b/src/target/xtensa/xtensa_chip.c
index ac758ed83..ac4a49ccf 100644
--- a/src/target/xtensa/xtensa_chip.c
+++ b/src/target/xtensa/xtensa_chip.c
@@ -144,17 +144,7 @@ static int xtensa_chip_examine(struct target *target)
static int xtensa_chip_jim_configure(struct target *target, struct jim_getopt_info *goi)
{
- static bool dap_configured;
- int ret = adiv5_jim_configure(target, goi);
- if (ret == JIM_OK) {
- LOG_DEBUG("xtensa '-dap' target option found");
- dap_configured = true;
- }
- if (!dap_configured) {
- LOG_DEBUG("xtensa '-dap' target option not yet found, assuming JTAG...");
- target->has_dap = false;
- }
- return ret;
+ return adiv5_jim_configure_ext(target, goi, NULL, ADI_CONFIGURE_DAP_OPTIONAL);
}
/** Methods for generic example of Xtensa-based chip-level targets. */
-----------------------------------------------------------------------
Summary of changes:
src/target/aarch64.c | 7 +------
src/target/arm_adi_v5.c | 27 ++++++++++++++++++---------
src/target/arm_adi_v5.h | 9 +++++++++
src/target/xtensa/xtensa_chip.c | 12 +-----------
4 files changed, 29 insertions(+), 26 deletions(-)
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Main OpenOCD repository
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|
From: openocd-gerrit <ope...@us...> - 2024-03-16 14:35:22
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 348b79aafe6826734921167397190c9032a6039e (commit)
from 12ff36bd19e4f25dd7505c46a77d9f2c47dc350a (commit)
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- Log -----------------------------------------------------------------
commit 348b79aafe6826734921167397190c9032a6039e
Author: Tomas Vanek <va...@fb...>
Date: Fri Feb 9 07:35:42 2024 +0100
drivers/cmsis_dap, kitprog: use helper to derive err code from ack
Unify the error codes returned by adapter drivers in the case
of the received SWD ACK field differs from OK.
Signed-off-by: Tomas Vanek <va...@fb...>
Change-Id: I29e478390b4b30408054a090ac6a7fac3415ae71
Reviewed-on: https://review.openocd.org/c/openocd/+/8137
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/jtag/drivers/cmsis_dap.c b/src/jtag/drivers/cmsis_dap.c
index 341d35cdf..d7367d813 100644
--- a/src/jtag/drivers/cmsis_dap.c
+++ b/src/jtag/drivers/cmsis_dap.c
@@ -944,7 +944,7 @@ static void cmsis_dap_swd_read_process(struct cmsis_dap *dap, enum cmsis_dap_blo
if (ack != SWD_ACK_OK) {
LOG_DEBUG("SWD ack not OK @ %d %s", transfer_count,
ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK");
- queued_retval = ack == SWD_ACK_WAIT ? ERROR_WAIT : ERROR_FAIL;
+ queued_retval = swd_ack_to_error_code(ack);
/* TODO: use results of transfers completed before the error occurred? */
goto skip;
}
diff --git a/src/jtag/drivers/kitprog.c b/src/jtag/drivers/kitprog.c
index c0d2adc10..98b0d1668 100644
--- a/src/jtag/drivers/kitprog.c
+++ b/src/jtag/drivers/kitprog.c
@@ -782,7 +782,7 @@ static int kitprog_swd_run_queue(void)
if (ack != SWD_ACK_OK || (buffer[read_index] & 0x08)) {
LOG_DEBUG("SWD ack not OK: %d %s", i,
ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK");
- queued_retval = ack == SWD_ACK_WAIT ? ERROR_WAIT : ERROR_FAIL;
+ queued_retval = swd_ack_to_error_code(ack);
break;
}
read_index++;
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/cmsis_dap.c | 2 +-
src/jtag/drivers/kitprog.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
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Main OpenOCD repository
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From: openocd-gerrit <ope...@us...> - 2024-03-10 17:55:20
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 12ff36bd19e4f25dd7505c46a77d9f2c47dc350a (commit)
from 561ea48d83ae4b83ff823888a80cbcc282b61333 (commit)
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- Log -----------------------------------------------------------------
commit 12ff36bd19e4f25dd7505c46a77d9f2c47dc350a
Author: Tomas Vanek <va...@fb...>
Date: Sun Mar 10 12:12:55 2024 +0100
flash/nor/nrf5: drop useless for cycle condition
Commit [1] added a break on error to the nrf5_erase() sector loop
and the checking of the res value became useless in the for loop condition.
Removing nrf5_get_probed_chip_if_halted() later in [2]
dropped res initialization and clang static analyser complains
"The left operand of '==' is a garbage value"
Drop the useless test!
Fixes: [1] commit 491636c8b832 ("flash/nor/nrf5: check protection before flash erase/write on nRF51")
Fixes: [2] commit 2db325f5395f ("flash/nor/nrf5: drop nrf5_get_probed_chip_if_halted()")
Signed-off-by: Tomas Vanek <va...@fb...>
Change-Id: Ife6071c509719f8d7dc312fe9a780bdcf2575f69
Reviewed-on: https://review.openocd.org/c/openocd/+/8174
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index 3f451a76c..bf8c9da5f 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -1071,7 +1071,7 @@ static int nrf5_erase(struct flash_bank *bank, unsigned int first,
}
/* For each sector to be erased */
- for (unsigned int s = first; s <= last && res == ERROR_OK; s++) {
+ for (unsigned int s = first; s <= last; s++) {
if (chip->features & NRF5_FEATURE_SERIES_51
&& bank->sectors[s].is_protected == 1) {
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/nrf5.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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From: openocd-gerrit <ope...@us...> - 2024-03-09 11:09:03
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 561ea48d83ae4b83ff823888a80cbcc282b61333 (commit)
from fcda9f1561bfc413e3723e5b4552bc7e91eb4a8d (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 561ea48d83ae4b83ff823888a80cbcc282b61333
Author: Walter Ji <wal...@os...>
Date: Fri Nov 17 11:27:56 2023 +0800
target/mips32: add dsp access support
Add access to dsp registers and a command for dsp related operations.
Checkpatch-ignore: MACRO_ARG_REUSE
Change-Id: I30aec0b9e4984896965edb1663f74216ad41101e
Signed-off-by: Walter Ji <wal...@os...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7867
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 4297258d9..bf4e0ad65 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -11070,6 +11070,11 @@ EJTAG Register Specification could be found in MIPS Document MD00047F, for
core specific EJTAG Register definition, please check Core Specific SUM manual.
@end deffn
+@deffn {Command} {mips32 dsp} [[register_name] [value]]
+Displays all DSP registers' contents or get/set value by register name. Will display
+an error if current CPU does not support DSP.
+@end deffn
+
@section RISC-V Architecture
@uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 5b94e6c89..ec2bfb7d0 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -161,6 +161,67 @@ static const struct {
#define MIPS32_NUM_REGS ARRAY_SIZE(mips32_regs)
+
+#define zero 0
+
+#define AT 1
+
+#define v0 2
+#define v1 3
+
+#define a0 4
+#define a1 5
+#define a2 6
+#define a3 7
+#define t0 8
+#define t1 9
+#define t2 10
+#define t3 11
+#define t4 12
+#define t5 13
+#define t6 14
+#define t7 15
+#define ta0 12 /* alias for $t4 */
+#define ta1 13 /* alias for $t5 */
+#define ta2 14 /* alias for $t6 */
+#define ta3 15 /* alias for $t7 */
+
+#define s0 16
+#define s1 17
+#define s2 18
+#define s3 19
+#define s4 20
+#define s5 21
+#define s6 22
+#define s7 23
+#define s8 30 /* == fp */
+
+#define t8 24
+#define t9 25
+#define k0 26
+#define k1 27
+
+#define gp 28
+
+#define sp 29
+#define fp 30
+#define ra 31
+
+
+static const struct {
+ const char *name;
+} mips32_dsp_regs[MIPS32NUMDSPREGS] = {
+ { "hi0"},
+ { "hi1"},
+ { "hi2"},
+ { "hi3"},
+ { "lo0"},
+ { "lo1"},
+ { "lo2"},
+ { "lo3"},
+ { "control"},
+};
+
static int mips32_get_core_reg(struct reg *reg)
{
int retval;
@@ -1544,6 +1605,204 @@ COMMAND_HANDLER(mips32_handle_cp0_command)
return retval;
}
+/**
+ * mips32_dsp_enable - Enable access to DSP registers
+ * @param[in] ctx: Context information for the pracc queue
+ * @param[in] isa: Instruction Set Architecture identifier
+ *
+ * @brief Enables access to DSP registers by modifying the status register.
+ *
+ * This function adds instructions to the context queue for enabling
+ * access to DSP registers by modifying the status register.
+ */
+static void mips32_dsp_enable(struct pracc_queue_info *ctx, int isa)
+{
+ /* Save Status Register */
+ /* move status to $9 (t1) 2*/
+ pracc_add(ctx, 0, MIPS32_MFC0(isa, 9, 12, 0));
+
+ /* Read it again in order to modify it */
+ /* move status to $0 (t0) 3*/
+ pracc_add(ctx, 0, MIPS32_MFC0(isa, 8, 12, 0));
+
+ /* Enable access to DSP registers by setting MX bit in status register */
+ /* $15 = MIPS32_PRACC_STACK 4/5/6*/
+ pracc_add(ctx, 0, MIPS32_LUI(isa, 15, UPPER16(MIPS32_DSP_ENABLE)));
+ pracc_add(ctx, 0, MIPS32_ORI(isa, 15, 15, LOWER16(MIPS32_DSP_ENABLE)));
+ pracc_add(ctx, 0, MIPS32_ISA_OR(8, 8, 15));
+ /* Enable DSP - update status registers 7*/
+ pracc_add(ctx, 0, MIPS32_MTC0(isa, 8, 12, 0));
+}
+
+/**
+ * mips32_dsp_restore - Restore DSP status registers to the previous setting
+ * @param[in] ctx: Context information pracc queue
+ * @param[in] isa: isa identifier
+ *
+ * @brief Restores the DSP status registers to their previous setting.
+ *
+ * This function adds instructions to the context queue for restoring the DSP
+ * status registers to their values before the operation.
+ */
+static void mips32_dsp_restore(struct pracc_queue_info *ctx, int isa)
+{
+ pracc_add(ctx, 0, MIPS32_MTC0(isa, 9, 12, 0)); /* Restore status registers to previous setting */
+ pracc_add(ctx, 0, MIPS32_NOP); /* nop */
+}
+
+/**
+ * mips32_pracc_read_dsp_reg - Read a value from a MIPS32 DSP register
+ * @param[in] ejtag_info: EJTAG information structure
+ * @param[out] val: Pointer to store the read value
+ * @param[in] reg: Index of the DSP register to read
+ *
+ * @brief Reads the value from the specified MIPS32 DSP register using EJTAG access.
+ *
+ * This function initiates a sequence of instructions to read the value from the
+ * specified DSP register. It will enable dsp module if its not enabled
+ * and restoring the status registers after the read operation.
+ *
+ * @return ERROR_OK on success; error code on failure.
+ */
+static int mips32_pracc_read_dsp_reg(struct mips_ejtag *ejtag_info, uint32_t *val, uint32_t reg)
+{
+ int isa = 0;
+
+ struct pracc_queue_info ctx = {
+ .max_code = 48,
+ .ejtag_info = ejtag_info
+ };
+
+ uint32_t dsp_read_code[] = {
+ MIPS32_MFHI(isa, t0), /* mfhi t0 ($ac0) - OPCODE - 0x00004010 */
+ MIPS32_DSP_MFHI(t0, 1), /* mfhi t0,$ac1 - OPCODE - 0x00204010 */
+ MIPS32_DSP_MFHI(t0, 2), /* mfhi t0,$ac2 - OPCODE - 0x00404010 */
+ MIPS32_DSP_MFHI(t0, 3), /* mfhi t0,$ac3 - OPCODE - 0x00604010*/
+ MIPS32_MFLO(isa, t0), /* mflo t0 ($ac0) - OPCODE - 0x00004012 */
+ MIPS32_DSP_MFLO(t0, 1), /* mflo t0,$ac1 - OPCODE - 0x00204012 */
+ MIPS32_DSP_MFLO(t0, 2), /* mflo t0,$ac2 - OPCODE - 0x00404012 */
+ MIPS32_DSP_MFLO(t0, 3), /* mflo t0,$ac3 - OPCODE - 0x00604012 */
+ MIPS32_DSP_RDDSP(t0, 0x3F), /* rddsp t0, 0x3f (DSPCtl) - OPCODE - 0x7c3f44b8 */
+ };
+
+ /* Check status register to determine if dsp register access is enabled */
+ /* Get status register so it can be restored later */
+
+ ctx.pracc_list = NULL;
+
+ /* Init context queue */
+ pracc_queue_init(&ctx);
+
+ if (ctx.retval != ERROR_OK)
+ goto exit;
+
+ /* Enables DSP whether its already enabled or not */
+ mips32_dsp_enable(&ctx, isa);
+
+ /* move AC or Control to $8 (t0) 8*/
+ pracc_add(&ctx, 0, dsp_read_code[reg]);
+ /* Restore status registers to previous setting */
+ mips32_dsp_restore(&ctx, isa);
+
+ /* $15 = MIPS32_PRACC_BASE_ADDR 1*/
+ pracc_add(&ctx, 0, MIPS32_LUI(isa, 15, PRACC_UPPER_BASE_ADDR));
+ /* store $8 to pracc_out 10*/
+ pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT, MIPS32_SW(isa, 8, PRACC_OUT_OFFSET, 15));
+ /* move COP0 DeSave to $15 11*/
+ pracc_add(&ctx, 0, MIPS32_MFC0(isa, 15, 31, 0));
+ /* restore upper 16 of $8 12*/
+ pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(ejtag_info->reg8)));
+ /* restore lower 16 of $8 13*/
+ pracc_add(&ctx, 0, MIPS32_ORI(isa, 8, 8, LOWER16(ejtag_info->reg8)));
+ /* restore upper 16 of $9 14*/
+ pracc_add(&ctx, 0, MIPS32_LUI(isa, 9, UPPER16(ejtag_info->reg9)));
+ pracc_add(&ctx, 0, MIPS32_SYNC(isa));
+ /* jump to start 18*/
+ pracc_add(&ctx, 0, MIPS32_B(isa, NEG16(ctx.code_count + 1)));
+ /* restore lower 16 of $9 15*/
+ pracc_add(&ctx, 0, MIPS32_ORI(isa, 9, 9, LOWER16(ejtag_info->reg9)));
+
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, val, 1);
+exit:
+ pracc_queue_free(&ctx);
+ return ctx.retval;
+}
+
+/**
+ * mips32_pracc_write_dsp_reg - Write a value to a MIPS32 DSP register
+ * @param[in] ejtag_info: EJTAG information structure
+ * @param[in] val: Value to be written to the register
+ * @param[in] reg: Index of the DSP register to write
+ *
+ * @brief Writes the specified value to the specified MIPS32 DSP register.
+ *
+ * This function initiates a sequence of instructions to write the given value to the
+ * specified DSP register.
+ *
+ * @return ERROR_OK on success; error code on failure.
+ */
+static int mips32_pracc_write_dsp_reg(struct mips_ejtag *ejtag_info, uint32_t val, uint32_t reg)
+{
+ int isa = 0;
+
+ struct pracc_queue_info ctx = {
+ .max_code = 48,
+ .ejtag_info = ejtag_info
+ };
+
+ uint32_t dsp_write_code[] = {
+ MIPS32_MTHI(isa, t0), /* mthi t0 ($ac0) - OPCODE - 0x01000011 */
+ MIPS32_DSP_MTHI(t0, 1), /* mthi t0, $ac1 - OPCODE - 0x01000811 */
+ MIPS32_DSP_MTHI(t0, 2), /* mthi t0, $ac2 - OPCODE - 0x01001011 */
+ MIPS32_DSP_MTHI(t0, 3), /* mthi t0, $ac3 - OPCODE - 0x01001811 */
+ MIPS32_MTLO(isa, t0), /* mtlo t0 ($ac0) - OPCODE - 0x01000013 */
+ MIPS32_DSP_MTLO(t0, 1), /* mtlo t0, $ac1 - OPCODE - 0x01000813 */
+ MIPS32_DSP_MTLO(t0, 2), /* mtlo t0, $ac2 - OPCODE - 0x01001013 */
+ MIPS32_DSP_MTLO(t0, 3), /* mtlo t0, $ac3 - OPCODE - 0x01001813 */
+ MIPS32_DSP_WRDSP(t0, 0x1F), /* wrdsp t0, 0x1f (DSPCtl) - OPCODE - 0x7d00fcf8*/
+ };
+
+ /* Init context queue */
+ pracc_queue_init(&ctx);
+ if (ctx.retval != ERROR_OK)
+ goto exit;
+
+ /* Enables DSP whether its already enabled or not */
+ mips32_dsp_enable(&ctx, isa);
+
+ /* Load val to $8 (t0) */
+ pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(val)));
+ pracc_add(&ctx, 0, MIPS32_ORI(isa, 8, 8, LOWER16(val)));
+
+ /* move AC or Control to $8 (t0) */
+ pracc_add(&ctx, 0, dsp_write_code[reg]);
+
+ /* nop, delay in order to ensure write */
+ pracc_add(&ctx, 0, MIPS32_NOP);
+ /* Restore status registers to previous setting */
+ mips32_dsp_restore(&ctx, isa);
+
+ /* move COP0 DeSave to $15 */
+ pracc_add(&ctx, 0, MIPS32_MFC0(isa, 15, 31, 0));
+
+ /* restore $8 */
+ pracc_add(&ctx, 0, MIPS32_LUI(isa, 8, UPPER16(ejtag_info->reg8)));
+ pracc_add(&ctx, 0, MIPS32_ORI(isa, 8, 8, LOWER16(ejtag_info->reg8)));
+
+ /* restore upper 16 of $9 */
+ pracc_add(&ctx, 0, MIPS32_LUI(isa, 9, UPPER16(ejtag_info->reg9)));
+
+ /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_B(isa, NEG16(ctx.code_count + 1)));
+ /* restore lower 16 of $9 */
+ pracc_add(&ctx, 0, MIPS32_ORI(isa, 9, 9, LOWER16(ejtag_info->reg9)));
+
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, 1);
+exit:
+ pracc_queue_free(&ctx);
+ return ctx.retval;
+}
+
/**
* mips32_handle_cpuinfo_command - Handles the 'cpuinfo' command.
* @param[in] cmd: Command invocation context.
@@ -1746,6 +2005,167 @@ COMMAND_HANDLER(mips32_handle_cpuinfo_command)
return ERROR_OK;
}
+/**
+ * mips32_dsp_find_register_by_name - Find DSP register index by name
+ * @param[in] reg_name: Name of the DSP register to find
+ *
+ * @brief Searches for a DSP register by name and returns its index.
+ * If no match is found, it returns MIPS32NUMDSPREGS.
+ *
+ * @return Index of the found register or MIPS32NUMDSPREGS if not found.
+ */
+static int mips32_dsp_find_register_by_name(const char *reg_name)
+{
+ if (reg_name)
+ for (int i = 0; i < MIPS32NUMDSPREGS; i++) {
+ if (strcmp(mips32_dsp_regs[i].name, reg_name) == 0)
+ return i;
+ }
+ return MIPS32NUMDSPREGS;
+}
+
+/**
+ * mips32_dsp_get_all_regs - Get values of all MIPS32 DSP registers
+ * @param[in] cmd: Command invocation context
+ * @param[in] ejtag_info: EJTAG information structure
+ *
+ * @brief This function iterates through all DSP registers, reads their values,
+ * and prints each register name along with its corresponding value.
+ *
+ * @return ERROR_OK on success; error code on failure.
+ */
+static int mips32_dsp_get_all_regs(struct command_invocation *cmd, struct mips_ejtag *ejtag_info)
+{
+ uint32_t value;
+ for (int i = 0; i < MIPS32NUMDSPREGS; i++) {
+ int retval = mips32_pracc_read_dsp_reg(ejtag_info, &value, i);
+ if (retval != ERROR_OK) {
+ command_print(CMD, "couldn't access reg %s", mips32_dsp_regs[i].name);
+ return retval;
+ }
+ command_print(CMD, "%*s: 0x%8.8x", 7, mips32_dsp_regs[i].name, value);
+ }
+ return ERROR_OK;
+}
+
+/**
+ * mips32_dsp_get_register - Get the value of a MIPS32 DSP register
+ * @param[in] cmd: Command invocation context
+ * @param[in] ejtag_info: EJTAG information structure
+ *
+ * @brief Retrieves the value of a specified MIPS32 DSP register.
+ * If the register is found, it reads the register value and prints the result.
+ * If the register is not found, it prints an error message.
+ *
+ * @return ERROR_OK on success; error code on failure.
+ */
+static int mips32_dsp_get_register(struct command_invocation *cmd, struct mips_ejtag *ejtag_info)
+{
+ uint32_t value;
+ int index = mips32_dsp_find_register_by_name(CMD_ARGV[0]);
+ if (index == MIPS32NUMDSPREGS) {
+ command_print(CMD, "ERROR: register '%s' not found", CMD_ARGV[0]);
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ int retval = mips32_pracc_read_dsp_reg(ejtag_info, &value, index);
+ if (retval != ERROR_OK)
+ command_print(CMD, "ERROR: Could not access dsp register %s", CMD_ARGV[0]);
+ else
+ command_print(CMD, "0x%8.8x", value);
+
+ return retval;
+}
+
+/**
+ * mips32_dsp_set_register - Set the value of a MIPS32 DSP register
+ * @param[in] cmd: Command invocation context
+ * @param[in] ejtag_info: EJTAG information structure
+ *
+ * @brief Sets the value of a specified MIPS32 DSP register.
+ * If the register is found, it writes provided value to the register.
+ * If the register is not found or there is an error in writing the value,
+ * it prints an error message.
+ *
+ * @return ERROR_OK on success; error code on failure.
+ */
+static int mips32_dsp_set_register(struct command_invocation *cmd, struct mips_ejtag *ejtag_info)
+{
+ uint32_t value;
+ int index = mips32_dsp_find_register_by_name(CMD_ARGV[0]);
+ if (index == MIPS32NUMDSPREGS) {
+ command_print(CMD, "ERROR: register '%s' not found", CMD_ARGV[0]);
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], value);
+
+ int retval = mips32_pracc_write_dsp_reg(ejtag_info, value, index);
+ if (retval != ERROR_OK)
+ command_print(CMD, "Error: could not write to dsp register %s", CMD_ARGV[0]);
+
+ return retval;
+}
+
+/**
+ * mips32_handle_dsp_command - Handles mips dsp related command
+ * @param[in] cmd: Command invocation context
+ *
+ * @brief Reads or sets the content of each dsp register.
+ *
+ * @return ERROR_OK on success; error code on failure.
+*/
+COMMAND_HANDLER(mips32_handle_dsp_command)
+{
+ int retval, tmp;
+ struct target *target = get_current_target(CMD_CTX);
+ struct mips32_common *mips32 = target_to_mips32(target);
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+
+ retval = mips32_verify_pointer(CMD, mips32);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (target->state != TARGET_HALTED) {
+ command_print(CMD, "target must be stopped for \"%s\" command", CMD_NAME);
+ return ERROR_OK;
+ }
+
+ /* Check for too many command args */
+ if (CMD_ARGC >= 3)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ /* Check if DSP access supported or not */
+ if (!mips32->dsp_imp) {
+ /* Issue Error Message */
+ command_print(CMD, "DSP not implemented by this processor");
+ return ERROR_OK;
+ }
+
+ switch (CMD_ARGC) {
+ case 0:
+ retval = mips32_dsp_get_all_regs(CMD, ejtag_info);
+ break;
+ case 1:
+ retval = mips32_dsp_get_register(CMD, ejtag_info);
+ break;
+ case 2:
+ tmp = *CMD_ARGV[0];
+ if (isdigit(tmp)) {
+ command_print(CMD, "Error: invalid dsp command format");
+ retval = ERROR_COMMAND_ARGUMENT_INVALID;
+ } else {
+ retval = mips32_dsp_set_register(CMD, ejtag_info);
+ }
+ break;
+ default:
+ command_print(CMD, "Error: invalid argument format, required 0-2, given %d", CMD_ARGC);
+ retval = ERROR_COMMAND_ARGUMENT_INVALID;
+ break;
+ }
+ return retval;
+}
+
/**
* mips32_handle_ejtag_reg_command - Handler commands related to EJTAG
* @param[in] cmd: Command invocation context
@@ -1847,6 +2267,14 @@ static const struct command_registration mips32_exec_command_handlers[] = {
.help = "display CPU information",
.usage = "",
},
+ {
+ .name = "dsp",
+ .handler = mips32_handle_dsp_command,
+ .mode = COMMAND_EXEC,
+ .help = "display or set DSP register; "
+ "with no arguments, displays all registers and their values",
+ .usage = "[[register_name] [value]]",
+ },
{
.name = "scan_delay",
.handler = mips32_handle_scan_delay_command,
diff --git a/src/target/mips32.h b/src/target/mips32.h
index 208c9da17..d512e4970 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -69,7 +69,7 @@
#define MIPS32_SCAN_DELAY_LEGACY_MODE 2000000
-#define MIPS32_NUM_DSPREGS 9
+#define MIPS32NUMDSPREGS 9
/* Bit Mask indicating CP0 register supported by this core */
#define MIPS_CP0_MK4 0x0001
@@ -734,6 +734,24 @@ struct mips32_algorithm {
/* ejtag specific instructions */
#define MICRO_MIPS32_SDBBP 0x000046C0
#define MICRO_MIPS_SDBBP 0x46C0
+#define MIPS32_DSP_ENABLE 0x1000000
+
+#define MIPS32_S_INST(rs, rac, opcode) \
+ (((rs) << 21) | ((rac) << 11) | (opcode))
+
+#define MIPS32_DSP_R_INST(rt, immd, opcode, extrw) \
+ ((0x1F << 26) | ((immd) << 16) | ((rt) << 11) | ((opcode) << 6) | (extrw))
+#define MIPS32_DSP_W_INST(rs, immd, opcode, extrw) \
+ ((0x1F << 26) | ((rs) << 21) | ((immd) << 11) | ((opcode) << 6) | (extrw))
+
+#define MIPS32_DSP_MFHI(reg, ac) MIPS32_R_INST(0, ac, 0, reg, 0, MIPS32_OP_MFHI)
+#define MIPS32_DSP_MFLO(reg, ac) MIPS32_R_INST(0, ac, 0, reg, 0, MIPS32_OP_MFLO)
+#define MIPS32_DSP_MTLO(reg, ac) MIPS32_S_INST(reg, ac, MIPS32_OP_MTLO)
+#define MIPS32_DSP_MTHI(reg, ac) MIPS32_S_INST(reg, ac, MIPS32_OP_MTHI)
+#define MIPS32_DSP_RDDSP(rt, mask) MIPS32_DSP_R_INST(rt, mask, 0x12, 0x38)
+#define MIPS32_DSP_WRDSP(rs, mask) MIPS32_DSP_W_INST(rs, mask, 0x13, 0x38)
+
+
/*
* MIPS32 Config1 Register (CP0 Register 16, Select 1)
*/
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 5 +
src/target/mips32.c | 428 ++++++++++++++++++++++++++++++++++++++++++++++++++++
src/target/mips32.h | 20 ++-
3 files changed, 452 insertions(+), 1 deletion(-)
hooks/post-receive
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Main OpenOCD repository
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From: openocd-gerrit <ope...@us...> - 2024-03-09 11:04:57
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via fcda9f1561bfc413e3723e5b4552bc7e91eb4a8d (commit)
from 5c395fdef42a5750852ea0fc0abd944cf303a39b (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit fcda9f1561bfc413e3723e5b4552bc7e91eb4a8d
Author: Antonio Borneo <bor...@gm...>
Date: Sun Feb 25 18:36:47 2024 +0100
gdb_server: fix segfault with GDB command 'flash-erase'
Running the GDB command 'flash-erase' triggers sending the remote
GDB commands 'vFlashErase' (one per flash bank) followed by one
single 'vFlashDone', with no 'vFlashWrite' commands in between.
This causes the field 'gdb_connection->vflash_image' to be NULL
during the execution of 'vFlashDone', triggering a segmentation
fault in OpenOCD.
While parsing 'vFlashDone', check if any image to flash has been
received.
Change-Id: I443021c7a531255b60f2c44c2685e52e3c34b5c8
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8164
Tested-by: jenkins
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index b14068941..ae288de1c 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -3376,6 +3376,13 @@ static int gdb_v_packet(struct connection *connection,
if (strncmp(packet, "vFlashDone", 10) == 0) {
uint32_t written;
+ /* GDB command 'flash-erase' does not send a vFlashWrite,
+ * so nothing to write here. */
+ if (!gdb_connection->vflash_image) {
+ gdb_put_packet(connection, "OK", 2);
+ return ERROR_OK;
+ }
+
/* process the flashing buffer. No need to erase as GDB
* always issues a vFlashErase first. */
target_call_event_callbacks(target,
-----------------------------------------------------------------------
Summary of changes:
src/server/gdb_server.c | 7 +++++++
1 file changed, 7 insertions(+)
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From: openocd-gerrit <ope...@us...> - 2024-03-09 11:04:19
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 5c395fdef42a5750852ea0fc0abd944cf303a39b (commit)
from 61e19349b2b83f844e9729a76ad5698e6c77c686 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 5c395fdef42a5750852ea0fc0abd944cf303a39b
Author: Antonio Borneo <bor...@gm...>
Date: Sun Feb 25 12:22:44 2024 +0100
mem_ap: fix GDB connections
After commit d9b2607ca094 ("gdb_server: support sparse register
maps"), GDB crashes while requesting the value of 'cpsr' because
the fake register is tagged as not existing.
Change the logic and set all register as existing, while still
limiting the list for the initial GDB request at connect.
Change-Id: I1c4e274c06147683db2a59a8920ae5ccd863e15c
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8163
Tested-by: jenkins
diff --git a/src/target/mem_ap.c b/src/target/mem_ap.c
index 5c81e3a75..61a9475e6 100644
--- a/src/target/mem_ap.c
+++ b/src/target/mem_ap.c
@@ -194,11 +194,11 @@ static const char *mem_ap_get_gdb_arch(const struct target *target)
* reg[24]: 32 bits, fps
* reg[25]: 32 bits, cpsr
*
- * Set 'exist' only to reg[0..15], so initial response to GDB is correct
+ * GDB requires only reg[0..15]
*/
#define NUM_REGS 26
+#define NUM_GDB_REGS 16
#define MAX_REG_SIZE 96
-#define REG_EXIST(n) ((n) < 16)
#define REG_SIZE(n) ((((n) >= 16) && ((n) < 24)) ? 96 : 32)
struct mem_ap_alloc_reg_list {
@@ -218,14 +218,14 @@ static int mem_ap_get_gdb_reg_list(struct target *target, struct reg **reg_list[
}
*reg_list = mem_ap_alloc->reg_list;
- *reg_list_size = NUM_REGS;
+ *reg_list_size = (reg_class == REG_CLASS_ALL) ? NUM_REGS : NUM_GDB_REGS;
struct reg *regs = mem_ap_alloc->regs;
for (int i = 0; i < NUM_REGS; i++) {
regs[i].number = i;
regs[i].value = mem_ap_alloc->regs_value;
regs[i].size = REG_SIZE(i);
- regs[i].exist = REG_EXIST(i);
+ regs[i].exist = true;
regs[i].type = &mem_ap_reg_arch_type;
(*reg_list)[i] = ®s[i];
}
-----------------------------------------------------------------------
Summary of changes:
src/target/mem_ap.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2024-03-09 11:03:11
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from cdc569ce3a0d76a638378b7d97ae9f5f1bcbd3c6 (commit)
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- Log -----------------------------------------------------------------
commit 61e19349b2b83f844e9729a76ad5698e6c77c686
Author: Tomas Vanek <va...@fb...>
Date: Mon Jan 22 12:13:46 2024 +0100
flash/nor/nrf5: use BIT() instead of << operator
for features flags.
Change-Id: I8bff0f5fac41c50180c847f36c6d2a075eca32ca
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8109
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index 35fa6d142..3f451a76c 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -17,6 +17,7 @@
#include <target/armv7m.h>
#include <helper/types.h>
#include <helper/time_support.h>
+#include <helper/bits.h>
/* Both those values are constant across the current spectrum ofr nRF5 devices */
#define WATCHDOG_REFRESH_REGISTER 0x40010600
@@ -94,10 +95,10 @@ struct nrf52_ficr_info {
};
enum nrf5_features {
- NRF5_FEATURE_SERIES_51 = 1 << 0,
- NRF5_FEATURE_SERIES_52 = 1 << 1,
- NRF5_FEATURE_BPROT = 1 << 2,
- NRF5_FEATURE_ACL_PROT = 1 << 3,
+ NRF5_FEATURE_SERIES_51 = BIT(0),
+ NRF5_FEATURE_SERIES_52 = BIT(1),
+ NRF5_FEATURE_BPROT = BIT(2),
+ NRF5_FEATURE_ACL_PROT = BIT(3),
};
struct nrf5_device_spec {
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/nrf5.c | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2024-03-09 11:02:47
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
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- Log -----------------------------------------------------------------
commit cdc569ce3a0d76a638378b7d97ae9f5f1bcbd3c6
Author: Tomas Vanek <va...@fb...>
Date: Sun Jan 21 23:34:30 2024 +0100
flash/nor/nrf5: drop nrf5 info command
The command substantially complicates support of nRF53/91
series. It was not even properly ported to nRF52.
The informative value is disputable. Who wants to see
e.g. override trim values for radio or unique device ID?
Drop it and simplify the driver.
Change-Id: Ia7fb20ce2ebf16065705c5d18deaf934e58db426
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8108
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 38c897045..4297258d9 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -7319,10 +7319,6 @@ works only for chips that do not have factory pre-programmed region 0
code.
@end deffn
-@deffn {Command} {nrf5 info}
-Decodes and shows information from FICR and UICR registers.
-@end deffn
-
@end deffn
@deffn {Flash Driver} {ocl}
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index 7bc1f0cfe..35fa6d142 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -46,32 +46,6 @@ enum nrf5_ficr_registers {
* On nRF52 is present but not documented */
NRF5_FICR_CONFIGID = NRF5_FICR_REG(0x05C),
- NRF5_FICR_DEVICEID0 = NRF5_FICR_REG(0x060),
- NRF5_FICR_DEVICEID1 = NRF5_FICR_REG(0x064),
- NRF5_FICR_ER0 = NRF5_FICR_REG(0x080),
- NRF5_FICR_ER1 = NRF5_FICR_REG(0x084),
- NRF5_FICR_ER2 = NRF5_FICR_REG(0x088),
- NRF5_FICR_ER3 = NRF5_FICR_REG(0x08C),
- NRF5_FICR_IR0 = NRF5_FICR_REG(0x090),
- NRF5_FICR_IR1 = NRF5_FICR_REG(0x094),
- NRF5_FICR_IR2 = NRF5_FICR_REG(0x098),
- NRF5_FICR_IR3 = NRF5_FICR_REG(0x09C),
- NRF5_FICR_DEVICEADDRTYPE = NRF5_FICR_REG(0x0A0),
- NRF5_FICR_DEVICEADDR0 = NRF5_FICR_REG(0x0A4),
- NRF5_FICR_DEVICEADDR1 = NRF5_FICR_REG(0x0A8),
-
- NRF51_FICR_OVERRIDEN = NRF5_FICR_REG(0x0AC),
- NRF51_FICR_NRF_1MBIT0 = NRF5_FICR_REG(0x0B0),
- NRF51_FICR_NRF_1MBIT1 = NRF5_FICR_REG(0x0B4),
- NRF51_FICR_NRF_1MBIT2 = NRF5_FICR_REG(0x0B8),
- NRF51_FICR_NRF_1MBIT3 = NRF5_FICR_REG(0x0BC),
- NRF51_FICR_NRF_1MBIT4 = NRF5_FICR_REG(0x0C0),
- NRF51_FICR_BLE_1MBIT0 = NRF5_FICR_REG(0x0EC),
- NRF51_FICR_BLE_1MBIT1 = NRF5_FICR_REG(0x0F0),
- NRF51_FICR_BLE_1MBIT2 = NRF5_FICR_REG(0x0F4),
- NRF51_FICR_BLE_1MBIT3 = NRF5_FICR_REG(0x0F8),
- NRF51_FICR_BLE_1MBIT4 = NRF5_FICR_REG(0x0FC),
-
/* Following registers are available on nRF52 and on nRF51 since rev 3 */
NRF5_FICR_INFO_PART = NRF5_FICR_REG(0x100),
NRF5_FICR_INFO_VARIANT = NRF5_FICR_REG(0x104),
@@ -87,9 +61,6 @@ enum nrf5_uicr_registers {
#define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
NRF51_UICR_CLENR0 = NRF5_UICR_REG(0x000),
- NRF51_UICR_RBPCONF = NRF5_UICR_REG(0x004),
- NRF51_UICR_XTALFREQ = NRF5_UICR_REG(0x008),
- NRF51_UICR_FWID = NRF5_UICR_REG(0x010),
};
enum nrf5_nvmc_registers {
@@ -1251,136 +1222,6 @@ COMMAND_HANDLER(nrf5_handle_mass_erase_command)
return res;
}
-COMMAND_HANDLER(nrf5_handle_info_command)
-{
- int res;
- struct flash_bank *bank = NULL;
- struct target *target = get_current_target(CMD_CTX);
-
- res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
- if (res != ERROR_OK)
- return res;
-
- assert(bank);
-
- struct nrf5_bank *nbank = bank->driver_priv;
- assert(nbank);
- struct nrf5_info *chip = nbank->chip;
- assert(chip);
-
- static struct {
- const uint32_t address;
- uint32_t value;
- } ficr[] = {
- { .address = NRF5_FICR_CODEPAGESIZE },
- { .address = NRF5_FICR_CODESIZE },
- { .address = NRF51_FICR_CLENR0 },
- { .address = NRF51_FICR_PPFC },
- { .address = NRF51_FICR_NUMRAMBLOCK },
- { .address = NRF51_FICR_SIZERAMBLOCK0 },
- { .address = NRF51_FICR_SIZERAMBLOCK1 },
- { .address = NRF51_FICR_SIZERAMBLOCK2 },
- { .address = NRF51_FICR_SIZERAMBLOCK3 },
- { .address = NRF5_FICR_CONFIGID },
- { .address = NRF5_FICR_DEVICEID0 },
- { .address = NRF5_FICR_DEVICEID1 },
- { .address = NRF5_FICR_ER0 },
- { .address = NRF5_FICR_ER1 },
- { .address = NRF5_FICR_ER2 },
- { .address = NRF5_FICR_ER3 },
- { .address = NRF5_FICR_IR0 },
- { .address = NRF5_FICR_IR1 },
- { .address = NRF5_FICR_IR2 },
- { .address = NRF5_FICR_IR3 },
- { .address = NRF5_FICR_DEVICEADDRTYPE },
- { .address = NRF5_FICR_DEVICEADDR0 },
- { .address = NRF5_FICR_DEVICEADDR1 },
- { .address = NRF51_FICR_OVERRIDEN },
- { .address = NRF51_FICR_NRF_1MBIT0 },
- { .address = NRF51_FICR_NRF_1MBIT1 },
- { .address = NRF51_FICR_NRF_1MBIT2 },
- { .address = NRF51_FICR_NRF_1MBIT3 },
- { .address = NRF51_FICR_NRF_1MBIT4 },
- { .address = NRF51_FICR_BLE_1MBIT0 },
- { .address = NRF51_FICR_BLE_1MBIT1 },
- { .address = NRF51_FICR_BLE_1MBIT2 },
- { .address = NRF51_FICR_BLE_1MBIT3 },
- { .address = NRF51_FICR_BLE_1MBIT4 },
- }, uicr[] = {
- { .address = NRF51_UICR_CLENR0, },
- { .address = NRF51_UICR_RBPCONF },
- { .address = NRF51_UICR_XTALFREQ },
- { .address = NRF51_UICR_FWID },
- };
-
- for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
- res = target_read_u32(chip->target, ficr[i].address,
- &ficr[i].value);
- if (res != ERROR_OK) {
- LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
- return res;
- }
- }
-
- for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
- res = target_read_u32(chip->target, uicr[i].address,
- &uicr[i].value);
- if (res != ERROR_OK) {
- LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
- return res;
- }
- }
-
- command_print(CMD,
- "\n[factory information control block]\n\n"
- "code page size: %"PRIu32"B\n"
- "code memory size: %"PRIu32"kB\n"
- "code region 0 size: %"PRIu32"kB\n"
- "pre-programmed code: %s\n"
- "number of ram blocks: %"PRIu32"\n"
- "ram block 0 size: %"PRIu32"B\n"
- "ram block 1 size: %"PRIu32"B\n"
- "ram block 2 size: %"PRIu32"B\n"
- "ram block 3 size: %"PRIu32 "B\n"
- "config id: %" PRIx32 "\n"
- "device id: 0x%"PRIx32"%08"PRIx32"\n"
- "encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
- "identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
- "device address type: 0x%"PRIx32"\n"
- "device address: 0x%"PRIx32"%08"PRIx32"\n"
- "override enable: %"PRIx32"\n"
- "NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
- "BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
- "\n[user information control block]\n\n"
- "code region 0 size: %"PRIu32"kB\n"
- "read back protection configuration: %"PRIx32"\n"
- "reset value for XTALFREQ: %"PRIx32"\n"
- "firmware id: 0x%04"PRIx32,
- ficr[0].value,
- (ficr[1].value * ficr[0].value) / 1024,
- (ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
- ((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
- ficr[4].value,
- ficr[5].value,
- (ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
- (ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
- (ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
- ficr[9].value,
- ficr[10].value, ficr[11].value,
- ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
- ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
- ficr[20].value,
- ficr[21].value, ficr[22].value,
- ficr[23].value,
- ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
- ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
- (uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
- uicr[1].value & 0xFFFF,
- uicr[2].value & 0xFF,
- uicr[3].value & 0xFFFF);
-
- return ERROR_OK;
-}
static const struct command_registration nrf5_exec_command_handlers[] = {
{
@@ -1390,13 +1231,6 @@ static const struct command_registration nrf5_exec_command_handlers[] = {
.help = "Erase all flash contents of the chip.",
.usage = "",
},
- {
- .name = "info",
- .handler = nrf5_handle_info_command,
- .mode = COMMAND_EXEC,
- .help = "Show FICR and UICR info.",
- .usage = "",
- },
COMMAND_REGISTRATION_DONE
};
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 4 --
src/flash/nor/nrf5.c | 166 ---------------------------------------------------
2 files changed, 170 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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From: openocd-gerrit <ope...@us...> - 2024-03-09 11:02:35
|
This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 2db325f5395fa24aefbf137584e5fdeedf390e97
Author: Tomas Vanek <va...@fb...>
Date: Sun Jan 21 18:14:14 2024 +0100
flash/nor/nrf5: drop nrf5_get_probed_chip_if_halted()
nrf5_get_probed_chip_if_halted() was somewhat bizarre
combination of functions:
- test if the target is halted is appropriate for flash
erase/write only, certainly not for getting chip info
- getting chip pointer takes place more frequently
and using one temporary variable for dereference
makes no harm
- probing chip is useless at all as the flash
infrastructure always calls auto_probe() before
entering a flash operation
Replace the function by ordinary and readable code.
Change-Id: Ic31f4e33d8b7b36687be3f40bfd0fe913d17b75f
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8107
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index 4446b3081..7bc1f0cfe 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -271,28 +271,10 @@ const struct flash_driver nrf5_flash, nrf51_flash;
static bool nrf5_bank_is_probed(const struct flash_bank *bank)
{
struct nrf5_bank *nbank = bank->driver_priv;
-
assert(nbank);
return nbank->probed;
}
-static int nrf5_probe(struct flash_bank *bank);
-
-static int nrf5_get_probed_chip_if_halted(struct flash_bank *bank, struct nrf5_info **chip)
-{
- if (bank->target->state != TARGET_HALTED) {
- LOG_ERROR("Target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
- struct nrf5_bank *nbank = bank->driver_priv;
- *chip = nbank->chip;
-
- if (nrf5_bank_is_probed(bank))
- return ERROR_OK;
-
- return nrf5_probe(bank);
-}
static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
{
@@ -420,9 +402,10 @@ static int nrf5_protect_check_clenr0(struct flash_bank *bank)
{
int res;
uint32_t clenr0;
+
struct nrf5_bank *nbank = bank->driver_priv;
+ assert(nbank);
struct nrf5_info *chip = nbank->chip;
-
assert(chip);
res = target_read_u32(chip->target, NRF51_FICR_CLENR0,
@@ -451,8 +434,8 @@ static int nrf5_protect_check_clenr0(struct flash_bank *bank)
static int nrf5_protect_check_bprot(struct flash_bank *bank)
{
struct nrf5_bank *nbank = bank->driver_priv;
+ assert(nbank);
struct nrf5_info *chip = nbank->chip;
-
assert(chip);
static uint32_t nrf5_bprot_offsets[4] = { 0x600, 0x604, 0x610, 0x614 };
@@ -482,8 +465,8 @@ static int nrf5_protect_check(struct flash_bank *bank)
return ERROR_OK;
struct nrf5_bank *nbank = bank->driver_priv;
+ assert(nbank);
struct nrf5_info *chip = nbank->chip;
-
assert(chip);
if (chip->features & NRF5_FEATURE_BPROT)
@@ -501,8 +484,11 @@ static int nrf5_protect_clenr0(struct flash_bank *bank, int set, unsigned int fi
{
int res;
uint32_t clenr0, ppfc;
+
struct nrf5_bank *nbank = bank->driver_priv;
+ assert(nbank);
struct nrf5_info *chip = nbank->chip;
+ assert(chip);
if (first != 0) {
LOG_ERROR("Code region 0 must start at the beginning of the bank");
@@ -559,18 +545,21 @@ error:
static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first,
unsigned int last)
{
- int res;
- struct nrf5_info *chip;
-
/* UICR cannot be write protected so just bail out early */
if (bank->base == NRF5_UICR_BASE) {
LOG_ERROR("UICR page does not support protection");
return ERROR_FLASH_OPER_UNSUPPORTED;
}
- res = nrf5_get_probed_chip_if_halted(bank, &chip);
- if (res != ERROR_OK)
- return res;
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ struct nrf5_bank *nbank = bank->driver_priv;
+ assert(nbank);
+ struct nrf5_info *chip = nbank->chip;
+ assert(chip);
if (chip->features & NRF5_FEATURE_SERIES_51)
return nrf5_protect_clenr0(bank, set, first, last);
@@ -631,7 +620,9 @@ static int get_nrf5_chip_type_str(const struct nrf5_info *chip, char *buf, unsig
static int nrf5_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct nrf5_bank *nbank = bank->driver_priv;
+ assert(nbank);
struct nrf5_info *chip = nbank->chip;
+ assert(chip);
char chip_type_str[256];
if (get_nrf5_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
@@ -748,8 +739,11 @@ static int nrf5_get_ram_size(struct target *target, uint32_t *ram_size)
static int nrf5_probe(struct flash_bank *bank)
{
int res;
+
struct nrf5_bank *nbank = bank->driver_priv;
+ assert(nbank);
struct nrf5_info *chip = nbank->chip;
+ assert(chip);
struct target *target = chip->target;
uint32_t configid;
@@ -1017,11 +1011,17 @@ static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const u
static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
- struct nrf5_info *chip;
+ int res;
- int res = nrf5_get_probed_chip_if_halted(bank, &chip);
- if (res != ERROR_OK)
- return res;
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ struct nrf5_bank *nbank = bank->driver_priv;
+ assert(nbank);
+ struct nrf5_info *chip = nbank->chip;
+ assert(chip);
assert(offset % 4 == 0);
assert(count % 4 == 0);
@@ -1074,11 +1074,16 @@ static int nrf5_erase(struct flash_bank *bank, unsigned int first,
unsigned int last)
{
int res;
- struct nrf5_info *chip;
- res = nrf5_get_probed_chip_if_halted(bank, &chip);
- if (res != ERROR_OK)
- return res;
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ struct nrf5_bank *nbank = bank->driver_priv;
+ assert(nbank);
+ struct nrf5_info *chip = nbank->chip;
+ assert(chip);
/* UICR CLENR0 based protection used on nRF51 prevents erase
* absolutely silently. NVMC has no flag to indicate the protection
@@ -1115,6 +1120,7 @@ static int nrf5_erase(struct flash_bank *bank, unsigned int first,
static void nrf5_free_driver_priv(struct flash_bank *bank)
{
struct nrf5_bank *nbank = bank->driver_priv;
+ assert(nbank);
struct nrf5_info *chip = nbank->chip;
if (!chip)
return;
@@ -1206,11 +1212,15 @@ COMMAND_HANDLER(nrf5_handle_mass_erase_command)
assert(bank);
- struct nrf5_info *chip;
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
- res = nrf5_get_probed_chip_if_halted(bank, &chip);
- if (res != ERROR_OK)
- return res;
+ struct nrf5_bank *nbank = bank->driver_priv;
+ assert(nbank);
+ struct nrf5_info *chip = nbank->chip;
+ assert(chip);
if (chip->features & NRF5_FEATURE_SERIES_51) {
uint32_t ppfc;
@@ -1253,11 +1263,10 @@ COMMAND_HANDLER(nrf5_handle_info_command)
assert(bank);
- struct nrf5_info *chip;
-
- res = nrf5_get_probed_chip_if_halted(bank, &chip);
- if (res != ERROR_OK)
- return res;
+ struct nrf5_bank *nbank = bank->driver_priv;
+ assert(nbank);
+ struct nrf5_info *chip = nbank->chip;
+ assert(chip);
static struct {
const uint32_t address;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/nrf5.c | 97 ++++++++++++++++++++++++++++------------------------
1 file changed, 53 insertions(+), 44 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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From: openocd-gerrit <ope...@us...> - 2024-03-09 11:01:55
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 42e4f26a3da8203d8f28c3edc490968273b1d904 (commit)
from 85bc3289699a23dfb66bd10927aa1a6330e3668c (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 42e4f26a3da8203d8f28c3edc490968273b1d904
Author: Tomas Vanek <va...@fb...>
Date: Sun Jan 21 18:08:33 2024 +0100
flash/nor/nrf5: add missing device types
from nRF52 family.
Change-Id: I6d2b4586700bb4014c0b77dbf4ea26d1b5dc9715
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8106
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index b6d712d3f..4446b3081 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -665,11 +665,15 @@ static int nrf5_read_ficr_info(struct nrf5_info *chip)
chip->features = NRF5_FEATURE_SERIES_52;
switch (chip->ficr_info.part) {
+ case 0x52805:
case 0x52810:
+ case 0x52811:
case 0x52832:
chip->features |= NRF5_FEATURE_BPROT;
break;
+ case 0x52820:
+ case 0x52833:
case 0x52840:
chip->features |= NRF5_FEATURE_ACL_PROT;
break;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/nrf5.c | 4 ++++
1 file changed, 4 insertions(+)
hooks/post-receive
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Main OpenOCD repository
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From: openocd-gerrit <ope...@us...> - 2024-03-09 11:01:29
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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via 19ef6634f021f545c2154cdd6d011608f1249308 (commit)
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- Log -----------------------------------------------------------------
commit 85bc3289699a23dfb66bd10927aa1a6330e3668c
Author: Tomas Vanek <va...@fb...>
Date: Sun Jan 21 18:00:06 2024 +0100
flash/nor/nrf5: add missing package codes
from Product Specification of nRF52805, 810, 811
820, 833 and 840.
While on it, rename the table to make sure the codes
are valid for nRF52 series only.
Change-Id: Id8f78fd214c5d345d1769378ae546a6be5a183ba
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8105
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index 18efae5c6..b6d712d3f 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -254,11 +254,16 @@ struct nrf5_device_package {
/* Newer devices have FICR INFO.PACKAGE.
* This table converts its value to two character code */
-static const struct nrf5_device_package nrf5_packages_table[] = {
+static const struct nrf5_device_package nrf52_packages_table[] = {
{ 0x2000, "QF" },
{ 0x2001, "CH" },
{ 0x2002, "CI" },
+ { 0x2003, "QC" },
+ { 0x2004, "QI/CA" }, /* differs nRF52805, 810, 811: CA, nRF52833, 840: QI */
{ 0x2005, "CK" },
+ { 0x2007, "QD" },
+ { 0x2008, "CJ" },
+ { 0x2009, "CF" },
};
const struct flash_driver nrf5_flash, nrf51_flash;
@@ -591,9 +596,9 @@ static bool nrf5_info_variant_to_str(uint32_t variant, char *bf)
static const char *nrf5_decode_info_package(uint32_t package)
{
- for (size_t i = 0; i < ARRAY_SIZE(nrf5_packages_table); i++) {
- if (nrf5_packages_table[i].package == package)
- return nrf5_packages_table[i].code;
+ for (size_t i = 0; i < ARRAY_SIZE(nrf52_packages_table); i++) {
+ if (nrf52_packages_table[i].package == package)
+ return nrf52_packages_table[i].code;
}
return "xx";
}
commit 19ef6634f021f545c2154cdd6d011608f1249308
Author: Tomas Vanek <va...@fb...>
Date: Sun Jan 21 16:01:00 2024 +0100
target/nrf51: use PAN #16 workaround in reset-init only
After 'reset run' or 'reset halt' the loaded application
is expected to manipulate RAMON register to workaround
the known silicon errata.
Moreover, writing to RAMON register from 'reset-end' event
after 'reset run' may collide with application intentions.
Use the workaround in 'reset-init' event only to ensure
correct function of target algorithms.
Change-Id: I7d2d92e6805a05a83676edb46b3163ef39b9a7e4
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8104
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg
index 53ac3069f..3781eccb5 100644
--- a/tcl/target/nrf51.cfg
+++ b/tcl/target/nrf51.cfg
@@ -58,4 +58,4 @@ proc enable_all_ram {} {
# resetting we enable all banks via the RAMON register
mww 0x40000524 0xF
}
-$_TARGETNAME configure -event reset-end { enable_all_ram }
+$_TARGETNAME configure -event reset-init { enable_all_ram }
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/nrf5.c | 13 +++++++++----
tcl/target/nrf51.cfg | 2 +-
2 files changed, 10 insertions(+), 5 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2024-03-09 11:01:01
|
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- Log -----------------------------------------------------------------
commit 1354ff7adfeff5d0c1024c2f2e9a9cd714a753d8
Author: Tomas Vanek <va...@fb...>
Date: Sun Jan 21 15:55:37 2024 +0100
flash/nor/nrf5, target/nrf51: deprecate nrf51 flash driver
Use the newer driver name 'nrf5' instead.
While on it set the unused parameters of flash bank
creation to zero.
While on it remove 2 empty comments.
Change-Id: I9cf0eadc5b696e6c8b7e6aec0ea3345967523e87
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8103
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index 001843d39..18efae5c6 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -1144,6 +1144,9 @@ FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
struct nrf5_info *chip;
struct nrf5_bank *nbank = NULL;
+ if (bank->driver == &nrf51_flash)
+ LOG_WARNING("Flash driver 'nrf51' is deprecated! Use 'nrf5' instead.");
+
switch (bank->base) {
case NRF5_FLASH_BASE:
case NRF5_UICR_BASE:
diff --git a/tcl/target/nrf51.cfg b/tcl/target/nrf51.cfg
index 48c2715d1..53ac3069f 100644
--- a/tcl/target/nrf51.cfg
+++ b/tcl/target/nrf51.cfg
@@ -45,13 +45,11 @@ if {![using_hla]} {
cortex_m reset_config sysresetreq
}
-flash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME
-flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
+flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 0 0 $_TARGETNAME
-#
# The chip should start up from internal 16Mhz RC, so setting adapter
# clock to 1Mhz should be OK
-#
adapter speed 1000
proc enable_all_ram {} {
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/nrf5.c | 3 +++
tcl/target/nrf51.cfg | 6 ++----
2 files changed, 5 insertions(+), 4 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2024-03-09 11:00:30
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from 07141132a7d787005c0829618a60b4a842be7847 (commit)
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- Log -----------------------------------------------------------------
commit 46ae39c6236ec04f7e518d876b3cd9dafb6eb878
Author: Tomas Vanek <va...@fb...>
Date: Sun Jan 21 15:40:37 2024 +0100
flash/nor/nrf5: drop unused part of HWIDs table
While on it update table comment and drop
not working URLs.
Change-Id: I9e21c72aa75a908c644460e43c148d3240c49b2d
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8102
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index d5de4a464..001843d39 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -42,7 +42,10 @@ enum nrf5_ficr_registers {
NRF51_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040),
NRF51_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044),
+ /* CONFIGID is documented on nRF51 series only.
+ * On nRF52 is present but not documented */
NRF5_FICR_CONFIGID = NRF5_FICR_REG(0x05C),
+
NRF5_FICR_DEVICEID0 = NRF5_FICR_REG(0x060),
NRF5_FICR_DEVICEID1 = NRF5_FICR_REG(0x064),
NRF5_FICR_ER0 = NRF5_FICR_REG(0x080),
@@ -164,26 +167,20 @@ struct nrf5_info {
.features = NRF5_FEATURE_SERIES_51, \
}
-#define NRF5_DEVICE_DEF(id, pt, var, bcode, fsize, features) \
-{ \
-.hwid = (id), \
-.part = pt, \
-.variant = var, \
-.build_code = bcode, \
-.flash_size_kb = (fsize), \
-.features = features, \
-}
-
-/* The known devices table below is derived from the "nRF5x series
- * compatibility matrix" documents, which can be found in the "DocLib" of
- * nordic:
+/*
+ * The table maps known HWIDs to the part numbers, variant
+ * build code and some other info. For nRF51 rev 1 and 2 devices
+ * this is the only way how to get the part number and variant.
*
- * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51422_ic_revision_overview
- * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51822_ic_revision_overview
- * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF51/latest/COMP/nrf51/nRF51824_ic_revision_overview
- * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52810/latest/COMP/nrf52810/nRF52810_ic_revision_overview
- * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52832/latest/COMP/nrf52832/ic_revision_overview
- * https://www.nordicsemi.com/DocLib/Content/Comp_Matrix/nRF52840/latest/COMP/nrf52840/nRF52840_ic_revision_overview
+ * All tested nRF51 rev 3 devices have FICR INFO fields
+ * but the fields are not documented in RM so we keep HWIDs in
+ * this table.
+ *
+ * nRF52 and newer devices have FICR INFO documented, the autodetection
+ * can rely on it and HWIDs table is not used.
+ *
+ * The known devices table below is derived from the "nRF5x series
+ * compatibility matrix" documents.
*
* Up to date with Matrix v2.0, plus some additional HWIDs.
*
@@ -248,19 +245,6 @@ static const struct nrf5_device_spec nrf5_known_devices_table[] = {
/* The driver fully autodetects nRF52 series devices by FICR INFO,
* no need for nRF52xxx HWIDs in this table */
-#if 0
- /* nRF52810 Devices */
- NRF5_DEVICE_DEF(0x0142, "52810", "QFAA", "B0", 192, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
- NRF5_DEVICE_DEF(0x0143, "52810", "QCAA", "C0", 192, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
-
- /* nRF52832 Devices */
- NRF5_DEVICE_DEF(0x00C7, "52832", "QFAA", "B0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
- NRF5_DEVICE_DEF(0x0139, "52832", "QFAA", "E0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
- NRF5_DEVICE_DEF(0x00E3, "52832", "CIAA", "B0", 512, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_BPROT),
-
- /* nRF52840 Devices */
- NRF5_DEVICE_DEF(0x0150, "52840", "QIAA", "C0", 1024, NRF5_FEATURE_SERIES_52 | NRF5_FEATURE_ACL_PROT),
-#endif
};
struct nrf5_device_package {
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/nrf5.c | 48 ++++++++++++++++--------------------------------
1 file changed, 16 insertions(+), 32 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2024-03-02 11:06:21
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 07141132a7d787005c0829618a60b4a842be7847 (commit)
from 271c4e5253abcd2ec617d5fb5e1a374d2b6a543d (commit)
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- Log -----------------------------------------------------------------
commit 07141132a7d787005c0829618a60b4a842be7847
Author: Antonio Borneo <bor...@gm...>
Date: Sat Dec 4 00:48:23 2021 +0100
gdb_server: don't send unrequested ACK at connection
On 2008-03-05, before git's age, commit 6d9501467441 adds sending
an ACK ('+' char) at GDB connection, before receiving any GDB
remote command that requires to be ACK'ed.
Neither the text added in the commit message ("added ACK upon
connection (send +)") nor in the associated comment ("send ACK to
GDB for debug request") provide an exhaustive explanation for
sending this unsolicited ACK.
This code has never been touched since its introduction.
Analysis of GDB code doesn't show it's required, including old GDB
code.
Running gdbserver (from GDB package) and attaching it with "nc"
shows that gdbserver does not send any ACK to a new connection.
Same for lldb-server.
Drop it!
Change-Id: Id68c352ce44dd85a1ea3d67446e17e2a241ef058
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6768
Tested-by: jenkins
Reviewed-by: Jan Matyas <jan...@co...>
Reviewed-by: Anatoly P <ana...@sy...>
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 13bc23395..b14068941 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -1001,9 +1001,6 @@ static int gdb_new_connection(struct connection *connection)
gdb_connection->output_flag = GDB_OUTPUT_NO;
gdb_connection->unique_index = next_unique_id++;
- /* send ACK to GDB for debug request */
- gdb_write(connection, "+", 1);
-
/* output goes through gdb connection */
command_set_output_handler(connection->cmd_ctx, gdb_output, connection);
-----------------------------------------------------------------------
Summary of changes:
src/server/gdb_server.c | 3 ---
1 file changed, 3 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2024-03-02 11:04:48
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 271c4e5253abcd2ec617d5fb5e1a374d2b6a543d (commit)
from 56a7925a1d2d890adbb5dbd76542bfe901620103 (commit)
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- Log -----------------------------------------------------------------
commit 271c4e5253abcd2ec617d5fb5e1a374d2b6a543d
Author: Erhan Kurubas <erh...@es...>
Date: Sat Feb 24 20:29:41 2024 +0100
target/esp_xtensa_smp: don't use coreid as an SMP index
For the sake of https://review.openocd.org/c/openocd/+/7957
Instead of "coreid", 'target smp' command call order used as
an index
Signed-off-by: Erhan Kurubas <erh...@es...>
Change-Id: Iab86b81868d37c0bf8663707ee11367c41f6b96d
Reviewed-on: https://review.openocd.org/c/openocd/+/8162
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/espressif/esp_xtensa_smp.c b/src/target/espressif/esp_xtensa_smp.c
index f883b1ce7..c49146d78 100644
--- a/src/target/espressif/esp_xtensa_smp.c
+++ b/src/target/espressif/esp_xtensa_smp.c
@@ -94,8 +94,11 @@ int esp_xtensa_smp_soft_reset_halt(struct target *target)
LOG_TARGET_DEBUG(target, "begin");
/* in SMP mode we need to ensure that at first we reset SOC on PRO-CPU
and then call xtensa_assert_reset() for all cores */
- if (target->smp && target->coreid != 0)
- return ERROR_OK;
+ if (target->smp) {
+ head = list_first_entry(target->smp_targets, struct target_list, lh);
+ if (head->target != target)
+ return ERROR_OK;
+ }
/* Reset the SoC first */
if (esp_xtensa_smp->chip_ops->reset) {
res = esp_xtensa_smp->chip_ops->reset(target);
-----------------------------------------------------------------------
Summary of changes:
src/target/espressif/esp_xtensa_smp.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2024-03-02 11:03:45
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from 179169268ca1bbac092324f597fbea090d75355e (commit)
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commit 56a7925a1d2d890adbb5dbd76542bfe901620103
Author: Luca Rufer <luc...@gm...>
Date: Thu Feb 8 21:59:47 2024 +0100
src/jtag/drivers/mpsse: Add support for new FTDI chip types.
The new FTDI ICs with USB-C Support have different bcdDevice
identifiers. The added bcdDevice identifiers are taken from
the chips datasheet, respectively. The patch was tested with
a FT4232HP IC.
The used bcdDevice IDs can be found in Section 8.1 of the respective
Datasheets:
https://ftdichip.com/wp-content/uploads/2023/09/DS_FT233HP-v1.4.pdf
https://ftdichip.com/wp-content/uploads/2023/09/DS_FT2233HP-v1.4.pdf
https://ftdichip.com/wp-content/uploads/2023/09/DS_FT4233HP-v1.5.pdf
Change-Id: I701083cb72030e398ce1c74310676e13895a77ff
Signed-off-by: Luca Rufer <luc...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8134
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/mpsse.c b/src/jtag/drivers/mpsse.c
index 41a8b6e33..f3499e386 100644
--- a/src/jtag/drivers/mpsse.c
+++ b/src/jtag/drivers/mpsse.c
@@ -265,6 +265,24 @@ static bool open_matching_device(struct mpsse_ctx *ctx, const uint16_t vids[], c
case 0x900:
ctx->type = TYPE_FT232H;
break;
+ case 0x2800:
+ ctx->type = TYPE_FT2233HP;
+ break;
+ case 0x2900:
+ ctx->type = TYPE_FT4233HP;
+ break;
+ case 0x3000:
+ ctx->type = TYPE_FT2232HP;
+ break;
+ case 0x3100:
+ ctx->type = TYPE_FT4232HP;
+ break;
+ case 0x3200:
+ ctx->type = TYPE_FT233HP;
+ break;
+ case 0x3300:
+ ctx->type = TYPE_FT232HP;
+ break;
default:
LOG_ERROR("unsupported FTDI chip type: 0x%04x", desc.bcdDevice);
goto error;
diff --git a/src/jtag/drivers/mpsse.h b/src/jtag/drivers/mpsse.h
index a017aff00..e92a9bb56 100644
--- a/src/jtag/drivers/mpsse.h
+++ b/src/jtag/drivers/mpsse.h
@@ -24,6 +24,12 @@ enum ftdi_chip_type {
TYPE_FT2232H,
TYPE_FT4232H,
TYPE_FT232H,
+ TYPE_FT2233HP,
+ TYPE_FT4233HP,
+ TYPE_FT2232HP,
+ TYPE_FT4232HP,
+ TYPE_FT233HP,
+ TYPE_FT232HP,
};
struct mpsse_ctx;
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/mpsse.c | 18 ++++++++++++++++++
src/jtag/drivers/mpsse.h | 6 ++++++
2 files changed, 24 insertions(+)
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From: openocd-gerrit <ope...@us...> - 2024-02-24 13:41:37
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from 33573cda4aa5685b32c44a81b1f2d84a28d78810 (commit)
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- Log -----------------------------------------------------------------
commit 179169268ca1bbac092324f597fbea090d75355e
Author: SydMontague <syd...@ph...>
Date: Fri Feb 2 12:12:48 2024 +0100
jtag/commands: fixed buffer overflow
When performing a command queue allocation larger than the default page
size of 1MiB any subsequent allocations will run into an integer under-
flow when checking for the remaining memory left in the current page.
Causing the function returning a pointer past the end of the buffer and
thus creating a buffer overflow.
This has been observed to cause some transfers to Efinix FPGAs to fail,
because another buffer can get corrupted in the process, causing its
respective free() to fail.
Change-Id: Ic5a0e1774e2dbd58f1a05127f14816c8251a7d9c
Signed-off-by: SydMontague <syd...@ph...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8126
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/jtag/commands.c b/src/jtag/commands.c
index c36c21923..a60684c88 100644
--- a/src/jtag/commands.c
+++ b/src/jtag/commands.c
@@ -103,7 +103,7 @@ void *cmd_queue_alloc(size_t size)
if (*p_page) {
p_page = &cmd_queue_pages_tail;
- if (CMD_QUEUE_PAGE_SIZE - (*p_page)->used < size)
+ if (CMD_QUEUE_PAGE_SIZE < (*p_page)->used + size)
p_page = &((*p_page)->next);
}
-----------------------------------------------------------------------
Summary of changes:
src/jtag/commands.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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From: openocd-gerrit <ope...@us...> - 2024-02-24 13:38:21
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 33573cda4aa5685b32c44a81b1f2d84a28d78810 (commit)
from b6ee13720688a9860f3397bb89ea171b0fc5ccce (commit)
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- Log -----------------------------------------------------------------
commit 33573cda4aa5685b32c44a81b1f2d84a28d78810
Author: Sevan Janiyan <ven...@ge...>
Date: Sat Jan 27 21:53:11 2024 +0000
src/target/riscv: Help older compilers
find members of a union, nested in struct.
Allows file to be compiled with GCC 4.0
Signed-off-by: Sevan Janiyan <ven...@ge...>
Change-Id: Ied68668d3b5f811573a20e11e83aceff268963eb
Reviewed-on: https://review.openocd.org/c/openocd/+/8120
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index d895ca372..9cd4922d2 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -3851,7 +3851,7 @@ int riscv_init_registers(struct target *target)
.type = REG_TYPE_ARCH_DEFINED,
.id = "FPU_FD",
.type_class = REG_TYPE_CLASS_UNION,
- .reg_type_union = &single_double_union
+ { .reg_type_union = &single_double_union }
};
static struct reg_data_type type_uint8 = { .type = REG_TYPE_UINT8, .id = "uint8" };
static struct reg_data_type type_uint16 = { .type = REG_TYPE_UINT16, .id = "uint16" };
-----------------------------------------------------------------------
Summary of changes:
src/target/riscv/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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From: openocd-gerrit <ope...@us...> - 2024-02-18 18:42:12
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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit b6ee13720688a9860f3397bb89ea171b0fc5ccce
Author: Kirill Radkin <kir...@sy...>
Date: Fri Jun 16 12:09:32 2023 +0300
driver: Add additional check for count of BYPASS devices
At least one TAP shouldn't be in BYPASS mode
Change-Id: Ic882acbfc9b6a9f4b0c3bb4741a49f3981503c8c
Signed-off-by: Kirill Radkin <kir...@sy...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7741
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/driver.c b/src/jtag/drivers/driver.c
index fae2aad22..e52816d3a 100644
--- a/src/jtag/drivers/driver.c
+++ b/src/jtag/drivers/driver.c
@@ -116,12 +116,21 @@ int interface_jtag_add_dr_scan(struct jtag_tap *active, int in_num_fields,
/* count devices in bypass */
size_t bypass_devices = 0;
+ size_t all_devices = 0;
for (struct jtag_tap *tap = jtag_tap_next_enabled(NULL); tap; tap = jtag_tap_next_enabled(tap)) {
+ all_devices++;
+
if (tap->bypass)
bypass_devices++;
}
+ if (all_devices == bypass_devices) {
+ LOG_ERROR("At least one TAP shouldn't be in BYPASS mode");
+
+ return ERROR_FAIL;
+ }
+
struct jtag_command *cmd = cmd_queue_alloc(sizeof(struct jtag_command));
struct scan_command *scan = cmd_queue_alloc(sizeof(struct scan_command));
struct scan_field *out_fields = cmd_queue_alloc((in_num_fields + bypass_devices) * sizeof(struct scan_field));
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/driver.c | 9 +++++++++
1 file changed, 9 insertions(+)
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