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From: openocd-gerrit <ope...@us...> - 2024-06-15 14:25:30
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via bf4be566a7e7f510977533a0402716d92f208f95 (commit)
via 9bc7a381b26703f38752771b924fe1c4b918b23d (commit)
from 7e4c9609ca9dfd2734f59d6261d2681b2211283b (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit bf4be566a7e7f510977533a0402716d92f208f95
Author: Daniel Anselmi <dan...@gm...>
Date: Mon Feb 19 23:22:19 2024 +0100
pld: small documentation fixes.
Change-Id: I969f51c38fc0c34c6bdba98b0e618d7f28ea4052
Signed-off-by: Daniel Anselmi <dan...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8084
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 03fa94466..e46e6004b 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -8799,8 +8799,8 @@ The file format must be inferred by the driver.
@section PLD/FPGA Drivers, Options, and Commands
-Drivers may support PLD-specific options to the @command{pld device}
-definition command, and may also define commands usable only with
+Drivers may support PLD-specific options to the @command{pld create}
+command, and may also define commands usable only with
that particular type of PLD.
@deffn {FPGA Driver} {virtex2} [@option{-no_jstart}]
@@ -8888,7 +8888,7 @@ For the option @option{-family} @var{name} is one of @var{trion|titanium}.
@deffn {FPGA Driver} {intel} @option{-family} <name>
This driver can be used to load the bitstream into Intel (former Altera) FPGAs.
-The families Cyclone III, Cyclone IV, Cyclone V, Cyclone 10, Arria II are supported.
+The families Cyclone III, Cyclone IV, Cyclone V, Cyclone 10 and Arria II are supported.
@c Arria V and Arria 10, MAX II, MAX V, MAX10)
The option @option{-family} @var{name} is one of @var{cycloneiii cycloneiv cyclonev cyclone10 arriaii}.
commit 9bc7a381b26703f38752771b924fe1c4b918b23d
Author: Daniel Anselmi <dan...@gm...>
Date: Mon Feb 19 23:22:19 2024 +0100
pld/intel: remove idcodes from intel.c
Remove list of id codes for all families.
Maintain a list with id, bscan-length and check position
in the tcl config files for each family.
The Intel FPGA Driver option 'family' is not otional anymore.
Change-Id: I9a40a041069e84f6b4728f2cd715756a36759c89
Signed-off-by: Daniel Anselmi <dan...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8083
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 8c9f3ff84..03fa94466 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -8886,13 +8886,12 @@ For the option @option{-family} @var{name} is one of @var{trion|titanium}.
@end deffn
-@deffn {FPGA Driver} {intel} [@option{-family} <name>]
+@deffn {FPGA Driver} {intel} @option{-family} <name>
This driver can be used to load the bitstream into Intel (former Altera) FPGAs.
The families Cyclone III, Cyclone IV, Cyclone V, Cyclone 10, Arria II are supported.
@c Arria V and Arria 10, MAX II, MAX V, MAX10)
-For the option @option{-family} @var{name} is one of @var{cycloneiii cycloneiv cyclonev cyclone10 arriaii}.
-This is needed when the JTAG ID of the device is ambiguous (same ID is used for chips in different families).
+The option @option{-family} @var{name} is one of @var{cycloneiii cycloneiv cyclonev cyclone10 arriaii}.
As input file format the driver supports a '.rbf' (raw bitstream file) file. The '.rbf' file can be generated
from a '.sof' file with @verb{|quartus_cpf -c blinker.sof blinker.rbf|}
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index 799552901..1a4c4b774 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -760,8 +760,9 @@ static const struct command_registration jtag_subcommand_handlers[] = {
.mode = COMMAND_EXEC,
.handler = handle_jtag_configure,
.help = "Return any Tcl handler for the specified "
- "TAP event.",
- .usage = "tap_name '-event' event_name",
+ "TAP event or the value of the IDCODE found in hardware.",
+ .usage = "tap_name '-event' event_name | "
+ "tap_name '-idcode'",
},
{
.name = "names",
diff --git a/src/pld/intel.c b/src/pld/intel.c
index fe85cd62c..a4bdabe26 100644
--- a/src/pld/intel.c
+++ b/src/pld/intel.c
@@ -37,142 +37,11 @@ struct intel_pld_device {
enum intel_family_e family;
};
-struct intel_device_parameters_elem {
- uint32_t id;
- unsigned int boundary_scan_length;
- int checkpos;
- enum intel_family_e family;
-};
-
-static const struct intel_device_parameters_elem intel_device_parameters[] = {
- {0x020f10dd, 603, 226, INTEL_CYCLONEIII}, /* EP3C5 EP3C10 */
- {0x020f20dd, 1080, 409, INTEL_CYCLONEIII}, /* EP3C16 */
- {0x020f30dd, 732, 286, INTEL_CYCLONEIII}, /* EP3C25 */
- {0x020f40dd, 1632, 604, INTEL_CYCLONEIII}, /* EP3C40 */
- {0x020f50dd, 1164, 442, INTEL_CYCLONEIII}, /* EP3C55 */
- {0x020f60dd, 1314, 502, INTEL_CYCLONEIII}, /* EP3C80 */
- {0x020f70dd, 1620, 613, INTEL_CYCLONEIII}, /* EP3C120*/
- {0x027010dd, 1314, 226, INTEL_CYCLONEIII}, /* EP3CLS70 */
- {0x027000dd, 1314, 226, INTEL_CYCLONEIII}, /* EP3CLS100 */
- {0x027030dd, 1314, 409, INTEL_CYCLONEIII}, /* EP3CLS150 */
- {0x027020dd, 1314, 409, INTEL_CYCLONEIII}, /* EP3CLS200 */
-
- {0x020f10dd, 603, 226, INTEL_CYCLONEIV}, /* EP4CE6 EP4CE10 */
- {0x020f20dd, 1080, 409, INTEL_CYCLONEIV}, /* EP4CE15 */
- {0x020f30dd, 732, 286, INTEL_CYCLONEIV}, /* EP4CE22 */
- {0x020f40dd, 1632, 604, INTEL_CYCLONEIV}, /* EP4CE30 EP4CE40 */
- {0x020f50dd, 1164, 442, INTEL_CYCLONEIV}, /* EP4CE55 */
- {0x020f60dd, 1314, 502, INTEL_CYCLONEIV}, /* EP4CE75 */
- {0x020f70dd, 1620, 613, INTEL_CYCLONEIV}, /* EP4CE115 */
- {0x028010dd, 260, 229, INTEL_CYCLONEIV}, /* EP4CGX15 */
- {0x028120dd, 494, 463, INTEL_CYCLONEIV}, /* EP4CGX22 */
- {0x028020dd, 494, 463, INTEL_CYCLONEIV}, /* EP4CGX30 */
- {0x028230dd, 1006, 943, INTEL_CYCLONEIV}, /* EP4CGX30 */
- {0x028130dd, 1006, 943, INTEL_CYCLONEIV}, /* EP4CGX50 */
- {0x028030dd, 1006, 943, INTEL_CYCLONEIV}, /* EP4CGX75 */
- {0x028140dd, 1495, 1438, INTEL_CYCLONEIV}, /* EP4CGX110 */
- {0x028040dd, 1495, 1438, INTEL_CYCLONEIV}, /* EP4CGX150 */
-
- {0x02b150dd, 864, 163, INTEL_CYCLONEV}, /* 5CEBA2F23 5CEBA2F17 5CEFA2M13 5CEFA2F23 5CEBA2U15 5CEFA2U19 5CEBA2U19 */
- {0x02d020dd, 1485, 19, INTEL_CYCLONEV}, /* 5CSXFC6D6F31 5CSTFD6D5F31 5CSEBA6U23 5CSEMA6U23 5CSEBA6U19 5CSEBA6U23
- 5CSEBA6U19 5CSEMA6F31 5CSXFC6C6U23 */
- {0x02b040dd, 1728, -1, INTEL_CYCLONEV}, /* 5CGXFC9EF35 5CGXBC9AU19 5CGXBC9CF23 5CGTFD9CF23 5CGXFC9AU19 5CGXFC9CF23
- 5CGXFC9EF31 5CGXFC9DF27 5CGXBC9DF27 5CGXBC9EF31 5CGTFD9EF31 5CGTFD9EF35
- 5CGTFD9AU19 5CGXBC9EF35 5CGTFD9DF27 */
- {0x02b050dd, 864, 163, INTEL_CYCLONEV}, /* 5CEFA4U19 5CEFA4F23 5CEFA4M13 5CEBA4F17 5CEBA4U15 5CEBA4U19 5CEBA4F23 */
- {0x02b030dd, 1488, 19, INTEL_CYCLONEV}, /* 5CGXBC7CU19 5CGTFD7CU19 5CGTFD7DF27 5CGXFC7BM15 5CGXFC7DF27 5CGXFC7DF31
- 5CGTFD7CF23 5CGXBC7CF23 5CGXBC7DF31 5CGTFD7BM15 5CGXFC7CU19 5CGTFD7DF31
- 5CGXBC7BM15 5CGXFC7CF23 5CGXBC7DF27 */
- {0x02d120dd, 1485, -1, INTEL_CYCLONEV}, /* 5CSEBA5U23 5CSEBA5U23 5CSTFD5D5F31 5CSEBA5U19 5CSXFC5D6F31 5CSEMA5U23
- 5CSEMA5F31 5CSXFC5C6U23 5CSEBA5U19 */
- {0x02b220dd, 1104, 19, INTEL_CYCLONEV}, /* 5CEBA5U19 5CEFA5U19 5CEFA5M13 5CEBA5F23 5CEFA5F23 */
- {0x02b020dd, 1104, 19, INTEL_CYCLONEV}, /* 5CGXBC5CU19 5CGXFC5F6M11 5CGXFC5CM13 5CGTFD5CF23 5CGXBC5CF23 5CGTFD5CF27
- 5CGTFD5F5M11 5CGXFC5CF27 5CGXFC5CU19 5CGTFD5CM13 5CGXFC5CF23 5CGXBC5CF27
- 5CGTFD5CU19 */
- {0x02d010dd, 1197, -1, INTEL_CYCLONEV}, /* 5CSEBA4U23 5CSXFC4C6U23 5CSEMA4U23 5CSEBA4U23 5CSEBA4U19 5CSEBA4U19
- 5CSXFC2C6U23 */
- {0x02b120dd, 1104, 19, INTEL_CYCLONEV}, /* 5CGXFC4CM13 5CGXFC4CU19 5CGXFC4F6M11 5CGXBC4CU19 5CGXFC4CF27 5CGXBC4CF23
- 5CGXBC4CF27 5CGXFC4CF23 */
- {0x02b140dd, 1728, -1, INTEL_CYCLONEV}, /* 5CEFA9F31 5CEBA9F31 5CEFA9F27 5CEBA9U19 5CEBA9F27 5CEFA9U19 5CEBA9F23
- 5CEFA9F23 */
- {0x02b010dd, 720, 19, INTEL_CYCLONEV}, /* 5CGXFC3U15 5CGXBC3U15 5CGXFC3F23 5CGXFC3U19 5CGXBC3U19 5CGXBC3F23 */
- {0x02b130dd, 1488, 19, INTEL_CYCLONEV}, /* 5CEFA7F31 5CEBA7F27 5CEBA7M15 5CEFA7U19 5CEBA7F23 5CEFA7F23 5CEFA7F27
- 5CEFA7M15 5CEBA7U19 5CEBA7F31 */
- {0x02d110dd, 1197, -1, INTEL_CYCLONEV}, /* 5CSEBA2U23 5CSEMA2U23 5CSEBA2U23 5CSEBA2U19 5CSEBA2U19 */
-
- {0x020f10dd, 603, 226, INTEL_CYCLONE10}, /* 10CL006E144 10CL006U256 10CL010M164 10CL010U256 10CL010E144 */
- {0x020f20dd, 1080, 409, INTEL_CYCLONE10}, /* 10CL016U256 10CL016E144 10CL016U484 10CL016F484 10CL016M164 */
- {0x020f30dd, 732, 286, INTEL_CYCLONE10}, /* 10CL025U256 10CL025E144 */
- {0x020f40dd, 1632, 604, INTEL_CYCLONE10}, /* 10CL040F484 10CL040U484 */
- {0x020f50dd, 1164, 442, INTEL_CYCLONE10}, /* 10CL055F484 10CL055U484 */
- {0x020f60dd, 1314, 502, INTEL_CYCLONE10}, /* 10CL080F484 10CL080F780 10CL080U484 */
- {0x020f70dd, 1620, 613, INTEL_CYCLONE10}, /* 10CL120F484 10CL120F780 */
-
- {0x02e120dd, 1339, -1, INTEL_CYCLONE10}, /* 10CX085U484 10CX085F672 */
- {0x02e320dd, 1339, -1, INTEL_CYCLONE10}, /* 10CX105F780 10CX105U484 10CX105F672 */
- {0x02e720dd, 1339, -1, INTEL_CYCLONE10}, /* 10CX150F672 10CX150F780 10CX150U484 */
- {0x02ef20dd, 1339, -1, INTEL_CYCLONE10}, /* 10CX220F672 10CX220F780 10CX220U484 */
-
- {0x025120dd, 1227, 1174, INTEL_ARRIAII}, /* EP2AGX45 */
- {0x025020dd, 1227, -1, INTEL_ARRIAII}, /* EP2AGX65 */
- {0x025130dd, 1467, -1, INTEL_ARRIAII}, /* EP2AGX95 */
- {0x025030dd, 1467, -1, INTEL_ARRIAII}, /* EP2AGX125 */
- {0x025140dd, 1971, -1, INTEL_ARRIAII}, /* EP2AGX190 */
- {0x025040dd, 1971, -1, INTEL_ARRIAII}, /* EP2AGX260 */
- {0x024810dd, 2274, -1, INTEL_ARRIAII}, /* EP2AGZ225 */
- {0x0240a0dd, 2682, -1, INTEL_ARRIAII}, /* EP2AGZ300 */
- {0x024820dd, 2682, -1, INTEL_ARRIAII}, /* EP2AGZ350 */
-};
-
-static int intel_fill_device_parameters(struct intel_pld_device *intel_info)
-{
- for (size_t i = 0; i < ARRAY_SIZE(intel_device_parameters); ++i) {
- if (intel_device_parameters[i].id == intel_info->tap->idcode &&
- intel_info->family == intel_device_parameters[i].family) {
- if (intel_info->boundary_scan_length == 0)
- intel_info->boundary_scan_length = intel_device_parameters[i].boundary_scan_length;
-
- if (intel_info->checkpos == -1)
- intel_info->checkpos = intel_device_parameters[i].checkpos;
-
- return ERROR_OK;
- }
- }
-
- return ERROR_FAIL;
-}
-
-static int intel_check_for_unique_id(struct intel_pld_device *intel_info)
-{
- int found = 0;
- for (size_t i = 0; i < ARRAY_SIZE(intel_device_parameters); ++i) {
- if (intel_device_parameters[i].id == intel_info->tap->idcode) {
- ++found;
- intel_info->family = intel_device_parameters[i].family;
- }
- }
-
- return (found == 1) ? ERROR_OK : ERROR_FAIL;
-}
-
static int intel_check_config(struct intel_pld_device *intel_info)
{
- if (!intel_info->tap->has_idcode) {
- LOG_ERROR("no IDCODE");
- return ERROR_FAIL;
- }
-
- if (intel_info->family == INTEL_UNKNOWN) {
- if (intel_check_for_unique_id(intel_info) != ERROR_OK) {
- LOG_ERROR("id is ambiguous, please specify family");
+ if (intel_info->boundary_scan_length == 0) {
+ LOG_ERROR("unknown boundary scan length. Please specify with 'intel set_bscan'.");
return ERROR_FAIL;
- }
- }
-
- if (intel_info->boundary_scan_length == 0 || intel_info->checkpos == -1) {
- int ret = intel_fill_device_parameters(intel_info);
- if (ret != ERROR_OK)
- return ret;
}
if (intel_info->checkpos >= 0 && (unsigned int)intel_info->checkpos >= intel_info->boundary_scan_length) {
@@ -305,6 +174,8 @@ static int intel_load(struct pld_device *pld_device, const char *filename)
LOG_ERROR("Check failed");
return ERROR_FAIL;
}
+ } else {
+ LOG_INFO("unable to check. Please specify with position 'intel set_check_pos'.");
}
retval = intel_set_instr(tap, 0x003);
@@ -417,7 +288,7 @@ COMMAND_HANDLER(intel_set_check_pos_command_handler)
PLD_CREATE_COMMAND_HANDLER(intel_pld_create_command)
{
- if (CMD_ARGC != 4 && CMD_ARGC != 6)
+ if (CMD_ARGC != 6)
return ERROR_COMMAND_SYNTAX_ERROR;
if (strcmp(CMD_ARGV[2], "-chain-position") != 0)
@@ -430,24 +301,23 @@ PLD_CREATE_COMMAND_HANDLER(intel_pld_create_command)
}
enum intel_family_e family = INTEL_UNKNOWN;
- if (CMD_ARGC == 6) {
- if (strcmp(CMD_ARGV[4], "-family") != 0)
- return ERROR_COMMAND_SYNTAX_ERROR;
-
- if (strcmp(CMD_ARGV[5], "cycloneiii") == 0) {
- family = INTEL_CYCLONEIII;
- } else if (strcmp(CMD_ARGV[5], "cycloneiv") == 0) {
- family = INTEL_CYCLONEIV;
- } else if (strcmp(CMD_ARGV[5], "cyclonev") == 0) {
- family = INTEL_CYCLONEV;
- } else if (strcmp(CMD_ARGV[5], "cyclone10") == 0) {
- family = INTEL_CYCLONE10;
- } else if (strcmp(CMD_ARGV[5], "arriaii") == 0) {
- family = INTEL_ARRIAII;
- } else {
- command_print(CMD, "unknown family");
- return ERROR_FAIL;
- }
+
+ if (strcmp(CMD_ARGV[4], "-family") != 0)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ if (strcmp(CMD_ARGV[5], "cycloneiii") == 0) {
+ family = INTEL_CYCLONEIII;
+ } else if (strcmp(CMD_ARGV[5], "cycloneiv") == 0) {
+ family = INTEL_CYCLONEIV;
+ } else if (strcmp(CMD_ARGV[5], "cyclonev") == 0) {
+ family = INTEL_CYCLONEV;
+ } else if (strcmp(CMD_ARGV[5], "cyclone10") == 0) {
+ family = INTEL_CYCLONE10;
+ } else if (strcmp(CMD_ARGV[5], "arriaii") == 0) {
+ family = INTEL_ARRIAII;
+ } else {
+ command_print(CMD, "unknown family");
+ return ERROR_FAIL;
}
struct intel_pld_device *intel_info = malloc(sizeof(struct intel_pld_device));
diff --git a/tcl/fpga/altera-arriaii.cfg b/tcl/fpga/altera-arriaii.cfg
index d59c18207..9cf680d5f 100644
--- a/tcl/fpga/altera-arriaii.cfg
+++ b/tcl/fpga/altera-arriaii.cfg
@@ -21,11 +21,26 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME arriaii
}
-jtag newtap $_CHIPNAME tap -irlen 10 \
- -expected-id 0x025120dd -expected-id 0x025040dd \
- -expected-id 0x025020dd -expected-id 0x024810dd \
- -expected-id 0x025130dd -expected-id 0x0240a0dd \
- -expected-id 0x025030dd -expected-id 0x024820dd \
- -expected-id 0x025140dd
+array set _ARRIA_2_DATA {
+ 0x025120dd {1227 1174 EP2AGX45}
+ 0x025020dd {1227 -1 EP2AGX65}
+ 0x025130dd {1467 -1 EP2AGX95}
+ 0x025030dd {1467 -1 EP2AGX125}
+ 0x025140dd {1971 -1 EP2AGX190}
+ 0x025040dd {1971 -1 EP2AGX260}
+ 0x024810dd {2274 -1 EP2AGZ225}
+ 0x0240a0dd {2682 -1 EP2AGZ300}
+ 0x024820dd {2682 -1 EP2AGZ350}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _ARRIA_2_DATA] {
+ set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family arriaii
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_ARRIA_2_DATA}"
+
diff --git a/tcl/fpga/altera-cyclone10.cfg b/tcl/fpga/altera-cyclone10.cfg
index 3a1bc1f65..0898c74e1 100644
--- a/tcl/fpga/altera-cyclone10.cfg
+++ b/tcl/fpga/altera-cyclone10.cfg
@@ -4,31 +4,33 @@
# see: https://www.intel.com/content/www/us/en/docs/programmable/683777/current/bst-operation-control.html
# and: https://www.intel.cn/content/dam/support/us/en/programmable/kdb/pdfs/literature/hb/cyclone-10/c10gx-51003.pdf
-# GX085: 0x02e120dd
-# GX105: 0x02e320dd
-# GX150: 0x02e720dd
-# GX220: 0x02ef20dd
-# 10cl006: 0x020f10dd
-# 10cl010: 0x020f10dd
-# 10cl016: 0x020f20dd
-# 10cl025: 0x020f30dd
-# 10cl040: 0x020f40dd
-# 10cl055: 0x020f50dd
-# 10cl080: 0x020f60dd
-# 10cl120: 0x020f70dd
-
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME cyclone10
}
-jtag newtap $_CHIPNAME tap -irlen 10 \
- -expected-id 0x02e720dd -expected-id 0x02e120dd \
- -expected-id 0x02ef20dd -expected-id 0x02e320dd \
- -expected-id 0x020f10dd -expected-id 0x020f20dd \
- -expected-id 0x020f30dd -expected-id 0x020f40dd \
- -expected-id 0x020f50dd -expected-id 0x020f60dd \
- -expected-id 0x020f70dd
+array set _CYCLONE_10_DATA {
+ 0x020f10dd { 603 226 10cl006_10cl010}
+ 0x020f20dd {1080 409 10cl016}
+ 0x020f30dd { 732 286 10cl025}
+ 0x020f40dd {1632 604 10cl040}
+ 0x020f50dd {1164 442 10cl055}
+ 0x020f60dd {1314 502 10cl080}
+ 0x020f70dd {1620 613 10cl120}
+ 0x02e120dd {1339 -1 GX085}
+ 0x02e320dd {1339 -1 GX105}
+ 0x02e720dd {1339 -1 GX150}
+ 0x02ef20dd {1339 -1 GX220}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLONE_10_DATA] {
+ set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
-pld device intel $_CHIPNAME.tap cyclone10
+pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclone10
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_10_DATA}"
diff --git a/tcl/fpga/altera-cycloneiii.cfg b/tcl/fpga/altera-cycloneiii.cfg
index d9be6455d..b0da418c0 100644
--- a/tcl/fpga/altera-cycloneiii.cfg
+++ b/tcl/fpga/altera-cycloneiii.cfg
@@ -4,32 +4,33 @@
# see Cyclone III Device Handbook
# Table 12-2: Device IDCODE for Cyclone III Device Family
-#EP3C5 0x020f10dd
-#EP3C10 0x020f10dd
-#EP3C16 0x020f20dd
-#EP3C25 0x020f30dd
-#EP3C40 0x020f40dd
-#EP3C55 0x020f50dd
-#EP3C80 0x020f60dd
-#EP3C120 0x020f70dd
-#Cyclone III LS
-#EP3CLS70 0x027010dd
-#EP3CLS100 0x027000dd
-#EP3CLS150 0x027030dd
-#EP3CLS200 0x027020dd
-
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME cycloneiii
}
-jtag newtap $_CHIPNAME tap -irlen 10 \
- -expected-id 0x020f10dd -expected-id 0x020f20dd \
- -expected-id 0x020f30dd -expected-id 0x020f40dd \
- -expected-id 0x020f50dd -expected-id 0x020f60dd \
- -expected-id 0x020f70dd -expected-id 0x027010dd \
- -expected-id 0x027000dd -expected-id 0x027030dd \
- -expected-id 0x027020dd
+array set _CYCLONE_3_DATA {
+ 0x020f10dd { 603 226 EP3C5_EP3C10}
+ 0x020f20dd {1080 409 EP3C16}
+ 0x020f30dd { 732 286 EP3C25}
+ 0x020f40dd {1632 604 EP3C40}
+ 0x020f50dd {1164 442 EP3C55}
+ 0x020f60dd {1314 502 EP3C80}
+ 0x020f70dd {1620 613 EP3C120}
+ 0x027010dd {1314 226 EP3CLS70}
+ 0x027000dd {1314 226 EP3CLS100}
+ 0x027030dd {1314 409 EP3CLS150}
+ 0x027020dd {1314 409 EP3CLS200}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLONE_3_DATA] {
+ set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiii
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_3_DATA}"
diff --git a/tcl/fpga/altera-cycloneiv.cfg b/tcl/fpga/altera-cycloneiv.cfg
index 6a908e8af..44eb89dec 100644
--- a/tcl/fpga/altera-cycloneiv.cfg
+++ b/tcl/fpga/altera-cycloneiv.cfg
@@ -4,38 +4,37 @@
# see Cyclone IV Device Handbook
# Table 10-2: IDCODE Information for 32-Bit Cyclone IV Devices
-#EP4CE6 0x020f10dd
-#EP4CE10 0x020f10dd
-#EP4CE15 0x020f20dd
-#EP4CE22 0x020f30dd
-#EP4CE30 0x020f40dd
-#EP4CE40 0x020f40dd
-#EP4CE55 0x020f50dd
-#EP4CE75 0x020f60dd
-#EP4CE115 0x020f70dd
-#EP4CGX15 0x028010dd
-#EP4CGX22 0x028120dd
-#EP4CGX30 (3) 0x028020dd
-#EP4CGX30 (4) 0x028230dd
-#EP4CGX50 0x028130dd
-#EP4CGX75 0x028030dd
-#EP4CGX110 0x028140dd
-#EP4CGX150 0x028040dd
-
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME cycloneiv
}
-jtag newtap $_CHIPNAME tap -irlen 10 \
- -expected-id 0x020f10dd -expected-id 0x020f20dd \
- -expected-id 0x020f30dd -expected-id 0x020f40dd \
- -expected-id 0x020f50dd -expected-id 0x020f60dd \
- -expected-id 0x020f70dd -expected-id 0x028010dd \
- -expected-id 0x028120dd -expected-id 0x028020dd \
- -expected-id 0x028230dd -expected-id 0x028130dd \
- -expected-id 0x028030dd -expected-id 0x028140dd \
- -expected-id 0x028040dd
+array set _CYCLON_4_DATA {
+ 0x020f10dd { 603 226 EP4CE6_EP4CE10}
+ 0x020f20dd {1080 409 EP4CE15}
+ 0x020f30dd { 732 286 EP4CE22}
+ 0x020f40dd {1632 604 EP4CE30_EP4CE40}
+ 0x020f50dd {1164 442 EP4CE55}
+ 0x020f60dd {1314 502 EP4CE75}
+ 0x020f70dd {1620 613 EP4CE115}
+ 0x028010dd { 260 229 EP4CGX15}
+ 0x028120dd { 494 463 EP4CGX22}
+ 0x028020dd { 494 463 EP4CGX30}
+ 0x028230dd {1006 943 EP4CGX30}
+ 0x028130dd {1006 943 EP4CGX50}
+ 0x028030dd {1006 943 EP4CGX75}
+ 0x028140dd {1495 1438 EP4CGX110}
+ 0x028040dd {1495 1438 EP4CGX150}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLON_4_DATA] {
+ set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cycloneiv
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_4_DATA}"
diff --git a/tcl/fpga/altera-cyclonev.cfg b/tcl/fpga/altera-cyclonev.cfg
index 46532a556..8d19cd8de 100644
--- a/tcl/fpga/altera-cyclonev.cfg
+++ b/tcl/fpga/altera-cyclonev.cfg
@@ -4,44 +4,36 @@
# see Cyclone V Device Handbook
# Table 9-1: IDCODE Information for Cyclone V Devices
-#5CEA2 0x02b150dd
-#5CEA4 0x02b050dd
-#5CEA5 0x02b220dd
-#5CEA7 0x02b130dd
-#5CEA9 0x02b140dd
-#5CGXC3 0x02b010dd
-#5CGXC4 0x02b120dd
-#5CGXC5 0x02b020dd
-#5CGXC7 0x02b030dd
-#5CGXC9 0x02b040dd
-#5CGTD5 0x02b020dd
-#5CGTD7 0x02b030dd
-#5CGTD9 0x02b040dd
-#5CSEA2 0x02d110dd
-#5CSEA4 0x02d010dd
-#5CSEA5 0x02d120dd
-#5CSEA6 0x02d020dd
-#5CSXC2 0x02d110dd
-#5CSXC4 0x02d010dd
-#5CSXC5 0x02d120dd
-#5CSXC6 0x02d020dd
-#5CSTD5 0x02d120dd
-#5CSTD6 0x02d020dd
-
-
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME cyclonev
}
-jtag newtap $_CHIPNAME tap -irlen 10 \
- -expected-id 0x02b150dd -expected-id 0x02b050dd \
- -expected-id 0x02b220dd -expected-id 0x02b130dd \
- -expected-id 0x02b140dd -expected-id 0x02b010dd \
- -expected-id 0x02b120dd -expected-id 0x02b020dd \
- -expected-id 0x02b030dd -expected-id 0x02b040dd \
- -expected-id 0x02d110dd -expected-id 0x02d010dd \
- -expected-id 0x02d120dd -expected-id 0x02d020dd
+array set _CYCLONE_5_DATA {
+ 0x02b150dd { 864 163 5CEA2}
+ 0x02d020dd {1485 19 5CSEA6_5CSXC6_5CSTD6}
+ 0x02b040dd {1728 -1 5CGXC9_5CGTD9}
+ 0x02b050dd { 864 163 5CEA4}
+ 0x02b030dd {1488 19 5CGXC7_5CGTD7}
+ 0x02d120dd {1485 -1 5CSEA5_5CSXC5_5CSTD5}
+ 0x02b220dd {1104 19 5CEA5}
+ 0x02b020dd {1104 19 5CGXC5_5CGTD5}
+ 0x02d010dd {1197 -1 5CSEA4_5CSXC4}
+ 0x02b120dd {1104 19 5CGXC4}
+ 0x02b140dd {1728 -1 5CEA9}
+ 0x02b010dd { 720 19 5CGXC3}
+ 0x02b130dd {1488 19 5CEA7}
+ 0x02d110dd {1197 -1 5CSEA2_5CSXC2}
+}
+
+set jtag_newtap_cmd {jtag newtap $_CHIPNAME tap -irlen 10 -ignore-version}
+foreach id [array names _CYCLONE_5_DATA] {
+ set cmd [concat "-expected-id" id]
+}
+eval $jtag_newtap_cmd
+
+source [find fpga/altera_common_init.cfg]
pld create $_CHIPNAME.pld intel -chain-position $_CHIPNAME.tap -family cyclonev
+jtag configure $_CHIPNAME.tap -event setup "set_bscan_checkpos_on_setup $_CHIPNAME {$_CYCLONE_5_DATA}"
diff --git a/tcl/fpga/altera_common_init.cfg b/tcl/fpga/altera_common_init.cfg
new file mode 100644
index 000000000..683a844cb
--- /dev/null
+++ b/tcl/fpga/altera_common_init.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+proc set_bscan_checkpos_on_setup {chipname data} {
+ set tapid_w_version [jtag cget $chipname.tap -idcode]
+ set version_mask 0x0fffffff
+ set tapid [format 0x%08x [expr {$tapid_w_version & $version_mask}]]
+ intel set_bscan $chipname.pld [lindex $data($tapid) 0]
+ intel set_check_pos $chipname.pld [lindex $data($tapid) 1]
+}
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 11 ++-
src/jtag/tcl.c | 5 +-
src/pld/intel.c | 174 +++++-----------------------------------
tcl/fpga/altera-arriaii.cfg | 27 +++++--
tcl/fpga/altera-cyclone10.cfg | 44 +++++-----
tcl/fpga/altera-cycloneiii.cfg | 43 +++++-----
tcl/fpga/altera-cycloneiv.cfg | 53 ++++++------
tcl/fpga/altera-cyclonev.cfg | 58 ++++++--------
tcl/fpga/altera_common_init.cfg | 9 +++
9 files changed, 156 insertions(+), 268 deletions(-)
create mode 100644 tcl/fpga/altera_common_init.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2024-06-15 14:25:00
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 7e4c9609ca9dfd2734f59d6261d2681b2211283b (commit)
from b1600bb342e191463094f534f71a4e5d51407e18 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 7e4c9609ca9dfd2734f59d6261d2681b2211283b
Author: Daniel Anselmi <dan...@gm...>
Date: Fri Feb 23 20:49:54 2024 +0100
pld/intel: remove duplicated code
Change-Id: I043d16c77ce97d3e888774747ed6bfc4c7e63c04
Signed-off-by: Daniel Anselmi <dan...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8082
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/pld/intel.c b/src/pld/intel.c
index a39e16c21..fe85cd62c 100644
--- a/src/pld/intel.c
+++ b/src/pld/intel.c
@@ -248,9 +248,6 @@ static int intel_load(struct pld_device *pld_device, const char *filename)
if (retval != ERROR_OK)
return retval;
- if (retval != ERROR_OK)
- return retval;
-
retval = intel_set_instr(tap, 0x002);
if (retval != ERROR_OK) {
free(bit_file.data);
-----------------------------------------------------------------------
Summary of changes:
src/pld/intel.c | 3 ---
1 file changed, 3 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: openocd-gerrit <ope...@us...> - 2024-06-15 14:14:31
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via b1600bb342e191463094f534f71a4e5d51407e18 (commit)
via a420f00d106cb2638bb4c272a4780e05623ea64b (commit)
from ed30c9a572ba8b7e8959f8998ebfeaaa12a37d70 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit b1600bb342e191463094f534f71a4e5d51407e18
Author: George Voicu <raz...@ho...>
Date: Sat Nov 5 11:14:22 2022 +0100
tcl/board: Support for Digilent Nexys 2 board
Support Digilent Nexys 2 board JTAG chain
Signed-off-by: George Voicu <raz...@ho...>
Change-Id: I350f80b49303c4b0402d93ebc120a591ef727551
Reviewed-on: https://review.openocd.org/c/openocd/+/7336
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/board/digilent_nexys2.cfg b/tcl/board/digilent_nexys2.cfg
new file mode 100644
index 000000000..c1c5b2ac6
--- /dev/null
+++ b/tcl/board/digilent_nexys2.cfg
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# https://digilent.com/reference/programmable-logic/nexys-2/start
+#
+# The Digilent Nexy2 normally requires proprietary tools to program and will
+# enumerate as:
+# ID 1443:0005 1443 ONBOARD USB
+#
+# However, the ixo-usb-jtag project provides an alternative open firmware for
+# the on board programmer. When using this firmware the board will then
+# enumerate as:
+# ID 16c0:06ad ixo.de USB-JTAG-IF (With SerialNumber == hw_nexys)
+#
+# See the interface/usb-jtag.cfg for more information.
+
+source [find interface/usb-jtag.cfg]
+source [find cpld/xilinx-xcf-s.cfg]
+source [find fpga/xilinx-xc3s.cfg]
+
+# Usage:
+#
+# Load Bitstream into FPGA:
+# openocd -f board/digilent_nexys2.cfg -c "init;\
+# pld load 0 bitstream.bit;\
+# shutdown"
+
+# Read Unique Device Identifier (DNA):
+# openocd -f board/digilent_nexys2.cfg -c "init;\
+# xilinx_print_dna [xc3s_get_dna xc3s.tap];\
+# shutdown"
commit a420f00d106cb2638bb4c272a4780e05623ea64b
Author: George Voicu <raz...@ho...>
Date: Sat Nov 5 11:08:43 2022 +0100
tcl/fpga: Support for Xilinx Spartan3 series devices
Tap definition for Xilinx Spartan 3/3E/3A/3AN/3A-DSP devices.
Signed-off-by: George Voicu <raz...@ho...>
Change-Id: Ieda2b61fc270840f9192976697fcac259c45e3b8
Reviewed-on: https://review.openocd.org/c/openocd/+/7335
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/tcl/fpga/xilinx-xc3s.cfg b/tcl/fpga/xilinx-xc3s.cfg
new file mode 100644
index 000000000..7c17206c9
--- /dev/null
+++ b/tcl/fpga/xilinx-xc3s.cfg
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Xilinx Spartan3 generation
+# https://www.xilinx.com/support/documentation/user_guides/ug331.pdf
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME xc3s
+}
+
+# Table 12-4 in https://www.xilinx.com/support/documentation/user_guides/ug332.pdf
+# the 4 top bits (28:31) are the die stepping, ignore them.
+jtag newtap $_CHIPNAME tap -irlen 6 -ignore-version \
+ -expected-id 0x02210093 \
+ -expected-id 0x02218093 \
+ -expected-id 0x02220093 \
+ -expected-id 0x02228093 \
+ -expected-id 0x02230093 \
+ -expected-id 0x02610093 \
+ -expected-id 0x02618093 \
+ -expected-id 0x02620093 \
+ -expected-id 0x02628093 \
+ -expected-id 0x02630093 \
+ -expected-id 0x03840093 \
+ -expected-id 0x0384E093 \
+ -expected-id 0x01C10093 \
+ -expected-id 0x01C1A093 \
+ -expected-id 0x01C22093 \
+ -expected-id 0x01C2E093 \
+ -expected-id 0x01C3A093 \
+ -expected-id 0x0140C093 \
+ -expected-id 0x01414093 \
+ -expected-id 0x0141C093 \
+ -expected-id 0x01428093 \
+ -expected-id 0x01434093 \
+ -expected-id 0x01440093 \
+ -expected-id 0x01448093 \
+ -expected-id 0x01450093
+
+pld create $_CHIPNAME.pld virtex2 -chain-position $_CHIPNAME.tap
+
+source [find fpga/xilinx-dna.cfg]
-----------------------------------------------------------------------
Summary of changes:
tcl/board/digilent_nexys2.cfg | 30 ++++++++++++++++++++++++++++++
tcl/{cpld => fpga}/xilinx-xc3s.cfg | 37 ++++++++++++++++++++-----------------
2 files changed, 50 insertions(+), 17 deletions(-)
create mode 100644 tcl/board/digilent_nexys2.cfg
copy tcl/{cpld => fpga}/xilinx-xc3s.cfg (72%)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2024-06-15 14:13:57
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via ed30c9a572ba8b7e8959f8998ebfeaaa12a37d70 (commit)
from b49e03f77ed890b39274d94ae6267bf07a68ba98 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit ed30c9a572ba8b7e8959f8998ebfeaaa12a37d70
Author: George Voicu <raz...@ho...>
Date: Sat Nov 5 10:48:47 2022 +0100
tcl/fpga/xilinx-dna: Support for reading Spartan3 DNA code
Add Xilinx Spartan3 ISC_DNA instruction
Signed-off-by: George Voicu <raz...@ho...>
Change-Id: Iaddb079c9fdd1b91c65def36878fe81783098696
Reviewed-on: https://review.openocd.org/c/openocd/+/7331
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/fpga/xilinx-dna.cfg b/tcl/fpga/xilinx-dna.cfg
index 56f8c1411..6b16b78fb 100644
--- a/tcl/fpga/xilinx-dna.cfg
+++ b/tcl/fpga/xilinx-dna.cfg
@@ -1,7 +1,9 @@
# SPDX-License-Identifier: GPL-2.0-or-later
+# Spartan3: Table 9-5 in https://www.xilinx.com/support/documentation/user_guides/ug332.pdf
proc xilinx_dna_addr {chip} {
array set addrs {
+ Spartan3 0x31
Spartan6 0x30
Series7 0x17
}
@@ -43,3 +45,7 @@ proc xc7_get_dna {tap} {
proc xc6s_get_dna {tap} {
return [xilinx_get_dna $tap Spartan6]
}
+
+proc xc3s_get_dna {tap} {
+ return [xilinx_get_dna $tap Spartan3]
+}
-----------------------------------------------------------------------
Summary of changes:
tcl/fpga/xilinx-dna.cfg | 6 ++++++
1 file changed, 6 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
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From: openocd-gerrit <ope...@us...> - 2024-06-15 14:12:47
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via b49e03f77ed890b39274d94ae6267bf07a68ba98 (commit)
from 400cf213c05d17cede4dca4787a5533959bd2183 (commit)
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- Log -----------------------------------------------------------------
commit b49e03f77ed890b39274d94ae6267bf07a68ba98
Author: Antonio Borneo <bor...@gm...>
Date: Sun May 26 12:38:43 2024 +0200
target/arm_tpiu_swo: Fix memory leak on error
In case of fail to allocate 'obj->name', the memory allocated for
'obj->out_filename' is not freed, thus leaking.
Since 'obj' is allocated with calloc(), thus zeroed, switch to use
the common error exit path for both allocations of 'obj->name' and
'obj->out_filename'.
Fixes: 2506ccb50915 ("target/arm_tpiu_swo: Fix division by zero")
Change-Id: I412f66ddd7bf7d260cee495324058482b26ff0c5
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8300
Tested-by: jenkins
Reviewed-by: zapb <de...@za...>
diff --git a/src/target/arm_tpiu_swo.c b/src/target/arm_tpiu_swo.c
index b5a488201..55a977844 100644
--- a/src/target/arm_tpiu_swo.c
+++ b/src/target/arm_tpiu_swo.c
@@ -965,8 +965,7 @@ static int jim_arm_tpiu_swo_create(Jim_Interp *interp, int argc, Jim_Obj *const
obj->out_filename = strdup("external");
if (!obj->out_filename) {
LOG_ERROR("Out of memory");
- free(obj);
- return JIM_ERR;
+ goto err_exit;
}
Jim_Obj *n;
@@ -974,8 +973,7 @@ static int jim_arm_tpiu_swo_create(Jim_Interp *interp, int argc, Jim_Obj *const
obj->name = strdup(Jim_GetString(n, NULL));
if (!obj->name) {
LOG_ERROR("Out of memory");
- free(obj);
- return JIM_ERR;
+ goto err_exit;
}
/* Do the rest as "configure" options */
-----------------------------------------------------------------------
Summary of changes:
src/target/arm_tpiu_swo.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2024-06-15 14:11:55
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 400cf213c05d17cede4dca4787a5533959bd2183
Author: Evgeniy Naydanov <evg...@sy...>
Date: Mon May 27 14:54:05 2024 +0300
fix GCC's `-Wcalloc-transposed-args` warning
GCC 14.1.0 warns about calls to `calloc()` with element size as the
first argument.
Link: https://gcc.gnu.org/onlinedocs/gcc-14.1.0/gcc/Warning-Options.html#index-Wcalloc-transposed-args
Change-Id: I7d44a74a003ee6ec49d165f91727972478214587
Signed-off-by: Evgeniy Naydanov <evg...@sy...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8301
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/flash/nor/ambiqmicro.c b/src/flash/nor/ambiqmicro.c
index 2b458bc8f..bb893778c 100644
--- a/src/flash/nor/ambiqmicro.c
+++ b/src/flash/nor/ambiqmicro.c
@@ -124,7 +124,7 @@ FLASH_BANK_COMMAND_HANDLER(ambiqmicro_flash_bank_command)
if (CMD_ARGC < 6)
return ERROR_COMMAND_SYNTAX_ERROR;
- ambiqmicro_info = calloc(sizeof(struct ambiqmicro_flash_bank), 1);
+ ambiqmicro_info = calloc(1, sizeof(struct ambiqmicro_flash_bank));
bank->driver_priv = ambiqmicro_info;
diff --git a/src/flash/nor/at91sam7.c b/src/flash/nor/at91sam7.c
index 6879a1bf2..86c80765f 100644
--- a/src/flash/nor/at91sam7.c
+++ b/src/flash/nor/at91sam7.c
@@ -560,7 +560,7 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
if (bnk > 0) {
if (!t_bank->next) {
/* create a new flash bank element */
- struct flash_bank *fb = calloc(sizeof(struct flash_bank), 1);
+ struct flash_bank *fb = calloc(1, sizeof(struct flash_bank));
if (!fb) {
LOG_ERROR("No memory for flash bank");
return ERROR_FAIL;
@@ -748,7 +748,7 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
if (bnk > 0) {
if (!t_bank->next) {
/* create a new bank element */
- struct flash_bank *fb = calloc(sizeof(struct flash_bank), 1);
+ struct flash_bank *fb = calloc(1, sizeof(struct flash_bank));
if (!fb) {
LOG_ERROR("No memory for flash bank");
return ERROR_FAIL;
diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c
index e8074e35b..fee36444e 100644
--- a/src/flash/nor/kinetis.c
+++ b/src/flash/nor/kinetis.c
@@ -930,7 +930,7 @@ FLASH_BANK_COMMAND_HANDLER(kinetis_flash_bank_command)
k_chip = kinetis_get_chip(target);
if (!k_chip) {
- k_chip = calloc(sizeof(struct kinetis_chip), 1);
+ k_chip = calloc(1, sizeof(struct kinetis_chip));
if (!k_chip) {
LOG_ERROR("No memory");
return ERROR_FAIL;
@@ -1031,7 +1031,7 @@ static int kinetis_create_missing_banks(struct kinetis_chip *k_chip)
bank_idx - k_chip->num_pflash_blocks);
}
- bank = calloc(sizeof(struct flash_bank), 1);
+ bank = calloc(1, sizeof(struct flash_bank));
if (!bank)
return ERROR_FAIL;
diff --git a/src/flash/nor/max32xxx.c b/src/flash/nor/max32xxx.c
index 51d6ae271..59a14af8b 100644
--- a/src/flash/nor/max32xxx.c
+++ b/src/flash/nor/max32xxx.c
@@ -87,7 +87,7 @@ FLASH_BANK_COMMAND_HANDLER(max32xxx_flash_bank_command)
return ERROR_FLASH_BANK_INVALID;
}
- info = calloc(sizeof(struct max32xxx_flash_bank), 1);
+ info = calloc(1, sizeof(struct max32xxx_flash_bank));
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], info->flash_size);
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[6], info->flc_base);
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[7], info->sector_size);
diff --git a/src/flash/nor/msp432.c b/src/flash/nor/msp432.c
index 5e2935d02..b5e2b0bf8 100644
--- a/src/flash/nor/msp432.c
+++ b/src/flash/nor/msp432.c
@@ -937,7 +937,7 @@ static int msp432_probe(struct flash_bank *bank)
if (is_main && MSP432P4 == msp432_bank->family_type) {
/* Create the info flash bank needed by MSP432P4 variants */
- struct flash_bank *info = calloc(sizeof(struct flash_bank), 1);
+ struct flash_bank *info = calloc(1, sizeof(struct flash_bank));
if (!info)
return ERROR_FAIL;
diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c
index 972686e3f..eab6244d4 100644
--- a/src/flash/nor/stellaris.c
+++ b/src/flash/nor/stellaris.c
@@ -453,7 +453,7 @@ FLASH_BANK_COMMAND_HANDLER(stellaris_flash_bank_command)
if (CMD_ARGC < 6)
return ERROR_COMMAND_SYNTAX_ERROR;
- stellaris_info = calloc(sizeof(struct stellaris_flash_bank), 1);
+ stellaris_info = calloc(1, sizeof(struct stellaris_flash_bank));
bank->base = 0x0;
bank->driver_priv = stellaris_info;
diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c
index 4e0f73182..3bafde56f 100644
--- a/src/flash/nor/stm32f2x.c
+++ b/src/flash/nor/stm32f2x.c
@@ -1020,7 +1020,7 @@ static int stm32x_probe(struct flash_bank *bank)
assert(num_sectors > 0);
bank->num_sectors = num_sectors;
- bank->sectors = calloc(sizeof(struct flash_sector), num_sectors);
+ bank->sectors = calloc(num_sectors, sizeof(struct flash_sector));
if (stm32x_otp_is_f7(bank))
bank->size = STM32F7_OTP_SIZE;
diff --git a/src/jtag/drivers/angie.c b/src/jtag/drivers/angie.c
index c024667bd..81dd1af82 100644
--- a/src/jtag/drivers/angie.c
+++ b/src/jtag/drivers/angie.c
@@ -1597,7 +1597,7 @@ static int angie_queue_scan(struct angie *device, struct jtag_command *cmd)
/* Allocate TDO buffer if required */
if (type == SCAN_IN || type == SCAN_IO) {
- tdo_buffer_start = calloc(sizeof(uint8_t), scan_size_bytes);
+ tdo_buffer_start = calloc(scan_size_bytes, sizeof(uint8_t));
if (!tdo_buffer_start)
return ERROR_FAIL;
diff --git a/src/jtag/drivers/ulink.c b/src/jtag/drivers/ulink.c
index 4f23c6c7f..0fe8989b9 100644
--- a/src/jtag/drivers/ulink.c
+++ b/src/jtag/drivers/ulink.c
@@ -1473,7 +1473,7 @@ static int ulink_queue_scan(struct ulink *device, struct jtag_command *cmd)
/* Allocate TDO buffer if required */
if ((type == SCAN_IN) || (type == SCAN_IO)) {
- tdo_buffer_start = calloc(sizeof(uint8_t), scan_size_bytes);
+ tdo_buffer_start = calloc(scan_size_bytes, sizeof(uint8_t));
if (!tdo_buffer_start)
return ERROR_FAIL;
diff --git a/src/target/arc_jtag.c b/src/target/arc_jtag.c
index ddb4f6232..a186709c6 100644
--- a/src/target/arc_jtag.c
+++ b/src/target/arc_jtag.c
@@ -298,7 +298,7 @@ static int arc_jtag_read_registers(struct arc_jtag *jtag_info, uint32_t type,
ARC_JTAG_READ_FROM_CORE_REG : ARC_JTAG_READ_FROM_AUX_REG);
arc_jtag_enque_set_transaction(jtag_info, transaction, TAP_DRPAUSE);
- uint8_t *data_buf = calloc(sizeof(uint8_t), count * 4);
+ uint8_t *data_buf = calloc(count * 4, sizeof(uint8_t));
arc_jtag_enque_register_rw(jtag_info, addr, data_buf, NULL, count);
@@ -498,7 +498,7 @@ int arc_jtag_read_memory(struct arc_jtag *jtag_info, uint32_t addr,
if (!count)
return ERROR_OK;
- data_buf = calloc(sizeof(uint8_t), count * 4);
+ data_buf = calloc(count * 4, sizeof(uint8_t));
arc_jtag_enque_reset_transaction(jtag_info);
/* We are reading from memory. */
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/ambiqmicro.c | 2 +-
src/flash/nor/at91sam7.c | 4 ++--
src/flash/nor/kinetis.c | 4 ++--
src/flash/nor/max32xxx.c | 2 +-
src/flash/nor/msp432.c | 2 +-
src/flash/nor/stellaris.c | 2 +-
src/flash/nor/stm32f2x.c | 2 +-
src/jtag/drivers/angie.c | 2 +-
src/jtag/drivers/ulink.c | 2 +-
src/target/arc_jtag.c | 4 ++--
10 files changed, 13 insertions(+), 13 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2024-06-08 09:20:43
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via e4c0904731320c686e5074e68db8358e2f3ce83d (commit)
from 70b362d4f47194eced99b448cc99b093641d1465 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit e4c0904731320c686e5074e68db8358e2f3ce83d
Author: Tomas Vanek <va...@fb...>
Date: Mon Jan 22 21:09:31 2024 +0100
flash/nor/nrf5: handle ERROR_WAIT during nRF91 flash erase
Erase is initiated by write to a flash address. Due to the
silicon errata of nRF91 the write stalls the bus until the page erase
is finished (takes up to 87ms).
If the adapter does not handle SWD WAIT properly, the following read
in nrf5_wait_for_nvmc() returns ERROR_WAIT.
Wait for fixed time before accessing AP. Not nice, but the only
working solution until all adapters handle SWD WAIT.
If the fixed wait does not suffice, continue the wait loop after a delay.
It makes some unnecessary noise however erase works.
Signed-off-by: Tomas Vanek <va...@fb...>
Change-Id: I63faf38dad79440a0117ed79930442bd2843c6db
Reviewed-on: https://review.openocd.org/c/openocd/+/8115
Reviewed-by: Tomáš Beneš <to...@dr...>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index cac233d47..f07433e67 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -373,6 +373,12 @@ static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
do {
res = nrf5_nvmc_read_u32(chip, NRF5_NVMC_READY, &ready);
+ if (res == ERROR_WAIT) {
+ /* The adapter does not handle SWD WAIT properly,
+ * add some delay to reduce number of error messages */
+ alive_sleep(10);
+ continue;
+ }
if (res != ERROR_OK) {
LOG_ERROR("Error waiting NVMC_READY: generic flash write/erase error (check protection etc...)");
return res;
@@ -1072,6 +1078,22 @@ static int nrf5_erase_page(struct flash_bank *bank,
} else if (chip->features & NRF5_FEATURE_ERASE_BY_FLASH_WR) {
res = target_write_u32(chip->target, bank->base + sector->offset, 0xffffffff);
+ /* nRF9160 errata [2] NVMC: CPU code execution from RAM halted during
+ * flash page erase operation
+ * https://infocenter.nordicsemi.com/index.jsp?topic=%2Ferrata_nRF9160_Rev1%2FERR%2FnRF9160%2FRev1%2Flatest%2Fanomaly_160_2.html
+ * affects also erasing by debugger MEM-AP write:
+ *
+ * Write to a flash address stalls the bus for 87 ms until
+ * page erase finishes! This makes problems if the adapter does not
+ * handle SWD WAIT properly or does not wait long enough.
+ * Using a target algo would not help, AP gets unresponsive too.
+ * Neither sending AP ABORT helps, the next AP access stalls again.
+ * Simply wait long enough before accessing AP again...
+ *
+ * The same errata was observed in nRF9161
+ */
+ if (chip->features & NRF5_FEATURE_SERIES_91)
+ alive_sleep(90);
} else {
res = nrf5_nvmc_write_u32(chip, NRF5_NVMC_ERASEPAGE, sector->offset);
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/nrf5.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
hooks/post-receive
--
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From: openocd-gerrit <ope...@us...> - 2024-06-08 09:19:45
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 70b362d4f47194eced99b448cc99b093641d1465 (commit)
from 17be341d38bda1115b3eb8878ef7f830982fabfb (commit)
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- Log -----------------------------------------------------------------
commit 70b362d4f47194eced99b448cc99b093641d1465
Author: Tomas Vanek <va...@fb...>
Date: Mon Jan 22 18:17:48 2024 +0100
flash/nor/nrf5: show proper SoC type on newer nRF91 devices
Since nRF9160 Product Specification v2.1 the new UICR SIPINFO
fields should be preferred over UICR INFO.
Tested on nRF9161.
Signed-off-by: Tomas Vanek <va...@fb...>
Change-Id: Ib8005b3b6292aa20fa83c1dcebd2de27df58b661
Reviewed-on: https://review.openocd.org/c/openocd/+/8114
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index 80243ed59..cac233d47 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -285,6 +285,22 @@ static const struct nrf5_ficr_map nrf53_91_ficr_offsets = {
.info_flash = 0x21c,
};
+/* Since nRF9160 Product Specification v2.1 there is
+ * a new UICR field SIPINFO, which should be preferred.
+ * The original INFO fields describe just a part of the chip
+ * (PARTNO=9120 at nRF9161)
+ */
+static const struct nrf5_ficr_map nrf91new_ficr_offsets = {
+ .codepagesize = 0x220,
+ .codesize = 0x224,
+ .configid = 0x200,
+ .info_part = 0x140, /* SIPINFO.PARTNO */
+ .info_variant = 0x148, /* SIPINFO.VARIANT */
+ .info_package = 0x214,
+ .info_ram = 0x218,
+ .info_flash = 0x21c,
+};
+
enum {
NRF53APP_91_FICR_BASE = 0x00FF0000,
NRF53APP_91_UICR_BASE = 0x00FF8000,
@@ -614,12 +630,17 @@ static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first,
return ERROR_FLASH_OPER_UNSUPPORTED;
}
-static bool nrf5_info_variant_to_str(uint32_t variant, char *bf)
+static bool nrf5_info_variant_to_str(uint32_t variant, char *bf, bool swap)
{
uint8_t b[4];
- h_u32_to_be(b, variant);
- if (isalnum(b[0]) && isalnum(b[1]) && isalnum(b[2]) && isalnum(b[3])) {
+ if (swap)
+ h_u32_to_le(b, variant);
+ else
+ h_u32_to_be(b, variant);
+
+ if (isalnum(b[0]) && isalnum(b[1]) && isalnum(b[2]) &&
+ (isalnum(b[3]) || b[3] == 0)) {
memcpy(bf, b, 4);
bf[4] = 0;
return true;
@@ -646,7 +667,10 @@ static int nrf5_get_chip_type_str(const struct nrf5_info *chip, char *buf, unsig
chip->spec->part, chip->spec->variant, chip->spec->build_code);
} else if (chip->ficr_info_valid) {
char variant[5];
- nrf5_info_variant_to_str(chip->ficr_info.variant, variant);
+
+ nrf5_info_variant_to_str(chip->ficr_info.variant, variant,
+ chip->features & NRF5_FEATURE_SERIES_91);
+
if (chip->features & (NRF5_FEATURE_SERIES_53 | NRF5_FEATURE_SERIES_91)) {
res = snprintf(buf, buf_size, "nRF%" PRIx32 "-%s",
chip->ficr_info.part, variant);
@@ -825,6 +849,16 @@ static int nrf5_probe(struct flash_bank *bank)
switch (bank->base) {
case NRF5_FLASH_BASE:
case NRF53APP_91_UICR_BASE:
+ res = nrf5_read_ficr_info_part(chip, &nrf53app_91_map, &nrf91new_ficr_offsets);
+ if (res == ERROR_OK) {
+ res = nrf53_91_partno_check(chip);
+ if (res == ERROR_OK) {
+ chip->map = &nrf53app_91_map;
+ chip->ficr_offsets = &nrf91new_ficr_offsets;
+ break;
+ }
+ }
+
res = nrf5_read_ficr_info_part(chip, &nrf53app_91_map, &nrf53_91_ficr_offsets);
if (res != ERROR_OK)
break;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/nrf5.c | 42 ++++++++++++++++++++++++++++++++++++++----
1 file changed, 38 insertions(+), 4 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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From: openocd-gerrit <ope...@us...> - 2024-06-08 09:16:44
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 17be341d38bda1115b3eb8878ef7f830982fabfb (commit)
from d94daf776c5778c94b2ead4db4bc368a20ffa5cf (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 17be341d38bda1115b3eb8878ef7f830982fabfb
Author: Tomas Vanek <va...@fb...>
Date: Mon Jan 22 15:33:47 2024 +0100
tcl/target: add nRF53 and nRF91 config files
Both devices can be configured with or without SWD multidrop.
nRF53 network core is examined on demand to avoid problems
when the core is forced off.
Change-Id: I08f88ff48ff7ac592e9214b89ca8e5e9428573a5
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8113
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/tcl/target/nrf53.cfg b/tcl/target/nrf53.cfg
new file mode 100644
index 000000000..307df902c
--- /dev/null
+++ b/tcl/target/nrf53.cfg
@@ -0,0 +1,146 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic nRF53 series: dual ARM Cortex-M33, multidrop SWD
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME nrf53
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x4000
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x6ba02477
+}
+
+# Configurable instance ID resides in application UICR TINSTANCE
+if { [info exists SWD_INSTANCE_ID] } {
+ set _SWD_INSTANCE_ID $SWD_INSTANCE_ID
+} else {
+ set _SWD_INSTANCE_ID 0
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+if { [info exists SWD_MULTIDROP] } {
+ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id 0x0070289 -instance-id $_SWD_INSTANCE_ID
+} else {
+ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+}
+
+set _TARGETNAME_APP $_CHIPNAME.cpuapp
+target create $_TARGETNAME_APP cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME_APP configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# The network core is not accessible over HLA
+if { ![using_hla] } {
+ set _TARGETNAME_NET $_CHIPNAME.cpunet
+ target create $_TARGETNAME_NET cortex_m -dap $_CHIPNAME.dap -ap-num 1 -defer-examine
+
+ targets $_TARGETNAME_APP
+
+ $_TARGETNAME_NET configure -work-area-phys 0x21000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+}
+
+# Keep adapter speed less or equal 2000 kHz or flash programming fails!
+adapter speed 1000
+
+source [find target/nrf_common.cfg]
+
+flash bank $_CHIPNAME.app.flash nrf5 0x00000000 0 0 0 $_TARGETNAME_APP
+flash bank $_CHIPNAME.app.uicr nrf5 0x00FF8000 0 0 0 $_TARGETNAME_APP
+
+if { ![using_hla] } {
+
+ flash bank $_CHIPNAME.net.flash nrf5 0x01000000 0 0 0 $_TARGETNAME_NET
+ flash bank $_CHIPNAME.net.uicr nrf5 0x01FF8000 0 0 0 $_TARGETNAME_NET
+
+ # System reset sets NETWORK.FORCEOFF which keeps the network core in reset
+ # Don't touch network core during reset
+ $_TARGETNAME_NET configure -event reset-assert {}
+ # and start it after application core reset is finished to make all flash accessible
+ $_TARGETNAME_APP configure -event reset-init "nrf53_cpunet_release $_CHIPNAME"
+
+ $_TARGETNAME_APP cortex_m reset_config sysresetreq
+ $_TARGETNAME_NET cortex_m reset_config sysresetreq
+
+ $_TARGETNAME_APP configure -event examine-fail { _nrf_check_ap_lock 2 3 }
+ $_TARGETNAME_NET configure -event examine-fail { _nrf_check_ap_lock 3 3 }
+
+ $_TARGETNAME_NET configure -event gdb-attach "_nrf53_cpunet_gdb_attach $_CHIPNAME"
+
+ proc _nrf53_cpunet_gdb_attach { _CHIPNAME } {
+ set _TARGETNAME_APP $_CHIPNAME.cpuapp
+ set _TARGETNAME_NET $_CHIPNAME.cpunet
+ set RESET_NETWORK_FORCEOFF 0x50005614
+
+ set is_off [$_TARGETNAME_APP read_memory $RESET_NETWORK_FORCEOFF 32 1]
+ if { $is_off } {
+ nrf53_cpunet_release $_CHIPNAME
+ $_TARGETNAME_NET arp_poll
+ $_TARGETNAME_NET arp_waitstate halted 100
+ } else {
+ if { ![$_TARGETNAME_NET was_examined] } {
+ $_TARGETNAME_NET arp_examine
+ $_TARGETNAME_NET arp_poll
+ }
+ set s [$_TARGETNAME_NET curstate]
+ if { ![string compare $s "halted"] } {
+ halt
+ }
+ }
+ }
+ lappend _telnet_autocomplete_skip _nrf53_cpunet_gdb_attach
+
+ # Release the network core
+ proc nrf53_cpunet_release { {_CHIPNAME nrf53} } {
+ set _TARGETNAME_APP $_CHIPNAME.cpuapp
+ set _TARGETNAME_NET $_CHIPNAME.cpunet
+ set RESET_NETWORK_FORCEOFF 0x50005614
+ set RESET_NETWORK_WORKAROUND 0x50005618
+ set CORTEX_M_DCB_DEMCR 0xE000EDFC
+
+ $_TARGETNAME_APP mww $RESET_NETWORK_WORKAROUND 1
+ $_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 0
+ $_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 1
+ set err [catch {$_TARGETNAME_NET arp_examine}]
+ if { $err } {
+ if { ![_nrf_check_ap_lock 3 3] } {
+ echo "Error: \[$_TARGETNAME_NET\] examination failed"
+ }
+ return
+ }
+ # set TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET
+ $_TARGETNAME_NET mww $CORTEX_M_DCB_DEMCR 0x01000501
+ # Write DEMCR directly intead of permanetly setting by cortex_m vector_catch reset
+ # following cortex_m_endreset_event() restores the original DEMCR value
+ $_TARGETNAME_APP mww $RESET_NETWORK_FORCEOFF 0
+ $_TARGETNAME_APP mww $RESET_NETWORK_WORKAROUND 0
+ }
+
+ # Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #2 or #3)
+ proc nrf53_cpuapp_recover {} {
+ _nrf_ctrl_ap_recover 2
+ }
+ add_help_text nrf53_cpuapp_recover "Mass erase flash and unlock nRF53 application CPU"
+
+ proc nrf53_recover {} {
+ _nrf_ctrl_ap_recover 3 1
+ }
+ add_help_text nrf53_recover "Mass erase all device flash and unlock nRF53"
+}
diff --git a/tcl/target/nrf91.cfg b/tcl/target/nrf91.cfg
new file mode 100644
index 000000000..e0ff4e546
--- /dev/null
+++ b/tcl/target/nrf91.cfg
@@ -0,0 +1,63 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic nRF91 series: ARM Cortex-M33, SWD only
+#
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME nrf91
+}
+
+# Work-area is a space in RAM used for flash programming
+# By default use 16kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x4000
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x6ba02477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+# Contrary to the product specification at least nRF9161 supports multidrop SWD.
+# The instance ID is fixed, no more than one nRF91 can be connected to one SWD bus.
+if { [info exists SWD_MULTIDROP] } {
+ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu -dp-id 0x0090289 -instance-id 0
+} else {
+ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+# Keep adapter speed less or equal 2000 kHz or flash programming fails!
+adapter speed 1000
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+source [find target/nrf_common.cfg]
+
+flash bank $_CHIPNAME.flash nrf5 0x00000000 0 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.uicr nrf5 0x00FF8000 0 0 0 $_TARGETNAME
+
+if { ![using_hla] } {
+ $_TARGETNAME cortex_m reset_config sysresetreq
+
+ $_TARGETNAME configure -event examine-fail { _nrf_check_ap_lock 4 3 }
+}
+
+# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #4)
+proc nrf91_recover {} {
+ _nrf_ctrl_ap_recover 4
+}
+add_help_text nrf91_recover "Mass erase and unlock nRF91 device"
diff --git a/tcl/target/nrf_common.cfg b/tcl/target/nrf_common.cfg
new file mode 100644
index 000000000..2ae5011e4
--- /dev/null
+++ b/tcl/target/nrf_common.cfg
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Nordic nRF52, nRF53 and nRF91 CTRL-AP handling
+#
+
+if { [using_hla] } {
+ echo ""
+ echo "nRF device has a CTRL-AP dedicated to recover the device from AP lock."
+ echo "A high level adapter (like a ST-Link) you are currently using cannot access"
+ echo "the CTRL-AP so 'nrfxx_recover' command will not work."
+ echo "Do not enable UICR APPROTECT."
+ echo ""
+} else {
+
+ # Test if debug/MEM-AP is locked by UICR APPROTECT
+ proc _nrf_check_ap_lock { ctrl_ap_num unlocked_value } {
+ set target [target current]
+ set dap [$target cget -dap]
+ set err [catch {set APPROTECTSTATUS [$dap apreg $ctrl_ap_num 0xc]}]
+ if {$err == 0 && $APPROTECTSTATUS < $unlocked_value} {
+ echo ""
+ echo "****** WARNING ******"
+ echo "\[$target\] device has AP lock engaged (see UICR APPROTECT register)."
+ echo "Debug access is denied."
+ echo "Use 'nrfxx_recover' to erase and unlock the device."
+ echo ""
+ poll off
+ return 1
+ }
+ return 0
+ }
+
+ # Mass erase and unlock the device using proprietary nRF CTRL-AP
+ proc _nrf_ctrl_ap_recover { ctrl_ap_num {is_cpunet 0} } {
+ set target [target current]
+ set dap [$target cget -dap]
+
+ set IDR [$dap apreg $ctrl_ap_num 0xfc]
+ if {$IDR != 0x12880000} {
+ echo "Error: Cannot access nRF CTRL-AP!"
+ return
+ }
+
+ poll off
+
+ # Reset and trigger ERASEALL task
+ $dap apreg $ctrl_ap_num 4 0
+ $dap apreg $ctrl_ap_num 4 1
+
+ for {set i 0} {1} {incr i} {
+ set ERASEALLSTATUS [$dap apreg $ctrl_ap_num 8]
+ if {$ERASEALLSTATUS == 0} {
+ echo "\[$target\] device has been successfully erased and unlocked."
+ break
+ }
+ if {$i == 0} {
+ echo "Waiting for chip erase..."
+ }
+ if {$i >= 150} {
+ echo "Error: \[$target\] recovery failed."
+ break
+ }
+ sleep 100
+ }
+
+ # Assert reset
+ $dap apreg $ctrl_ap_num 0 1
+
+ # Deassert reset
+ $dap apreg $ctrl_ap_num 0 0
+
+ # Reset ERASEALL task
+ $dap apreg $ctrl_ap_num 4 0
+
+ if { $is_cpunet } {
+ reset init
+ } else {
+ sleep 100
+ $target arp_examine
+ poll on
+ }
+ }
+
+ lappend _telnet_autocomplete_skip _nrf_check_ap_lock _nrf_ctrl_ap_recover
+}
-----------------------------------------------------------------------
Summary of changes:
tcl/target/nrf53.cfg | 146 ++++++++++++++++++++++++++++++++++++++++++++++
tcl/target/nrf91.cfg | 63 ++++++++++++++++++++
tcl/target/nrf_common.cfg | 86 +++++++++++++++++++++++++++
3 files changed, 295 insertions(+)
create mode 100644 tcl/target/nrf53.cfg
create mode 100644 tcl/target/nrf91.cfg
create mode 100644 tcl/target/nrf_common.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2024-06-08 09:05:00
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via d94daf776c5778c94b2ead4db4bc368a20ffa5cf (commit)
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- Log -----------------------------------------------------------------
commit d94daf776c5778c94b2ead4db4bc368a20ffa5cf
Author: Tomas Vanek <va...@fb...>
Date: Mon Jan 22 12:45:49 2024 +0100
flash/nor/nrf5: add basic nRF53 and nRF91 support
Probes all flash and UICR areas.
Flash erase and write tested.
On nRF53 mass erase works on the application core flash bank only.
The Tcl script nrf53_recover can serve as the workaround on the
network core.
TODO: mass erase of the nRF53 network core flash.
Some ideas taken from [1] and [2].
Change-Id: I8e27a780f4d82bcabf029f79b87ac46cf6a531c7
Link: [1] 7404: flash: nor: add support for Nordic nRF9160 | https://review.openocd.org/c/openocd/+/7404
Link: [2] 8062: flash: nor: add support for Nordic nRF9160 | https://review.openocd.org/c/openocd/+/8062
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8112
Reviewed-by: Tomáš Beneš <to...@dr...>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index b782e0ba9..8c9f3ff84 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -7316,12 +7316,13 @@ flash bank $_FLASHNAME npcx 0x64000000 0 0 0 $_TARGETNAME
@end deffn
@deffn {Flash Driver} {nrf5}
-All members of the nRF51 microcontroller families from Nordic Semiconductor
-include internal flash and use ARM Cortex-M0 core. nRF52 family powered
-by ARM Cortex-M4 or M4F core is supported too. nRF52832 is fully supported
-including BPROT flash protection scheme. nRF52833 and nRF52840 devices are
-supported with the exception of security extensions (flash access control list
-- ACL).
+Supports all members of the nRF51, nRF52 and nRF53 microcontroller families from
+Nordic Semiconductor. nRF91 family is supported too. One driver handles both
+the main flash and the UICR area.
+
+Flash protection is handled on nRF51 family and nRF52805, nRF52810, nRF52811,
+nRF52832 devices. Flash access control list (ACL) protection scheme of the newer
+devices is not supported.
@example
flash bank $_FLASHNAME nrf5 0 0x00000000 0 0 $_TARGETNAME
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index 641f3ab21..80243ed59 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -79,6 +79,9 @@ enum nrf5_features {
NRF5_FEATURE_SERIES_52 = BIT(1),
NRF5_FEATURE_BPROT = BIT(2),
NRF5_FEATURE_ACL_PROT = BIT(3),
+ NRF5_FEATURE_SERIES_53 = BIT(4),
+ NRF5_FEATURE_SERIES_91 = BIT(5),
+ NRF5_FEATURE_ERASE_BY_FLASH_WR = BIT(6),
};
struct nrf5_device_spec {
@@ -268,6 +271,55 @@ static const struct nrf5_map nrf51_52_map = {
.watchdog_refresh_addr = 0x40010600,
};
+
+/* Third generation devices (nRF53, nRF91) */
+
+static const struct nrf5_ficr_map nrf53_91_ficr_offsets = {
+ .codepagesize = 0x220,
+ .codesize = 0x224,
+ .configid = 0x200,
+ .info_part = 0x20c,
+ .info_variant = 0x210,
+ .info_package = 0x214,
+ .info_ram = 0x218,
+ .info_flash = 0x21c,
+};
+
+enum {
+ NRF53APP_91_FICR_BASE = 0x00FF0000,
+ NRF53APP_91_UICR_BASE = 0x00FF8000,
+ NRF53NET_FLASH_BASE = 0x01000000,
+ NRF53NET_FICR_BASE = 0x01FF0000,
+ NRF53NET_UICR_BASE = 0x01FF8000,
+};
+
+static const struct nrf5_map nrf53app_91_map = {
+ .flash_base = NRF5_FLASH_BASE,
+ .ficr_base = NRF53APP_91_FICR_BASE,
+ .uicr_base = NRF53APP_91_UICR_BASE,
+ .nvmc_base = 0x50039000,
+
+ .watchdog_refresh_addr = 0x50018600,
+};
+
+/* nRF53 duality:
+ * SoC consists of two Cortex-M33 cores:
+ * - application core with security extensions
+ * - network core
+ * Each core has its own RAM, flash, FICR and UICR
+ * The flash driver probes and handles flash and UICR of one core
+ * independently of those dedicated to the other core.
+ */
+static const struct nrf5_map nrf53net_map = {
+ .flash_base = NRF53NET_FLASH_BASE,
+ .ficr_base = NRF53NET_FICR_BASE,
+ .uicr_base = NRF53NET_UICR_BASE,
+ .nvmc_base = 0x41080000,
+
+ .watchdog_refresh_addr = 0x41080000,
+};
+
+
const struct flash_driver nrf5_flash, nrf51_flash;
static bool nrf5_bank_is_probed(const struct flash_bank *bank)
@@ -595,10 +647,15 @@ static int nrf5_get_chip_type_str(const struct nrf5_info *chip, char *buf, unsig
} else if (chip->ficr_info_valid) {
char variant[5];
nrf5_info_variant_to_str(chip->ficr_info.variant, variant);
- res = snprintf(buf, buf_size, "nRF%" PRIx32 "-%s%.2s(build code: %s)",
- chip->ficr_info.part,
- nrf5_decode_info_package(chip->ficr_info.package),
- variant, &variant[2]);
+ if (chip->features & (NRF5_FEATURE_SERIES_53 | NRF5_FEATURE_SERIES_91)) {
+ res = snprintf(buf, buf_size, "nRF%" PRIx32 "-%s",
+ chip->ficr_info.part, variant);
+ } else {
+ res = snprintf(buf, buf_size, "nRF%" PRIx32 "-%s%.2s(build code: %s)",
+ chip->ficr_info.part,
+ nrf5_decode_info_package(chip->ficr_info.package),
+ variant, &variant[2]);
+ }
} else {
res = snprintf(buf, buf_size, "nRF51xxx (HWID 0x%04" PRIx16 ")", chip->hwid);
}
@@ -627,26 +684,27 @@ static int nrf5_info(struct flash_bank *bank, struct command_invocation *cmd)
return ERROR_OK;
}
-static int nrf5_read_ficr_info(struct nrf5_info *chip, const struct nrf5_map *map,
+static int nrf5_read_ficr_info_part(struct nrf5_info *chip, const struct nrf5_map *map,
const struct nrf5_ficr_map *ficr_offsets)
{
- int res;
struct target *target = chip->target;
uint32_t ficr_base = map->ficr_base;
- chip->ficr_info_valid = false;
-
- res = target_read_u32(target, ficr_base + ficr_offsets->info_part, &chip->ficr_info.part);
- if (res != ERROR_OK) {
+ int res = target_read_u32(target, ficr_base + ficr_offsets->info_part, &chip->ficr_info.part);
+ if (res != ERROR_OK)
LOG_DEBUG("Couldn't read FICR INFO.PART register");
- return res;
- }
+
+ return res;
+}
+
+static int nrf51_52_partno_check(struct nrf5_info *chip)
+{
uint32_t series = chip->ficr_info.part & 0xfffff000;
switch (series) {
case 0x51000:
chip->features = NRF5_FEATURE_SERIES_51;
- break;
+ return ERROR_OK;
case 0x52000:
chip->features = NRF5_FEATURE_SERIES_52;
@@ -665,19 +723,40 @@ static int nrf5_read_ficr_info(struct nrf5_info *chip, const struct nrf5_map *ma
chip->features |= NRF5_FEATURE_ACL_PROT;
break;
}
- break;
+ return ERROR_OK;
default:
LOG_DEBUG("FICR INFO likely not implemented. Invalid PART value 0x%08"
- PRIx32, chip->ficr_info.part);
+ PRIx32, chip->ficr_info.part);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
+}
+
+static int nrf53_91_partno_check(struct nrf5_info *chip)
+{
+ uint32_t series = chip->ficr_info.part & 0xffffff00;
+ switch (series) {
+ case 0x5300:
+ chip->features = NRF5_FEATURE_SERIES_53 | NRF5_FEATURE_ERASE_BY_FLASH_WR;
+ return ERROR_OK;
- /* Now we know the device has FICR INFO filled by something relevant:
- * Although it is not documented, the tested nRF51 rev 3 devices
- * have FICR INFO.PART, RAM and FLASH of the same format as nRF52.
- * VARIANT and PACKAGE coding is unknown for a nRF51 device.
- * nRF52 devices have FICR INFO documented and always filled. */
+ case 0x9100:
+ chip->features = NRF5_FEATURE_SERIES_91 | NRF5_FEATURE_ERASE_BY_FLASH_WR;
+ return ERROR_OK;
+
+ default:
+ LOG_DEBUG("Invalid FICR INFO PART value 0x%08"
+ PRIx32, chip->ficr_info.part);
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+}
+
+static int nrf5_read_ficr_more_info(struct nrf5_info *chip)
+{
+ int res;
+ struct target *target = chip->target;
+ const struct nrf5_ficr_map *ficr_offsets = chip->ficr_offsets;
+ uint32_t ficr_base = chip->map->ficr_base;
res = target_read_u32(target, ficr_base + ficr_offsets->info_variant, &chip->ficr_info.variant);
if (res != ERROR_OK)
@@ -692,11 +771,7 @@ static int nrf5_read_ficr_info(struct nrf5_info *chip, const struct nrf5_map *ma
return res;
res = target_read_u32(target, ficr_base + ficr_offsets->info_flash, &chip->ficr_info.flash);
- if (res != ERROR_OK)
- return res;
-
- chip->ficr_info_valid = true;
- return ERROR_OK;
+ return res;
}
/* nRF51 series only */
@@ -735,7 +810,7 @@ static int nrf51_get_ram_size(struct target *target, uint32_t *ram_size)
static int nrf5_probe(struct flash_bank *bank)
{
- int res;
+ int res = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
struct nrf5_bank *nbank = bank->driver_priv;
assert(nbank);
@@ -744,15 +819,72 @@ static int nrf5_probe(struct flash_bank *bank)
struct target *target = chip->target;
chip->spec = NULL;
+ chip->ficr_info_valid = false;
- /* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
- chip->features = NRF5_FEATURE_SERIES_51;
- chip->map = &nrf51_52_map;
- chip->ficr_offsets = &nrf51_52_ficr_offsets;
+ /* First try to detect nRF53/91 */
+ switch (bank->base) {
+ case NRF5_FLASH_BASE:
+ case NRF53APP_91_UICR_BASE:
+ res = nrf5_read_ficr_info_part(chip, &nrf53app_91_map, &nrf53_91_ficr_offsets);
+ if (res != ERROR_OK)
+ break;
- /* Don't bail out on error for the case that some old engineering
- * sample has FICR INFO registers unreadable. We can proceed anyway. */
- (void)nrf5_read_ficr_info(chip, chip->map, chip->ficr_offsets);
+ res = nrf53_91_partno_check(chip);
+ if (res != ERROR_OK)
+ break;
+
+ chip->map = &nrf53app_91_map;
+ chip->ficr_offsets = &nrf53_91_ficr_offsets;
+ break;
+
+ case NRF53NET_FLASH_BASE:
+ case NRF53NET_UICR_BASE:
+ res = nrf5_read_ficr_info_part(chip, &nrf53net_map, &nrf53_91_ficr_offsets);
+ if (res != ERROR_OK)
+ break;
+
+ res = nrf53_91_partno_check(chip);
+ if (res != ERROR_OK)
+ break;
+
+ chip->map = &nrf53net_map;
+ chip->ficr_offsets = &nrf53_91_ficr_offsets;
+ break;
+
+ default:
+ break;
+ }
+
+ /* If nRF53/91 is not detected, try nRF51/52 */
+ if (res != ERROR_OK) {
+ /* Guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
+ chip->features = NRF5_FEATURE_SERIES_51;
+ chip->map = &nrf51_52_map;
+ chip->ficr_offsets = &nrf51_52_ficr_offsets;
+
+ /* Don't bail out on error for the case that some old engineering
+ * sample has FICR INFO registers unreadable. We can proceed anyway. */
+ res = nrf5_read_ficr_info_part(chip, chip->map, chip->ficr_offsets);
+ if (res == ERROR_OK)
+ res = nrf51_52_partno_check(chip);
+ }
+
+ if (res == ERROR_OK) {
+ /* Now we know the device has FICR INFO filled by something relevant:
+ * Although it is not documented, the tested nRF51 rev 3 devices
+ * have FICR INFO.PART, RAM and FLASH of the same format as nRF52.
+ * VARIANT and PACKAGE coding is unknown for a nRF51 device.
+ * nRF52 devices have FICR INFO documented and always filled. */
+ res = nrf5_read_ficr_more_info(chip);
+ if (res == ERROR_OK) {
+ chip->ficr_info_valid = true;
+ } else if (chip->features & NRF5_FEATURE_SERIES_51) {
+ LOG_DEBUG("Couldn't read some of FICR INFO registers");
+ } else {
+ LOG_ERROR("Couldn't read some of FICR INFO registers");
+ return res;
+ }
+ }
const struct nrf5_ficr_map *ficr_offsets = chip->ficr_offsets;
uint32_t ficr_base = chip->map->ficr_base;
@@ -904,6 +1036,9 @@ static int nrf5_erase_page(struct flash_bank *bank,
res = nrf5_nvmc_write_u32(chip, NRF5_NVMC_ERASEUICR, 0x00000001);
+ } else if (chip->features & NRF5_FEATURE_ERASE_BY_FLASH_WR) {
+ res = target_write_u32(chip->target, bank->base + sector->offset, 0xffffffff);
+
} else {
res = nrf5_nvmc_write_u32(chip, NRF5_NVMC_ERASEPAGE, sector->offset);
}
@@ -1175,7 +1310,10 @@ FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
switch (bank->base) {
case NRF5_FLASH_BASE:
+ case NRF53NET_FLASH_BASE:
case NRF51_52_UICR_BASE:
+ case NRF53APP_91_UICR_BASE:
+ case NRF53NET_UICR_BASE:
break;
default:
LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
@@ -1194,9 +1332,12 @@ FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
switch (bank->base) {
case NRF5_FLASH_BASE:
+ case NRF53NET_FLASH_BASE:
nbank = &chip->bank[0];
break;
case NRF51_52_UICR_BASE:
+ case NRF53APP_91_UICR_BASE:
+ case NRF53NET_UICR_BASE:
nbank = &chip->bank[1];
break;
}
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 13 ++--
src/flash/nor/nrf5.c | 207 +++++++++++++++++++++++++++++++++++++++++++--------
2 files changed, 181 insertions(+), 39 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2024-06-08 09:04:20
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via fc7a428fc2a5d1e74621e56a2cbd2c31566fc63f (commit)
from 37f9485cef8b98aaed739c8140b3674441dc5876 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit fc7a428fc2a5d1e74621e56a2cbd2c31566fc63f
Author: Tomas Vanek <va...@fb...>
Date: Mon Jan 22 14:17:27 2024 +0100
flash/nor/nrf5: make flash erase little faster
Enable and disable erase mode only once
instead of toggling it for each sector.
Refactor to decrease the number of call levels.
Change-Id: Ie546a4fc24da0eea2753a2bebaa63d941ef7aa1d
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8111
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index b4a8e979e..641f3ab21 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -375,7 +375,7 @@ static int nrf5_nvmc_read_only(struct nrf5_info *chip)
NRF5_NVMC_CONFIG_REN);
if (res != ERROR_OK) {
- LOG_ERROR("Failed to enable read-only operation");
+ LOG_ERROR("Failed to disable write/erase operation");
return res;
}
/*
@@ -389,35 +389,6 @@ static int nrf5_nvmc_read_only(struct nrf5_info *chip)
return res;
}
-static int nrf5_nvmc_generic_erase(struct nrf5_info *chip,
- uint32_t erase_register, uint32_t erase_value)
-{
- int res;
-
- res = nrf5_nvmc_erase_enable(chip);
- if (res != ERROR_OK)
- goto error;
-
- res = nrf5_nvmc_write_u32(chip,
- erase_register,
- erase_value);
- if (res != ERROR_OK)
- goto set_read_only;
-
- res = nrf5_wait_for_nvmc(chip);
- if (res != ERROR_OK)
- goto set_read_only;
-
- return nrf5_nvmc_read_only(chip);
-
-set_read_only:
- nrf5_nvmc_read_only(chip);
-error:
- LOG_ERROR("Failed to erase reg: 0x%08"PRIx32" val: 0x%08"PRIx32,
- erase_register, erase_value);
- return ERROR_FAIL;
-}
-
/* nRF51 series only */
static int nrf51_protect_check_clenr0(struct flash_bank *bank)
{
@@ -900,13 +871,6 @@ static int nrf5_auto_probe(struct flash_bank *bank)
return nrf5_probe(bank);
}
-static int nrf5_erase_all(struct nrf5_info *chip)
-{
- LOG_DEBUG("Erasing all non-volatile memory");
- return nrf5_nvmc_generic_erase(chip,
- NRF5_NVMC_ERASEALL,
- 0x00000001);
-}
static int nrf5_erase_page(struct flash_bank *bank,
struct nrf5_info *chip,
@@ -938,17 +902,18 @@ static int nrf5_erase_page(struct flash_bank *bank,
}
}
- res = nrf5_nvmc_generic_erase(chip,
- NRF5_NVMC_ERASEUICR,
- 0x00000001);
-
+ res = nrf5_nvmc_write_u32(chip, NRF5_NVMC_ERASEUICR, 0x00000001);
} else {
- res = nrf5_nvmc_generic_erase(chip,
- NRF5_NVMC_ERASEPAGE,
- sector->offset);
+ res = nrf5_nvmc_write_u32(chip, NRF5_NVMC_ERASEPAGE, sector->offset);
+ }
+
+ if (res != ERROR_OK) {
+ /* caller logs the error */
+ return res;
}
+ res = nrf5_wait_for_nvmc(chip);
return res;
}
@@ -1137,13 +1102,18 @@ static int nrf5_erase(struct flash_bank *bank, unsigned int first,
return res;
}
+ res = nrf5_nvmc_erase_enable(chip);
+ if (res != ERROR_OK)
+ goto error;
+
/* For each sector to be erased */
for (unsigned int s = first; s <= last; s++) {
if (chip->features & NRF5_FEATURE_SERIES_51
&& bank->sectors[s].is_protected == 1) {
LOG_ERROR("Flash sector %d is protected", s);
- return ERROR_FLASH_PROTECTED;
+ res = ERROR_FLASH_PROTECTED;
+ break;
}
res = nrf5_erase_page(bank, chip, &bank->sectors[s]);
@@ -1153,7 +1123,9 @@ static int nrf5_erase(struct flash_bank *bank, unsigned int first,
}
}
- return ERROR_OK;
+error:
+ nrf5_nvmc_read_only(chip);
+ return res;
}
static void nrf5_free_driver_priv(struct flash_bank *bank)
@@ -1277,14 +1249,27 @@ COMMAND_HANDLER(nrf5_handle_mass_erase_command)
}
}
- res = nrf5_erase_all(chip);
+ res = nrf5_nvmc_erase_enable(chip);
+ if (res != ERROR_OK)
+ goto error;
+
+ res = nrf5_nvmc_write_u32(chip, NRF5_NVMC_ERASEALL, 0x00000001);
+ if (res != ERROR_OK) {
+ LOG_ERROR("Mass erase failed");
+ goto error;
+ }
+
+ res = nrf5_wait_for_nvmc(chip);
+ if (res != ERROR_OK)
+ LOG_ERROR("Mass erase did not complete");
+
+error:
+ nrf5_nvmc_read_only(chip);
+
if (res == ERROR_OK) {
LOG_INFO("Mass erase completed.");
if (chip->features & NRF5_FEATURE_SERIES_51)
LOG_INFO("A reset or power cycle is required if the flash was protected before.");
-
- } else {
- LOG_ERROR("Failed to erase the chip");
}
return res;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/nrf5.c | 85 ++++++++++++++++++++++------------------------------
1 file changed, 35 insertions(+), 50 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2024-06-08 09:00:26
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 37f9485cef8b98aaed739c8140b3674441dc5876 (commit)
from ed9203f4aaf3b4a28d5e28da2cdb1a52d9f7c408 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 37f9485cef8b98aaed739c8140b3674441dc5876
Author: Tomas Vanek <va...@fb...>
Date: Sun Jan 21 23:25:13 2024 +0100
flash/nor/nrf5: introduce address maps
Preparatory change before extending support to nRF53 and 91.
While on it, rename nRF51 and 52 specific routines and constants.
Change-Id: I46bc496cef5cbde46d6755a4b908c875351f6612
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8110
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index bf8c9da5f..b4a8e979e 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -19,8 +19,7 @@
#include <helper/time_support.h>
#include <helper/bits.h>
-/* Both those values are constant across the current spectrum ofr nRF5 devices */
-#define WATCHDOG_REFRESH_REGISTER 0x40010600
+/* The refresh code is constant across the current spectrum of nRF5 devices */
#define WATCHDOG_REFRESH_VALUE 0x6e524635
enum {
@@ -28,12 +27,9 @@ enum {
};
enum nrf5_ficr_registers {
- NRF5_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
+ NRF51_52_FICR_BASE = 0x10000000, /* Factory Information Configuration Registers */
-#define NRF5_FICR_REG(offset) (NRF5_FICR_BASE + offset)
-
- NRF5_FICR_CODEPAGESIZE = NRF5_FICR_REG(0x010),
- NRF5_FICR_CODESIZE = NRF5_FICR_REG(0x014),
+#define NRF5_FICR_REG(offset) (NRF51_52_FICR_BASE + (offset))
NRF51_FICR_CLENR0 = NRF5_FICR_REG(0x028),
NRF51_FICR_PPFC = NRF5_FICR_REG(0x02C),
@@ -42,39 +38,23 @@ enum nrf5_ficr_registers {
NRF51_FICR_SIZERAMBLOCK1 = NRF5_FICR_REG(0x03C),
NRF51_FICR_SIZERAMBLOCK2 = NRF5_FICR_REG(0x040),
NRF51_FICR_SIZERAMBLOCK3 = NRF5_FICR_REG(0x044),
-
- /* CONFIGID is documented on nRF51 series only.
- * On nRF52 is present but not documented */
- NRF5_FICR_CONFIGID = NRF5_FICR_REG(0x05C),
-
- /* Following registers are available on nRF52 and on nRF51 since rev 3 */
- NRF5_FICR_INFO_PART = NRF5_FICR_REG(0x100),
- NRF5_FICR_INFO_VARIANT = NRF5_FICR_REG(0x104),
- NRF5_FICR_INFO_PACKAGE = NRF5_FICR_REG(0x108),
- NRF5_FICR_INFO_RAM = NRF5_FICR_REG(0x10C),
- NRF5_FICR_INFO_FLASH = NRF5_FICR_REG(0x110),
};
enum nrf5_uicr_registers {
- NRF5_UICR_BASE = 0x10001000, /* User Information
+ NRF51_52_UICR_BASE = 0x10001000, /* User Information
* Configuration Registers */
-#define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
+#define NRF5_UICR_REG(offset) (NRF51_52_UICR_BASE + (offset))
NRF51_UICR_CLENR0 = NRF5_UICR_REG(0x000),
};
enum nrf5_nvmc_registers {
- NRF5_NVMC_BASE = 0x4001E000, /* Non-Volatile Memory
- * Controller Registers */
-
-#define NRF5_NVMC_REG(offset) (NRF5_NVMC_BASE + offset)
-
- NRF5_NVMC_READY = NRF5_NVMC_REG(0x400),
- NRF5_NVMC_CONFIG = NRF5_NVMC_REG(0x504),
- NRF5_NVMC_ERASEPAGE = NRF5_NVMC_REG(0x508),
- NRF5_NVMC_ERASEALL = NRF5_NVMC_REG(0x50C),
- NRF5_NVMC_ERASEUICR = NRF5_NVMC_REG(0x514),
+ NRF5_NVMC_READY = 0x400,
+ NRF5_NVMC_CONFIG = 0x504,
+ NRF5_NVMC_ERASEPAGE = 0x508,
+ NRF5_NVMC_ERASEALL = 0x50C,
+ NRF5_NVMC_ERASEUICR = 0x514,
NRF5_BPROT_BASE = 0x40000000,
};
@@ -110,6 +90,28 @@ struct nrf5_device_spec {
enum nrf5_features features;
};
+/* FICR registers offsets */
+struct nrf5_ficr_map {
+ uint32_t codepagesize;
+ uint32_t codesize;
+ uint32_t configid;
+ uint32_t info_part;
+ uint32_t info_variant;
+ uint32_t info_package;
+ uint32_t info_ram;
+ uint32_t info_flash;
+};
+
+/* Map of device */
+struct nrf5_map {
+ uint32_t flash_base;
+ uint32_t ficr_base;
+ uint32_t uicr_base;
+ uint32_t nvmc_base;
+
+ uint32_t watchdog_refresh_addr;
+};
+
struct nrf5_info {
unsigned int refcount;
@@ -127,6 +129,9 @@ struct nrf5_info {
enum nrf5_features features;
unsigned int flash_size_kb;
unsigned int ram_size_kb;
+
+ const struct nrf5_map *map;
+ const struct nrf5_ficr_map *ficr_offsets;
};
#define NRF51_DEVICE_DEF(id, pt, var, bcode, fsize) \
@@ -238,6 +243,31 @@ static const struct nrf5_device_package nrf52_packages_table[] = {
{ 0x2009, "CF" },
};
+static const struct nrf5_ficr_map nrf51_52_ficr_offsets = {
+ .codepagesize = 0x10,
+ .codesize = 0x14,
+
+ /* CONFIGID is documented on nRF51 series only.
+ * On nRF52 is present but not documented */
+ .configid = 0x5c,
+
+ /* Following registers are available on nRF52 and on nRF51 since rev 3 */
+ .info_part = 0x100,
+ .info_variant = 0x104,
+ .info_package = 0x108,
+ .info_ram = 0x10c,
+ .info_flash = 0x110,
+};
+
+static const struct nrf5_map nrf51_52_map = {
+ .flash_base = NRF5_FLASH_BASE,
+ .ficr_base = NRF51_52_FICR_BASE,
+ .uicr_base = NRF51_52_UICR_BASE,
+ .nvmc_base = 0x4001E000,
+
+ .watchdog_refresh_addr = 0x40010600,
+};
+
const struct flash_driver nrf5_flash, nrf51_flash;
static bool nrf5_bank_is_probed(const struct flash_bank *bank)
@@ -248,6 +278,24 @@ static bool nrf5_bank_is_probed(const struct flash_bank *bank)
return nbank->probed;
}
+static bool nrf5_bank_is_uicr(const struct nrf5_bank *nbank)
+{
+ struct nrf5_info *chip = nbank->chip;
+ assert(chip);
+
+ return nbank == &chip->bank[1];
+}
+
+static int nrf5_nvmc_read_u32(struct nrf5_info *chip, uint32_t reg_offset, uint32_t *value)
+{
+ return target_read_u32(chip->target, chip->map->nvmc_base + reg_offset, value);
+}
+
+static int nrf5_nvmc_write_u32(struct nrf5_info *chip, uint32_t reg_offset, uint32_t value)
+{
+ return target_write_u32(chip->target, chip->map->nvmc_base + reg_offset, value);
+}
+
static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
{
uint32_t ready;
@@ -256,7 +304,7 @@ static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
int64_t ts_start = timeval_ms();
do {
- res = target_read_u32(chip->target, NRF5_NVMC_READY, &ready);
+ res = nrf5_nvmc_read_u32(chip, NRF5_NVMC_READY, &ready);
if (res != ERROR_OK) {
LOG_ERROR("Error waiting NVMC_READY: generic flash write/erase error (check protection etc...)");
return res;
@@ -276,7 +324,7 @@ static int nrf5_wait_for_nvmc(struct nrf5_info *chip)
static int nrf5_nvmc_erase_enable(struct nrf5_info *chip)
{
int res;
- res = target_write_u32(chip->target,
+ res = nrf5_nvmc_write_u32(chip,
NRF5_NVMC_CONFIG,
NRF5_NVMC_CONFIG_EEN);
@@ -299,7 +347,7 @@ static int nrf5_nvmc_erase_enable(struct nrf5_info *chip)
static int nrf5_nvmc_write_enable(struct nrf5_info *chip)
{
int res;
- res = target_write_u32(chip->target,
+ res = nrf5_nvmc_write_u32(chip,
NRF5_NVMC_CONFIG,
NRF5_NVMC_CONFIG_WEN);
@@ -322,7 +370,7 @@ static int nrf5_nvmc_write_enable(struct nrf5_info *chip)
static int nrf5_nvmc_read_only(struct nrf5_info *chip)
{
int res;
- res = target_write_u32(chip->target,
+ res = nrf5_nvmc_write_u32(chip,
NRF5_NVMC_CONFIG,
NRF5_NVMC_CONFIG_REN);
@@ -350,7 +398,7 @@ static int nrf5_nvmc_generic_erase(struct nrf5_info *chip,
if (res != ERROR_OK)
goto error;
- res = target_write_u32(chip->target,
+ res = nrf5_nvmc_write_u32(chip,
erase_register,
erase_value);
if (res != ERROR_OK)
@@ -370,7 +418,8 @@ error:
return ERROR_FAIL;
}
-static int nrf5_protect_check_clenr0(struct flash_bank *bank)
+/* nRF51 series only */
+static int nrf51_protect_check_clenr0(struct flash_bank *bank)
{
int res;
uint32_t clenr0;
@@ -403,7 +452,8 @@ static int nrf5_protect_check_clenr0(struct flash_bank *bank)
return ERROR_OK;
}
-static int nrf5_protect_check_bprot(struct flash_bank *bank)
+/* nRF52 series only */
+static int nrf52_protect_check_bprot(struct flash_bank *bank)
{
struct nrf5_bank *nbank = bank->driver_priv;
assert(nbank);
@@ -432,26 +482,27 @@ static int nrf5_protect_check_bprot(struct flash_bank *bank)
static int nrf5_protect_check(struct flash_bank *bank)
{
- /* UICR cannot be write protected so just return early */
- if (bank->base == NRF5_UICR_BASE)
- return ERROR_OK;
-
struct nrf5_bank *nbank = bank->driver_priv;
assert(nbank);
struct nrf5_info *chip = nbank->chip;
assert(chip);
+ /* UICR cannot be write protected so just return early */
+ if (nrf5_bank_is_uicr(nbank))
+ return ERROR_OK;
+
if (chip->features & NRF5_FEATURE_BPROT)
- return nrf5_protect_check_bprot(bank);
+ return nrf52_protect_check_bprot(bank);
if (chip->features & NRF5_FEATURE_SERIES_51)
- return nrf5_protect_check_clenr0(bank);
+ return nrf51_protect_check_clenr0(bank);
LOG_WARNING("Flash protection of this nRF device is not supported");
return ERROR_FLASH_OPER_UNSUPPORTED;
}
-static int nrf5_protect_clenr0(struct flash_bank *bank, int set, unsigned int first,
+/* nRF51 series only */
+static int nrf51_protect_clenr0(struct flash_bank *bank, int set, unsigned int first,
unsigned int last)
{
int res;
@@ -517,8 +568,13 @@ error:
static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first,
unsigned int last)
{
+ struct nrf5_bank *nbank = bank->driver_priv;
+ assert(nbank);
+ struct nrf5_info *chip = nbank->chip;
+ assert(chip);
+
/* UICR cannot be write protected so just bail out early */
- if (bank->base == NRF5_UICR_BASE) {
+ if (nrf5_bank_is_uicr(nbank)) {
LOG_ERROR("UICR page does not support protection");
return ERROR_FLASH_OPER_UNSUPPORTED;
}
@@ -528,13 +584,8 @@ static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first,
return ERROR_TARGET_NOT_HALTED;
}
- struct nrf5_bank *nbank = bank->driver_priv;
- assert(nbank);
- struct nrf5_info *chip = nbank->chip;
- assert(chip);
-
if (chip->features & NRF5_FEATURE_SERIES_51)
- return nrf5_protect_clenr0(bank, set, first, last);
+ return nrf51_protect_clenr0(bank, set, first, last);
LOG_ERROR("Flash protection setting is not supported on this nRF5 device");
return ERROR_FLASH_OPER_UNSUPPORTED;
@@ -564,7 +615,7 @@ static const char *nrf5_decode_info_package(uint32_t package)
return "xx";
}
-static int get_nrf5_chip_type_str(const struct nrf5_info *chip, char *buf, unsigned int buf_size)
+static int nrf5_get_chip_type_str(const struct nrf5_info *chip, char *buf, unsigned int buf_size)
{
int res;
if (chip->spec) {
@@ -597,7 +648,7 @@ static int nrf5_info(struct flash_bank *bank, struct command_invocation *cmd)
assert(chip);
char chip_type_str[256];
- if (get_nrf5_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
+ if (nrf5_get_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
return ERROR_FAIL;
command_print_sameline(cmd, "%s %ukB Flash, %ukB RAM",
@@ -605,14 +656,16 @@ static int nrf5_info(struct flash_bank *bank, struct command_invocation *cmd)
return ERROR_OK;
}
-static int nrf5_read_ficr_info(struct nrf5_info *chip)
+static int nrf5_read_ficr_info(struct nrf5_info *chip, const struct nrf5_map *map,
+ const struct nrf5_ficr_map *ficr_offsets)
{
int res;
struct target *target = chip->target;
+ uint32_t ficr_base = map->ficr_base;
chip->ficr_info_valid = false;
- res = target_read_u32(target, NRF5_FICR_INFO_PART, &chip->ficr_info.part);
+ res = target_read_u32(target, ficr_base + ficr_offsets->info_part, &chip->ficr_info.part);
if (res != ERROR_OK) {
LOG_DEBUG("Couldn't read FICR INFO.PART register");
return res;
@@ -655,19 +708,19 @@ static int nrf5_read_ficr_info(struct nrf5_info *chip)
* VARIANT and PACKAGE coding is unknown for a nRF51 device.
* nRF52 devices have FICR INFO documented and always filled. */
- res = target_read_u32(target, NRF5_FICR_INFO_VARIANT, &chip->ficr_info.variant);
+ res = target_read_u32(target, ficr_base + ficr_offsets->info_variant, &chip->ficr_info.variant);
if (res != ERROR_OK)
return res;
- res = target_read_u32(target, NRF5_FICR_INFO_PACKAGE, &chip->ficr_info.package);
+ res = target_read_u32(target, ficr_base + ficr_offsets->info_package, &chip->ficr_info.package);
if (res != ERROR_OK)
return res;
- res = target_read_u32(target, NRF5_FICR_INFO_RAM, &chip->ficr_info.ram);
+ res = target_read_u32(target, ficr_base + ficr_offsets->info_ram, &chip->ficr_info.ram);
if (res != ERROR_OK)
return res;
- res = target_read_u32(target, NRF5_FICR_INFO_FLASH, &chip->ficr_info.flash);
+ res = target_read_u32(target, ficr_base + ficr_offsets->info_flash, &chip->ficr_info.flash);
if (res != ERROR_OK)
return res;
@@ -675,7 +728,8 @@ static int nrf5_read_ficr_info(struct nrf5_info *chip)
return ERROR_OK;
}
-static int nrf5_get_ram_size(struct target *target, uint32_t *ram_size)
+/* nRF51 series only */
+static int nrf51_get_ram_size(struct target *target, uint32_t *ram_size)
{
int res;
@@ -718,24 +772,33 @@ static int nrf5_probe(struct flash_bank *bank)
assert(chip);
struct target *target = chip->target;
- uint32_t configid;
- res = target_read_u32(target, NRF5_FICR_CONFIGID, &configid);
- if (res != ERROR_OK) {
- LOG_ERROR("Couldn't read CONFIGID register");
- return res;
- }
-
- /* HWID is stored in the lower two bytes of the CONFIGID register */
- chip->hwid = configid & 0xFFFF;
+ chip->spec = NULL;
/* guess a nRF51 series if the device has no FICR INFO and we don't know HWID */
chip->features = NRF5_FEATURE_SERIES_51;
+ chip->map = &nrf51_52_map;
+ chip->ficr_offsets = &nrf51_52_ficr_offsets;
/* Don't bail out on error for the case that some old engineering
* sample has FICR INFO registers unreadable. We can proceed anyway. */
- (void)nrf5_read_ficr_info(chip);
+ (void)nrf5_read_ficr_info(chip, chip->map, chip->ficr_offsets);
+
+ const struct nrf5_ficr_map *ficr_offsets = chip->ficr_offsets;
+ uint32_t ficr_base = chip->map->ficr_base;
+ uint32_t configid = 0;
+ res = target_read_u32(target, ficr_base + ficr_offsets->configid, &configid);
+ if (res != ERROR_OK) {
+ if (chip->features & NRF5_FEATURE_SERIES_51) {
+ LOG_ERROR("Couldn't read FICR CONFIGID register");
+ return res;
+ }
+
+ LOG_DEBUG("Couldn't read FICR CONFIGID register, using FICR INFO");
+ }
+
+ /* HWID is stored in the lower two bytes of the CONFIGID register */
+ chip->hwid = configid & 0xFFFF;
- chip->spec = NULL;
for (size_t i = 0; i < ARRAY_SIZE(nrf5_known_devices_table); i++) {
if (chip->hwid == nrf5_known_devices_table[i].hwid) {
chip->spec = &nrf5_known_devices_table[i];
@@ -753,15 +816,17 @@ static int nrf5_probe(struct flash_bank *bank)
if (chip->ficr_info_valid) {
chip->ram_size_kb = chip->ficr_info.ram;
- } else {
+ } else if (chip->features & NRF5_FEATURE_SERIES_51) {
uint32_t ram_size;
- nrf5_get_ram_size(target, &ram_size);
+ nrf51_get_ram_size(target, &ram_size);
chip->ram_size_kb = ram_size / 1024;
+ } else {
+ chip->ram_size_kb = 0;
}
- /* The value stored in NRF5_FICR_CODEPAGESIZE is the number of bytes in one page of FLASH. */
+ /* The value stored in FICR CODEPAGESIZE is the number of bytes in one page of FLASH. */
uint32_t flash_page_size;
- res = target_read_u32(chip->target, NRF5_FICR_CODEPAGESIZE,
+ res = target_read_u32(chip->target, ficr_base + ficr_offsets->codepagesize,
&flash_page_size);
if (res != ERROR_OK) {
LOG_ERROR("Couldn't read code page size");
@@ -769,9 +834,10 @@ static int nrf5_probe(struct flash_bank *bank)
}
/* Note the register name is misleading,
- * NRF5_FICR_CODESIZE is the number of pages in flash memory, not the number of bytes! */
+ * FICR CODESIZE is the number of pages in flash memory, not the number of bytes! */
uint32_t num_sectors;
- res = target_read_u32(chip->target, NRF5_FICR_CODESIZE, &num_sectors);
+ res = target_read_u32(chip->target, ficr_base + ficr_offsets->codesize,
+ &num_sectors);
if (res != ERROR_OK) {
LOG_ERROR("Couldn't read code memory size");
return res;
@@ -781,7 +847,7 @@ static int nrf5_probe(struct flash_bank *bank)
if (!chip->bank[0].probed && !chip->bank[1].probed) {
char chip_type_str[256];
- if (get_nrf5_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
+ if (nrf5_get_chip_type_str(chip, chip_type_str, sizeof(chip_type_str)) != ERROR_OK)
return ERROR_FAIL;
const bool device_is_unknown = (!chip->spec && !chip->ficr_info_valid);
LOG_INFO("%s%s %ukB Flash, %ukB RAM",
@@ -793,7 +859,7 @@ static int nrf5_probe(struct flash_bank *bank)
free(bank->sectors);
- if (bank->base == NRF5_FLASH_BASE) {
+ if (bank->base == chip->map->flash_base) {
/* Sanity check */
if (chip->spec && chip->flash_size_kb != chip->spec->flash_size_kb)
LOG_WARNING("Chip's reported Flash capacity does not match expected one");
@@ -810,6 +876,7 @@ static int nrf5_probe(struct flash_bank *bank)
chip->bank[0].probed = true;
} else {
+ /* UICR bank */
bank->num_sectors = 1;
bank->size = flash_page_size;
@@ -849,7 +916,7 @@ static int nrf5_erase_page(struct flash_bank *bank,
LOG_DEBUG("Erasing page at 0x%"PRIx32, sector->offset);
- if (bank->base == NRF5_UICR_BASE) {
+ if (bank->base == chip->map->uicr_base) {
if (chip->features & NRF5_FEATURE_SERIES_51) {
uint32_t ppfc;
res = target_read_u32(chip->target, NRF51_FICR_PPFC,
@@ -958,7 +1025,7 @@ static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const u
buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
buf_set_u32(reg_params[3].value, 0, 32, address);
buf_set_u32(reg_params[4].value, 0, 32, WATCHDOG_REFRESH_VALUE);
- buf_set_u32(reg_params[5].value, 0, 32, WATCHDOG_REFRESH_REGISTER);
+ buf_set_u32(reg_params[5].value, 0, 32, chip->map->watchdog_refresh_addr);
retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
0, NULL,
@@ -1008,7 +1075,7 @@ static int nrf5_write(struct flash_bank *bank, const uint8_t *buffer,
* is protected. */
if (chip->features & NRF5_FEATURE_SERIES_51) {
- res = nrf5_protect_check_clenr0(bank);
+ res = nrf51_protect_check_clenr0(bank);
if (res != ERROR_OK)
return res;
@@ -1065,7 +1132,7 @@ static int nrf5_erase(struct flash_bank *bank, unsigned int first,
* is protected. */
if (chip->features & NRF5_FEATURE_SERIES_51) {
- res = nrf5_protect_check_clenr0(bank);
+ res = nrf51_protect_check_clenr0(bank);
if (res != ERROR_OK)
return res;
}
@@ -1136,7 +1203,7 @@ FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
switch (bank->base) {
case NRF5_FLASH_BASE:
- case NRF5_UICR_BASE:
+ case NRF51_52_UICR_BASE:
break;
default:
LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
@@ -1157,7 +1224,7 @@ FLASH_BANK_COMMAND_HANDLER(nrf5_flash_bank_command)
case NRF5_FLASH_BASE:
nbank = &chip->bank[0];
break;
- case NRF5_UICR_BASE:
+ case NRF51_52_UICR_BASE:
nbank = &chip->bank[1];
break;
}
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/nrf5.c | 237 +++++++++++++++++++++++++++++++++------------------
1 file changed, 152 insertions(+), 85 deletions(-)
hooks/post-receive
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From: openocd-gerrit <ope...@us...> - 2024-06-08 08:51:49
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via ed9203f4aaf3b4a28d5e28da2cdb1a52d9f7c408 (commit)
from 1fba55a9b62118ac102c161bb8efcd2ceed379a1 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit ed9203f4aaf3b4a28d5e28da2cdb1a52d9f7c408
Author: Paul Fertser <fer...@gm...>
Date: Thu Apr 25 14:33:07 2024 +0300
gdb_server: do not start multiple instances on "pipe"
For configurations which include multiple targets and the "pipe" mode is
requested only the first gdb_server instance should be enabled,
otherwise GDB gets confusing replies, goes out of sync and the session
fails in weird ways.
Compile-tested only.
Signed-off-by: Paul Fertser <fer...@gm...>
Change-Id: If8f13aa7b58e9b0dc6d5ae88cf75538b34cc1218
Reviewed-on: https://review.openocd.org/c/openocd/+/8222
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 7c2f41e41..0ded8e440 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -3879,7 +3879,7 @@ static int gdb_target_add_one(struct target *target)
return gdb_target_start(target, target->gdb_port_override);
}
- if (strcmp(gdb_port, "disabled") == 0) {
+ if (strcmp(gdb_port_next, "disabled") == 0) {
LOG_INFO("gdb port disabled");
return ERROR_OK;
}
@@ -3908,6 +3908,8 @@ static int gdb_target_add_one(struct target *target)
gdb_port_next = strdup("0");
}
}
+ } else if (strcmp(gdb_port_next, "pipe") == 0) {
+ gdb_port_next = "disabled";
}
}
return retval;
-----------------------------------------------------------------------
Summary of changes:
src/server/gdb_server.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
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--
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From: openocd-gerrit <ope...@us...> - 2024-06-08 08:51:19
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 1fba55a9b62118ac102c161bb8efcd2ceed379a1 (commit)
from 0a3217b8ff34043e6c59850e5d7667edf97ec447 (commit)
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- Log -----------------------------------------------------------------
commit 1fba55a9b62118ac102c161bb8efcd2ceed379a1
Author: Marc Schink <de...@za...>
Date: Sat Jun 1 10:41:29 2024 +0200
flash/nor/tcl: Fix memory leak of flash bank name
Change-Id: I54cd1ee479a0570ae849a71be47c82eebd1ae454
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8303
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
index 720fb60a1..6ac932be7 100644
--- a/src/flash/nor/tcl.c
+++ b/src/flash/nor/tcl.c
@@ -1298,6 +1298,7 @@ COMMAND_HANDLER(handle_flash_bank_command)
if (retval != ERROR_OK) {
LOG_ERROR("'%s' driver rejected flash bank at " TARGET_ADDR_FMT
"; usage: %s", driver_name, c->base, driver->usage);
+ free(c->name);
free(c);
return retval;
}
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/tcl.c | 1 +
1 file changed, 1 insertion(+)
hooks/post-receive
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From: openocd-gerrit <ope...@us...> - 2024-06-08 08:46:49
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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via 84126893ff9305060b7d481ebf50e8c7405d7eae (commit)
from d382c95d57c0ad9ed2dcc83c95404babb7647708 (commit)
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- Log -----------------------------------------------------------------
commit 0a3217b8ff34043e6c59850e5d7667edf97ec447
Author: Marc Schink <de...@za...>
Date: Sat May 25 18:57:10 2024 +0200
tcl/board: Add config for NXP FRDM-KV31F
Change-Id: I4d7cd1bcadd8159e4830107c2788708aef02add0
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8299
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/board/nxp/frdm-kv31f-jlink.cfg b/tcl/board/nxp/frdm-kv31f-jlink.cfg
new file mode 100644
index 000000000..e55a01cd7
--- /dev/null
+++ b/tcl/board/nxp/frdm-kv31f-jlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration file for NXP FRDM-KV31F development boards.
+#
+# This configuration file is only for FRDM-KV31F development boards with the
+# SEGGER J-Link OpenSDA firmware, see:
+# https://www.segger.com/products/debug-probes/j-link/models/other-j-links/opensda-sda-v2/
+
+source [find interface/jlink.cfg]
+
+# Set working area size to 32 KiB.
+set WORKAREASIZE 0x8000
+
+# Set the chip name.
+set CHIPNAME kv31f
+
+transport select swd
+
+source [find target/kx.cfg]
+
+reset_config srst_only
commit 84126893ff9305060b7d481ebf50e8c7405d7eae
Author: Marc Schink <de...@za...>
Date: Sat May 25 18:55:23 2024 +0200
tcl/board: Add config for NXP FRDM-KV11Z
Change-Id: I9cd497a085f8f9c7854ae3b96e60a73b3b050d0e
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8298
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/tcl/board/nxp/frdm-kv11z-jlink.cfg b/tcl/board/nxp/frdm-kv11z-jlink.cfg
new file mode 100644
index 000000000..725a37b9e
--- /dev/null
+++ b/tcl/board/nxp/frdm-kv11z-jlink.cfg
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Configuration file for NXP FRDM-KV11Z development boards.
+#
+# This configuration file is only for FRDM-KV11Z development boards with the
+# SEGGER J-Link OpenSDA firmware, see:
+# https://www.segger.com/products/debug-probes/j-link/models/other-j-links/opensda-sda-v2/
+
+source [find interface/jlink.cfg]
+
+# Set working area size to 16 KiB.
+set WORKAREASIZE 0x4000
+
+# Set the chip name.
+set CHIPNAME kv11z
+
+transport select swd
+
+source [find target/kx.cfg]
+
+reset_config srst_only
-----------------------------------------------------------------------
Summary of changes:
tcl/board/nxp/frdm-kv11z-jlink.cfg | 21 +++++++++++++++++++++
tcl/board/nxp/frdm-kv31f-jlink.cfg | 21 +++++++++++++++++++++
2 files changed, 42 insertions(+)
create mode 100644 tcl/board/nxp/frdm-kv11z-jlink.cfg
create mode 100644 tcl/board/nxp/frdm-kv31f-jlink.cfg
hooks/post-receive
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From: openocd-gerrit <ope...@us...> - 2024-06-08 08:46:09
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from 2f8bb252ffb89cb2019f634230bc17b4dfccc75a (commit)
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commit d382c95d57c0ad9ed2dcc83c95404babb7647708
Author: Parshintsev Anatoly <ana...@sy...>
Date: Thu Jun 22 19:28:52 2023 +0300
target/riscv: support for smp group manipulation
this functionality allows to query if a target belongs to some smp group
and to dynamically turn on/off smp-specific behavior
Change-Id: I67bafb1817c621a38ae4a2f55e12e4143e992c4e
Signed-off-by: Parshintsev Anatoly <ana...@sy...>
Signed-off-by: Bernhard Rosenkränzer <be...@ba...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8296
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 87e3650b4..b782e0ba9 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -11278,6 +11278,18 @@ When utilizing version 0.11 of the RISC-V Debug Specification,
and DBUS registers, respectively.
@end deffn
+@deffn {Command} {riscv smp} [on|off]
+Display, enable or disable SMP handling mode. This command is needed only if
+user wants to temporary @b{disable} SMP handling for an existing SMP group
+(see @code{aarch64 smp} for additional information). To define an SMP
+group the command @code{target smp} should be used.
+@end deffn
+
+@deffn {Command} {riscv smp_gdb} [core_id]
+Display/set the current core displayed in GDB. This is needed only if
+@code{riscv smp} was used.
+@end deffn
+
@deffn {Command} {riscv use_bscan_tunnel} value
Enable or disable use of a BSCAN tunnel to reach the Debug Module. Supply the
width of the DM transport TAP's instruction register to enable. Supply a
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 9cd4922d2..511a3c6c3 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -3049,6 +3049,9 @@ static const struct command_registration riscv_command_handlers[] = {
.usage = "",
.chain = semihosting_common_handlers
},
+ {
+ .chain = smp_command_handlers
+ },
COMMAND_REGISTRATION_DONE
};
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 12 ++++++++++++
src/target/riscv/riscv.c | 3 +++
2 files changed, 15 insertions(+)
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From: openocd-gerrit <ope...@us...> - 2024-06-08 08:45:31
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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via 9623069e8090fbbf80250836e82feaecdb65233e (commit)
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- Log -----------------------------------------------------------------
commit 2f8bb252ffb89cb2019f634230bc17b4dfccc75a
Author: Tim Newsome <ti...@si...>
Date: Mon Sep 21 14:10:27 2020 -0700
doc: Minimally describe the BSCAN tunnel interface.
Add minimal documentation for the BSCAN tunnel interface.
This is based on Tim Newsome <ti...@si...>'s work on
the RISC-V fork.
Change-Id: I5e0cd6972cb90649670249765e9bb30c2847eea6
Signed-off-by: Tim Newsome <ti...@si...>
Signed-off-by: Bernhard Rosenkränzer <be...@ba...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8297
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 5eef81e40..87e3650b4 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -11279,8 +11279,22 @@ and DBUS registers, respectively.
@end deffn
@deffn {Command} {riscv use_bscan_tunnel} value
-Enable or disable use of a BSCAN tunnel to reach DM. Supply the width of
-the DM transport TAP's instruction register to enable. Supply a value of 0 to disable.
+Enable or disable use of a BSCAN tunnel to reach the Debug Module. Supply the
+width of the DM transport TAP's instruction register to enable. Supply a
+value of 0 to disable.
+
+This BSCAN tunnel interface is specific to SiFive IP. Anybody may implement
+it, but currently there is no good documentation on it. In a nutshell, this
+feature scans USER4 into a Xilinx TAP to select the tunnel device (assuming
+hardware is present and it is hooked up to the Xilinx USER4 IR) and
+encapsulates a tunneled scan directive into a DR scan into the Xilinx TAP. A
+tunneled DR scan consists of:
+@enumerate
+@item 1 bit that selects IR when 0, or DR when 1
+@item 7 bits that encode the width of the desired tunneled scan
+@item A width+1 stream of bits for the tunneled TDI. The plus one is because there is a one-clock skew between TDI of Xilinx chain and TDO from tunneled chain.
+@item 3 bits of zero that the tunnel uses to go back to idle state.
+@end enumerate
@end deffn
@deffn {Command} {riscv set_ebreakm} on|off
commit 9623069e8090fbbf80250836e82feaecdb65233e
Author: Mark Featherston <ma...@em...>
Date: Thu May 23 13:24:32 2024 -0700
jtag/drivers/ftdi: Use command_print instead of LOG_USER for get_signal
LOG_USER only outputs to user interfaces, but leaves no way to get the
FTDI inputs over the RPC interface. Switch to command_print so this
string goes to both logs and the RPC interface.
Change-Id: I99024194b6687b88d354ef278aa25f372c862c22
Signed-off-by: Mark Featherston <ma...@em...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8294
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
Reviewed-by: zapb <de...@za...>
diff --git a/src/jtag/drivers/ftdi.c b/src/jtag/drivers/ftdi.c
index 58f83af59..661300506 100644
--- a/src/jtag/drivers/ftdi.c
+++ b/src/jtag/drivers/ftdi.c
@@ -852,7 +852,7 @@ COMMAND_HANDLER(ftdi_handle_get_signal_command)
uint16_t sig_data = 0;
sig = find_signal_by_name(CMD_ARGV[0]);
if (!sig) {
- LOG_ERROR("interface configuration doesn't define signal '%s'", CMD_ARGV[0]);
+ command_print(CMD, "interface configuration doesn't define signal '%s'", CMD_ARGV[0]);
return ERROR_FAIL;
}
@@ -860,7 +860,7 @@ COMMAND_HANDLER(ftdi_handle_get_signal_command)
if (ret != ERROR_OK)
return ret;
- LOG_USER("Signal %s = %#06x", sig->name, sig_data);
+ command_print(CMD, "%#06x", sig_data);
return ERROR_OK;
}
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 18 ++++++++++++++++--
src/jtag/drivers/ftdi.c | 4 ++--
2 files changed, 18 insertions(+), 4 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2024-06-08 08:45:05
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 72b39088ee1772a65e74004fdc096db09edf8c0c (commit)
from b5e7118048250a4ffc589fd8b82a11de05132d23 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 72b39088ee1772a65e74004fdc096db09edf8c0c
Author: Antonio Borneo <bor...@gm...>
Date: Mon Apr 8 17:42:52 2024 +0200
target: reset examine after assert_reset
For some target, the API assert_reset() checks if the target has
been examined, with target_was_examined(), to perform conditional
operations like:
- assert adapter's srst;
- write some register to catch the reset vector;
- invalidate the register cache.
Targets created with -defer-examine gets the examine flag reset
right before entering in their assert_reset(), disrupting the
actions above.
For targets created with -defer-examine, move the reset examine
after the assert_reset().
Change-Id: If96e7876dcace8905165115292deb93a3e45cb36
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8293
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/target/target.c b/src/target/target.c
index efc168903..7d4947a6e 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -5365,17 +5365,19 @@ COMMAND_HANDLER(handle_target_reset)
return ERROR_FAIL;
}
- if (target->defer_examine)
- target_reset_examined(target);
-
/* determine if we should halt or not. */
target->reset_halt = (a != 0);
/* When this happens - all workareas are invalid. */
target_free_all_working_areas_restore(target, 0);
/* do the assert */
- if (n->value == NVP_ASSERT)
- return target->type->assert_reset(target);
+ if (n->value == NVP_ASSERT) {
+ int retval = target->type->assert_reset(target);
+ if (target->defer_examine)
+ target_reset_examined(target);
+ return retval;
+ }
+
return target->type->deassert_reset(target);
}
-----------------------------------------------------------------------
Summary of changes:
src/target/target.c | 12 +++++++-----
1 file changed, 7 insertions(+), 5 deletions(-)
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--
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From: openocd-gerrit <ope...@us...> - 2024-06-08 08:44:30
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via b5e7118048250a4ffc589fd8b82a11de05132d23 (commit)
via 7050cade9dcea77dd9882669ea97fddc6a8084d4 (commit)
from 223e3d8fe76d86f01111bbe37f83a19d719ac81a (commit)
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- Log -----------------------------------------------------------------
commit b5e7118048250a4ffc589fd8b82a11de05132d23
Author: Noah Moroze <noa...@gm...>
Date: Wed May 15 22:50:58 2024 -0400
src/helper/startup: fix syntax errors
The missing closing brackets were caught by tclint v0.2.5
(https://github.com/nmoroze/tclint):
```
tclint src/helper/startup.tcl | grep "syntax error"
```
The improperly escaped backslash was caught by manual inspection during
code review.
Change-Id: I8cd44e58040d4627f6b2fc8b88ca8a930cda0ba6
Signed-off-by: Noah Moroze <noa...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8282
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/helper/startup.tcl b/src/helper/startup.tcl
index 5a0d479f5..e6e76e68f 100644
--- a/src/helper/startup.tcl
+++ b/src/helper/startup.tcl
@@ -11,10 +11,10 @@ proc find {filename} {
if {[catch {ocd_find $filename} t]==0} {
return $t
}
- if {[catch {ocd_find [string map {\ /} $filename} t]==0} {
+ if {[catch {ocd_find [string map {\\ /} $filename]} t]==0} {
return $t
}
- if {[catch {ocd_find [string map {/ \\} $filename} t]==0} {
+ if {[catch {ocd_find [string map {/ \\} $filename]} t]==0} {
return $t
}
# make sure error message matches original input string
commit 7050cade9dcea77dd9882669ea97fddc6a8084d4
Author: Noah Moroze <noa...@gm...>
Date: Wed May 15 22:49:23 2024 -0400
tcl/chip/st/spear: fix syntax errors
While the current jimtcl does not consider this an error, the Tcl
dodekalogue states that strings terminate at the second double quote
character (see https://www.tcl.tk/man/tcl/TclCmd/Tcl.htm#M8).
These syntax errors were caught by tclint v0.2.5
(https://github.com/nmoroze/tclint):
```
tclint tcl/chip/st/spear/spear3xx_ddr.tcl | grep "syntax error"
```
Change-Id: I2763d93095e3db7590644652f16b7b24939d6cae
Signed-off-by: Noah Moroze <noa...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8281
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/chip/st/spear/spear3xx_ddr.tcl b/tcl/chip/st/spear/spear3xx_ddr.tcl
index 59925672d..06962215b 100644
--- a/tcl/chip/st/spear/spear3xx_ddr.tcl
+++ b/tcl/chip/st/spear/spear3xx_ddr.tcl
@@ -10,7 +10,7 @@
proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} {
if { $ddr_chips != 1 && $ddr_chips != 2 } {
- error "Only 1 or 2 DDR chips permitted. Wrong value "$ddr_chips
+ error "Only 1 or 2 DDR chips permitted. Wrong value $ddr_chips"
}
if { $ddr_type == "mt47h64m16_3_333_cl5_async" } {
@@ -21,7 +21,7 @@ proc sp3xx_ddr_init {ddr_type {ddr_chips 1}} {
# ????? $ddr_chips
# set ddr_size 0x?????
} else {
- error "sp3xx_ddr_init: unrecognized DDR type "$ddr_type
+ error "sp3xx_ddr_init: unrecognized DDR type $ddr_type"
}
# MPMC START
-----------------------------------------------------------------------
Summary of changes:
src/helper/startup.tcl | 4 ++--
tcl/chip/st/spear/spear3xx_ddr.tcl | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2024-06-08 08:44:02
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 223e3d8fe76d86f01111bbe37f83a19d719ac81a (commit)
from eecba412cd8a6d515c925d87fe53e79881305517 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 223e3d8fe76d86f01111bbe37f83a19d719ac81a
Author: Noah Moroze <noa...@gm...>
Date: Wed May 15 22:47:53 2024 -0400
tcl/target/c100helper: fix syntax errors
Fixes: 64d89d5ee1a5 ("tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change")
These syntax errors were caught by tclint v0.2.5
(https://github.com/nmoroze/tclint):
```
tclint tcl/target/c100helper.tcl | grep "syntax error"
```
Change-Id: I511c54353c4853560adca6b4852d48df2aade283
Signed-off-by: Noah Moroze <noa...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8280
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/tcl/target/c100helper.tcl b/tcl/target/c100helper.tcl
index d1d3f258b..ba0e4fe0a 100644
--- a/tcl/target/c100helper.tcl
+++ b/tcl/target/c100helper.tcl
@@ -176,7 +176,7 @@ proc setupAmbaClk {} {
mmw $CLKCORE_AHB_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
# wait for PLL to lock
echo "Waiting for Amba PLL to lock"
- while {[expr {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK]} == 0} { sleep 1 }
+ while {[mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK == 0} { sleep 1 }
# remove the internal PLL bypass
mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
# remove PLL from BYPASS mode using MUX
@@ -250,7 +250,7 @@ proc setupArmClk {} {
mmw $CLKCORE_ARM_CLK_CNTRL [expr {($x << 16) + ($w << 8) + $y}] 0x0
# wait for PLL to lock
echo "Waiting for Amba PLL to lock"
- while {[expr {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK]} == 0} { sleep 1 }
+ while {[mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK == 0} { sleep 1 }
# remove the internal PLL bypass
mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
# remove PLL from BYPASS mode using MUX
-----------------------------------------------------------------------
Summary of changes:
tcl/target/c100helper.tcl | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2024-06-08 08:42:59
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via eecba412cd8a6d515c925d87fe53e79881305517 (commit)
from c7c4d4d48c63c1048414779f633641ea4e9657c8 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit eecba412cd8a6d515c925d87fe53e79881305517
Author: Noah Moroze <noa...@gm...>
Date: Wed May 15 22:39:12 2024 -0400
tcl/memory: fix syntax errors
Using a command in an expression requires a bracketed command
substitution.
These syntax errors were caught by tclint v0.2.5
(https://github.com/nmoroze/tclint):
```
tclint tcl/memory.tcl | grep "syntax error"
```
Change-Id: I510d46222f4fb02d6ef73121b231d5b2df77e5c0
Signed-off-by: Noah Moroze <noa...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8279
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/tcl/memory.tcl b/tcl/memory.tcl
index b11174995..8b93b515e 100644
--- a/tcl/memory.tcl
+++ b/tcl/memory.tcl
@@ -66,10 +66,10 @@ proc iswithin { ADDRESS BASE LEN } {
proc address_info { ADDRESS } {
foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } {
- if { info exists $WHERE } {
+ if { [info exists $WHERE] } {
set lmt [set N_[set WHERE]]
for { set region 0 } { $region < $lmt } { incr region } {
- if { iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN) } {
+ if { [iswithin $ADDRESS $WHERE($region,BASE) $WHERE($region,LEN)] } {
return "$WHERE $region";
}
}
-----------------------------------------------------------------------
Summary of changes:
tcl/memory.tcl | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2024-06-08 08:42:29
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via c7c4d4d48c63c1048414779f633641ea4e9657c8 (commit)
from 71013521d7b195022616284aabc5e072a60c52bf (commit)
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revisions in full, below.
- Log -----------------------------------------------------------------
commit c7c4d4d48c63c1048414779f633641ea4e9657c8
Author: Marc Schink <de...@za...>
Date: Mon May 20 11:32:19 2024 +0200
contrib: Drop 'coresight-trace.txt'
This document is outdated and has broken text formatting. It also
provides no useful information to users nor developers, at worst it
causes confusion. For that reason, drop this file.
Change-Id: Id5ee1f6e74d1a641c60d897f114bb97f5fd48e5b
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8292
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/contrib/coresight-trace.txt b/contrib/coresight-trace.txt
deleted file mode 100644
index 517119b6f..000000000
--- a/contrib/coresight-trace.txt
+++ /dev/null
@@ -1,68 +0,0 @@
-+OpenOCD and CoreSight Tracing
-+
-Many recent ARM chips (Using e..g. Cortex-M3 and
-Cortex-M4 cores) support CoreSight debug/trace.
-This note sketches an approach currently planned for those cores
-with OpenOCD.
-
- This tracing data can help debug and tune ARM software, but not
-all cores support tracing. Some support more extensive tracing
-other cores with trace support +should be able to use the same
-approach and maybe some of the same analysis code.
-
-+the Cortex-M3 is assumed here to be the
-+core in use, for simplicity and to reflect current OpenOCD users.
-
-
-This note summarizes a software model to generate, collect, and
-analyze such trace data . That is not fully implemented as of early
-January 2011, +and thus is not *yet* usable.
-+
-+
-+Some microcontroller cores support a low pin-count Single-wire trace,
-with a mode where +trace data is emitted (usually to a UART. To use
-this mode, +SWD must be in use.
-+At this writing, OpenOCD SWD support is not yet complete either.
-
-(There are also multi-wire trace ports requiring more complex debug
-adapters than OpenOCD currently supports, and offering richer data.
-+
-+
-+* ENABLING involves activating SWD and (single wire) trace.
-+
-+current expectations are that OpenOCD itself will handle enabling;
-activating single wire trace involves a debug adapter interaction, and
-collecting that trace data requires particular (re)wiring.
-+
-+* CONFIGURATION involves setting up ITM and/or ETM modules to emit the
-+desired data from the Cortex core. (This might include dumping
-+event counters printf-style messages; code profiling; and more. Not all
-+cores offer the same trace capabilities.
-+
-+current expectations are that Tcl scripts will be used to configure these
-+modules for the desired tracing, by direct writes to registers. In some
-+cases (as with RTOS event tracking and similar messaging, this might
-+be augmented or replaced by user code running on the ARM core.
-+
-+COLLECTION involves reading that trace data, probably through UART, and
-+saving it in a useful format to analyse For now, deferred analysis modes
-are assumed, not than real-time or interactive ones.
-+
-+
-+current expectations are to to dump data in text using contrib/itmdump.c
-+or derived tools, and to post-process it into reports. Such reports might
-+include program messaging (such as application data streams via ITM, maybe
-+using printf type messaging; code coverage analysis or so forth. Recent
-+versions of CMSIS software reserve some ITM codespace for RTOS event
-tracing and include ITM messaging support.
-Clearly some of that data would be valuable for interactive debugging.
-+
-+Should someone get ambitious, GUI reports should be possible. GNU tools
-+for simpler reports like gprof may be simpler to support at first.
-+In any case, OpenOCD is not currently GUI-oriented. Accordingly, we now
-+expect any such graphics to come from postprocessing.
-
- measurements for RTOS event timings should also be easy to collect.
-+Examples include context and message switch times, as well as times
-for application interactions.
-+
-----------------------------------------------------------------------
Summary of changes:
contrib/coresight-trace.txt | 68 ---------------------------------------------
1 file changed, 68 deletions(-)
delete mode 100644 contrib/coresight-trace.txt
hooks/post-receive
--
Main OpenOCD repository
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|
From: openocd-gerrit <ope...@us...> - 2024-06-08 08:39:07
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 71013521d7b195022616284aabc5e072a60c52bf (commit)
from 437dde701c13e707e5fd912ef6403e09052e4d9b (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 71013521d7b195022616284aabc5e072a60c52bf
Author: Antonio Borneo <bor...@gm...>
Date: Fri May 3 23:04:46 2024 +0200
server: gdb: respect command gdb_report_register_access_error
Commit 236c54c94a53 ("server/gdb_server.c: support unavailable
registers") correctly returns a string of 'x' when the register is
not available in the current target.
While implementing this, it incorrectly drops the pre-existing
feature of optionally ignoring errors while reading a register.
This feature has a real use case documented in the OpenOCD manual
in chapter 'Using GDB as a non-intrusive memory inspector', where
GDB attaches to a target without halting it. For targets that need
to be halted to read its registers, we need to hack the values of
the registers returned to GDB; either returning 'xxxx' or an error
causes GDB to drop the connection.
Re-add the check on 'gdb_report_register_access_error' to keep the
pre-existing behavior when a register error has to be ignored:
- return a string of '0';
- drop a debug message.
Change-Id: Ie65c92f259f92502e688914f334655b635874179
Signed-off-by: Antonio Borneo <bor...@gm...>
Fixes: 236c54c94a53 ("server/gdb_server.c: support unavailable registers")
Reviewed-on: https://review.openocd.org/c/openocd/+/8228
Tested-by: jenkins
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 5052bf43b..7c2f41e41 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -1233,6 +1233,8 @@ static int gdb_get_reg_value_as_str(struct target *target, char *tstr, struct re
tstr[len] = '\0';
return ERROR_OK;
}
+ memset(tstr, '0', len);
+ tstr[len] = '\0';
return ERROR_FAIL;
}
@@ -1277,7 +1279,9 @@ static int gdb_get_registers_packet(struct connection *connection,
for (i = 0; i < reg_list_size; i++) {
if (!reg_list[i] || reg_list[i]->exist == false || reg_list[i]->hidden)
continue;
- if (gdb_get_reg_value_as_str(target, reg_packet_p, reg_list[i]) != ERROR_OK) {
+ retval = gdb_get_reg_value_as_str(target, reg_packet_p, reg_list[i]);
+ if (retval != ERROR_OK && gdb_report_register_access_error) {
+ LOG_DEBUG("Couldn't get register %s.", reg_list[i]->name);
free(reg_packet);
free(reg_list);
return gdb_error(connection, retval);
@@ -1395,7 +1399,9 @@ static int gdb_get_register_packet(struct connection *connection,
reg_packet = calloc(DIV_ROUND_UP(reg_list[reg_num]->size, 8) * 2 + 1, 1); /* plus one for string termination null */
- if (gdb_get_reg_value_as_str(target, reg_packet, reg_list[reg_num]) != ERROR_OK) {
+ retval = gdb_get_reg_value_as_str(target, reg_packet, reg_list[reg_num]);
+ if (retval != ERROR_OK && gdb_report_register_access_error) {
+ LOG_DEBUG("Couldn't get register %s.", reg_list[reg_num]->name);
free(reg_packet);
free(reg_list);
return gdb_error(connection, retval);
-----------------------------------------------------------------------
Summary of changes:
src/server/gdb_server.c | 10 ++++++++--
1 file changed, 8 insertions(+), 2 deletions(-)
hooks/post-receive
--
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|
From: openocd-gerrit <ope...@us...> - 2024-05-11 11:56:24
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 2c8376b79d104a855bd3a559e59edf330309bcad (commit)
from 22ddf62d759b10a89e9c4c3f3929a66c9d72572d (commit)
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- Log -----------------------------------------------------------------
commit 2c8376b79d104a855bd3a559e59edf330309bcad
Author: Ian Thompson <ia...@ca...>
Date: Wed Jan 31 15:14:25 2024 -0800
target/xtensa: avoid IHI for writes to non-executable memory
For MPU configs, determine memory access rights
by probing protection TLB. Issuing IHI without execute
permissions can trigger an exception.
No new clang static analyzer warnings.
Change-Id: Iea8eab5c2113df3f954285c3b9a79e96d41aa941
Signed-off-by: Ian Thompson <ia...@ca...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8080
Reviewed-by: Erhan Kurubas <erh...@es...>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index fb7748aa2..f7c82efed 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -158,6 +158,12 @@
#define XT_INS_RFWU(X) (XT_ISBE(X) ? 0x005300 << 8 : 0x003500)
#define XT_INS_RFWO_RFWU_MASK(X) (XT_ISBE(X) ? 0xFFFFFF << 8 : 0xFFFFFF)
+/* Read Protection TLB Entry Info */
+#define XT_INS_PPTLB(X, S, T) _XT_INS_FORMAT_RRR(X, 0x500000, ((S) << 4) | (T), 0xD)
+
+#define XT_TLB1_ACC_SHIFT 8
+#define XT_TLB1_ACC_MSK 0xF
+
#define XT_WATCHPOINTS_NUM_MAX 2
/* Special register number macro for DDR, PS, WB, A3, A4 registers.
@@ -298,6 +304,27 @@ enum xtensa_mem_region_type {
XTENSA_MEM_REGS_NUM
};
+/**
+ * Types of access rights for MPU option
+ * The first block is kernel RWX ARs; the second block is user rwx ARs.
+ */
+enum xtensa_mpu_access_type {
+ XTENSA_ACC_00X_000 = 0x2,
+ XTENSA_ACC_000_00X,
+ XTENSA_ACC_R00_000,
+ XTENSA_ACC_R0X_000,
+ XTENSA_ACC_RW0_000,
+ XTENSA_ACC_RWX_000,
+ XTENSA_ACC_0W0_0W0,
+ XTENSA_ACC_RW0_RWX,
+ XTENSA_ACC_RW0_R00,
+ XTENSA_ACC_RWX_R0X,
+ XTENSA_ACC_R00_R00,
+ XTENSA_ACC_R0X_R0X,
+ XTENSA_ACC_RW0_RW0,
+ XTENSA_ACC_RWX_RWX
+};
+
/* Register definition as union for list allocation */
union xtensa_reg_val_u {
xtensa_reg_val_t val;
@@ -521,6 +548,44 @@ static void xtensa_queue_exec_ins_wide(struct xtensa *xtensa, uint8_t *ops, uint
}
}
+/* NOTE: Assumes A3 has already been saved and marked dirty; A3 will be clobbered */
+static inline bool xtensa_region_ar_exec(struct target *target, target_addr_t start, target_addr_t end)
+{
+ struct xtensa *xtensa = target_to_xtensa(target);
+ if (xtensa->core_config->mpu.enabled) {
+ /* For cores with the MPU option, issue PPTLB on start and end addresses.
+ * Parse access rights field, and confirm both have execute permissions.
+ */
+ for (int i = 0; i <= 1; i++) {
+ uint32_t at, acc;
+ uint8_t at_buf[4];
+ bool exec_acc;
+ target_addr_t addr = i ? end : start;
+ xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, addr);
+ xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
+ xtensa_queue_exec_ins(xtensa, XT_INS_PPTLB(xtensa, XT_REG_A3, XT_REG_A3));
+ xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3));
+ xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, at_buf);
+ int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
+ if (res != ERROR_OK)
+ LOG_TARGET_ERROR(target, "Error queuing PPTLB: %d", res);
+ res = xtensa_core_status_check(target);
+ if (res != ERROR_OK)
+ LOG_TARGET_ERROR(target, "Error issuing PPTLB: %d", res);
+ at = buf_get_u32(at_buf, 0, 32);
+ acc = (at >> XT_TLB1_ACC_SHIFT) & XT_TLB1_ACC_MSK;
+ exec_acc = ((acc == XTENSA_ACC_00X_000) || (acc == XTENSA_ACC_R0X_000) ||
+ (acc == XTENSA_ACC_RWX_000) || (acc == XTENSA_ACC_RWX_R0X) ||
+ (acc == XTENSA_ACC_R0X_R0X) || (acc == XTENSA_ACC_RWX_RWX));
+ LOG_TARGET_DEBUG(target, "PPTLB(" TARGET_ADDR_FMT ") -> 0x%08" PRIx32 " exec_acc %d",
+ addr, at, exec_acc);
+ if (!exec_acc)
+ return false;
+ }
+ }
+ return true;
+}
+
static int xtensa_queue_pwr_reg_write(struct xtensa *xtensa, unsigned int reg, uint32_t data)
{
struct xtensa_debug_module *dm = &xtensa->dbg_mod;
@@ -2176,11 +2241,13 @@ int xtensa_write_memory(struct target *target,
}
} else {
/* Invalidate ICACHE, writeback DCACHE if present */
- uint32_t issue_ihi = xtensa_is_icacheable(xtensa, address);
- uint32_t issue_dhwb = xtensa_is_dcacheable(xtensa, address);
- if (issue_ihi || issue_dhwb) {
+ bool issue_ihi = xtensa_is_icacheable(xtensa, address) &&
+ xtensa_region_ar_exec(target, addrstart_al, addrend_al);
+ bool issue_dhwbi = xtensa_is_dcacheable(xtensa, address);
+ LOG_TARGET_DEBUG(target, "Cache OPs: IHI %d, DHWBI %d", issue_ihi, issue_dhwbi);
+ if (issue_ihi || issue_dhwbi) {
uint32_t ilinesize = issue_ihi ? xtensa->core_config->icache.line_size : UINT32_MAX;
- uint32_t dlinesize = issue_dhwb ? xtensa->core_config->dcache.line_size : UINT32_MAX;
+ uint32_t dlinesize = issue_dhwbi ? xtensa->core_config->dcache.line_size : UINT32_MAX;
uint32_t linesize = MIN(ilinesize, dlinesize);
uint32_t off = 0;
adr = addrstart_al;
@@ -2193,7 +2260,7 @@ int xtensa_write_memory(struct target *target,
}
if (issue_ihi)
xtensa_queue_exec_ins(xtensa, XT_INS_IHI(xtensa, XT_REG_A3, off));
- if (issue_dhwb)
+ if (issue_dhwbi)
xtensa_queue_exec_ins(xtensa, XT_INS_DHWBI(xtensa, XT_REG_A3, off));
off += linesize;
if (off > 1020) {
@@ -2205,7 +2272,11 @@ int xtensa_write_memory(struct target *target,
/* Execute cache WB/INV instructions */
res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
- xtensa_core_status_check(target);
+ if (res != ERROR_OK)
+ LOG_TARGET_ERROR(target,
+ "Error queuing cache writeback/invaldate instruction(s): %d",
+ res);
+ res = xtensa_core_status_check(target);
if (res != ERROR_OK)
LOG_TARGET_ERROR(target,
"Error issuing cache writeback/invaldate instruction(s): %d",
@@ -2367,7 +2438,8 @@ int xtensa_poll(struct target *target)
static int xtensa_update_instruction(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
{
struct xtensa *xtensa = target_to_xtensa(target);
- unsigned int issue_ihi = xtensa_is_icacheable(xtensa, address);
+ unsigned int issue_ihi = xtensa_is_icacheable(xtensa, address) &&
+ xtensa_region_ar_exec(target, address, address + size);
unsigned int issue_dhwbi = xtensa_is_dcacheable(xtensa, address);
uint32_t icache_line_size = issue_ihi ? xtensa->core_config->icache.line_size : UINT32_MAX;
uint32_t dcache_line_size = issue_dhwbi ? xtensa->core_config->dcache.line_size : UINT32_MAX;
@@ -2385,7 +2457,8 @@ static int xtensa_update_instruction(struct target *target, target_addr_t addres
/* Write start address to A3 and invalidate */
xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, address);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
- LOG_TARGET_DEBUG(target, "DHWBI, IHI for address "TARGET_ADDR_FMT, address);
+ LOG_TARGET_DEBUG(target, "IHI %d, DHWBI %d for address " TARGET_ADDR_FMT,
+ issue_ihi, issue_dhwbi, address);
if (issue_dhwbi) {
xtensa_queue_exec_ins(xtensa, XT_INS_DHWBI(xtensa, XT_REG_A3, 0));
if (!same_dc_line) {
-----------------------------------------------------------------------
Summary of changes:
src/target/xtensa/xtensa.c | 89 +++++++++++++++++++++++++++++++++++++++++-----
1 file changed, 81 insertions(+), 8 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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|
From: openocd-gerrit <ope...@us...> - 2024-05-11 11:56:07
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 22ddf62d759b10a89e9c4c3f3929a66c9d72572d (commit)
from 126d8a0972ab6031588eb2f0e1fc3957bd3ccc6b (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 22ddf62d759b10a89e9c4c3f3929a66c9d72572d
Author: Parshintsev Anatoly <ana...@sy...>
Date: Fri May 3 00:28:33 2024 +0300
gdb_server: enable keep-alive packets for qCRC packet
Change-Id: Ia384179bb83ad6b70bf385cc9d575e9ec58f76c7
Signed-off-by: Parshintsev Anatoly <ana...@sy...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8227
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index c1ee4aa2a..dfd7cd520 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -2845,7 +2845,9 @@ static int gdb_query_packet(struct connection *connection,
len = strtoul(separator + 1, NULL, 16);
+ gdb_connection->output_flag = GDB_OUTPUT_NOTIF;
retval = target_checksum_memory(target, addr, len, &checksum);
+ gdb_connection->output_flag = GDB_OUTPUT_NO;
if (retval == ERROR_OK) {
snprintf(gdb_reply, 10, "C%8.8" PRIx32 "", checksum);
-----------------------------------------------------------------------
Summary of changes:
src/server/gdb_server.c | 2 ++
1 file changed, 2 insertions(+)
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Main OpenOCD repository
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