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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-479-g712c1244e

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- Log -----------------------------------------------------------------
commit 712c1244e8486bb4519ad0144a03c3c48c030214
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Aug 6 10:32:46 2023 +0200

    helper/command: simplify script_command_args_alloc()
    
    The output parameter nwords is always equal to the input parameter
    argc, when the function succeeds.
    
    Drop the parameter nwords and let the caller use directly the
    value in argc.
    
    While there, convert some 'unsigned' to 'unsigned int'.
    
    Change-Id: Ie3d8ce1351792f3c07fe39cdcbcd180fd24dc928
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8054
    Tested-by: jenkins

diff --git a/src/helper/command.c b/src/helper/command.c
index 96023336c..f7ec0e21f 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -161,15 +161,13 @@ static void script_command_args_free(char **words, unsigned nwords)
 	free(words);
 }
 
-static char **script_command_args_alloc(
-	unsigned argc, Jim_Obj * const *argv, unsigned *nwords)
+static char **script_command_args_alloc(unsigned int argc, Jim_Obj * const *argv)
 {
 	char **words = malloc(argc * sizeof(char *));
 	if (!words)
 		return NULL;
 
-	unsigned i;
-	for (i = 0; i < argc; i++) {
+	for (unsigned int i = 0; i < argc; i++) {
 		const char *w = Jim_GetString(argv[i], NULL);
 		words[i] = strdup(w);
 		if (!words[i]) {
@@ -177,7 +175,6 @@ static char **script_command_args_alloc(
 			return NULL;
 		}
 	}
-	*nwords = i;
 	return words;
 }
 
@@ -901,8 +898,8 @@ static int exec_command(Jim_Interp *interp, struct command_context *cmd_ctx,
 		return c->jim_handler(interp, argc, argv);
 
 	/* use c->handler */
-	unsigned int nwords;
-	char **words = script_command_args_alloc(argc, argv, &nwords);
+	unsigned int nwords = argc;
+	char **words = script_command_args_alloc(argc, argv);
 	if (!words)
 		return JIM_ERR;
 

-----------------------------------------------------------------------

Summary of changes:
 src/helper/command.c | 11 ++++-------
 1 file changed, 4 insertions(+), 7 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-478-g5e1468da1

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- Log -----------------------------------------------------------------
commit 5e1468da186e65029316a359493e2d2353e21512
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Aug 6 10:40:03 2023 +0200

    helper/command: drop unused variables
    
    In both functions script_debug() and script_command_args_alloc()
    the variable len is never used, and Jim_GetString() does not
    mandate it.
    
    Drop the variable and pass NULL to Jim_GetString().
    
    Change-Id: I754b27a59c6087cde729496be42609d2a7145b0c
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8053
    Tested-by: jenkins

diff --git a/src/helper/command.c b/src/helper/command.c
index ef50ab5bd..96023336c 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -145,8 +145,7 @@ static void script_debug(Jim_Interp *interp, unsigned int argc, Jim_Obj * const
 
 	char *dbg = alloc_printf("command -");
 	for (unsigned i = 0; i < argc; i++) {
-		int len;
-		const char *w = Jim_GetString(argv[i], &len);
+		const char *w = Jim_GetString(argv[i], NULL);
 		char *t = alloc_printf("%s %s", dbg, w);
 		free(dbg);
 		dbg = t;
@@ -171,8 +170,7 @@ static char **script_command_args_alloc(
 
 	unsigned i;
 	for (i = 0; i < argc; i++) {
-		int len;
-		const char *w = Jim_GetString(argv[i], &len);
+		const char *w = Jim_GetString(argv[i], NULL);
 		words[i] = strdup(w);
 		if (!words[i]) {
 			script_command_args_free(words, i);

-----------------------------------------------------------------------

Summary of changes:
 src/helper/command.c | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)


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- Log -----------------------------------------------------------------
commit 6e6d486de2c668e14f9534fab820eea305826753
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Dec 3 18:10:45 2023 +0100

    target: drop deprecated code for mem2array and array2mem
    
    Commit e370e06b724f ("target: Deprecate 'array2mem' and
    'mem2array''") has already replaced the deprecated root versions
    of commands mem2array and array2mem with TCL proc's that use
    'read_memory' and 'write_memory'. It has left the deprecated code
    of the target's version of the commands because the effort to code
    the TCL replacement was not considered valuable.
    
    To drop the last jim_handler commands, I consider much easier and
    less error-prone to code them in TCL instead of converting the
    deprecated code to COMMAND_HANDLER.
    
    Drop the code in target.c and extend the TCL proc's.
    While there, add the TCL procs to _telnet_autocomplete_skip.
    
    Change-Id: I97d2370d8af479434ddf5af68541f90913982bc0
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8052
    Tested-by: jenkins

diff --git a/src/target/startup.tcl b/src/target/startup.tcl
index 35492a6d9..75e0edc77 100644
--- a/src/target/startup.tcl
+++ b/src/target/startup.tcl
@@ -219,31 +219,44 @@ proc init_target_events {} {
 proc init_board {} {
 }
 
-proc mem2array {arrayname bitwidth address count {phys ""}} {
-	echo "DEPRECATED! use 'read_memory' not 'mem2array'"
-
-	upvar $arrayname $arrayname
-	set $arrayname ""
-	set i 0
-
-	foreach elem [read_memory $address $bitwidth $count {*}$phys] {
-		set ${arrayname}($i) $elem
-		incr i
-	}
-}
-
-proc array2mem {arrayname bitwidth address count {phys ""}} {
-	echo "DEPRECATED! use 'write_memory' not 'array2mem'"
-
-	upvar $arrayname $arrayname
-	set data ""
+lappend _telnet_autocomplete_skip _post_init_target_array_mem
+proc _post_init_target_array_mem {} {
+	set targets [target names]
+	lappend targets ""
 
-	for {set i 0} {$i < $count} {incr i} {
-		lappend data [expr $${arrayname}($i)]
+	foreach t $targets {
+		if {$t != ""} {
+			set t "$t "
+		}
+		eval [format	{lappend ::_telnet_autocomplete_skip "%smem2array"} $t]
+		eval [format	{proc {%smem2array} {arrayname bitwidth address count {phys ""}} {
+							echo "DEPRECATED! use 'read_memory' not 'mem2array'"
+
+							upvar $arrayname $arrayname
+							set $arrayname ""
+							set i 0
+
+							foreach elem [%sread_memory $address $bitwidth $count {*}$phys] {
+								set ${arrayname}($i) $elem
+								incr i
+							}
+						}} $t $t]
+		eval [format    {lappend ::_telnet_autocomplete_skip "%sarray2mem"} $t]
+		eval [format    {proc {%sarray2mem} {arrayname bitwidth address count {phys ""}} {
+							echo "DEPRECATED! use 'write_memory' not 'array2mem'"
+
+							upvar $arrayname $arrayname
+							set data ""
+
+							for {set i 0} {$i < $count} {incr i} {
+								lappend data [expr $${arrayname}($i)]
+							}
+
+							%swrite_memory $address $bitwidth $data {*}$phys
+						}} $t $t]
 	}
-
-	write_memory $address $bitwidth $data {*}$phys
 }
+lappend post_init_commands _post_init_target_array_mem
 
 # smp_on/smp_off were already DEPRECATED in v0.11.0 through http://openocd.zylin.com/4615
 lappend _telnet_autocomplete_skip "aarch64 smp_on"
diff --git a/src/target/target.c b/src/target/target.c
index 61890aa3e..920511e96 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -56,10 +56,6 @@ static int target_read_buffer_default(struct target *target, target_addr_t addre
 		uint32_t count, uint8_t *buffer);
 static int target_write_buffer_default(struct target *target, target_addr_t address,
 		uint32_t count, const uint8_t *buffer);
-static int target_array2mem(Jim_Interp *interp, struct target *target,
-		int argc, Jim_Obj * const *argv);
-static int target_mem2array(Jim_Interp *interp, struct target *target,
-		int argc, Jim_Obj * const *argv);
 static int target_register_user_commands(struct command_context *cmd_ctx);
 static int target_get_gdb_fileio_info_default(struct target *target,
 		struct gdb_fileio_info *fileio_info);
@@ -4397,192 +4393,6 @@ COMMAND_HANDLER(handle_profile_command)
 	return retval;
 }
 
-static int new_u64_array_element(Jim_Interp *interp, const char *varname, int idx, uint64_t val)
-{
-	char *namebuf;
-	Jim_Obj *obj_name, *obj_val;
-	int result;
-
-	namebuf = alloc_printf("%s(%d)", varname, idx);
-	if (!namebuf)
-		return JIM_ERR;
-
-	obj_name = Jim_NewStringObj(interp, namebuf, -1);
-	jim_wide wide_val = val;
-	obj_val = Jim_NewWideObj(interp, wide_val);
-	if (!obj_name || !obj_val) {
-		free(namebuf);
-		return JIM_ERR;
-	}
-
-	Jim_IncrRefCount(obj_name);
-	Jim_IncrRefCount(obj_val);
-	result = Jim_SetVariable(interp, obj_name, obj_val);
-	Jim_DecrRefCount(interp, obj_name);
-	Jim_DecrRefCount(interp, obj_val);
-	free(namebuf);
-	/* printf("%s(%d) <= 0%08x\n", varname, idx, val); */
-	return result;
-}
-
-static int target_mem2array(Jim_Interp *interp, struct target *target, int argc, Jim_Obj *const *argv)
-{
-	int e;
-
-	LOG_WARNING("DEPRECATED! use 'read_memory' not 'mem2array'");
-
-	/* argv[0] = name of array to receive the data
-	 * argv[1] = desired element width in bits
-	 * argv[2] = memory address
-	 * argv[3] = count of times to read
-	 * argv[4] = optional "phys"
-	 */
-	if (argc < 4 || argc > 5) {
-		Jim_WrongNumArgs(interp, 0, argv, "varname width addr nelems [phys]");
-		return JIM_ERR;
-	}
-
-	/* Arg 0: Name of the array variable */
-	const char *varname = Jim_GetString(argv[0], NULL);
-
-	/* Arg 1: Bit width of one element */
-	long l;
-	e = Jim_GetLong(interp, argv[1], &l);
-	if (e != JIM_OK)
-		return e;
-	const unsigned int width_bits = l;
-
-	if (width_bits != 8 &&
-			width_bits != 16 &&
-			width_bits != 32 &&
-			width_bits != 64) {
-		Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-		Jim_AppendStrings(interp, Jim_GetResult(interp),
-				"Invalid width param. Must be one of: 8, 16, 32 or 64.", NULL);
-		return JIM_ERR;
-	}
-	const unsigned int width = width_bits / 8;
-
-	/* Arg 2: Memory address */
-	jim_wide wide_addr;
-	e = Jim_GetWide(interp, argv[2], &wide_addr);
-	if (e != JIM_OK)
-		return e;
-	target_addr_t addr = (target_addr_t)wide_addr;
-
-	/* Arg 3: Number of elements to read */
-	e = Jim_GetLong(interp, argv[3], &l);
-	if (e != JIM_OK)
-		return e;
-	size_t len = l;
-
-	/* Arg 4: phys */
-	bool is_phys = false;
-	if (argc > 4) {
-		int str_len = 0;
-		const char *phys = Jim_GetString(argv[4], &str_len);
-		if (!strncmp(phys, "phys", str_len))
-			is_phys = true;
-		else
-			return JIM_ERR;
-	}
-
-	/* Argument checks */
-	if (len == 0) {
-		Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-		Jim_AppendStrings(interp, Jim_GetResult(interp), "mem2array: zero width read?", NULL);
-		return JIM_ERR;
-	}
-	if ((addr + (len * width)) < addr) {
-		Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-		Jim_AppendStrings(interp, Jim_GetResult(interp), "mem2array: addr + len - wraps to zero?", NULL);
-		return JIM_ERR;
-	}
-	if (len > 65536) {
-		Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-		Jim_AppendStrings(interp, Jim_GetResult(interp),
-				"mem2array: too large read request, exceeds 64K items", NULL);
-		return JIM_ERR;
-	}
-
-	if ((width == 1) ||
-		((width == 2) && ((addr & 1) == 0)) ||
-		((width == 4) && ((addr & 3) == 0)) ||
-		((width == 8) && ((addr & 7) == 0))) {
-		/* alignment correct */
-	} else {
-		char buf[100];
-		Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-		sprintf(buf, "mem2array address: " TARGET_ADDR_FMT " is not aligned for %" PRIu32 " byte reads",
-				addr,
-				width);
-		Jim_AppendStrings(interp, Jim_GetResult(interp), buf, NULL);
-		return JIM_ERR;
-	}
-
-	/* Transfer loop */
-
-	/* index counter */
-	size_t idx = 0;
-
-	const size_t buffersize = 4096;
-	uint8_t *buffer = malloc(buffersize);
-	if (!buffer)
-		return JIM_ERR;
-
-	/* assume ok */
-	e = JIM_OK;
-	while (len) {
-		/* Slurp... in buffer size chunks */
-		const unsigned int max_chunk_len = buffersize / width;
-		const size_t chunk_len = MIN(len, max_chunk_len); /* in elements.. */
-
-		int retval;
-		if (is_phys)
-			retval = target_read_phys_memory(target, addr, width, chunk_len, buffer);
-		else
-			retval = target_read_memory(target, addr, width, chunk_len, buffer);
-		if (retval != ERROR_OK) {
-			/* BOO !*/
-			LOG_ERROR("mem2array: Read @ " TARGET_ADDR_FMT ", w=%u, cnt=%zu, failed",
-					  addr,
-					  width,
-					  chunk_len);
-			Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-			Jim_AppendStrings(interp, Jim_GetResult(interp), "mem2array: cannot read memory", NULL);
-			e = JIM_ERR;
-			break;
-		} else {
-			for (size_t i = 0; i < chunk_len ; i++, idx++) {
-				uint64_t v = 0;
-				switch (width) {
-					case 8:
-						v = target_buffer_get_u64(target, &buffer[i*width]);
-						break;
-					case 4:
-						v = target_buffer_get_u32(target, &buffer[i*width]);
-						break;
-					case 2:
-						v = target_buffer_get_u16(target, &buffer[i*width]);
-						break;
-					case 1:
-						v = buffer[i] & 0x0ff;
-						break;
-				}
-				new_u64_array_element(interp, varname, idx, v);
-			}
-			len -= chunk_len;
-			addr += chunk_len * width;
-		}
-	}
-
-	free(buffer);
-
-	Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-
-	return e;
-}
-
 COMMAND_HANDLER(handle_target_read_memory)
 {
 	/*
@@ -4706,201 +4516,6 @@ COMMAND_HANDLER(handle_target_read_memory)
 	return ERROR_OK;
 }
 
-static int get_u64_array_element(Jim_Interp *interp, const char *varname, size_t idx, uint64_t *val)
-{
-	char *namebuf = alloc_printf("%s(%zu)", varname, idx);
-	if (!namebuf)
-		return JIM_ERR;
-
-	Jim_Obj *obj_name = Jim_NewStringObj(interp, namebuf, -1);
-	if (!obj_name) {
-		free(namebuf);
-		return JIM_ERR;
-	}
-
-	Jim_IncrRefCount(obj_name);
-	Jim_Obj *obj_val = Jim_GetVariable(interp, obj_name, JIM_ERRMSG);
-	Jim_DecrRefCount(interp, obj_name);
-	free(namebuf);
-	if (!obj_val)
-		return JIM_ERR;
-
-	jim_wide wide_val;
-	int result = Jim_GetWide(interp, obj_val, &wide_val);
-	*val = wide_val;
-	return result;
-}
-
-static int target_array2mem(Jim_Interp *interp, struct target *target,
-		int argc, Jim_Obj *const *argv)
-{
-	int e;
-
-	LOG_WARNING("DEPRECATED! use 'write_memory' not 'array2mem'");
-
-	/* argv[0] = name of array from which to read the data
-	 * argv[1] = desired element width in bits
-	 * argv[2] = memory address
-	 * argv[3] = number of elements to write
-	 * argv[4] = optional "phys"
-	 */
-	if (argc < 4 || argc > 5) {
-		Jim_WrongNumArgs(interp, 0, argv, "varname width addr nelems [phys]");
-		return JIM_ERR;
-	}
-
-	/* Arg 0: Name of the array variable */
-	const char *varname = Jim_GetString(argv[0], NULL);
-
-	/* Arg 1: Bit width of one element */
-	long l;
-	e = Jim_GetLong(interp, argv[1], &l);
-	if (e != JIM_OK)
-		return e;
-	const unsigned int width_bits = l;
-
-	if (width_bits != 8 &&
-			width_bits != 16 &&
-			width_bits != 32 &&
-			width_bits != 64) {
-		Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-		Jim_AppendStrings(interp, Jim_GetResult(interp),
-				"Invalid width param. Must be one of: 8, 16, 32 or 64.", NULL);
-		return JIM_ERR;
-	}
-	const unsigned int width = width_bits / 8;
-
-	/* Arg 2: Memory address */
-	jim_wide wide_addr;
-	e = Jim_GetWide(interp, argv[2], &wide_addr);
-	if (e != JIM_OK)
-		return e;
-	target_addr_t addr = (target_addr_t)wide_addr;
-
-	/* Arg 3: Number of elements to write */
-	e = Jim_GetLong(interp, argv[3], &l);
-	if (e != JIM_OK)
-		return e;
-	size_t len = l;
-
-	/* Arg 4: Phys */
-	bool is_phys = false;
-	if (argc > 4) {
-		int str_len = 0;
-		const char *phys = Jim_GetString(argv[4], &str_len);
-		if (!strncmp(phys, "phys", str_len))
-			is_phys = true;
-		else
-			return JIM_ERR;
-	}
-
-	/* Argument checks */
-	if (len == 0) {
-		Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-		Jim_AppendStrings(interp, Jim_GetResult(interp),
-				"array2mem: zero width read?", NULL);
-		return JIM_ERR;
-	}
-
-	if ((addr + (len * width)) < addr) {
-		Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-		Jim_AppendStrings(interp, Jim_GetResult(interp),
-				"array2mem: addr + len - wraps to zero?", NULL);
-		return JIM_ERR;
-	}
-
-	if (len > 65536) {
-		Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-		Jim_AppendStrings(interp, Jim_GetResult(interp),
-				"array2mem: too large memory write request, exceeds 64K items", NULL);
-		return JIM_ERR;
-	}
-
-	if ((width == 1) ||
-		((width == 2) && ((addr & 1) == 0)) ||
-		((width == 4) && ((addr & 3) == 0)) ||
-		((width == 8) && ((addr & 7) == 0))) {
-		/* alignment correct */
-	} else {
-		char buf[100];
-		Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-		sprintf(buf, "array2mem address: " TARGET_ADDR_FMT " is not aligned for %" PRIu32 " byte reads",
-				addr,
-				width);
-		Jim_AppendStrings(interp, Jim_GetResult(interp), buf, NULL);
-		return JIM_ERR;
-	}
-
-	/* Transfer loop */
-
-	/* assume ok */
-	e = JIM_OK;
-
-	const size_t buffersize = 4096;
-	uint8_t *buffer = malloc(buffersize);
-	if (!buffer)
-		return JIM_ERR;
-
-	/* index counter */
-	size_t idx = 0;
-
-	while (len) {
-		/* Slurp... in buffer size chunks */
-		const unsigned int max_chunk_len = buffersize / width;
-
-		const size_t chunk_len = MIN(len, max_chunk_len); /* in elements.. */
-
-		/* Fill the buffer */
-		for (size_t i = 0; i < chunk_len; i++, idx++) {
-			uint64_t v = 0;
-			if (get_u64_array_element(interp, varname, idx, &v) != JIM_OK) {
-				free(buffer);
-				return JIM_ERR;
-			}
-			switch (width) {
-			case 8:
-				target_buffer_set_u64(target, &buffer[i * width], v);
-				break;
-			case 4:
-				target_buffer_set_u32(target, &buffer[i * width], v);
-				break;
-			case 2:
-				target_buffer_set_u16(target, &buffer[i * width], v);
-				break;
-			case 1:
-				buffer[i] = v & 0x0ff;
-				break;
-			}
-		}
-		len -= chunk_len;
-
-		/* Write the buffer to memory */
-		int retval;
-		if (is_phys)
-			retval = target_write_phys_memory(target, addr, width, chunk_len, buffer);
-		else
-			retval = target_write_memory(target, addr, width, chunk_len, buffer);
-		if (retval != ERROR_OK) {
-			/* BOO !*/
-			LOG_ERROR("array2mem: Write @ " TARGET_ADDR_FMT ", w=%u, cnt=%zu, failed",
-					  addr,
-					  width,
-					  chunk_len);
-			Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-			Jim_AppendStrings(interp, Jim_GetResult(interp), "array2mem: cannot read memory", NULL);
-			e = JIM_ERR;
-			break;
-		}
-		addr += chunk_len * width;
-	}
-
-	free(buffer);
-
-	Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-
-	return e;
-}
-
 static int target_jim_write_memory(Jim_Interp *interp, int argc,
 		Jim_Obj * const *argv)
 {
@@ -5637,24 +5252,6 @@ static int jim_target_configure(Jim_Interp *interp, int argc, Jim_Obj * const *a
 	return target_configure(&goi, target);
 }
 
-static int jim_target_mem2array(Jim_Interp *interp,
-		int argc, Jim_Obj *const *argv)
-{
-	struct command_context *cmd_ctx = current_command_context(interp);
-	assert(cmd_ctx);
-	struct target *target = get_current_target(cmd_ctx);
-	return target_mem2array(interp, target, argc - 1, argv + 1);
-}
-
-static int jim_target_array2mem(Jim_Interp *interp,
-		int argc, Jim_Obj *const *argv)
-{
-	struct command_context *cmd_ctx = current_command_context(interp);
-	assert(cmd_ctx);
-	struct target *target = get_current_target(cmd_ctx);
-	return target_array2mem(interp, target, argc - 1, argv + 1);
-}
-
 COMMAND_HANDLER(handle_target_examine)
 {
 	bool allow_defer = false;
@@ -5976,22 +5573,6 @@ static const struct command_registration target_instance_command_handlers[] = {
 		.help = "Display target memory as 8-bit bytes",
 		.usage = "address [count]",
 	},
-	{
-		.name = "array2mem",
-		.mode = COMMAND_EXEC,
-		.jim_handler = jim_target_array2mem,
-		.help = "Writes Tcl array of 8/16/32 bit numbers "
-			"to target memory",
-		.usage = "arrayname bitwidth address count",
-	},
-	{
-		.name = "mem2array",
-		.mode = COMMAND_EXEC,
-		.jim_handler = jim_target_mem2array,
-		.help = "Loads Tcl array of 8/16/32 bit numbers "
-			"from target memory",
-		.usage = "arrayname bitwidth address count",
-	},
 	{
 		.name = "get_reg",
 		.mode = COMMAND_EXEC,

-----------------------------------------------------------------------

Summary of changes:
 src/target/startup.tcl |  57 ++++---
 src/target/target.c    | 419 -------------------------------------------------
 2 files changed, 35 insertions(+), 441 deletions(-)


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- Log -----------------------------------------------------------------
commit 305f293201a1d75f24eaa188294b78b284c8185b
Author: Antonio Borneo <bor...@gm...>
Date:   Thu Jan 4 22:26:38 2024 +0100

    LICENSES: drop SPDX tag 'GPL-2.0' and use 'GPL-2.0-only'
    
    The SPDX tag 'GPL-2.0' has been deprecated in
    https://spdx.org/licenses/GPL-2.0.html
    and the preferred tag is now 'GPL-2.0-only'
    https://spdx.org/licenses/GPL-2.0-only.html
    
    Update the LICENSES documents and the SPDX of the only file that
    reports the deprecated tag.
    
    Change-Id: I3c3215438bc4378ff470bb9fa8fa962505a9ae50
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8064
    Tested-by: jenkins

diff --git a/LICENSES/license-rules.txt b/LICENSES/license-rules.txt
index c75192930..ecc8e4db1 100644
--- a/LICENSES/license-rules.txt
+++ b/LICENSES/license-rules.txt
@@ -173,7 +173,6 @@ OpenOCD, can be broken down into:
 
    File format examples::
 
-      Valid-License-Identifier: GPL-2.0
       Valid-License-Identifier: GPL-2.0-only
       Valid-License-Identifier: GPL-2.0-or-later
       SPDX-URL: https://spdx.org/licenses/GPL-2.0.html
@@ -182,8 +181,6 @@ OpenOCD, can be broken down into:
         tag/value pairs into a comment according to the placement
         guidelines in the licensing rules documentation.
         For 'GNU General Public License (GPL) version 2 only' use:
-          SPDX-License-Identifier: GPL-2.0
-        or
           SPDX-License-Identifier: GPL-2.0-only
         For 'GNU General Public License (GPL) version 2 or any later version' use:
           SPDX-License-Identifier: GPL-2.0-or-later
diff --git a/LICENSES/preferred/GPL-2.0 b/LICENSES/preferred/GPL-2.0
index 2ca4651c3..687bdddb1 100644
--- a/LICENSES/preferred/GPL-2.0
+++ b/LICENSES/preferred/GPL-2.0
@@ -1,4 +1,3 @@
-Valid-License-Identifier: GPL-2.0
 Valid-License-Identifier: GPL-2.0-only
 Valid-License-Identifier: GPL-2.0-or-later
 SPDX-URL: https://spdx.org/licenses/GPL-2.0.html
@@ -7,8 +6,6 @@ Usage-Guide:
   tag/value pairs into a comment according to the placement
   guidelines in the licensing rules documentation.
   For 'GNU General Public License (GPL) version 2 only' use:
-    SPDX-License-Identifier: GPL-2.0
-  or
     SPDX-License-Identifier: GPL-2.0-only
   For 'GNU General Public License (GPL) version 2 or any later version' use:
     SPDX-License-Identifier: GPL-2.0-or-later
diff --git a/src/target/mips_cpu.h b/src/target/mips_cpu.h
index 2f31dbd66..c3b7b54ba 100644
--- a/src/target/mips_cpu.h
+++ b/src/target/mips_cpu.h
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier: GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0-only */
 #ifndef OPENOCD_TARGET_MIPS_CPU_H
 #define OPENOCD_TARGET_MIPS_CPU_H
 

-----------------------------------------------------------------------

Summary of changes:
 LICENSES/license-rules.txt | 3 ---
 LICENSES/preferred/GPL-2.0 | 3 ---
 src/target/mips_cpu.h      | 2 +-
 3 files changed, 1 insertion(+), 7 deletions(-)


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- Log -----------------------------------------------------------------
commit 0de852f56130bfffa427bbc04bcea0370eecb0f3
Author: Evgeniy Didin <di...@sy...>
Date:   Fri Jul 31 00:13:12 2020 +0300

    target/arc: skip over breakpoints in arc_resume()
    
    When requested by the core code (handle_breakpoints = true),
    arc_resume() should be able to advance over a potential breakpoint set
    at the resume address instead of getting stuck in one place. This is
    achieved by removing the breakpoint, executing one instruction,
    resetting the breakpoint, then proceeding forward as normal.
    
    With this patch applied, openocd is now able to resume from a
    breakpoint halt when debugging ARCv2 targets via telnet.
    
    This has previously been committed to the Zephyr project's openocd repo
    (see https://github.com/zephyrproject-rtos/openocd/pull/31).
    
    Change-Id: I17dba0dcea311d394b303c587bc2dfaa99d67859
    Signed-off-by: Evgeniy Didin <di...@sy...>
    Signed-off-by: Stephanos Ioannidis <ro...@st...>
    Signed-off-by: Artemiy Volkov <ar...@sy...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7817
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/target/arc.c b/src/target/arc.c
index f3449aada..72e4d918d 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -52,6 +52,11 @@ static int arc_remove_watchpoint(struct target *target,
 	struct watchpoint *watchpoint);
 static int arc_enable_watchpoints(struct target *target);
 static int arc_enable_breakpoints(struct target *target);
+static int arc_unset_breakpoint(struct target *target,
+		struct breakpoint *breakpoint);
+static int arc_set_breakpoint(struct target *target,
+		struct breakpoint *breakpoint);
+static int arc_single_step_core(struct target *target);
 
 void arc_reg_data_type_add(struct target *target,
 		struct arc_reg_data_type *data_type)
@@ -750,6 +755,29 @@ static int arc_examine(struct target *target)
 	return ERROR_OK;
 }
 
+static int arc_exit_debug(struct target *target)
+{
+	uint32_t value;
+	struct arc_common *arc = target_to_arc(target);
+
+	/* Do read-modify-write sequence, or DEBUG.UB will be reset unintentionally. */
+	CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, &value));
+	value |= SET_CORE_FORCE_HALT; /* set the HALT bit */
+	CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, value));
+	alive_sleep(1);
+
+	target->state = TARGET_HALTED;
+	CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
+
+	if (debug_level >= LOG_LVL_DEBUG) {
+		LOG_DEBUG("core stopped (halted) debug-reg: 0x%08" PRIx32, value);
+		CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
+		LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value);
+	}
+
+	return ERROR_OK;
+}
+
 static int arc_halt(struct target *target)
 {
 	uint32_t value, irq_state;
@@ -1251,7 +1279,7 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
 	uint32_t value;
 	struct reg *pc = &arc->core_and_aux_cache->reg_list[arc->pc_index_in_cache];
 
-	LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints(not supported yet):%i,"
+	LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints:%i,"
 		" debug_execution:%i", current, address, handle_breakpoints, debug_execution);
 
 	/* We need to reset ARC cache variables so caches
@@ -1296,6 +1324,19 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
 		CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_PC_REG, value));
 	}
 
+	/* the front-end may request us not to handle breakpoints here */
+	if (handle_breakpoints) {
+		/* Single step past breakpoint at current address */
+		struct breakpoint *breakpoint = breakpoint_find(target, resume_pc);
+		if (breakpoint) {
+			LOG_DEBUG("skipping past breakpoint at 0x%08" TARGET_PRIxADDR,
+				breakpoint->address);
+			CHECK_RETVAL(arc_unset_breakpoint(target, breakpoint));
+			CHECK_RETVAL(arc_single_step_core(target));
+			CHECK_RETVAL(arc_set_breakpoint(target, breakpoint));
+		}
+	}
+
 	/* Restore IRQ state if not in debug_execution*/
 	if (!debug_execution)
 		CHECK_RETVAL(arc_enable_interrupts(target, arc->irq_state));
@@ -2027,6 +2068,22 @@ static int arc_config_step(struct target *target, int enable_step)
 	return ERROR_OK;
 }
 
+static int arc_single_step_core(struct target *target)
+{
+	CHECK_RETVAL(arc_debug_entry(target));
+
+	/* disable interrupts while stepping */
+	CHECK_RETVAL(arc_enable_interrupts(target, 0));
+
+	/* configure single step mode */
+	CHECK_RETVAL(arc_config_step(target, 1));
+
+	/* exit debug mode */
+	CHECK_RETVAL(arc_exit_debug(target));
+
+	return ERROR_OK;
+}
+
 static int arc_step(struct target *target, int current, target_addr_t address,
 	int handle_breakpoints)
 {

-----------------------------------------------------------------------

Summary of changes:
 src/target/arc.c | 59 +++++++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 58 insertions(+), 1 deletion(-)


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- Log -----------------------------------------------------------------
commit 2c10e3e2577604f5ec75b7f688f53fa2b3cbb0e7
Author: Evgeniy Didin <di...@sy...>
Date:   Fri Jul 31 00:13:12 2020 +0300

    target/arc: restore breakpoints in arc_resume()
    
    Presently, we rely on gdb to restore break/watchpoints upon resuming
    execution in arc_resume(). To match this behavior in absence of gdb
    (more specifically, when handle_breakpoints is true), this patch
    explicitly re-enables all breakpoints and watchpoints in arc_resume().
    
    This has previously been committed to the Zephyr project's openocd repo
    (see https://github.com/zephyrproject-rtos/openocd/pull/31).
    
    Change-Id: I59e9c91270ef0b5fd19cfc570663dc67a6022dbd
    Signed-off-by: Evgeniy Didin <di...@sy...>
    Signed-off-by: Stephanos Ioannidis <ro...@st...>
    Signed-off-by: Artemiy Volkov <ar...@sy...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7816
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Oleksij Rempel <li...@re...>

diff --git a/src/target/arc.c b/src/target/arc.c
index 0f7b11025..f3449aada 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -50,6 +50,8 @@
 
 static int arc_remove_watchpoint(struct target *target,
 	struct watchpoint *watchpoint);
+static int arc_enable_watchpoints(struct target *target);
+static int arc_enable_breakpoints(struct target *target);
 
 void arc_reg_data_type_add(struct target *target,
 		struct arc_reg_data_type *data_type)
@@ -1262,6 +1264,13 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
+	if (!debug_execution) {
+		/* (gdb) continue = execute until we hit break/watch-point */
+		target_free_all_working_areas(target);
+		CHECK_RETVAL(arc_enable_breakpoints(target));
+		CHECK_RETVAL(arc_enable_watchpoints(target));
+	}
+
 	/* current = 1: continue on current PC, otherwise continue at <address> */
 	if (!current) {
 		target_buffer_set_u32(target, pc->value, address);
@@ -1658,6 +1667,19 @@ static int arc_unset_breakpoint(struct target *target,
 	return retval;
 }
 
+static int arc_enable_breakpoints(struct target *target)
+{
+	struct breakpoint *breakpoint = target->breakpoints;
+
+	/* set any pending breakpoints */
+	while (breakpoint) {
+		if (!breakpoint->is_set)
+			CHECK_RETVAL(arc_set_breakpoint(target, breakpoint));
+		breakpoint = breakpoint->next;
+	}
+
+	return ERROR_OK;
+}
 
 static int arc_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
@@ -1895,6 +1917,20 @@ static int arc_unset_watchpoint(struct target *target,
 	return retval;
 }
 
+static int arc_enable_watchpoints(struct target *target)
+{
+	struct watchpoint *watchpoint = target->watchpoints;
+
+	/* set any pending watchpoints */
+	while (watchpoint) {
+		if (!watchpoint->is_set)
+			CHECK_RETVAL(arc_set_watchpoint(target, watchpoint));
+		watchpoint = watchpoint->next;
+	}
+
+	return ERROR_OK;
+}
+
 static int arc_add_watchpoint(struct target *target,
 	struct watchpoint *watchpoint)
 {

-----------------------------------------------------------------------

Summary of changes:
 src/target/arc.c | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)


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- Log -----------------------------------------------------------------
commit 04eda372634f995c732bed4f67855be258ab0e41
Author: ianst <ia...@ca...>
Date:   Wed Dec 6 14:34:09 2023 -0800

    target/xtensa: extra debug info for "xtensa exe" failures
    
    - Read and display EXCCAUSE on exe error
    - Clean up error messages
    - Clarify "xtensa exe" documentation
    
    Signed-off-by: ianst <ia...@ca...>
    Change-Id: I90ed39f6afb6543c0c873301501435384b4dccbe
    Reviewed-on: https://review.openocd.org/c/openocd/+/7982
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 53730eafa..e4d4dc5d6 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -11600,13 +11600,14 @@ This feature is not well implemented and tested yet.
 @end deffn
 
 @deffn {Command} {xtensa exe} <ascii-encoded hexadecimal instruction bytes>
-Execute arbitrary instruction(s) provided as an ascii string.  The string represents an integer
-number of instruction bytes, thus its length must be even.
+Execute one arbitrary instruction provided as an ascii string. The string represents an integer
+number of instruction bytes, thus its length must be even. The instruction can be of any width
+that is valid for the Xtensa core configuration.
 @end deffn
 
 @deffn {Command} {xtensa dm} (address) [value]
-Read or write Xtensa Debug Module (DM) registers.  @var{address} is required for both reads
-and writes and is a 4-byte-aligned value typically between 0 and 0x3ffc.  @var{value} is specified
+Read or write Xtensa Debug Module (DM) registers. @var{address} is required for both reads
+and writes and is a 4-byte-aligned value typically between 0 and 0x3ffc. @var{value} is specified
 only for write accesses.
 @end deffn
 
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index d2ca32c1d..ab3bfbb09 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -3483,15 +3483,21 @@ static COMMAND_HELPER(xtensa_cmd_exe_do, struct target *target)
 	LOG_TARGET_DEBUG(target, "execute stub: %s", CMD_ARGV[0]);
 	xtensa_queue_exec_ins_wide(xtensa, ops, oplen);	/* Handles endian-swap */
 	status = xtensa_dm_queue_execute(&xtensa->dbg_mod);
-	if (status != ERROR_OK)
-		LOG_TARGET_ERROR(target, "TIE queue execute: %d\n", status);
-	status = xtensa_core_status_check(target);
-	if (status != ERROR_OK)
-		LOG_TARGET_ERROR(target, "TIE instr execute: %d\n", status);
+	if (status != ERROR_OK) {
+		LOG_TARGET_ERROR(target, "exec: queue error %d", status);
+	} else {
+		status = xtensa_core_status_check(target);
+		if (status != ERROR_OK)
+			LOG_TARGET_ERROR(target, "exec: status error %d", status);
+	}
 
 	/* Reread register cache and restore saved regs after instruction execution */
 	if (xtensa_fetch_all_regs(target) != ERROR_OK)
-		LOG_TARGET_ERROR(target, "%s: Failed to fetch register cache (post-exec).", target_name(target));
+		LOG_TARGET_ERROR(target, "post-exec: register fetch error");
+	if (status != ERROR_OK) {
+		LOG_TARGET_ERROR(target, "post-exec: EXCCAUSE 0x%02" PRIx32,
+			xtensa_reg_get(target, XT_REG_IDX_EXCCAUSE));
+	}
 	xtensa_reg_set(target, XT_REG_IDX_EXCCAUSE, exccause);
 	xtensa_reg_set(target, XT_REG_IDX_CPENABLE, cpenable);
 	return status;

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi           |  9 +++++----
 src/target/xtensa/xtensa.c | 18 ++++++++++++------
 2 files changed, 17 insertions(+), 10 deletions(-)


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- Log -----------------------------------------------------------------
commit 22ebb693b62fd05bcbe2c0101e180b92ca5b11f3
Author: Tarek BOCHKATI <tar...@gm...>
Date:   Thu Apr 28 03:46:35 2022 +0100

    cortex_m: add detection of MVE feature for Armv8.1-M cores
    
    For Armv8.1-M based cores, detect if the core implements the optional
    M-profile vector extension (MVE), using MVFR1 register.
    
    While at there rework armv7m->fp_feature detection based on MVFR0
    and MVFR1 registers.
    
    Change-Id: I92d5b1759aea9f7561d285f46acdec51d6efb7b4
    Signed-off-by: Tarek BOCHKATI <tar...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/6950
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index 8693404d2..2878dd1c7 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -211,6 +211,8 @@ enum {
 	FPV4_SP,
 	FPV5_SP,
 	FPV5_DP,
+	FPV5_MVE_I,
+	FPV5_MVE_F,
 };
 
 #define ARMV7M_NUM_CORE_REGS (ARMV7M_CORE_LAST_REG - ARMV7M_CORE_FIRST_REG + 1)
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index d9e8b538f..6a29a5fd4 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2486,16 +2486,17 @@ static bool cortex_m_has_tz(struct target *target)
 	return (dauthstatus & DAUTHSTATUS_SID_MASK) != 0;
 }
 
-#define MVFR0 0xe000ef40
-#define MVFR1 0xe000ef44
 
-#define MVFR0_DEFAULT_M4 0x10110021
-#define MVFR1_DEFAULT_M4 0x11000011
+#define MVFR0          0xE000EF40
+#define MVFR0_SP_MASK  0x000000F0
+#define MVFR0_SP       0x00000020
+#define MVFR0_DP_MASK  0x00000F00
+#define MVFR0_DP       0x00000200
 
-#define MVFR0_DEFAULT_M7_SP 0x10110021
-#define MVFR0_DEFAULT_M7_DP 0x10110221
-#define MVFR1_DEFAULT_M7_SP 0x11000011
-#define MVFR1_DEFAULT_M7_DP 0x12000011
+#define MVFR1          0xE000EF44
+#define MVFR1_MVE_MASK 0x00000F00
+#define MVFR1_MVE_I    0x00000100
+#define MVFR1_MVE_F    0x00000200
 
 static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
 		struct adiv5_ap **debug_ap)
@@ -2509,7 +2510,7 @@ static int cortex_m_find_mem_ap(struct adiv5_dap *swjdp,
 int cortex_m_examine(struct target *target)
 {
 	int retval;
-	uint32_t cpuid, fpcr, mvfr0, mvfr1;
+	uint32_t cpuid, fpcr;
 	struct cortex_m_common *cortex_m = target_to_cm(target);
 	struct adiv5_dap *swjdp = cortex_m->armv7m.arm.dap;
 	struct armv7m_common *armv7m = target_to_armv7m(target);
@@ -2584,25 +2585,37 @@ int cortex_m_examine(struct target *target)
 		LOG_TARGET_DEBUG(target, "cpuid: 0x%8.8" PRIx32 "", cpuid);
 
 		if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV4) {
+			uint32_t mvfr0;
 			target_read_u32(target, MVFR0, &mvfr0);
-			target_read_u32(target, MVFR1, &mvfr1);
 
-			/* test for floating point feature on Cortex-M4 */
-			if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
-				LOG_TARGET_DEBUG(target, "%s floating point feature FPv4_SP found", cortex_m->core_info->name);
+			if ((mvfr0 & MVFR0_SP_MASK) == MVFR0_SP) {
+				LOG_TARGET_DEBUG(target, "%s floating point feature FPv4_SP found",
+						cortex_m->core_info->name);
 				armv7m->fp_feature = FPV4_SP;
 			}
 		} else if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV5) {
+			uint32_t mvfr0, mvfr1;
 			target_read_u32(target, MVFR0, &mvfr0);
 			target_read_u32(target, MVFR1, &mvfr1);
 
-			/* test for floating point features on Cortex-M7 */
-			if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
-				LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_SP found", cortex_m->core_info->name);
+			if ((mvfr0 & MVFR0_DP_MASK) == MVFR0_DP) {
+				if ((mvfr1 & MVFR1_MVE_MASK) == MVFR1_MVE_F) {
+					LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_DP + MVE-F found",
+							cortex_m->core_info->name);
+					armv7m->fp_feature = FPV5_MVE_F;
+				} else {
+					LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_DP found",
+							cortex_m->core_info->name);
+					armv7m->fp_feature = FPV5_DP;
+				}
+			} else if ((mvfr0 & MVFR0_SP_MASK) == MVFR0_SP) {
+				LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_SP found",
+						cortex_m->core_info->name);
 				armv7m->fp_feature = FPV5_SP;
-			} else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
-				LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_DP found", cortex_m->core_info->name);
-				armv7m->fp_feature = FPV5_DP;
+			} else if ((mvfr1 & MVFR1_MVE_MASK) == MVFR1_MVE_I) {
+				LOG_TARGET_DEBUG(target, "%s floating point feature MVE-I found",
+						cortex_m->core_info->name);
+				armv7m->fp_feature = FPV5_MVE_I;
 			}
 		}
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv7m.h   |  2 ++
 src/target/cortex_m.c | 51 ++++++++++++++++++++++++++++++++-------------------
 2 files changed, 34 insertions(+), 19 deletions(-)


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- Log -----------------------------------------------------------------
commit d2b2ac28d9a240a534a8e8bbe2fb0e791f003807
Author: Daniel Anselmi <dan...@gm...>
Date:   Sun Mar 12 01:43:32 2023 +0100

    ipdbg: improve ipdbg-host speed
    
    By queuing multiple jtag transfers the connection speed between
    JTAG-Host and JTAG-Hub is improved. This is due to much less
    calls to OS functions. An improvement of about x30 has been
    measured with ftdi-based jtag adapters
    
    For this to work the JTAG-Host server needs to know if flow control
    is enabled on the JTAG-Hub ports. This is possible with newer
    JTAG-Hub/JtagCDC. For old JTAG-Hubs the queuing is not enabled so
    this change is backwards compatible.
    
    Change-Id: I8a5108adbe2a2c1e3d3620b5c9ff77a546bfc14e
    Signed-off-by: Daniel Anselmi <dan...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7978
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/server/ipdbg.c b/src/server/ipdbg.c
index c1bdb2939..073323032 100644
--- a/src/server/ipdbg.c
+++ b/src/server/ipdbg.c
@@ -20,6 +20,17 @@
 #define IPDBG_MIN_DR_LENGTH 11
 #define IPDBG_MAX_DR_LENGTH 13
 #define IPDBG_TCP_PORT_STR_MAX_LENGTH 6
+#define IPDBG_SCRATCH_MEMORY_SIZE 1024
+#define IPDBG_EMPTY_DOWN_TRANSFERS 1024
+#define IPDBG_CONSECUTIVE_UP_TRANSFERS 1024
+
+#if IPDBG_SCRATCH_MEMORY_SIZE < IPDBG_EMPTY_DOWN_TRANSFERS
+#error "scratch Memory must be at least IPDBG_EMPTY_DOWN_TRANSFERS"
+#endif
+
+#if IPDBG_SCRATCH_MEMORY_SIZE < IPDBG_CONSECUTIVE_UP_TRANSFERS
+#error "scratch Memory must be at least IPDBG_CONSECUTIVE_UP_TRANSFERS"
+#endif
 
 /* private connection data for IPDBG */
 struct ipdbg_fifo {
@@ -48,6 +59,13 @@ struct ipdbg_virtual_ir_info {
 	uint32_t value;
 };
 
+struct ipdbg_hub_scratch_memory {
+	uint8_t *dr_out_vals;
+	uint8_t *dr_in_vals;
+	uint8_t *vir_out_val;
+	struct scan_field *fields;
+};
+
 struct ipdbg_hub {
 	uint32_t user_instruction;
 	uint32_t max_tools;
@@ -62,7 +80,9 @@ struct ipdbg_hub {
 	struct connection **connections;
 	uint8_t data_register_length;
 	uint8_t dn_xoff;
+	uint8_t flow_control_enabled;
 	struct ipdbg_virtual_ir_info *virtual_ir;
+	struct ipdbg_hub_scratch_memory scratch_memory;
 };
 
 static struct ipdbg_hub *ipdbg_first_hub;
@@ -236,20 +256,28 @@ static int ipdbg_create_hub(struct jtag_tap *tap, uint32_t user_instruction, uin
 {
 	*hub = NULL;
 	struct ipdbg_hub *new_hub = calloc(1, sizeof(struct ipdbg_hub));
-	if (!new_hub) {
-		free(virtual_ir);
-		LOG_ERROR("Out of memory");
-		return ERROR_FAIL;
-	}
+	if (!new_hub)
+		goto mem_err_hub;
 
+	const size_t dreg_buffer_size = DIV_ROUND_UP(data_register_length, 8);
 	new_hub->max_tools = ipdbg_max_tools_from_data_register_length(data_register_length);
+
+	new_hub->scratch_memory.dr_out_vals = calloc(IPDBG_SCRATCH_MEMORY_SIZE, dreg_buffer_size);
+	new_hub->scratch_memory.dr_in_vals = calloc(IPDBG_SCRATCH_MEMORY_SIZE, dreg_buffer_size);
+	new_hub->scratch_memory.fields = calloc(IPDBG_SCRATCH_MEMORY_SIZE, sizeof(struct scan_field));
 	new_hub->connections = calloc(new_hub->max_tools, sizeof(struct connection *));
-	if (!new_hub->connections) {
-		free(virtual_ir);
-		free(new_hub);
-		LOG_ERROR("Out of memory");
-		return ERROR_FAIL;
-	}
+
+	if (virtual_ir)
+		new_hub->scratch_memory.vir_out_val = calloc(1, DIV_ROUND_UP(virtual_ir->length, 8));
+
+	if (!new_hub->scratch_memory.dr_out_vals || !new_hub->scratch_memory.dr_in_vals ||
+		!new_hub->scratch_memory.fields || (virtual_ir && !new_hub->scratch_memory.vir_out_val) ||
+		!new_hub->connections)
+		goto mem_err2;
+
+	if (virtual_ir)
+		buf_set_u32(new_hub->scratch_memory.vir_out_val, 0, virtual_ir->length, virtual_ir->value);
+
 	new_hub->tap                  = tap;
 	new_hub->user_instruction     = user_instruction;
 	new_hub->data_register_length = data_register_length;
@@ -260,8 +288,19 @@ static int ipdbg_create_hub(struct jtag_tap *tap, uint32_t user_instruction, uin
 	new_hub->virtual_ir           = virtual_ir;
 
 	*hub = new_hub;
-
 	return ERROR_OK;
+
+mem_err2:
+	free(new_hub->scratch_memory.vir_out_val);
+	free(new_hub->connections);
+	free(new_hub->scratch_memory.fields);
+	free(new_hub->scratch_memory.dr_in_vals);
+	free(new_hub->scratch_memory.dr_out_vals);
+	free(new_hub);
+mem_err_hub:
+	free(virtual_ir);
+	LOG_ERROR("Out of memory");
+	return ERROR_FAIL;
 }
 
 static void ipdbg_free_hub(struct ipdbg_hub *hub)
@@ -270,6 +309,10 @@ static void ipdbg_free_hub(struct ipdbg_hub *hub)
 		return;
 	free(hub->connections);
 	free(hub->virtual_ir);
+	free(hub->scratch_memory.dr_out_vals);
+	free(hub->scratch_memory.dr_in_vals);
+	free(hub->scratch_memory.fields);
+	free(hub->scratch_memory.vir_out_val);
 	free(hub);
 }
 
@@ -348,20 +391,11 @@ static int ipdbg_shift_vir(struct ipdbg_hub *hub)
 	if (!tap)
 		return ERROR_FAIL;
 
-	uint8_t *dr_out_val = calloc(DIV_ROUND_UP(hub->virtual_ir->length, 8), 1);
-	if (!dr_out_val) {
-		LOG_ERROR("Out of memory");
-		return ERROR_FAIL;
-	}
-	buf_set_u32(dr_out_val, 0, hub->virtual_ir->length, hub->virtual_ir->value);
-
-	struct scan_field fields;
-	ipdbg_init_scan_field(&fields, NULL, hub->virtual_ir->length, dr_out_val);
-	jtag_add_dr_scan(tap, 1, &fields, TAP_IDLE);
+	ipdbg_init_scan_field(hub->scratch_memory.fields, NULL,
+		hub->virtual_ir->length, hub->scratch_memory.vir_out_val);
+	jtag_add_dr_scan(tap, 1, hub->scratch_memory.fields, TAP_IDLE);
 	retval = jtag_execute_queue();
 
-	free(dr_out_val);
-
 	return retval;
 }
 
@@ -374,33 +408,15 @@ static int ipdbg_shift_data(struct ipdbg_hub *hub, uint32_t dn_data, uint32_t *u
 	if (!tap)
 		return ERROR_FAIL;
 
-	uint8_t *dr_out_val = calloc(DIV_ROUND_UP(hub->data_register_length, 8), 1);
-	if (!dr_out_val) {
-		LOG_ERROR("Out of memory");
-		return ERROR_FAIL;
-	}
-	buf_set_u32(dr_out_val, 0, hub->data_register_length, dn_data);
-
-	uint8_t *dr_in_val = NULL;
-	if (up_data) {
-		dr_in_val = calloc(DIV_ROUND_UP(hub->data_register_length, 8), 1);
-		if (!dr_in_val) {
-			LOG_ERROR("Out of memory");
-			free(dr_out_val);
-			return ERROR_FAIL;
-		}
-	}
+	buf_set_u32(hub->scratch_memory.dr_out_vals, 0, hub->data_register_length, dn_data);
 
-	struct scan_field fields;
-	ipdbg_init_scan_field(&fields, dr_in_val, hub->data_register_length, dr_out_val);
-	jtag_add_dr_scan(tap, 1, &fields, TAP_IDLE);
+	ipdbg_init_scan_field(hub->scratch_memory.fields, hub->scratch_memory.dr_in_vals,
+						hub->data_register_length, hub->scratch_memory.dr_out_vals);
+	jtag_add_dr_scan(tap, 1, hub->scratch_memory.fields, TAP_IDLE);
 	int retval = jtag_execute_queue();
 
 	if (up_data && retval == ERROR_OK)
-		*up_data = buf_get_u32(dr_in_val, 0, hub->data_register_length);
-
-	free(dr_out_val);
-	free(dr_in_val);
+		*up_data = buf_get_u32(hub->scratch_memory.dr_in_vals, 0, hub->data_register_length);
 
 	return retval;
 }
@@ -432,6 +448,60 @@ static int ipdbg_distribute_data_from_hub(struct ipdbg_hub *hub, uint32_t up)
 	return ERROR_OK;
 }
 
+static void ipdbg_check_for_xoff(struct ipdbg_hub *hub, size_t tool,
+								uint32_t rx_data)
+{
+	if ((rx_data & hub->xoff_mask) && hub->last_dn_tool != hub->max_tools) {
+		hub->dn_xoff |= BIT(hub->last_dn_tool);
+		LOG_INFO("tool %d sent xoff", hub->last_dn_tool);
+	}
+
+	hub->last_dn_tool = tool;
+}
+
+static int ipdbg_shift_empty_data(struct ipdbg_hub *hub)
+{
+	if (!hub)
+		return ERROR_FAIL;
+
+	struct jtag_tap *tap = hub->tap;
+	if (!tap)
+		return ERROR_FAIL;
+
+	const size_t dreg_buffer_size = DIV_ROUND_UP(hub->data_register_length, 8);
+	memset(hub->scratch_memory.dr_out_vals, 0, dreg_buffer_size);
+	for (size_t i = 0; i < IPDBG_EMPTY_DOWN_TRANSFERS; ++i) {
+		ipdbg_init_scan_field(hub->scratch_memory.fields + i,
+								hub->scratch_memory.dr_in_vals + i * dreg_buffer_size,
+								hub->data_register_length,
+								hub->scratch_memory.dr_out_vals);
+		jtag_add_dr_scan(tap, 1, hub->scratch_memory.fields + i, TAP_IDLE);
+	}
+
+	int retval = jtag_execute_queue();
+
+	if (retval == ERROR_OK) {
+		uint32_t up_data;
+		for (size_t i = 0; i < IPDBG_EMPTY_DOWN_TRANSFERS; ++i) {
+			up_data = buf_get_u32(hub->scratch_memory.dr_in_vals +
+									i * dreg_buffer_size, 0,
+									hub->data_register_length);
+			int rv = ipdbg_distribute_data_from_hub(hub, up_data);
+			if (rv != ERROR_OK)
+				retval = rv;
+
+			if (i == 0) {
+				/* check if xoff sent is only needed on the first transfer which
+				   may contain the xoff of the prev down transfer.
+				*/
+				ipdbg_check_for_xoff(hub, hub->max_tools, up_data);
+			}
+		}
+	}
+
+	return retval;
+}
+
 static int ipdbg_jtag_transfer_byte(struct ipdbg_hub *hub, size_t tool, struct ipdbg_connection *connection)
 {
 	uint32_t dn = hub->valid_mask | ((tool & hub->tool_mask) << 8) |
@@ -445,14 +515,63 @@ static int ipdbg_jtag_transfer_byte(struct ipdbg_hub *hub, size_t tool, struct i
 	if (ret != ERROR_OK)
 		return ret;
 
-	if ((up & hub->xoff_mask) && (hub->last_dn_tool != hub->max_tools)) {
-		hub->dn_xoff |= BIT(hub->last_dn_tool);
-		LOG_INFO("tool %d sent xoff", hub->last_dn_tool);
+	ipdbg_check_for_xoff(hub, tool, up);
+
+	return ERROR_OK;
+}
+
+static int ipdbg_jtag_transfer_bytes(struct ipdbg_hub *hub,
+			size_t tool, struct ipdbg_connection *connection)
+{
+	if (!hub)
+		return ERROR_FAIL;
+
+	struct jtag_tap *tap = hub->tap;
+	if (!tap)
+		return ERROR_FAIL;
+
+	const size_t dreg_buffer_size = DIV_ROUND_UP(hub->data_register_length, 8);
+	size_t num_tx = (connection->dn_fifo.count < IPDBG_CONSECUTIVE_UP_TRANSFERS) ?
+		connection->dn_fifo.count : IPDBG_CONSECUTIVE_UP_TRANSFERS;
+
+	for (size_t i = 0; i < num_tx; ++i) {
+		uint32_t dn_data = hub->valid_mask | ((tool & hub->tool_mask) << 8) |
+			(0x00fful & ipdbg_get_from_fifo(&connection->dn_fifo));
+		buf_set_u32(hub->scratch_memory.dr_out_vals + i * dreg_buffer_size, 0,
+					hub->data_register_length, dn_data);
+
+		ipdbg_init_scan_field(hub->scratch_memory.fields + i,
+								hub->scratch_memory.dr_in_vals +
+									i * dreg_buffer_size,
+								hub->data_register_length,
+								hub->scratch_memory.dr_out_vals +
+									i * dreg_buffer_size);
+		jtag_add_dr_scan(tap, 1, hub->scratch_memory.fields + i, TAP_IDLE);
 	}
 
-	hub->last_dn_tool = tool;
+	int retval = jtag_execute_queue();
 
-	return ERROR_OK;
+	if (retval == ERROR_OK) {
+		uint32_t up_data;
+		for (size_t i = 0; i < num_tx; ++i) {
+			up_data = buf_get_u32(hub->scratch_memory.dr_in_vals +
+									i * dreg_buffer_size,
+									0, hub->data_register_length);
+			int rv = ipdbg_distribute_data_from_hub(hub, up_data);
+			if (rv != ERROR_OK)
+				retval = rv;
+			if (i == 0) {
+				/* check if xoff sent is only needed on the first transfer which
+				   may contain the xoff of the prev down transfer.
+				   No checks for this channel because this function is only
+				   called for channels without enabled flow control.
+				*/
+				ipdbg_check_for_xoff(hub, tool, up_data);
+			}
+		}
+	}
+
+	return retval;
 }
 
 static int ipdbg_polling_callback(void *priv)
@@ -468,33 +587,25 @@ static int ipdbg_polling_callback(void *priv)
 		return ret;
 
 	/* transfer dn buffers to jtag-hub */
-	unsigned int num_transfers = 0;
 	for (size_t tool = 0; tool < hub->max_tools; ++tool) {
 		struct connection *conn = hub->connections[tool];
 		if (conn && conn->priv) {
 			struct ipdbg_connection *connection = conn->priv;
 			while (((hub->dn_xoff & BIT(tool)) == 0) && !ipdbg_fifo_is_empty(&connection->dn_fifo)) {
-				ret = ipdbg_jtag_transfer_byte(hub, tool, connection);
+				if (hub->flow_control_enabled & BIT(tool))
+					ret = ipdbg_jtag_transfer_byte(hub, tool, connection);
+				else
+					ret = ipdbg_jtag_transfer_bytes(hub, tool, connection);
 				if (ret != ERROR_OK)
 					return ret;
-				++num_transfers;
 			}
 		}
 	}
 
 	/* some transfers to get data from jtag-hub in case there is no dn data */
-	while (num_transfers++ < hub->max_tools) {
-		uint32_t dn = 0;
-		uint32_t up = 0;
-
-		int retval = ipdbg_shift_data(hub, dn, &up);
-		if (retval != ERROR_OK)
-			return ret;
-
-		retval = ipdbg_distribute_data_from_hub(hub, up);
-		if (retval != ERROR_OK)
-			return ret;
-	}
+	ret = ipdbg_shift_empty_data(hub);
+	if (ret != ERROR_OK)
+		return ret;
 
 	/* write from up fifos to sockets */
 	for (size_t tool = 0; tool < hub->max_tools; ++tool) {
@@ -510,6 +621,33 @@ static int ipdbg_polling_callback(void *priv)
 	return ERROR_OK;
 }
 
+static int ipdbg_get_flow_control_info_from_hub(struct ipdbg_hub *hub)
+{
+	uint32_t up_data;
+
+	/* on older implementations the flow_control_enable_word is not sent to us.
+		so we don't know -> assume it's enabled on all channels */
+	hub->flow_control_enabled = 0x7f;
+
+	int ret = ipdbg_shift_data(hub, 0UL, &up_data);
+	if (ret != ERROR_OK)
+		return ret;
+
+	const bool valid_up_data = up_data & hub->valid_mask;
+	if (valid_up_data) {
+		const size_t tool = (up_data >> 8) & hub->tool_mask;
+		/* the first valid data from hub is flow_control_enable_word */
+		if (tool == hub->tool_mask)
+			hub->flow_control_enabled = up_data & 0x007f;
+		else
+			ipdbg_distribute_data_from_hub(hub, up_data);
+	}
+
+	LOG_INFO("Flow control enabled on IPDBG JTAG Hub: 0x%02x", hub->flow_control_enabled);
+
+	return ERROR_OK;
+}
+
 static int ipdbg_start_polling(struct ipdbg_service *service, struct connection *connection)
 {
 	struct ipdbg_hub *hub = service->hub;
@@ -536,6 +674,10 @@ static int ipdbg_start_polling(struct ipdbg_service *service, struct connection
 	if (ret != ERROR_OK)
 		return ret;
 
+	ret = ipdbg_get_flow_control_info_from_hub(hub);
+	if (ret != ERROR_OK)
+		return ret;
+
 	LOG_INFO("IPDBG start_polling");
 
 	const int time_ms = 20;

-----------------------------------------------------------------------

Summary of changes:
 src/server/ipdbg.c | 276 ++++++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 209 insertions(+), 67 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

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- Log -----------------------------------------------------------------
commit 44e02e1f49cc09703cb3b4088d0c1c4f9e2d9c87
Author: Tomas Vanek <va...@fb...>
Date:   Sun Dec 10 11:58:43 2023 +0100

    jtag/drivers/cmsis_dap: use oocd_libusb_dev_mem_alloc() helper
    
    On some systems (at least Windows/CYGWIN and macOS) libusb_dev_mem_alloc()
    simply returns NULL. The helper can fall-back to malloc() to allocate
    CMSIS-DAP pending command/response buffers.
    
    Fixes: fd75e9e54270 (jtag/drivers/cmsis_dap_bulk: use asynchronous libusb transfer)
    Signed-off-by: Tomas Vanek <va...@fb...>
    Change-Id: I89660f6747ad9d494b8192711cbbee5764e058fa
    Reviewed-on: https://review.openocd.org/c/openocd/+/8044
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/jtag/drivers/cmsis_dap_usb_bulk.c b/src/jtag/drivers/cmsis_dap_usb_bulk.c
index 17e490f05..92a972a04 100644
--- a/src/jtag/drivers/cmsis_dap_usb_bulk.c
+++ b/src/jtag/drivers/cmsis_dap_usb_bulk.c
@@ -33,12 +33,6 @@
 #include "cmsis_dap.h"
 #include "libusb_helper.h"
 
-#if !defined(LIBUSB_API_VERSION) || (LIBUSB_API_VERSION < 0x01000105) \
-		|| defined(_WIN32) || defined(__CYGWIN__)
-	#define libusb_dev_mem_alloc(dev, sz) malloc(sz)
-	#define libusb_dev_mem_free(dev, buffer, sz) free(buffer)
-#endif
-
 enum {
 	CMSIS_DAP_TRANSFER_PENDING = 0,	/* must be 0, used in libusb_handle_events_completed */
 	CMSIS_DAP_TRANSFER_IDLE,
@@ -599,33 +593,34 @@ static int cmsis_dap_usb_alloc(struct cmsis_dap *dap, unsigned int pkt_sz)
 	dap->command = dap->packet_buffer;
 	dap->response = dap->packet_buffer;
 
+	struct cmsis_dap_backend_data *bdata = dap->bdata;
 	for (unsigned int i = 0; i < MAX_PENDING_REQUESTS; i++) {
-		dap->bdata->command_transfers[i].buffer =
-			libusb_dev_mem_alloc(dap->bdata->dev_handle, pkt_sz);
-		if (!dap->bdata->command_transfers[i].buffer) {
-			LOG_ERROR("unable to allocate CMSIS-DAP packet buffer");
-			return ERROR_FAIL;
-		}
-		dap->bdata->response_transfers[i].buffer =
-			libusb_dev_mem_alloc(dap->bdata->dev_handle, pkt_sz);
-		if (!dap->bdata->response_transfers[i].buffer) {
-			LOG_ERROR("unable to allocate CMSIS-DAP packet buffer");
+		bdata->command_transfers[i].buffer =
+			oocd_libusb_dev_mem_alloc(bdata->dev_handle, pkt_sz);
+
+		bdata->response_transfers[i].buffer =
+			oocd_libusb_dev_mem_alloc(bdata->dev_handle, pkt_sz);
+
+		if (!bdata->command_transfers[i].buffer
+			|| !bdata->response_transfers[i].buffer) {
+			LOG_ERROR("unable to allocate CMSIS-DAP pending packet buffer");
 			return ERROR_FAIL;
 		}
 	}
-
 	return ERROR_OK;
 }
 
 static void cmsis_dap_usb_free(struct cmsis_dap *dap)
 {
+	struct cmsis_dap_backend_data *bdata = dap->bdata;
+
 	for (unsigned int i = 0; i < MAX_PENDING_REQUESTS; i++) {
-		libusb_dev_mem_free(dap->bdata->dev_handle,
-			dap->bdata->command_transfers[i].buffer, dap->packet_size);
-		dap->bdata->command_transfers[i].buffer = NULL;
-		libusb_dev_mem_free(dap->bdata->dev_handle,
-			dap->bdata->response_transfers[i].buffer, dap->packet_size);
-		dap->bdata->response_transfers[i].buffer = NULL;
+		oocd_libusb_dev_mem_free(bdata->dev_handle,
+			bdata->command_transfers[i].buffer, dap->packet_size);
+		oocd_libusb_dev_mem_free(bdata->dev_handle,
+			bdata->response_transfers[i].buffer, dap->packet_size);
+		bdata->command_transfers[i].buffer = NULL;
+		bdata->response_transfers[i].buffer = NULL;
 	}
 
 	free(dap->packet_buffer);

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/cmsis_dap_usb_bulk.c | 41 +++++++++++++++--------------------
 1 file changed, 18 insertions(+), 23 deletions(-)


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commit 15f74c2595fe20235b27ce079a35e066d6b6611c
Author: Tomas Vanek <va...@fb...>
Date:   Wed Dec 20 13:20:27 2023 +0100

    drivers/libusb_helper: introduce oocd_libusb_dev_mem_alloc() helper
    
    On some systems (at least Windows/CYGWIN and macOS) libusb_dev_mem_alloc()
    simply returns NULL.
    
    Use the result of the very first libusb_dev_mem_alloc() call to decide
    if the underlining system supports dev mem allocation or we should
    fall-back to plain heap malloc().
    
    From the decision time on, keep using the selected type of memory allocator
    and deallocator.
    
    Signed-off-by: Tomas Vanek <va...@fb...>
    Change-Id: Ia1f0965cea44b4bb6d936b02ec43f5a16a46f080
    Reviewed-on: https://review.openocd.org/c/openocd/+/8059
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/jtag/drivers/libusb_helper.c b/src/jtag/drivers/libusb_helper.c
index 9d788ee39..57ea8cd3f 100644
--- a/src/jtag/drivers/libusb_helper.c
+++ b/src/jtag/drivers/libusb_helper.c
@@ -377,3 +377,59 @@ int jtag_libusb_handle_events_completed(int *completed)
 {
 	return libusb_handle_events_completed(jtag_libusb_context, completed);
 }
+
+static enum {
+	DEV_MEM_NOT_YET_DECIDED,
+	DEV_MEM_AVAILABLE,
+	DEV_MEM_FALLBACK_MALLOC
+} dev_mem_allocation;
+
+/* Older libusb does not implement following API calls - define stubs instead */
+#if !defined(LIBUSB_API_VERSION) || (LIBUSB_API_VERSION < 0x01000105)
+static uint8_t *libusb_dev_mem_alloc(libusb_device_handle *devh, size_t length)
+{
+	return NULL;
+}
+
+static int libusb_dev_mem_free(libusb_device_handle *devh,
+							   uint8_t *buffer, size_t length)
+{
+	return LIBUSB_ERROR_NOT_SUPPORTED;
+}
+#endif
+
+uint8_t *oocd_libusb_dev_mem_alloc(libusb_device_handle *devh,
+			size_t length)
+{
+	uint8_t *buffer = NULL;
+	if (dev_mem_allocation != DEV_MEM_FALLBACK_MALLOC)
+		buffer = libusb_dev_mem_alloc(devh, length);
+
+	if (dev_mem_allocation == DEV_MEM_NOT_YET_DECIDED)
+		dev_mem_allocation = buffer ? DEV_MEM_AVAILABLE : DEV_MEM_FALLBACK_MALLOC;
+
+	if (dev_mem_allocation == DEV_MEM_FALLBACK_MALLOC)
+		buffer = malloc(length);
+
+	return buffer;
+}
+
+int oocd_libusb_dev_mem_free(libusb_device_handle *devh,
+		uint8_t *buffer, size_t length)
+{
+	if (!buffer)
+		return ERROR_OK;
+
+	switch (dev_mem_allocation) {
+	case DEV_MEM_AVAILABLE:
+		return jtag_libusb_error(libusb_dev_mem_free(devh, buffer, length));
+
+	case DEV_MEM_FALLBACK_MALLOC:
+		free(buffer);
+		return ERROR_OK;
+
+	case DEV_MEM_NOT_YET_DECIDED:
+		return ERROR_FAIL;
+	}
+	return ERROR_FAIL;
+}
diff --git a/src/jtag/drivers/libusb_helper.h b/src/jtag/drivers/libusb_helper.h
index 09309b40c..3cd83c6b3 100644
--- a/src/jtag/drivers/libusb_helper.h
+++ b/src/jtag/drivers/libusb_helper.h
@@ -67,4 +67,27 @@ int jtag_libusb_choose_interface(struct libusb_device_handle *devh,
 int jtag_libusb_get_pid(struct libusb_device *dev, uint16_t *pid);
 int jtag_libusb_handle_events_completed(int *completed);
 
+/**
+ * Attempts to allocate a block of persistent DMA memory suitable for transfers
+ * against the USB device. Fall-back to the ordinary heap malloc()
+ * if the first libusb_dev_mem_alloc() call fails.
+ * @param devh _libusb_ device handle.
+ * @param length size of desired data buffer
+ * @returns a pointer to the newly allocated memory, or NULL on failure
+ */
+uint8_t *oocd_libusb_dev_mem_alloc(libusb_device_handle *devh,
+			size_t length);
+
+/**
+ * Free device memory allocated with oocd_libusb_dev_mem_alloc().
+ * Uses either libusb_dev_mem_free() or free() consistently with
+ * the used method of allocation.
+ * @param devh _libusb_ device handle.
+ * @param buffer pointer to the previously allocated memory
+ * @param length size of desired data buffer
+ * @returns Returns ERROR_OK on success, ERROR_FAIL otherwise.
+ */
+int oocd_libusb_dev_mem_free(libusb_device_handle *devh,
+			uint8_t *buffer, size_t length);
+
 #endif /* OPENOCD_JTAG_DRIVERS_LIBUSB_HELPER_H */

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/libusb_helper.c | 56 ++++++++++++++++++++++++++++++++++++++++
 src/jtag/drivers/libusb_helper.h | 23 +++++++++++++++++
 2 files changed, 79 insertions(+)


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- Log -----------------------------------------------------------------
commit 5c53034d85480d0855394c4683733f61b27b6c5e
Author: Marc Schink <de...@za...>
Date:   Tue Nov 14 10:55:46 2023 +0100

    doc/openocd: Mention APM32F1 and APM32F4 series
    
    Change-Id: I2ff28b0fdf4923a58771a44ad6e83ac871d6fa9e
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8018
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 395d03ca2..cc133f791 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -7709,7 +7709,7 @@ applied to all of them.
 @deffn {Flash Driver} {stm32f1x}
 This driver supports the STM32F0, STM32F1 and STM32F3 microcontroller series from STMicroelectronics.
 The driver is also compatible with the GD32F1, GD32VF103 (RISC-V core), GD32F3 and GD32E23 microcontroller series from GigaDevice.
-The driver also supports the APM32F0 series from Geehy Semiconductor.
+The driver also supports the APM32F0 and APM32F1 series from Geehy Semiconductor.
 The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
 
 @example
@@ -7771,6 +7771,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
 @deffn {Flash Driver} {stm32f2x}
 All members of the STM32F2, STM32F4 and STM32F7 microcontroller families from STMicroelectronics
 include internal flash and use ARM Cortex-M3/M4/M7 cores.
+The driver also works for the APM32F4 series from Geehy Semiconductor.
 The driver automatically recognizes a number of these chips using
 the chip identification register, and autoconfigures itself.
 

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)


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commit b0f99dfed0d0f95d3f9190f1767b4f2f6969f5bc
Author: Marc Schink <de...@za...>
Date:   Wed Nov 8 10:27:36 2023 +0100

    tcl/target: Add Geehy APM32F1x config
    
    Tested with APM32F103CBT6 using JTAG and SWD transport. All flash
    operations, including sector and device protection, work as expected.
    
    Change-Id: Ibefe1a65d710aea87b86ab7ff8a4153512a0ea4f
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8017
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/tcl/target/geehy/apm32f1x.cfg b/tcl/target/geehy/apm32f1x.cfg
new file mode 100644
index 000000000..dc42e060a
--- /dev/null
+++ b/tcl/target/geehy/apm32f1x.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Geehy APM32F1x target
+#
+# https://global.geehy.com/MCU
+#
+
+#
+# APM32F1x devices support JTAG and SWD transport.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME apm32f1x
+}
+
+# Work-area is a space in RAM used for flash programming, by default use 4 KiB.
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to perform a soft reset.
+   cortex_m reset_config sysresetreq
+}

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/geehy/{apm32f4x.cfg => apm32f1x.cfg} | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)
 copy tcl/target/geehy/{apm32f4x.cfg => apm32f1x.cfg} (74%)


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- Log -----------------------------------------------------------------
commit 7f3aba13191debc68742f70580de7cf8465d3611
Author: Marc Schink <de...@za...>
Date:   Sun May 14 15:03:07 2023 +0200

    tcl/target: Add Geehy APM32F4x config
    
    Tested with APM32407RGT6 using JTAG and SWD transport. All flash
    operations, including sector and device protection, work as expected.
    
    Revision identifier (0x0009) is not updated due to missing documentation.
    
    Change-Id: I33f4630fd00096656369ecc923aea2dcad77c7d3
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8016
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/geehy/apm32f4x.cfg b/tcl/target/geehy/apm32f4x.cfg
new file mode 100644
index 000000000..3ed58d15b
--- /dev/null
+++ b/tcl/target/geehy/apm32f4x.cfg
@@ -0,0 +1,57 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Geehy APM32F4x target
+#
+# https://global.geehy.com/MCU
+#
+
+#
+# APM32F4x devices support JTAG and SWD transport.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME apm32f4x
+}
+
+# Work-area is a space in RAM used for flash programming, by default use 4 KiB.
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+     set _CPUTAPID 0x4ba00477
+   } else {
+     set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if { [using_jtag] } {
+   jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to perform a soft reset.
+   cortex_m reset_config sysresetreq
+}

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/geehy/{apm32f0x.cfg => apm32f4x.cfg} | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)
 copy tcl/target/geehy/{apm32f0x.cfg => apm32f4x.cfg} (65%)


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- Log -----------------------------------------------------------------
commit d46a3d635e3d41e2c531a20c97bde217431b5f76
Author: Marc Schink <de...@za...>
Date:   Sat May 13 12:37:12 2023 +0200

    tcl/target: Add Geehy APM32F0x config
    
    Tested with APM32F030C8T using SWD transport. All flash operations,
    including sector and device protection, work as expected.
    
    Revision identifier (0x0011) is not updated due to missing documentation.
    
    Introduce a new directory structure that contains the manufacturer for
    the sake of clarity.
    
    Change-Id: I679387943b09fef640f8f8b6904e542f4e4b29aa
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8015
    Reviewed-by: Tomas Vanek <va...@fb...>
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/target/geehy/apm32f0x.cfg b/tcl/target/geehy/apm32f0x.cfg
new file mode 100644
index 000000000..502c09275
--- /dev/null
+++ b/tcl/target/geehy/apm32f0x.cfg
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Geehy APM32F0x target
+#
+# https://global.geehy.com/MCU
+#
+
+#
+# APM32F0x devices support SWD transport only.
+#
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME apm32f0x
+}
+
+# Work-area is a space in RAM used for flash programming, by default use 1 KiB.
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x400
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to perform a soft reset.
+   cortex_m reset_config sysresetreq
+}

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/geehy/apm32f0x.cfg | 49 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 tcl/target/geehy/apm32f0x.cfg


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- Log -----------------------------------------------------------------
commit a90b1642ec1c5dc12c7d9d2af806efee582f7b19
Author: Marc Schink <de...@za...>
Date:   Sat May 13 12:24:04 2023 +0200

    flash/nor/stm32f1x: Add support for Geehy APM32F0 series
    
    Tested with APM32F030C8T.
    
    Change-Id: I63cd8b66424135dae481a96ba560e6f0b1f9544e
    Suggested-by: Christian U <in...@cu...>
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8014
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 7467e6ad9..395d03ca2 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -7707,12 +7707,10 @@ applied to all of them.
 @end deffn
 
 @deffn {Flash Driver} {stm32f1x}
-All members of the STM32F0, STM32F1 and STM32F3 microcontroller families
-from STMicroelectronics and all members of the GD32F1x0, GD32F3x0 and GD32E23x microcontroller
-families from GigaDevice include internal flash and use ARM Cortex-M0/M3/M4/M23 cores.
-The driver also works with GD32VF103 powered by RISC-V core.
-The driver automatically recognizes a number of these chips using
-the chip identification register, and autoconfigures itself.
+This driver supports the STM32F0, STM32F1 and STM32F3 microcontroller series from STMicroelectronics.
+The driver is also compatible with the GD32F1, GD32VF103 (RISC-V core), GD32F3 and GD32E23 microcontroller series from GigaDevice.
+The driver also supports the APM32F0 series from Geehy Semiconductor.
+The driver automatically recognizes a number of these chips using the chip identification register, and autoconfigures itself.
 
 @example
 flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index b3bb84335..5a3c2da66 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -745,6 +745,7 @@ static int stm32x_get_property_addr(struct target *target, struct stm32x_propert
 
 	switch (cortex_m_get_impl_part(target)) {
 	case CORTEX_M0_PARTNO: /* STM32F0x devices */
+	case CORTEX_M0P_PARTNO: /* APM32F0x devices */
 		addr->device_id = 0x40015800;
 		addr->flash_size = 0x1FFFF7CC;
 		return ERROR_OK;

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi         | 10 ++++------
 src/flash/nor/stm32f1x.c |  1 +
 2 files changed, 5 insertions(+), 6 deletions(-)


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commit 5394e5b762ec01bef6bd5b00faa63b3361599e24
Author: Marc Schink <de...@za...>
Date:   Mon Dec 11 16:28:17 2023 +0100

    target/cortex_m: Add Cortex-M85 part
    
    Change-Id: I91d4c05307d9611ecab11eb52218ab1cb7ed65e3
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8048
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Tarek BOCHKATI <tar...@gm...>

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 3eafee0a1..d9e8b538f 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -105,6 +105,12 @@ static const struct cortex_m_part_info cortex_m_parts[] = {
 		.arch = ARM_ARCH_V8M,
 		.flags = CORTEX_M_F_HAS_FPV5,
 	},
+	{
+		.impl_part = CORTEX_M85_PARTNO,
+		.name = "Cortex-M85",
+		.arch = ARM_ARCH_V8M,
+		.flags = CORTEX_M_F_HAS_FPV5,
+	},
 	{
 		.impl_part = STAR_MC1_PARTNO,
 		.name = "STAR-MC1",
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 0bc139911..a585b786b 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -56,6 +56,7 @@ enum cortex_m_impl_part {
 	CORTEX_M33_PARTNO    = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD21),
 	CORTEX_M35P_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD31),
 	CORTEX_M55_PARTNO    = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD22),
+	CORTEX_M85_PARTNO    = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD23),
 	INFINEON_SLX2_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_INFINEON, 0xDB0),
 	REALTEK_M200_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_REALTEK, 0xd20),
 	REALTEK_M300_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_REALTEK, 0xd22),

-----------------------------------------------------------------------

Summary of changes:
 src/target/cortex_m.c | 6 ++++++
 src/target/cortex_m.h | 1 +
 2 files changed, 7 insertions(+)


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commit 8df529fa663cef2004a6a26e8f147b8c96e03de9
Author: Aleksey Shargalin <myo...@gm...>
Date:   Tue Oct 31 17:23:40 2017 +0300

    bitbang: Add flush before sleep
    
    Some bitbang interfaces have no speed regulation and work as fast as
    they can. Only the sequence of execuded commands is guaranteed but
    not the timing. It works most of time with one exception: when the
    JTAG_SLEEP command is executed, we expect that all previous commands
    already finished so that the sleep interval is guaranteed.
    For now  there may be situations when the sleep time has passed but
    previous commands are not actually executed.
    This patch adds a flush command to the bitbang interface, connects it
    to the existing implementation for remote_bitbang, and runs it when
    the JTAG_SLEEP command is executed.
    
    Change-Id: If40894a63d29a260a4ded134b008df6dd1e89c46
    Signed-off-by: Aleksey Shargalin <myo...@gm...>
    Signed-off-by: David Ryskalczyk <dav...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/4284
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/jtag/drivers/bitbang.c b/src/jtag/drivers/bitbang.c
index 6e97d1584..186d2098a 100644
--- a/src/jtag/drivers/bitbang.c
+++ b/src/jtag/drivers/bitbang.c
@@ -360,6 +360,8 @@ int bitbang_execute_queue(void)
 				break;
 			case JTAG_SLEEP:
 				LOG_DEBUG_IO("sleep %" PRIu32, cmd->cmd.sleep->us);
+				if (bitbang_interface->flush && (bitbang_interface->flush() != ERROR_OK))
+					return ERROR_FAIL;
 				bitbang_sleep(cmd->cmd.sleep->us);
 				break;
 			case JTAG_TMS:
diff --git a/src/jtag/drivers/bitbang.h b/src/jtag/drivers/bitbang.h
index e3714df9c..097a5c0d1 100644
--- a/src/jtag/drivers/bitbang.h
+++ b/src/jtag/drivers/bitbang.h
@@ -57,6 +57,9 @@ struct bitbang_interface {
 
 	/** Sleep for some number of microseconds. **/
 	int (*sleep)(unsigned int microseconds);
+
+	/** Force a flush. */
+	int (*flush)(void);
 };
 
 extern const struct swd_driver bitbang_swd;
diff --git a/src/jtag/drivers/remote_bitbang.c b/src/jtag/drivers/remote_bitbang.c
index c488f8334..6d0fba2e4 100644
--- a/src/jtag/drivers/remote_bitbang.c
+++ b/src/jtag/drivers/remote_bitbang.c
@@ -281,6 +281,7 @@ static struct bitbang_interface remote_bitbang_bitbang = {
 	.swd_write = &remote_bitbang_swd_write,
 	.blink = &remote_bitbang_blink,
 	.sleep = &remote_bitbang_sleep,
+	.flush = &remote_bitbang_flush,
 };
 
 static int remote_bitbang_init_tcp(void)

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/bitbang.c        | 2 ++
 src/jtag/drivers/bitbang.h        | 3 +++
 src/jtag/drivers/remote_bitbang.c | 1 +
 3 files changed, 6 insertions(+)


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commit 65fc586d6ee18813937ec0fdb264b9e0d4bc1c76
Author: Henrik Nordström <hen...@ad...>
Date:   Sun Dec 17 17:39:50 2023 +0100

    tcl/target: add Marvell Octeon TX2 CN9130 target
    
    This has a quite complex JTAG router chain requiring both a custom
    BYPASS instruction to access child taps, and JTAG configuration to
    enable individual DAP nodes.
    
    Change-Id: I6f5345764e1566d70c8526a7e8ec5d250185bd2c
    Signed-off-by: Henrik Nordström <hen...@ad...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8042
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/marvell/cn9130.cfg b/tcl/target/marvell/cn9130.cfg
new file mode 100644
index 000000000..23e472f28
--- /dev/null
+++ b/tcl/target/marvell/cn9130.cfg
@@ -0,0 +1,178 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# cn9130 -- support for the Marvell Octeon TX2 / CN9130 CPU family
+#
+# hen...@ad..., Nov 2023
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME cn9130
+}
+
+if { [info exists MASTERTAPID] } {
+   set _MASTERTAPID $MASTERTAPID
+} else {
+   set _MASTERTAPID 0x07025357
+}
+
+if { [info exists APTAPID] } {
+   set _APTAPID $APTAPID
+} else {
+   set _APTAPID 0x4ba00477
+}
+
+if { [info exists SBTAPID] } {
+   set _SBTAPID $SBTAPID
+} else {
+   set _SBTAPID 0x4ba00477
+}
+
+if { [info exists CORES] } {
+   set _CORES $CORES
+} else {
+   set _CORES 4
+}
+
+# CTI base address should be possible to read from the CoreSight
+# ROM table like how the DBG base address is when not specified.
+if { [info exists CTIBASE] } {
+   set _CTIBASE $CTIBASE
+} else {
+   set _CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
+}
+
+# CN9130 is a multi-die chip and has a multi level hierarchical
+# JTAG TAP, where all the DAPs are disabled at reset, requiring
+# both configuration to enable access to the chip DAPs, and a
+# vendor specific bypass IR instruction to access the slave TAPs
+# via the master TAP. In addition there is a number of sample
+# bits that should be ignored.
+#
+# The default BYPASS instruction in the master TAP bypasses the
+# whole chip and not only the master TAP. And similarly on
+# IDCODE the master TAP only responds with it's own ID and
+# bypasses the other TAPs on the chip, while OpenOCD expects
+# ID from all enabled TAPs in the chain.
+
+# Bootstrap with the default boundary scan oriented TAP configuration
+# where the master,ap,sb TAPs are seen as one big fat TAP, which matches
+# what OpenOCD expects from IDCODE and BYPASS.
+
+jtag newtap $_CHIPNAME bs  -irlen 19 -enable -expected-id $_MASTERTAPID
+
+# Declare the full JTAG chain, but in disabled state during setup
+
+jtag newtap $_CHIPNAME sample4 -irlen 1 -disable
+jtag newtap $_CHIPNAME sample3 -irlen 1 -disable
+jtag newtap $_CHIPNAME sample2 -irlen 1 -disable
+jtag newtap $_CHIPNAME ap.cpu  -irlen 4 -disable -expected-id $_APTAPID
+jtag newtap $_CHIPNAME ap      -irlen 5 -disable
+jtag newtap $_CHIPNAME sample1 -irlen 1 -disable
+jtag newtap $_CHIPNAME sb.cpu  -irlen 4 -disable -expected-id $_SBTAPID
+jtag newtap $_CHIPNAME sb      -irlen 5 -disable
+jtag newtap $_CHIPNAME master  -irlen 5 -disable -ir-bypass 0x11 -expected-id $_MASTERTAPID
+
+# Once the iniial IDCODE scan has completed switch to more detailed
+# scan chain giving access to the individual chip TAPs.
+
+jtag configure $_CHIPNAME.bs -event setup "cn9130_enable_full_chain $_CHIPNAME"
+
+proc cn9130_enable_full_chain { _CHIPNAME } {
+   # Switch to detailed TAP declaration
+   jtag tapdisable $_CHIPNAME.bs
+   jtag tapenable $_CHIPNAME.master
+   jtag tapenable $_CHIPNAME.sb
+   jtag tapenable $_CHIPNAME.sample1
+   jtag tapenable $_CHIPNAME.ap
+   jtag tapenable $_CHIPNAME.sample2
+   jtag tapenable $_CHIPNAME.sample3
+   jtag tapenable $_CHIPNAME.sample4
+}
+
+# AP & SB TAPs have a config register to enable/disable access to
+# the auxilary DAP TAP. Default off which hides the DAP TAP from
+# the scan chain.
+proc cn9130_dap_config { chip tap state } {
+   irscan $chip.$tap 0x12
+   drscan $chip.$tap 32 $state
+}
+
+jtag configure $_CHIPNAME.bs -event tap-disable ""
+jtag configure $_CHIPNAME.bs -event tap-enable ""
+jtag configure $_CHIPNAME.sample4 -event tap-enable ""
+jtag configure $_CHIPNAME.sample3 -event tap-enable ""
+jtag configure $_CHIPNAME.sample2 -event tap-enable ""
+jtag configure $_CHIPNAME.ap.cpu -event tap-disable "cn9130_dap_config $_CHIPNAME ap 0"
+jtag configure cn9130.ap.cpu -event tap-enable "cn9130_dap_config $_CHIPNAME ap 1"
+jtag configure $_CHIPNAME.ap -event tap-enable ""
+jtag configure $_CHIPNAME.sample1 -event tap-enable ""
+jtag configure $_CHIPNAME.sb.cpu -event tap-disable "cn9130_dap_config $_CHIPNAME sb 0"
+jtag configure cn9130.sb.cpu -event tap-enable "cn9130_dap_config $_CHIPNAME sb 1"
+jtag configure $_CHIPNAME.sb -event tap-enable ""
+jtag configure $_CHIPNAME.master -event tap-enable ""
+
+dap create $_CHIPNAME.ap.dap -chain-position $_CHIPNAME.ap.cpu
+
+# Main bus
+target create $_CHIPNAME.ap.axi mem_ap \
+   -dap $_CHIPNAME.ap.dap \
+   -ap-num 0
+
+# Periperials bus
+target create $_CHIPNAME.ap.apb mem_ap \
+   -dap $_CHIPNAME.ap.dap \
+   -ap-num 1
+
+# MSS bus
+target create $_CHIPNAME.ap.ahb mem_ap \
+   -dap $_CHIPNAME.ap.dap \
+   -ap-num 2
+
+# AP A72 CPU cores
+set _smp_command ""
+for { set _core 0 } { $_core < $_CORES } { incr _core 1 } {
+   cti create $_CHIPNAME.ap.cti.$_core \
+      -dap $_CHIPNAME.ap.dap \
+      -baseaddr [ lindex $_CTIBASE $_core ]  \
+      -ap-num 1
+
+   if { $_core == 0 } {
+      target create $_CHIPNAME.ap.a72.$_core aarch64 \
+         -dap $_CHIPNAME.ap.dap \
+         -ap-num 1 \
+         -cti $_CHIPNAME.ap.cti.$_core \
+         -coreid $_core \
+         -rtos hwthread
+      set _smp_command "target smp $_CHIPNAME.ap.a72.$_core"
+   } else {
+      # Defer non-boot cores. Held hard in reset until
+      # SMP is activated.
+      target create $_CHIPNAME.ap.a72.$_core aarch64 \
+         -dap $_CHIPNAME.ap.dap \
+         -ap-num 1 \
+         -cti $_CHIPNAME.ap.cti.$_core \
+         -coreid $_core \
+         -defer-examine
+      set _smp_command "$_smp_command $_CHIPNAME.ap.a72.$_core"
+   }
+
+}
+
+# Set up the A72 cluster as SMP
+# Note: Only the boot core is active by default. The other core DAPs can
+# be enabled by arp_examine after they have been released from hard reset.
+eval $_smp_command
+
+# AP MSS M3 CPU core. Defer as it is held in reset until firmware is loaded.
+target create $_CHIPNAME.ap.mss cortex_m -dap $_CHIPNAME.ap.dap -ap-num 2 -defer-examine
+
+# Why is this needed? reset fails with "Debug regions are unpowered" otherwise
+$_CHIPNAME.ap.axi configure -event examine-start "dap init"
+
+# Automate enabling the AP A72 DAP once the full scan chain is enabled
+proc cn9130_ap_setup { _CHIPNAME } {
+   jtag tapenable $_CHIPNAME.ap.cpu
+   targets $_CHIPNAME.ap.a72.0
+}
+jtag configure $_CHIPNAME.ap -event setup "cn9130_ap_setup $_CHIPNAME"

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/marvell/cn9130.cfg | 178 ++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 178 insertions(+)
 create mode 100644 tcl/target/marvell/cn9130.cfg


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- Log -----------------------------------------------------------------
commit 8d3728f931888d2e9a9bc5a31d26c8327649e676
Author: Henrik Nordström <hen...@ad...>
Date:   Sun Dec 17 23:14:37 2023 +0100

    jtag: add -ir-bypass option to newtap
    
    Some devices with an internal multi-tap JTAG router require a vendor
    specific bypass instruction to bypass the master TAP when addressing
    slave taps internal to the same device. On these devices the standard
    bypass instruction bypasses the whole device.
    
    Change-Id: I4506f0e67c9e4dfe39b7fa18c63d67900313e594
    Signed-off-by: Henrik Nordström <hen...@ad...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8041
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/doc/openocd.texi b/doc/openocd.texi
index ec7c9964a..7467e6ad9 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4424,6 +4424,10 @@ there seems to be no problems with JTAG scan chain operations.
 register during initial examination and when checking the sticky error bit.
 This bit is normally checked after setting the CSYSPWRUPREQ bit, but some
 devices do not set the ack bit until sometime later.
+@item @code{-ir-bypass} @var{NUMBER}
+@*Vendor specific bypass instruction, required by some hierarchical JTAG
+routers where the normal BYPASS instruction bypasses the whole router and
+a vendor specific bypass instruction is required to access child nodes.
 @end itemize
 @end deffn
 
diff --git a/src/jtag/drivers/driver.c b/src/jtag/drivers/driver.c
index 773231500..fae2aad22 100644
--- a/src/jtag/drivers/driver.c
+++ b/src/jtag/drivers/driver.c
@@ -85,7 +85,13 @@ int interface_jtag_add_ir_scan(struct jtag_tap *active,
 			tap->bypass = true;
 
 			field->num_bits = tap->ir_length;
-			field->out_value = buf_set_ones(cmd_queue_alloc(DIV_ROUND_UP(tap->ir_length, 8)), tap->ir_length);
+			if (tap->ir_bypass_value) {
+				uint8_t *v = cmd_queue_alloc(DIV_ROUND_UP(tap->ir_length, 8));
+				buf_set_u64(v, 0, tap->ir_length, tap->ir_bypass_value);
+				field->out_value = v;
+			} else {
+				field->out_value = buf_set_ones(cmd_queue_alloc(DIV_ROUND_UP(tap->ir_length, 8)), tap->ir_length);
+			}
 			field->in_value = NULL; /* do not collect input for tap's in bypass */
 		}
 
diff --git a/src/jtag/hla/hla_transport.c b/src/jtag/hla/hla_transport.c
index 08ee18f36..c0443d835 100644
--- a/src/jtag/hla/hla_transport.c
+++ b/src/jtag/hla/hla_transport.c
@@ -45,6 +45,7 @@ static const struct command_registration hl_swd_transport_subcommand_handlers[]
 			"['-ignore-version'] "
 			"['-ignore-bypass'] "
 			"['-ircapture' number] "
+			"['-ir-bypass' number] "
 			"['-mask' number]",
 	 },
 	COMMAND_REGISTRATION_DONE
@@ -74,6 +75,7 @@ static const struct command_registration hl_transport_jtag_subcommand_handlers[]
 			"['-ignore-version'] "
 			"['-ignore-bypass'] "
 			"['-ircapture' number] "
+			"['-ir-bypass' number] "
 			"['-mask' number]",
 	 },
 	{
diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h
index 1d1c495cf..470ae1833 100644
--- a/src/jtag/jtag.h
+++ b/src/jtag/jtag.h
@@ -133,6 +133,9 @@ struct jtag_tap {
 	/** Bypass register selected */
 	bool bypass;
 
+	/** Bypass instruction value */
+	uint64_t ir_bypass_value;
+
 	struct jtag_tap_event_action *event_action;
 
 	struct jtag_tap *next_tap;
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index 85a66aaf6..407aeb1d8 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -386,6 +386,7 @@ static int jtag_tap_configure_cmd(struct jim_getopt_info *goi, struct jtag_tap *
 #define NTAP_OPT_EXPECTED_ID 5
 #define NTAP_OPT_VERSION   6
 #define NTAP_OPT_BYPASS    7
+#define NTAP_OPT_IRBYPASS    8
 
 static const struct nvp jtag_newtap_opts[] = {
 	{ .name = "-irlen",          .value = NTAP_OPT_IRLEN },
@@ -396,6 +397,7 @@ static const struct nvp jtag_newtap_opts[] = {
 	{ .name = "-expected-id",    .value = NTAP_OPT_EXPECTED_ID },
 	{ .name = "-ignore-version", .value = NTAP_OPT_VERSION },
 	{ .name = "-ignore-bypass",  .value = NTAP_OPT_BYPASS },
+	{ .name = "-ir-bypass",      .value = NTAP_OPT_IRBYPASS },
 	{ .name = NULL,              .value = -1 },
 };
 
@@ -499,6 +501,15 @@ static COMMAND_HELPER(handle_jtag_newtap_args, struct jtag_tap *tap)
 			tap->ignore_bypass = true;
 			break;
 
+		case NTAP_OPT_IRBYPASS:
+			if (!CMD_ARGC)
+				return ERROR_COMMAND_ARGUMENT_INVALID;
+
+			COMMAND_PARSE_NUMBER(u64, CMD_ARGV[0], tap->ir_bypass_value);
+			CMD_ARGC--;
+			CMD_ARGV++;
+			break;
+
 		default:
 			nvp_unknown_command_print(CMD, jtag_newtap_opts, NULL, CMD_ARGV[-1]);
 			return ERROR_COMMAND_ARGUMENT_INVALID;
@@ -752,6 +763,7 @@ static const struct command_registration jtag_subcommand_handlers[] = {
 			"['-ignore-version'] "
 			"['-ignore-bypass'] "
 			"['-ircapture' number] "
+			"['-ir-bypass' number] "
 			"['-mask' number]",
 	},
 	{
diff --git a/src/target/adi_v5_dapdirect.c b/src/target/adi_v5_dapdirect.c
index 575092cbf..f3a90c0b1 100644
--- a/src/target/adi_v5_dapdirect.c
+++ b/src/target/adi_v5_dapdirect.c
@@ -66,6 +66,7 @@ static const struct command_registration dapdirect_jtag_subcommand_handlers[] =
 			"['-ignore-version'] "
 			"['-ignore-bypass'] "
 			"['-ircapture' number] "
+			"['-ir-bypass' number] "
 			"['-mask' number]",
 	},
 	{
@@ -156,6 +157,7 @@ static const struct command_registration dapdirect_swd_subcommand_handlers[] = {
 			"['-ignore-version'] "
 			"['-ignore-bypass'] "
 			"['-ircapture' number] "
+			"['-ir-bypass' number] "
 			"['-mask' number]",
 	},
 	COMMAND_REGISTRATION_DONE
diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c
index edcad741e..6d6f287b0 100644
--- a/src/target/adi_v5_swd.c
+++ b/src/target/adi_v5_swd.c
@@ -705,6 +705,7 @@ static const struct command_registration swd_commands[] = {
 			"['-ignore-version'] "
 			"['-ignore-bypass'] "
 			"['-ircapture' number] "
+			"['-ir-bypass' number] "
 			"['-mask' number]",
 	},
 	COMMAND_REGISTRATION_DONE

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi              |  4 ++++
 src/jtag/drivers/driver.c     |  8 +++++++-
 src/jtag/hla/hla_transport.c  |  2 ++
 src/jtag/jtag.h               |  3 +++
 src/jtag/tcl.c                | 12 ++++++++++++
 src/target/adi_v5_dapdirect.c |  2 ++
 src/target/adi_v5_swd.c       |  1 +
 7 files changed, 31 insertions(+), 1 deletion(-)


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commit fc268f83261e08cfb1751f8e8f9a20900bf0e360
Author: Peter Collingbourne <pc...@go...>
Date:   Fri Dec 8 13:57:44 2023 -0800

    target/armv8: Add more support for decoding memory attributes
    
    Change-Id: I7ac7b06d67ec806a9ebffc26a7c6b9c24f024478
    Signed-off-by: Peter Collingbourne <pc...@go...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8043
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/target/armv8.c b/src/target/armv8.c
index d197477ac..daf1ffca3 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -943,6 +943,81 @@ int armv8_mmu_translate_va(struct target *target,  target_addr_t va, target_addr
 	return ERROR_OK;
 }
 
+static void armv8_decode_cacheability(int attr)
+{
+	if (attr == 0) {
+		LOG_USER_N("UNPREDICTABLE");
+		return;
+	}
+	if (attr == 4) {
+		LOG_USER_N("Non-cacheable");
+		return;
+	}
+	switch (attr & 0xC) {
+		case 0:
+			LOG_USER_N("Write-Through Transient");
+			break;
+		case 0x4:
+			LOG_USER_N("Write-Back Transient");
+			break;
+		case 0x8:
+			LOG_USER_N("Write-Through Non-transient");
+			break;
+		case 0xC:
+			LOG_USER_N("Write-Back Non-transient");
+			break;
+	}
+	if (attr & 2)
+		LOG_USER_N(" Read-Allocate");
+	else
+		LOG_USER_N(" No-Read Allocate");
+	if (attr & 1)
+		LOG_USER_N(" Write-Allocate");
+	else
+		LOG_USER_N(" No-Write Allocate");
+}
+
+static void armv8_decode_memory_attr(int attr)
+{
+	if (attr == 0x40) {
+		LOG_USER("Normal Memory, Inner Non-cacheable, "
+			 "Outer Non-cacheable, XS=0");
+	} else if (attr == 0xA0) {
+		LOG_USER("Normal Memory, Inner Write-through Cacheable, "
+			 "Outer Write-through Cacheable, Read-Allocate, "
+			 "No-Write Allocate, Non-transient, XS=0");
+	} else if (attr == 0xF0) {
+		LOG_USER("Tagged Normal Memory, Inner Write-Back, "
+			 "Outer Write-Back, Read-Allocate, Write-Allocate, "
+			 "Non-transient");
+	} else if ((attr & 0xF0) == 0) {
+		switch (attr & 0xC) {
+			case 0:
+				LOG_USER_N("Device-nGnRnE Memory");
+				break;
+			case 0x4:
+				LOG_USER_N("Device-nGnRE Memory");
+				break;
+			case 0x8:
+				LOG_USER_N("Device-nGRE Memory");
+				break;
+			case 0xC:
+				LOG_USER_N("Device-GRE Memory");
+				break;
+		}
+		if (attr & 1)
+			LOG_USER(", XS=0");
+		else
+			LOG_USER_N("\n");
+	} else {
+		LOG_USER_N("Normal Memory, Inner ");
+		armv8_decode_cacheability(attr & 0xF);
+		LOG_USER_N(", Outer ");
+		armv8_decode_cacheability(attr >> 4);
+		LOG_USER_N("\n");
+	}
+}
+
 /*  V8 method VA TO PA  */
 int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
 	target_addr_t *val, int meminfo)
@@ -1025,11 +1100,9 @@ int armv8_mmu_translate_va_pa(struct target *target, target_addr_t va,
 			int NS = (par >> 9) & 1;
 			int ATTR = (par >> 56) & 0xFF;
 
-			char *memtype = (ATTR & 0xF0) == 0 ? "Device Memory" : "Normal Memory";
-
 			LOG_USER("%sshareable, %s",
 					shared_name[SH], secure_name[NS]);
-			LOG_USER("%s", memtype);
+			armv8_decode_memory_attr(ATTR);
 		}
 	}
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv8.c | 79 +++++++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 76 insertions(+), 3 deletions(-)


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commit 357996d99626170c11cb896be91c4cdc2afbca8d
Author: Tomas Vanek <va...@fb...>
Date:   Wed Mar 15 14:12:47 2023 +0100

    target/adi_v5_swd: optimize sequences in swd_connect_multidrop()
    
    swd_connect_multidrop() sent DORMANT_TO_SWD and called
    swd_multidrop_select_inner(). DORMANT_TO_SWD sequence ends
    with a LINE_RESET sequence.
    swd_multidrop_select_inner() sent LINE_RESET sequence again.
    It was useless in this case.
    
    swd_connect_multidrop() emited JTAG_TO_DORMANT and DORMANT_TO_SWD
    sequences before connecting each DAP in SWD multidrop bus.
    It is sufficient to emit JTAG_TO_DORMANT and DORMANT_TO_SWD
    just once and emit the shorter LINE_RESET instead for subsequent DAPs.
    
    Introduce a global variable swd_multidrop_in_swd_state
    and use it to control what sequence is emitted.
    
    In case of reconnect after an error, always use the full switch
    JTAG_TO_DORMANT and DORMANT_TO_SWD.
    
    Change-Id: Iba21620f6a9680793208bf398960ed0eb59df3b1
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7218
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c
index 968798b32..edcad741e 100644
--- a/src/target/adi_v5_swd.c
+++ b/src/target/adi_v5_swd.c
@@ -48,6 +48,8 @@ static bool do_sync;
 
 static struct adiv5_dap *swd_multidrop_selected_dap;
 
+static bool swd_multidrop_in_swd_state;
+
 
 static int swd_queue_dp_write_inner(struct adiv5_dap *dap, unsigned int reg,
 		uint32_t data);
@@ -187,7 +189,15 @@ static int swd_multidrop_select_inner(struct adiv5_dap *dap, uint32_t *dpidr_ptr
 
 	assert(dap_is_multidrop(dap));
 
-	swd_send_sequence(dap, LINE_RESET);
+	/* Send JTAG_TO_DORMANT and DORMANT_TO_SWD just once
+	 * and then use shorter LINE_RESET until communication fails */
+	if (!swd_multidrop_in_swd_state) {
+		swd_send_sequence(dap, JTAG_TO_DORMANT);
+		swd_send_sequence(dap, DORMANT_TO_SWD);
+	} else {
+		swd_send_sequence(dap, LINE_RESET);
+	}
+
 	/*
 	 * Zero dap->select and set dap->select_dpbanksel_valid
 	 * to skip the write to DP_SELECT before DPIDR read, avoiding
@@ -245,6 +255,7 @@ static int swd_multidrop_select_inner(struct adiv5_dap *dap, uint32_t *dpidr_ptr
 
 	LOG_DEBUG_IO("Selected DP_TARGETSEL 0x%08" PRIx32, dap->multidrop_targetsel);
 	swd_multidrop_selected_dap = dap;
+	swd_multidrop_in_swd_state = true;
 
 	if (dpidr_ptr)
 		*dpidr_ptr = dpidr;
@@ -294,8 +305,9 @@ static int swd_connect_multidrop(struct adiv5_dap *dap)
 	int64_t timeout = timeval_ms() + 500;
 
 	do {
-		swd_send_sequence(dap, JTAG_TO_DORMANT);
-		swd_send_sequence(dap, DORMANT_TO_SWD);
+		/* Do not make any assumptions about SWD state in case of reconnect */
+		if (dap->do_reconnect)
+			swd_multidrop_in_swd_state = false;
 
 		/* Clear link state, including the SELECT cache. */
 		dap->do_reconnect = false;
@@ -306,6 +318,7 @@ static int swd_connect_multidrop(struct adiv5_dap *dap)
 		if (retval == ERROR_OK)
 			break;
 
+		swd_multidrop_in_swd_state = false;
 		alive_sleep(1);
 
 	} while (timeval_ms() < timeout);
@@ -316,6 +329,7 @@ static int swd_connect_multidrop(struct adiv5_dap *dap)
 		return retval;
 	}
 
+	swd_multidrop_in_swd_state = true;
 	LOG_INFO("SWD DPIDR 0x%08" PRIx32 ", DLPIDR 0x%08" PRIx32,
 			  dpidr, dlpidr);
 
@@ -392,6 +406,13 @@ static int swd_connect_single(struct adiv5_dap *dap)
 	return retval;
 }
 
+static int swd_pre_connect(struct adiv5_dap *dap)
+{
+	swd_multidrop_in_swd_state = false;
+
+	return ERROR_OK;
+}
+
 static int swd_connect(struct adiv5_dap *dap)
 {
 	int status;
@@ -627,7 +648,12 @@ static void swd_quit(struct adiv5_dap *dap)
 
 	done = true;
 	if (dap_is_multidrop(dap)) {
+		/* Emit the switch seq to dormant state regardless the state mirrored
+		 * in swd_multidrop_in_swd_state. Doing so ensures robust operation
+		 * in the case the variable is out of sync.
+		 * Sending SWD_TO_DORMANT makes no change if the DP is already dormant. */
 		swd->switch_seq(SWD_TO_DORMANT);
+		swd_multidrop_in_swd_state = false;
 		/* Revisit!
 		 * Leaving DPs in dormant state was tested and offers some safety
 		 * against DPs mismatch in case of unintentional use of non-multidrop SWD.
@@ -648,6 +674,7 @@ static void swd_quit(struct adiv5_dap *dap)
 }
 
 const struct dap_ops swd_dap_ops = {
+	.pre_connect_init = swd_pre_connect,
 	.connect = swd_connect,
 	.send_sequence = swd_send_sequence,
 	.queue_dp_read = swd_queue_dp_read,

-----------------------------------------------------------------------

Summary of changes:
 src/target/adi_v5_swd.c | 33 ++++++++++++++++++++++++++++++---
 1 file changed, 30 insertions(+), 3 deletions(-)


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commit bfc12522395af86ba634aa8e085a8051ca6fd43c
Author: Tomas Vanek <va...@fb...>
Date:   Wed Mar 15 13:58:52 2023 +0100

    target/arm_adi_v5,arm_dap: introduce pre_connect_init() dap operation
    
    SWD multidrop requires some initialization once before connecting
    all daps. Provide an optional pre-connect dap operation.
    
    Change-Id: I778215c512c56423a425dda80ab19a739f22f285
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7542
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index e07b577af..fc7fdafd8 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -420,6 +420,9 @@ struct adiv5_dap {
  * available until run().
  */
 struct dap_ops {
+	/** Optional; called once on the first enabled dap before connecting */
+	int (*pre_connect_init)(struct adiv5_dap *dap);
+
 	/** connect operation for SWD */
 	int (*connect)(struct adiv5_dap *dap);
 
diff --git a/src/target/arm_dap.c b/src/target/arm_dap.c
index 84cc6c743..9f4afae74 100644
--- a/src/target/arm_dap.c
+++ b/src/target/arm_dap.c
@@ -91,6 +91,7 @@ static int dap_init_all(void)
 {
 	struct arm_dap_object *obj;
 	int retval;
+	bool pre_connect = true;
 
 	LOG_DEBUG("Initializing all DAPs ...");
 
@@ -123,6 +124,14 @@ static int dap_init_all(void)
 				is_adiv6(dap) ? "ADIv6" : "ADIv5");
 		}
 
+		if (pre_connect && dap->ops->pre_connect_init) {
+			retval = dap->ops->pre_connect_init(dap);
+			if (retval != ERROR_OK)
+				return retval;
+
+			pre_connect = false;
+		}
+
 		retval = dap->ops->connect(dap);
 		if (retval != ERROR_OK)
 			return retval;

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_adi_v5.h | 3 +++
 src/target/arm_dap.c    | 9 +++++++++
 2 files changed, 12 insertions(+)


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commit ee3fb5a0eacb42e8e881239194485d79d128d246
Author: Tomas Vanek <va...@fb...>
Date:   Tue Mar 14 18:40:25 2023 +0100

    target/arm_adi_v5: fix DP SELECT logic
    
    The original code supported ADIv5 only, just one SELECT register
    with some reserved bits - the pseudo value DP_SELECT_INVALID was
    just fine to indicate the DP SELECT register is in an unknown state.
    
    Added ADIv6 support required DP SELECT and SELECT1 registers
    without reserved bits. Therefore DP_SELECT_INVALID value became
    reachable as a (fortunately not really used) ADIv6 AP ADDR.
    
    JTAG DPBANKSEL setting support introduced with ADIv6 does not
    honor DP_SELECT_INVALID correctly: required select value
    gets compared to DP_SELECT_INVALID value and the most common zero
    bank does not trigger DP SELECT write.
    
    DP banked registers need just to set DP SELECT. ADIv6 AP register
    addressing scheme may use both DP SELECT and SELECT1. This further
    complicates using a single invalid value.
    
    Moreover the difference how the SWD line reset influences
    DPBANKSEL field between ADIv5 and ADIv6 deserves better handling
    than setting select cache to zero and then to DP_SELECT_INVALID
    in a very specific code positions.
    
    Introduce bool flags indicating the validity of each SELECT
    register and one SWD specific for DPBANKSEL field.
    Use the latter to prevent selecting DP BANK before taking
    the connection out of reset by reading DPIDR.
    
    Treat DP SELECT and SELECT1 individually in ADIv6 64-bit mode.
    
    Update comments to reflect the difference between ADIv5 and ADIv6
    in SWD line reset.
    
    Change-Id: Ibbb0b06cb592be072571218b666566a13d8dff0e
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7541
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index afdc0e577..8d54a50fb 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -353,17 +353,25 @@ static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
 	uint64_t sel = (reg_addr >> 4) & DP_SELECT_DPBANK;
 
 	/* No need to change SELECT or RDBUFF as they are not banked */
-	if (instr == JTAG_DP_DPACC && reg_addr != DP_SELECT && reg_addr != DP_RDBUFF &&
-			sel != (dap->select & 0xf)) {
-		if (dap->select != DP_SELECT_INVALID)
-			sel |= dap->select & ~0xfull;
-		dap->select = sel;
-		LOG_DEBUG("DP BANKSEL: %x", (uint32_t)sel);
+	if (instr == JTAG_DP_DPACC && reg_addr != DP_SELECT && reg_addr != DP_RDBUFF
+			&& (!dap->select_valid || sel != (dap->select & DP_SELECT_DPBANK))) {
+		/* Use the AP part of dap->select regardless of dap->select_valid:
+		 * if !dap->select_valid
+		 * dap->select contains a speculative value likely going to be used
+		 * in the following swd_queue_ap_bankselect() */
+		sel |= dap->select & SELECT_AP_MASK;
+
+		LOG_DEBUG_IO("DP BANK SELECT: %" PRIx32, (uint32_t)sel);
+
 		buf_set_u32(out_value_buf, 0, 32, (uint32_t)sel);
+
 		retval = adi_jtag_dp_scan(dap, JTAG_DP_DPACC,
 				DP_SELECT, DPAP_WRITE, out_value_buf, NULL, 0, NULL);
 		if (retval != ERROR_OK)
 			return retval;
+
+		dap->select = sel;
+		dap->select_valid = true;
 	}
 	buf_set_u32(out_value_buf, 0, 32, outvalue);
 
@@ -520,7 +528,10 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap)
 					/* timeout happened */
 					if (tmp->ack == JTAG_ACK_WAIT) {
 						LOG_ERROR("Timeout during WAIT recovery");
-						dap->select = DP_SELECT_INVALID;
+						dap->select_valid = false;
+						dap->select1_valid = false;
+						/* Keep dap->select unchanged, the same AP and AP bank
+						 * is likely going to be used further */
 						jtag_ap_q_abort(dap, NULL);
 						/* clear the sticky overrun condition */
 						adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
@@ -580,7 +591,7 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap)
 
 			/* TODO: ADIv6 DP SELECT1 handling */
 
-			dap->select = DP_SELECT_INVALID;
+			dap->select_valid = false;
 		}
 
 		list_for_each_entry_safe(el, tmp, &replay_list, lh) {
@@ -615,7 +626,10 @@ static int jtagdp_overrun_check(struct adiv5_dap *dap)
 			if (retval == ERROR_OK) {
 				if (el->ack == JTAG_ACK_WAIT) {
 					LOG_ERROR("Timeout during WAIT recovery");
-					dap->select = DP_SELECT_INVALID;
+					dap->select_valid = false;
+					dap->select1_valid = false;
+					/* Keep dap->select unchanged, the same AP and AP bank
+					 * is likely going to be used further */
 					jtag_ap_q_abort(dap, NULL);
 					/* clear the sticky overrun condition */
 					adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
@@ -748,41 +762,60 @@ static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
 	return retval;
 }
 
-/** Select the AP register bank matching bits 7:4 of reg. */
+/** Select the AP register bank */
 static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned reg)
 {
 	int retval;
 	struct adiv5_dap *dap = ap->dap;
 	uint64_t sel;
 
-	if (is_adiv6(dap)) {
+	if (is_adiv6(dap))
 		sel = ap->ap_num | (reg & 0x00000FF0);
-		if (sel == (dap->select & ~0xfull))
-			return ERROR_OK;
+	else
+		sel = (ap->ap_num << 24) | (reg & ADIV5_DP_SELECT_APBANK);
 
-		if (dap->select != DP_SELECT_INVALID)
-			sel |= dap->select & 0xf;
-		dap->select = sel;
-		LOG_DEBUG("AP BANKSEL: %" PRIx64, sel);
+	uint64_t sel_diff = (sel ^ dap->select) & SELECT_AP_MASK;
+
+	bool set_select = !dap->select_valid || (sel_diff & 0xffffffffull);
+	bool set_select1 = is_adiv6(dap) && dap->asize > 32
+						&& (!dap->select1_valid
+							|| sel_diff & (0xffffffffull << 32));
+
+	if (set_select && set_select1) {
+		/* Prepare DP bank for DP_SELECT1 now to save one write */
+		sel |= (DP_SELECT1 >> 4) & DP_SELECT_DPBANK;
+	} else {
+		/* Use the DP part of dap->select regardless of dap->select_valid:
+		 * if !dap->select_valid
+		 * dap->select contains a speculative value likely going to be used
+		 * in the following swd_queue_dp_bankselect().
+		 * Moreover dap->select_valid should never be false here as a DP bank
+		 * is always selected before selecting an AP bank */
+		sel |= dap->select & DP_SELECT_DPBANK;
+	}
+
+	if (set_select) {
+		LOG_DEBUG_IO("AP BANK SELECT: %" PRIx32, (uint32_t)sel);
 
 		retval = jtag_dp_q_write(dap, DP_SELECT, (uint32_t)sel);
-		if (retval != ERROR_OK)
+		if (retval != ERROR_OK) {
+			dap->select_valid = false;
 			return retval;
-
-		if (dap->asize > 32)
-			return jtag_dp_q_write(dap, DP_SELECT1, (uint32_t)(sel >> 32));
-		return ERROR_OK;
+		}
 	}
 
-	/* ADIv5 */
-	sel = (ap->ap_num << 24) | (reg & ADIV5_DP_SELECT_APBANK);
+	if (set_select1) {
+		LOG_DEBUG_IO("AP BANK SELECT1: %" PRIx32, (uint32_t)(sel >> 32));
 
-	if (sel == dap->select)
-		return ERROR_OK;
+		retval = jtag_dp_q_write(dap, DP_SELECT1, (uint32_t)(sel >> 32));
+		if (retval != ERROR_OK) {
+			dap->select1_valid = false;
+			return retval;
+		}
+	}
 
 	dap->select = sel;
-
-	return jtag_dp_q_write(dap, DP_SELECT, (uint32_t)sel);
+	return ERROR_OK;
 }
 
 static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned reg,
diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c
index 1b743657c..968798b32 100644
--- a/src/target/adi_v5_swd.c
+++ b/src/target/adi_v5_swd.c
@@ -99,27 +99,31 @@ static inline int check_sync(struct adiv5_dap *dap)
 	return do_sync ? swd_run_inner(dap) : ERROR_OK;
 }
 
-/** Select the DP register bank matching bits 7:4 of reg. */
+/** Select the DP register bank */
 static int swd_queue_dp_bankselect(struct adiv5_dap *dap, unsigned int reg)
 {
-	/* Only register address 0 and 4 are banked. */
+	/* Only register address 0 (ADIv6 only) and 4 are banked. */
 	if ((reg & 0xf) > 4)
 		return ERROR_OK;
 
-	uint64_t sel = (reg & 0x000000F0) >> 4;
-	if (dap->select != DP_SELECT_INVALID)
-		sel |= dap->select & ~0xfULL;
+	uint32_t sel = (reg >> 4) & DP_SELECT_DPBANK;
 
-	if (sel == dap->select)
+	/* DP register 0 is not mapped according to ADIv5
+	 * whereas ADIv6 ensures DPBANKSEL = 0 after line reset */
+	if ((dap->select_valid || ((reg & 0xf) == 0 && dap->select_dpbanksel_valid))
+			&& (sel == (dap->select & DP_SELECT_DPBANK)))
 		return ERROR_OK;
 
-	dap->select = sel;
+	/* Use the AP part of dap->select regardless of dap->select_valid:
+	 * if !dap->select_valid
+	 * dap->select contains a speculative value likely going to be used
+	 * in the following swd_queue_ap_bankselect() */
+	sel |= (uint32_t)(dap->select & SELECT_AP_MASK);
 
-	int retval = swd_queue_dp_write_inner(dap, DP_SELECT, (uint32_t)sel);
-	if (retval != ERROR_OK)
-		dap->select = DP_SELECT_INVALID;
+	LOG_DEBUG_IO("DP BANK SELECT: %" PRIx32, sel);
 
-	return retval;
+	/* dap->select cache gets updated in the following call */
+	return swd_queue_dp_write_inner(dap, DP_SELECT, sel);
 }
 
 static int swd_queue_dp_read_inner(struct adiv5_dap *dap, unsigned int reg,
@@ -147,24 +151,31 @@ static int swd_queue_dp_write_inner(struct adiv5_dap *dap, unsigned int reg,
 	swd_finish_read(dap);
 
 	if (reg == DP_SELECT) {
-		dap->select = data & (ADIV5_DP_SELECT_APSEL | ADIV5_DP_SELECT_APBANK | DP_SELECT_DPBANK);
+		dap->select = data | (dap->select & (0xffffffffull << 32));
 
 		swd->write_reg(swd_cmd(false, false, reg), data, 0);
 
 		retval = check_sync(dap);
-		if (retval != ERROR_OK)
-			dap->select = DP_SELECT_INVALID;
+		dap->select_valid = (retval == ERROR_OK);
+		dap->select_dpbanksel_valid = dap->select_valid;
 
 		return retval;
 	}
 
+	if (reg == DP_SELECT1)
+		dap->select = ((uint64_t)data << 32) | (dap->select & 0xffffffffull);
+
 	retval = swd_queue_dp_bankselect(dap, reg);
-	if (retval != ERROR_OK)
-		return retval;
+	if (retval == ERROR_OK) {
+		swd->write_reg(swd_cmd(false, false, reg), data, 0);
+
+		retval = check_sync(dap);
+	}
 
-	swd->write_reg(swd_cmd(false, false, reg), data, 0);
+	if (reg == DP_SELECT1)
+		dap->select1_valid = (retval == ERROR_OK);
 
-	return check_sync(dap);
+	return retval;
 }
 
 
@@ -177,19 +188,17 @@ static int swd_multidrop_select_inner(struct adiv5_dap *dap, uint32_t *dpidr_ptr
 	assert(dap_is_multidrop(dap));
 
 	swd_send_sequence(dap, LINE_RESET);
-	/* From ARM IHI 0074C ADIv6.0, chapter B4.3.3 "Connection and line reset
-	 * sequence":
-	 * - line reset sets DP_SELECT_DPBANK to zero;
-	 * - read of DP_DPIDR takes the connection out of reset;
-	 * - write of DP_TARGETSEL keeps the connection in reset;
-	 * - other accesses return protocol error (SWDIO not driven by target).
-	 *
-	 * Read DP_DPIDR to get out of reset. Initialize dap->select to zero to
-	 * skip the write to DP_SELECT, avoiding the protocol error. Set again
-	 * dap->select to DP_SELECT_INVALID because the rest of the register is
-	 * unknown after line reset.
+	/*
+	 * Zero dap->select and set dap->select_dpbanksel_valid
+	 * to skip the write to DP_SELECT before DPIDR read, avoiding
+	 * the protocol error.
+	 * Clear the other validity flags because the rest of the DP
+	 * SELECT and SELECT1 registers is unknown after line reset.
 	 */
 	dap->select = 0;
+	dap->select_dpbanksel_valid = true;
+	dap->select_valid = false;
+	dap->select1_valid = false;
 
 	retval = swd_queue_dp_write_inner(dap, DP_TARGETSEL, dap->multidrop_targetsel);
 	if (retval != ERROR_OK)
@@ -209,8 +218,6 @@ static int swd_multidrop_select_inner(struct adiv5_dap *dap, uint32_t *dpidr_ptr
 			return retval;
 	}
 
-	dap->select = DP_SELECT_INVALID;
-
 	retval = swd_queue_dp_read_inner(dap, DP_DLPIDR, &dlpidr);
 	if (retval != ERROR_OK)
 		return retval;
@@ -335,19 +342,20 @@ static int swd_connect_single(struct adiv5_dap *dap)
 
 		/* The sequences to enter in SWD (JTAG_TO_SWD and DORMANT_TO_SWD) end
 		 * with a SWD line reset sequence (50 clk with SWDIO high).
-		 * From ARM IHI 0074C ADIv6.0, chapter B4.3.3 "Connection and line reset
-		 * sequence":
-		 * - line reset sets DP_SELECT_DPBANK to zero;
+		 * From ARM IHI 0031F ADIv5.2 and ARM IHI 0074C ADIv6.0,
+		 * chapter B4.3.3 "Connection and line reset sequence":
+		 * - DPv3 (ADIv6) only: line reset sets DP_SELECT_DPBANK to zero;
 		 * - read of DP_DPIDR takes the connection out of reset;
 		 * - write of DP_TARGETSEL keeps the connection in reset;
 		 * - other accesses return protocol error (SWDIO not driven by target).
 		 *
-		 * Read DP_DPIDR to get out of reset. Initialize dap->select to zero to
-		 * skip the write to DP_SELECT, avoiding the protocol error. Set again
-		 * dap->select to DP_SELECT_INVALID because the rest of the register is
-		 * unknown after line reset.
+		 * dap_invalidate_cache() sets dap->select to zero and all validity
+		 * flags to invalid. Set dap->select_dpbanksel_valid only
+		 * to skip the write to DP_SELECT, avoiding the protocol error.
+		 * Read DP_DPIDR to get out of reset.
 		 */
-		dap->select = 0;
+		dap->select_dpbanksel_valid = true;
+
 		retval = swd_queue_dp_read_inner(dap, DP_DPIDR, &dpidr);
 		if (retval == ERROR_OK) {
 			retval = swd_run_inner(dap);
@@ -360,8 +368,6 @@ static int swd_connect_single(struct adiv5_dap *dap)
 		dap->switch_through_dormant = !dap->switch_through_dormant;
 	} while (timeval_ms() < timeout);
 
-	dap->select = DP_SELECT_INVALID;
-
 	if (retval != ERROR_OK) {
 		LOG_ERROR("Error connecting DP: cannot read IDR");
 		return retval;
@@ -494,49 +500,55 @@ static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
 	return swd_queue_dp_write_inner(dap, reg, data);
 }
 
-/** Select the AP register bank matching bits 7:4 of reg. */
+/** Select the AP register bank */
 static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
 {
 	int retval;
 	struct adiv5_dap *dap = ap->dap;
 	uint64_t sel;
 
-	if (is_adiv6(dap)) {
+	if (is_adiv6(dap))
 		sel = ap->ap_num | (reg & 0x00000FF0);
-		if (sel == (dap->select & ~0xfULL))
-			return ERROR_OK;
-
-		if (dap->select != DP_SELECT_INVALID)
-			sel |= dap->select & 0xf;
-		dap->select = sel;
-		LOG_DEBUG("AP BANKSEL: %" PRIx64, sel);
-
-		retval = swd_queue_dp_write(dap, DP_SELECT, (uint32_t)sel);
+	else
+		sel = (ap->ap_num << 24) | (reg & ADIV5_DP_SELECT_APBANK);
 
-		if (retval == ERROR_OK && dap->asize > 32)
-			retval = swd_queue_dp_write(dap, DP_SELECT1, (uint32_t)(sel >> 32));
+	uint64_t sel_diff = (sel ^ dap->select) & SELECT_AP_MASK;
 
-		if (retval != ERROR_OK)
-			dap->select = DP_SELECT_INVALID;
+	bool set_select = !dap->select_valid || (sel_diff & 0xffffffffull);
+	bool set_select1 = is_adiv6(dap) && dap->asize > 32
+						&& (!dap->select1_valid
+							|| sel_diff & (0xffffffffull << 32));
 
-		return retval;
+	if (set_select && set_select1) {
+		/* Prepare DP bank for DP_SELECT1 now to save one write */
+		sel |= (DP_SELECT1 & 0x000000f0) >> 4;
+	} else {
+		/* Use the DP part of dap->select regardless of dap->select_valid:
+		 * if !dap->select_valid
+		 * dap->select contains a speculative value likely going to be used
+		 * in the following swd_queue_dp_bankselect().
+		 * Moreover dap->select_valid should never be false here as a DP bank
+		 * is always selected before selecting an AP bank */
+		sel |= dap->select & DP_SELECT_DPBANK;
 	}
 
-	/* ADIv5 */
-	sel = (ap->ap_num << 24) | (reg & ADIV5_DP_SELECT_APBANK);
-	if (dap->select != DP_SELECT_INVALID)
-		sel |= dap->select & DP_SELECT_DPBANK;
+	if (set_select) {
+		LOG_DEBUG_IO("AP BANK SELECT: %" PRIx32, (uint32_t)sel);
 
-	if (sel == dap->select)
-		return ERROR_OK;
+		retval = swd_queue_dp_write(dap, DP_SELECT, (uint32_t)sel);
+		if (retval != ERROR_OK)
+			return retval;
+	}
 
-	dap->select = sel;
+	if (set_select1) {
+		LOG_DEBUG_IO("AP BANK SELECT1: %" PRIx32, (uint32_t)(sel >> 32));
 
-	retval = swd_queue_dp_write_inner(dap, DP_SELECT, sel);
-	if (retval != ERROR_OK)
-		dap->select = DP_SELECT_INVALID;
+		retval = swd_queue_dp_write(dap, DP_SELECT1, (uint32_t)(sel >> 32));
+		if (retval != ERROR_OK)
+			return retval;
+	}
 
-	return retval;
+	return ERROR_OK;
 }
 
 static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index da5da3197..434bf50fe 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -655,7 +655,11 @@ int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
  */
 void dap_invalidate_cache(struct adiv5_dap *dap)
 {
-	dap->select = DP_SELECT_INVALID;
+	dap->select = 0;	/* speculate the first AP access will select AP 0, bank 0 */
+	dap->select_valid = false;
+	dap->select1_valid = false;
+	dap->select_dpbanksel_valid = false;
+
 	dap->last_read = NULL;
 
 	int i;
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index e21589363..e07b577af 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -100,7 +100,11 @@
 #define ADIV5_DP_SELECT_APSEL	0xFF000000
 #define ADIV5_DP_SELECT_APBANK	0x000000F0
 #define DP_SELECT_DPBANK		0x0000000F
-#define DP_SELECT_INVALID		0x00FFFF00 /* Reserved bits one */
+/*
+ * Mask of AP ADDR in select cache, concatenating DP SELECT and DP_SELECT1.
+ * In case of ADIv5, the mask contains both APSEL and APBANKSEL fields.
+ */
+#define SELECT_AP_MASK			(~(uint64_t)DP_SELECT_DPBANK)
 
 #define DP_APSEL_MAX			(255) /* Strict limit for ADIv5, number of AP buffers for ADIv6 */
 #define DP_APSEL_INVALID		0xF00 /* more than DP_APSEL_MAX and not ADIv6 aligned 4k */
@@ -338,11 +342,21 @@ struct adiv5_dap {
 	/* The current manually selected AP by the "dap apsel" command */
 	uint64_t apsel;
 
+	/** Cache for DP SELECT and SELECT1 (ADIv6) register. */
+	uint64_t select;
+	/** Validity of DP SELECT cache. false will force register rewrite */
+	bool select_valid;
+	bool select1_valid;	/* ADIv6 only */
 	/**
-	 * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
-	 * indicates no cached value and forces rewrite of the register.
+	 * Partial DPBANKSEL validity for SWD only.
+	 * ADIv6 line reset sets DP SELECT DPBANKSEL to zero,
+	 * ADIv5 does not.
+	 * We can rely on it for the banked DP register 0 also on ADIv5
+	 * as ADIv5 has no mapping for DP reg 0 - it is always DPIDR.
+	 * It is important to avoid setting DP SELECT in connection
+	 * reset state before reading DPIDR.
 	 */
-	uint64_t select;
+	bool select_dpbanksel_valid;
 
 	/* information about current pending SWjDP-AHBAP transaction */
 	uint8_t  ack;

-----------------------------------------------------------------------

Summary of changes:
 src/target/adi_v5_jtag.c |  89 +++++++++++++++++++---------
 src/target/adi_v5_swd.c  | 148 +++++++++++++++++++++++++----------------------
 src/target/arm_adi_v5.c  |   6 +-
 src/target/arm_adi_v5.h  |  22 +++++--
 4 files changed, 164 insertions(+), 101 deletions(-)


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Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-445-g492dc7c53

[openocd-gerrit <ope...@us...>]

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generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  492dc7c537d5685e5e6d41757b73eea2365b96ee (commit)
      from  49489747d26d4dcd679fb16afec61d90d7ca3586 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 492dc7c537d5685e5e6d41757b73eea2365b96ee
Author: Antonio Borneo <bor...@gm...>
Date:   Thu Dec 14 22:05:52 2023 +0100

    helper/bin2char: drop trailing empty line
    
    For unknown reasons, the coreutils tool 'od' on MacOS outputs an
    extra empty line, which appears in the new auto-generated files.
    
    Modify the script bin2char.sh to drop every empty line.
    
    Change-Id: Id835fecadb58ad4ddfc11ef9f9a2e8d75c5dffe9
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8051
    Reviewed-by: Erhan Kurubas <erh...@es...>
    Tested-by: jenkins
    Reviewed-by: Henrik Nordström <hen...@ad...>

diff --git a/src/helper/bin2char.sh b/src/helper/bin2char.sh
index b89433d86..cf94bee29 100755
--- a/src/helper/bin2char.sh
+++ b/src/helper/bin2char.sh
@@ -12,4 +12,4 @@
 }
 
 echo "/* Autogenerated with $0 */"
-od -v -A n -t x1 | sed 's/ *\(..\) */0x\1,/g'
+od -v -A n -t x1 | sed 's/ *\(..\) */0x\1,/g;/^$/d'

-----------------------------------------------------------------------

Summary of changes:
 src/helper/bin2char.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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