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From: openocd-gerrit <ope...@us...> - 2023-11-18 11:20:18
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 7c60f6593edd692cff90b8486412a9b8adba28d2 (commit)
from f8096ce68724d15d0ef9a7edfd6d2aaa0f83a6e5 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 7c60f6593edd692cff90b8486412a9b8adba28d2
Author: Kirill Radkin <kir...@sy...>
Date: Wed Oct 18 19:13:25 2023 +0300
breakpoints: Fix endless loop in bp/wp_clear_target
If we can't remove bp/wp, we will stuck in endless loop
Change-Id: I44c0a164db1d15c0a0637d33c75087a49cf5c0f4
Signed-off-by: Kirill Radkin <kir...@sy...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7940
Tested-by: jenkins
Reviewed-by: Anatoly P <kup...@gm...>
Reviewed-by: Tim Newsome <ti...@si...>
Reviewed-by: Jan Matyas <jan...@co...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c
index d9c12f523..d4662c4de 100644
--- a/src/target/breakpoints.c
+++ b/src/target/breakpoints.c
@@ -326,6 +326,8 @@ static int breakpoint_remove_internal(struct target *target, target_addr_t addre
static int breakpoint_remove_all_internal(struct target *target)
{
+ LOG_TARGET_DEBUG(target, "Delete all breakpoints");
+
struct breakpoint *breakpoint = target->breakpoints;
int retval = ERROR_OK;
@@ -464,22 +466,6 @@ int watchpoint_remove_all(struct target *target)
return breakpoint_watchpoint_remove_all(target, WATCHPOINT);
}
-static int breakpoint_clear_target_internal(struct target *target)
-{
- LOG_DEBUG("Delete all breakpoints for target: %s",
- target_name(target));
-
- int retval = ERROR_OK;
-
- while (target->breakpoints) {
- int status = breakpoint_free(target, target->breakpoints);
- if (status != ERROR_OK)
- retval = status;
- }
-
- return retval;
-}
-
int breakpoint_clear_target(struct target *target)
{
int retval = ERROR_OK;
@@ -489,13 +475,13 @@ int breakpoint_clear_target(struct target *target)
foreach_smp_target(head, target->smp_targets) {
struct target *curr = head->target;
- int status = breakpoint_clear_target_internal(curr);
+ int status = breakpoint_remove_all_internal(curr);
if (status != ERROR_OK)
retval = status;
}
} else {
- retval = breakpoint_clear_target_internal(target);
+ retval = breakpoint_remove_all_internal(target);
}
return retval;
@@ -659,16 +645,19 @@ int watchpoint_remove(struct target *target, target_addr_t address)
int watchpoint_clear_target(struct target *target)
{
- int retval = ERROR_OK;
-
LOG_DEBUG("Delete all watchpoints for target: %s",
target_name(target));
- while (target->watchpoints) {
- int status = watchpoint_free(target, target->watchpoints);
+
+ struct watchpoint *watchpoint = target->watchpoints;
+ int retval = ERROR_OK;
+
+ while (watchpoint) {
+ struct watchpoint *tmp = watchpoint;
+ watchpoint = watchpoint->next;
+ int status = watchpoint_free(target, tmp);
if (status != ERROR_OK)
retval = status;
}
-
return retval;
}
-----------------------------------------------------------------------
Summary of changes:
src/target/breakpoints.c | 35 ++++++++++++-----------------------
1 file changed, 12 insertions(+), 23 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2023-11-18 11:19:04
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via f8096ce68724d15d0ef9a7edfd6d2aaa0f83a6e5 (commit)
from 9ebc2a65191308d3677a84ebbbdad97a93eae7de (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit f8096ce68724d15d0ef9a7edfd6d2aaa0f83a6e5
Author: ianst <ia...@ca...>
Date: Thu Nov 9 07:28:50 2023 -0800
xtensa: update XDM register map for TRAX support
- Include additional debug module registers
- Add translation function for DM reg addr -> ID
- Add DM read/write commands
Signed-off-by: ianst <ia...@ca...>
Change-Id: If95419d24a9f27a40fa695c8c15326cdfd127ef1
Reviewed-on: https://review.openocd.org/c/openocd/+/7973
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 4eb911c3c..b03da4f83 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -11487,6 +11487,12 @@ Execute arbitrary instruction(s) provided as an ascii string. The string repres
number of instruction bytes, thus its length must be even.
@end deffn
+@deffn {Command} {xtensa dm} (address) [value]
+Read or write Xtensa Debug Module (DM) registers. @var{address} is required for both reads
+and writes and is a 4-byte-aligned value typically between 0 and 0x3ffc. @var{value} is specified
+only for write accesses.
+@end deffn
+
@subsection Xtensa Performance Monitor Configuration
@deffn {Command} {xtensa perfmon_enable} <counter_id> <select> [mask] [kernelcnt] [tracelevel]
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index c575b534e..2aacc3620 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -3978,6 +3978,38 @@ COMMAND_HANDLER(xtensa_cmd_smpbreak)
get_current_target(CMD_CTX));
}
+COMMAND_HELPER(xtensa_cmd_dm_rw_do, struct xtensa *xtensa)
+{
+ if (CMD_ARGC == 1) {
+ // read: xtensa dm addr
+ uint32_t addr = strtoul(CMD_ARGV[0], NULL, 0);
+ uint32_t val;
+ int res = xtensa_dm_read(&xtensa->dbg_mod, addr, &val);
+ if (res == ERROR_OK)
+ command_print(CMD, "xtensa DM(0x%08" PRIx32 ") -> 0x%08" PRIx32, addr, val);
+ else
+ command_print(CMD, "xtensa DM(0x%08" PRIx32 ") : read ERROR %" PRId32, addr, res);
+ return res;
+ } else if (CMD_ARGC == 2) {
+ // write: xtensa dm addr value
+ uint32_t addr = strtoul(CMD_ARGV[0], NULL, 0);
+ uint32_t val = strtoul(CMD_ARGV[1], NULL, 0);
+ int res = xtensa_dm_write(&xtensa->dbg_mod, addr, val);
+ if (res == ERROR_OK)
+ command_print(CMD, "xtensa DM(0x%08" PRIx32 ") <- 0x%08" PRIx32, addr, val);
+ else
+ command_print(CMD, "xtensa DM(0x%08" PRIx32 ") : write ERROR %" PRId32, addr, res);
+ return res;
+ }
+ return ERROR_COMMAND_SYNTAX_ERROR;
+}
+
+COMMAND_HANDLER(xtensa_cmd_dm_rw)
+{
+ return CALL_COMMAND_HANDLER(xtensa_cmd_dm_rw_do,
+ target_to_xtensa(get_current_target(CMD_CTX)));
+}
+
COMMAND_HELPER(xtensa_cmd_tracestart_do, struct xtensa *xtensa)
{
struct xtensa_trace_status trace_status;
@@ -4234,6 +4266,13 @@ static const struct command_registration xtensa_any_command_handlers[] = {
.help = "Set the way the CPU chains OCD breaks",
.usage = "[none|breakinout|runstall] | [BreakIn] [BreakOut] [RunStallIn] [DebugModeOut]",
},
+ {
+ .name = "dm",
+ .handler = xtensa_cmd_dm_rw,
+ .mode = COMMAND_ANY,
+ .help = "Xtensa DM read/write",
+ .usage = "addr [value]"
+ },
{
.name = "perfmon_enable",
.handler = xtensa_cmd_perfmon_enable,
diff --git a/src/target/xtensa/xtensa_debug_module.c b/src/target/xtensa/xtensa_debug_module.c
index 31d7a9435..8045779b8 100644
--- a/src/target/xtensa/xtensa_debug_module.c
+++ b/src/target/xtensa/xtensa_debug_module.c
@@ -34,6 +34,16 @@ static const struct xtensa_dm_pwr_reg_offsets xdm_pwr_regs[XDMREG_PWRNUM] =
static const struct xtensa_dm_reg_offsets xdm_regs[XDMREG_NUM] =
XTENSA_DM_REG_OFFSETS;
+static enum xtensa_dm_reg xtensa_dm_regaddr_to_id(uint32_t addr)
+{
+ enum xtensa_dm_reg id;
+ uint32_t addr_masked = (addr & (XTENSA_DM_APB_ALIGN - 1));
+ for (id = XDMREG_TRAXID; id < XDMREG_NUM; id++)
+ if (xdm_regs[id].apb == addr_masked)
+ break;
+ return id;
+}
+
static void xtensa_dm_add_set_ir(struct xtensa_debug_module *dm, uint8_t value)
{
struct scan_field field;
@@ -285,6 +295,34 @@ int xtensa_dm_core_status_clear(struct xtensa_debug_module *dm, xtensa_dsr_t bit
return xtensa_dm_queue_execute(dm);
}
+int xtensa_dm_read(struct xtensa_debug_module *dm, uint32_t addr, uint32_t *val)
+{
+ enum xtensa_dm_reg reg = xtensa_dm_regaddr_to_id(addr);
+ uint8_t buf[sizeof(uint32_t)];
+ if (reg < XDMREG_NUM) {
+ xtensa_dm_queue_enable(dm);
+ dm->dbg_ops->queue_reg_read(dm, reg, buf);
+ xtensa_dm_queue_tdi_idle(dm);
+ int res = xtensa_dm_queue_execute(dm);
+ if (res == ERROR_OK && val)
+ *val = buf_get_u32(buf, 0, 32);
+ return res;
+ }
+ return ERROR_FAIL;
+}
+
+int xtensa_dm_write(struct xtensa_debug_module *dm, uint32_t addr, uint32_t val)
+{
+ enum xtensa_dm_reg reg = xtensa_dm_regaddr_to_id(addr);
+ if (reg < XDMREG_NUM) {
+ xtensa_dm_queue_enable(dm);
+ dm->dbg_ops->queue_reg_write(dm, reg, val);
+ xtensa_dm_queue_tdi_idle(dm);
+ return xtensa_dm_queue_execute(dm);
+ }
+ return ERROR_FAIL;
+}
+
int xtensa_dm_trace_start(struct xtensa_debug_module *dm, struct xtensa_trace_start_config *cfg)
{
/*Turn off trace unit so we can start a new trace. */
diff --git a/src/target/xtensa/xtensa_debug_module.h b/src/target/xtensa/xtensa_debug_module.h
index 46b29354c..495da2a64 100644
--- a/src/target/xtensa/xtensa_debug_module.h
+++ b/src/target/xtensa/xtensa_debug_module.h
@@ -75,6 +75,22 @@ enum xtensa_dm_reg {
XDMREG_DELAYCNT,
XDMREG_MEMADDRSTART,
XDMREG_MEMADDREND,
+ XDMREG_EXTTIMELO,
+ XDMREG_EXTTIMEHI,
+ XDMREG_TRAXRSVD48,
+ XDMREG_TRAXRSVD4C,
+ XDMREG_TRAXRSVD50,
+ XDMREG_TRAXRSVD54,
+ XDMREG_TRAXRSVD58,
+ XDMREG_TRAXRSVD5C,
+ XDMREG_TRAXRSVD60,
+ XDMREG_TRAXRSVD64,
+ XDMREG_TRAXRSVD68,
+ XDMREG_TRAXRSVD6C,
+ XDMREG_TRAXRSVD70,
+ XDMREG_TRAXRSVD74,
+ XDMREG_CONFIGID0,
+ XDMREG_CONFIGID1,
/* Performance Monitor Registers */
XDMREG_PMG,
@@ -168,6 +184,22 @@ struct xtensa_dm_reg_offsets {
{ .nar = 0x07, .apb = 0x001c }, /* XDMREG_DELAYCNT */ \
{ .nar = 0x08, .apb = 0x0020 }, /* XDMREG_MEMADDRSTART */ \
{ .nar = 0x09, .apb = 0x0024 }, /* XDMREG_MEMADDREND */ \
+ { .nar = 0x10, .apb = 0x0040 }, /* XDMREG_EXTTIMELO */ \
+ { .nar = 0x11, .apb = 0x0044 }, /* XDMREG_EXTTIMEHI */ \
+ { .nar = 0x12, .apb = 0x0048 }, /* XDMREG_TRAXRSVD48 */ \
+ { .nar = 0x13, .apb = 0x004c }, /* XDMREG_TRAXRSVD4C */ \
+ { .nar = 0x14, .apb = 0x0050 }, /* XDMREG_TRAXRSVD50 */ \
+ { .nar = 0x15, .apb = 0x0054 }, /* XDMREG_TRAXRSVD54 */ \
+ { .nar = 0x16, .apb = 0x0058 }, /* XDMREG_TRAXRSVD58 */ \
+ { .nar = 0x17, .apb = 0x005c }, /* XDMREG_TRAXRSVD5C */ \
+ { .nar = 0x18, .apb = 0x0060 }, /* XDMREG_TRAXRSVD60 */ \
+ { .nar = 0x19, .apb = 0x0064 }, /* XDMREG_TRAXRSVD64 */ \
+ { .nar = 0x1a, .apb = 0x0068 }, /* XDMREG_TRAXRSVD68 */ \
+ { .nar = 0x1b, .apb = 0x006c }, /* XDMREG_TRAXRSVD6C */ \
+ { .nar = 0x1c, .apb = 0x0070 }, /* XDMREG_TRAXRSVD70 */ \
+ { .nar = 0x1d, .apb = 0x0074 }, /* XDMREG_TRAXRSVD74 */ \
+ { .nar = 0x1e, .apb = 0x0078 }, /* XDMREG_CONFIGID0 */ \
+ { .nar = 0x1f, .apb = 0x007c }, /* XDMREG_CONFIGID1 */ \
\
/* Performance Monitor Registers */ \
{ .nar = 0x20, .apb = 0x1000 }, /* XDMREG_PMG */ \
@@ -297,6 +329,11 @@ struct xtensa_dm_reg_offsets {
#define DEBUGCAUSE_DI BIT(5) /* Debug Interrupt */
#define DEBUGCAUSE_VALID BIT(31) /* Pseudo-value to trigger reread (NX only) */
+/* TRAXID */
+#define TRAXID_PRODNO_TRAX 0 /* TRAXID.PRODNO value for TRAX module */
+#define TRAXID_PRODNO_SHIFT 28
+#define TRAXID_PRODNO_MASK 0xf
+
#define TRAXCTRL_TREN BIT(0) /* Trace enable. Tracing starts on 0->1 */
#define TRAXCTRL_TRSTP BIT(1) /* Trace Stop. Make 1 to stop trace. */
#define TRAXCTRL_PCMEN BIT(2) /* PC match enable */
@@ -512,6 +549,9 @@ static inline xtensa_dsr_t xtensa_dm_core_status_get(struct xtensa_debug_module
return dm->core_status.dsr;
}
+int xtensa_dm_read(struct xtensa_debug_module *dm, uint32_t addr, uint32_t *val);
+int xtensa_dm_write(struct xtensa_debug_module *dm, uint32_t addr, uint32_t val);
+
int xtensa_dm_device_id_read(struct xtensa_debug_module *dm);
static inline xtensa_ocdid_t xtensa_dm_device_id_get(struct xtensa_debug_module *dm)
{
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 6 +++++
src/target/xtensa/xtensa.c | 39 ++++++++++++++++++++++++++++++++
src/target/xtensa/xtensa_debug_module.c | 38 +++++++++++++++++++++++++++++++
src/target/xtensa/xtensa_debug_module.h | 40 +++++++++++++++++++++++++++++++++
4 files changed, 123 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2023-11-18 11:18:07
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 9ebc2a65191308d3677a84ebbbdad97a93eae7de (commit)
from 3862e07688ea68298841891145deddd226c3c7e5 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 9ebc2a65191308d3677a84ebbbdad97a93eae7de
Author: ianst <ia...@ca...>
Date: Fri Oct 20 13:00:41 2023 -0700
doc: xtensa architecture clarifications/fixes
- Fix Xtensa .cfg file references for NXP EVK
- Add clarification note for "xtensa xtmem" command
- Resolve TEX build warnings
Signed-off-by: ianst <ia...@ca...>
Change-Id: I0f2b56d0d084d86f557fadf3ac35fd04bf99650c
Reviewed-on: https://review.openocd.org/c/openocd/+/7972
Tested-by: jenkins
Reviewed-by: Erhan Kurubas <erh...@es...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 45c2e4df5..4eb911c3c 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -11364,16 +11364,18 @@ NOTE: @file{xtensa-core-XXX.cfg} must match the target Xtensa hardware
connected to OpenOCD.
Some example Xtensa configurations are bundled with OpenOCD for reference:
-@itemize @bullet
+@enumerate
@item Cadence Palladium VDebug emulation target. The user can combine their
@file{xtensa-core-XXX.cfg} with the provided
@file{board/xtensa-palladium-vdebug.cfg} to debug an emulated Xtensa RTL design.
-@item NXP MIMXRT685-EVK evaluation kit. The relevant configuration files are
-@file{board/xtensa-rt685-jlink.cfg} and @file{board/xtensa-core-nxp_rt600.cfg}.
-Additional information is provided by
-@uref{https://www.nxp.com/design/development-boards/i-mx-evaluation-and-development-boards/i-mx-rt600-evaluation-kit:MIMXRT685-EVK,
-NXP}.
+@item NXP MIMXRT685-EVK evaluation kit. The relevant configuration files are:
+@itemize @bullet
+@item @file{board/xtensa-rt685-ext.cfg}
+@item @file{target/xtensa-core-nxp_rt600.cfg}
@end itemize
+Additional information is available by searching for "i.MX RT600 Evaluation Kit"
+on @url{https://www.nxp.com}.
+@end enumerate
@subsection Xtensa Configuration Commands
@@ -11398,6 +11400,11 @@ others may be common to both but have different valid ranges.
Configure Xtensa target memory. Memory type determines access rights,
where RAMs are read/write while ROMs are read-only. @var{baseaddr} and
@var{bytes} are both integers, typically hexadecimal and decimal, respectively.
+
+NOTE: Some Xtensa memory types, such as system RAM/ROM or MMIO/device regions,
+can be added or modified after the Xtensa core has been generated. Additional
+@code{xtensa xtmem} definitions should be manually added to xtensa-core-XXX.cfg
+to keep OpenOCD's target address map consistent with the Xtensa configuration.
@end deffn
@deffn {Config Command} {xtensa xtmem} (@option{icache}|@option{dcache}) linebytes cachebytes ways [writeback]
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 19 +++++++++++++------
1 file changed, 13 insertions(+), 6 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2023-11-18 11:17:24
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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commit 3862e07688ea68298841891145deddd226c3c7e5
Author: Marc Schink <de...@za...>
Date: Wed Nov 1 09:27:05 2023 +0100
target: Remove break/watchpoints in target_destroy()
Break- and watchpoints are not removed when a target is destroyed
which introduces a memory leak.
Change-Id: I6143d48f7efd765b7752a12fdc337da3496d896f
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7956
Reviewed-by: Marek Vrbka <mar...@co...>
Reviewed-by: Tomas Vanek <va...@fb...>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/target.c b/src/target/target.c
index 148bc9fb7..30f7029a5 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -2212,6 +2212,9 @@ uint32_t target_get_working_area_avail(struct target *target)
static void target_destroy(struct target *target)
{
+ breakpoint_remove_all(target);
+ watchpoint_remove_all(target);
+
if (target->type->deinit_target)
target->type->deinit_target(target);
-----------------------------------------------------------------------
Summary of changes:
src/target/target.c | 3 +++
1 file changed, 3 insertions(+)
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From: openocd-gerrit <ope...@us...> - 2023-11-18 11:17:06
|
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generated because a ref change was pushed to the repository containing
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commit d4575b647a3603200a9bb4a784d170f792ab88d0
Author: Antonio Borneo <bor...@gm...>
Date: Sun Nov 5 17:02:26 2023 +0100
target: fix segmentation fault on target create
In the unusual (and even incorrect) case of running the command
target create ...
before defining an adapter and the associated transport, the
command causes a segmentation fault. E.g.:
openocd -c 'target create cpu cortex-m -endian little'
Check that get_current_transport() returns a valid pointer before
referencing it.
Change-Id: I9796a7e92196ef3df5c7152b27c34102045dc9e7
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7962
Reviewed-by: Tomas Vanek <va...@fb...>
Tested-by: jenkins
diff --git a/src/target/target.c b/src/target/target.c
index d368cb515..148bc9fb7 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -6143,7 +6143,7 @@ static int target_create(struct jim_getopt_info *goi)
if (e != JIM_OK)
return e;
struct transport *tr = get_current_transport();
- if (tr->override_target) {
+ if (tr && tr->override_target) {
e = tr->override_target(&cp);
if (e != ERROR_OK) {
LOG_ERROR("The selected transport doesn't support this target");
-----------------------------------------------------------------------
Summary of changes:
src/target/target.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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From: openocd-gerrit <ope...@us...> - 2023-11-18 11:16:42
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit b39072f2ef72f02601b40931d3a38c465804a906
Author: Antonio Borneo <bor...@gm...>
Date: Sun Nov 5 12:55:27 2023 +0100
target: use boolean values for 'valid' and 'dirty' flags
Convert to boolean the remaining numeric assignment and comparison
Change-Id: Idc25221d93e85236185aab9ee36f0a379939c89c
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7961
Reviewed-by: zapb <de...@za...>
Tested-by: jenkins
diff --git a/src/target/arc.c b/src/target/arc.c
index 45005b29b..0f7b11025 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -1265,8 +1265,8 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
/* current = 1: continue on current PC, otherwise continue at <address> */
if (!current) {
target_buffer_set_u32(target, pc->value, address);
- pc->dirty = 1;
- pc->valid = 1;
+ pc->dirty = true;
+ pc->valid = true;
LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address);
}
@@ -1281,7 +1281,7 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
resume_pc, pc->dirty, pc->valid);
/* check if GDB tells to set our PC where to continue from */
- if ((pc->valid == 1) && (resume_pc == target_buffer_get_u32(target, pc->value))) {
+ if (pc->valid && resume_pc == target_buffer_get_u32(target, pc->value)) {
value = target_buffer_get_u32(target, pc->value);
LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32, value);
CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_PC_REG, value));
@@ -2007,8 +2007,8 @@ static int arc_step(struct target *target, int current, target_addr_t address,
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current) {
buf_set_u32(pc->value, 0, 32, address);
- pc->dirty = 1;
- pc->valid = 1;
+ pc->dirty = true;
+ pc->valid = true;
}
LOG_DEBUG("Target steps one instruction from PC=0x%" PRIx32,
diff --git a/src/target/etm.c b/src/target/etm.c
index 6718875ee..d083017f7 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -552,8 +552,8 @@ static int etm_set_reg(struct reg *reg, uint32_t value)
}
buf_set_u32(reg->value, 0, reg->size, value);
- reg->valid = 1;
- reg->dirty = 0;
+ reg->valid = true;
+ reg->dirty = false;
return ERROR_OK;
}
diff --git a/src/target/mips64.c b/src/target/mips64.c
index 37f36855c..48f4563dc 100644
--- a/src/target/mips64.c
+++ b/src/target/mips64.c
@@ -247,8 +247,8 @@ static int mips64_set_core_reg(struct reg *reg, uint8_t *buf)
return ERROR_TARGET_NOT_HALTED;
buf_set_u64(reg->value, 0, 64, value);
- reg->dirty = 1;
- reg->valid = 1;
+ reg->dirty = true;
+ reg->valid = true;
return ERROR_OK;
}
@@ -265,8 +265,8 @@ static int mips64_read_core_reg(struct target *target, int num)
reg_value = mips64->core_regs[num];
buf_set_u64(mips64->core_cache->reg_list[num].value, 0, 64, reg_value);
- mips64->core_cache->reg_list[num].valid = 1;
- mips64->core_cache->reg_list[num].dirty = 0;
+ mips64->core_cache->reg_list[num].valid = true;
+ mips64->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
@@ -284,8 +284,8 @@ static int mips64_write_core_reg(struct target *target, int num)
reg_value = buf_get_u64(mips64->core_cache->reg_list[num].value, 0, 64);
mips64->core_regs[num] = reg_value;
LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value);
- mips64->core_cache->reg_list[num].valid = 1;
- mips64->core_cache->reg_list[num].dirty = 0;
+ mips64->core_cache->reg_list[num].valid = true;
+ mips64->core_cache->reg_list[num].dirty = false;
return ERROR_OK;
}
@@ -297,8 +297,8 @@ int mips64_invalidate_core_regs(struct target *target)
unsigned int i;
for (i = 0; i < mips64->core_cache->num_regs; i++) {
- mips64->core_cache->reg_list[i].valid = 0;
- mips64->core_cache->reg_list[i].dirty = 0;
+ mips64->core_cache->reg_list[i].valid = false;
+ mips64->core_cache->reg_list[i].dirty = false;
}
return ERROR_OK;
diff --git a/src/target/mips_mips64.c b/src/target/mips_mips64.c
index bf6095358..9921e9380 100644
--- a/src/target/mips_mips64.c
+++ b/src/target/mips_mips64.c
@@ -625,8 +625,8 @@ static int mips_mips64_resume(struct target *target, int current,
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current) {
buf_set_u64(pc->value, 0, 64, address);
- pc->dirty = 1;
- pc->valid = 1;
+ pc->dirty = true;
+ pc->valid = true;
}
resume_pc = buf_get_u64(pc->value, 0, 64);
@@ -717,8 +717,8 @@ static int mips_mips64_step(struct target *target, int current,
* <address> */
if (!current) {
buf_set_u64(pc->value, 0, 64, address);
- pc->dirty = 1;
- pc->valid = 1;
+ pc->dirty = true;
+ pc->valid = true;
}
/* the front-end may request us not to handle breakpoints */
-----------------------------------------------------------------------
Summary of changes:
src/target/arc.c | 10 +++++-----
src/target/etm.c | 4 ++--
src/target/mips64.c | 16 ++++++++--------
src/target/mips_mips64.c | 8 ++++----
4 files changed, 19 insertions(+), 19 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2023-11-18 11:16:25
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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from 9fcf33da8e09fb93a1f3f1eb0409e64a820698b4 (commit)
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commit 5587710c1a0537df78d87bcc0472e25a974d91c1
Author: Antonio Borneo <bor...@gm...>
Date: Sat Nov 4 15:55:24 2023 +0100
nor: rsl10: fix minor coding style
I use a script to compare the commands in the code with the ones
in the documentation.
Fix the style of the data to simplify the parsing.
Change-Id: I0f1d7e9ff5e2928312ca1a2f3424f82d2910580a
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7960
Tested-by: jenkins
Reviewed-by: zapb <de...@za...>
diff --git a/src/flash/nor/rsl10.c b/src/flash/nor/rsl10.c
index 5f0ac9b8f..c286e9ac8 100644
--- a/src/flash/nor/rsl10.c
+++ b/src/flash/nor/rsl10.c
@@ -815,7 +815,8 @@ static const struct command_registration rsl10_exec_command_handlers[] = {
.help = "Mass erase all unprotected flash areas",
.usage = "",
},
- COMMAND_REGISTRATION_DONE};
+ COMMAND_REGISTRATION_DONE
+};
static const struct command_registration rsl10_command_handlers[] = {
{
@@ -825,7 +826,8 @@ static const struct command_registration rsl10_command_handlers[] = {
.usage = "",
.chain = rsl10_exec_command_handlers,
},
- COMMAND_REGISTRATION_DONE};
+ COMMAND_REGISTRATION_DONE
+};
const struct flash_driver rsl10_flash = {
.name = "rsl10",
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/rsl10.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2023-11-11 18:49:09
|
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commit 9fcf33da8e09fb93a1f3f1eb0409e64a820698b4
Author: Antonio Borneo <bor...@gm...>
Date: Thu Nov 9 15:15:10 2023 +0100
contrib/rtos-helpers/FreeRTOS-openocd: change license to CC0-1.0
This file is intended to be included in any user's project that
plans to use OpenOCD awareness for FreeRTOS.
It is supposed to be distributed under a permissive license to not
impact the original license of the user's project.
Distribute it under Creative Commons Zero v1.0 Universal license.
Change-Id: I7ac90e8b742517bcafc08c00662625671c8159c4
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7995
Reviewed-by: Karl Palsson <ka...@tw...>
Reviewed-by: Paul Fertser <fer...@gm...>
Tested-by: jenkins
diff --git a/contrib/rtos-helpers/FreeRTOS-openocd.c b/contrib/rtos-helpers/FreeRTOS-openocd.c
index 000453d5d..5f82ac7a2 100644
--- a/contrib/rtos-helpers/FreeRTOS-openocd.c
+++ b/contrib/rtos-helpers/FreeRTOS-openocd.c
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
+// SPDX-License-Identifier: CC0-1.0
/*
* Since at least FreeRTOS V7.5.3 uxTopUsedPriority is no longer
commit edf8e916a266b5df15f456fcec748caf6b2b350c
Author: Antonio Borneo <bor...@gm...>
Date: Thu Nov 9 15:12:08 2023 +0100
LICENSES: Add the CC0-1.0 license
Add the full text of the CC0-1.0 license to the OpenOCD tree. It
was copied directly from:
https://spdx.org/licenses/CC0-1.0.html#licenseText
Add the required tags for reference and tooling.
Change-Id: Iae9c1431b6ffdd68ad5780deb78a257edb0b67f3
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7994
Tested-by: jenkins
Reviewed-by: Karl Palsson <ka...@tw...>
diff --git a/LICENSES/preferred/CC0-1.0 b/LICENSES/preferred/CC0-1.0
new file mode 100644
index 000000000..ba3c8c795
--- /dev/null
+++ b/LICENSES/preferred/CC0-1.0
@@ -0,0 +1,130 @@
+Valid-License-Identifier: CC0-1.0
+SPDX-URL: https://spdx.org/licenses/CC0-1.0.html
+Usage-Guide:
+ To use the Creative Commons Zero v1.0 Universal License put the following
+ SPDX tag/value pair into a comment according to the placement guidelines in
+ the licensing rules documentation:
+ SPDX-License-Identifier: CC0-1.0
+License-Text:
+
+Creative Commons Legal Code
+
+CC0 1.0 Universal
+
+ CREATIVE COMMONS CORPORATION IS NOT A LAW FIRM AND DOES NOT PROVIDE
+ LEGAL SERVICES. DISTRIBUTION OF THIS DOCUMENT DOES NOT CREATE AN
+ ATTORNEY-CLIENT RELATIONSHIP. CREATIVE COMMONS PROVIDES THIS
+ INFORMATION ON AN "AS-IS" BASIS. CREATIVE COMMONS MAKES NO WARRANTIES
+ REGARDING THE USE OF THIS DOCUMENT OR THE INFORMATION OR WORKS
+ PROVIDED HEREUNDER, AND DISCLAIMS LIABILITY FOR DAMAGES RESULTING FROM
+ THE USE OF THIS DOCUMENT OR THE INFORMATION OR WORKS PROVIDED
+ HEREUNDER.
+
+Statement of Purpose
+
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+1. Copyright and Related Rights. A Work made available under CC0 may be
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+ vi. database rights (such as those arising under Directive 96/9/EC of the
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+vii. other similar, equivalent or corresponding rights throughout the
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+
+2. Waiver. To the greatest extent permitted by, but not in contravention
+of, applicable law, Affirmer hereby overtly, fully, permanently,
+irrevocably and unconditionally waives, abandons, and surrenders all of
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+3. Public License Fallback. Should any part of the Waiver for any reason
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+limitation commercial, advertising or promotional purposes (the
+"License"). The License shall be deemed effective as of the date CC0 was
+applied by Affirmer to the Work. Should any part of the License for any
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+partial invalidity or ineffectiveness shall not invalidate the remainder
+of the License, and in such case Affirmer hereby affirms that he or she
+will not (i) exercise any of his or her remaining Copyright and Related
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+action with respect to the Work, in either case contrary to Affirmer's
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+
+4. Limitations and Disclaimers.
+
+ a. No trademark or patent rights held by Affirmer are waived, abandoned,
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diff --git a/Makefile.am b/Makefile.am
index a4f77adc2..153c471a9 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -64,6 +64,7 @@ EXTRA_DIST += \
LICENSES/preferred/BSD-2-Clause-Views \
LICENSES/preferred/BSD-3-Clause \
LICENSES/preferred/BSD-Source-Code \
+ LICENSES/preferred/CC0-1.0 \
LICENSES/preferred/GFDL-1.2 \
LICENSES/preferred/gfdl-1.2.texi.readme \
LICENSES/preferred/GPL-2.0 \
commit d378c3a1d637b61afd4c4f9c2c075cc05be2cb9d
Author: Daniel Anselmi <dan...@gm...>
Date: Mon Sep 25 00:05:38 2023 +0200
pld/certus: fix crash when loading bitstream
Loading a bitstream to cetrus device crashed due to
missing initialization.
Change-Id: Ibd9a04b84e514f9635af01a2b73bae478e534eb7
Signed-off-by: Daniel Anselmi <dan...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7908
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/pld/certus.c b/src/pld/certus.c
index a49501f54..ccb3feb90 100644
--- a/src/pld/certus.c
+++ b/src/pld/certus.c
@@ -121,6 +121,7 @@ static int lattice_certus_enable_programming(struct jtag_tap *tap)
uint8_t buffer = 0;
field.num_bits = 8;
field.out_value = &buffer;
+ field.in_value = NULL;
jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
jtag_add_runtest(2, TAP_IDLE);
return jtag_execute_queue();
-----------------------------------------------------------------------
Summary of changes:
LICENSES/preferred/CC0-1.0 | 130 ++++++++++++++++++++++++++++++++
Makefile.am | 1 +
contrib/rtos-helpers/FreeRTOS-openocd.c | 2 +-
src/pld/certus.c | 1 +
4 files changed, 133 insertions(+), 1 deletion(-)
create mode 100644 LICENSES/preferred/CC0-1.0
hooks/post-receive
--
Main OpenOCD repository
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|
From: openocd-gerrit <ope...@us...> - 2023-11-11 18:47:29
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 5b878b6e8b23d4c4b7aa3bf157c262e4f8620882
Author: Nishanth Menon <nm...@ti...>
Date: Tue Oct 17 16:10:17 2023 -0500
tcl/board: Add TI AM273 launchpad config
Add basic connection details with AM273 Launchpad
For further details, see: https://www.ti.com/tool/LP-AM273
Change-Id: I88a02cdbccb65c185e808503d080cc1f12c909ae
Signed-off-by: Nishanth Menon <nm...@ti...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7951
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/board/ti_am273_launchpad.cfg b/tcl/board/ti_am273_launchpad.cfg
new file mode 100644
index 000000000..c17170bf1
--- /dev/null
+++ b/tcl/board/ti_am273_launchpad.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments AM273 Launchpad
+# https://www.ti.com/tool/LP-AM273
+#
+
+# AM273 Launchpad has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+ set SOC am273
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 250
commit cb60f75a56ba54b5a52da00add5312f94bb67c86
Author: Nishanth Menon <nm...@ti...>
Date: Tue Oct 17 16:07:41 2023 -0500
tcl/target/ti_k3: Add AM273 SoC
Add support for the TI K3 family AM273 SoC.
For further details, see https://www.ti.com/lit/pdf/spruiu0
Change-Id: Ifa21d0760831f4f525ecd976fb8d086ffdbc9e9f
Signed-off-by: Nishanth Menon <nm...@ti...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7950
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 24b3fae87..23825b86b 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -6,6 +6,8 @@
# Has 4 R5 Cores, M4F and an M3
# * AM263: https://www.ti.com/lit/pdf/spruj17
# Has 4 R5 Cores and an M3
+# * AM273: https://www.ti.com/lit/pdf/spruiu0
+# Has 2 R5 Cores and an M3
# * AM625: https://www.ti.com/lit/pdf/spruiv7a
# Has 4 ARMV8 Cores and 1 R5 Core and an M4F
# * AM62A7: https://www.ti.com/lit/pdf/spruj16a
@@ -91,6 +93,25 @@ switch $_soc {
set R5_CTIBASE {0x90038000 0x90039000 0x90058000 0x90059000}
set _r5_ap_num 5
}
+ am273 {
+ set _K3_DAP_TAPID 0x1bb6a02f
+
+ # Mem-ap port
+ set _mem_ap_num 6
+
+ # system controller is on AP0
+ set _sysctrl_ap_num 0
+
+ # AM273 has 0 ARMV8 CPUs
+ set _armv8_cores 0
+
+ # AM273 has 1 cluster of 2 R5s cores.
+ set _r5_cores 2
+ set R5_NAMES {main0_r5.0 main0_r5.1}
+ set R5_DBGBASE {0x90030000 0x90032000}
+ set R5_CTIBASE {0x90038000 0x90039000}
+ set _r5_ap_num 5
+ }
am654 {
set _K3_DAP_TAPID 0x0bb5a02f
commit 17f34355e550900c6563431c35517c8e082cd5e2
Author: Nishanth Menon <nm...@ti...>
Date: Tue Oct 17 16:02:44 2023 -0500
tcl/board: Add TI AM263 launchpad config
Add basic connection details with AM263 Launchpad
For further details, see: https://www.ti.com/tool/LP-AM263
Change-Id: I94c7a9ca70734ae89c6df3f02137d5bd32fde774
Signed-off-by: Nishanth Menon <nm...@ti...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7949
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/tcl/board/ti_am263_launchpad.cfg b/tcl/board/ti_am263_launchpad.cfg
new file mode 100644
index 000000000..a07a21b3d
--- /dev/null
+++ b/tcl/board/ti_am263_launchpad.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments AM263 Launchpad
+# https://www.ti.com/tool/LP-AM263
+#
+
+# AM263 Launchpad has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+ set SOC am263
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 250
commit e4e94a355d4cfd79a98df8ceefa8432a3a14d076
Author: Nishanth Menon <nm...@ti...>
Date: Tue Oct 17 16:00:27 2023 -0500
tcl/target/ti_k3: Add AM263 SoC
Add support for the TI K3 family AM263 SoC.
For further details, see https://www.ti.com/lit/pdf/spruim2
Change-Id: I9a91b3d675511661dfc2710a7183bd59b98da133
Signed-off-by: Nishanth Menon <nm...@ti...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7948
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index e4a235b29..24b3fae87 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -4,6 +4,8 @@
# Texas Instruments K3 devices:
# * AM243: https://www.ti.com/lit/pdf/spruim2
# Has 4 R5 Cores, M4F and an M3
+# * AM263: https://www.ti.com/lit/pdf/spruj17
+# Has 4 R5 Cores and an M3
# * AM625: https://www.ti.com/lit/pdf/spruiv7a
# Has 4 ARMV8 Cores and 1 R5 Core and an M4F
# * AM62A7: https://www.ti.com/lit/pdf/spruj16a
@@ -73,6 +75,22 @@ set _mem_ap_num 2
# Set configuration overrides for each SOC
switch $_soc {
+ am263 {
+ set _K3_DAP_TAPID 0x2bb7d02f
+
+ # Mem-ap port
+ set _mem_ap_num 6
+
+ # AM263 has 0 ARMV8 CPUs
+ set _armv8_cores 0
+
+ # AM263 has 2 cluster of 2 R5s cores.
+ set _r5_cores 4
+ set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
+ set R5_DBGBASE {0x90030000 0x90032000 0x90050000 0x90052000}
+ set R5_CTIBASE {0x90038000 0x90039000 0x90058000 0x90059000}
+ set _r5_ap_num 5
+ }
am654 {
set _K3_DAP_TAPID 0x0bb5a02f
commit ba39343e3d5e1c8878f314e496172d829c22e231
Author: Nishanth Menon <nm...@ti...>
Date: Tue Oct 17 15:53:59 2023 -0500
tcl/board: Add TI AM243 launchpad config
Add basic connection details with AM243 Launchpad
For further details, see: https://www.ti.com/tool/LP-AM243
Change-Id: Id8cec6675a222888b0007484209558d6503dbcda
Signed-off-by: Nishanth Menon <nm...@ti...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7947
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/board/ti_am243_launchpad.cfg b/tcl/board/ti_am243_launchpad.cfg
new file mode 100644
index 000000000..aa75dda88
--- /dev/null
+++ b/tcl/board/ti_am243_launchpad.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments AM243 Launchpad
+# https://www.ti.com/tool/LP-AM243
+#
+
+# AM243 Launchpad has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+ set SOC am243
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 250
commit a646057c7eaf52e077afac98405c2aa2fa7d96bb
Author: Nishanth Menon <nm...@ti...>
Date: Tue Oct 17 15:50:49 2023 -0500
tcl/target/ti_k3: Add AM243 SoC
Add support for the TI K3 family AM243 SoC. This SoC is built on the
same base of AM642, so reuse the configuration with the exception of
Cortex-A53 which is not available on this device.
For further details, see https://www.ti.com/lit/pdf/spruim2
Change-Id: I971ba878b0f503e5120f6853634776eb61d05080
Signed-off-by: Nishanth Menon <nm...@ti...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7946
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index f1f8994f1..e4a235b29 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -2,6 +2,8 @@
# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
#
# Texas Instruments K3 devices:
+# * AM243: https://www.ti.com/lit/pdf/spruim2
+# Has 4 R5 Cores, M4F and an M3
# * AM625: https://www.ti.com/lit/pdf/spruiv7a
# Has 4 ARMV8 Cores and 1 R5 Core and an M4F
# * AM62A7: https://www.ti.com/lit/pdf/spruj16a
@@ -85,6 +87,7 @@ switch $_soc {
# Sysctrl power-ap unlock offsets
set _sysctrl_ap_unlock_offsets {0xf0 0x50}
}
+ am243 -
am642 {
set _K3_DAP_TAPID 0x0bb3802f
@@ -102,6 +105,12 @@ switch $_soc {
# M4 processor
set _gp_mcu_cores 1
+
+ # Overrides for am243
+ if { "$_soc" == "am243" } {
+ # Uses the same JTAG ID
+ set _armv8_cores 0
+ }
}
am625 {
set _K3_DAP_TAPID 0x0bb7e02f
commit 7919b0965b1b75a9e1a8fe33defb83528196683e
Author: Nishanth Menon <nm...@ti...>
Date: Tue Oct 17 15:47:12 2023 -0500
tcl/target/ti_k3: Sort the SoC documentation alphabetically
Sort the documentation for the TI K3 parts alphabetically.
Change-Id: I2c40714ad590e3d9232a6f915c157d677e0c3610
Signed-off-by: Nishanth Menon <nm...@ti...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7945
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 4e563f2be..f1f8994f1 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -2,24 +2,24 @@
# Copyright (C) 2019-2021 Texas Instruments Incorporated - http://www.ti.com/
#
# Texas Instruments K3 devices:
+# * AM625: https://www.ti.com/lit/pdf/spruiv7a
+# Has 4 ARMV8 Cores and 1 R5 Core and an M4F
+# * AM62A7: https://www.ti.com/lit/pdf/spruj16a
+# Has 4 ARMV8 Cores and 2 R5 Cores
+# * AM62P: https://www.ti.com/lit/pdf/spruj83
+# Has 4 ARMV8 Cores and 2 R5 Cores
+# * AM642: https://www.ti.com/lit/pdf/spruim2
+# Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
# * AM654x: https://www.ti.com/lit/pdf/spruid7
# Has 4 ARMV8 Cores and 2 R5 Cores and an M3
-# * J721E: https://www.ti.com/lit/pdf/spruil1
-# Has 2 ARMV8 Cores and 6 R5 Cores and an M3
# * J7200: https://www.ti.com/lit/pdf/spruiu1
# Has 2 ARMV8 Cores and 4 R5 Cores and an M3
+# * J721E: https://www.ti.com/lit/pdf/spruil1
+# Has 2 ARMV8 Cores and 6 R5 Cores and an M3
# * J721S2: https://www.ti.com/lit/pdf/spruj28
# Has 2 ARMV8 Cores and 6 R5 Cores and an M4F
# * J784S4/AM69: http://www.ti.com/lit/zip/spruj52
# Has 8 ARMV8 Cores and 8 R5 Cores
-# * AM642: https://www.ti.com/lit/pdf/spruim2
-# Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
-# * AM625: https://www.ti.com/lit/pdf/spruiv7a
-# Has 4 ARMV8 Cores and 1 R5 Core and an M4F
-# * AM62a7: https://www.ti.com/lit/pdf/spruj16a
-# Has 4 ARMV8 Cores and 2 R5 Cores
-# * AM62P: https://www.ti.com/lit/pdf/spruj83
-# Has 4 ARMV8 Cores and 2 R5 Cores
#
source [find target/swj-dp.tcl]
commit 9a79dfb709ad84d243cb866928b4253c7ea45078
Author: Nishanth Menon <nm...@ti...>
Date: Tue Oct 17 15:36:55 2023 -0500
tcl/target/ti_k3: Make Cortex-A processors optional
The AM2x family of K3 SoCs typically do not contain a Cortex-A53 or
A72 processor. So, make the cpu "up" functions available when armv8
processor count > 0.
Change-Id: I985b194fe7cc63e4134ad84ccd921cc456eb412f
Signed-off-by: Nishanth Menon <nm...@ti...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7944
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index bb2a991ce..4e563f2be 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -341,24 +341,26 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
}
}
-# Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
-set _armv8_up_cmd "$_armv8_cpu_name"_up
-# Available if V8_SMP_DEBUG is set to non-zero value
-set _armv8_smp_cmd "$_armv8_cpu_name"_smp
-
-if { $_v8_smp_debug == 0 } {
- proc $_armv8_up_cmd { args } {
- foreach _core $args {
- targets $_core
- _cpu_no_smp_up
+if { $_armv8_cores > 0 } {
+ # Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
+ set _armv8_up_cmd "$_armv8_cpu_name"_up
+ # Available if V8_SMP_DEBUG is set to non-zero value
+ set _armv8_smp_cmd "$_armv8_cpu_name"_smp
+
+ if { $_v8_smp_debug == 0 } {
+ proc $_armv8_up_cmd { args } {
+ foreach _core $args {
+ targets $_core
+ _cpu_no_smp_up
+ }
}
+ } else {
+ proc $_armv8_smp_cmd { args } {
+ _armv8_smp_up
+ }
+ # Declare SMP
+ target smp {*}$_v8_smp_targets
}
-} else {
- proc $_armv8_smp_cmd { args } {
- _armv8_smp_up
- }
- # Declare SMP
- target smp {*}$_v8_smp_targets
}
for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
-----------------------------------------------------------------------
Summary of changes:
.../{ti_am62pevm.cfg => ti_am243_launchpad.cfg} | 9 +-
.../{ti_am62pevm.cfg => ti_am263_launchpad.cfg} | 9 +-
.../{ti_am62pevm.cfg => ti_am273_launchpad.cfg} | 9 +-
tcl/target/ti_k3.cfg | 100 +++++++++++++++------
4 files changed, 90 insertions(+), 37 deletions(-)
copy tcl/board/{ti_am62pevm.cfg => ti_am243_launchpad.cfg} (73%)
copy tcl/board/{ti_am62pevm.cfg => ti_am263_launchpad.cfg} (73%)
copy tcl/board/{ti_am62pevm.cfg => ti_am273_launchpad.cfg} (73%)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2023-11-11 18:44:55
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 5ea20d7ed99e252947a85f93db870109cc094efc (commit)
via 4b879bb01737f11a11f05c3b4feb09e6ddc85a5d (commit)
from 00b07390826f7cd5f72bc036e3907a87c6cbc33d (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 5ea20d7ed99e252947a85f93db870109cc094efc
Author: Nishanth Menon <nm...@ti...>
Date: Wed Oct 18 13:45:39 2023 -0500
tcl/target/ti_k3: Convert memory access ap port num as a variable
Convert the memory access ap port num as a variable to allow support
for the AM2x family of K3 SoCs.
Change-Id: Ibd96c94055721f60d95179dab21d014c15b0f562
Signed-off-by: Nishanth Menon <nm...@ti...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7943
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index e05b81a17..bb2a991ce 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -66,6 +66,9 @@ set _gp_mcu_cores 0
# General Purpose MCU power-ap unlock offsets
set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
+# Generic mem-ap port number
+set _mem_ap_num 2
+
# Set configuration overrides for each SOC
switch $_soc {
am654 {
@@ -423,5 +426,5 @@ if { 0 == [string compare [adapter name] dmem ] } {
}
} else {
# AXI AP access port for SoC address map
- target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num 2
+ target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num $_mem_ap_num
}
commit 4b879bb01737f11a11f05c3b4feb09e6ddc85a5d
Author: Nishanth Menon <nm...@ti...>
Date: Tue Oct 17 13:56:00 2023 -0500
tcl/target/ti_k3: Convert Cortex-R5 ap port num as a variable
Convert the Cortex-R5 ap port num as a variable to allow support for
the AM2x family of K3 SoCs.
Change-Id: I7dc8b459dca8b5f21395230b5cb782b14538bd48
Signed-off-by: Nishanth Menon <nm...@ti...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7942
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 78ee8b2ca..e05b81a17 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -56,6 +56,7 @@ set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
+set _r5_ap_num 1
# Finally an General Purpose(GP) MCU
set CM4_CTIBASE {0x20001000}
@@ -359,12 +360,12 @@ if { $_v8_smp_debug == 0 } {
for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
set _r5_name [lindex $R5_NAMES $_core]
- cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \
+ cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num $_r5_ap_num \
-baseaddr [lindex $R5_CTIBASE $_core]
# inactive core examination will fail - wait till startup of additional core
target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
- -dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine \
+ -dbgbase [lindex $R5_DBGBASE $_core] -ap-num $_r5_ap_num -defer-examine \
-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]
$_TARGETNAME.$_r5_name configure -event gdb-attach {
-----------------------------------------------------------------------
Summary of changes:
tcl/target/ti_k3.cfg | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2023-11-11 18:44:41
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 00b07390826f7cd5f72bc036e3907a87c6cbc33d (commit)
from 42441fd96cf86ffca61f77afe24aae21fb00bb89 (commit)
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- Log -----------------------------------------------------------------
commit 00b07390826f7cd5f72bc036e3907a87c6cbc33d
Author: Nishanth Menon <nm...@ti...>
Date: Tue Oct 17 13:51:51 2023 -0500
tcl/target/ti_k3: Convert sysctrl ap port num as a variable
Convert the sysctrl ap port num as a variable to allow support for the
AM2x family of K3 SoCs.
Change-Id: I1b5b55e48240e6654779dd636fdf07bca055e192
Signed-off-by: Nishanth Menon <nm...@ti...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7941
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 1cd85eec3..78ee8b2ca 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -44,6 +44,7 @@ set CM3_CTIBASE {0x3C016000}
# sysctrl power-ap unlock offsets
set _sysctrl_ap_unlock_offsets {0xf0 0x44}
+set _sysctrl_ap_num 7
# All the ARMV8s are the next processors.
# CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1
@@ -266,9 +267,11 @@ set _TARGETNAME $_CHIPNAME.cpu
set _CTINAME $_CHIPNAME.cti
# sysctrl is always present
-cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
+cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap \
+ -ap-num $_sysctrl_ap_num -baseaddr [lindex $CM3_CTIBASE 0]
-target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine \
+target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap \
+ -ap-num $_sysctrl_ap_num -defer-examine \
-rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl]
$_TARGETNAME.sysctrl configure -event reset-assert { }
-----------------------------------------------------------------------
Summary of changes:
tcl/target/ti_k3.cfg | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2023-11-11 18:44:18
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 42441fd96cf86ffca61f77afe24aae21fb00bb89 (commit)
from a9080087d82688043ca216d50926228d09631297 (commit)
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- Log -----------------------------------------------------------------
commit 42441fd96cf86ffca61f77afe24aae21fb00bb89
Author: Peter Collingbourne <pc...@go...>
Date: Thu Oct 19 19:07:29 2023 -0700
target: Add a debug_reason command
This allows programmatically determining the debug reason.
Change-Id: I0c3e85cebb6dc28fc0fc212beca84a484ac654a5
Signed-off-by: Peter Collingbourne <pc...@go...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7952
Reviewed-by: Jan Matyas <jan...@co...>
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/doc/openocd.texi b/doc/openocd.texi
index a2965189f..45c2e4df5 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5296,6 +5296,18 @@ Displays the current target state:
(Also, @pxref{eventpolling,,Event Polling}.)
@end deffn
+@deffn {Command} {$target_name debug_reason}
+Displays the current debug reason:
+@code{debug-request},
+@code{breakpoint},
+@code{watchpoint},
+@code{watchpoint-and-breakpoint},
+@code{single-step},
+@code{target-not-halted},
+@code{program-exit},
+@code{exception-catch} or @code{undefined}.
+@end deffn
+
@deffn {Command} {$target_name eventlist}
Displays a table listing all event handlers
currently associated with this target.
diff --git a/src/target/target.c b/src/target/target.c
index 61c243510..d368cb515 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -5874,6 +5874,18 @@ COMMAND_HANDLER(handle_target_current_state)
return ERROR_OK;
}
+COMMAND_HANDLER(handle_target_debug_reason)
+{
+ if (CMD_ARGC != 0)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct target *target = get_current_target(CMD_CTX);
+
+ command_print(CMD, "%s", debug_reason_name(target));
+
+ return ERROR_OK;
+}
+
static int jim_target_invoke_event(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
{
struct jim_getopt_info goi;
@@ -6025,6 +6037,13 @@ static const struct command_registration target_instance_command_handlers[] = {
.help = "displays the current state of this target",
.usage = "",
},
+ {
+ .name = "debug_reason",
+ .mode = COMMAND_EXEC,
+ .handler = handle_target_debug_reason,
+ .help = "displays the debug reason of this target",
+ .usage = "",
+ },
{
.name = "arp_examine",
.mode = COMMAND_EXEC,
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 12 ++++++++++++
src/target/target.c | 19 +++++++++++++++++++
2 files changed, 31 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2023-11-11 18:06:16
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via a9080087d82688043ca216d50926228d09631297 (commit)
from 0f261188f1161a685b22c1e3d3e07b3666a31971 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit a9080087d82688043ca216d50926228d09631297
Author: Erhan Kurubas <erh...@es...>
Date: Sat Oct 28 20:58:08 2023 +0200
target/breakpoints: make breakpoint_watchpoint_remove_all static
Fixes below Sparse tool warning.
warning: symbol 'breakpoint_watchpoint_remove_all' was not declared.
Should it be static?
Signed-off-by: Erhan Kurubas <erh...@es...>
Change-Id: I4af1d5aa54abcb45f746b877513ba0b5fccbeb47
Reviewed-on: https://review.openocd.org/c/openocd/+/7955
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
Reviewed-by: Jan Matyas <jan...@co...>
Reviewed-by: Marek Vrbka <mar...@co...>
diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c
index 07d0a7371..d9c12f523 100644
--- a/src/target/breakpoints.c
+++ b/src/target/breakpoints.c
@@ -425,7 +425,7 @@ static int watchpoint_remove_all_internal(struct target *target)
return retval;
}
-int breakpoint_watchpoint_remove_all(struct target *target, enum breakpoint_watchpoint bp_wp)
+static int breakpoint_watchpoint_remove_all(struct target *target, enum breakpoint_watchpoint bp_wp)
{
assert(bp_wp == BREAKPOINT || bp_wp == WATCHPOINT);
int retval = ERROR_OK;
-----------------------------------------------------------------------
Summary of changes:
src/target/breakpoints.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2023-11-11 18:05:42
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 0f261188f1161a685b22c1e3d3e07b3666a31971 (commit)
from d209598ce93bf9477f9c81c7c44b6756c63ccbf3 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 0f261188f1161a685b22c1e3d3e07b3666a31971
Author: Evgeniy Naydanov <evg...@sy...>
Date: Tue Oct 10 13:57:43 2023 +0300
target: fix a memory leak in image_open
Change-Id: I629be26e7752858091ad58c2b3b07f43e22e8c23
Signed-off-by: Evgeniy Naydanov <evg...@sy...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7935
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/target/image.c b/src/target/image.c
index e998a35f4..9175c200a 100644
--- a/src/target/image.c
+++ b/src/target/image.c
@@ -968,12 +968,13 @@ int image_open(struct image *image, const char *url, const char *type_string)
retval = fileio_open(&image_binary->fileio, url, FILEIO_READ, FILEIO_BINARY);
if (retval != ERROR_OK)
- return retval;
+ goto free_mem_on_error;
+
size_t filesize;
retval = fileio_size(image_binary->fileio, &filesize);
if (retval != ERROR_OK) {
fileio_close(image_binary->fileio);
- return retval;
+ goto free_mem_on_error;
}
image->num_sections = 1;
@@ -988,14 +989,14 @@ int image_open(struct image *image, const char *url, const char *type_string)
retval = fileio_open(&image_ihex->fileio, url, FILEIO_READ, FILEIO_TEXT);
if (retval != ERROR_OK)
- return retval;
+ goto free_mem_on_error;
retval = image_ihex_buffer_complete(image);
if (retval != ERROR_OK) {
LOG_ERROR(
"failed buffering IHEX image, check server output for additional information");
fileio_close(image_ihex->fileio);
- return retval;
+ goto free_mem_on_error;
}
} else if (image->type == IMAGE_ELF) {
struct image_elf *image_elf;
@@ -1004,12 +1005,12 @@ int image_open(struct image *image, const char *url, const char *type_string)
retval = fileio_open(&image_elf->fileio, url, FILEIO_READ, FILEIO_BINARY);
if (retval != ERROR_OK)
- return retval;
+ goto free_mem_on_error;
retval = image_elf_read_headers(image);
if (retval != ERROR_OK) {
fileio_close(image_elf->fileio);
- return retval;
+ goto free_mem_on_error;
}
} else if (image->type == IMAGE_MEMORY) {
struct target *target = get_target(url);
@@ -1039,14 +1040,14 @@ int image_open(struct image *image, const char *url, const char *type_string)
retval = fileio_open(&image_mot->fileio, url, FILEIO_READ, FILEIO_TEXT);
if (retval != ERROR_OK)
- return retval;
+ goto free_mem_on_error;
retval = image_mot_buffer_complete(image);
if (retval != ERROR_OK) {
LOG_ERROR(
"failed buffering S19 image, check server output for additional information");
fileio_close(image_mot->fileio);
- return retval;
+ goto free_mem_on_error;
}
} else if (image->type == IMAGE_BUILDER) {
image->num_sections = 0;
@@ -1067,6 +1068,11 @@ int image_open(struct image *image, const char *url, const char *type_string)
}
return retval;
+
+free_mem_on_error:
+ free(image->type_private);
+ image->type_private = NULL;
+ return retval;
};
int image_read_section(struct image *image,
-----------------------------------------------------------------------
Summary of changes:
src/target/image.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2023-11-11 18:04:52
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via d209598ce93bf9477f9c81c7c44b6756c63ccbf3 (commit)
from 7d1f132cea58017003534a45ad444e55c23fd5be (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit d209598ce93bf9477f9c81c7c44b6756c63ccbf3
Author: Walter Ji <wal...@os...>
Date: Tue Sep 26 17:11:00 2023 +0800
target/mips32: update mips32 config register parsing
Enhance `mips32_read_config_regs` to better detect MIPS32 ISA,
DSP, and FPU features, allowing user to get more detailed
target information.
Most of these information will be used in MIPS m/iAptiv support.
Change-Id: I23571a626ec64fa019acac91bdbfcb434373bfc1
Signed-off-by: Walter Ji <wal...@os...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7911
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 99688b008..5c346c42d 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -805,15 +805,82 @@ int mips32_cpu_probe(struct target *target)
return ERROR_OK;
}
+/* reads dsp implementation info from CP0 Config3 register {DSPP, DSPREV}*/
+void mips32_read_config_dsp(struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
+{
+ uint32_t dsp_present = ((ejtag_info->config[3] & MIPS32_CONFIG3_DSPP_MASK) >> MIPS32_CONFIG3_DSPP_SHIFT);
+ if (dsp_present) {
+ mips32->dsp_imp = ((ejtag_info->config[3] & MIPS32_CONFIG3_DSPREV_MASK) >> MIPS32_CONFIG3_DSPREV_SHIFT) + 1;
+ LOG_USER("DSP implemented: %s, rev %d", "yes", mips32->dsp_imp);
+ } else {
+ LOG_USER("DSP implemented: %s", "no");
+ }
+}
+
+/* read fpu implementation info from CP0 Config1 register {CU1, FP}*/
+int mips32_read_config_fpu(struct mips32_common *mips32, struct mips_ejtag *ejtag_info)
+{
+ int retval;
+ uint32_t fp_imp = (ejtag_info->config[1] & MIPS32_CONFIG1_FP_MASK) >> MIPS32_CONFIG1_FP_SHIFT;
+ char buf[60] = {0};
+ if (!fp_imp) {
+ LOG_USER("FPU implemented: %s", "no");
+ mips32->fp_imp = MIPS32_FP_IMP_NONE;
+ return ERROR_OK;
+ }
+ uint32_t status_value;
+ bool status_fr, status_cu1;
+
+ retval = mips32_cp0_read(ejtag_info, &status_value, MIPS32_C0_STATUS, 0);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to read cp0 status register");
+ return retval;
+ }
+
+ status_fr = (status_value >> MIPS32_CP0_STATUS_FR_SHIFT) & 0x1;
+ status_cu1 = (status_value >> MIPS32_CP0_STATUS_CU1_SHIFT) & 0x1;
+ if (status_cu1) {
+ /* TODO: read fpu(cp1) config register for current operating mode.
+ * Now its set to 32 bits by default. */
+ snprintf(buf, sizeof(buf), "yes");
+ fp_imp = MIPS32_FP_IMP_32;
+ } else {
+ snprintf(buf, sizeof(buf), "yes, disabled");
+ fp_imp = MIPS32_FP_IMP_UNKNOWN;
+ }
+
+ mips32->fpu_in_64bit = status_fr;
+ mips32->fpu_enabled = status_cu1;
+
+ LOG_USER("FPU implemented: %s", buf);
+ mips32->fp_imp = fp_imp;
+
+ return ERROR_OK;
+}
+
+/* Checks if current target implements Common Device Memory Map and therefore Fast Debug Channel (MD00090) */
+void mips32_read_config_fdc(struct mips32_common *mips32, struct mips_ejtag *ejtag_info, uint32_t dcr)
+{
+ if (((ejtag_info->config[3] & MIPS32_CONFIG3_CDMM_MASK) != 0) && ((dcr & EJTAG_DCR_FDC) != 0)) {
+ mips32->fdc = 1;
+ mips32->semihosting = 1;
+ } else {
+ mips32->fdc = 0;
+ mips32->semihosting = 0;
+ }
+}
+
/* read config to config3 cp0 registers and log isa implementation */
int mips32_read_config_regs(struct target *target)
{
struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+ char buf[60] = {0};
+ int retval;
if (ejtag_info->config_regs == 0)
for (int i = 0; i != 4; i++) {
- int retval = mips32_cp0_read(ejtag_info, &ejtag_info->config[i], 16, i);
+ retval = mips32_cp0_read(ejtag_info, &ejtag_info->config[i], 16, i);
if (retval != ERROR_OK) {
LOG_ERROR("isa info not available, failed to read cp0 config register: %" PRId32, i);
ejtag_info->config_regs = 0;
@@ -828,27 +895,56 @@ int mips32_read_config_regs(struct target *target)
LOG_DEBUG("read %"PRIu32" config registers", ejtag_info->config_regs);
+ mips32->isa_rel = (ejtag_info->config[0] & MIPS32_CONFIG0_AR_MASK) >> MIPS32_CONFIG0_AR_SHIFT;
+ snprintf(buf, sizeof(buf), ", release %s(AR=%d)",
+ mips32->isa_rel == MIPS32_RELEASE_1 ? "1"
+ : mips32->isa_rel == MIPS32_RELEASE_2 ? "2"
+ : mips32->isa_rel == MIPS32_RELEASE_6 ? "6"
+ : "unknown", mips32->isa_rel);
+
if (ejtag_info->impcode & EJTAG_IMP_MIPS16) {
mips32->isa_imp = MIPS32_MIPS16;
- LOG_USER("MIPS32 with MIPS16 support implemented");
-
+ LOG_USER("ISA implemented: %s%s", "MIPS32, MIPS16", buf);
} else if (ejtag_info->config_regs >= 4) { /* config3 implemented */
unsigned isa_imp = (ejtag_info->config[3] & MIPS32_CONFIG3_ISA_MASK) >> MIPS32_CONFIG3_ISA_SHIFT;
if (isa_imp == 1) {
mips32->isa_imp = MMIPS32_ONLY;
- LOG_USER("MICRO MIPS32 only implemented");
+ LOG_USER("ISA implemented: %s%s", "microMIPS32", buf);
} else if (isa_imp != 0) {
mips32->isa_imp = MIPS32_MMIPS32;
- LOG_USER("MIPS32 and MICRO MIPS32 implemented");
+ LOG_USER("ISA implemented: %s%s", "MIPS32, microMIPS32", buf);
}
+ } else if (mips32->isa_imp == MIPS32_ONLY) {
+ /* initial default value */
+ LOG_USER("ISA implemented: %s%s", "MIPS32", buf);
}
- if (mips32->isa_imp == MIPS32_ONLY) /* initial default value */
- LOG_USER("MIPS32 only implemented");
+ /* Retrieve DSP info */
+ mips32_read_config_dsp(mips32, ejtag_info);
+
+ /* Retrieve if Float Point CoProcessor Implemented */
+ retval = mips32_read_config_fpu(mips32, ejtag_info);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("fpu info is not available, error while reading cp0 status");
+ mips32->fp_imp = MIPS32_FP_IMP_NONE;
+ return retval;
+ }
+
+ uint32_t dcr;
+
+ retval = target_read_u32(target, EJTAG_DCR, &dcr);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("failed to read EJTAG_DCR register");
+ return retval;
+ }
+
+ /* Determine if FDC and CDMM are implemented for this core */
+ mips32_read_config_fdc(mips32, ejtag_info, dcr);
return ERROR_OK;
}
+
int mips32_checksum_memory(struct target *target, target_addr_t address,
uint32_t count, uint32_t *checksum)
{
diff --git a/src/target/mips32.h b/src/target/mips32.h
index 7bf638458..d072eb99a 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -46,9 +46,21 @@
#define MIPS32_CONFIG0_AR_SHIFT 10
#define MIPS32_CONFIG0_AR_MASK (0x7 << MIPS32_CONFIG0_AR_SHIFT)
+#define MIPS32_CONFIG1_FP_SHIFT 0
+#define MIPS32_CONFIG1_FP_MASK BIT(MIPS32_CONFIG1_FP_SHIFT)
+
#define MIPS32_CONFIG1_DL_SHIFT 10
#define MIPS32_CONFIG1_DL_MASK (0x7 << MIPS32_CONFIG1_DL_SHIFT)
+#define MIPS32_CONFIG3_CDMM_SHIFT 3
+#define MIPS32_CONFIG3_CDMM_MASK BIT(MIPS32_CONFIG3_CDMM_SHIFT)
+
+#define MIPS32_CONFIG3_DSPP_SHIFT 10
+#define MIPS32_CONFIG3_DSPP_MASK BIT(MIPS32_CONFIG3_DSPP_SHIFT)
+
+#define MIPS32_CONFIG3_DSPREV_SHIFT 11
+#define MIPS32_CONFIG3_DSPREV_MASK BIT(MIPS32_CONFIG3_DSPREV_SHIFT)
+
#define MIPS32_CONFIG3_ISA_SHIFT 14
#define MIPS32_CONFIG3_ISA_MASK (3 << MIPS32_CONFIG3_ISA_SHIFT)
@@ -57,6 +69,8 @@
#define MIPS32_SCAN_DELAY_LEGACY_MODE 2000000
+#define MIPS32_NUM_DSPREGS 9
+
/* Bit Mask indicating CP0 register supported by this core */
#define MIPS_CP0_MK4 0x0001
#define MIPS_CP0_MAPTIV_UC 0x0002
@@ -237,6 +251,31 @@ enum mips32_isa_imp {
MIPS32_MMIPS32 = 3,
};
+/* Release 2~5 does not have much change regarding to the ISA under User mode,
+* therefore no new Architecture Revision(AR) level is assigned to them.
+* Release 6 changed some instruction's encoding/mnemonic, removed instructions that
+* has lost its purposes/none are using, and added some new instructions as well.
+*/
+enum mips32_isa_rel {
+ MIPS32_RELEASE_1 = 0,
+ MIPS32_RELEASE_2 = 1,
+ MIPS32_RELEASE_6 = 2,
+ MIPS32_RELEASE_UNKNOWN,
+};
+
+enum mips32_fp_imp {
+ MIPS32_FP_IMP_NONE = 0,
+ MIPS32_FP_IMP_32 = 1,
+ MIPS32_FP_IMP_64 = 2,
+ MIPS32_FP_IMP_UNKNOWN = 3,
+};
+
+enum mips32_dsp_imp {
+ MIPS32_DSP_IMP_NONE = 0,
+ MIPS32_DSP_IMP_REV1 = 1,
+ MIPS32_DSP_IMP_REV2 = 2,
+};
+
struct mips32_comparator {
int used;
uint32_t bp_value;
@@ -261,6 +300,18 @@ struct mips32_common {
enum mips32_isa_mode isa_mode;
enum mips32_isa_imp isa_imp;
+ enum mips32_isa_rel isa_rel;
+ enum mips32_fp_imp fp_imp;
+ enum mips32_dsp_imp dsp_imp;
+
+ int fdc;
+ int semihosting;
+ uint32_t cp0_mask;
+
+ /* FPU enabled (cp0.status.cu1) */
+ bool fpu_enabled;
+ /* FPU mode (cp0.status.fr) */
+ bool fpu_in_64bit;
/* processor identification register */
uint32_t prid;
@@ -560,6 +611,173 @@ struct mips32_algorithm {
#define MIPS16_SDBBP(isa) (isa ? MMIPS16_SDBBP : MIPS16_ISA_SDBBP)
+/*
+ * MIPS32 Config1 Register (CP0 Register 16, Select 1)
+ */
+#define MIPS32_CFG1_M 0x80000000 /* Config2 implemented */
+#define MIPS32_CFG1_MMUSMASK 0x7e000000 /* mmu size - 1 */
+#define MIPS32_CFG1_MMUSSHIFT 25
+#define MIPS32_CFG1_ISMASK 0x01c00000 /* icache lines 64<<n */
+#define MIPS32_CFG1_ISSHIFT 22
+#define MIPS32_CFG1_ILMASK 0x00380000 /* icache line size 2<<n */
+#define MIPS32_CFG1_ILSHIFT 19
+#define MIPS32_CFG1_IAMASK 0x00070000 /* icache ways - 1 */
+#define MIPS32_CFG1_IASHIFT 16
+#define MIPS32_CFG1_DSMASK 0x0000e000 /* dcache lines 64<<n */
+#define MIPS32_CFG1_DSSHIFT 13
+#define MIPS32_CFG1_DLMASK 0x00001c00 /* dcache line size 2<<n */
+#define MIPS32_CFG1_DLSHIFT 10
+#define MIPS32_CFG1_DAMASK 0x00000380 /* dcache ways - 1 */
+#define MIPS32_CFG1_DASHIFT 7
+#define MIPS32_CFG1_C2 0x00000040 /* Coprocessor 2 present */
+#define MIPS32_CFG1_MD 0x00000020 /* MDMX implemented */
+#define MIPS32_CFG1_PC 0x00000010 /* performance counters implemented */
+#define MIPS32_CFG1_WR 0x00000008 /* watch registers implemented */
+#define MIPS32_CFG1_CA 0x00000004 /* compression (mips16) implemented */
+#define MIPS32_CFG1_EP 0x00000002 /* ejtag implemented */
+#define MIPS32_CFG1_FP 0x00000001 /* fpu implemented */
+
+/*
+ * MIPS32 Coprocessor 0 register numbers
+ */
+#define MIPS32_C0_INDEX 0
+#define MIPS32_C0_INX 0
+#define MIPS32_C0_RANDOM 1
+#define MIPS32_C0_RAND 1
+#define MIPS32_C0_ENTRYLO0 2
+#define MIPS32_C0_TLBLO0 2
+#define MIPS32_C0_ENTRYLO1 3
+#define MIPS32_C0_TLBLO1 3
+#define MIPS32_C0_CONTEXT 4
+#define MIPS32_C0_CTXT 4
+#define MIPS32_C0_PAGEMASK 5
+#define MIPS32_C0_PAGEGRAIN (5, 1)
+#define MIPS32_C0_WIRED 6
+#define MIPS32_C0_HWRENA 7
+#define MIPS32_C0_BADVADDR 8
+#define MIPS32_C0_VADDR 8
+#define MIPS32_C0_COUNT 9
+#define MIPS32_C0_ENTRYHI 10
+#define MIPS32_C0_TLBHI 10
+#define MIPS32_C0_GUESTCTL1 10
+#define MIPS32_C0_COMPARE 11
+#define MIPS32_C0_STATUS 12
+#define MIPS32_C0_SR 12
+#define MIPS32_C0_INTCTL (12, 1)
+#define MIPS32_C0_SRSCTL (12, 2)
+#define MIPS32_C0_SRSMAP (12, 3)
+#define MIPS32_C0_CAUSE 13
+#define MIPS32_C0_CR 13
+#define MIPS32_C0_EPC 14
+#define MIPS32_C0_PRID 15
+#define MIPS32_C0_EBASE (15, 1)
+#define MIPS32_C0_CONFIG 16
+#define MIPS32_C0_CONFIG0 (16, 0)
+#define MIPS32_C0_CONFIG1 (16, 1)
+#define MIPS32_C0_CONFIG2 (16, 2)
+#define MIPS32_C0_CONFIG3 (16, 3)
+#define MIPS32_C0_LLADDR 17
+#define MIPS32_C0_WATCHLO 18
+#define MIPS32_C0_WATCHHI 19
+#define MIPS32_C0_DEBUG 23
+#define MIPS32_C0_DEPC 24
+#define MIPS32_C0_PERFCNT 25
+#define MIPS32_C0_ERRCTL 26
+#define MIPS32_C0_CACHEERR 27
+#define MIPS32_C0_TAGLO 28
+#define MIPS32_C0_ITAGLO 28
+#define MIPS32_C0_DTAGLO (28, 2)
+#define MIPS32_C0_TAGLO2 (28, 4)
+#define MIPS32_C0_DATALO (28, 1)
+#define MIPS32_C0_IDATALO (28, 1)
+#define MIPS32_C0_DDATALO (28, 3)
+#define MIPS32_C0_DATALO2 (28, 5)
+#define MIPS32_C0_TAGHI 29
+#define MIPS32_C0_ITAGHI 29
+#define MIPS32_C0_DATAHI (29, 1)
+#define MIPS32_C0_ERRPC 30
+#define MIPS32_C0_DESAVE 31
+
+/*
+ * MIPS32 MMU types
+ */
+#define MIPS32_MMU_TLB 1
+#define MIPS32_MMU_BAT 2
+#define MIPS32_MMU_FIXED 3
+#define MIPS32_MMU_DUAL_VTLB_FTLB 4
+
+enum mips32_cpu_vendor {
+ MIPS32_CPU_VENDOR_MTI,
+ MIPS32_CPU_VENDOR_ALCHEMY,
+ MIPS32_CPU_VENDOR_BROADCOM,
+ MIPS32_CPU_VENDOR_ALTERA,
+ MIPS32_CPU_VENDOR_LEXRA,
+};
+
+enum mips32_isa_supported {
+ MIPS16,
+ MIPS32,
+ MIPS64,
+ MICROMIPS_ONLY,
+ MIPS32_AT_RESET_AND_MICROMIPS,
+ MICROMIPS_AT_RESET_AND_MIPS32,
+};
+
+struct mips32_cpu_features {
+ /* Type of CPU (4Kc, 24Kf, etc.) */
+ uint32_t cpu_core;
+
+ /* Internal representation of cpu type */
+ uint32_t cpu_type;
+
+ /* Processor vendor */
+ enum mips32_cpu_vendor vendor;
+
+ /* Supported ISA and boot config */
+ enum mips32_isa_supported isa;
+
+ /* PRID */
+ uint32_t prid;
+
+ /* Processor implemented the MultiThreading ASE */
+ bool mtase;
+
+ /* Processor implemented the DSP ASE */
+ bool dspase;
+
+ /* Processor implemented the SmartMIPS ASE */
+ bool smase;
+
+ /* Processor implemented the MIPS16[e] ASE */
+ bool m16ase;
+
+ /* Processor implemented the microMIPS ASE */
+ bool micromipsase;
+
+ /* Processor implemented the Virtualization ASE */
+ uint32_t vzase;
+
+ uint32_t vz_guest_id_width;
+
+ /* ebase.cpuid number */
+ uint32_t cpuid;
+
+ uint32_t inst_cache_size;
+ uint32_t data_cache_size;
+ uint32_t mmu_type;
+ uint32_t tlb_entries;
+ uint32_t num_shadow_regs;
+
+ /* Processor implemented the MSA module */
+ bool msa;
+
+ /* Processor implemented mfhc0 and mthc0 instructions */
+ bool mvh;
+
+ bool guest_ctl1_present;
+ bool cdmm;
+};
+
extern const struct command_registration mips32_command_handlers[];
int mips32_arch_state(struct target *target);
-----------------------------------------------------------------------
Summary of changes:
src/target/mips32.c | 110 ++++++++++++++++++++++++--
src/target/mips32.h | 218 ++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 321 insertions(+), 7 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2023-11-11 18:04:28
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 7d1f132cea58017003534a45ad444e55c23fd5be (commit)
via cca530c09df312927291f27b010088d38342b1d4 (commit)
via f58b5ddaf27d899eca72c8707e32f1c3cfc25551 (commit)
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- Log -----------------------------------------------------------------
commit 7d1f132cea58017003534a45ad444e55c23fd5be
Author: Marek Vrbka <mar...@co...>
Date: Fri Nov 3 10:48:02 2023 +0100
target: Fix get_reg, prevent returning invalid data
This patch forces a read of register from the target
in the get_reg command in case the register cache
does not hold a valid value at that moment.
Note that the command "reg" already handles it
correctly, no fix is needed there.
Change-Id: I75fad25188e94ee4e06162ab6d600ea24dbf590a
Signed-off-by: Marek Vrbka <mar...@co...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7958
Reviewed-by: Jan Matyas <jan...@co...>
Reviewed-by: zapb <de...@za...>
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/target/target.c b/src/target/target.c
index 384b4ec84..61c243510 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -5149,7 +5149,7 @@ static int target_jim_get_reg(Jim_Interp *interp, int argc,
return JIM_ERR;
}
- if (force) {
+ if (force || !reg->valid) {
int retval = reg->type->get(reg);
if (retval != ERROR_OK) {
commit cca530c09df312927291f27b010088d38342b1d4
Author: Oliver Graute <oli...@ko...>
Date: Wed Nov 1 22:46:33 2023 +0100
tcl/board: add board configuration for Advantech IMX8QM DMSSE20
Change-Id: Iebf2a901b428cf3b99110aea0f3ab0e1f17b0250
Signed-off-by: Oliver Graute <oli...@ko...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7974
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
Reviewed-by: zapb <de...@za...>
diff --git a/tcl/board/advantech_imx8qm_dmsse20.cfg b/tcl/board/advantech_imx8qm_dmsse20.cfg
new file mode 100644
index 000000000..a867b2de0
--- /dev/null
+++ b/tcl/board/advantech_imx8qm_dmsse20.cfg
@@ -0,0 +1,23 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# configuration file for Advantech IMX8QM DMSSE20
+#
+
+# only JTAG supported
+transport select jtag
+
+# set a safe JTAG clock speed, can be overridden
+adapter speed 1000
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 70
+
+# board has an i.MX8QM with 4 Cortex-A53 cores and 2 Cortex-A72
+set CHIPNAME imx8qm
+set CHIPCORES 6
+
+# source SoC configuration
+source [find tcl/target/imx8qm.cfg]
commit f58b5ddaf27d899eca72c8707e32f1c3cfc25551
Author: Marc Schink <de...@za...>
Date: Fri Nov 3 11:04:08 2023 +0100
target/target: Use boolean values for 'valid' flag
Change-Id: Ieaa25b9ef0997c0f75ddfb652325c1a9e53a8d8d
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7959
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Jan Matyas <jan...@co...>
diff --git a/src/target/target.c b/src/target/target.c
index 10d0088d5..384b4ec84 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -3139,9 +3139,9 @@ COMMAND_HANDLER(handle_reg_command)
if ((CMD_ARGC == 1) || ((CMD_ARGC == 2) && !((CMD_ARGV[1][0] >= '0')
&& (CMD_ARGV[1][0] <= '9')))) {
if ((CMD_ARGC == 2) && (strcmp(CMD_ARGV[1], "force") == 0))
- reg->valid = 0;
+ reg->valid = false;
- if (reg->valid == 0) {
+ if (!reg->valid) {
int retval = reg->type->get(reg);
if (retval != ERROR_OK) {
LOG_ERROR("Could not read register '%s'", reg->name);
-----------------------------------------------------------------------
Summary of changes:
src/target/target.c | 6 +++---
.../{nxp_mcimx8m-evk.cfg => advantech_imx8qm_dmsse20.cfg} | 11 +++++------
2 files changed, 8 insertions(+), 9 deletions(-)
copy tcl/board/{nxp_mcimx8m-evk.cfg => advantech_imx8qm_dmsse20.cfg} (64%)
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From: openocd-gerrit <ope...@us...> - 2023-11-11 18:02:57
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 59c4d35fa43d39b195510c9d1d415435912dcaed (commit)
from b388f4805c3ce6e0b7ce7e5995c9305529db8e46 (commit)
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- Log -----------------------------------------------------------------
commit 59c4d35fa43d39b195510c9d1d415435912dcaed
Author: Antonio Borneo <bor...@gm...>
Date: Fri Oct 27 17:42:45 2023 +0200
jep106: update to revision JEP106BH September 2023
The original documents from Jedec since JEP106BG, do not report
the entry for "21 NXP (Philips)", replaced by "c".
It's clearly a typo.
Keep the line from JEP106BF.01 for "NXP (Philips)".
Change-Id: I273c8c5ecf48336ce5189b484a7236273ba90184
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7954
Tested-by: jenkins
diff --git a/src/helper/jep106.inc b/src/helper/jep106.inc
index 6c8196765..bcf354c91 100644
--- a/src/helper/jep106.inc
+++ b/src/helper/jep106.inc
@@ -2,15 +2,15 @@
/*
* The manufacturer's standard identification code list appears in JEP106.
- * Copyright (c) 2022 JEDEC. All rights reserved.
+ * Copyright (c) 2023 JEDEC. All rights reserved.
*
* JEP106 is regularly updated. For the current manufacturer's standard
* identification code list, please visit the JEDEC website at www.jedec.org .
*/
-/* This file is aligned to revision JEP106BG May 2023. */
+/* This file is aligned to revision JEP106BH September 2023. */
-/* "NXP (Philips)" is reported below, while missing in JEP106BG */
+/* "NXP (Philips)" is reported below, while missing since JEP106BG */
[0][0x01 - 1] = "AMD",
[0][0x02 - 1] = "AMI",
@@ -1375,7 +1375,7 @@
[10][0x65 - 1] = "Esperanto Technologies",
[10][0x66 - 1] = "JinSheng Electronic (Shenzhen) Co Ltd",
[10][0x67 - 1] = "Shenzhen Shi Bolunshuai Technology",
-[10][0x68 - 1] = "Shanghai Rei Zuan Information Tech",
+[10][0x68 - 1] = "Shanghai Rui Zuan Information Tech",
[10][0x69 - 1] = "Fraunhofer IIS",
[10][0x6a - 1] = "Kandou Bus SA",
[10][0x6b - 1] = "Acer",
@@ -1841,4 +1841,51 @@
[14][0x3f - 1] = "Shenzhen Dingsheng Technology Co Ltd",
[14][0x40 - 1] = "EVAS Intelligence Co Ltd",
[14][0x41 - 1] = "Kaibright Electronic Technologies",
+[14][0x42 - 1] = "Fraunhofer IMS",
+[14][0x43 - 1] = "Shenzhen Xinrui Renhe Technology",
+[14][0x44 - 1] = "Beijing Vcore Technology Co Ltd",
+[14][0x45 - 1] = "Silicon Innovation Technologies Co Ltd",
+[14][0x46 - 1] = "Shenzhen Zhengxinda Technology Co Ltd",
+[14][0x47 - 1] = "Shenzhen Remai Electronics Co Lttd",
+[14][0x48 - 1] = "Shenzhen Xinruiyan Electronics Co Ltd",
+[14][0x49 - 1] = "CEC Huada Electronic Design Co Ltd",
+[14][0x4a - 1] = "Westberry Technology Inc",
+[14][0x4b - 1] = "Tongxin Microelectronics Co Ltd",
+[14][0x4c - 1] = "UNIM Semiconductor (Shang Hai) Co Ltd",
+[14][0x4d - 1] = "Shenzhen Qiaowenxingyu Industrial Co Ltd",
+[14][0x4e - 1] = "ICC",
+[14][0x4f - 1] = "Enfabrica Corporation",
+[14][0x50 - 1] = "Niobium Microsystems Inc",
+[14][0x51 - 1] = "Xiaoli AI Electronics (Shenzhen) Co Ltd",
+[14][0x52 - 1] = "Silicon Mitus",
+[14][0x53 - 1] = "Ajiatek Inc",
+[14][0x54 - 1] = "HomeNet",
+[14][0x55 - 1] = "Shenzhen Shubang Technology Co Ltd",
+[14][0x56 - 1] = "Exacta Technologies Ltd",
+[14][0x57 - 1] = "Synology",
+[14][0x58 - 1] = "Trium Elektronik Bilgi Islem San Ve Dis",
+[14][0x59 - 1] = "Shenzhen Hippstor Technology Co Ltd",
+[14][0x5a - 1] = "SSCT",
+[14][0x5b - 1] = "Sichuan Heentai Semiconductor Co Ltd",
+[14][0x5c - 1] = "Zhejiang University",
+[14][0x5d - 1] = "www.shingroup.cn",
+[14][0x5e - 1] = "Suzhou Nano Mchip Technology Company",
+[14][0x5f - 1] = "Feature Integration Technology Inc",
+[14][0x60 - 1] = "d-Matrix",
+[14][0x61 - 1] = "Golden Memory",
+[14][0x62 - 1] = "Qingdao Thunderobot Technology Co Ltd",
+[14][0x63 - 1] = "Shenzhen Tianxiang Chuangxin Technology",
+[14][0x64 - 1] = "HYPHY USA",
+[14][0x65 - 1] = "Valkyrie",
+[14][0x66 - 1] = "Suzhou Hesetc Electronic Technology Co",
+[14][0x67 - 1] = "Hainan Zhongyuncun Technology Co Ltd",
+[14][0x68 - 1] = "Shenzhen Yousheng Bona Technology Co",
+[14][0x69 - 1] = "Shenzhen Xinle Chuang Technology Co",
+[14][0x6a - 1] = "DEEPX",
+[14][0x6b - 1] = "iStarChip CA LLC",
+[14][0x6c - 1] = "Shenzhen Vinreada Technology Co Ltd",
+[14][0x6d - 1] = "Novatek Microelectronics Corp",
+[14][0x6e - 1] = "Chemgdu EG Technology Co Ltd",
+[14][0x6f - 1] = "AGI Technology",
+[14][0x70 - 1] = "Syntiant",
/* EOF */
-----------------------------------------------------------------------
Summary of changes:
src/helper/jep106.inc | 55 +++++++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 51 insertions(+), 4 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2023-10-27 11:41:59
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via b388f4805c3ce6e0b7ce7e5995c9305529db8e46 (commit)
from e5d26f1546fbe3cba310a3828c75be9ab786be29 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit b388f4805c3ce6e0b7ce7e5995c9305529db8e46
Author: Kirill Radkin <kir...@sy...>
Date: Mon Sep 25 13:10:20 2023 +0300
OpenOCD memory leak in `hwthread_update_threads()`
Update `os_free()` from `rtos/rtos.c:96` to fix memory leaks
Change-Id: Id7b4c775291b735a0b4423151c2930afce6bf0bd
Signed-off-by: Kirill Radkin <kir...@sy...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7934
Reviewed-by: Tim Newsome <ti...@si...>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c
index 136d93bf6..0df1182c0 100644
--- a/src/rtos/rtos.c
+++ b/src/rtos/rtos.c
@@ -78,6 +78,7 @@ static void os_free(struct target *target)
return;
free(target->rtos->symbols);
+ rtos_free_threadlist(target->rtos);
free(target->rtos);
target->rtos = NULL;
}
-----------------------------------------------------------------------
Summary of changes:
src/rtos/rtos.c | 1 +
1 file changed, 1 insertion(+)
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From: openocd-gerrit <ope...@us...> - 2023-10-27 11:41:41
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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commit e5d26f1546fbe3cba310a3828c75be9ab786be29
Author: Tomas Vanek <va...@fb...>
Date: Mon Oct 2 16:40:23 2023 +0200
flash/nor/spi: add guide to select proper erase cmd
Extend comments in flash_devices array.
Signed-off-by: Tomas Vanek <va...@fb...>
Change-Id: I7ab85a2d37803b6bc9fc7a2a91ae2effb6ec288d
Reviewed-on: https://review.openocd.org/c/openocd/+/7925
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyp...@gm...>
diff --git a/src/flash/nor/spi.c b/src/flash/nor/spi.c
index ace274f3d..bf654f9f6 100644
--- a/src/flash/nor/spi.c
+++ b/src/flash/nor/spi.c
@@ -22,10 +22,22 @@
/* Shared table of known SPI flash devices for SPI-based flash drivers. Taken
* from device datasheets and Linux SPI flash drivers. */
const struct flash_device flash_devices[] = {
- /* name, read_cmd, qread_cmd, pprog_cmd, erase_cmd, chip_erase_cmd, device_id,
- * pagesize, sectorsize, size_in_bytes
- * note: device id is usually 3 bytes long, however the unused highest byte counts
- * continuation codes for manufacturer id as per JEP106xx */
+ /* Note: device_id is usually 3 bytes long, however the unused highest byte counts
+ * continuation codes for manufacturer id as per JEP106xx.
+ *
+ * All sizes (page, sector/block and flash) are in bytes.
+ *
+ * Guide to select a proper erase command (if both sector and block erase cmds are available):
+ * Use 4kbit sector erase cmd and set erase size to the size of sector for small devices
+ * (4Mbit and less, size <= 0x80000) to prevent too raw erase granularity.
+ * Use 64kbit block erase cmd and set erase size to the size of block for bigger devices
+ * (8Mbit and more, size >= 0x100000) to keep erase speed reasonable.
+ * If the device implements also 32kbit block erase, use it for 8Mbit, size == 0x100000.
+ */
+ /* name read qread page erase chip device_id page erase flash
+ * _cmd _cmd _prog _cmd* _erase size size* size
+ * _cmd _cmd
+ */
FLASH_ID("st m25pe10", 0x03, 0x00, 0x02, 0xd8, 0x00, 0x00118020, 0x100, 0x10000, 0x20000),
FLASH_ID("st m25pe20", 0x03, 0x00, 0x02, 0xd8, 0x00, 0x00128020, 0x100, 0x10000, 0x40000),
FLASH_ID("st m25pe40", 0x03, 0x00, 0x02, 0xd8, 0x00, 0x00138020, 0x100, 0x10000, 0x80000),
@@ -174,6 +186,11 @@ const struct flash_device flash_devices[] = {
FLASH_ID("zetta zd25q16", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x001560ba, 0x100, 0x10000, 0x200000),
/* FRAM, no erase commands, no write page or sectors */
+
+ /* name read qread page device_id total
+ * _cmd _cmd _prog size
+ * _cmd
+ */
FRAM_ID("fu mb85rs16n", 0x03, 0, 0x02, 0x00010104, 0x800),
FRAM_ID("fu mb85rs32v", 0x03, 0, 0x02, 0x00010204, 0x1000), /* exists ? */
FRAM_ID("fu mb85rs64v", 0x03, 0, 0x02, 0x00020304, 0x2000),
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/spi.c | 25 +++++++++++++++++++++----
1 file changed, 21 insertions(+), 4 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2023-10-25 01:35:47
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commit a080d9795ae5fd4d8ca83fd996667212fc77013c
Author: EasyDevKits <in...@ea...>
Date: Sat Oct 14 21:48:56 2023 +0200
jtag/drivers: Extension of jtag_libusb_open
In jtag_libusb_open I've added a parameter for delivering the device
description for which this function should search and adjusted all
callers of this function. A new driver for WCH CH347 JTAG chips
will use this new parameter.
See also: https://review.openocd.org/c/openocd/+/7937
Change-Id: I85e1d7b1f7912ba5e223f0f26323ff3b7600e17d
Signed-off-by: EasyDevKits <in...@ea...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7938
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/angie.c b/src/jtag/drivers/angie.c
index 9cc086599..b6bde5b3b 100644
--- a/src/jtag/drivers/angie.c
+++ b/src/jtag/drivers/angie.c
@@ -257,7 +257,7 @@ static int angie_usb_open(struct angie *device)
const uint16_t vids[] = {ANGIE_VID, ANGIE_VID, ANGIE_VID, ANGIE_VID, 0};
const uint16_t pids[] = {ANGIE_PID, ANGIE_PID_2, ANGIE_PID_3, ANGIE_PID_4, 0};
- int ret = jtag_libusb_open(vids, pids, &usb_device_handle, NULL);
+ int ret = jtag_libusb_open(vids, pids, NULL, &usb_device_handle, NULL);
if (ret != ERROR_OK)
return ret;
diff --git a/src/jtag/drivers/arm-jtag-ew.c b/src/jtag/drivers/arm-jtag-ew.c
index a37272084..eada67f45 100644
--- a/src/jtag/drivers/arm-jtag-ew.c
+++ b/src/jtag/drivers/arm-jtag-ew.c
@@ -677,7 +677,7 @@ static struct armjtagew *armjtagew_usb_open(void)
const uint16_t pids[] = { USB_PID, 0 };
struct libusb_device_handle *dev;
- if (jtag_libusb_open(vids, pids, &dev, NULL) != ERROR_OK)
+ if (jtag_libusb_open(vids, pids, NULL, &dev, NULL) != ERROR_OK)
return NULL;
struct armjtagew *result = malloc(sizeof(struct armjtagew));
diff --git a/src/jtag/drivers/esp_usb_jtag.c b/src/jtag/drivers/esp_usb_jtag.c
index 2ed0f58fd..950405954 100644
--- a/src/jtag/drivers/esp_usb_jtag.c
+++ b/src/jtag/drivers/esp_usb_jtag.c
@@ -487,7 +487,7 @@ static int esp_usb_jtag_init(void)
bitq_interface->in_rdy = esp_usb_jtag_in_rdy;
bitq_interface->in = esp_usb_jtag_in;
- int r = jtag_libusb_open(vids, pids, &priv->usb_device, NULL);
+ int r = jtag_libusb_open(vids, pids, NULL, &priv->usb_device, NULL);
if (r != ERROR_OK) {
LOG_ERROR("esp_usb_jtag: could not find or open device!");
goto out;
diff --git a/src/jtag/drivers/ft232r.c b/src/jtag/drivers/ft232r.c
index c2ec78ad8..2d9d9ef34 100644
--- a/src/jtag/drivers/ft232r.c
+++ b/src/jtag/drivers/ft232r.c
@@ -246,7 +246,7 @@ static int ft232r_init(void)
{
uint16_t avids[] = {ft232r_vid, 0};
uint16_t apids[] = {ft232r_pid, 0};
- if (jtag_libusb_open(avids, apids, &adapter, NULL)) {
+ if (jtag_libusb_open(avids, apids, NULL, &adapter, NULL)) {
const char *ft232r_serial_desc = adapter_get_required_serial();
LOG_ERROR("ft232r not found: vid=%04x, pid=%04x, serial=%s\n",
ft232r_vid, ft232r_pid, (!ft232r_serial_desc) ? "[any]" : ft232r_serial_desc);
diff --git a/src/jtag/drivers/kitprog.c b/src/jtag/drivers/kitprog.c
index b953218b8..e126a9c22 100644
--- a/src/jtag/drivers/kitprog.c
+++ b/src/jtag/drivers/kitprog.c
@@ -275,7 +275,7 @@ static int kitprog_usb_open(void)
const uint16_t vids[] = { VID, 0 };
const uint16_t pids[] = { PID, 0 };
- if (jtag_libusb_open(vids, pids, &kitprog_handle->usb_handle, NULL) != ERROR_OK) {
+ if (jtag_libusb_open(vids, pids, NULL, &kitprog_handle->usb_handle, NULL) != ERROR_OK) {
LOG_ERROR("Failed to open or find the device");
return ERROR_FAIL;
}
diff --git a/src/jtag/drivers/libusb_helper.c b/src/jtag/drivers/libusb_helper.c
index c77fe78c2..9d788ee39 100644
--- a/src/jtag/drivers/libusb_helper.c
+++ b/src/jtag/drivers/libusb_helper.c
@@ -146,12 +146,13 @@ static bool jtag_libusb_match_serial(struct libusb_device_handle *device,
}
int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
- struct libusb_device_handle **out,
+ const char *product, struct libusb_device_handle **out,
adapter_get_alternate_serial_fn adapter_get_alternate_serial)
{
int cnt, idx, err_code;
int retval = ERROR_FAIL;
bool serial_mismatch = false;
+ bool product_mismatch = false;
struct libusb_device_handle *libusb_handle = NULL;
const char *serial = adapter_get_required_serial();
@@ -188,10 +189,18 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
continue;
}
+ if (product &&
+ !string_descriptor_equal(libusb_handle, dev_desc.iProduct, product)) {
+ product_mismatch = true;
+ libusb_close(libusb_handle);
+ continue;
+ }
+
/* Success. */
*out = libusb_handle;
retval = ERROR_OK;
serial_mismatch = false;
+ product_mismatch = false;
break;
}
if (cnt >= 0)
@@ -200,6 +209,9 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
if (serial_mismatch)
LOG_INFO("No device matches the serial string");
+ if (product_mismatch)
+ LOG_INFO("No device matches the product string");
+
if (retval != ERROR_OK)
libusb_exit(jtag_libusb_context);
diff --git a/src/jtag/drivers/libusb_helper.h b/src/jtag/drivers/libusb_helper.h
index 75f133519..09309b40c 100644
--- a/src/jtag/drivers/libusb_helper.h
+++ b/src/jtag/drivers/libusb_helper.h
@@ -33,7 +33,7 @@ typedef char * (*adapter_get_alternate_serial_fn)(struct libusb_device_handle *d
bool jtag_libusb_match_ids(struct libusb_device_descriptor *dev_desc,
const uint16_t vids[], const uint16_t pids[]);
int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
- struct libusb_device_handle **out,
+ const char *product, struct libusb_device_handle **out,
adapter_get_alternate_serial_fn adapter_get_alternate_serial);
void jtag_libusb_close(struct libusb_device_handle *dev);
int jtag_libusb_control_transfer(struct libusb_device_handle *dev,
diff --git a/src/jtag/drivers/opendous.c b/src/jtag/drivers/opendous.c
index 2e1d64814..4d9fd998a 100644
--- a/src/jtag/drivers/opendous.c
+++ b/src/jtag/drivers/opendous.c
@@ -695,7 +695,7 @@ struct opendous_jtag *opendous_usb_open(void)
struct opendous_jtag *result;
struct libusb_device_handle *devh;
- if (jtag_libusb_open(opendous_probe->VID, opendous_probe->PID, &devh, NULL) != ERROR_OK)
+ if (jtag_libusb_open(opendous_probe->VID, opendous_probe->PID, NULL, &devh, NULL) != ERROR_OK)
return NULL;
jtag_libusb_set_configuration(devh, 0);
diff --git a/src/jtag/drivers/openjtag.c b/src/jtag/drivers/openjtag.c
index fe3a8ff7f..dca27b0a6 100644
--- a/src/jtag/drivers/openjtag.c
+++ b/src/jtag/drivers/openjtag.c
@@ -438,7 +438,7 @@ static int openjtag_init_cy7c65215(void)
int ret;
usbh = NULL;
- ret = jtag_libusb_open(cy7c65215_vids, cy7c65215_pids, &usbh, NULL);
+ ret = jtag_libusb_open(cy7c65215_vids, cy7c65215_pids, NULL, &usbh, NULL);
if (ret != ERROR_OK) {
LOG_ERROR("unable to open cy7c65215 device");
goto err;
diff --git a/src/jtag/drivers/osbdm.c b/src/jtag/drivers/osbdm.c
index d8fe7135e..84f2fd66a 100644
--- a/src/jtag/drivers/osbdm.c
+++ b/src/jtag/drivers/osbdm.c
@@ -363,7 +363,7 @@ static int osbdm_flush(struct osbdm *osbdm, struct queue *queue)
static int osbdm_open(struct osbdm *osbdm)
{
(void)memset(osbdm, 0, sizeof(*osbdm));
- if (jtag_libusb_open(osbdm_vid, osbdm_pid, &osbdm->devh, NULL) != ERROR_OK)
+ if (jtag_libusb_open(osbdm_vid, osbdm_pid, NULL, &osbdm->devh, NULL) != ERROR_OK)
return ERROR_FAIL;
if (libusb_claim_interface(osbdm->devh, 0) != ERROR_OK)
diff --git a/src/jtag/drivers/rlink.c b/src/jtag/drivers/rlink.c
index 65f7494bd..a28e76e01 100644
--- a/src/jtag/drivers/rlink.c
+++ b/src/jtag/drivers/rlink.c
@@ -1448,7 +1448,7 @@ static int rlink_init(void)
const uint16_t vids[] = { USB_IDVENDOR, 0 };
const uint16_t pids[] = { USB_IDPRODUCT, 0 };
- if (jtag_libusb_open(vids, pids, &hdev, NULL) != ERROR_OK)
+ if (jtag_libusb_open(vids, pids, NULL, &hdev, NULL) != ERROR_OK)
return ERROR_FAIL;
struct libusb_device_descriptor descriptor;
diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c
index c5326a206..b14fbf1f3 100644
--- a/src/jtag/drivers/stlink_usb.c
+++ b/src/jtag/drivers/stlink_usb.c
@@ -3406,7 +3406,7 @@ static int stlink_usb_usb_open(void *handle, struct hl_interface_param_s *param)
in order to become operational.
*/
do {
- if (jtag_libusb_open(param->vid, param->pid,
+ if (jtag_libusb_open(param->vid, param->pid, NULL,
&h->usb_backend_priv.fd, stlink_usb_get_alternate_serial) != ERROR_OK) {
LOG_ERROR("open failed");
return ERROR_FAIL;
diff --git a/src/jtag/drivers/ti_icdi_usb.c b/src/jtag/drivers/ti_icdi_usb.c
index 3e3621873..4260e2d39 100644
--- a/src/jtag/drivers/ti_icdi_usb.c
+++ b/src/jtag/drivers/ti_icdi_usb.c
@@ -675,7 +675,7 @@ static int icdi_usb_open(struct hl_interface_param_s *param, void **fd)
/* TI (Stellaris) ICDI provides its serial number in the USB descriptor;
no need to provide a callback here. */
- jtag_libusb_open(param->vid, param->pid, &h->usb_dev, NULL);
+ jtag_libusb_open(param->vid, param->pid, NULL, &h->usb_dev, NULL);
if (!h->usb_dev) {
LOG_ERROR("open failed");
diff --git a/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c b/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c
index f5e0026a7..de0d2d847 100644
--- a/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c
+++ b/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c
@@ -202,7 +202,7 @@ static int ublast2_libusb_init(struct ublast_lowlevel *low)
bool renumeration = false;
int ret;
- if (jtag_libusb_open(vids, pids, &temp, NULL) == ERROR_OK) {
+ if (jtag_libusb_open(vids, pids, NULL, &temp, NULL) == ERROR_OK) {
LOG_INFO("Altera USB-Blaster II (uninitialized) found");
LOG_INFO("Loading firmware...");
ret = load_usb_blaster_firmware(temp, low);
@@ -216,13 +216,13 @@ static int ublast2_libusb_init(struct ublast_lowlevel *low)
const uint16_t pids_renum[] = { low->ublast_pid, 0 };
if (renumeration == false) {
- if (jtag_libusb_open(vids_renum, pids_renum, &low->libusb_dev, NULL) != ERROR_OK) {
+ if (jtag_libusb_open(vids_renum, pids_renum, NULL, &low->libusb_dev, NULL) != ERROR_OK) {
LOG_ERROR("Altera USB-Blaster II not found");
return ERROR_FAIL;
}
} else {
int retry = 10;
- while (jtag_libusb_open(vids_renum, pids_renum, &low->libusb_dev, NULL) != ERROR_OK && retry--) {
+ while (jtag_libusb_open(vids_renum, pids_renum, NULL, &low->libusb_dev, NULL) != ERROR_OK && retry--) {
usleep(1000000);
LOG_INFO("Waiting for reenumerate...");
}
diff --git a/src/jtag/drivers/usbprog.c b/src/jtag/drivers/usbprog.c
index 5d41656b4..aa655ed7e 100644
--- a/src/jtag/drivers/usbprog.c
+++ b/src/jtag/drivers/usbprog.c
@@ -341,7 +341,7 @@ struct usbprog_jtag *usbprog_jtag_open(void)
const uint16_t pids[] = { PID, 0 };
struct libusb_device_handle *dev;
- if (jtag_libusb_open(vids, pids, &dev, NULL) != ERROR_OK)
+ if (jtag_libusb_open(vids, pids, NULL, &dev, NULL) != ERROR_OK)
return NULL;
struct usbprog_jtag *tmp = malloc(sizeof(struct usbprog_jtag));
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/angie.c | 2 +-
src/jtag/drivers/arm-jtag-ew.c | 2 +-
src/jtag/drivers/esp_usb_jtag.c | 2 +-
src/jtag/drivers/ft232r.c | 2 +-
src/jtag/drivers/kitprog.c | 2 +-
src/jtag/drivers/libusb_helper.c | 14 +++++++++++++-
src/jtag/drivers/libusb_helper.h | 2 +-
src/jtag/drivers/opendous.c | 2 +-
src/jtag/drivers/openjtag.c | 2 +-
src/jtag/drivers/osbdm.c | 2 +-
src/jtag/drivers/rlink.c | 2 +-
src/jtag/drivers/stlink_usb.c | 2 +-
src/jtag/drivers/ti_icdi_usb.c | 2 +-
src/jtag/drivers/usb_blaster/ublast2_access_libusb.c | 6 +++---
src/jtag/drivers/usbprog.c | 2 +-
15 files changed, 29 insertions(+), 17 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: openocd-gerrit <ope...@us...> - 2023-10-25 01:35:03
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 1d555d21d9036fec1604c0f5e41a1202038b87ae (commit)
from e887cfb9e8e8e42513b38e09960849becc5d42e3 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 1d555d21d9036fec1604c0f5e41a1202038b87ae
Author: EasyDevKits <in...@ea...>
Date: Sat Oct 14 18:14:13 2023 +0200
tools/scripts: iManufacturer added to camelcase.txt
The iManufacturer is also a member of structure libusb_device_descriptor.
No need to output a check message by checkpatch.sh
Change-Id: Ibbb2eb9cde3482c8d4d6ea784f51a973eb36f8c5
Signed-off-by: EasyDevKits <in...@ea...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7936
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/tools/scripts/camelcase.txt b/tools/scripts/camelcase.txt
index 2caa81caa..b78790200 100644
--- a/tools/scripts/camelcase.txt
+++ b/tools/scripts/camelcase.txt
@@ -77,6 +77,7 @@ bNumInterfaces
idProduct
idVendor
iInterface
+iManufacturer
iProduct
iSerialNumber
wMaxPacketSize
-----------------------------------------------------------------------
Summary of changes:
tools/scripts/camelcase.txt | 1 +
1 file changed, 1 insertion(+)
hooks/post-receive
--
Main OpenOCD repository
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|
From: openocd-gerrit <ope...@us...> - 2023-10-25 01:34:28
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via e887cfb9e8e8e42513b38e09960849becc5d42e3 (commit)
from 18c64af13500342da5dc304cb3f2024078815bd4 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit e887cfb9e8e8e42513b38e09960849becc5d42e3
Author: Walter Ji <wal...@os...>
Date: Mon Oct 9 11:42:44 2023 +0800
target/mips32: check read regs result in save context
Add result check for mips32_pracc_read_regs in mips32_save_context.
Change-Id: Ie796d2b05a9feb11e246c2d0771b52cad4fb70db
Signed-off-by: Walter Ji <wal...@os...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7932
Reviewed-by: Oleksij Rempel <li...@re...>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 18160b237..99688b008 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -306,7 +306,11 @@ int mips32_save_context(struct target *target)
struct mips32_common *mips32 = target_to_mips32(target);
/* read core registers */
- mips32_pracc_read_regs(mips32);
+ int retval = mips32_pracc_read_regs(mips32);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Could not read core registers from target");
+ return retval;
+ }
for (i = 0; i < MIPS32_NUM_REGS; i++) {
if (!mips32->core_cache->reg_list[i].valid)
-----------------------------------------------------------------------
Summary of changes:
src/target/mips32.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
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From: openocd-gerrit <ope...@us...> - 2023-10-25 01:33:43
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 18c64af13500342da5dc304cb3f2024078815bd4 (commit)
from c7d1f0ddabb301e00738686671b939bb92a06ed9 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 18c64af13500342da5dc304cb3f2024078815bd4
Author: Walter Ji <wal...@os...>
Date: Tue Sep 26 16:56:02 2023 +0800
target/mips32: rework mips core register related functions
Update mips core definitions.
Reworked mips core register structure and read/write function.
Add coprocessor0 register definitions for target configuration.
Change-Id: I59c1f4cc4020db8a78e8d79f7421b87382fa1709
Signed-off-by: Walter Ji <wal...@os...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7864
Reviewed-by: Oleksij Rempel <li...@re...>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 4e6d25118..18160b237 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -27,7 +27,7 @@ static const char *mips_isa_strings[] = {
"MIPS32", "MIPS16", "", "MICRO MIPS32",
};
-#define MIPS32_GDB_DUMMY_FP_REG 1
+#define MIPS32_GDB_FP_REG 1
/*
* GDB registers
@@ -39,7 +39,7 @@ static const struct {
enum reg_type type;
const char *group;
const char *feature;
- int flag;
+ int size;
} mips32_regs[] = {
{ 0, "r0", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
{ 1, "r1", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
@@ -73,88 +73,93 @@ static const struct {
{ 29, "r29", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
{ 30, "r30", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
{ 31, "r31", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
- { 32, "status", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 },
- { 33, "lo", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
- { 34, "hi", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
- { 35, "badvaddr", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 },
- { 36, "cause", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cp0", 0 },
- { 37, "pc", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
-
- { 38, "f0", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 39, "f1", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 40, "f2", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 41, "f3", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 42, "f4", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 43, "f5", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 44, "f6", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 45, "f7", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 46, "f8", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 47, "f9", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 48, "f10", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 49, "f11", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 50, "f12", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 51, "f13", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 52, "f14", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 53, "f15", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 54, "f16", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 55, "f17", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 56, "f18", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 57, "f19", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 58, "f20", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 59, "f21", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 60, "f22", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 61, "f23", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 62, "f24", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 63, "f25", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 64, "f26", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 65, "f27", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 66, "f28", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 67, "f29", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 68, "f30", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 69, "f31", REG_TYPE_IEEE_SINGLE, NULL,
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 70, "fcsr", REG_TYPE_INT, "float",
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
- { 71, "fir", REG_TYPE_INT, "float",
- "org.gnu.gdb.mips.fpu", MIPS32_GDB_DUMMY_FP_REG },
+ { 32, "lo", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+ { 33, "hi", REG_TYPE_INT, NULL, "org.gnu.gdb.mips.cpu", 0 },
+
+ { MIPS32_REGLIST_FP_INDEX + 0, "f0", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 1, "f1", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 2, "f2", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 3, "f3", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 4, "f4", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 5, "f5", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 6, "f6", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 7, "f7", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 8, "f8", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 9, "f9", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 10, "f10", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 11, "f11", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 12, "f12", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 13, "f13", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 14, "f14", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 15, "f15", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 16, "f16", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 17, "f17", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 18, "f18", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 19, "f19", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 20, "f20", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 21, "f21", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 22, "f22", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 23, "f23", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 24, "f24", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 25, "f25", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 26, "f26", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 27, "f27", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 28, "f28", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 29, "f29", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 30, "f30", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+ { MIPS32_REGLIST_FP_INDEX + 31, "f31", REG_TYPE_IEEE_DOUBLE, NULL,
+ "org.gnu.gdb.mips.fpu", MIPS32_GDB_FP_REG },
+
+ { MIPS32_REGLIST_FPC_INDEX + 0, "fcsr", REG_TYPE_INT, "float",
+ "org.gnu.gdb.mips.fpu", 0 },
+ { MIPS32_REGLIST_FPC_INDEX + 1, "fir", REG_TYPE_INT, "float",
+ "org.gnu.gdb.mips.fpu", 0 },
+
+ { MIPS32_REGLIST_C0_STATUS_INDEX, "status", REG_TYPE_INT, NULL,
+ "org.gnu.gdb.mips.cp0", 0 },
+ { MIPS32_REGLIST_C0_BADVADDR_INDEX, "badvaddr", REG_TYPE_INT, NULL,
+ "org.gnu.gdb.mips.cp0", 0 },
+ { MIPS32_REGLIST_C0_CAUSE_INDEX, "cause", REG_TYPE_INT, NULL,
+ "org.gnu.gdb.mips.cp0", 0 },
+ { MIPS32_REGLIST_C0_PC_INDEX, "pc", REG_TYPE_INT, NULL,
+ "org.gnu.gdb.mips.cpu", 0 },
+ { MIPS32_REGLIST_C0_GUESTCTL1_INDEX, "guestCtl1", REG_TYPE_INT, NULL,
+ "org.gnu.gdb.mips.cp0", 0 },
};
-
#define MIPS32_NUM_REGS ARRAY_SIZE(mips32_regs)
-static uint8_t mips32_gdb_dummy_fp_value[] = {0, 0, 0, 0};
-
static int mips32_get_core_reg(struct reg *reg)
{
int retval;
@@ -174,12 +179,21 @@ static int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
{
struct mips32_core_reg *mips32_reg = reg->arch_info;
struct target *target = mips32_reg->target;
- uint32_t value = buf_get_u32(buf, 0, 32);
+ uint64_t value;
+
+ if (reg->size == 64)
+ value = buf_get_u64(buf, 0, 64);
+ else
+ value = buf_get_u32(buf, 0, 32);
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
- buf_set_u32(reg->value, 0, 32, value);
+ if (reg->size == 64)
+ buf_set_u64(reg->value, 0, 64, value);
+ else
+ buf_set_u32(reg->value, 0, 32, value);
+
reg->dirty = true;
reg->valid = true;
@@ -188,7 +202,8 @@ static int mips32_set_core_reg(struct reg *reg, uint8_t *buf)
static int mips32_read_core_reg(struct target *target, unsigned int num)
{
- uint32_t reg_value;
+ unsigned int cnum;
+ uint64_t reg_value = 0;
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
@@ -196,17 +211,40 @@ static int mips32_read_core_reg(struct target *target, unsigned int num)
if (num >= MIPS32_NUM_REGS)
return ERROR_COMMAND_SYNTAX_ERROR;
- reg_value = mips32->core_regs[num];
- buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
+ if (num >= MIPS32_REGLIST_C0_INDEX) {
+ /* CP0 */
+ cnum = num - MIPS32_REGLIST_C0_INDEX;
+ reg_value = mips32->core_regs.cp0[cnum];
+ buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
+ } else if (num >= MIPS32_REGLIST_FPC_INDEX) {
+ /* FPCR */
+ cnum = num - MIPS32_REGLIST_FPC_INDEX;
+ reg_value = mips32->core_regs.fpcr[cnum];
+ buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
+ } else if (num >= MIPS32_REGLIST_FP_INDEX) {
+ /* FPR */
+ cnum = num - MIPS32_REGLIST_FP_INDEX;
+ reg_value = mips32->core_regs.fpr[cnum];
+ buf_set_u64(mips32->core_cache->reg_list[num].value, 0, 64, reg_value);
+ } else {
+ /* GPR */
+ cnum = num - MIPS32_REGLIST_GP_INDEX;
+ reg_value = mips32->core_regs.gpr[cnum];
+ buf_set_u32(mips32->core_cache->reg_list[num].value, 0, 32, reg_value);
+ }
+
mips32->core_cache->reg_list[num].valid = true;
mips32->core_cache->reg_list[num].dirty = false;
+ LOG_DEBUG("read core reg %i value 0x%" PRIx64 "", num, reg_value);
+
return ERROR_OK;
}
static int mips32_write_core_reg(struct target *target, unsigned int num)
{
- uint32_t reg_value;
+ unsigned int cnum;
+ uint64_t reg_value;
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
@@ -214,9 +252,29 @@ static int mips32_write_core_reg(struct target *target, unsigned int num)
if (num >= MIPS32_NUM_REGS)
return ERROR_COMMAND_SYNTAX_ERROR;
- reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
- mips32->core_regs[num] = reg_value;
- LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
+ if (num >= MIPS32_REGLIST_C0_INDEX) {
+ /* CP0 */
+ cnum = num - MIPS32_REGLIST_C0_INDEX;
+ reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
+ mips32->core_regs.cp0[cnum] = (uint32_t)reg_value;
+ } else if (num >= MIPS32_REGLIST_FPC_INDEX) {
+ /* FPCR */
+ cnum = num - MIPS32_REGLIST_FPC_INDEX;
+ reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
+ mips32->core_regs.fpcr[cnum] = (uint32_t)reg_value;
+ } else if (num >= MIPS32_REGLIST_FP_INDEX) {
+ /* FPR */
+ cnum = num - MIPS32_REGLIST_FP_INDEX;
+ reg_value = buf_get_u64(mips32->core_cache->reg_list[num].value, 0, 64);
+ mips32->core_regs.fpr[cnum] = reg_value;
+ } else {
+ /* GPR */
+ cnum = num - MIPS32_REGLIST_GP_INDEX;
+ reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
+ mips32->core_regs.gpr[cnum] = (uint32_t)reg_value;
+ }
+
+ LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value);
mips32->core_cache->reg_list[num].valid = true;
mips32->core_cache->reg_list[num].dirty = false;
@@ -246,10 +304,9 @@ int mips32_save_context(struct target *target)
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
- struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
/* read core registers */
- mips32_pracc_read_regs(ejtag_info, mips32->core_regs);
+ mips32_pracc_read_regs(mips32);
for (i = 0; i < MIPS32_NUM_REGS; i++) {
if (!mips32->core_cache->reg_list[i].valid)
@@ -265,7 +322,6 @@ int mips32_restore_context(struct target *target)
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
- struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
for (i = 0; i < MIPS32_NUM_REGS; i++) {
if (mips32->core_cache->reg_list[i].dirty)
@@ -273,7 +329,7 @@ int mips32_restore_context(struct target *target)
}
/* write core regs */
- mips32_pracc_write_regs(ejtag_info, mips32->core_regs);
+ mips32_pracc_write_regs(mips32);
return ERROR_OK;
}
@@ -285,7 +341,7 @@ int mips32_arch_state(struct target *target)
LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32 "",
mips_isa_strings[mips32->isa_mode],
debug_reason_name(target),
- buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
+ buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32));
return ERROR_OK;
}
@@ -322,25 +378,19 @@ struct reg_cache *mips32_build_reg_cache(struct target *target)
arch_info[i].mips32_common = mips32;
reg_list[i].name = mips32_regs[i].name;
- reg_list[i].size = 32;
-
- if (mips32_regs[i].flag == MIPS32_GDB_DUMMY_FP_REG) {
- reg_list[i].value = mips32_gdb_dummy_fp_value;
- reg_list[i].valid = true;
- reg_list[i].arch_info = NULL;
- register_init_dummy(®_list[i]);
- } else {
- reg_list[i].value = calloc(1, 4);
- reg_list[i].valid = false;
- reg_list[i].type = &mips32_reg_type;
- reg_list[i].arch_info = &arch_info[i];
-
- reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
- if (reg_list[i].reg_data_type)
- reg_list[i].reg_data_type->type = mips32_regs[i].type;
- else
- LOG_ERROR("unable to allocate reg type list");
- }
+ reg_list[i].size = mips32_regs[i].size ? 64 : 32;
+
+ reg_list[i].value = mips32_regs[i].size ? calloc(1, 8) : calloc(1, 4);
+ reg_list[i].valid = false;
+ reg_list[i].type = &mips32_reg_type;
+ reg_list[i].arch_info = &arch_info[i];
+
+ reg_list[i].reg_data_type = calloc(1, sizeof(struct reg_data_type));
+ if (reg_list[i].reg_data_type)
+ reg_list[i].reg_data_type->type = mips32_regs[i].type;
+ else
+ LOG_ERROR("unable to allocate reg type list");
+
reg_list[i].dirty = false;
@@ -407,7 +457,7 @@ static int mips32_run_and_wait(struct target *target, target_addr_t entry_point,
return ERROR_TARGET_TIMEOUT;
}
- pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
+ pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32);
if (exit_point && (pc != exit_point)) {
LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 " ", pc);
return ERROR_TARGET_TIMEOUT;
diff --git a/src/target/mips32.h b/src/target/mips32.h
index 3d03e98c5..7bf638458 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -57,6 +57,139 @@
#define MIPS32_SCAN_DELAY_LEGACY_MODE 2000000
+/* Bit Mask indicating CP0 register supported by this core */
+#define MIPS_CP0_MK4 0x0001
+#define MIPS_CP0_MAPTIV_UC 0x0002
+#define MIPS_CP0_MAPTIV_UP 0x0004
+#define MIPS_CP0_IAPTIV 0x0008
+
+/* CP0 Status register fields */
+#define MIPS32_CP0_STATUS_FR_SHIFT 26
+#define MIPS32_CP0_STATUS_CU1_SHIFT 29
+
+/* CP1 FIR register fields */
+#define MIPS32_CP1_FIR_F64_SHIFT 22
+
+static const struct {
+ unsigned int reg;
+ unsigned int sel;
+ const char *name;
+ const unsigned int core;
+} mips32_cp0_regs[] = {
+ {0, 0, "index", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
+ {0, 1, "mvpcontrol", MIPS_CP0_IAPTIV},
+ {0, 2, "mvpconf0", MIPS_CP0_IAPTIV},
+ {0, 3, "mvpconf1", MIPS_CP0_IAPTIV},
+ {1, 0, "random", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
+ {1, 1, "vpecontrol", MIPS_CP0_IAPTIV},
+ {1, 2, "vpeconf0", MIPS_CP0_IAPTIV},
+ {1, 3, "vpeconf1", MIPS_CP0_IAPTIV},
+ {1, 4, "yqmask", MIPS_CP0_IAPTIV},
+ {1, 5, "vpeschedule", MIPS_CP0_IAPTIV},
+ {1, 6, "vpeschefback", MIPS_CP0_IAPTIV},
+ {1, 7, "vpeopt", MIPS_CP0_IAPTIV},
+ {2, 0, "entrylo0", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
+ {2, 1, "tcstatus", MIPS_CP0_IAPTIV},
+ {2, 2, "tcbind", MIPS_CP0_IAPTIV},
+ {2, 3, "tcrestart", MIPS_CP0_IAPTIV},
+ {2, 4, "tchalt", MIPS_CP0_IAPTIV},
+ {2, 5, "tccontext", MIPS_CP0_IAPTIV},
+ {2, 6, "tcschedule", MIPS_CP0_IAPTIV},
+ {2, 7, "tcschefback", MIPS_CP0_IAPTIV},
+ {3, 0, "entrylo1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
+ {3, 7, "tcopt", MIPS_CP0_IAPTIV},
+ {4, 0, "context", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
+ {4, 2, "userlocal", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {5, 0, "pagemask", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
+ {5, 1, "pagegrain", MIPS_CP0_MAPTIV_UP},
+ {5, 2, "segctl0", MIPS_CP0_IAPTIV},
+ {5, 3, "segctl1", MIPS_CP0_IAPTIV},
+ {5, 4, "segctl2", MIPS_CP0_IAPTIV},
+ {6, 0, "wired", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
+ {6, 1, "srsconf0", MIPS_CP0_IAPTIV},
+ {6, 2, "srsconf1", MIPS_CP0_IAPTIV},
+ {6, 3, "srsconf2", MIPS_CP0_IAPTIV},
+ {6, 4, "srsconf3", MIPS_CP0_IAPTIV},
+ {6, 5, "srsconf4", MIPS_CP0_IAPTIV},
+ {7, 0, "hwrena", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {8, 0, "badvaddr", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {8, 1, "badinstr", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
+ {8, 2, "badinstrp", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
+ {9, 0, "count", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {10, 0, "entryhi", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP},
+ {10, 4, "guestctl1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4},
+ {10, 5, "guestctl2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4},
+ {10, 6, "guestctl3", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4},
+ {11, 0, "compare", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {11, 4, "guestctl0ext", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4},
+ {12, 0, "status", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {12, 1, "intctl", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {12, 2, "srsctl", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {12, 3, "srsmap", MIPS_CP0_IAPTIV},
+ {12, 3, "srsmap1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
+ {12, 4, "view_ipl", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {12, 5, "srsmap2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
+ {12, 6, "guestctl0", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4},
+ {12, 7, "gtoffset", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MK4},
+ {13, 0, "cause", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {13, 5, "nestedexc", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {14, 0, "epc", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {14, 2, "nestedepc", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {15, 0, "prid", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {15, 1, "ebase", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {15, 2, "cdmmbase", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {15, 3, "cmgcrbase", MIPS_CP0_IAPTIV},
+ {16, 0, "config", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {16, 1, "config1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {16, 2, "config2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {16, 3, "config3", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {16, 4, "config4", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {16, 5, "config5", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {16, 7, "config7", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {17, 0, "lladdr", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {18, 0, "watchlo0", MIPS_CP0_IAPTIV},
+ {18, 1, "watchlo1", MIPS_CP0_IAPTIV},
+ {18, 2, "watchlo2", MIPS_CP0_IAPTIV},
+ {18, 3, "watchlo3", MIPS_CP0_IAPTIV},
+ {19, 0, "watchhi0", MIPS_CP0_IAPTIV},
+ {19, 1, "watchhi1", MIPS_CP0_IAPTIV},
+ {19, 2, "watchhi2", MIPS_CP0_IAPTIV},
+ {19, 3, "watchhi3", MIPS_CP0_IAPTIV},
+ {23, 0, "debug", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {23, 1, "tracecontrol", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {23, 2, "tracecontrol2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {23, 3, "usertracedata1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {23, 4, "tracebpc", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {23, 4, "traceibpc", MIPS_CP0_IAPTIV},
+ {23, 5, "tracedbpc", MIPS_CP0_IAPTIV},
+ {24, 0, "depc", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {24, 2, "tracecontrol3", MIPS_CP0_IAPTIV},
+ {24, 3, "usertracedata2", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {25, 0, "perfctl0", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {25, 1, "perfcnt0", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {25, 2, "perfctl1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {25, 3, "perfcnt1", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {26, 0, "errctl", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {27, 0, "cacheerr", MIPS_CP0_IAPTIV},
+ {28, 0, "itaglo", MIPS_CP0_IAPTIV},
+ {28, 0, "taglo", MIPS_CP0_IAPTIV},
+ {28, 1, "idatalo", MIPS_CP0_IAPTIV},
+ {28, 1, "datalo", MIPS_CP0_IAPTIV},
+ {28, 2, "dtaglo", MIPS_CP0_IAPTIV},
+ {28, 3, "ddatalo", MIPS_CP0_IAPTIV},
+ {28, 4, "l23taglo", MIPS_CP0_IAPTIV},
+ {28, 5, "l23datalo", MIPS_CP0_IAPTIV},
+ {29, 1, "idatahi", MIPS_CP0_IAPTIV},
+ {29, 2, "dtaghi", MIPS_CP0_IAPTIV},
+ {29, 5, "l23datahi", MIPS_CP0_IAPTIV},
+ {30, 0, "errorepc", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {31, 0, "desave", MIPS_CP0_IAPTIV | MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP | MIPS_CP0_MK4},
+ {31, 2, "kscratch1", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
+ {31, 3, "kscratch2", MIPS_CP0_MAPTIV_UC | MIPS_CP0_MAPTIV_UP},
+};
+
+#define MIPS32NUMCP0REGS ((int)ARRAY_SIZE(mips32_cp0_regs))
+
/* Insert extra NOPs after the DRET instruction on exit from debug. */
#define EJTAG_QUIRK_PAD_DRET BIT(0)
@@ -67,6 +200,30 @@ enum {
MIPS32NUMCOREREGS
};
+/* offsets into mips32 core register cache */
+
+#define MIPS32_REG_GP_COUNT 34
+#define MIPS32_REG_FP_COUNT 32
+#define MIPS32_REG_FPC_COUNT 2
+#define MIPS32_REG_C0_COUNT 5
+
+#define MIPS32_REGLIST_GP_INDEX 0
+#define MIPS32_REGLIST_FP_INDEX (MIPS32_REGLIST_GP_INDEX + MIPS32_REG_GP_COUNT)
+#define MIPS32_REGLIST_FPC_INDEX (MIPS32_REGLIST_FP_INDEX + MIPS32_REG_FP_COUNT)
+#define MIPS32_REGLIST_C0_INDEX (MIPS32_REGLIST_FPC_INDEX + MIPS32_REG_FPC_COUNT)
+
+#define MIPS32_REGLIST_C0_STATUS_INDEX (MIPS32_REGLIST_C0_INDEX + 0)
+#define MIPS32_REGLIST_C0_BADVADDR_INDEX (MIPS32_REGLIST_C0_INDEX + 1)
+#define MIPS32_REGLIST_C0_CAUSE_INDEX (MIPS32_REGLIST_C0_INDEX + 2)
+#define MIPS32_REGLIST_C0_PC_INDEX (MIPS32_REGLIST_C0_INDEX + 3)
+#define MIPS32_REGLIST_C0_GUESTCTL1_INDEX (MIPS32_REGLIST_C0_INDEX + 4)
+
+#define MIPS32_REG_C0_STATUS_INDEX 0
+#define MIPS32_REG_C0_BADVADDR_INDEX 1
+#define MIPS32_REG_C0_CAUSE_INDEX 2
+#define MIPS32_REG_C0_PC_INDEX 3
+#define MIPS32_REG_C0_GUESTCTL1_INDEX 4
+
enum mips32_isa_mode {
MIPS32_ISA_MIPS32 = 0,
MIPS32_ISA_MIPS16E = 1,
@@ -86,13 +243,22 @@ struct mips32_comparator {
uint32_t reg_address;
};
+struct mips32_core_regs {
+ uint32_t gpr[MIPS32_REG_GP_COUNT];
+ uint64_t fpr[MIPS32_REG_FP_COUNT];
+ uint32_t fpcr[MIPS32_REG_FPC_COUNT];
+ uint32_t cp0[MIPS32_REG_C0_COUNT];
+};
+
struct mips32_common {
unsigned int common_magic;
void *arch_info;
struct reg_cache *core_cache;
struct mips_ejtag ejtag_info;
- uint32_t core_regs[MIPS32NUMCOREREGS];
+
+ struct mips32_core_regs core_regs;
+
enum mips32_isa_mode isa_mode;
enum mips32_isa_imp isa_imp;
diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c
index c4704b5a5..9f0d87cd9 100644
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@@ -823,9 +823,13 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int siz
return retval;
}
-int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs)
+int mips32_pracc_write_regs(struct mips32_common *mips32)
{
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
struct pracc_queue_info ctx = {.ejtag_info = ejtag_info};
+ uint32_t *gprs = mips32->core_regs.gpr;
+ uint32_t *c0rs = mips32->core_regs.cp0;
+
pracc_queue_init(&ctx);
uint32_t cp0_write_code[] = {
@@ -837,66 +841,178 @@ int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs)
MIPS32_MTC0(ctx.isa, 1, 24, 0), /* move $1 to depc (pc) */
};
+ uint32_t cp0_write_data[] = {
+ /* lo */
+ gprs[32],
+ /* hi */
+ gprs[33],
+ /* status */
+ c0rs[0],
+ /* badvaddr */
+ c0rs[1],
+ /* cause */
+ c0rs[2],
+ /* depc (pc) */
+ c0rs[3],
+ };
+
+ for (size_t i = 0; i < ARRAY_SIZE(cp0_write_code); i++) {
+ /* load CP0 value in $1 */
+ pracc_add_li32(&ctx, 1, cp0_write_data[i], 0);
+ /* write value from $1 to CP0 register */
+ pracc_add(&ctx, 0, cp0_write_code[i]);
+ }
+
/* load registers 2 to 31 with li32, optimize */
for (int i = 2; i < 32; i++)
- pracc_add_li32(&ctx, i, regs[i], 1);
+ pracc_add_li32(&ctx, i, gprs[i], 1);
- for (int i = 0; i != 6; i++) {
- pracc_add_li32(&ctx, 1, regs[i + 32], 0); /* load CPO value in $1 */
- pracc_add(&ctx, 0, cp0_write_code[i]); /* write value from $1 to CPO register */
- }
- pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0)); /* load $15 in DeSave */
- pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 1, UPPER16((regs[1])))); /* load upper half word in $1 */
- pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
- pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 1, 1, LOWER16((regs[1])))); /* load lower half word in $1 */
+ /* load $15 in DeSave */
+ pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0));
+ /* load upper half word in $1 */
+ pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 1, UPPER16((gprs[1]))));
+ /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa)));
+ /* load lower half word in $1 */
+ pracc_add(&ctx, 0, MIPS32_ORI(ctx.isa, 1, 1, LOWER16((gprs[1]))));
ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL, 1);
- ejtag_info->reg8 = regs[8];
- ejtag_info->reg9 = regs[9];
+ ejtag_info->reg8 = gprs[8];
+ ejtag_info->reg9 = gprs[9];
pracc_queue_free(&ctx);
return ctx.retval;
}
-int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs)
+/* Saves content in `$1` to `DeSave(cp0.31.0)` and loads `MIPS32_PRACC_BASE_ADDR` into `$1` */
+static void mips32_pracc_store_regs_set_base_addr(struct pracc_queue_info *ctx)
{
- struct pracc_queue_info ctx = {.ejtag_info = ejtag_info};
- pracc_queue_init(&ctx);
+ /* move $1 to COP0 DeSave */
+ pracc_add(ctx, 0, MIPS32_MTC0(ctx->isa, 1, 31, 0));
+ /* $1 = MIP32_PRACC_BASE_ADDR */
+ pracc_add(ctx, 0, MIPS32_LUI(ctx->isa, 1, PRACC_UPPER_BASE_ADDR));
+}
- uint32_t cp0_read_code[] = {
- MIPS32_MFC0(ctx.isa, 8, 12, 0), /* move status to $8 */
- MIPS32_MFLO(ctx.isa, 8), /* move lo to $8 */
- MIPS32_MFHI(ctx.isa, 8), /* move hi to $8 */
- MIPS32_MFC0(ctx.isa, 8, 8, 0), /* move badvaddr to $8 */
- MIPS32_MFC0(ctx.isa, 8, 13, 0), /* move cause to $8 */
- MIPS32_MFC0(ctx.isa, 8, 24, 0), /* move depc (pc) to $8 */
+/* This function assumes the address for saving is stored in `$1`.
+ * And that action is performed in `mips32_pracc_set_save_base_addr`.
+ */
+static void mips32_pracc_store_regs_gpr(struct pracc_queue_info *ctx, unsigned int offset_gpr)
+{
+ for (int i = 2; i != 32; i++)
+ pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + offset_gpr + (i * 4),
+ MIPS32_SW(ctx->isa, i, PRACC_OUT_OFFSET + offset_gpr + (i * 4), 1));
+}
+
+static void mips32_pracc_store_regs_lohi(struct pracc_queue_info *ctx)
+{
+ uint32_t lohi_read_code[] = {
+ MIPS32_MFLO(ctx->isa, 8), /* move lo to $8 */
+ MIPS32_MFHI(ctx->isa, 8), /* move hi to $8 */
};
- pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 1, 31, 0)); /* move $1 to COP0 DeSave */
- pracc_add(&ctx, 0, MIPS32_LUI(ctx.isa, 1, PRACC_UPPER_BASE_ADDR)); /* $1 = MIP32_PRACC_BASE_ADDR */
+ /* store lo & hi */
+ for (int i = 0; i < 2; i++) {
+ /* load COP0 needed registers to $8 */
+ pracc_add(ctx, 0, lohi_read_code[i]);
+ /* store $8 at PARAM OUT */
+ pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + (i + 32) * 4,
+ MIPS32_SW(ctx->isa, 8, PRACC_OUT_OFFSET + (i + 32) * 4, 1));
+ }
+}
- for (int i = 2; i != 32; i++) /* store GPR's 2 to 31 */
- pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + (i * 4),
- MIPS32_SW(ctx.isa, i, PRACC_OUT_OFFSET + (i * 4), 1));
+/* Saves CP0 registers [status, badvaddr, cause, depc] */
+static void mips32_pracc_store_regs_cp0_context(struct pracc_queue_info *ctx, unsigned int offset_cp0)
+{
+ uint32_t cp0_read_code[] = {
+ MIPS32_MFC0(ctx->isa, 8, 12, 0), /* move status to $8 */
+ MIPS32_MFC0(ctx->isa, 8, 8, 0), /* move badvaddr to $8 */
+ MIPS32_MFC0(ctx->isa, 8, 13, 0), /* move cause to $8 */
+ MIPS32_MFC0(ctx->isa, 8, 24, 0), /* move depc (pc) to $8 */
+ };
- for (int i = 0; i != 6; i++) {
- pracc_add(&ctx, 0, cp0_read_code[i]); /* load COP0 needed registers to $8 */
- pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + (i + 32) * 4, /* store $8 at PARAM OUT */
- MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + (i + 32) * 4, 1));
+ /* store cp0 */
+ for (size_t i = 0; i < ARRAY_SIZE(cp0_read_code); i++) {
+ size_t offset = offset_cp0 + (i * 4);
+
+ /* load COP0 needed registers to $8 */
+ pracc_add(ctx, 0, cp0_read_code[i]);
+ /* store $8 at PARAM OUT */
+ pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + offset,
+ MIPS32_SW(ctx->isa, 8, PRACC_OUT_OFFSET + offset, 1));
}
- pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 8, 31, 0)); /* move DeSave to $8, reg1 value */
- pracc_add(&ctx, MIPS32_PRACC_PARAM_OUT + 4, /* store reg1 value from $8 to param out */
- MIPS32_SW(ctx.isa, 8, PRACC_OUT_OFFSET + 4, 1));
+}
- pracc_add(&ctx, 0, MIPS32_MFC0(ctx.isa, 1, 31, 0)); /* move COP0 DeSave to $1, restore reg1 */
- pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa))); /* jump to start */
- pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0)); /* load $15 in DeSave */
+/* Loads original content of $1 into $8,
+ * then store it to the batch data access address.
+ * Finally it restores $1 from DeSave.
+ */
+static void mips32_pracc_store_regs_restore(struct pracc_queue_info *ctx)
+{
+ /* move DeSave to $8, reg1 value */
+ pracc_add(ctx, 0, MIPS32_MFC0(ctx->isa, 8, 31, 0));
+ /* store reg1 value from $8 to param out */
+ pracc_add(ctx, MIPS32_PRACC_PARAM_OUT + 4,
+ MIPS32_SW(ctx->isa, 8, PRACC_OUT_OFFSET + 4, 1));
+
+ /* move COP0 DeSave to $1, restore reg1 */
+ pracc_add(ctx, 0, MIPS32_MFC0(ctx->isa, 1, 31, 0));
+}
+
+/* This function performs following actions:
+ * Saves `$1` to `DeSave`,
+ * then load `PRACC_UPPER_BASE_ADDR` for saving the register data structure into `$1`,
+ * Saves `$2` ~ `$31` to `PRACC_UPPER_BASE_ADDR + offset_gpr`
+ * Saves HI and LO,
+ * Saves necessary cp0 registers.
+*/
+static void mips32_pracc_store_regs(struct pracc_queue_info *ctx,
+ unsigned int offset_gpr, unsigned int offset_cp0)
+{
+ mips32_pracc_store_regs_set_base_addr(ctx);
+ mips32_pracc_store_regs_gpr(ctx, offset_gpr);
+ mips32_pracc_store_regs_lohi(ctx);
+ mips32_pracc_store_regs_cp0_context(ctx, offset_cp0);
+ mips32_pracc_store_regs_restore(ctx);
+}
+
+int mips32_pracc_read_regs(struct mips32_common *mips32)
+{
+ struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+ struct pracc_queue_info ctx = {.ejtag_info = ejtag_info};
+ struct mips32_core_regs *core_regs = &mips32->core_regs;
+ unsigned int offset_gpr = ((uint8_t *)&core_regs->gpr[0]) - (uint8_t *)core_regs;
+ unsigned int offset_cp0 = ((uint8_t *)&core_regs->cp0[0]) - (uint8_t *)core_regs;
+
+ /*
+ * This procedure has to be in 2 distinctive steps, because we can
+ * only know whether FP is enabled after reading CP0.
+ *
+ * Step 1: Read everything except CP1 stuff
+ * Step 2: Read CP1 stuff if FP is implemented
+ */
+
+ pracc_queue_init(&ctx);
- ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, regs, 1);
+ mips32_pracc_store_regs(&ctx, offset_gpr, offset_cp0);
+
+ /* jump to start */
+ pracc_add(&ctx, 0, MIPS32_B(ctx.isa, NEG16((ctx.code_count + 1) << ctx.isa)));
+ /* load $15 in DeSave */
+ pracc_add(&ctx, 0, MIPS32_MTC0(ctx.isa, 15, 31, 0));
+
+ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, (uint32_t *)&mips32->core_regs, 1);
- ejtag_info->reg8 = regs[8]; /* reg8 is saved but not restored, next called function should restore it */
- ejtag_info->reg9 = regs[9];
pracc_queue_free(&ctx);
+
+ /* reg8 is saved but not restored, next called function should restore it */
+ ejtag_info->reg8 = mips32->core_regs.gpr[8];
+ ejtag_info->reg9 = mips32->core_regs.gpr[9];
+
+ /* we only care if FP is actually impl'd and if cp1 is enabled */
+ /* since we already read cp0 in the prev step */
+ /* now we know what's in cp0.status */
+ /* TODO: Read FPRs */
+
return ctx.retval;
}
diff --git a/src/target/mips32_pracc.h b/src/target/mips32_pracc.h
index 1b0076867..587a44691 100644
--- a/src/target/mips32_pracc.h
+++ b/src/target/mips32_pracc.h
@@ -36,6 +36,8 @@
#define PRACC_BLOCK 128 /* 1 Kbyte */
+struct mips32_common;
+
struct pa_list {
uint32_t instr;
uint32_t addr;
@@ -64,8 +66,8 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info,
int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_area *source,
int write_t, uint32_t addr, int count, uint32_t *buf);
-int mips32_pracc_read_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
-int mips32_pracc_write_regs(struct mips_ejtag *ejtag_info, uint32_t *regs);
+int mips32_pracc_read_regs(struct mips32_common *mips32);
+int mips32_pracc_write_regs(struct mips32_common *mips32);
/**
* \b mips32_cp0_read
diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index eb80742d6..852444a51 100644
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -123,11 +123,12 @@
/* Debug Control Register DCR */
#define EJTAG_DCR 0xFF300000
-#define EJTAG_DCR_ENM (1 << 29)
-#define EJTAG_DCR_DB (1 << 17)
-#define EJTAG_DCR_IB (1 << 16)
-#define EJTAG_DCR_INTE (1 << 4)
-#define EJTAG_DCR_MP (1 << 2)
+#define EJTAG_DCR_ENM BIT(29)
+#define EJTAG_DCR_FDC BIT(18)
+#define EJTAG_DCR_DB BIT(17)
+#define EJTAG_DCR_IB BIT(16)
+#define EJTAG_DCR_INTE BIT(4)
+#define EJTAG_DCR_MP BIT(2)
/* breakpoint support */
/* EJTAG_V20_* was tested on Broadcom BCM7401
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 46d241cb3..0a06bb160 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -108,11 +108,11 @@ static int mips_m4k_debug_entry(struct target *target)
mips32->isa_mode = MIPS32_ISA_MIPS32;
/* other than mips32 only and isa bit set ? */
- if (mips32->isa_imp && buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1))
+ if (mips32->isa_imp && buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 1))
mips32->isa_mode = mips32->isa_imp == 2 ? MIPS32_ISA_MIPS16E : MIPS32_ISA_MMIPS32;
LOG_DEBUG("entered debug state at PC 0x%" PRIx32 ", target->state: %s",
- buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32),
+ buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32),
target_state_name(target));
return ERROR_OK;
@@ -443,18 +443,18 @@ static int mips_m4k_internal_restore(struct target *target, int current,
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current) {
mips_m4k_isa_filter(mips32->isa_imp, &address);
- buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
- mips32->core_cache->reg_list[MIPS32_PC].dirty = true;
- mips32->core_cache->reg_list[MIPS32_PC].valid = true;
+ buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32, address);
+ mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = true;
+ mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].valid = true;
}
if ((mips32->isa_imp > 1) && debug_execution) /* if more than one isa supported */
- buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 1, mips32->isa_mode);
+ buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 1, mips32->isa_mode);
if (!current)
resume_pc = address;
else
- resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32);
+ resume_pc = buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32);
mips32_restore_context(target);
@@ -537,15 +537,15 @@ static int mips_m4k_step(struct target *target, int current,
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current) {
mips_m4k_isa_filter(mips32->isa_imp, &address);
- buf_set_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32, address);
- mips32->core_cache->reg_list[MIPS32_PC].dirty = true;
- mips32->core_cache->reg_list[MIPS32_PC].valid = true;
+ buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32, address);
+ mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].dirty = true;
+ mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].valid = true;
}
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints) {
breakpoint = breakpoint_find(target,
- buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
+ buf_get_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32));
if (breakpoint)
mips_m4k_unset_breakpoint(target, breakpoint);
}
-----------------------------------------------------------------------
Summary of changes:
src/target/mips32.c | 278 +++++++++++++++++++++++++++-------------------
src/target/mips32.h | 168 +++++++++++++++++++++++++++-
src/target/mips32_pracc.c | 196 +++++++++++++++++++++++++-------
src/target/mips32_pracc.h | 6 +-
src/target/mips_ejtag.h | 11 +-
src/target/mips_m4k.c | 22 ++--
6 files changed, 508 insertions(+), 173 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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From: openocd-gerrit <ope...@us...> - 2023-10-14 12:07:12
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via c7d1f0ddabb301e00738686671b939bb92a06ed9 (commit)
from 14b1b35e4247091f1e90311f9b61805ae1f6f34d (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit c7d1f0ddabb301e00738686671b939bb92a06ed9
Author: Parshintsev Anatoly <ana...@sy...>
Date: Sun Jul 30 15:35:45 2023 +0300
target: check if target is not examined on reg command
Change-Id: I46093c85374986a36d10eaac38b98bd5e05835ca
Signed-off-by: Parshintsev Anatoly <ana...@sy...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7841
Reviewed-by: Jan Matyas <jan...@co...>
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
Reviewed-by: Marek Vrbka <mar...@co...>
diff --git a/src/target/target.c b/src/target/target.c
index dfa86fdb3..10d0088d5 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -3052,6 +3052,10 @@ COMMAND_HANDLER(handle_reg_command)
LOG_DEBUG("-");
struct target *target = get_current_target(CMD_CTX);
+ if (!target_was_examined(target)) {
+ LOG_ERROR("Target not examined yet");
+ return ERROR_TARGET_NOT_EXAMINED;
+ }
struct reg *reg = NULL;
/* list all available registers for the current target */
-----------------------------------------------------------------------
Summary of changes:
src/target/target.c | 4 ++++
1 file changed, 4 insertions(+)
hooks/post-receive
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From: openocd-gerrit <ope...@us...> - 2023-10-14 12:04:40
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 14b1b35e4247091f1e90311f9b61805ae1f6f34d (commit)
via 7822260ed4e434740e715e4c759db0c6fefb87e9 (commit)
from eba5d211937d1ebcb3669810ff63ad1083600b67 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 14b1b35e4247091f1e90311f9b61805ae1f6f34d
Author: Tim Newsome <ti...@si...>
Date: Wed Aug 16 12:47:57 2023 -0700
server/gdb_server: Log gdb index in debug messages.
This makes it easier to look at log files where multiple gdb instances
are connected.
Change-Id: Ic5aca52b32ee03ac35ffbed9a2fc552abb0a1cba
Signed-off-by: Tim Newsome <ti...@si...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7895
Reviewed-by: Jan Matyas <jan...@co...>
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 497f62c42..d1bcfb540 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -95,6 +95,8 @@ struct gdb_connection {
char *thread_list;
/* flag to mask the output from gdb_log_callback() */
enum gdb_output_flag output_flag;
+ /* Unique index for this GDB connection. */
+ unsigned int unique_index;
};
#if 0
@@ -351,6 +353,7 @@ static void gdb_log_incoming_packet(struct connection *connection, char *packet)
return;
struct target *target = get_target_from_connection(connection);
+ struct gdb_connection *gdb_connection = connection->priv;
/* Avoid dumping non-printable characters to the terminal */
const unsigned packet_len = strlen(packet);
@@ -365,14 +368,15 @@ static void gdb_log_incoming_packet(struct connection *connection, char *packet)
if (packet_prefix_printable) {
const unsigned int prefix_len = colon - packet + 1; /* + 1 to include the ':' */
const unsigned int payload_len = packet_len - prefix_len;
- LOG_TARGET_DEBUG(target, "received packet: %.*s<binary-data-%u-bytes>", prefix_len,
- packet, payload_len);
+ LOG_TARGET_DEBUG(target, "{%d} received packet: %.*s<binary-data-%u-bytes>",
+ gdb_connection->unique_index, prefix_len, packet, payload_len);
} else {
- LOG_TARGET_DEBUG(target, "received packet: <binary-data-%u-bytes>", packet_len);
+ LOG_TARGET_DEBUG(target, "{%d} received packet: <binary-data-%u-bytes>",
+ gdb_connection->unique_index, packet_len);
}
} else {
/* All chars printable, dump the packet as is */
- LOG_TARGET_DEBUG(target, "received packet: %s", packet);
+ LOG_TARGET_DEBUG(target, "{%d} received packet: %s", gdb_connection->unique_index, packet);
}
}
@@ -383,13 +387,14 @@ static void gdb_log_outgoing_packet(struct connection *connection, char *packet_
return;
struct target *target = get_target_from_connection(connection);
+ struct gdb_connection *gdb_connection = connection->priv;
if (find_nonprint_char(packet_buf, packet_len))
- LOG_TARGET_DEBUG(target, "sending packet: $<binary-data-%u-bytes>#%2.2x",
- packet_len, checksum);
+ LOG_TARGET_DEBUG(target, "{%d} sending packet: $<binary-data-%u-bytes>#%2.2x",
+ gdb_connection->unique_index, packet_len, checksum);
else
- LOG_TARGET_DEBUG(target, "sending packet: $%.*s#%2.2x", packet_len, packet_buf,
- checksum);
+ LOG_TARGET_DEBUG(target, "{%d} sending packet: $%.*s#%2.2x",
+ gdb_connection->unique_index, packet_len, packet_buf, checksum);
}
static int gdb_put_packet_inner(struct connection *connection,
@@ -971,6 +976,7 @@ static int gdb_new_connection(struct connection *connection)
struct target *target;
int retval;
int initial_ack;
+ static unsigned int next_unique_id = 1;
target = get_target_from_connection(connection);
connection->priv = gdb_connection;
@@ -993,6 +999,7 @@ static int gdb_new_connection(struct connection *connection)
gdb_connection->target_desc.tdesc_length = 0;
gdb_connection->thread_list = NULL;
gdb_connection->output_flag = GDB_OUTPUT_NO;
+ gdb_connection->unique_index = next_unique_id++;
/* send ACK to GDB for debug request */
gdb_write(connection, "+", 1);
@@ -1051,20 +1058,19 @@ static int gdb_new_connection(struct connection *connection)
}
}
- gdb_actual_connections++;
log_printf_lf(all_targets->next ? LOG_LVL_INFO : LOG_LVL_DEBUG,
__FILE__, __LINE__, __func__,
"New GDB Connection: %d, Target %s, state: %s",
- gdb_actual_connections,
+ gdb_connection->unique_index,
target_name(target),
target_state_name(target));
if (!target_was_examined(target)) {
LOG_ERROR("Target %s not examined yet, refuse gdb connection %d!",
- target_name(target), gdb_actual_connections);
- gdb_actual_connections--;
+ target_name(target), gdb_connection->unique_index);
return ERROR_TARGET_NOT_EXAMINED;
}
+ gdb_actual_connections++;
if (target->state != TARGET_HALTED)
LOG_WARNING("GDB connection %d on target %s not halted",
@@ -1095,7 +1101,8 @@ static int gdb_connection_closed(struct connection *connection)
log_remove_callback(gdb_log_callback, connection);
gdb_actual_connections--;
- LOG_DEBUG("GDB Close, Target: %s, state: %s, gdb_actual_connections=%d",
+ LOG_DEBUG("{%d} GDB Close, Target: %s, state: %s, gdb_actual_connections=%d",
+ gdb_connection->unique_index,
target_name(target),
target_state_name(target),
gdb_actual_connections);
commit 7822260ed4e434740e715e4c759db0c6fefb87e9
Author: Marek Vrbka <mar...@co...>
Date: Mon Sep 25 10:00:42 2023 +0200
target: Change the watchpoint type print from number to letter
Previously, when listing the watchpoints, OpenOCD printed
numbers 0, 1 and 2 representing READ, WRITE and ACCESS type
watchpoints.
This patch changes it to 'r', 'w' and 'a'. This increases the
clarity as what type the watchpoint actually is.
Change-Id: I9eac72dfd0bb2a9596a5b0c080a3f584556ed599
Signed-off-by: Marek Vrbka <mar...@co...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7909
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Jan Matyas <jan...@co...>
diff --git a/src/target/target.c b/src/target/target.c
index bed8a2cbc..dfa86fdb3 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -4069,13 +4069,14 @@ COMMAND_HANDLER(handle_wp_command)
struct watchpoint *watchpoint = target->watchpoints;
while (watchpoint) {
+ char wp_type = (watchpoint->rw == WPT_READ ? 'r' : (watchpoint->rw == WPT_WRITE ? 'w' : 'a'));
command_print(CMD, "address: " TARGET_ADDR_FMT
", len: 0x%8.8" PRIx32
- ", r/w/a: %i, value: 0x%8.8" PRIx64
+ ", r/w/a: %c, value: 0x%8.8" PRIx64
", mask: 0x%8.8" PRIx64,
watchpoint->address,
watchpoint->length,
- (int)watchpoint->rw,
+ wp_type,
watchpoint->value,
watchpoint->mask);
watchpoint = watchpoint->next;
-----------------------------------------------------------------------
Summary of changes:
src/server/gdb_server.c | 33 ++++++++++++++++++++-------------
src/target/target.c | 5 +++--
2 files changed, 23 insertions(+), 15 deletions(-)
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