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|
From: oharboe at B. <oh...@ma...> - 2009-08-18 12:27:25
|
Author: oharboe
Date: 2009-08-18 12:27:24 +0200 (Tue, 18 Aug 2009)
New Revision: 2589
Modified:
trunk/tcl/target/lm3s1968.cfg
trunk/tcl/target/lm3s3748.cfg
trunk/tcl/target/lm3s6965.cfg
trunk/tcl/target/lm3s811.cfg
trunk/tcl/target/lm3s9b9x.cfg
Log:
David Brownell <da...@pa...> Cleanup the Stellaris target configs:
- remove endianness options; these chips hard-wire "little"
- $_TARGETNAME updates:
* don't pass $_TARGETNAME where a TAP label is required
* flash config uses $_TARGETNAME (it might not be target #0)
* simplify one $_TARGETNAME construction
- update work area setup:
* remove VM spec; these chips have no VM!
* fix some wrong sizes (0x4000 == 16K, not 4K)
* simplify: take defaults
- comment fixups
Modified: trunk/tcl/target/lm3s1968.cfg
===================================================================
--- trunk/tcl/target/lm3s1968.cfg 2009-08-18 10:25:28 UTC (rev 2588)
+++ trunk/tcl/target/lm3s1968.cfg 2009-08-18 10:27:24 UTC (rev 2589)
@@ -6,13 +6,6 @@
set _CHIPNAME lm3s1968
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a little endian
- set _ENDIAN little
-}
-
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
@@ -26,10 +19,10 @@
# this stops the debug registers from being cleared
# this will be fixed in later revisions of silicon
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
+target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3s
-# 4k working area at base of ram
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0
+# 8k working area at base of ram, not backed up
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
#flash configuration
-flash bank stellaris 0 0 0 0 0
+flash bank stellaris 0 0 0 0 $_TARGETNAME
Modified: trunk/tcl/target/lm3s3748.cfg
===================================================================
--- trunk/tcl/target/lm3s3748.cfg 2009-08-18 10:25:28 UTC (rev 2588)
+++ trunk/tcl/target/lm3s3748.cfg 2009-08-18 10:27:24 UTC (rev 2589)
@@ -6,13 +6,6 @@
set _CHIPNAME lm3s3748
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a little endian
- set _ENDIAN little
-}
-
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
@@ -26,11 +19,10 @@
# parts (third generation, includes LM3S3748). It keeps the debug registers
# from being cleared, by using software reset not SRST; NOP on newer revs.
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN \
- -chain-position $_TARGETNAME -variant lm3s
+target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3s
# 8k working area at base of ram, not backed up
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
# flash configuration -- one bank of 128K
-flash bank stellaris 0 0 0 0 0
+flash bank stellaris 0 0 0 0 $_TARGETNAME
Modified: trunk/tcl/target/lm3s6965.cfg
===================================================================
--- trunk/tcl/target/lm3s6965.cfg 2009-08-18 10:25:28 UTC (rev 2588)
+++ trunk/tcl/target/lm3s6965.cfg 2009-08-18 10:27:24 UTC (rev 2589)
@@ -1,23 +1,14 @@
-# script for luminary lm3s6965
+# TI/Luminary Stellaris lm3s6965
-
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME lm3s6965
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a little endian
- set _ENDIAN little
-}
-
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
- # force an error till we get a good number
set _CPUTAPID 0x3ba00477
}
@@ -36,11 +27,11 @@
# the luminary variant causes a software reset rather than asserting SRST
# this stops the debug registers from being cleared
# this will be fixed in later revisions of silicon
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3s
-# 4k working area at base of ram
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0
+# 8k working area at base of ram, not backed up
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
#flash configuration
-flash bank stellaris 0 0 0 0 0
+flash bank stellaris 0 0 0 0 $_TARGETNAME
Modified: trunk/tcl/target/lm3s811.cfg
===================================================================
--- trunk/tcl/target/lm3s811.cfg 2009-08-18 10:25:28 UTC (rev 2588)
+++ trunk/tcl/target/lm3s811.cfg 2009-08-18 10:27:24 UTC (rev 2589)
@@ -6,13 +6,6 @@
set _CHIPNAME lm3s811
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a little endian
- set _ENDIAN little
-}
-
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
@@ -26,10 +19,10 @@
# this stops the debug registers from being cleared
# this will be fixed in later revisions of silicon
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
+target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3s
-# 8k working area at base of ram
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x2000 -work-area-backup 0
+# 8k working area at base of ram, not backed up
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x2000
#flash configuration
-flash bank stellaris 0 0 0 0 0
+flash bank stellaris 0 0 0 0 $_TARGETNAME
Modified: trunk/tcl/target/lm3s9b9x.cfg
===================================================================
--- trunk/tcl/target/lm3s9b9x.cfg 2009-08-18 10:25:28 UTC (rev 2588)
+++ trunk/tcl/target/lm3s9b9x.cfg 2009-08-18 10:27:24 UTC (rev 2589)
@@ -11,17 +11,10 @@
set _CHIPNAME lm3s9b9x
}
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # this defaults to a little endian
- set _ENDIAN little
-}
-
if { [info exists CPUTAPID ] } {
set _CPUTAPID $CPUTAPID
} else {
- # forth generation Tempest device
+ # Fourth generation "Tempest" device
set _CPUTAPID 0x4ba00477
}
@@ -30,10 +23,10 @@
#Cortex-M3 with Luminary lm3s variant
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s
+target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu -variant lm3s
-# 16k working area at base of ram
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0
+# 16k working area at base of ram, not backed up
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 0x4000
#flash configuration
-flash bank stellaris 0 0 0 0 0
+flash bank stellaris 0 0 0 0 $_TARGETNAME
|
|
From: oharboe at B. <oh...@ma...> - 2009-08-18 12:25:31
|
Author: oharboe
Date: 2009-08-18 12:25:28 +0200 (Tue, 18 Aug 2009)
New Revision: 2588
Modified:
trunk/doc/openocd.texi
trunk/src/target/cortex_m3.c
trunk/src/target/cortex_m3.h
Log:
David Brownell <da...@pa...> Add "cortex_m3 vector_catch" command and docs. One minor
issue with this is that the core debug support uses this
mechanism, then trashes its state over reset. Users can
Work around that (for now) by re-assigning the desired
config after reset.
Also fixes "target halted due to target-not-halted" goof.
When we can't describe the reason using OpenOCD's limited
vocabulary, say "reason undefined" instead of saying it's
not halted.
Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi 2009-08-18 10:22:44 UTC (rev 2587)
+++ trunk/doc/openocd.texi 2009-08-18 10:25:28 UTC (rev 2588)
@@ -737,7 +737,9 @@
early boot code, which performs some of the same actions
that the @code{reset-init} event handler does.
Likewise, the @command{arm9tdmi vector_catch} command (or
-its @command{xscale vector_catch} sibling) can be a timesaver
+@cindex vector_catch
+its siblings @command{xscale vector_catch}
+and @command{cortex_m3 vector_catch}) can be a timesaver
during some debug sessions, but don't make everyone use that either.
Keep those kinds of debugging aids in your user config file,
along with messaging and tracing setup.
@@ -4738,6 +4740,7 @@
@anchor{arm9tdmi vector_catch}
@deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
+@cindex vector_catch
Vector Catch hardware provides a sort of dedicated breakpoint
for hardware events such as reset, interrupt, and abort.
You can use this to conserve normal breakpoint resources,
@@ -4927,6 +4930,7 @@
@anchor{xscale vector_catch}
@deffn Command {xscale vector_catch} [mask]
+@cindex vector_catch
Display a bitmask showing the hardware vectors to catch.
If the optional parameter is provided, first set the bitmask to that value.
@end deffn
@@ -5016,6 +5020,33 @@
Control masking (disabling) interrupts during target step/resume.
@end deffn
+@deffn Command {cortex_m3 vector_catch} [@option{all}|@option{none}|list]
+@cindex vector_catch
+Vector Catch hardware provides dedicated breakpoints
+for certain hardware events.
+
+Parameters request interception of
+@option{all} of these hardware event vectors,
+@option{none} of them,
+or one or more of the following:
+@option{hard_err} for a HardFault exception;
+@option{mm_err} for a MemManage exception;
+@option{bus_err} for a BusFault exception;
+@option{irq_err},
+@option{state_err},
+@option{chk_err}, or
+@option{nocp_err} for various UsageFault exceptions; or
+@option{reset}.
+If NVIC setup code does not enable them,
+MemManage, BusFault, and UsageFault exceptions
+are mapped to HardFault.
+UsageFault checks for
+divide-by-zero and unaligned access
+must also be explicitly enabled.
+
+This finishes by listing the current vector catch configuration.
+@end deffn
+
@anchor{Software Debug Messages and Tracing}
@section Software Debug Messages and Tracing
@cindex Linux-ARM DCC support
Modified: trunk/src/target/cortex_m3.c
===================================================================
--- trunk/src/target/cortex_m3.c 2009-08-18 10:22:44 UTC (rev 2587)
+++ trunk/src/target/cortex_m3.c 2009-08-18 10:25:28 UTC (rev 2588)
@@ -37,6 +37,9 @@
#include "arm_disassembler.h"
+#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
+
+
/* cli handling */
int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
int handle_cortex_m3_mask_interrupts_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
@@ -174,7 +177,7 @@
/* Read Debug Fault Status Register */
mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
- /* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */
+ /* Clear Debug Fault Status */
mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
@@ -307,8 +310,6 @@
if ((target->debug_reason != DBG_REASON_DBGRQ)
&& (target->debug_reason != DBG_REASON_SINGLESTEP))
{
- /* INCOMPLETE */
-
if (cortex_m3->nvic_dfsr & DFSR_BKPT)
{
target->debug_reason = DBG_REASON_BREAKPOINT;
@@ -317,6 +318,10 @@
}
else if (cortex_m3->nvic_dfsr & DFSR_DWTTRAP)
target->debug_reason = DBG_REASON_WATCHPOINT;
+ else if (cortex_m3->nvic_dfsr & DFSR_VCATCH)
+ target->debug_reason = DBG_REASON_BREAKPOINT;
+ else /* EXTERNAL, HALTED, DWTTRAP w/o BKPT */
+ target->debug_reason = DBG_REASON_UNDEFINED;
}
return ERROR_OK;
@@ -1703,6 +1708,73 @@
return ERROR_OK;
}
+static const struct {
+ char name[10];
+ unsigned mask;
+} vec_ids[] = {
+ { "hard_err", VC_HARDERR, },
+ { "int_err", VC_INTERR, },
+ { "bus_err", VC_BUSERR, },
+ { "state_err", VC_STATERR, },
+ { "chk_err", VC_CHKERR, },
+ { "nocp_err", VC_NOCPERR, },
+ { "mm_err", VC_MMERR, },
+ { "reset", VC_CORERESET, },
+};
+
+static int
+handle_cortex_m3_vector_catch_command(struct command_context_s *cmd_ctx,
+ char *cmd, char **argv, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ uint32_t demcr = 0;
+ int i;
+
+ mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+
+ if (argc > 0) {
+ unsigned catch = 0;
+
+ if (argc == 1) {
+ if (strcmp(argv[0], "all") == 0) {
+ catch = VC_HARDERR | VC_INTERR | VC_BUSERR
+ | VC_STATERR | VC_CHKERR | VC_NOCPERR
+ | VC_MMERR | VC_CORERESET;
+ goto write;
+ } else if (strcmp(argv[0], "none") == 0) {
+ goto write;
+ }
+ }
+ while (argc-- > 0) {
+ for (i = 0; i < ARRAY_SIZE(vec_ids); i++) {
+ if (strcmp(argv[argc], vec_ids[i].name) != 0)
+ continue;
+ catch |= vec_ids[i].mask;
+ break;
+ }
+ if (i == ARRAY_SIZE(vec_ids)) {
+ LOG_ERROR("No CM3 vector '%s'", argv[argc]);
+ return ERROR_INVALID_ARGUMENTS;
+ }
+ }
+write:
+ demcr &= ~0xffff;
+ demcr |= catch;
+
+ /* write, but don't assume it stuck */
+ mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
+ mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(vec_ids); i++)
+ command_print(cmd_ctx, "%9s: %s", vec_ids[i].name,
+ (demcr & vec_ids[i].mask) ? "catch" : "ignore");
+
+ return ERROR_OK;
+}
+
int cortex_m3_register_commands(struct command_context_s *cmd_ctx)
{
int retval;
@@ -1719,6 +1791,9 @@
register_command(cmd_ctx, cortex_m3_cmd, "maskisr",
handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC,
"mask cortex_m3 interrupts ['on'|'off']");
+ register_command(cmd_ctx, cortex_m3_cmd, "vector_catch",
+ handle_cortex_m3_vector_catch_command, COMMAND_EXEC,
+ "catch hardware vectors ['all'|'none'|<list>]");
return retval;
}
Modified: trunk/src/target/cortex_m3.h
===================================================================
--- trunk/src/target/cortex_m3.h 2009-08-18 10:22:44 UTC (rev 2587)
+++ trunk/src/target/cortex_m3.h 2009-08-18 10:25:28 UTC (rev 2588)
@@ -80,7 +80,12 @@
/* DCB_DEMCR bit and field definitions */
#define TRCENA (1 << 24)
#define VC_HARDERR (1 << 10)
+#define VC_INTERR (1 << 9)
#define VC_BUSERR (1 << 8)
+#define VC_STATERR (1 << 7)
+#define VC_CHKERR (1 << 6)
+#define VC_NOCPERR (1 << 5)
+#define VC_MMERR (1 << 4)
#define VC_CORERESET (1 << 0)
#define NVIC_ICTR 0xE000E004
|
|
From: oharboe at B. <oh...@ma...> - 2009-08-18 12:22:45
|
Author: oharboe
Date: 2009-08-18 12:22:44 +0200 (Tue, 18 Aug 2009)
New Revision: 2587
Modified:
trunk/src/target/arm9tdmi.c
trunk/src/target/embeddedice.c
Log:
David Brownell <da...@pa...> Clean up ARM7/ARM9 EmbeddedICE register handling ... don't use parallel
arrays (error prone) or assume all registers are 32-bits wide (they can
have fewer bits); don't use spaces in register names, so they can be
passed more easily to the "reg" command.
Minor updates for ARM9 vector_catch support: it's an 8-bit value. This
seems to help this core's vector_catch command work a bit better; but its
behavior wih the register cache is still goofy.
Modified: trunk/src/target/arm9tdmi.c
===================================================================
--- trunk/src/target/arm9tdmi.c 2009-08-18 10:20:25 UTC (rev 2586)
+++ trunk/src/target/arm9tdmi.c 2009-08-18 10:22:44 UTC (rev 2587)
@@ -995,7 +995,7 @@
embeddedice_read_reg(vector_catch);
/* get the current setting */
- vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
+ vector_catch_value = buf_get_u32(vector_catch->value, 0, 8);
if (argc > 0)
{
@@ -1028,7 +1028,9 @@
command_print(cmd_ctx, "vector '%s' not found, leaving current setting unchanged", args[i]);
/* reread current setting */
- vector_catch_value = buf_get_u32(vector_catch->value, 0, 32);
+ vector_catch_value = buf_get_u32(
+ vector_catch->value,
+ 0, 8);
break;
}
@@ -1036,7 +1038,7 @@
}
/* store new settings */
- buf_set_u32(vector_catch->value, 0, 32, vector_catch_value);
+ buf_set_u32(vector_catch->value, 0, 8, vector_catch_value);
embeddedice_store_reg(vector_catch);
}
Modified: trunk/src/target/embeddedice.c
===================================================================
--- trunk/src/target/embeddedice.c 2009-08-18 10:20:25 UTC (rev 2586)
+++ trunk/src/target/embeddedice.c 2009-08-18 10:22:44 UTC (rev 2587)
@@ -29,6 +29,7 @@
#include "embeddedice.h"
+#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0])))
#if 0
static bitfield_desc_t embeddedice_comms_ctrl_bitfield_desc[] =
@@ -40,39 +41,103 @@
};
#endif
-static int embeddedice_reg_arch_info[] =
-{
- 0x0, 0x1, 0x4, 0x5,
- 0x8, 0x9, 0xa, 0xb, 0xc, 0xd,
- 0x10, 0x11, 0x12, 0x13, 0x14, 0x15,
- 0x2
+/*
+ * From: ARM9E-S TRM, DDI 0165, table C-4 (and similar, for other cores)
+ */
+static const struct {
+ char *name;
+ unsigned short addr;
+ unsigned short width;
+} eice_regs[] = {
+ [EICE_DBG_CTRL] = {
+ .name = "debug_ctrl",
+ .addr = 0,
+ /* width is assigned based on EICE version */
+ },
+ [EICE_DBG_STAT] = {
+ .name = "debug_status",
+ .addr = 1,
+ /* width is assigned based on EICE version */
+ },
+ [EICE_COMMS_CTRL] = {
+ .name = "comms_ctrl",
+ .addr = 4,
+ .width = 6,
+ },
+ [EICE_COMMS_DATA] = {
+ .name = "comms_data",
+ .addr = 5,
+ .width = 32,
+ },
+ [EICE_W0_ADDR_VALUE] = {
+ .name = "watch_0_addr_value",
+ .addr = 8,
+ .width = 32,
+ },
+ [EICE_W0_ADDR_MASK] = {
+ .name = "watch_0_addr_mask",
+ .addr = 9,
+ .width = 32,
+ },
+ [EICE_W0_DATA_VALUE ] = {
+ .name = "watch_0_data_value",
+ .addr = 10,
+ .width = 32,
+ },
+ [EICE_W0_DATA_MASK] = {
+ .name = "watch_0_data_mask",
+ .addr = 11,
+ .width = 32,
+ },
+ [EICE_W0_CONTROL_VALUE] = {
+ .name = "watch_0_control_value",
+ .addr = 12,
+ .width = 9,
+ },
+ [EICE_W0_CONTROL_MASK] = {
+ .name = "watch_0_control_mask",
+ .addr = 13,
+ .width = 8,
+ },
+ [EICE_W1_ADDR_VALUE] = {
+ .name = "watch_1_addr_value",
+ .addr = 16,
+ .width = 32,
+ },
+ [EICE_W1_ADDR_MASK] = {
+ .name = "watch_1_addr_mask",
+ .addr = 17,
+ .width = 32,
+ },
+ [EICE_W1_DATA_VALUE] = {
+ .name = "watch_1_data_value",
+ .addr = 18,
+ .width = 32,
+ },
+ [EICE_W1_DATA_MASK] = {
+ .name = "watch_1_data_mask",
+ .addr = 19,
+ .width = 32,
+ },
+ [EICE_W1_CONTROL_VALUE] = {
+ .name = "watch_1_control_value",
+ .addr = 20,
+ .width = 9,
+ },
+ [EICE_W1_CONTROL_MASK] = {
+ .name = "watch_1_control_mask",
+ .addr = 21,
+ .width = 8,
+ },
+ /* vector_catch isn't always present */
+ [EICE_VEC_CATCH] = {
+ .name = "vector_catch",
+ .addr = 2,
+ .width = 8,
+ },
};
-static char* embeddedice_reg_list[] =
-{
- "debug_ctrl",
- "debug_status",
- "comms_ctrl",
- "comms_data",
-
- "watch 0 addr value",
- "watch 0 addr mask",
- "watch 0 data value",
- "watch 0 data mask",
- "watch 0 control value",
- "watch 0 control mask",
-
- "watch 1 addr value",
- "watch 1 addr mask",
- "watch 1 data value",
- "watch 1 data mask",
- "watch 1 control value",
- "watch 1 control mask",
-
- "vector catch"
-};
-
static int embeddedice_reg_arch_type = -1;
static int embeddedice_get_reg(reg_t *reg);
@@ -84,18 +149,18 @@
reg_t *reg_list = NULL;
embeddedice_reg_t *arch_info = NULL;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
- int num_regs;
+ int num_regs = ARRAY_SIZE(eice_regs);
int i;
int eice_version = 0;
/* register a register arch-type for EmbeddedICE registers only once */
if (embeddedice_reg_arch_type == -1)
- embeddedice_reg_arch_type = register_reg_arch_type(embeddedice_get_reg, embeddedice_set_reg_w_exec);
+ embeddedice_reg_arch_type = register_reg_arch_type(
+ embeddedice_get_reg, embeddedice_set_reg_w_exec);
- if (arm7_9->has_vector_catch)
- num_regs = 17;
- else
- num_regs = 16;
+ /* vector_catch isn't always present */
+ if (!arm7_9->has_vector_catch)
+ num_regs--;
/* the actual registers are kept in two arrays */
reg_list = calloc(num_regs, sizeof(reg_t));
@@ -110,8 +175,8 @@
/* set up registers */
for (i = 0; i < num_regs; i++)
{
- reg_list[i].name = embeddedice_reg_list[i];
- reg_list[i].size = 32;
+ reg_list[i].name = eice_regs[i].name;
+ reg_list[i].size = eice_regs[i].width;
reg_list[i].dirty = 0;
reg_list[i].valid = 0;
reg_list[i].bitfield_desc = NULL;
@@ -119,7 +184,7 @@
reg_list[i].value = calloc(1, 4);
reg_list[i].arch_info = &arch_info[i];
reg_list[i].arch_type = embeddedice_reg_arch_type;
- arch_info[i].addr = embeddedice_reg_arch_info[i];
+ arch_info[i].addr = eice_regs[i].addr;
arch_info[i].jtag_info = jtag_info;
}
@@ -137,43 +202,57 @@
}
eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
+ LOG_DEBUG("Embedded ICE version %d", eice_version);
switch (eice_version)
{
case 1:
+ /* ARM7TDMI r3, ARM7TDMI-S r3
+ *
+ * REVISIT docs say ARM7TDMI-S r4 uses version 1 but
+ * that it has 6-bit CTRL and 5-bit STAT... doc bug?
+ * ARM7TDMI r4 docs say EICE v4.
+ */
reg_list[EICE_DBG_CTRL].size = 3;
reg_list[EICE_DBG_STAT].size = 5;
break;
case 2:
+ /* ARM9TDMI */
reg_list[EICE_DBG_CTRL].size = 4;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_single_step = 1;
break;
case 3:
- LOG_ERROR("EmbeddedICE version 3 detected, EmbeddedICE handling might be broken");
+ LOG_ERROR("EmbeddedICE v%d handling might be broken",
+ eice_version);
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_single_step = 1;
arm7_9->has_monitor_mode = 1;
break;
case 4:
+ /* ARM7TDMI r4 */
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_monitor_mode = 1;
break;
case 5:
+ /* ARM9E-S rev 1 */
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_single_step = 1;
arm7_9->has_monitor_mode = 1;
break;
case 6:
+ /* ARM7EJ-S, ARM9E-S rev 2, ARM9EJ-S */
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 10;
+ /* DBG_STAT has MOE bits */
arm7_9->has_monitor_mode = 1;
break;
case 7:
- LOG_WARNING("EmbeddedICE version 7 detected, EmbeddedICE handling might be broken");
+ LOG_ERROR("EmbeddedICE v%d handling might be broken",
+ eice_version);
reg_list[EICE_DBG_CTRL].size = 6;
reg_list[EICE_DBG_STAT].size = 5;
arm7_9->has_monitor_mode = 1;
@@ -276,7 +355,7 @@
* EICE_COMMS_DATA would read the register twice
* reading the control register is safe
*/
- buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
+ buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_CTRL].addr);
jtag_add_dr_scan_check(3, fields, jtag_get_end_state());
@@ -305,7 +384,7 @@
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
- buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
+ buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
@@ -322,7 +401,8 @@
* to avoid reading additional data from the DCC data reg
*/
if (size == 1)
- buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
+ buf_set_u32(fields[1].out_value, 0, 5,
+ eice_regs[EICE_COMMS_CTRL].addr);
fields[0].in_value = (uint8_t *)data;
jtag_add_dr_scan(3, fields, jtag_get_end_state());
@@ -407,7 +487,7 @@
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
- buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_DATA]);
+ buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
@@ -462,7 +542,7 @@
fields[1].tap = jtag_info->tap;
fields[1].num_bits = 5;
fields[1].out_value = field1_out;
- buf_set_u32(fields[1].out_value, 0, 5, embeddedice_reg_arch_info[EICE_COMMS_CTRL]);
+ buf_set_u32(fields[1].out_value, 0, 5, eice_regs[EICE_COMMS_DATA].addr);
fields[1].in_value = NULL;
fields[2].tap = jtag_info->tap;
|
|
From: oharboe at B. <oh...@ma...> - 2009-08-18 12:20:26
|
Author: oharboe
Date: 2009-08-18 12:20:25 +0200 (Tue, 18 Aug 2009)
New Revision: 2586
Modified:
trunk/src/target/armv7m.c
Log:
David Brownell <da...@pa...> Several of the ARMv7M registers are 8 bits or less; don't
display them as 32 bits unless that's their true size.
(Removes some confusion.
Modified: trunk/src/target/armv7m.c
===================================================================
--- trunk/src/target/armv7m.c 2009-08-18 10:18:18 UTC (rev 2585)
+++ trunk/src/target/armv7m.c 2009-08-18 10:20:25 UTC (rev 2586)
@@ -87,35 +87,36 @@
static const struct {
unsigned id;
char *name;
+ unsigned bits;
} armv7m_regs[] = {
- { ARMV7M_R0, "r0" },
- { ARMV7M_R1, "r1" },
- { ARMV7M_R2, "r2" },
- { ARMV7M_R3, "r3" },
+ { ARMV7M_R0, "r0", 32 },
+ { ARMV7M_R1, "r1", 32 },
+ { ARMV7M_R2, "r2", 32 },
+ { ARMV7M_R3, "r3", 32 },
- { ARMV7M_R4, "r4" },
- { ARMV7M_R5, "r5" },
- { ARMV7M_R6, "r6" },
- { ARMV7M_R7, "r7" },
+ { ARMV7M_R4, "r4", 32 },
+ { ARMV7M_R5, "r5", 32 },
+ { ARMV7M_R6, "r6", 32 },
+ { ARMV7M_R7, "r7", 32 },
- { ARMV7M_R8, "r8" },
- { ARMV7M_R9, "r9" },
- { ARMV7M_R10, "r10" },
- { ARMV7M_R11, "r11" },
+ { ARMV7M_R8, "r8", 32 },
+ { ARMV7M_R9, "r9", 32 },
+ { ARMV7M_R10, "r10", 32 },
+ { ARMV7M_R11, "r11", 32 },
- { ARMV7M_R12, "r12" },
- { ARMV7M_R13, "sp" },
- { ARMV7M_R14, "lr" },
- { ARMV7M_PC, "pc" },
+ { ARMV7M_R12, "r12", 32 },
+ { ARMV7M_R13, "sp", 32 },
+ { ARMV7M_R14, "lr", 32 },
+ { ARMV7M_PC, "pc", 32 },
- { ARMV7M_xPSR, "xPSR" },
- { ARMV7M_MSP, "msp" },
- { ARMV7M_PSP, "psp" },
+ { ARMV7M_xPSR, "xPSR", 32 },
+ { ARMV7M_MSP, "msp", 32 },
+ { ARMV7M_PSP, "psp", 32 },
- { ARMV7M_PRIMASK, "primask" },
- { ARMV7M_BASEPRI, "basepri" },
- { ARMV7M_FAULTMASK, "faultmask" },
- { ARMV7M_CONTROL, "control" },
+ { ARMV7M_PRIMASK, "primask", 1 },
+ { ARMV7M_BASEPRI, "basepri", 8 },
+ { ARMV7M_FAULTMASK, "faultmask", 1 },
+ { ARMV7M_CONTROL, "control", 2 },
};
#define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs)
@@ -534,7 +535,7 @@
arch_info[i].target = target;
arch_info[i].armv7m_common = armv7m;
reg_list[i].name = armv7m_regs[i].name;
- reg_list[i].size = 32;
+ reg_list[i].size = armv7m_regs[i].bits;
reg_list[i].value = calloc(1, 4);
reg_list[i].dirty = 0;
reg_list[i].valid = 0;
|
|
From: oharboe at B. <oh...@ma...> - 2009-08-18 12:18:19
|
Author: oharboe
Date: 2009-08-18 12:18:18 +0200 (Tue, 18 Aug 2009)
New Revision: 2585
Modified:
trunk/src/flash/davinci_nand.c
Log:
Piotr Ziecik <ko...@se...> Due to errors in chipselect management in davinci_nand driver
OpenOCD was able to access only to chips attached to first EMIF
chipselect. This patch fixes chipselect management code and allows
OpenOCD to access to NAND devices attached to any EMIF CS line.
Modified: trunk/src/flash/davinci_nand.c
===================================================================
--- trunk/src/flash/davinci_nand.c 2009-08-16 12:08:35 UTC (rev 2584)
+++ trunk/src/flash/davinci_nand.c 2009-08-18 10:18:18 UTC (rev 2585)
@@ -365,7 +365,7 @@
struct davinci_nand *info = nand->controller_priv;
target_t *target = info->target;
const uint32_t fcr_addr = info->aemif + NANDFCR;
- const uint32_t ecc1_addr = info->aemif + NANDFECC + info->chipsel;
+ const uint32_t ecc1_addr = info->aemif + NANDFECC + (4 * info->chipsel);
uint32_t fcr, ecc1;
/* Write contiguous ECC bytes starting at specified offset.
@@ -676,11 +676,11 @@
|| aemif == 0x01e10000 /* dm335, dm355 */
|| aemif == 0x01d10000 /* dm365 */
) {
- if (chip < 0x0200000 || chip >= 0x0a000000) {
+ if (chip < 0x02000000 || chip >= 0x0a000000) {
LOG_ERROR("NAND address %08lx out of range?", chip);
goto fail;
}
- chipsel = (chip - 0x02000000) >> 21;
+ chipsel = (chip - 0x02000000) >> 25;
} else {
LOG_ERROR("unrecognized AEMIF controller address %08lx", aemif);
goto fail;
|
|
From: oharboe at B. <oh...@ma...> - 2009-08-16 14:08:36
|
Author: oharboe Date: 2009-08-16 14:08:35 +0200 (Sun, 16 Aug 2009) New Revision: 2584 Added: trunk/tcl/board/ek-lm3s811.cfg Modified: trunk/tcl/target/lm3s811.cfg Log: Xiaofan Chen <xia...@gm...> Split LM3S811 config file into target file and board file Added: trunk/tcl/board/ek-lm3s811.cfg =================================================================== --- trunk/tcl/board/ek-lm3s811.cfg 2009-08-16 11:58:40 UTC (rev 2583) +++ trunk/tcl/board/ek-lm3s811.cfg 2009-08-16 12:08:35 UTC (rev 2584) @@ -0,0 +1,19 @@ +# +# TI/Luminary Stellaris LM3S811 Evaluation Kits +# +# http://www.luminarymicro.com/products/stellaris_811_evaluation_kits.html + +# include the FT2232 interface config for on-board JTAG interface +source [find interface/luminary.cfg] + +# include the target config +source [find target/lm3s811.cfg] + +# jtag speed +jtag_khz 500 + +jtag_nsrst_delay 100 +jtag_ntrst_delay 100 + +#LM3S811 Evaluation Board has only srst +reset_config srst_only Property changes on: trunk/tcl/board/ek-lm3s811.cfg ___________________________________________________________________ Name: svn:eol-style + native Modified: trunk/tcl/target/lm3s811.cfg =================================================================== --- trunk/tcl/target/lm3s811.cfg 2009-08-16 11:58:40 UTC (rev 2583) +++ trunk/tcl/target/lm3s811.cfg 2009-08-16 12:08:35 UTC (rev 2584) @@ -1,4 +1,4 @@ -# Script for luminary lm3s811 +# Script for TI/Luminary Stellaris LM3S811 if { [info exists CHIPNAME] } { set _CHIPNAME $CHIPNAME @@ -16,26 +16,16 @@ if { [info exists CPUTAPID ] } { set _CPUTAPID $CPUTAPID } else { - # force an error till we get a good number set _CPUTAPID 0x3ba00477 } -# jtag speed -jtag_khz 500 - -jtag_nsrst_delay 100 -jtag_ntrst_delay 100 - -#LM3S811 Evaluation Board has only srst -reset_config srst_only - #jtag scan chain jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID # the luminary variant causes a software reset rather than asserting SRST # this stops the debug registers from being cleared # this will be fixed in later revisions of silicon -set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +set _TARGETNAME $_CHIPNAME.cpu target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s # 8k working area at base of ram |
|
From: oharboe at B. <oh...@ma...> - 2009-08-16 13:58:41
|
Author: oharboe
Date: 2009-08-16 13:58:40 +0200 (Sun, 16 Aug 2009)
New Revision: 2583
Added:
trunk/tcl/target/c100.cfg
trunk/tcl/target/telo.cfg
Log:
michal smulski <mic...@oo...> arm11 target config files
Added: trunk/tcl/target/c100.cfg
===================================================================
--- trunk/tcl/target/c100.cfg 2009-08-16 11:54:56 UTC (rev 2582)
+++ trunk/tcl/target/c100.cfg 2009-08-16 11:58:40 UTC (rev 2583)
@@ -0,0 +1,65 @@
+# c100 config
+#
+#jtag_nsrst_delay 5000
+#jtag_ntrst_delay 3000
+#reset_config none
+reset_config trst_and_srst separate
+#reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME c100
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x27b3645b
+}
+
+if { [info exists DSPTAPID ] } {
+ set _DSPTAPID $DSPTAPID
+} else {
+ set _DSPTAPID 0x27b3645b
+}
+
+jtag newtap $_CHIPNAME dsp -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_DSPTAPID
+
+
+# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
+jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# C100's ARAM 64k SRAM
+$_TARGETNAME configure -work-area-phys 0x0a000000 -work-area-size 0x10000 -work-area-backup 0
+
+
+proc power_restore {} { puts "Sensed power restore. No action." }
+proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
+
+
+# issue telnet: reset init
+# issue gdb: monitor reset init
+$_TARGETNAME configure -event reset-init {
+ # Force target into ARM state.
+# soft_reset_halt # not implemented on ARM11
+ puts "Halting C100.CPU"
+ halt
+}
+
+$_TARGETNAME configure -event reset-deassert-post {
+ # Force target into ARM state.
+# soft_reset_halt # not implemented on ARM11
+ puts "Detected SRSRT asserted on C100.CPU"
+
+}
+# Valid events: old-gdb_program_config, old-pre_resume, early-halted, halted, resumed, resume-start, resume-end, gdb-start, gdb-end, reset-start, reset-assert-pre, reset-assert-post, reset-deassert-pre, reset-deassert-post, reset-halt-pre, reset-halt-post, reset-wait-pre, reset-wait-post, reset-init, reset-end, examine-start, examine-end, debug-halted, debug-resumed, gdb-attach, gdb-detach, gdb-flash-write-start, gdb-flash-write-end, gdb-flash-erase-start, gdb-flash-erase-end, resume-start, resume-ok, or resume-end
Property changes on: trunk/tcl/target/c100.cfg
___________________________________________________________________
Name: svn:eol-style
+ native
Added: trunk/tcl/target/telo.cfg
===================================================================
--- trunk/tcl/target/telo.cfg 2009-08-16 11:54:56 UTC (rev 2582)
+++ trunk/tcl/target/telo.cfg 2009-08-16 11:58:40 UTC (rev 2583)
@@ -0,0 +1,9 @@
+source [find c100.cfg]
+
+# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
+# it's really 16MB but the upper 8mb is controller via gpio?
+flash bank cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
+
+#
+gdb_memory_map enable
+
Property changes on: trunk/tcl/target/telo.cfg
___________________________________________________________________
Name: svn:eol-style
+ native
|
|
From: oharboe at B. <oh...@ma...> - 2009-08-16 13:54:58
|
Author: oharboe Date: 2009-08-16 13:54:56 +0200 (Sun, 16 Aug 2009) New Revision: 2582 Added: trunk/tcl/board/ek-lm3s1968.cfg trunk/tcl/target/lm3s1968.cfg Log: Xiaofan Chen <xia...@gm...> Add config file for TI-Luminary LM3S1968 chip and EK-LM3S1968 board Added: trunk/tcl/board/ek-lm3s1968.cfg =================================================================== --- trunk/tcl/board/ek-lm3s1968.cfg 2009-08-16 11:52:50 UTC (rev 2581) +++ trunk/tcl/board/ek-lm3s1968.cfg 2009-08-16 11:54:56 UTC (rev 2582) @@ -0,0 +1,23 @@ +# +# TI/Luminary Stellaris LM3S1968 Evaluation Kits +# +# http://www.luminarymicro.com/products/lm3s1968_evaluation_kits.html + +# NOTE: to use J-Link instead of the on-board interface, +# you may also need to reduce jtag_khz to be about 1200. +# source [find interface/jlink.cfg] + +# include the FT2232 interface config for on-board JTAG interface +source [find interface/luminary.cfg] + +# include the target config +source [find target/lm3s1968.cfg] + +# jtag speed +jtag_khz 3000 + +jtag_nsrst_delay 100 +jtag_ntrst_delay 100 + +#LM3S1968 Evaluation Board has only srst +reset_config srst_only Property changes on: trunk/tcl/board/ek-lm3s1968.cfg ___________________________________________________________________ Name: svn:eol-style + native Added: trunk/tcl/target/lm3s1968.cfg =================================================================== --- trunk/tcl/target/lm3s1968.cfg 2009-08-16 11:52:50 UTC (rev 2581) +++ trunk/tcl/target/lm3s1968.cfg 2009-08-16 11:54:56 UTC (rev 2582) @@ -0,0 +1,35 @@ +# Script for TI/Luminary Stellaris LM3S1968 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME lm3s1968 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a little endian + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + set _CPUTAPID 0x3ba00477 +} + +#jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 1 -irmask 0xf -expected-id $_CPUTAPID + +# the luminary variant causes a software reset rather than asserting SRST +# this stops the debug registers from being cleared +# this will be fixed in later revisions of silicon +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME -variant lm3s + +# 4k working area at base of ram +$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 0x4000 -work-area-backup 0 + +#flash configuration +flash bank stellaris 0 0 0 0 0 Property changes on: trunk/tcl/target/lm3s1968.cfg ___________________________________________________________________ Name: svn:eol-style + native |
|
From: oharboe at B. <oh...@ma...> - 2009-08-16 13:52:54
|
Author: oharboe
Date: 2009-08-16 13:52:50 +0200 (Sun, 16 Aug 2009)
New Revision: 2581
Modified:
trunk/src/target/arm_disassembler.c
Log:
Ferdinand Postema <fer...@po...> cygwin 32 bit warning
Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c 2009-08-16 11:49:21 UTC (rev 2580)
+++ trunk/src/target/arm_disassembler.c 2009-08-16 11:52:50 UTC (rev 2581)
@@ -3522,7 +3522,7 @@
case 3:
if (rt == 0xf) {
immed = opcode & 0xfff;
- sprintf(cp, "PLI\t[r%d, #%d]\t; %#3.3" PRIx32,
+ sprintf(cp, "PLI\t[r%d, #%d]\t; %#3.3x",
rn, immed, immed);
return ERROR_OK;
}
|
|
From: oharboe at B. <oh...@ma...> - 2009-08-16 13:49:23
|
Author: oharboe Date: 2009-08-16 13:49:21 +0200 (Sun, 16 Aug 2009) New Revision: 2580 Modified: trunk/src/target/arm11_dbgtap.c Log: added note w/reference to discussion on whether or not arm11 code is broken or not. Modified: trunk/src/target/arm11_dbgtap.c =================================================================== --- trunk/src/target/arm11_dbgtap.c 2009-08-13 13:54:53 UTC (rev 2579) +++ trunk/src/target/arm11_dbgtap.c 2009-08-16 11:49:21 UTC (rev 2580) @@ -479,6 +479,10 @@ * * To disable this code, try "memwrite burst false" * + * FIX!!! should we use multiple TAP_IDLE here or not??? + * + * https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html + * https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html */ tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] = { |
|
From: ntfreak at B. <nt...@ma...> - 2009-08-13 15:54:56
|
Author: ntfreak
Date: 2009-08-13 15:54:53 +0200 (Thu, 13 Aug 2009)
New Revision: 2579
Added:
trunk/tcl/board/keil_mcb1700.cfg
trunk/tcl/target/lpc1768.cfg
Modified:
trunk/doc/openocd.texi
trunk/src/flash/lpc2000.c
trunk/src/flash/lpc2000.h
Log:
Audrius Urmanavi?\196?\141ius [did...@gm...]:
Add flash programming support for NXP LPC1700 cortex_m3 based family
Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi 2009-08-07 09:37:59 UTC (rev 2578)
+++ trunk/doc/openocd.texi 2009-08-13 13:54:53 UTC (rev 2579)
@@ -130,7 +130,7 @@
@b{Flash Programing:} Flash writing is supported for external CFI
compatible NOR flashes (Intel and AMD/Spansion command set) and several
-internal flashes (LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
+internal flashes (LPC1700, LPC2000, AT91SAM7, AT91SAM3U, STR7x, STR9x, LM3, and
STM32x). Preliminary support for various NAND flash controllers
(LPC3180, Orion, S3C24xx, more) controller is included.
@@ -3274,15 +3274,16 @@
@end deffn
@deffn {Flash Driver} lpc2000
-Most members of the LPC2000 microcontroller family from NXP
-include internal flash and use ARM7TDMI cores.
+Most members of the LPC1700 and LPC2000 microcontroller families from NXP
+include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
The @var{lpc2000} driver defines two mandatory and one optional parameters,
which must appear in the following order:
@itemize
@item @var{variant} ... required, may be
@var{lpc2000_v1} (older LPC21xx and LPC22xx)
-or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
+@var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx)
+or @var{lpc1700} (LPC175x and LPC176x)
@item @var{clock_kHz} ... the frequency, in kiloHertz,
at which the core is running
@item @var{calc_checksum} ... optional (but you probably want to provide this!),
Modified: trunk/src/flash/lpc2000.c
===================================================================
--- trunk/src/flash/lpc2000.c 2009-08-07 09:37:59 UTC (rev 2578)
+++ trunk/src/flash/lpc2000.c 2009-08-13 13:54:53 UTC (rev 2579)
@@ -2,6 +2,9 @@
* Copyright (C) 2005 by Dominic Rath *
* Dom...@gm... *
* *
+ * LPC1700 support Copyright (C) 2009 by Audrius Urmanavicius *
+ * did...@gm... *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
@@ -24,13 +27,14 @@
#include "lpc2000.h"
#include "armv4_5.h"
+#include "armv7m.h"
#include "binarybuffer.h"
-/* flash programming support for Philips LPC2xxx devices
+/* flash programming support for NXP LPC17xx and LPC2xxx devices
* currently supported devices:
* variant 1 (lpc2000_v1):
- * - 2104 | 5|6
+ * - 2104 | 5 | 6
* - 2114 | 9
* - 2124 | 9
* - 2194
@@ -40,9 +44,13 @@
* variant 2 (lpc2000_v2):
* - 213x
* - 214x
- * - 2101 | 2|3
- * - 2364 | 6|8
+ * - 2101 | 2 | 3
+ * - 2364 | 6 | 8
* - 2378
+ *
+ * lpc1700:
+ * - 175x
+ * - 176x (tested with LPC1768)
*/
static int lpc2000_register_commands(struct command_context_s *cmd_ctx);
@@ -85,15 +93,14 @@
static int lpc2000_build_sector_list(struct flash_bank_s *bank)
{
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
+ int i;
+ uint32_t offset = 0;
/* default to a 4096 write buffer */
lpc2000_info->cmd51_max_buffer = 4096;
- if (lpc2000_info->variant == 1)
+ if (lpc2000_info->variant == lpc2000_v1)
{
- int i = 0;
- uint32_t offset = 0;
-
/* variant 1 has different layout for 128kb and 256kb flashes */
if (bank->size == 128 * 1024)
{
@@ -144,41 +151,37 @@
exit(-1);
}
}
- else if (lpc2000_info->variant == 2)
+ else if (lpc2000_info->variant == lpc2000_v2)
{
- int num_sectors;
- int i;
- uint32_t offset = 0;
-
/* variant 2 has a uniform layout, only number of sectors differs */
switch (bank->size)
{
case 4 * 1024:
lpc2000_info->cmd51_max_buffer = 1024;
- num_sectors = 1;
+ bank->num_sectors = 1;
break;
case 8 * 1024:
lpc2000_info->cmd51_max_buffer = 1024;
- num_sectors = 2;
+ bank->num_sectors = 2;
break;
case 16 * 1024:
- num_sectors = 4;
+ bank->num_sectors = 4;
break;
case 32 * 1024:
- num_sectors = 8;
+ bank->num_sectors = 8;
break;
case 64 * 1024:
- num_sectors = 9;
+ bank->num_sectors = 9;
break;
case 128 * 1024:
- num_sectors = 11;
+ bank->num_sectors = 11;
break;
case 256 * 1024:
- num_sectors = 15;
+ bank->num_sectors = 15;
break;
case 512 * 1024:
case 500 * 1024:
- num_sectors = 27;
+ bank->num_sectors = 27;
break;
default:
LOG_ERROR("BUG: unknown bank->size encountered");
@@ -186,10 +189,9 @@
break;
}
- bank->num_sectors = num_sectors;
- bank->sectors = malloc(sizeof(flash_sector_t) * num_sectors);
+ bank->sectors = malloc(sizeof(flash_sector_t) * bank->num_sectors);
- for (i = 0; i < num_sectors; i++)
+ for (i = 0; i < bank->num_sectors; i++)
{
if ((i >= 0) && (i < 8))
{
@@ -217,6 +219,42 @@
}
}
}
+ else if (lpc2000_info->variant == lpc1700)
+ {
+ switch(bank->size)
+ {
+ case 32 * 1024:
+ bank->num_sectors = 8;
+ break;
+ case 64 * 1024:
+ bank->num_sectors = 16;
+ break;
+ case 128 * 1024:
+ bank->num_sectors = 18;
+ break;
+ case 256 * 1024:
+ bank->num_sectors = 22;
+ break;
+ case 512 * 1024:
+ bank->num_sectors = 30;
+ break;
+ default:
+ LOG_ERROR("BUG: unknown bank->size encountered");
+ exit(-1);
+ }
+
+ bank->sectors = malloc(sizeof(flash_sector_t) * bank->num_sectors);
+
+ for(i = 0; i < bank->num_sectors; i++)
+ {
+ bank->sectors[i].offset = offset;
+ /* sectors 0-15 are 4kB-sized, 16 and above are 32kB-sized for LPC17xx devices */
+ bank->sectors[i].size = (i < 16)? 4 * 1024 : 32 * 1024;
+ offset += bank->sectors[i].size;
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = 1;
+ }
+ }
else
{
LOG_ERROR("BUG: unknown lpc2000_info->variant encountered");
@@ -226,22 +264,24 @@
return ERROR_OK;
}
-/* call LPC2000 IAP function
- * uses 172 bytes working area
+/* call LPC1700/LPC2000 IAP function
+ * uses 180 bytes working area
* 0x0 to 0x7: jump gate (BX to thumb state, b -2 to wait)
- * 0x8 to 0x1f: command parameter table
- * 0x20 to 0x2b: command result table
- * 0x2c to 0xac: stack (only 128b needed)
+ * 0x8 to 0x1f: command parameter table (1+5 words)
+ * 0x20 to 0x33: command result table (1+4 words)
+ * 0x34 to 0xb3: stack (only 128b needed)
*/
-static int lpc2000_iap_call(flash_bank_t *bank, int code, uint32_t param_table[5], uint32_t result_table[2])
+static int lpc2000_iap_call(flash_bank_t *bank, int code, uint32_t param_table[5], uint32_t result_table[4])
{
int retval;
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
target_t *target = bank->target;
mem_param_t mem_params[2];
reg_param_t reg_params[5];
- armv4_5_algorithm_t armv4_5_info;
- uint32_t status_code;
+ armv4_5_algorithm_t armv4_5_info; /* for LPC2000 */
+ armv7m_algorithm_t armv7m_info; /* for LPC1700 */
+ uint32_t status_code;
+ uint32_t iap_entry_point = 0; /* to make compiler happier */
/* regrab previously allocated working_area, or allocate a new one */
if (!lpc2000_info->iap_working_area)
@@ -249,61 +289,117 @@
uint8_t jump_gate[8];
/* make sure we have a working area */
- if (target_alloc_working_area(target, 172, &lpc2000_info->iap_working_area) != ERROR_OK)
+ if (target_alloc_working_area(target, 180, &lpc2000_info->iap_working_area) != ERROR_OK)
{
LOG_ERROR("no working area specified, can't write LPC2000 internal flash");
return ERROR_FLASH_OPERATION_FAILED;
}
/* write IAP code to working area */
- target_buffer_set_u32(target, jump_gate, ARMV4_5_BX(12));
- target_buffer_set_u32(target, jump_gate + 4, ARMV4_5_B(0xfffffe, 0));
+ switch(lpc2000_info->variant)
+ {
+ case lpc1700:
+ target_buffer_set_u32(target, jump_gate, ARMV7M_T_BX(12));
+ target_buffer_set_u32(target, jump_gate + 4, ARMV7M_T_B(0xfffffe));
+ break;
+ case lpc2000_v1:
+ case lpc2000_v2:
+ target_buffer_set_u32(target, jump_gate, ARMV4_5_BX(12));
+ target_buffer_set_u32(target, jump_gate + 4, ARMV4_5_B(0xfffffe, 0));
+ break;
+ default:
+ LOG_ERROR("BUG: unknown bank->size encountered");
+ exit(-1);
+ }
+
if ((retval = target_write_memory(target, lpc2000_info->iap_working_area->address, 4, 2, jump_gate)) != ERROR_OK)
{
+ LOG_ERROR("Write memory at address 0x%8.8" PRIx32 " failed (check work_area definition)", lpc2000_info->iap_working_area->address);
return retval;
}
}
- armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
- armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
- armv4_5_info.core_state = ARMV4_5_STATE_ARM;
+ switch(lpc2000_info->variant)
+ {
+ case lpc1700:
+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_info.core_mode = ARMV7M_MODE_ANY;
+ iap_entry_point = 0x1fff1ff1;
+ break;
+ case lpc2000_v1:
+ case lpc2000_v2:
+ armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+ armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+ armv4_5_info.core_state = ARMV4_5_STATE_ARM;
+ iap_entry_point = 0x7ffffff1;
+ break;
+ default:
+ LOG_ERROR("BUG: unknown lpc2000->variant encountered");
+ exit(-1);
+ }
/* command parameter table */
- init_mem_param(&mem_params[0], lpc2000_info->iap_working_area->address + 8, 4 * 6, PARAM_OUT);
+ init_mem_param(&mem_params[0], lpc2000_info->iap_working_area->address + 8, 6 * 4, PARAM_OUT);
target_buffer_set_u32(target, mem_params[0].value, code);
- target_buffer_set_u32(target, mem_params[0].value + 0x4, param_table[0]);
- target_buffer_set_u32(target, mem_params[0].value + 0x8, param_table[1]);
- target_buffer_set_u32(target, mem_params[0].value + 0xc, param_table[2]);
+ target_buffer_set_u32(target, mem_params[0].value + 0x04, param_table[0]);
+ target_buffer_set_u32(target, mem_params[0].value + 0x08, param_table[1]);
+ target_buffer_set_u32(target, mem_params[0].value + 0x0c, param_table[2]);
target_buffer_set_u32(target, mem_params[0].value + 0x10, param_table[3]);
target_buffer_set_u32(target, mem_params[0].value + 0x14, param_table[4]);
init_reg_param(®_params[0], "r0", 32, PARAM_OUT);
- buf_set_u32(reg_params[0].value, 0, 32, lpc2000_info->iap_working_area->address + 0x8);
+ buf_set_u32(reg_params[0].value, 0, 32, lpc2000_info->iap_working_area->address + 0x08);
/* command result table */
- init_mem_param(&mem_params[1], lpc2000_info->iap_working_area->address + 0x20, 4 * 3, PARAM_IN);
+ init_mem_param(&mem_params[1], lpc2000_info->iap_working_area->address + 0x20, 5 * 4, PARAM_IN);
init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
buf_set_u32(reg_params[1].value, 0, 32, lpc2000_info->iap_working_area->address + 0x20);
/* IAP entry point */
init_reg_param(®_params[2], "r12", 32, PARAM_OUT);
- buf_set_u32(reg_params[2].value, 0, 32, 0x7ffffff1);
+ buf_set_u32(reg_params[2].value, 0, 32, iap_entry_point);
- /* IAP stack */
- init_reg_param(®_params[3], "r13_svc", 32, PARAM_OUT);
- buf_set_u32(reg_params[3].value, 0, 32, lpc2000_info->iap_working_area->address + 0xac);
+ switch(lpc2000_info->variant)
+ {
+ case lpc1700:
+ /* IAP stack */
+ init_reg_param(®_params[3], "sp", 32, PARAM_OUT);
+ buf_set_u32(reg_params[3].value, 0, 32, lpc2000_info->iap_working_area->address + 0xb4);
- /* return address */
- init_reg_param(®_params[4], "lr_svc", 32, PARAM_OUT);
- buf_set_u32(reg_params[4].value, 0, 32, lpc2000_info->iap_working_area->address + 0x4);
+ /* return address */
+ init_reg_param(®_params[4], "lr", 32, PARAM_OUT);
+ buf_set_u32(reg_params[4].value, 0, 32, (lpc2000_info->iap_working_area->address + 0x04) | 1); /* bit0 of LR = 1 to return in Thumb mode */
- target_run_algorithm(target, 2, mem_params, 5, reg_params, lpc2000_info->iap_working_area->address, lpc2000_info->iap_working_area->address + 0x4, 10000, &armv4_5_info);
+ target_run_algorithm(target, 2, mem_params, 5, reg_params, lpc2000_info->iap_working_area->address, lpc2000_info->iap_working_area->address + 0x4, 10000, &armv7m_info);
+ break;
+ case lpc2000_v1:
+ case lpc2000_v2:
+ /* IAP stack */
+ init_reg_param(®_params[3], "r13_svc", 32, PARAM_OUT);
+ buf_set_u32(reg_params[3].value, 0, 32, lpc2000_info->iap_working_area->address + 0xb4);
- status_code = buf_get_u32(mem_params[1].value, 0, 32);
- result_table[0] = target_buffer_get_u32(target, mem_params[1].value);
- result_table[1] = target_buffer_get_u32(target, mem_params[1].value + 4);
+ /* return address */
+ init_reg_param(®_params[4], "lr_svc", 32, PARAM_OUT);
+ buf_set_u32(reg_params[4].value, 0, 32, lpc2000_info->iap_working_area->address + 0x04);
+ target_run_algorithm(target, 2, mem_params, 5, reg_params, lpc2000_info->iap_working_area->address, lpc2000_info->iap_working_area->address + 0x4, 10000, &armv4_5_info);
+ break;
+ default:
+ LOG_ERROR("BUG: unknown lpc2000->variant encountered");
+ exit(-1);
+ }
+
+
+ status_code = target_buffer_get_u32(target, mem_params[1].value);
+ result_table[0] = target_buffer_get_u32(target, mem_params[1].value + 0x04);
+ result_table[1] = target_buffer_get_u32(target, mem_params[1].value + 0x08);
+ result_table[2] = target_buffer_get_u32(target, mem_params[1].value + 0x0c);
+ result_table[3] = target_buffer_get_u32(target, mem_params[1].value + 0x10);
+
+ LOG_DEBUG("IAP command = %i (0x%8.8" PRIx32", 0x%8.8" PRIx32", 0x%8.8" PRIx32", 0x%8.8" PRIx32", 0x%8.8" PRIx32") completed with result = %8.8" PRIx32,
+ code, param_table[0], param_table[1], param_table[2], param_table[3], param_table[4], status_code);
+
destroy_mem_param(&mem_params[0]);
destroy_mem_param(&mem_params[1]);
@@ -319,7 +415,7 @@
static int lpc2000_iap_blank_check(struct flash_bank_s *bank, int first, int last)
{
uint32_t param_table[5];
- uint32_t result_table[2];
+ uint32_t result_table[4];
int status_code;
int i;
@@ -349,7 +445,7 @@
return ERROR_FLASH_BUSY;
break;
default:
- LOG_ERROR("BUG: unknown LPC2000 status code");
+ LOG_ERROR("BUG: unknown LPC2000 status code %i", status_code);
exit(-1);
}
}
@@ -357,7 +453,8 @@
return ERROR_OK;
}
-/* flash bank lpc2000 <base> <size> 0 0 <target#> <lpc_variant> <cclk> [calc_checksum]
+/*
+ * flash bank lpc2000 <base> <size> 0 0 <target#> <lpc_variant> <cclk> [calc_checksum]
*/
static int lpc2000_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
{
@@ -374,21 +471,31 @@
if (strcmp(args[6], "lpc2000_v1") == 0)
{
- lpc2000_info->variant = 1;
+ lpc2000_info->variant = lpc2000_v1;
lpc2000_info->cmd51_dst_boundary = 512;
lpc2000_info->cmd51_can_256b = 0;
lpc2000_info->cmd51_can_8192b = 1;
+ lpc2000_info->checksum_vector = 5;
}
else if (strcmp(args[6], "lpc2000_v2") == 0)
{
- lpc2000_info->variant = 2;
+ lpc2000_info->variant = lpc2000_v2;
lpc2000_info->cmd51_dst_boundary = 256;
lpc2000_info->cmd51_can_256b = 1;
lpc2000_info->cmd51_can_8192b = 0;
+ lpc2000_info->checksum_vector = 5;
}
+ else if (strcmp(args[6], "lpc1700") == 0)
+ {
+ lpc2000_info->variant = lpc1700;
+ lpc2000_info->cmd51_dst_boundary = 256;
+ lpc2000_info->cmd51_can_256b = 1;
+ lpc2000_info->cmd51_can_8192b = 0;
+ lpc2000_info->checksum_vector = 7;
+ }
else
{
- LOG_ERROR("unknown LPC2000 variant");
+ LOG_ERROR("unknown LPC2000 variant: %s", args[6]);
free(lpc2000_info);
return ERROR_FLASH_BANK_INVALID;
}
@@ -411,7 +518,7 @@
{
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
uint32_t param_table[5];
- uint32_t result_table[2];
+ uint32_t result_table[4];
int status_code;
if (bank->target->state != TARGET_HALTED)
@@ -475,7 +582,7 @@
int first_sector = 0;
int last_sector = 0;
uint32_t param_table[5];
- uint32_t result_table[2];
+ uint32_t result_table[4];
int status_code;
int i;
working_area_t *download_area;
@@ -490,10 +597,7 @@
if (offset + count > bank->size)
return ERROR_FLASH_DST_OUT_OF_BANK;
- if (lpc2000_info->cmd51_can_256b)
- dst_min_alignment = 256;
- else
- dst_min_alignment = 512;
+ dst_min_alignment = lpc2000_info->cmd51_dst_boundary;
if (offset % dst_min_alignment)
{
@@ -515,25 +619,25 @@
if ((offset == 0) && (count >= 0x20) && lpc2000_info->calc_checksum)
{
uint32_t checksum = 0;
- int i = 0;
+ int i;
for (i = 0; i < 8; i++)
{
- LOG_DEBUG("0x%2.2x: 0x%8.8" PRIx32, i * 4, buf_get_u32(buffer + (i * 4), 0, 32));
- if (i != 5)
+ LOG_DEBUG("Vector 0x%2.2x: 0x%8.8" PRIx32, i * 4, buf_get_u32(buffer + (i * 4), 0, 32));
+ if (i != lpc2000_info->checksum_vector)
checksum += buf_get_u32(buffer + (i * 4), 0, 32);
}
checksum = 0 - checksum;
LOG_DEBUG("checksum: 0x%8.8" PRIx32, checksum);
- uint32_t original_value = buf_get_u32(buffer + (5 * 4), 0, 32);
+ uint32_t original_value = buf_get_u32(buffer + (lpc2000_info->checksum_vector * 4), 0, 32);
if (original_value != checksum)
{
- LOG_WARNING("Verification will fail since checksum in image(0x%8.8" PRIx32 ") written to flash was different from calculated vector checksum(0x%8.8" PRIx32 ").",
+ LOG_WARNING("Verification will fail since checksum in image (0x%8.8" PRIx32 ") to be written to flash is different from calculated vector checksum (0x%8.8" PRIx32 ").",
original_value, checksum);
LOG_WARNING("To remove this warning modify build tools on developer PC to inject correct LPC vector checksum.");
}
- buf_set_u32(buffer + 0x14, 0, 32, checksum);
+ buf_set_u32(buffer + (lpc2000_info->checksum_vector * 4), 0, 32, checksum);
}
/* allocate a working area */
@@ -590,10 +694,8 @@
else
{
uint8_t *last_buffer = malloc(thisrun_bytes);
- uint32_t i;
memcpy(last_buffer, buffer + bytes_written, bytes_remaining);
- for (i = bytes_remaining; i < thisrun_bytes; i++)
- last_buffer[i] = 0xff;
+ memset(last_buffer + bytes_remaining, 0xff, thisrun_bytes - bytes_remaining);
target_write_buffer(bank->target, download_area->address, thisrun_bytes, last_buffer);
free(last_buffer);
}
@@ -667,7 +769,7 @@
{
lpc2000_flash_bank_t *lpc2000_info = bank->driver_priv;
- snprintf(buf, buf_size, "lpc2000 flash driver variant: %i, clk: %" PRIi32 , lpc2000_info->variant, lpc2000_info->cclk);
+ snprintf(buf, buf_size, "lpc2000 flash driver variant: %i, clk: %" PRIi32 "kHz" , lpc2000_info->variant, lpc2000_info->cclk);
return ERROR_OK;
}
@@ -676,7 +778,7 @@
{
flash_bank_t *bank;
uint32_t param_table[5];
- uint32_t result_table[2];
+ uint32_t result_table[4];
int status_code;
if (argc < 1)
Modified: trunk/src/flash/lpc2000.h
===================================================================
--- trunk/src/flash/lpc2000.h 2009-08-07 09:37:59 UTC (rev 2578)
+++ trunk/src/flash/lpc2000.h 2009-08-13 13:54:53 UTC (rev 2579)
@@ -2,6 +2,9 @@
* Copyright (C) 2005 by Dominic Rath *
* Dom...@gm... *
* *
+ * LPC1700 support Copyright (C) 2009 by Audrius Urmanavicius *
+ * did...@gm... *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
@@ -22,9 +25,16 @@
#include "flash.h"
+typedef enum
+{
+ lpc2000_v1,
+ lpc2000_v2,
+ lpc1700
+} lpc2000_variant;
+
typedef struct lpc2000_flash_bank_s
{
- int variant;
+ lpc2000_variant variant;
struct working_area_s *iap_working_area;
uint32_t cclk;
int cmd51_dst_boundary;
@@ -32,6 +42,7 @@
int cmd51_can_8192b;
int calc_checksum;
uint32_t cmd51_max_buffer;
+ int checksum_vector;
} lpc2000_flash_bank_t;
enum lpc2000_status_codes
@@ -47,7 +58,16 @@
LPC2000_SECTOR_NOT_BLANK = 8,
LPC2000_SECTOR_NOT_PREPARED = 9,
LPC2000_COMPARE_ERROR = 10,
- LPC2000_BUSY = 11
+ LPC2000_BUSY = 11,
+ LPC2000_PARAM_ERROR = 12,
+ LPC2000_ADDR_ERROR = 13,
+ LPC2000_ADDR_NOT_MAPPED = 14,
+ LPC2000_CMD_NOT_LOCKED = 15,
+ LPC2000_INVALID_CODE = 16,
+ LPC2000_INVALID_BAUD_RATE = 17,
+ LPC2000_INVALID_STOP_BIT = 18,
+ LPC2000_CRP_ENABLED = 19
+
};
#endif /* LPC2000_H */
Added: trunk/tcl/board/keil_mcb1700.cfg
===================================================================
--- trunk/tcl/board/keil_mcb1700.cfg 2009-08-07 09:37:59 UTC (rev 2578)
+++ trunk/tcl/board/keil_mcb1700.cfg 2009-08-13 13:54:53 UTC (rev 2579)
@@ -0,0 +1,8 @@
+#
+# Keil MCB1700 eval board
+#
+# http://www.keil.com/mcb1700/picture.asp
+#
+
+source [find target/lpc1768.cfg]
+
Property changes on: trunk/tcl/board/keil_mcb1700.cfg
___________________________________________________________________
Name: svn:eol-style
+ native
Added: trunk/tcl/target/lpc1768.cfg
===================================================================
--- trunk/tcl/target/lpc1768.cfg 2009-08-07 09:37:59 UTC (rev 2578)
+++ trunk/tcl/target/lpc1768.cfg 2009-08-13 13:54:53 UTC (rev 2579)
@@ -0,0 +1,49 @@
+# NXP LPC1768 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM, clocked with 4MHz internal RC oscillator
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME lpc1768
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x4ba00477
+}
+
+#delays on reset lines
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+# LPC2000 & LPC1700 -> SRST causes TRST
+reset_config trst_and_srst srst_pulls_trst
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+# LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0
+
+$_TARGETNAME configure -event reset-init {
+ soft_reset_halt
+ #do not remap 0x0000-0x0020 to anything but the flash
+# mwb 0xE01FC040 0x01
+ mwb 0xE000ED08 0x00
+}
+
+# LPC1768 has 512kB of user-available FLASH (bootloader is located in separate dedicated region).
+# flash bank lpc1700 <base> <size> 0 0 <target#> <variant> <cclk> [calc_checksum]
+
+flash bank lpc2000 0x0 0x80000 0 0 0 lpc1700 12000 calc_checksum
+
+# 4MHz / 6 = 666kHz, so use 500
+jtag_khz 500
Property changes on: trunk/tcl/target/lpc1768.cfg
___________________________________________________________________
Name: svn:eol-style
+ native
|
|
From: ntfreak at B. <nt...@ma...> - 2009-08-07 11:38:00
|
Author: ntfreak
Date: 2009-08-07 11:37:59 +0200 (Fri, 07 Aug 2009)
New Revision: 2578
Modified:
trunk/src/jtag/tcl.c
Log:
David Brownell <da...@pa...>:
Warn about anyone using "jtag_speed" commands; that command is obsolete, and will someday be removed.
Modified: trunk/src/jtag/tcl.c
===================================================================
--- trunk/src/jtag/tcl.c 2009-08-07 09:29:41 UTC (rev 2577)
+++ trunk/src/jtag/tcl.c 2009-08-07 09:37:59 UTC (rev 2578)
@@ -942,6 +942,9 @@
{
int retval = ERROR_OK;
+ command_print(cmd_ctx, "OLD SYNTAX: DEPRECATED - "
+ "use jtag_khz, not jtag_speed");
+
if (argc > 1)
return ERROR_COMMAND_SYNTAX_ERROR;
if (argc == 1)
|
|
From: ntfreak at B. <nt...@ma...> - 2009-08-07 11:29:42
|
Author: ntfreak
Date: 2009-08-07 11:29:41 +0200 (Fri, 07 Aug 2009)
New Revision: 2577
Modified:
trunk/doc/openocd.texi
Log:
David Brownell <da...@pa...>:
Better explanation for the TAP "-ircapture" parameter.
Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi 2009-08-07 09:19:06 UTC (rev 2576)
+++ trunk/doc/openocd.texi 2009-08-07 09:29:41 UTC (rev 2577)
@@ -2198,7 +2198,10 @@
@itemize @bullet
@item @code{-ircapture} @var{NUMBER}
-@*The IDCODE capture command, such as 0x01.
+@*The bit pattern loaded by the TAP into the JTAG shift register
+on entry to the @sc{ircapture} state, such as 0x01.
+JTAG requires the two LSBs of this value to be 01.
+The value is used to verify that instruction scans work correctly.
@item @code{-irlen} @var{NUMBER}
@*The length in bits of the
instruction register, such as 4 or 5 bits.
|
|
From: ntfreak at B. <nt...@ma...> - 2009-08-07 11:19:06
|
Author: ntfreak
Date: 2009-08-07 11:19:06 +0200 (Fri, 07 Aug 2009)
New Revision: 2576
Modified:
trunk/src/target/arm7_9_common.c
Log:
Ferdinand Postema [fer...@po...]
- fix vector catch issues with certain ARM9 cores - AT91SAM9260 and STR9
Modified: trunk/src/target/arm7_9_common.c
===================================================================
--- trunk/src/target/arm7_9_common.c 2009-08-07 09:09:06 UTC (rev 2575)
+++ trunk/src/target/arm7_9_common.c 2009-08-07 09:19:06 UTC (rev 2576)
@@ -1015,6 +1015,9 @@
{
/* program vector catch register to catch reset vector */
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
+
+ /* extra runtest added as issues were found with certain ARM9 cores (maybe more) - AT91SAM9260 and STR9 */
+ jtag_add_runtest(1, jtag_get_end_state());
}
else
{
|
|
From: ntfreak at B. <nt...@ma...> - 2009-08-07 11:09:06
|
Author: ntfreak
Date: 2009-08-07 11:09:06 +0200 (Fri, 07 Aug 2009)
New Revision: 2575
Modified:
trunk/src/target/armv7m.c
Log:
- fix segfault introduced during cortex reg cleanup
Modified: trunk/src/target/armv7m.c
===================================================================
--- trunk/src/target/armv7m.c 2009-08-06 23:34:34 UTC (rev 2574)
+++ trunk/src/target/armv7m.c 2009-08-07 09:09:06 UTC (rev 2575)
@@ -26,7 +26,7 @@
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
* *
- * ARMv7-M Architecture, Application Level Reference Manual *
+ * ARMv7-M Architecture, Application Level Reference Manual *
* ARM DDI 0405C (September 2008) *
* *
***************************************************************************/
@@ -454,7 +454,7 @@
}
}
- for (i = ARMV7M_NUM_REGS; i >= 0; i--)
+ for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--)
{
uint32_t regvalue;
regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
|
|
From: ntfreak at B. <nt...@ma...> - 2009-08-07 01:34:36
|
Author: ntfreak
Date: 2009-08-07 01:34:34 +0200 (Fri, 07 Aug 2009)
New Revision: 2574
Modified:
trunk/src/jtag/jlink.c
Log:
Gary Carlson [gca...@ca...]:
- revert patch from rev1507 as it was causing reset issues with arm9 cores
Modified: trunk/src/jtag/jlink.c
===================================================================
--- trunk/src/jtag/jlink.c 2009-08-06 21:44:18 UTC (rev 2573)
+++ trunk/src/jtag/jlink.c 2009-08-06 23:34:34 UTC (rev 2574)
@@ -499,12 +499,10 @@
{
jlink_simple_command(EMU_CMD_HW_TRST0);
}
+
if (trst == 0)
{
jlink_simple_command(EMU_CMD_HW_TRST1);
- jtag_sleep(5000);
- jlink_end_state(TAP_RESET);
- jlink_state_move();
}
}
|
|
From: ntfreak at B. <nt...@ma...> - 2009-08-06 23:44:19
|
Author: ntfreak Date: 2009-08-06 23:44:18 +0200 (Thu, 06 Aug 2009) New Revision: 2573 Modified: trunk/tcl/interface/arm-usb-ocd.cfg trunk/tcl/interface/axm0432.cfg trunk/tcl/interface/calao-usb-a9260-c01.cfg trunk/tcl/interface/calao-usb-a9260-c02.cfg trunk/tcl/interface/flyswatter.cfg trunk/tcl/interface/hitex_str9-comstick.cfg trunk/tcl/interface/icebear.cfg trunk/tcl/interface/jtagkey.cfg trunk/tcl/interface/luminary-lm3s811.cfg trunk/tcl/interface/luminary.cfg trunk/tcl/interface/olimex-arm-usb-ocd.cfg trunk/tcl/interface/olimex-jtag-tiny.cfg trunk/tcl/interface/oocdlink.cfg trunk/tcl/interface/openocd-usb.cfg trunk/tcl/interface/sheevaplug.cfg trunk/tcl/interface/signalyzer.cfg trunk/tcl/interface/stm32-stick.cfg trunk/tcl/interface/turtelizer2.cfg Log: - Bring all the ftdi names inline in the cfg scripts. scripts will now work for either ftd2xx or libftdi drivers. Modified: trunk/tcl/interface/arm-usb-ocd.cfg =================================================================== --- trunk/tcl/interface/arm-usb-ocd.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/arm-usb-ocd.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -5,7 +5,7 @@ # interface ft2232 -ft2232_device_desc "Olimex OpenOCD JTAG A" +ft2232_device_desc "Olimex OpenOCD JTAG" ft2232_layout "olimex-jtag" ft2232_vid_pid 0x15BA 0x0003 Modified: trunk/tcl/interface/axm0432.cfg =================================================================== --- trunk/tcl/interface/axm0432.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/axm0432.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -5,7 +5,7 @@ # interface ft2232 -ft2232_device_desc "Symphony SoundBite A" +ft2232_device_desc "Symphony SoundBite" ft2232_layout "axm0432_jtag" ft2232_vid_pid 0x0403 0x6010 Modified: trunk/tcl/interface/calao-usb-a9260-c01.cfg =================================================================== --- trunk/tcl/interface/calao-usb-a9260-c01.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/calao-usb-a9260-c01.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -6,7 +6,7 @@ interface ft2232 ft2232_layout jtagkey -ft2232_device_desc "USB-A9260 A" +ft2232_device_desc "USB-A9260" ft2232_vid_pid 0x0403 0x6010 script interface/calao-usb-a9260.cfg script target/at91sam9260minimal.cfg Modified: trunk/tcl/interface/calao-usb-a9260-c02.cfg =================================================================== --- trunk/tcl/interface/calao-usb-a9260-c02.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/calao-usb-a9260-c02.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -6,7 +6,7 @@ interface ft2232 ft2232_layout jtagkey -ft2232_device_desc "USB-A9260 A" +ft2232_device_desc "USB-A9260" ft2232_vid_pid 0x0403 0x6001 script interface/calao-usb-a9260.cfg script target/at91sam9260minimal.cfg Modified: trunk/tcl/interface/flyswatter.cfg =================================================================== --- trunk/tcl/interface/flyswatter.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/flyswatter.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -5,7 +5,7 @@ # interface ft2232 -ft2232_device_desc "Flyswatter A" +ft2232_device_desc "Flyswatter" ft2232_layout "flyswatter" ft2232_vid_pid 0x0403 0x6010 jtag_speed 1 Modified: trunk/tcl/interface/hitex_str9-comstick.cfg =================================================================== --- trunk/tcl/interface/hitex_str9-comstick.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/hitex_str9-comstick.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -5,7 +5,7 @@ # interface ft2232 -ft2232_device_desc "STR9-comStick A" +ft2232_device_desc "STR9-comStick" ft2232_layout comstick ft2232_vid_pid 0x0640 0x002c Modified: trunk/tcl/interface/icebear.cfg =================================================================== --- trunk/tcl/interface/icebear.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/icebear.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -5,7 +5,7 @@ # interface ft2232 -# ft2232_device_desc "" +ft2232_device_desc "ICEbear JTAG adapter" ft2232_layout icebear ft2232_vid_pid 0x0403 0xc140 Modified: trunk/tcl/interface/jtagkey.cfg =================================================================== --- trunk/tcl/interface/jtagkey.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/jtagkey.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -5,7 +5,7 @@ # interface ft2232 -ft2232_device_desc "Amontec JTAGkey A" +ft2232_device_desc "Amontec JTAGkey" ft2232_layout jtagkey ft2232_vid_pid 0x0403 0xcff8 Modified: trunk/tcl/interface/luminary-lm3s811.cfg =================================================================== --- trunk/tcl/interface/luminary-lm3s811.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/luminary-lm3s811.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -5,6 +5,6 @@ # interface ft2232 -ft2232_device_desc "LM3S811 Evaluation Board A" +ft2232_device_desc "LM3S811 Evaluation Board" ft2232_layout evb_lm3s811 Modified: trunk/tcl/interface/luminary.cfg =================================================================== --- trunk/tcl/interface/luminary.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/luminary.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -5,7 +5,7 @@ # interface ft2232 -ft2232_device_desc "Stellaris Evaluation Board A" +ft2232_device_desc "Stellaris Evaluation Board" ft2232_layout evb_lm3s811 ft2232_vid_pid 0x0403 0xbcd9 Modified: trunk/tcl/interface/olimex-arm-usb-ocd.cfg =================================================================== --- trunk/tcl/interface/olimex-arm-usb-ocd.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/olimex-arm-usb-ocd.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -5,7 +5,7 @@ # interface ft2232 -ft2232_device_desc "Olimex OpenOCD JTAG A" +ft2232_device_desc "Olimex OpenOCD JTAG" ft2232_layout olimex-jtag ft2232_vid_pid 0x15ba 0x0003 Modified: trunk/tcl/interface/olimex-jtag-tiny.cfg =================================================================== --- trunk/tcl/interface/olimex-jtag-tiny.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/olimex-jtag-tiny.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -5,7 +5,7 @@ # interface ft2232 -ft2232_device_desc "Olimex OpenOCD JTAG TINY A" +ft2232_device_desc "Olimex OpenOCD JTAG TINY" ft2232_layout olimex-jtag ft2232_vid_pid 0x15ba 0x0004 Modified: trunk/tcl/interface/oocdlink.cfg =================================================================== --- trunk/tcl/interface/oocdlink.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/oocdlink.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -5,7 +5,7 @@ # interface ft2232 -ft2232_device_desc "OOCDLink A" +ft2232_device_desc "OOCDLink" ft2232_layout oocdlink ft2232_vid_pid 0x0403 0xbaf8 jtag_khz 5 Modified: trunk/tcl/interface/openocd-usb.cfg =================================================================== --- trunk/tcl/interface/openocd-usb.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/openocd-usb.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -6,7 +6,7 @@ interface ft2232 ft2232_vid_pid 0x0403 0x6010 -ft2232_device_desc "Dual RS232 A" +ft2232_device_desc "Dual RS232" ft2232_layout "oocdlink" ft2232_latency 2 # 6/(1+n) Mhz TCLK Modified: trunk/tcl/interface/sheevaplug.cfg =================================================================== --- trunk/tcl/interface/sheevaplug.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/sheevaplug.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -7,6 +7,6 @@ interface ft2232 ft2232_layout sheevaplug ft2232_vid_pid 0x9e88 0x9e8f -ft2232_device_desc "SheevaPlug JTAGKey FT2232D B" +ft2232_device_desc "SheevaPlug JTAGKey FT2232D" jtag_khz 2000 Modified: trunk/tcl/interface/signalyzer.cfg =================================================================== --- trunk/tcl/interface/signalyzer.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/signalyzer.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -5,7 +5,7 @@ # interface ft2232 -ft2232_device_desc "Signalyzer A" +ft2232_device_desc "Signalyzer" ft2232_layout signalyzer ft2232_vid_pid 0x0403 0xbca0 Modified: trunk/tcl/interface/stm32-stick.cfg =================================================================== --- trunk/tcl/interface/stm32-stick.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/stm32-stick.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -5,7 +5,7 @@ # interface ft2232 -ft2232_device_desc "STM32-PerformanceStick A" +ft2232_device_desc "STM32-PerformanceStick" ft2232_layout stm32stick ft2232_vid_pid 0x0640 0x002d Modified: trunk/tcl/interface/turtelizer2.cfg =================================================================== --- trunk/tcl/interface/turtelizer2.cfg 2009-08-06 19:52:56 UTC (rev 2572) +++ trunk/tcl/interface/turtelizer2.cfg 2009-08-06 21:44:18 UTC (rev 2573) @@ -5,7 +5,7 @@ # interface ft2232 -ft2232_device_desc "Turtelizer JTAG/RS232 Adapter A" +ft2232_device_desc "Turtelizer JTAG/RS232 Adapter" ft2232_layout turtelizer2 ft2232_vid_pid 0x0403 0xbdc8 |
|
From: <zw...@ma...> - 2009-08-06 21:52:59
|
Author: zwelch
Date: 2009-08-06 21:52:56 +0200 (Thu, 06 Aug 2009)
New Revision: 2572
Modified:
trunk/src/target/arm11.c
Log:
michal smulski <mic...@oo...>:
Fix ARM11 half-word bulk memory read and write.
Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c 2009-07-31 08:52:03 UTC (rev 2571)
+++ trunk/src/target/arm11.c 2009-08-06 19:52:56 UTC (rev 2572)
@@ -1149,7 +1149,7 @@
arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
uint16_t svalue = res;
- memcpy(buffer + count * sizeof(uint16_t), &svalue, sizeof(uint16_t));
+ memcpy(buffer + i * sizeof(uint16_t), &svalue, sizeof(uint16_t));
}
break;
@@ -1219,7 +1219,7 @@
for (size_t i = 0; i < count; i++)
{
uint16_t value;
- memcpy(&value, buffer + count * sizeof(uint16_t), sizeof(uint16_t));
+ memcpy(&value, buffer + i * sizeof(uint16_t), sizeof(uint16_t));
/* MRC p14,0,r1,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
|
|
From: ntfreak at B. <nt...@ma...> - 2009-07-31 10:52:04
|
Author: ntfreak
Date: 2009-07-31 10:52:03 +0200 (Fri, 31 Jul 2009)
New Revision: 2571
Modified:
trunk/configure.in
Log:
- add configure error if building parport interface under cygwin and sys/io.h missing
Modified: trunk/configure.in
===================================================================
--- trunk/configure.in 2009-07-27 18:56:43 UTC (rev 2570)
+++ trunk/configure.in 2009-07-31 08:52:03 UTC (rev 2571)
@@ -467,6 +467,10 @@
else
is_cygwin=yes
AC_DEFINE(IS_CYGWIN, 1, [1 if building for Cygwin.])
+ # sys/io.h needed under cygwin for parport access
+ if test $build_parport = yes; then
+ AC_CHECK_HEADERS(sys/io.h,[],AC_MSG_ERROR([Please install the cygwin ioperm package]))
+ fi
fi
AC_DEFINE(IS_WIN32, 1, [1 if building for Win32.])
|
|
From: oharboe at B. <oh...@ma...> - 2009-07-27 20:56:44
|
Author: oharboe
Date: 2009-07-27 20:56:43 +0200 (Mon, 27 Jul 2009)
New Revision: 2570
Modified:
trunk/src/server/gdb_server.c
Log:
Fix NPE in GDB_EVENT_END as logforwarding was not disabled early enough
Modified: trunk/src/server/gdb_server.c
===================================================================
--- trunk/src/server/gdb_server.c 2009-07-27 14:46:49 UTC (rev 2569)
+++ trunk/src/server/gdb_server.c 2009-07-27 18:56:43 UTC (rev 2570)
@@ -816,6 +816,11 @@
gdb_service_t *gdb_service = connection->service->priv;
gdb_connection_t *gdb_connection = connection->priv;
+ /* we're done forwarding messages. Tear down callback before
+ * cleaning up connection.
+ */
+ log_remove_callback(gdb_log_callback, connection);
+
gdb_actual_connections--;
LOG_DEBUG("GDB Close, Target: %s, state: %s, gdb_actual_connections=%d",
gdb_service->target->cmd_name,
@@ -843,9 +848,10 @@
LOG_ERROR("BUG: connection->priv == NULL");
}
+
target_unregister_event_callback(gdb_target_callback_event_handler, connection);
+
target_call_event_callbacks(gdb_service->target, TARGET_EVENT_GDB_END);
- log_remove_callback(gdb_log_callback, connection);
target_call_event_callbacks(gdb_service->target, TARGET_EVENT_GDB_DETACH);
|
|
From: oharboe at B. <oh...@ma...> - 2009-07-27 16:46:50
|
Author: oharboe Date: 2009-07-27 16:46:49 +0200 (Mon, 27 Jul 2009) New Revision: 2569 Modified: trunk/BUGS Log: add "dummy" interface trick to the BUGS reporting suggestions Modified: trunk/BUGS =================================================================== --- trunk/BUGS 2009-07-26 20:00:39 UTC (rev 2568) +++ trunk/BUGS 2009-07-27 14:46:49 UTC (rev 2569) @@ -34,8 +34,15 @@ @section bugscrashdump Obtaining Crash Backtraces -If OpenOCD is crashing, you can use GDB to get a trace:@par +If OpenOCD is crashing, there are two very effective things you can do to +improve your chances of getting help on the development mailing list. + +Try to reproduce the problem using the dummy JTAG interface to allow other developers to replicate +your problem robustly and use GDB to get a trace:@par @code +% OPENOCDSRC/configure --enable-dummy ... +% openocd -f interface/dummy.cfg -f target/xxx.cfg +=> SEGFAULT % gdb --args openocd .... (gdb) run (gdb) bt |
|
From: oharboe at B. <oh...@ma...> - 2009-07-26 22:00:40
|
Author: oharboe
Date: 2009-07-26 22:00:39 +0200 (Sun, 26 Jul 2009)
New Revision: 2568
Modified:
trunk/src/target/arm_disassembler.c
Log:
David Brownell <da...@pa...> More testcase work:
A5.3.11 Data processing (shifted register)
The usual kinds of problems; the most noteworthy were that
the "S"et flags bit was mis-handled in these instructions.
---
This is the last patch from a quickie set of tests covering all
encodings of the instructions with 32-bit opcodes. There may
be some corner cases left, plus the instructions that aren't
yet handled, but the Thumb2 disassembler is no longer just
"lightly" tested with GCC output ... the new code paths have
mostly been verified.
Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c 2009-07-26 19:59:33 UTC (rev 2567)
+++ trunk/src/target/arm_disassembler.c 2009-07-26 20:00:39 UTC (rev 2568)
@@ -1395,6 +1395,7 @@
}
else
{
+ /* REVISIT: if reg_imm == 0, display as "MOVS" */
instruction->type = ARM_ADD;
mnemonic = "ADDS";
}
@@ -3017,17 +3018,18 @@
char *mnemonic;
char *suffix = "";
- immed |= (opcode >> 10) & 0x7;
- if (opcode & (1 << 21))
+ immed |= (opcode >> 10) & 0x1c;
+ if (opcode & (1 << 20))
suffix = "S";
switch (op) {
case 0:
if (rd == 0xf) {
- if (!(opcode & (1 << 21)))
+ if (!(opcode & (1 << 20)))
return ERROR_INVALID_ARGUMENTS;
instruction->type = ARM_TST;
mnemonic = "TST";
+ suffix = "";
goto two;
}
instruction->type = ARM_AND;
@@ -3058,7 +3060,7 @@
break;
default:
if (immed == 0) {
- sprintf(cp, "RRX%s.W\tr%d, r%d",
+ sprintf(cp, "RRX%s\tr%d, r%d",
suffix, rd,
(int) (opcode & 0xf));
return ERROR_OK;
@@ -3085,10 +3087,11 @@
break;
case 4:
if (rd == 0xf) {
- if (!(opcode & (1 << 21)))
+ if (!(opcode & (1 << 20)))
return ERROR_INVALID_ARGUMENTS;
instruction->type = ARM_TEQ;
mnemonic = "TEQ";
+ suffix = "";
goto two;
}
instruction->type = ARM_EOR;
@@ -3096,10 +3099,11 @@
break;
case 8:
if (rd == 0xf) {
- if (!(opcode & (1 << 21)))
+ if (!(opcode & (1 << 20)))
return ERROR_INVALID_ARGUMENTS;
instruction->type = ARM_CMN;
mnemonic = "CMN";
+ suffix = "";
goto two;
}
instruction->type = ARM_ADD;
@@ -3119,6 +3123,7 @@
return ERROR_INVALID_ARGUMENTS;
instruction->type = ARM_CMP;
mnemonic = "CMP";
+ suffix = "";
goto two;
}
instruction->type = ARM_SUB;
@@ -3146,13 +3151,17 @@
break;
case 1:
suffix = "LSR";
+ if (immed == 32)
+ immed = 0;
break;
case 2:
suffix = "ASR";
+ if (immed == 32)
+ immed = 0;
break;
case 3:
if (immed == 0) {
- strcpy(cp, "RRX");
+ strcpy(cp, ", RRX");
return ERROR_OK;
}
suffix = "ROR";
|
|
From: oharboe at B. <oh...@ma...> - 2009-07-26 21:59:33
|
Author: oharboe
Date: 2009-07-26 21:59:33 +0200 (Sun, 26 Jul 2009)
New Revision: 2567
Modified:
trunk/src/target/arm_disassembler.c
Log:
More instruction decoding fixes:
A5.3.5 Load/store multiple
A5.3.7 Load word
There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM
fixes are just using width specs to match UAL syntax, except for two
opcode name typos. Load word had two bitmask goofs.
Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c 2009-07-26 19:58:25 UTC (rev 2566)
+++ trunk/src/target/arm_disassembler.c 2009-07-26 19:59:33 UTC (rev 2567)
@@ -2853,6 +2853,7 @@
sprintf(cp, "STR%s.W\tr%d, [r%d, r%d, LSL #%d]",
size, rt, rn, (int) opcode & 0x0f,
(int) (opcode >> 4) & 0x03);
+ return ERROR_OK;
imm12:
immed = opcode & 0x0fff;
@@ -3354,18 +3355,21 @@
int rt = (opcode >> 12) & 0xf;
int op2 = (opcode >> 6) & 0x3f;
unsigned immed;
- char *p1 = "]", *p2 = "";
+ char *p1 = "", *p2 = "]";
char *mnemonic;
switch ((opcode >> 23) & 0x3) {
case 0:
if ((rn & rt) == 0xf) {
-preload_immediate_t2:
+pld_literal:
immed = opcode & 0xfff;
-preload_immediate_t1:
- p1 = (opcode & (1 << 21)) ? "W" : "";
- sprintf(cp, "PLD%s\t[r%d, #%d]\t; %#6.6x",
- p1, rn, immed, immed);
+ address = thumb_alignpc4(address);
+ if (opcode & (1 << 23))
+ address += immed;
+ else
+ address -= immed;
+ sprintf(cp, "PLD\tr%d, %#8.8" PRIx32,
+ rt, address);
return ERROR_OK;
}
if (rn == 0x0f && rt != 0x0f) {
@@ -3391,12 +3395,17 @@
if ((op2 & 0x3c) == 0x30) {
if (rt == 0x0f) {
immed = opcode & 0xff;
- goto preload_immediate_t1;
+ immed = -immed;
+preload_immediate:
+ p1 = (opcode & (1 << 21)) ? "W" : "";
+ sprintf(cp, "PLD%s\t[r%d, #%d]\t; %#6.6x",
+ p1, rn, immed, immed);
+ return ERROR_OK;
}
mnemonic = "LDRB";
ldrxb_immediate_t3:
immed = opcode & 0xff;
- if (opcode & 0x200)
+ if (!(opcode & 0x200))
immed = -immed;
/* two indexed modes will write back rn */
@@ -3432,8 +3441,12 @@
}
break;
case 1:
- if (rt == 0xf)
- goto preload_immediate_t2;
+ if ((rn & rt) == 0xf)
+ goto pld_literal;
+ if (rt == 0xf) {
+ immed = opcode & 0xfff;
+ goto preload_immediate;
+ }
if (rn == 0x0f)
goto ldrb_literal;
mnemonic = "LDRB.W";
@@ -3441,7 +3454,6 @@
goto ldrxb_immediate_t2;
case 2:
if ((rn & rt) == 0xf) {
-pli_immediate:
immed = opcode & 0xfff;
address = thumb_alignpc4(address);
if (opcode & (1 << 23))
@@ -3466,7 +3478,7 @@
break;
if ((op2 & 0x3c) == 0x38) {
immed = opcode & 0xff;
- sprintf(cp, "LDRSBT\tr%d, [r%d, #%d]\t; %2.2x",
+ sprintf(cp, "LDRSBT\tr%d, [r%d, #%d]\t; %#2.2x",
rt, rn, immed, immed);
return ERROR_OK;
}
@@ -3474,8 +3486,8 @@
if (rt == 0xf) {
immed = opcode & 0xff;
immed = -immed; // pli
- sprintf(cp, "PLI\t[r%d, #-%d]\t; %2.2x",
- rn, immed, immed);
+ sprintf(cp, "PLI\t[r%d, #%d]\t; -%#2.2x",
+ rn, immed, -immed);
return ERROR_OK;
}
mnemonic = "LDRSB";
@@ -3499,8 +3511,12 @@
}
break;
case 3:
- if (rt == 0xf)
- goto pli_immediate;
+ if (rt == 0xf) {
+ immed = opcode & 0xfff;
+ sprintf(cp, "PLI\t[r%d, #%d]\t; %#3.3" PRIx32,
+ rn, immed, immed);
+ return ERROR_OK;
+ }
if (rn == 0xf)
goto ldrsb_literal;
immed = opcode & 0xfff;
|
|
From: oharboe at B. <oh...@ma...> - 2009-07-26 21:58:26
|
Author: oharboe
Date: 2009-07-26 21:58:25 +0200 (Sun, 26 Jul 2009)
New Revision: 2566
Modified:
trunk/src/target/arm_disassembler.c
Log:
David Brownell <da...@pa...> More fixes from test cases:
A5.3.8 Load halfword, unallocated memory hints
It's mostly the usual sort of bitmasking goofage and getting the
width specs right. In one case an older x86 GCC generated bad code
unless I structred a conditional differently (sigh).
Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c 2009-07-26 19:56:58 UTC (rev 2565)
+++ trunk/src/target/arm_disassembler.c 2009-07-26 19:58:25 UTC (rev 2566)
@@ -3517,7 +3517,7 @@
int rn = (opcode >> 16) & 0xf;
int rt = (opcode >> 12) & 0xf;
int op2 = (opcode >> 6) & 0x3f;
- char *sign = (opcode & (1 < 24)) ? "S" : "";
+ char *sign = "";
unsigned immed;
if (rt == 0xf) {
@@ -3525,6 +3525,9 @@
return ERROR_OK;
}
+ if (opcode & (1 << 24))
+ sign = "S";
+
if ((opcode & (1 << 23)) == 0) {
if (rn == 0xf) {
ldrh_literal:
@@ -3547,16 +3550,16 @@
return ERROR_OK;
}
if ((op2 & 0x3c) == 0x38) {
- immed = (opcode >> 4) & 0x3;
+ immed = opcode & 0xff;
sprintf(cp, "LDR%sHT\tr%d, [r%d, #%d]\t; %#2.2x",
sign, rt, rn, immed, immed);
return ERROR_OK;
}
if ((op2 & 0x3c) == 0x30 || (op2 & 0x24) == 0x24) {
- char *p1 = "]", *p2 = "";
+ char *p1 = "", *p2 = "]";
immed = opcode & 0xff;
- if (opcode & 0x200)
+ if (!(opcode & 0x200))
immed = -immed;
/* two indexed modes will write back rn */
@@ -3577,8 +3580,9 @@
goto ldrh_literal;
immed = opcode & 0xfff;
- sprintf(cp, "LDR%sH.W\tr%d, [r%d, #%d]\t; %#6.6x",
- sign, rt, rn, immed, immed);
+ sprintf(cp, "LDR%sH%s\tr%d, [r%d, #%d]\t; %#6.6x",
+ sign, *sign ? "" : ".W",
+ rt, rn, immed, immed);
return ERROR_OK;
}
@@ -3653,7 +3657,7 @@
retval = t2ev_load_word(opcode, address, instruction, cp);
/* ARMv7-M: A5.3.8 Load halfword, unallocated memory hints */
- else if ((opcode & 0x1e700000) == 0x18e00000)
+ else if ((opcode & 0x1e700000) == 0x18300000)
retval = t2ev_load_halfword(opcode, address, instruction, cp);
/* ARMv7-M: A5.3.9 Load byte, memory hints */
|
|
From: oharboe at B. <oh...@ma...> - 2009-07-26 21:57:00
|
Author: oharboe
Date: 2009-07-26 21:56:58 +0200 (Sun, 26 Jul 2009)
New Revision: 2565
Modified:
trunk/src/target/arm_disassembler.c
Log:
David Brownell <da...@pa...> More instruction decoding fixes:
A5.3.5 Load/store multiple
A5.3.7 Load word
There was a longstanding bug in Thumb-1 LDM; the rest of the LDM/STM
fixes are just using width specs to match UAL syntax, except for two
opcode name typos. Load word had two bitmask goofs.
Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c 2009-07-24 16:49:44 UTC (rev 2564)
+++ trunk/src/target/arm_disassembler.c 2009-07-26 19:56:58 UTC (rev 2565)
@@ -1944,17 +1944,21 @@
if ((opcode & 0xf000) == 0xc000)
{ /* generic load/store multiple */
+ char *wback = "!";
+
if (L)
{
instruction->type = ARM_LDM;
mnemonic = "LDM";
+ if (opcode & (1 << Rn))
+ wback = "";
}
else
{
instruction->type = ARM_STM;
mnemonic = "STM";
}
- snprintf(ptr_name,7,"r%i!, ",Rn);
+ snprintf(ptr_name, sizeof ptr_name, "r%i%s, ", Rn, wback);
}
else
{ /* push/pop */
@@ -2965,22 +2969,22 @@
switch (op) {
case 2:
- sprintf(cp, "STMB\tr%d%s, ", rn, t ? "!" : "");
+ sprintf(cp, "STM.W\tr%d%s, ", rn, t ? "!" : "");
break;
case 3:
if (rn == 13 && t)
- sprintf(cp, "POP\t");
+ sprintf(cp, "POP.W\t");
else
sprintf(cp, "LDM.W\tr%d%s, ", rn, t ? "!" : "");
break;
case 4:
if (rn == 13 && t)
- sprintf(cp, "PUSH\t");
+ sprintf(cp, "PUSH.W\t");
else
- sprintf(cp, "STM.W\tr%d%s, ", rn, t ? "!" : "");
+ sprintf(cp, "STMDB\tr%d%s, ", rn, t ? "!" : "");
break;
case 5:
- sprintf(cp, "LDMB\tr%d%s, ", rn, t ? "!" : "");
+ sprintf(cp, "LDMDB.W\tr%d%s, ", rn, t ? "!" : "");
break;
default:
return ERROR_INVALID_ARGUMENTS;
@@ -3279,7 +3283,7 @@
if (rn == 0xf) {
immed = opcode & 0x0fff;
- if (opcode & (1 << 23))
+ if ((opcode & (1 << 23)) == 0)
immed = -immed;
sprintf(cp, "LDR\tr%d, %#8.8" PRIx32,
(int) (opcode >> 12) & 0xf,
@@ -3317,7 +3321,7 @@
if (((opcode >> 8) & 0xf) == 0xc || (opcode & 0x0900) == 0x0900) {
char *p1 = "]", *p2 = "";
- if (!(opcode & 0x0600))
+ if (!(opcode & 0x0500))
return ERROR_INVALID_ARGUMENTS;
immed = opcode & 0x00ff;
|
