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From: oharboe at B. <oh...@ma...> - 2009-07-24 18:49:58
|
Author: oharboe Date: 2009-07-24 18:49:44 +0200 (Fri, 24 Jul 2009) New Revision: 2564 Modified: trunk/src/target/arm_disassembler.c Log: David Brownell <da...@pa...> More instruction decoding fixes based on test cases, covering ARMv7-M arch manual: A5.3.1 Data processing (modified immediate) A5.3.3 Data processing (plain binary immediate) A5.3.4 Branches and miscellaneous control and other (immediate) encodings referenced there. Several of these just tweak the new syntax ("Unified" ARM/Thumb: UAL) but there were a few bugs too. Modified: trunk/src/target/arm_disassembler.c =================================================================== --- trunk/src/target/arm_disassembler.c 2009-07-24 16:48:12 UTC (rev 2563) +++ trunk/src/target/arm_disassembler.c 2009-07-24 16:49:44 UTC (rev 2564) @@ -1644,7 +1644,7 @@ break; case 0x9: instruction->type = ARM_RSB; - mnemonic = "NEGS"; + mnemonic = "RSBS"; instruction->info.data_proc.variant = 0 /*immediate*/; instruction->info.data_proc.shifter_operand.immediate.immediate = 0; instruction->info.data_proc.Rn = Rm; @@ -2600,7 +2600,6 @@ mnemonic = "TST"; one = true; suffix = ""; - suffix2 = ".W"; rd = rn; } else { instruction->type = ARM_AND; @@ -2660,6 +2659,7 @@ case 10: instruction->type = ARM_ADC; mnemonic = "ADC"; + suffix2 = ".W"; break; case 11: instruction->type = ARM_SBC; @@ -2708,8 +2708,8 @@ bool add = false; bool is_signed = false; - immed = (opcode & 0x0ff) | ((opcode & 0x7000) >> 12); - if (opcode & (1 << 27)) + immed = (opcode & 0x0ff) | ((opcode & 0x7000) >> 4); + if (opcode & (1 << 26)) immed |= (1 << 11); switch ((opcode >> 20) & 0x1f) { @@ -2718,15 +2718,16 @@ add = true; goto do_adr; } - mnemonic = "ADD.W"; + mnemonic = "ADDW"; break; case 4: - mnemonic = "MOV.W"; - break; + immed |= (opcode >> 4) & 0xf000; + sprintf(cp, "MOVW\tr%d, #%d\t; %#3.3x", rd, immed, immed); + return ERROR_OK; case 0x0a: if (rn == 0xf) goto do_adr; - mnemonic = "SUB.W"; + mnemonic = "SUBW"; break; case 0x0c: /* move constant to top 16 bits of register */ @@ -2743,7 +2744,7 @@ immed |= (opcode >> 10) & 0x1c; sprintf(cp, "%sSAT\tr%d, #%d, r%d, %s #%d\t", is_signed ? "S" : "U", - rd, (int) (opcode & 0x1f) + 1, rn, + rd, (int) (opcode & 0x1f) + is_signed, rn, (opcode & (1 << 21)) ? "ASR" : "LSL", immed ? immed : 32); return ERROR_OK; |
From: oharboe at B. <oh...@ma...> - 2009-07-24 18:48:17
|
Author: oharboe Date: 2009-07-24 18:48:12 +0200 (Fri, 24 Jul 2009) New Revision: 2563 Modified: trunk/src/target/arm_disassembler.c Log: David Brownell <da...@pa...> Bugfix some instruction decoding ... I've crafted asm files with testcases covering several new encodings in these sections of the ARMv7-M arch manual: A5.3.12 Data processing (register) A5.3.13 Miscellaneous operations A5.3.14 Multiply, and multiply accumulate A5.3.15 Long multiply, long multiply accumulate, and divide The issues were mostly in '12 and '13; some new related 16-bit opcodes had issues too. Modified: trunk/src/target/arm_disassembler.c =================================================================== --- trunk/src/target/arm_disassembler.c 2009-07-24 05:42:45 UTC (rev 2562) +++ trunk/src/target/arm_disassembler.c 2009-07-24 16:48:12 UTC (rev 2563) @@ -2098,7 +2098,7 @@ char *suffix; /* added in ARMv6 */ - switch (opcode & 0x00c0) { + switch ((opcode >> 6) & 3) { case 0: suffix = ""; break; @@ -3201,7 +3201,7 @@ (int) (opcode >> 0) & 0xf); } else if (opcode & (1 << 7)) { - switch ((opcode >> 24) & 0xf) { + switch ((opcode >> 20) & 0xf) { case 0: case 1: case 4: @@ -3221,7 +3221,7 @@ (opcode & (1 << 24)) ? 'U' : 'S', (opcode & (1 << 26)) ? 'B' : 'H', (int) (opcode >> 8) & 0xf, - (int) (opcode >> 16) & 0xf, + (int) (opcode >> 0) & 0xf, suffix); break; case 8: @@ -3230,7 +3230,7 @@ case 0xb: if (opcode & (1 << 6)) return ERROR_INVALID_ARGUMENTS; - if (~opcode & (0xff << 12)) + if (((opcode >> 12) & 0xf) != 0xf) return ERROR_INVALID_ARGUMENTS; if (!(opcode & (1 << 20))) return ERROR_INVALID_ARGUMENTS; |
From: oharboe at B. <oh...@ma...> - 2009-07-24 07:42:53
|
Author: oharboe Date: 2009-07-24 07:42:45 +0200 (Fri, 24 Jul 2009) New Revision: 2562 Modified: trunk/src/target/arm_disassembler.c Log: Andreas Fritiofson <and...@gm...> I noticed there are a few checks for (rt == 0xf) even though that case is handled with an early return at the top of the function. Modified: trunk/src/target/arm_disassembler.c =================================================================== --- trunk/src/target/arm_disassembler.c 2009-07-23 15:35:16 UTC (rev 2561) +++ trunk/src/target/arm_disassembler.c 2009-07-24 05:42:45 UTC (rev 2562) @@ -3523,8 +3523,6 @@ if ((opcode & (1 << 23)) == 0) { if (rn == 0xf) { ldrh_literal: - if (rt == 0xf) - return ERROR_INVALID_ARGUMENTS; immed = opcode & 0xfff; address = thumb_alignpc4(address); if (opcode & (1 << 23)) @@ -3535,8 +3533,6 @@ sign, rt, address); return ERROR_OK; } - if (rt == 0xf) - return ERROR_INVALID_ARGUMENTS; if (op2 == 0) { int rm = opcode & 0xf; @@ -3574,12 +3570,11 @@ } else { if (rn == 0xf) goto ldrh_literal; - if (rt != 0x0f) { - immed = opcode & 0xfff; - sprintf(cp, "LDR%sH.W\tr%d, [r%d, #%d]\t; %#6.6x", - sign, rt, rn, immed, immed); - return ERROR_OK; - } + + immed = opcode & 0xfff; + sprintf(cp, "LDR%sH.W\tr%d, [r%d, #%d]\t; %#6.6x", + sign, rt, rn, immed, immed); + return ERROR_OK; } return ERROR_INVALID_ARGUMENTS; |
From: oharboe at B. <oh...@ma...> - 2009-07-23 17:35:17
|
Author: oharboe Date: 2009-07-23 17:35:16 +0200 (Thu, 23 Jul 2009) New Revision: 2561 Modified: trunk/src/target/arm_disassembler.c Log: David Brownell <da...@pa...> thumb2 disassembly for Load halfword Modified: trunk/src/target/arm_disassembler.c =================================================================== --- trunk/src/target/arm_disassembler.c 2009-07-23 15:34:03 UTC (rev 2560) +++ trunk/src/target/arm_disassembler.c 2009-07-23 15:35:16 UTC (rev 2561) @@ -3506,6 +3506,85 @@ return ERROR_INVALID_ARGUMENTS; } +static int t2ev_load_halfword(uint32_t opcode, uint32_t address, + arm_instruction_t *instruction, char *cp) +{ + int rn = (opcode >> 16) & 0xf; + int rt = (opcode >> 12) & 0xf; + int op2 = (opcode >> 6) & 0x3f; + char *sign = (opcode & (1 < 24)) ? "S" : ""; + unsigned immed; + + if (rt == 0xf) { + sprintf(cp, "HINT (UNALLOCATED)"); + return ERROR_OK; + } + + if ((opcode & (1 << 23)) == 0) { + if (rn == 0xf) { +ldrh_literal: + if (rt == 0xf) + return ERROR_INVALID_ARGUMENTS; + immed = opcode & 0xfff; + address = thumb_alignpc4(address); + if (opcode & (1 << 23)) + address += immed; + else + address -= immed; + sprintf(cp, "LDR%sH\tr%d, %#8.8" PRIx32, + sign, rt, address); + return ERROR_OK; + } + if (rt == 0xf) + return ERROR_INVALID_ARGUMENTS; + if (op2 == 0) { + int rm = opcode & 0xf; + + immed = (opcode >> 4) & 0x3; + sprintf(cp, "LDR%sH.W\tr%d, [r%d, r%d, LSL #%d]", + sign, rt, rn, rm, immed); + return ERROR_OK; + } + if ((op2 & 0x3c) == 0x38) { + immed = (opcode >> 4) & 0x3; + sprintf(cp, "LDR%sHT\tr%d, [r%d, #%d]\t; %#2.2x", + sign, rt, rn, immed, immed); + return ERROR_OK; + } + if ((op2 & 0x3c) == 0x30 || (op2 & 0x24) == 0x24) { + char *p1 = "]", *p2 = ""; + + immed = opcode & 0xff; + if (opcode & 0x200) + immed = -immed; + + /* two indexed modes will write back rn */ + if (opcode & 0x100) { + if (opcode & 0x400) /* pre-indexed */ + p2 = "]!"; + else { /* post-indexed */ + p1 = "]"; + p2 = ""; + } + } + sprintf(cp, "LDR%sH\tr%d, [r%d%s, #%d%s\t; %#8.8x", + sign, rt, rn, p1, immed, p2, immed); + return ERROR_OK; + } + } else { + if (rn == 0xf) + goto ldrh_literal; + if (rt != 0x0f) { + immed = opcode & 0xfff; + sprintf(cp, "LDR%sH.W\tr%d, [r%d, #%d]\t; %#6.6x", + sign, rt, rn, immed, immed); + return ERROR_OK; + } + } + + return ERROR_INVALID_ARGUMENTS; +} + /* * REVISIT for Thumb2 instructions, instruction->type and friends aren't * always set. That means eventual arm_simulate_step() support for Thumb2 @@ -3573,6 +3652,10 @@ else if ((opcode & 0x1f700000) == 0x18500000) retval = t2ev_load_word(opcode, address, instruction, cp); + /* ARMv7-M: A5.3.8 Load halfword, unallocated memory hints */ + else if ((opcode & 0x1e700000) == 0x18e00000) + retval = t2ev_load_halfword(opcode, address, instruction, cp); + /* ARMv7-M: A5.3.9 Load byte, memory hints */ else if ((opcode & 0x1e700000) == 0x18100000) retval = t2ev_load_byte_hints(opcode, address, instruction, cp); @@ -3585,7 +3668,9 @@ else if ((opcode & 0x1e000000) == 0x0a000000) retval = t2ev_data_shift(opcode, address, instruction, cp); - /* ARMv7-M: A5.3.12 Data processing (register) */ + /* ARMv7-M: A5.3.12 Data processing (register) + * and A5.3.13 Miscellaneous operations + */ else if ((opcode & 0x1f000000) == 0x1a000000) retval = t2ev_data_reg(opcode, address, instruction, cp); |
From: oharboe at B. <oh...@ma...> - 2009-07-23 17:34:09
|
Author: oharboe Date: 2009-07-23 17:34:03 +0200 (Thu, 23 Jul 2009) New Revision: 2560 Modified: trunk/src/target/arm_disassembler.c Log: David Brownell <da...@pa...> thumb2 disassembly for Load byte, memory hints Modified: trunk/src/target/arm_disassembler.c =================================================================== --- trunk/src/target/arm_disassembler.c 2009-07-23 07:04:21 UTC (rev 2559) +++ trunk/src/target/arm_disassembler.c 2009-07-23 15:34:03 UTC (rev 2560) @@ -2,6 +2,8 @@ * Copyright (C) 2006 by Dominic Rath * * Dom...@gm... * * * + * Copyright (C) 2009 by David Brownell * + * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * * the Free Software Foundation; either version 2 of the License, or * @@ -3340,6 +3342,170 @@ return ERROR_INVALID_ARGUMENTS; } +static int t2ev_load_byte_hints(uint32_t opcode, uint32_t address, + arm_instruction_t *instruction, char *cp) +{ + int rn = (opcode >> 16) & 0xf; + int rt = (opcode >> 12) & 0xf; + int op2 = (opcode >> 6) & 0x3f; + unsigned immed; + char *p1 = "]", *p2 = ""; + char *mnemonic; + + switch ((opcode >> 23) & 0x3) { + case 0: + if ((rn & rt) == 0xf) { +preload_immediate_t2: + immed = opcode & 0xfff; +preload_immediate_t1: + p1 = (opcode & (1 << 21)) ? "W" : ""; + sprintf(cp, "PLD%s\t[r%d, #%d]\t; %#6.6x", + p1, rn, immed, immed); + return ERROR_OK; + } + if (rn == 0x0f && rt != 0x0f) { +ldrb_literal: + immed = opcode & 0xfff; + address = thumb_alignpc4(address); + if (opcode & (1 << 23)) + address += immed; + else + address -= immed; + sprintf(cp, "LDRB\tr%d, %#8.8" PRIx32, + rt, address); + return ERROR_OK; + } + if (rn == 0x0f) + break; + if ((op2 & 0x3c) == 0x38) { + immed = opcode & 0xff; + sprintf(cp, "LDRBT\tr%d, [r%d, #%d]\t; %#2.2x", + rt, rn, immed, immed); + return ERROR_OK; + } + if ((op2 & 0x3c) == 0x30) { + if (rt == 0x0f) { + immed = opcode & 0xff; + goto preload_immediate_t1; + } + mnemonic = "LDRB"; +ldrxb_immediate_t3: + immed = opcode & 0xff; + if (opcode & 0x200) + immed = -immed; + + /* two indexed modes will write back rn */ + if (opcode & 0x100) { + if (opcode & 0x400) /* pre-indexed */ + p2 = "]!"; + else { /* post-indexed */ + p1 = "]"; + p2 = ""; + } + } +ldrxb_immediate_t2: + sprintf(cp, "%s\tr%d, [r%d%s, #%d%s\t; %#8.8x", + mnemonic, rt, rn, p1, + immed, p2, immed); + return ERROR_OK; + } + if ((op2 & 0x24) == 0x24) { + mnemonic = "LDRB"; + goto ldrxb_immediate_t3; + } + if (op2 == 0) { + int rm = opcode & 0xf; + + if (rt == 0x0f) + sprintf(cp, "PLD\t"); + else + sprintf(cp, "LDRB.W\tr%d, ", rt); + immed = (opcode >> 4) & 0x3; + cp = strchr(cp, 0); + sprintf(cp, "[r%d, r%d, LSL #%d]", rn, rm, immed); + return ERROR_OK; + } + break; + case 1: + if (rt == 0xf) + goto preload_immediate_t2; + if (rn == 0x0f) + goto ldrb_literal; + mnemonic = "LDRB.W"; + immed = opcode & 0xfff; + goto ldrxb_immediate_t2; + case 2: + if ((rn & rt) == 0xf) { +pli_immediate: + immed = opcode & 0xfff; + address = thumb_alignpc4(address); + if (opcode & (1 << 23)) + address += immed; + else + address -= immed; + sprintf(cp, "PLI\t%#8.8" PRIx32, address); + return ERROR_OK; + } + if (rn == 0xf && rt != 0xf) { +ldrsb_literal: + immed = opcode & 0xfff; + address = thumb_alignpc4(address); + if (opcode & (1 << 23)) + address += immed; + else + address -= immed; + sprintf(cp, "LDRSB\t%#8.8" PRIx32, address); + return ERROR_OK; + } + if (rn == 0xf) + break; + if ((op2 & 0x3c) == 0x38) { + immed = opcode & 0xff; + sprintf(cp, "LDRSBT\tr%d, [r%d, #%d]\t; %2.2x", + rt, rn, immed, immed); + return ERROR_OK; + } + if ((op2 & 0x3c) == 0x30) { + if (rt == 0xf) { + immed = opcode & 0xff; + immed = -immed; // pli + sprintf(cp, "PLI\t[r%d, #-%d]\t; %2.2x", + rn, immed, immed); + return ERROR_OK; + } + mnemonic = "LDRSB"; + goto ldrxb_immediate_t3; + } + if ((op2 & 0x24) == 0x24) { + mnemonic = "LDRSB"; + goto ldrxb_immediate_t3; + } + if (op2 == 0) { + int rm = opcode & 0xf; + + if (rt == 0x0f) + sprintf(cp, "PLI\t"); + else + sprintf(cp, "LDRSB.W\tr%d, ", rt); + immed = (opcode >> 4) & 0x3; + cp = strchr(cp, 0); + sprintf(cp, "[r%d, r%d, LSL #%d]", rn, rm, immed); + return ERROR_OK; + } + break; + case 3: + if (rt == 0xf) + goto pli_immediate; + if (rn == 0xf) + goto ldrsb_literal; + immed = opcode & 0xfff; + mnemonic = "LDRSB"; + goto ldrxb_immediate_t2; + } + + return ERROR_INVALID_ARGUMENTS; +} + /* * REVISIT for Thumb2 instructions, instruction->type and friends aren't * always set. That means eventual arm_simulate_step() support for Thumb2 @@ -3407,6 +3573,10 @@ else if ((opcode & 0x1f700000) == 0x18500000) retval = t2ev_load_word(opcode, address, instruction, cp); + /* ARMv7-M: A5.3.9 Load byte, memory hints */ + else if ((opcode & 0x1e700000) == 0x18100000) + retval = t2ev_load_byte_hints(opcode, address, instruction, cp); + /* ARMv7-M: A5.3.10 Store single data item */ else if ((opcode & 0x1f100000) == 0x18000000) retval = t2ev_store_single(opcode, address, instruction, cp); |
From: oharboe at B. <oh...@ma...> - 2009-07-23 09:04:26
|
Author: oharboe Date: 2009-07-23 09:04:21 +0200 (Thu, 23 Jul 2009) New Revision: 2559 Modified: trunk/src/jtag/amt_jtagaccel.c trunk/src/jtag/bitbang.c trunk/src/target/arm_adi_v5.c Log: Ferdinand Postema <fer...@po...> fix cygwin warnings Modified: trunk/src/jtag/amt_jtagaccel.c =================================================================== --- trunk/src/jtag/amt_jtagaccel.c 2009-07-23 07:02:43 UTC (rev 2558) +++ trunk/src/jtag/amt_jtagaccel.c 2009-07-23 07:04:21 UTC (rev 2559) @@ -374,7 +374,7 @@ break; case JTAG_SLEEP: #ifdef _DEBUG_JTAG_IO_ - LOG_DEBUG("sleep %i", cmd->cmd.sleep->us); + LOG_DEBUG("sleep %" PRIi32, cmd->cmd.sleep->us); #endif jtag_sleep(cmd->cmd.sleep->us); break; Modified: trunk/src/jtag/bitbang.c =================================================================== --- trunk/src/jtag/bitbang.c 2009-07-23 07:02:43 UTC (rev 2558) +++ trunk/src/jtag/bitbang.c 2009-07-23 07:04:21 UTC (rev 2559) @@ -308,7 +308,7 @@ break; case JTAG_SLEEP: #ifdef _DEBUG_JTAG_IO_ - LOG_DEBUG("sleep %i", cmd->cmd.sleep->us); + LOG_DEBUG("sleep %" PRIi32, cmd->cmd.sleep->us); #endif jtag_sleep(cmd->cmd.sleep->us); break; Modified: trunk/src/target/arm_adi_v5.c =================================================================== --- trunk/src/target/arm_adi_v5.c 2009-07-23 07:02:43 UTC (rev 2558) +++ trunk/src/target/arm_adi_v5.c 2009-07-23 07:04:21 UTC (rev 2559) @@ -1144,7 +1144,7 @@ dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr); retval = swjdp_transaction_endcheck(swjdp); - command_print(cmd_ctx, "0x%8.8x", baseaddr); + command_print(cmd_ctx, "0x%8.8" PRIx32, baseaddr); if (apselsave != apsel) dap_ap_select(swjdp, apselsave); @@ -1162,7 +1162,7 @@ memaccess_tck = strtoul(args[0], NULL, 0); swjdp->memaccess_tck = memaccess_tck; - command_print(cmd_ctx, "memory bus access delay set to %i tck", + command_print(cmd_ctx, "memory bus access delay set to %" PRIi32 " tck", swjdp->memaccess_tck); return ERROR_OK; @@ -1181,7 +1181,7 @@ dap_ap_select(swjdp, apsel); dap_ap_read_reg_u32(swjdp, 0xFC, &apid); retval = swjdp_transaction_endcheck(swjdp); - command_print(cmd_ctx, "ap %i selected, identification register 0x%8.8x", + command_print(cmd_ctx, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32, apsel, apid); return retval; @@ -1203,7 +1203,7 @@ dap_ap_read_reg_u32(swjdp, 0xFC, &apid); retval = swjdp_transaction_endcheck(swjdp); - command_print(cmd_ctx, "0x%8.8x", apid); + command_print(cmd_ctx, "0x%8.8" PRIx32, apid); if (apselsave != apsel) dap_ap_select(swjdp, apselsave); |
From: oharboe at B. <oh...@ma...> - 2009-07-23 09:02:50
|
Author: oharboe Date: 2009-07-23 09:02:43 +0200 (Thu, 23 Jul 2009) New Revision: 2558 Modified: trunk/src/target/arm_disassembler.c Log: David Brownell <da...@pa...> fix warnings Modified: trunk/src/target/arm_disassembler.c =================================================================== --- trunk/src/target/arm_disassembler.c 2009-07-22 19:35:23 UTC (rev 2557) +++ trunk/src/target/arm_disassembler.c 2009-07-23 07:02:43 UTC (rev 2558) @@ -1710,7 +1710,7 @@ snprintf(instruction->text, 128, "0x%8.8" PRIx32 " 0x%4.4x \t" - "LDR\tr%i, [pc, #%#" PRIx32 "]\t; %#8.8x", + "LDR\tr%i, [pc, #%#" PRIx32 "]\t; %#8.8" PRIx32, address, opcode, Rd, immediate, thumb_alignpc4(address) + immediate); @@ -2452,7 +2452,7 @@ } if (opcode & 0x00f0) { - sprintf(cp, "DBG\t#%d", opcode & 0xf); + sprintf(cp, "DBG\t#%d", (int) opcode & 0xf); return ERROR_OK; } @@ -2533,7 +2533,7 @@ case 0x38: case 0x39: sprintf(cp, "MSR\t%s, r%d", special_name(opcode & 0xff), - (opcode >> 16) & 0x0f); + (int) (opcode >> 16) & 0x0f); return ERROR_OK; case 0x3a: return t2ev_hint(opcode, address, instruction, cp); @@ -2541,7 +2541,7 @@ return t2ev_misc(opcode, address, instruction, cp); case 0x3e: case 0x3f: - sprintf(cp, "MRS\tr%d, %s", (opcode >> 8) & 0x0f, + sprintf(cp, "MRS\tr%d, %s", (int) (opcode >> 8) & 0x0f, special_name(opcode & 0xff)); return ERROR_OK; } @@ -2741,7 +2741,7 @@ immed |= (opcode >> 10) & 0x1c; sprintf(cp, "%sSAT\tr%d, #%d, r%d, %s #%d\t", is_signed ? "S" : "U", - rd, (opcode & 0x1f) + 1, rn, + rd, (int) (opcode & 0x1f) + 1, rn, (opcode & (1 << 21)) ? "ASR" : "LSL", immed ? immed : 32); return ERROR_OK; @@ -2755,7 +2755,7 @@ sprintf(cp, "%sBFX\tr%d, r%d, #%d, #%d\t", is_signed ? "S" : "U", rd, rn, immed, - (opcode & 0x1f) + 1); + (int) (opcode & 0x1f) + 1); return ERROR_OK; case 0x16: immed = (opcode >> 6) & 0x03; @@ -2763,11 +2763,11 @@ if (rn == 0xf) /* bitfield clear */ sprintf(cp, "BFC\tr%d, #%d, #%d\t", rd, immed, - (opcode & 0x1f) + 1 - immed); + (int) (opcode & 0x1f) + 1 - immed); else /* bitfield insert */ sprintf(cp, "BFI\tr%d, r%d, #%d, #%d\t", rd, rn, immed, - (opcode & 0x1f) + 1 - immed); + (int) (opcode & 0x1f) + 1 - immed); return ERROR_OK; default: return ERROR_INVALID_ARGUMENTS; @@ -2844,8 +2844,8 @@ } sprintf(cp, "STR%s.W\tr%d, [r%d, r%d, LSL #%d]", - size, rt, rn, opcode & 0x0f, - (opcode >> 4) & 0x03); + size, rt, rn, (int) opcode & 0x0f, + (int) (opcode >> 4) & 0x03); imm12: immed = opcode & 0x0fff; @@ -2887,22 +2887,24 @@ { int ra = (opcode >> 12) & 0xf; - switch (opcode & 0x007000f0) { case 0: if (ra == 0xf) sprintf(cp, "MUL\tr%d, r%d, r%d", - (opcode >> 8) & 0xf, (opcode >> 16) & 0xf, - (opcode >> 0) & 0xf); + (int) (opcode >> 8) & 0xf, + (int) (opcode >> 16) & 0xf, + (int) (opcode >> 0) & 0xf); else sprintf(cp, "MLA\tr%d, r%d, r%d, r%d", - (opcode >> 8) & 0xf, (opcode >> 16) & 0xf, - (opcode >> 0) & 0xf, ra); + (int) (opcode >> 8) & 0xf, + (int) (opcode >> 16) & 0xf, + (int) (opcode >> 0) & 0xf, ra); break; case 0x10: sprintf(cp, "MLS\tr%d, r%d, r%d, r%d", - (opcode >> 8) & 0xf, (opcode >> 16) & 0xf, - (opcode >> 0) & 0xf, ra); + (int) (opcode >> 8) & 0xf, + (int) (opcode >> 16) & 0xf, + (int) (opcode >> 0) & 0xf, ra); break; default: return ERROR_INVALID_ARGUMENTS; @@ -2927,18 +2929,18 @@ sprintf(cp, "%c%sL\tr%d, r%d, r%d, r%d", (op & 0x20) ? 'U' : 'S', infix, - (opcode >> 12) & 0xf, - (opcode >> 8) & 0xf, - (opcode >> 16) & 0xf, - (opcode >> 0) & 0xf); + (int) (opcode >> 12) & 0xf, + (int) (opcode >> 8) & 0xf, + (int) (opcode >> 16) & 0xf, + (int) (opcode >> 0) & 0xf); break; case 0x1f: case 0x3f: sprintf(cp, "%cDIV\tr%d, r%d, r%d", (op & 0x20) ? 'U' : 'S', - (opcode >> 8) & 0xf, - (opcode >> 16) & 0xf, - (opcode >> 0) & 0xf); + (int) (opcode >> 8) & 0xf, + (int) (opcode >> 16) & 0xf, + (int) (opcode >> 0) & 0xf); break; default: return ERROR_INVALID_ARGUMENTS; @@ -3034,7 +3036,8 @@ case 0: if (immed == 0) { sprintf(cp, "MOV%s.W\tr%d, r%d", - suffix, rd, (opcode & 0xf)); + suffix, rd, + (int) (opcode & 0xf)); return ERROR_OK; } mnemonic = "LSL"; @@ -3048,7 +3051,8 @@ default: if (immed == 0) { sprintf(cp, "RRX%s.W\tr%d, r%d", - suffix, rd, (opcode & 0xf)); + suffix, rd, + (int) (opcode & 0xf)); return ERROR_OK; } mnemonic = "ROR"; @@ -3121,7 +3125,7 @@ } sprintf(cp, "%s%s.W\tr%d, r%d, r%d", - mnemonic, suffix, rd, rn, (opcode & 0xf)); + mnemonic, suffix, rd, rn, (int) (opcode & 0xf)); shift: cp = strchr(cp, 0); @@ -3151,12 +3155,13 @@ two: sprintf(cp, "%s%s.W\tr%d, r%d", - mnemonic, suffix, rn, (opcode & 0xf)); + mnemonic, suffix, rn, (int) (opcode & 0xf)); goto shift; immediate: sprintf(cp, "%s%s.W\tr%d, r%d, #%d", - mnemonic, suffix, rd, (opcode & 0xf), immed ? immed : 32); + mnemonic, suffix, rd, + (int) (opcode & 0xf), immed ? immed : 32); return ERROR_OK; } @@ -3189,9 +3194,9 @@ suffix = "S"; sprintf(cp, "%s%s.W\tr%d, r%d, r%d", mnemonic, suffix, - (opcode >> 8) & 0xf, - (opcode >> 16) & 0xf, - (opcode >> 0) & 0xf); + (int) (opcode >> 8) & 0xf, + (int) (opcode >> 16) & 0xf, + (int) (opcode >> 0) & 0xf); } else if (opcode & (1 << 7)) { switch ((opcode >> 24) & 0xf) { @@ -3213,8 +3218,8 @@ sprintf(cp, "%cXT%c.W\tr%d, r%d%s", (opcode & (1 << 24)) ? 'U' : 'S', (opcode & (1 << 26)) ? 'B' : 'H', - (opcode >> 8) & 0xf, - (opcode >> 16) & 0xf, + (int) (opcode >> 8) & 0xf, + (int) (opcode >> 16) & 0xf, suffix); break; case 8: @@ -3250,8 +3255,8 @@ } sprintf(cp, "%s\tr%d, r%d", mnemonic, - (opcode >> 8) & 0xf, - (opcode >> 0) & 0xf); + (int) (opcode >> 8) & 0xf, + (int) (opcode >> 0) & 0xf); break; default: return ERROR_INVALID_ARGUMENTS; @@ -3274,7 +3279,7 @@ if (opcode & (1 << 23)) immed = -immed; sprintf(cp, "LDR\tr%d, %#8.8" PRIx32, - (opcode >> 12) & 0xf, + (int) (opcode >> 12) & 0xf, thumb_alignpc4(address) + immed); return ERROR_OK; } @@ -3282,17 +3287,17 @@ if (opcode & (1 << 23)) { immed = opcode & 0x0fff; sprintf(cp, "LDR.W\tr%d, [r%d, #%d]\t; %#3.3x", - (opcode >> 12) & 0xf, + (int) (opcode >> 12) & 0xf, rn, immed, immed); return ERROR_OK; } if (!(opcode & (0x3f << 6))) { sprintf(cp, "LDR.W\tr%d, [r%d, r%d, LSL #%d]", - (opcode >> 12) & 0xf, + (int) (opcode >> 12) & 0xf, rn, - (opcode >> 0) & 0xf, - (opcode >> 4) & 0x3); + (int) (opcode >> 0) & 0xf, + (int) (opcode >> 4) & 0x3); return ERROR_OK; } @@ -3301,7 +3306,7 @@ immed = opcode & 0x00ff; sprintf(cp, "LDRT\tr%d, [r%d, #%d]\t; %#2.2x", - (opcode >> 12) & 0xf, + (int) (opcode >> 12) & 0xf, rn, immed, immed); return ERROR_OK; } @@ -3325,7 +3330,7 @@ } sprintf(cp, "LDR\tr%d, [r%d%s, #%s%u%s\t; %#2.2x", - (opcode >> 12) & 0xf, + (int) (opcode >> 12) & 0xf, rn, p1, (opcode & 0x200) ? "" : "-", immed, p2, immed); @@ -3433,7 +3438,8 @@ return ERROR_OK; } - LOG_DEBUG("Can't decode 32-bit Thumb2 yet (opcode=%08x)", opcode); + LOG_DEBUG("Can't decode 32-bit Thumb2 yet (opcode=%08" PRIx32 ")", + opcode); strcpy(cp, "(32-bit Thumb2 ...)"); return ERROR_OK; |
From: oharboe at B. <oh...@ma...> - 2009-07-22 21:35:23
|
Author: oharboe Date: 2009-07-22 21:35:23 +0200 (Wed, 22 Jul 2009) New Revision: 2557 Modified: trunk/tcl/board/crossbow_tech_imote2.cfg Log: Jonathan Cameron <ji...@ca...> fix regression from 1836 when the reset_config command was removed from pxa270.cfg Modified: trunk/tcl/board/crossbow_tech_imote2.cfg =================================================================== --- trunk/tcl/board/crossbow_tech_imote2.cfg 2009-07-22 14:25:56 UTC (rev 2556) +++ trunk/tcl/board/crossbow_tech_imote2.cfg 2009-07-22 19:35:23 UTC (rev 2557) @@ -6,5 +6,7 @@ # longer-than-normal reset delay jtag_nsrst_delay 800 +reset_config trst_and_srst separate + # works for P30 flash flash bank cfi 0x00000000 0x2000000 2 2 $_TARGETNAME |
From: oharboe at B. <oh...@ma...> - 2009-07-22 16:25:57
|
Author: oharboe Date: 2009-07-22 16:25:56 +0200 (Wed, 22 Jul 2009) New Revision: 2556 Added: trunk/tcl/target/samsung_s3c2450.cfg Log: Stefano Voulaz <s.v...@pr...> first cut samsung_s3c2450 Added: trunk/tcl/target/samsung_s3c2450.cfg =================================================================== --- trunk/tcl/target/samsung_s3c2450.cfg 2009-07-21 20:19:02 UTC (rev 2555) +++ trunk/tcl/target/samsung_s3c2450.cfg 2009-07-22 14:25:56 UTC (rev 2556) @@ -0,0 +1,49 @@ +# Target configuration for the Samsung 2450 system on chip +# Processor : ARM926ejs (wb) rev 0 (v4l) +# Info: JTAG tap: s3c2450.cpu tap/device found: 0x07926F0F + + +# FIX!!! what to use here? +# +# RCLK? +# +# jtag_khz 0 +# +# Really low clock during reset? +# +# jtag_khz 1 + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME s3c2450 +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + # this defaults to a bigendian + set _ENDIAN little +} + +if { [info exists CPUTAPID ] } { + set _CPUTAPID $CPUTAPID +} else { + # force an error till we get a good number + set _CPUTAPID 0x07926f0f +} + +#jtag scan chain +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xE -irmask 0x0f -expected-id $_CPUTAPID + +set _TARGETNAME [format "%s.cpu" $_CHIPNAME] +target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs + +# FIX!!!!! should this really use srst_pulls_trst? +# With srst_pulls_trst "reset halt" will not reset into the +# halted mode, but rather "reset run" and then halt the target. +# +# However, without "srst_pulls_trst", then "reset halt" produces weird +# errors: +# WARNING: unknown debug reason: 0x0 +reset_config trst_and_srst \ No newline at end of file Property changes on: trunk/tcl/target/samsung_s3c2450.cfg ___________________________________________________________________ Name: svn:eol-style + native |
From: ntfreak at B. <nt...@ma...> - 2009-07-21 22:19:03
|
Author: ntfreak Date: 2009-07-21 22:19:02 +0200 (Tue, 21 Jul 2009) New Revision: 2555 Modified: trunk/src/target/armv7m.c Log: David Brownell <da...@pa...>: Dump SP on poll, and show whether it's MSP or PSP. Thread mode can use either stack pointer, so this is part of the state that's not yet displayed. Shrink some lines. Modified: trunk/src/target/armv7m.c =================================================================== --- trunk/src/target/armv7m.c 2009-07-21 20:15:11 UTC (rev 2554) +++ trunk/src/target/armv7m.c 2009-07-21 20:19:02 UTC (rev 2555) @@ -478,14 +478,21 @@ { /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; + uint32_t ctrl, sp; + ctrl = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 32); + sp = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_R13].value, 0, 32); + LOG_USER("target halted due to %s, current mode: %s %s\n" - "xPSR: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32, - Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name, + "xPSR: %#8.8" PRIx32 " pc: %#8.8" PRIx32 " %csp: %#8.8" PRIx32, + Jim_Nvp_value2name_simple(nvp_target_debug_reason, + target->debug_reason)->name, armv7m_mode_strings[armv7m->core_mode], armv7m_exception_string(armv7m->exception_number), buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32), - buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32)); + buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32), + (ctrl & 0x02) ? 'p' : 'm', + sp); return ERROR_OK; } |
From: ntfreak at B. <nt...@ma...> - 2009-07-21 22:15:12
|
Author: ntfreak Date: 2009-07-21 22:15:11 +0200 (Tue, 21 Jul 2009) New Revision: 2554 Modified: trunk/src/target/armv7m.c trunk/src/target/armv7m.h trunk/src/target/cortex_m3.c Log: David Brownell <da...@pa...>: Clean up treatment of registers in ARMv7-M and Cortex-M3. - At the arch level: * Just list registers and names; don't impose core-specific policy about how they are accessed. * Each register has a symbol. * Remove the register mode field (irrelevant to debugger) - At the core/implementation level: * Just map the registers to their relevant access methods; don't require the arch level to say how that should work (cores other than Cortex-M3 could do it differently). * Don't use undefined bits from register 20. * Use register IDs that are part of the ARMv7-M interface. In short, there's now a real distinction between the arch and core layers. Modified: trunk/src/target/armv7m.c =================================================================== --- trunk/src/target/armv7m.c 2009-07-21 20:05:05 UTC (rev 2553) +++ trunk/src/target/armv7m.c 2009-07-21 20:15:11 UTC (rev 2554) @@ -36,7 +36,9 @@ #include "armv7m.h" +#define ARRAY_SIZE(x) ((int)(sizeof(x)/sizeof((x)[0]))) + #if 0 #define _DEBUG_INSTRUCTION_EXECUTION_ #endif @@ -46,7 +48,7 @@ "Thread", "Thread (User)", "Handler", }; -char* armv7m_exception_strings[] = +static char *armv7m_exception_strings[] = { "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", @@ -54,16 +56,6 @@ "DebugMonitor", "RESERVED", "PendSV", "SysTick" }; -char* armv7m_core_reg_list[] = -{ - /* Registers accessed through core debug */ - "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", - "sp", "lr", "pc", - "xPSR", "msp", "psp", - /* Registers accessed through special reg 20 */ - "primask", "basepri", "faultmask", "control" -}; - uint8_t armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; reg_t armv7m_gdb_dummy_fp_reg = @@ -87,37 +79,47 @@ }; #endif -armv7m_core_reg_t armv7m_core_reg_list_arch_info[] = -{ - /* CORE_GP are accesible using the core debug registers */ - {0, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {1, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {2, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {3, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {4, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {5, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {6, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {7, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {8, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {9, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {10, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {11, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {12, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {13, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {14, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, - {15, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, +/* + * These registers are not memory-mapped. The ARMv7-M profile includes + * memory mapped registers too, such as for the NVIC (interrupt controller) + * and SysTick (timer) modules; those can mostly be treated as peripherals. + */ +static const struct { + unsigned id; + char *name; +} armv7m_regs[] = { + { ARMV7M_R0, "r0" }, + { ARMV7M_R1, "r1" }, + { ARMV7M_R2, "r2" }, + { ARMV7M_R3, "r3" }, - {16, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* xPSR */ - {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */ - {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */ + { ARMV7M_R4, "r4" }, + { ARMV7M_R5, "r5" }, + { ARMV7M_R6, "r6" }, + { ARMV7M_R7, "r7" }, - /* CORE_SP are accesible using coreregister 20 */ - {19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */ - {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */ - {21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */ - {22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL} /* CONTROL */ + { ARMV7M_R8, "r8" }, + { ARMV7M_R9, "r9" }, + { ARMV7M_R10, "r10" }, + { ARMV7M_R11, "r11" }, + + { ARMV7M_R12, "r12" }, + { ARMV7M_R13, "sp" }, + { ARMV7M_R14, "lr" }, + { ARMV7M_PC, "pc" }, + + { ARMV7M_xPSR, "xPSR" }, + { ARMV7M_MSP, "msp" }, + { ARMV7M_PSP, "psp" }, + + { ARMV7M_PRIMASK, "primask" }, + { ARMV7M_BASEPRI, "basepri" }, + { ARMV7M_FAULTMASK, "faultmask" }, + { ARMV7M_CONTROL, "control" }, }; +#define ARMV7M_NUM_REGS ARRAY_SIZE(armv7m_regs) + int armv7m_core_reg_arch_type = -1; int armv7m_dummy_core_reg_arch_type = -1; @@ -133,7 +135,7 @@ if (armv7m->pre_restore_context) armv7m->pre_restore_context(target); - for (i = ARMV7NUMCOREREGS-1; i >= 0; i--) + for (i = ARMV7M_NUM_REGS - 1; i >= 0; i--) { if (armv7m->core_cache->reg_list[i].dirty) { @@ -204,7 +206,7 @@ /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; - if ((num < 0) || (num >= ARMV7NUMCOREREGS)) + if ((num < 0) || (num >= ARMV7M_NUM_REGS)) return ERROR_INVALID_ARGUMENTS; armv7m_core_reg = armv7m->core_cache->reg_list[num].arch_info; @@ -225,7 +227,7 @@ /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; - if ((num < 0) || (num >= ARMV7NUMCOREREGS)) + if ((num < 0) || (num >= ARMV7M_NUM_REGS)) return ERROR_INVALID_ARGUMENTS; reg_value = buf_get_u32(armv7m->core_cache->reg_list[num].value, 0, 32); @@ -268,6 +270,13 @@ *reg_list_size = 26; *reg_list = malloc(sizeof(reg_t*) * (*reg_list_size)); + /* + * GDB register packet format for ARM: + * - the first 16 registers are r0..r15 + * - (obsolete) 8 FPA registers + * - (obsolete) FPA status + * - CPSR + */ for (i = 0; i < 16; i++) { (*reg_list)[i] = &armv7m->core_cache->reg_list[i]; @@ -337,7 +346,7 @@ enum armv7m_mode core_mode = armv7m->core_mode; int retval = ERROR_OK; int i; - uint32_t context[ARMV7NUMCOREREGS]; + uint32_t context[ARMV7M_NUM_REGS]; if (armv7m_algorithm_info->common_magic != ARMV7M_COMMON_MAGIC) { @@ -353,7 +362,7 @@ /* refresh core register cache */ /* Not needed if core register cache is always consistent with target process state */ - for (i = 0; i < ARMV7NUMCOREREGS; i++) + for (i = 0; i < ARMV7M_NUM_REGS; i++) { if (!armv7m->core_cache->reg_list[i].valid) armv7m->read_core_reg(target, i); @@ -390,7 +399,8 @@ if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY) { LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode); - buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode); + buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, + 0, 1, armv7m_algorithm_info->core_mode); armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1; armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1; } @@ -444,14 +454,16 @@ } } - for (i = ARMV7NUMCOREREGS-1; i >= 0; i--) + for (i = ARMV7M_NUM_REGS; i >= 0; i--) { uint32_t regvalue; regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32); if (regvalue != context[i]) { - LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", armv7m->core_cache->reg_list[i].name, context[i]); - buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]); + LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32, + armv7m->core_cache->reg_list[i].name, context[i]); + buf_set_u32(armv7m->core_cache->reg_list[i].value, + 0, 32, context[i]); armv7m->core_cache->reg_list[i].valid = 1; armv7m->core_cache->reg_list[i].dirty = 1; } @@ -467,12 +479,13 @@ /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; - LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "", + LOG_USER("target halted due to %s, current mode: %s %s\n" + "xPSR: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32, Jim_Nvp_value2name_simple(nvp_target_debug_reason,target->debug_reason)->name, armv7m_mode_strings[armv7m->core_mode], armv7m_exception_string(armv7m->exception_number), buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32), - buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32)); + buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_PC].value, 0, 32)); return ERROR_OK; } @@ -482,11 +495,11 @@ /* get pointers to arch-specific information */ armv7m_common_t *armv7m = target->arch_info; - int num_regs = ARMV7NUMCOREREGS; + int num_regs = ARMV7M_NUM_REGS; reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache); reg_cache_t *cache = malloc(sizeof(reg_cache_t)); - reg_t *reg_list = malloc(sizeof(reg_t) * num_regs); - armv7m_core_reg_t *arch_info = malloc(sizeof(armv7m_core_reg_t) * num_regs); + reg_t *reg_list = calloc(num_regs, sizeof(reg_t)); + armv7m_core_reg_t *arch_info = calloc(num_regs, sizeof(armv7m_core_reg_t)); int i; if (armv7m_core_reg_arch_type == -1) @@ -510,10 +523,10 @@ for (i = 0; i < num_regs; i++) { - arch_info[i] = armv7m_core_reg_list_arch_info[i]; + arch_info[i].num = armv7m_regs[i].id; arch_info[i].target = target; arch_info[i].armv7m_common = armv7m; - reg_list[i].name = armv7m_core_reg_list[i]; + reg_list[i].name = armv7m_regs[i].name; reg_list[i].size = 32; reg_list[i].value = calloc(1, 4); reg_list[i].dirty = 0; Modified: trunk/src/target/armv7m.h =================================================================== --- trunk/src/target/armv7m.h 2009-07-21 20:05:05 UTC (rev 2553) +++ trunk/src/target/armv7m.h 2009-07-21 20:15:11 UTC (rev 2554) @@ -50,22 +50,43 @@ ARMV7M_REGISTER_MEMMAP }; -extern char* armv7m_exception_strings[]; - extern char *armv7m_exception_string(int number); /* offsets into armv7m core register cache */ enum { + /* for convenience, the first set of indices match + * the Cortex-M3 DCRSR selectors + */ + ARMV7M_R0, + ARMV7M_R1, + ARMV7M_R2, + ARMV7M_R3, + + ARMV7M_R4, + ARMV7M_R5, + ARMV7M_R6, + ARMV7M_R7, + + ARMV7M_R8, + ARMV7M_R9, + ARMV7M_R10, + ARMV7M_R11, + + ARMV7M_R12, + ARMV7M_R13, + ARMV7M_R14, ARMV7M_PC = 15, + ARMV7M_xPSR = 16, ARMV7M_MSP, ARMV7M_PSP, + + /* this next set of indices is arbitrary */ ARMV7M_PRIMASK, ARMV7M_BASEPRI, ARMV7M_FAULTMASK, ARMV7M_CONTROL, - ARMV7NUMCOREREGS }; #define ARMV7M_COMMON_MAGIC 0x2A452A45 @@ -107,7 +128,6 @@ { uint32_t num; enum armv7m_regtype type; - enum armv7m_mode mode; target_t *target; armv7m_common_t *armv7m_common; } armv7m_core_reg_t; Modified: trunk/src/target/cortex_m3.c =================================================================== --- trunk/src/target/cortex_m3.c 2009-07-21 20:05:05 UTC (rev 2553) +++ trunk/src/target/cortex_m3.c 2009-07-21 20:15:11 UTC (rev 2554) @@ -395,7 +395,9 @@ /* Examine target state and mode */ /* First load register acessible through core debug port*/ - for (i = 0; i < ARMV7M_PRIMASK; i++) + int num_regs = armv7m->core_cache->num_regs; + + for (i = 0; i < num_regs; i++) { if (!armv7m->core_cache->reg_list[i].valid) armv7m->read_core_reg(target, i); @@ -418,13 +420,6 @@ cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff); } - /* Now we can load SP core registers */ - for (i = ARMV7M_PRIMASK; i < ARMV7NUMCOREREGS; i++) - { - if (!armv7m->core_cache->reg_list[i].valid) - armv7m->read_core_reg(target, i); - } - /* Are we in an exception handler */ if (xPSR & 0x1FF) { @@ -1253,8 +1248,12 @@ armv7m_common_t *armv7m = target->arch_info; swjdp_common_t *swjdp = &armv7m->swjdp_info; - if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP)) - { + /* NOTE: we "know" here that the register identifiers used + * in the v7m header match the Cortex-M3 Debug Core Register + * Selector values for R0..R15, xPSR, MSP, and PSP. + */ + switch (num) { + case 0 ... 18: /* read a normal core register */ retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num); @@ -1264,35 +1263,41 @@ return ERROR_JTAG_DEVICE_ERROR; } LOG_DEBUG("load from core reg %i value 0x%" PRIx32 "",(int)num,*value); - } - else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */ - { - /* read other registers */ + break; + + case ARMV7M_PRIMASK: + case ARMV7M_BASEPRI: + case ARMV7M_FAULTMASK: + case ARMV7M_CONTROL: + /* Cortex-M3 packages these four registers as bitfields + * in one Debug Core register. So say r0 and r2 docs; + * it was removed from r1 docs, but still works. + */ cortexm3_dap_read_coreregister_u32(swjdp, value, 20); switch (num) { - case 19: - *value = buf_get_u32((uint8_t*)value, 0, 8); + case ARMV7M_PRIMASK: + *value = buf_get_u32((uint8_t*)value, 0, 1); break; - case 20: + case ARMV7M_BASEPRI: *value = buf_get_u32((uint8_t*)value, 8, 8); break; - case 21: - *value = buf_get_u32((uint8_t*)value, 16, 8); + case ARMV7M_FAULTMASK: + *value = buf_get_u32((uint8_t*)value, 16, 1); break; - case 22: - *value = buf_get_u32((uint8_t*)value, 24, 8); + case ARMV7M_CONTROL: + *value = buf_get_u32((uint8_t*)value, 24, 2); break; } LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value); - } - else - { + break; + + default: return ERROR_INVALID_ARGUMENTS; } @@ -1313,14 +1318,19 @@ * in "thumb" mode, or an INVSTATE exception will occur. This is a * hack to deal with the fact that gdb will sometimes "forge" * return addresses, and doesn't set the LSB correctly (i.e., when - * printing expressions containing function calls, it sets LR = 0.) */ - - if (num == 14) + * printing expressions containing function calls, it sets LR = 0.) + * Valid exception return codes have bit 0 set too. + */ + if (num == ARMV7M_R14) value |= 0x01; #endif - if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP)) - { + /* NOTE: we "know" here that the register identifiers used + * in the v7m header match the Cortex-M3 Debug Core Register + * Selector values for R0..R15, xPSR, MSP, and PSP. + */ + switch (num) { + case 0 ... 18: retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num); if (retval != ERROR_OK) { @@ -1329,38 +1339,43 @@ return ERROR_JTAG_DEVICE_ERROR; } LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value); - } - else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */ - { - /* write other registers */ + break; + case ARMV7M_PRIMASK: + case ARMV7M_BASEPRI: + case ARMV7M_FAULTMASK: + case ARMV7M_CONTROL: + /* Cortex-M3 packages these four registers as bitfields + * in one Debug Core register. So say r0 and r2 docs; + * it was removed from r1 docs, but still works. + */ cortexm3_dap_read_coreregister_u32(swjdp, ®, 20); switch (num) { - case 19: - buf_set_u32((uint8_t*)®, 0, 8, value); + case ARMV7M_PRIMASK: + buf_set_u32((uint8_t*)®, 0, 1, value); break; - case 20: + case ARMV7M_BASEPRI: buf_set_u32((uint8_t*)®, 8, 8, value); break; - case 21: - buf_set_u32((uint8_t*)®, 16, 8, value); + case ARMV7M_FAULTMASK: + buf_set_u32((uint8_t*)®, 16, 1, value); break; - case 22: - buf_set_u32((uint8_t*)®, 24, 8, value); + case ARMV7M_CONTROL: + buf_set_u32((uint8_t*)®, 24, 2, value); break; } cortexm3_dap_write_coreregister_u32(swjdp, reg, 20); LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value); - } - else - { + break; + + default: return ERROR_INVALID_ARGUMENTS; } |
From: ntfreak at B. <nt...@ma...> - 2009-07-21 22:05:06
|
Author: ntfreak Date: 2009-07-21 22:05:05 +0200 (Tue, 21 Jul 2009) New Revision: 2553 Modified: trunk/src/target/arm_disassembler.c Log: David Brownell <da...@pa...>: Minor updates to the Thumb2 disassembly: - Bugfixes: * Distinguish branch from misc via "!=" not "==" * MRS register shift is 8 bits (vs MSR being 16) - Format tweaks: * CPS needed tab (not space) * add commma before some shifts * add space after comma in LDM/STM * use ".W" width spec on various instructions Modified: trunk/src/target/arm_disassembler.c =================================================================== --- trunk/src/target/arm_disassembler.c 2009-07-21 20:03:17 UTC (rev 2552) +++ trunk/src/target/arm_disassembler.c 2009-07-21 20:05:05 UTC (rev 2553) @@ -2080,7 +2080,7 @@ (opcode & 0x80) ? "BE" : "LE"); else /* ASSUME (opcode & 0x0fe0) == 0x0660 */ snprintf(instruction->text, 128, - "0x%8.8" PRIx32 " 0x%4.4x \tCPSI%c %s%s%s", + "0x%8.8" PRIx32 " 0x%4.4x \tCPSI%c\t%s%s%s", address, opcode, (opcode & 0x0010) ? 'D' : 'E', (opcode & 0x0004) ? "A" : "", @@ -2522,7 +2522,7 @@ case 0x4: goto undef; case 0: - if (((opcode >> 23) & 0x07) == 0x07) + if (((opcode >> 23) & 0x07) != 0x07) return t2ev_cond_b(opcode, address, instruction, cp); if (opcode & (1 << 26)) goto undef; @@ -2541,7 +2541,7 @@ return t2ev_misc(opcode, address, instruction, cp); case 0x3e: case 0x3f: - sprintf(cp, "MRS\tr%d, %s", (opcode >> 16) & 0x0f, + sprintf(cp, "MRS\tr%d, %s", (opcode >> 8) & 0x0f, special_name(opcode & 0xff)); return ERROR_OK; } @@ -2560,6 +2560,7 @@ unsigned func; bool one = false; char *suffix = ""; + char *suffix2 = ""; /* ARMv7-M: A5.3.2 Modified immediate constants */ func = (opcode >> 11) & 0x0e; @@ -2597,6 +2598,7 @@ mnemonic = "TST"; one = true; suffix = ""; + suffix2 = ".W"; rd = rn; } else { instruction->type = ARM_AND; @@ -2612,6 +2614,7 @@ instruction->type = ARM_MOV; mnemonic = "MOV"; one = true; + suffix2 = ".W"; } else { instruction->type = ARM_ORR; mnemonic = "ORR"; @@ -2649,6 +2652,7 @@ } else { instruction->type = ARM_ADD; mnemonic = "ADD"; + suffix2 = ".W"; } break; case 10: @@ -2670,21 +2674,24 @@ instruction->type = ARM_SUB; mnemonic = "SUB"; } + suffix2 = ".W"; break; case 14: instruction->type = ARM_RSB; mnemonic = "RSB"; + suffix2 = ".W"; break; default: return ERROR_INVALID_ARGUMENTS; } if (one) - sprintf(cp, "%s\tr%d, #%d\t; %#8.8x", - mnemonic, rd, immed, immed); + sprintf(cp, "%s%s\tr%d, #%d\t; %#8.8x", + mnemonic, suffix2 ,rd, immed, immed); else - sprintf(cp, "%s%s\tr%d, r%d, #%d\t; %#8.8x", - mnemonic, suffix, rd, rn, immed, immed); + sprintf(cp, "%s%s%s\tr%d, r%d, #%d\t; %#8.8x", + mnemonic, suffix, suffix2, + rd, rn, immed, immed); return ERROR_OK; } @@ -2959,13 +2966,13 @@ if (rn == 13 && t) sprintf(cp, "POP\t"); else - sprintf(cp, "LDM\tr%d%s, ", rn, t ? "!" : ""); + sprintf(cp, "LDM.W\tr%d%s, ", rn, t ? "!" : ""); break; case 4: if (rn == 13 && t) sprintf(cp, "PUSH\t"); else - sprintf(cp, "STM\tr%d%s, ", rn, t ? "!" : ""); + sprintf(cp, "STM.W\tr%d%s, ", rn, t ? "!" : ""); break; case 5: sprintf(cp, "LDMB\tr%d%s, ", rn, t ? "!" : ""); @@ -2980,7 +2987,7 @@ if ((registers & 1) == 0) continue; registers &= ~1; - sprintf(cp, "r%d%s", t, registers ? "," : ""); + sprintf(cp, "r%d%s", t, registers ? ", " : ""); cp = strchr(cp, 0); } *cp++ = '}'; @@ -3139,7 +3146,7 @@ suffix = "ROR"; break; } - sprintf(cp, " %s #%d", suffix, immed ? immed : 32); + sprintf(cp, ", %s #%d", suffix, immed ? immed : 32); return ERROR_OK; two: |
From: ntfreak at B. <nt...@ma...> - 2009-07-21 22:03:18
|
Author: ntfreak Date: 2009-07-21 22:03:17 +0200 (Tue, 21 Jul 2009) New Revision: 2552 Modified: trunk/src/target/armv7m.c trunk/src/target/armv7m.h trunk/src/target/cortex_m3.c trunk/src/target/cortex_m3.h Log: David Brownell <da...@pa...>: Revert parts of the previous ARMv7-M register patch. It turns out that part of the issue is a documentation problem for the Cortex-M3 r1 parts. So for the rest, simpler fixes are possible (in followup patch). Modified: trunk/src/target/armv7m.c =================================================================== --- trunk/src/target/armv7m.c 2009-07-20 07:03:11 UTC (rev 2551) +++ trunk/src/target/armv7m.c 2009-07-21 20:03:17 UTC (rev 2552) @@ -60,8 +60,8 @@ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", "xPSR", "msp", "psp", - /* reg 20 has 4 bytes: CONTROL, FAULTMASK, BASEPRI, PRIMASK */ - "spec20", + /* Registers accessed through special reg 20 */ + "primask", "basepri", "faultmask", "control" }; uint8_t armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; @@ -111,11 +111,11 @@ {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */ {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */ - /* FIXME the register numbers here are core-specific. - * Numbers 0..18 above work for all Cortex-M3 revisions. - * Number 20 below works for CM3 r2p0 and later. - */ - {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, + /* CORE_SP are accesible using coreregister 20 */ + {19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */ + {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */ + {21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */ + {22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL} /* CONTROL */ }; int armv7m_core_reg_arch_type = -1; @@ -387,21 +387,12 @@ armv7m_set_core_reg(reg, reg_params[i].value); } - /* NOTE: CONTROL is bits 31:24 of SPEC20 register, if it's present; - * holding a two-bit field. - * - * FIXME need a solution using ARMV7M_T_MSR(). Use it at least for - * earlier cores. - */ - if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY - && armv7m->has_spec20) + if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY) { LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode); - - buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_SPEC20].value, - 24, 2, armv7m_algorithm_info->core_mode); - armv7m->core_cache->reg_list[ARMV7M_SPEC20].dirty = 1; - armv7m->core_cache->reg_list[ARMV7M_SPEC20].valid = 1; + buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode); + armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1; + armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1; } /* ARMV7M always runs in Thumb state */ Modified: trunk/src/target/armv7m.h =================================================================== --- trunk/src/target/armv7m.h 2009-07-20 07:03:11 UTC (rev 2551) +++ trunk/src/target/armv7m.h 2009-07-21 20:03:17 UTC (rev 2552) @@ -61,15 +61,10 @@ ARMV7M_xPSR = 16, ARMV7M_MSP, ARMV7M_PSP, - - /* FIXME the register numbers here are core-specific. Cortex-M3 - * through r1p1 only defines registers up to PSP; see ARM DDI 0337E. - * - * It's r2p0 (see ARM DDI 0337G) which defines the register that's - * called SPEC20 here, with four single-byte fields with CONTROL - * (highest byte), FAULTMASK, BASEPRI, and PRIMASK (lowest byte). - */ - ARMV7M_SPEC20 = 20, + ARMV7M_PRIMASK, + ARMV7M_BASEPRI, + ARMV7M_FAULTMASK, + ARMV7M_CONTROL, ARMV7NUMCOREREGS }; @@ -83,7 +78,6 @@ int exception_number; swjdp_common_t swjdp_info; - bool has_spec20; /* Direct processor core register read and writes */ int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value); Modified: trunk/src/target/cortex_m3.c =================================================================== --- trunk/src/target/cortex_m3.c 2009-07-20 07:03:11 UTC (rev 2551) +++ trunk/src/target/cortex_m3.c 2009-07-21 20:03:17 UTC (rev 2552) @@ -395,7 +395,7 @@ /* Examine target state and mode */ /* First load register acessible through core debug port*/ - for (i = 0; i < ARMV7NUMCOREREGS; i++) + for (i = 0; i < ARMV7M_PRIMASK; i++) { if (!armv7m->core_cache->reg_list[i].valid) armv7m->read_core_reg(target, i); @@ -418,19 +418,22 @@ cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff); } + /* Now we can load SP core registers */ + for (i = ARMV7M_PRIMASK; i < ARMV7NUMCOREREGS; i++) + { + if (!armv7m->core_cache->reg_list[i].valid) + armv7m->read_core_reg(target, i); + } + /* Are we in an exception handler */ if (xPSR & 0x1FF) { armv7m->core_mode = ARMV7M_MODE_HANDLER; armv7m->exception_number = (xPSR & 0x1FF); } - else if (armv7m->has_spec20) + else { - /* NOTE: CONTROL is bits 31:24 of SPEC20 register, holding - * a two-bit field. Unavailable before r2p0... - */ - armv7m->core_mode = buf_get_u32( - armv7m->core_cache->reg_list[ARMV7M_SPEC20].value, 24, 2); + armv7m->core_mode = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1); armv7m->exception_number = 0; } @@ -633,26 +636,16 @@ if (debug_execution) { /* Disable interrupts */ - /* We disable interrupts in the PRIMASK register instead - * of masking with C_MASKINTS, + /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS, * This is probably the same issue as Cortex-M3 Errata 377493: - * C_MASKINTS in parallel with disabled interrupts can cause - * local faults to not be taken. (FIXED in r1p0 and later.) - * - * NOTE: PRIMASK is bits 7:0 of SPEC20 register, holding a - * one bit field. Available this way for r2p0 and later... - */ - if (armv7m->has_spec20) { - buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_SPEC20] - .value, 0, 1, 1); - armv7m->core_cache->reg_list[ARMV7M_SPEC20].dirty = 1; - armv7m->core_cache->reg_list[ARMV7M_SPEC20].valid = 1; - } + * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */ + buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1); + armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1; + armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1; /* Make sure we are in Thumb mode */ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32, - buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) - | (1 << 24)); + buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24)); armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1; armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1; } @@ -1474,14 +1467,8 @@ if ((retval = target_read_u32(target, CPUID, &cpuid)) != ERROR_OK) return retval; - if (((cpuid >> 4) & 0xc3f) == 0xc23) { + if (((cpuid >> 4) & 0xc3f) == 0xc23) LOG_DEBUG("CORTEX-M3 processor detected"); - if (((cpuid >> 20) & 0xf) >= 2) { - armv7m->has_spec20 = true; - LOG_DEBUG("r2p0 or later detected"); - } - } else - LOG_WARNING("not a CORTEX-M3 processor?"); LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid); target_read_u32(target, NVIC_ICTR, &ictr); Modified: trunk/src/target/cortex_m3.h =================================================================== --- trunk/src/target/cortex_m3.h 2009-07-20 07:03:11 UTC (rev 2551) +++ trunk/src/target/cortex_m3.h 2009-07-21 20:03:17 UTC (rev 2552) @@ -117,21 +117,6 @@ #define FPCR_REPLACE_BKPT_HIGH (2 << 30) #define FPCR_REPLACE_BKPT_BOTH (3 << 30) -/* Use MRS/MSR to read/write any of these special registers. Some of - * them (xPSR, MSP, PSP) are always available using DCRxR. Starting in - * Cortex-M3 r2p0, some (CONTROL, BASEPRI, and *MASK) are also available - * through DCRxR. - * NOTE: this listing omits xPSR components and other mixtures. - */ -#define SR_XPSR 3 -#define SR_MSP 8 -#define SR_PSP 9 -#define SR_PRIMASK 16 -#define SR_BASEPRI 17 -#define SR_BASEPRI_MAX 18 -#define SR_FAULTMASK 19 -#define SR_CONTROL 20 - typedef struct cortex_m3_fp_comparator_s { int used; |
From: ntfreak at B. <nt...@ma...> - 2009-07-20 09:03:12
|
Author: ntfreak Date: 2009-07-20 09:03:11 +0200 (Mon, 20 Jul 2009) New Revision: 2551 Modified: trunk/src/flash/cfi.c Log: - fix issue with reading device id, bug appeared when flash_address code was added - fix issue when multiple flash chips are connected, eg. x16 x 2 on 32bit mcu bus Modified: trunk/src/flash/cfi.c =================================================================== --- trunk/src/flash/cfi.c 2009-07-19 19:31:54 UTC (rev 2550) +++ trunk/src/flash/cfi.c 2009-07-20 07:03:11 UTC (rev 2551) @@ -2172,7 +2172,7 @@ { return retval; } - if ((retval = target_read_u16(target, flash_address(bank, 0, 0x02), &cfi_info->device_id)) != ERROR_OK) + if ((retval = target_read_u16(target, flash_address(bank, 0, 0x01), &cfi_info->device_id)) != ERROR_OK) { return retval; } @@ -2383,9 +2383,10 @@ sector++; } } - if (offset != cfi_info->dev_size) + if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width)) { - LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", cfi_info->dev_size, offset); + LOG_WARNING("CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "", \ + (cfi_info->dev_size * bank->bus_width / bank->chip_width), offset); } } |
From: oharboe at B. <oh...@ma...> - 2009-07-19 21:31:56
|
Author: oharboe Date: 2009-07-19 21:31:54 +0200 (Sun, 19 Jul 2009) New Revision: 2550 Modified: trunk/TODO Log: aduc flash problems have been resolved Modified: trunk/TODO =================================================================== --- trunk/TODO 2009-07-17 19:54:25 UTC (rev 2549) +++ trunk/TODO 2009-07-19 19:31:54 UTC (rev 2550) @@ -149,14 +149,6 @@ @section thelistflash Flash Support -- aduc702x segfault reported by Thomas A Moulton - -https://lists.berlios.de/pipermail/openocd-development/2009-July/009186.html - -- aduc7024 programming w/working area does not work: - -https://lists.berlios.de/pipermail/openocd-development/2009-July/009337.html - - finish documentation for the following flash drivers: - avr - ecosflash |
From: oharboe at B. <oh...@ma...> - 2009-07-17 21:54:30
|
Author: oharboe Date: 2009-07-17 21:54:25 +0200 (Fri, 17 Jul 2009) New Revision: 2549 Modified: trunk/TODO trunk/doc/manual/scripting.txt trunk/ecosflash/Makefile trunk/ecosflash/flash.S trunk/ecosflash/flash.c trunk/src/ecosboard.c trunk/src/flash/ecos.c trunk/src/flash/flash.c trunk/src/flash/flash.h trunk/src/flash/lpc288x.c trunk/src/helper/binarybuffer.c trunk/src/helper/binarybuffer.h trunk/src/helper/command.c trunk/src/helper/command.h trunk/src/helper/configuration.c trunk/src/helper/configuration.h trunk/src/helper/fileio.c trunk/src/helper/fileio.h trunk/src/helper/ioutil.c trunk/src/helper/jim-eventloop.c trunk/src/helper/jim-eventloop.h trunk/src/helper/jim.c trunk/src/helper/jim.h trunk/src/helper/log.c trunk/src/helper/log.h trunk/src/helper/options.c trunk/src/helper/replacements.c trunk/src/helper/replacements.h trunk/src/helper/time_support.c trunk/src/helper/time_support.h trunk/src/helper/types.h trunk/src/jtag/bitbang.c trunk/src/jtag/bitbang.h trunk/src/jtag/core.c trunk/src/jtag/dummy.c trunk/src/jtag/interface.c trunk/src/jtag/jtag.h trunk/src/jtag/minidummy/jtag_minidriver.h trunk/src/jtag/minidummy/minidummy.c trunk/src/jtag/parport.c trunk/src/jtag/rlink/rlink.c trunk/src/jtag/tcl.c trunk/src/jtag/zy1000/jtag_minidriver.h trunk/src/jtag/zy1000/zy1000.c trunk/src/openocd.c trunk/src/server/gdb_server.c trunk/src/server/gdb_server.h trunk/src/server/httpd.c trunk/src/server/server.c trunk/src/server/server.h trunk/src/server/telnet_server.c trunk/src/server/telnet_server.h trunk/src/target/arm7_9_common.c trunk/src/target/arm7_9_common.h trunk/src/target/arm7tdmi.c trunk/src/target/arm_jtag.c trunk/src/target/arm_jtag.h trunk/src/target/armv7m.c trunk/src/target/embeddedice.c trunk/src/target/embeddedice.h trunk/src/target/image.c trunk/src/target/image.h trunk/src/target/mips32.c trunk/src/target/register.c trunk/src/target/register.h trunk/src/target/target.c trunk/src/target/target.h trunk/src/target/target_request.c trunk/src/target/target_request.h trunk/src/target/xscale.c trunk/src/target/xscale.h trunk/src/xsvf/xsvf.c Log: Andreas Fritiofson <and...@gm...> UTF8 fixes Modified: trunk/TODO =================================================================== --- trunk/TODO 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/TODO 2009-07-17 19:54:25 UTC (rev 2549) @@ -117,7 +117,7 @@ - ARM923EJS: - reset run/halt/step is not robust; needs testing to map out problems. - ARM11 improvements (MB?) - - fix single stepping (reported by �H) + - fix single stepping (reported by ØH) - implement missing functionality (grep FNC_INFO_NOTIMPLEMENTED ...) - Cortex A8 support (ML) - add target implementation (ML) @@ -169,7 +169,7 @@ - finish implementing bus width/chip width handling (suggested by NC) - factor vendor-specific code into separate source files - add new callback interface for vendor-specific code -- investigate/implement "thin wrapper" to use eCos CFI drivers (�H) +- investigate/implement "thin wrapper" to use eCos CFI drivers (ØH) @section thelistdebug Debugger Support Modified: trunk/doc/manual/scripting.txt =================================================================== --- trunk/doc/manual/scripting.txt 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/doc/manual/scripting.txt 2009-07-17 19:54:25 UTC (rev 2549) @@ -15,7 +15,7 @@ to those same end users. Jim Tcl was chosen as it was easy to integrate, works -great in an embedded environment and vind Harboe +great in an embedded environment and Øyvind Harboe had experience with it. @section scriptinguses Uses of scripting Modified: trunk/ecosflash/Makefile =================================================================== --- trunk/ecosflash/Makefile 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/ecosflash/Makefile 2009-07-17 19:54:25 UTC (rev 2549) @@ -1,7 +1,7 @@ #####ECOSGPLCOPYRIGHTBEGIN#### ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. -## Copyright (C) 2008 vind Harboe +## Copyright (C) 2008 Øyvind Harboe ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free Modified: trunk/ecosflash/flash.S =================================================================== --- trunk/ecosflash/flash.S 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/ecosflash/flash.S 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ #####ECOSGPLCOPYRIGHTBEGIN#### ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. -## Copyright (C) 2008 vind Harboe +## Copyright (C) 2008 Øyvind Harboe ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free Modified: trunk/ecosflash/flash.c =================================================================== --- trunk/ecosflash/flash.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/ecosflash/flash.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ #####ECOSGPLCOPYRIGHTBEGIN#### ## ------------------------------------------- ## This file is part of eCos, the Embedded Configurable Operating System. -## Copyright (C) 2008 vind Harboe +## Copyright (C) 2008 Øyvind Harboe ## ## eCos is free software; you can redistribute it and/or modify it under ## the terms of the GNU General Public License as published by the Free Modified: trunk/src/ecosboard.c =================================================================== --- trunk/src/ecosboard.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/ecosboard.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2007-2008 by �yvind Harboe * + * Copyright (C) 2007-2008 by Øyvind Harboe * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * Modified: trunk/src/flash/ecos.c =================================================================== --- trunk/src/flash/ecos.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/flash/ecos.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/flash/flash.c =================================================================== --- trunk/src/flash/flash.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/flash/flash.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/flash/flash.h =================================================================== --- trunk/src/flash/flash.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/flash/flash.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/flash/lpc288x.c =================================================================== --- trunk/src/flash/lpc288x.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/flash/lpc288x.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -214,8 +214,8 @@ return ERROR_OK; } -/* The frequency is the AHB clock frequency divided by (CLK_DIV ) + 1. - * This must be programmed such that the Flash Programming clock frequency is 66 kHz 20%. +/* The frequency is the AHB clock frequency divided by (CLK_DIV ×3) + 1. + * This must be programmed such that the Flash Programming clock frequency is 66 kHz ± 20%. * AHB = 12 MHz ? * 12000000/66000 = 182 * CLK_DIV = 60 ? */ Modified: trunk/src/helper/binarybuffer.c =================================================================== --- trunk/src/helper/binarybuffer.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/binarybuffer.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2004, 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/helper/binarybuffer.h =================================================================== --- trunk/src/helper/binarybuffer.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/binarybuffer.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2004, 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/helper/command.c =================================================================== --- trunk/src/helper/command.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/command.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 �yvind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008, Duane Ellis * Modified: trunk/src/helper/command.h =================================================================== --- trunk/src/helper/command.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/command.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/helper/configuration.c =================================================================== --- trunk/src/helper/configuration.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/configuration.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2004, 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/helper/configuration.h =================================================================== --- trunk/src/helper/configuration.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/configuration.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2004, 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/helper/fileio.c =================================================================== --- trunk/src/helper/fileio.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/fileio.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2007 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/helper/fileio.h =================================================================== --- trunk/src/helper/fileio.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/fileio.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2007 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/helper/ioutil.c =================================================================== --- trunk/src/helper/ioutil.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/ioutil.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2007-2008 by vind Harboe * + * Copyright (C) 2007-2008 by Øyvind Harboe * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * Modified: trunk/src/helper/jim-eventloop.c =================================================================== --- trunk/src/helper/jim-eventloop.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/jim-eventloop.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -3,7 +3,7 @@ * Copyright 2005 Salvatore Sanfilippo <an...@in...> * Copyright 2005 Clemens Hintze <c.h...@gm...> * Copyright 2005 patthoyts - Pat Thoyts <pat...@us...> - * Copyright 2008 oharboe - vind Harboe - oyv...@zy... + * Copyright 2008 oharboe - Øyvind Harboe - oyv...@zy... * Copyright 2008 Andrew Lunn <an...@lu...> * Copyright 2008 Duane Ellis <op...@du...> * Copyright 2008 Uwe Klein <uk...@kl...> Modified: trunk/src/helper/jim-eventloop.h =================================================================== --- trunk/src/helper/jim-eventloop.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/jim-eventloop.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -3,7 +3,7 @@ * Copyright 2005 Salvatore Sanfilippo <an...@in...> * Copyright 2005 Clemens Hintze <c.h...@gm...> * Copyright 2005 patthoyts - Pat Thoyts <pat...@us...> - * Copyright 2008 oharboe - vind Harboe - oyv...@zy... + * Copyright 2008 oharboe - Øyvind Harboe - oyv...@zy... * Copyright 2008 Andrew Lunn <an...@lu...> * Copyright 2008 Duane Ellis <op...@du...> * Copyright 2008 Uwe Klein <uk...@kl...> Modified: trunk/src/helper/jim.c =================================================================== --- trunk/src/helper/jim.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/jim.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -3,7 +3,7 @@ * Copyright 2005 Salvatore Sanfilippo <an...@in...> * Copyright 2005 Clemens Hintze <c.h...@gm...> * Copyright 2005 patthoyts - Pat Thoyts <pat...@us...> - * Copyright 2008 oharboe - vind Harboe - oyv...@zy... + * Copyright 2008 oharboe - Øyvind Harboe - oyv...@zy... * Copyright 2008 Andrew Lunn <an...@lu...> * Copyright 2008 Duane Ellis <op...@du...> * Copyright 2008 Uwe Klein <uk...@kl...> Modified: trunk/src/helper/jim.h =================================================================== --- trunk/src/helper/jim.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/jim.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -3,7 +3,7 @@ * Copyright 2005 Salvatore Sanfilippo <an...@in...> * Copyright 2005 Clemens Hintze <c.h...@gm...> * Copyright 2005 patthoyts - Pat Thoyts <pat...@us...> - * Copyright 2008 oharboe - vind Harboe - oyv...@zy... + * Copyright 2008 oharboe - Øyvind Harboe - oyv...@zy... * Copyright 2008 Andrew Lunn <an...@lu...> * Copyright 2008 Duane Ellis <op...@du...> * Copyright 2008 Uwe Klein <uk...@kl...> Modified: trunk/src/helper/log.c =================================================================== --- trunk/src/helper/log.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/log.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/helper/log.h =================================================================== --- trunk/src/helper/log.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/log.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/helper/options.c =================================================================== --- trunk/src/helper/options.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/options.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2004, 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/helper/replacements.c =================================================================== --- trunk/src/helper/replacements.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/replacements.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2006 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/helper/replacements.h =================================================================== --- trunk/src/helper/replacements.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/replacements.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2006 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/helper/time_support.c =================================================================== --- trunk/src/helper/time_support.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/time_support.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2006 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/helper/time_support.h =================================================================== --- trunk/src/helper/time_support.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/time_support.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2006 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/helper/types.h =================================================================== --- trunk/src/helper/types.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/helper/types.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2004, 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/jtag/bitbang.c =================================================================== --- trunk/src/jtag/bitbang.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/jtag/bitbang.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * @@ -46,12 +46,12 @@ * Set this to 1 and str912 reset halt will fail. * * If someone can submit a patch with an explanation it will be greatly - * appreciated, but as far as I can tell () DCLK is generated upon + * appreciated, but as far as I can tell (ØH) DCLK is generated upon * clk = 0 in TAP_IDLE. Good luck deducing that from the ARM documentation! * The ARM documentation uses the term "DCLK is asserted while in the TAP_IDLE * state". With hardware there is no such thing as *while* in a state. There * are only edges. So clk => 0 is in fact a very subtle state transition that - * happens *while* in the TAP_IDLE state. "#&"#&"#&"#& + * happens *while* in the TAP_IDLE state. "#&¤"#¤&"#&"#& * * For "reset halt" the last thing that happens before srst is asserted * is that the breakpoint is set up. If DCLK is not wiggled one last Modified: trunk/src/jtag/bitbang.h =================================================================== --- trunk/src/jtag/bitbang.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/jtag/bitbang.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/jtag/core.c =================================================================== --- trunk/src/jtag/core.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/jtag/core.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2009 SoftPLC Corporation * Modified: trunk/src/jtag/dummy.c =================================================================== --- trunk/src/jtag/dummy.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/jtag/dummy.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2008 by vind Harboe * + * Copyright (C) 2008 by Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/jtag/interface.c =================================================================== --- trunk/src/jtag/interface.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/jtag/interface.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2009 SoftPLC Corporation * Modified: trunk/src/jtag/jtag.h =================================================================== --- trunk/src/jtag/jtag.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/jtag/jtag.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * -* Copyright (C) 2007,2008 vind Harboe * +* Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/jtag/minidummy/jtag_minidriver.h =================================================================== --- trunk/src/jtag/minidummy/jtag_minidriver.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/jtag/minidummy/jtag_minidriver.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2007-2008 by vind Harboe * + * Copyright (C) 2007-2008 by Øyvind Harboe * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * Modified: trunk/src/jtag/minidummy/minidummy.c =================================================================== --- trunk/src/jtag/minidummy/minidummy.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/jtag/minidummy/minidummy.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2007-2008 by vind Harboe * + * Copyright (C) 2007-2008 by Øyvind Harboe * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * Modified: trunk/src/jtag/parport.c =================================================================== --- trunk/src/jtag/parport.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/jtag/parport.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -247,7 +247,7 @@ static int parport_register_commands(struct command_context_s *cmd_ctx) { register_command(cmd_ctx, NULL, "parport_port", parport_handle_parport_port_command, - COMMAND_CONFIG, "either the address of the I/O port or the number of the �/dev/parport� device"); + COMMAND_CONFIG, "either the address of the I/O port or the number of the '/dev/parport' device"); register_command(cmd_ctx, NULL, "parport_cable", parport_handle_parport_cable_command, COMMAND_CONFIG, "the layout of the parallel port cable used to connect to the target"); register_command(cmd_ctx, NULL, "parport_write_on_exit", parport_handle_write_on_exit_command, Modified: trunk/src/jtag/rlink/rlink.c =================================================================== --- trunk/src/jtag/rlink/rlink.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/jtag/rlink/rlink.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 Rob Brown, Lou Deluxe * Modified: trunk/src/jtag/tcl.c =================================================================== --- trunk/src/jtag/tcl.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/jtag/tcl.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 �yvind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2009 SoftPLC Corporation * Modified: trunk/src/jtag/zy1000/jtag_minidriver.h =================================================================== --- trunk/src/jtag/zy1000/jtag_minidriver.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/jtag/zy1000/jtag_minidriver.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2007-2008 by vind Harboe * + * Copyright (C) 2007-2008 by Øyvind Harboe * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * Modified: trunk/src/jtag/zy1000/zy1000.c =================================================================== --- trunk/src/jtag/zy1000/zy1000.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/jtag/zy1000/zy1000.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2007-2008 by �yvind Harboe * + * Copyright (C) 2007-2008 by Øyvind Harboe * * * * This program is free software; you can redistribute it and/or modify * * it under the terms of the GNU General Public License as published by * Modified: trunk/src/openocd.c =================================================================== --- trunk/src/openocd.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/openocd.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 Richard Missenden * Modified: trunk/src/server/gdb_server.c =================================================================== --- trunk/src/server/gdb_server.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/server/gdb_server.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 �yvind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/server/gdb_server.h =================================================================== --- trunk/src/server/gdb_server.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/server/gdb_server.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/server/httpd.c =================================================================== --- trunk/src/server/httpd.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/server/httpd.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -1,5 +1,5 @@ /*************************************************************************** - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 Free Software Foundation Modified: trunk/src/server/server.c =================================================================== --- trunk/src/server/server.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/server/server.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/server/server.h =================================================================== --- trunk/src/server/server.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/server/server.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/server/telnet_server.c =================================================================== --- trunk/src/server/telnet_server.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/server/telnet_server.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/server/telnet_server.h =================================================================== --- trunk/src/server/telnet_server.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/server/telnet_server.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/target/arm7_9_common.c =================================================================== --- trunk/src/target/arm7_9_common.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/target/arm7_9_common.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 �yvind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/target/arm7_9_common.h =================================================================== --- trunk/src/target/arm7_9_common.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/target/arm7_9_common.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/target/arm7tdmi.c =================================================================== --- trunk/src/target/arm7tdmi.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/target/arm7tdmi.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -5,7 +5,7 @@ * Copyright (C) 2008 by Spencer Oliver * * sp...@sp... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/target/arm_jtag.c =================================================================== --- trunk/src/target/arm_jtag.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/target/arm_jtag.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/target/arm_jtag.h =================================================================== --- trunk/src/target/arm_jtag.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/target/arm_jtag.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/target/armv7m.c =================================================================== --- trunk/src/target/armv7m.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/target/armv7m.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -8,7 +8,7 @@ * Copyright (C) 2008 by Spencer Oliver * * sp...@sp... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/target/embeddedice.c =================================================================== --- trunk/src/target/embeddedice.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/target/embeddedice.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/target/embeddedice.h =================================================================== --- trunk/src/target/embeddedice.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/target/embeddedice.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005, 2006 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/target/image.c =================================================================== --- trunk/src/target/image.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/target/image.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2007 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/target/image.h =================================================================== --- trunk/src/target/image.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/target/image.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2007 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/target/mips32.c =================================================================== --- trunk/src/target/mips32.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/target/mips32.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -4,7 +4,7 @@ * * * Copyright (C) 2008 by David T.L. Wong * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/target/register.c =================================================================== --- trunk/src/target/register.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/target/register.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/target/register.h =================================================================== --- trunk/src/target/register.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/target/register.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * This program is free software; you can redistribute it and/or modify * Modified: trunk/src/target/target.c =================================================================== --- trunk/src/target/target.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/target/target.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 �yvind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008, Duane Ellis * Modified: trunk/src/target/target.h =================================================================== --- trunk/src/target/target.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/target/target.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2005 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/target/target_request.c =================================================================== --- trunk/src/target/target_request.c 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/target/target_request.c 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2007 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/target/target_request.h =================================================================== --- trunk/src/target/target_request.h 2009-07-16 10:44:42 UTC (rev 2548) +++ trunk/src/target/target_request.h 2009-07-17 19:54:25 UTC (rev 2549) @@ -2,7 +2,7 @@ * Copyright (C) 2007 by Dominic Rath * * Dom...@gm... * * * - * Copyright (C) 2007,2008 vind Harboe * + * Copyright (C) 2007,2008 Øyvind Harboe * * oyv...@zy... * * * * Copyright (C) 2008 by Spencer Oliver * Modified: trunk/src/target/xscale.c ====... [truncated message content] |
From: oharboe at B. <oh...@ma...> - 2009-07-16 12:44:43
|
Author: oharboe Date: 2009-07-16 12:44:42 +0200 (Thu, 16 Jul 2009) New Revision: 2548 Modified: trunk/TODO Log: added item to come up with slick new 32 bit jtag_add_xxx() API Modified: trunk/TODO =================================================================== --- trunk/TODO 2009-07-16 10:43:15 UTC (rev 2547) +++ trunk/TODO 2009-07-16 10:44:42 UTC (rev 2548) @@ -39,11 +39,16 @@ @subsection thelistjtagcore JTAG Core -The following tasks have been suggeted for cleaning up the JTAG layer: +The following tasks have been suggested for cleaning up the JTAG layer: - use tap_set_state everywhere to allow logging TAP state transitions - rename other tap_states to use standard JTAG names (suggested by ML) - Encapsulate cmd_queue_cur_state and related varaible handling. +- add slick 32 bit versions of jtag_add_xxx_scan() that avoids +buf_set_u32() calls and other evidence of poor impedance match between +API and calling code. New API should cut down # of lines in calling +code by 100's and make things clearer. Also potentially be supported +directly in minidriver API for better embedded host performance. The following tasks have been suggested for adding new core JTAG support: |
From: oharboe at B. <oh...@ma...> - 2009-07-16 12:43:21
|
Author: oharboe Date: 2009-07-16 12:43:15 +0200 (Thu, 16 Jul 2009) New Revision: 2547 Modified: trunk/src/target/feroceon.c Log: microscopic whitespace cleanup Modified: trunk/src/target/feroceon.c =================================================================== --- trunk/src/target/feroceon.c 2009-07-16 10:30:50 UTC (rev 2546) +++ trunk/src/target/feroceon.c 2009-07-16 10:43:15 UTC (rev 2547) @@ -132,33 +132,18 @@ fields[0].tap = jtag_info->tap; fields[0].num_bits = 32; fields[0].out_value = out_buf; - fields[0].in_value = NULL; - - - - fields[1].tap = jtag_info->tap; fields[1].num_bits = 3; fields[1].out_value = &sysspeed_buf; - fields[1].in_value = NULL; - - - - fields[2].tap = jtag_info->tap; fields[2].num_bits = 32; fields[2].out_value = instr_buf; - fields[2].in_value = NULL; - - - - jtag_add_dr_scan(3, fields, jtag_get_end_state()); /* no jtag_add_runtest(0, jtag_get_end_state()) here */ |
From: oharboe at B. <oh...@ma...> - 2009-07-16 12:30:52
|
Author: oharboe Date: 2009-07-16 12:30:50 +0200 (Thu, 16 Jul 2009) New Revision: 2546 Modified: trunk/src/target/mips_ejtag.c Log: microscopic white space fixes Modified: trunk/src/target/mips_ejtag.c =================================================================== --- trunk/src/target/mips_ejtag.c 2009-07-16 10:03:33 UTC (rev 2545) +++ trunk/src/target/mips_ejtag.c 2009-07-16 10:30:50 UTC (rev 2546) @@ -44,12 +44,8 @@ field.num_bits = tap->ir_length; field.out_value = t; buf_set_u32(field.out_value, 0, field.num_bits, new_instr); - field.in_value = NULL; - - - jtag_add_ir_scan(1, &field, jtag_get_end_state()); } @@ -67,12 +63,8 @@ field.tap = ejtag_info->tap; field.num_bits = 32; field.out_value = NULL; - field.in_value = (void*)idcode; - - - jtag_add_dr_scan(1, &field, jtag_get_end_state()); if (jtag_execute_queue() != ERROR_OK) @@ -94,12 +86,8 @@ field.tap = ejtag_info->tap; field.num_bits = 32; field.out_value = NULL; - field.in_value = (void*)impcode; - - - jtag_add_dr_scan(1, &field, jtag_get_end_state()); if (jtag_execute_queue() != ERROR_OK) @@ -125,12 +113,8 @@ field.num_bits = 32; field.out_value = t; buf_set_u32(field.out_value, 0, field.num_bits, *data); - field.in_value = r; - - - jtag_add_dr_scan(1, &field, jtag_get_end_state()); if ((retval = jtag_execute_queue()) != ERROR_OK) |
From: ntfreak at B. <nt...@ma...> - 2009-07-16 12:03:35
|
Author: ntfreak Date: 2009-07-16 12:03:33 +0200 (Thu, 16 Jul 2009) New Revision: 2545 Modified: trunk/configure.in Log: - disable using parport ppdev under win32 hosts Modified: trunk/configure.in =================================================================== --- trunk/configure.in 2009-07-16 00:08:36 UTC (rev 2544) +++ trunk/configure.in 2009-07-16 10:03:33 UTC (rev 2545) @@ -453,6 +453,7 @@ case $host in *-cygwin*) is_win32=yes + parport_use_ppdev=no AC_COMPILE_IFELSE(AC_LANG_PROGRAM([],[return __MINGW32__;]), [is_mingw=yes],[is_mingw=no]) @@ -474,6 +475,7 @@ *-mingw*) is_mingw=yes is_win32=yes + parport_use_ppdev=no if test x$parport_use_giveio = xno; then AC_MSG_WARN([--disable-parport-giveio is not supported by MinGW32 hosts]) |
From: <zw...@ma...> - 2009-07-16 02:08:44
|
Author: zwelch Date: 2009-07-16 02:08:36 +0200 (Thu, 16 Jul 2009) New Revision: 2544 Modified: trunk/src/target/arm_adi_v5.c trunk/src/target/arm_adi_v5.h trunk/src/target/armv7m.c Log: Magnus Lundin <lu...@ml...>, Oyvind Harboe <oyv...@zy...>, David Brownell <da...@pa...>: Move the dap command handler implementations to arm_adi_v5.c, leaving just thin wrappers in armv7m.c. There should be no change in functionality here. (From Magnus.) Minor style cleanup: whitespace, line length, etc. Update spec references to use docs which are currently available. (From Dave.) Modified: trunk/src/target/arm_adi_v5.c =================================================================== --- trunk/src/target/arm_adi_v5.c 2009-07-16 00:08:21 UTC (rev 2543) +++ trunk/src/target/arm_adi_v5.c 2009-07-16 00:08:36 UTC (rev 2544) @@ -29,8 +29,8 @@ * * * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A * * * - * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A * - * Cortex-M3(tm) TRM, ARM DDI 0337C * + * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D * + * Cortex-M3(tm) TRM, ARM DDI 0337G * * * ***************************************************************************/ @@ -1129,3 +1129,85 @@ return ERROR_OK; } +int dap_baseaddr_command(struct command_context_s *cmd_ctx, + swjdp_common_t *swjdp, char **args, int argc) +{ + uint32_t apsel, apselsave, baseaddr; + int retval; + + apsel = swjdp->apsel; + apselsave = swjdp->apsel; + if (argc > 0) + apsel = strtoul(args[0], NULL, 0); + if (apselsave != apsel) + dap_ap_select(swjdp, apsel); + + dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr); + retval = swjdp_transaction_endcheck(swjdp); + command_print(cmd_ctx, "0x%8.8x", baseaddr); + + if (apselsave != apsel) + dap_ap_select(swjdp, apselsave); + + return retval; +} + +int dap_memaccess_command(struct command_context_s *cmd_ctx, + swjdp_common_t *swjdp, char **args, int argc) +{ + uint32_t memaccess_tck; + + memaccess_tck = swjdp->memaccess_tck; + if (argc > 0) + memaccess_tck = strtoul(args[0], NULL, 0); + + swjdp->memaccess_tck = memaccess_tck; + command_print(cmd_ctx, "memory bus access delay set to %i tck", + swjdp->memaccess_tck); + + return ERROR_OK; +} + +int dap_apsel_command(struct command_context_s *cmd_ctx, + swjdp_common_t *swjdp, char **args, int argc) +{ + uint32_t apsel, apid; + int retval; + + apsel = 0; + if (argc > 0) + apsel = strtoul(args[0], NULL, 0); + + dap_ap_select(swjdp, apsel); + dap_ap_read_reg_u32(swjdp, 0xFC, &apid); + retval = swjdp_transaction_endcheck(swjdp); + command_print(cmd_ctx, "ap %i selected, identification register 0x%8.8x", + apsel, apid); + + return retval; +} + +int dap_apid_command(struct command_context_s *cmd_ctx, + swjdp_common_t *swjdp, char **args, int argc) +{ + uint32_t apsel, apselsave, apid; + int retval; + + apsel = swjdp->apsel; + apselsave = swjdp->apsel; + if (argc > 0) + apsel = strtoul(args[0], NULL, 0); + + if (apselsave != apsel) + dap_ap_select(swjdp, apsel); + + dap_ap_read_reg_u32(swjdp, 0xFC, &apid); + retval = swjdp_transaction_endcheck(swjdp); + command_print(cmd_ctx, "0x%8.8x", apid); + if (apselsave != apsel) + dap_ap_select(swjdp, apselsave); + + return retval; +} + + Modified: trunk/src/target/arm_adi_v5.h =================================================================== --- trunk/src/target/arm_adi_v5.h 2009-07-16 00:08:21 UTC (rev 2543) +++ trunk/src/target/arm_adi_v5.h 2009-07-16 00:08:36 UTC (rev 2544) @@ -145,13 +145,17 @@ /* Initialisation of the debug system, power domains and registers */ extern int ahbap_debugport_init(swjdp_common_t *swjdp); -extern int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, int apsel); + /* Commands for user dap access */ -/* Currently implemented in armv7m, needs armv7m target structure to find jtag and swjdp structures */ -extern int handle_dap_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -extern int handle_dap_apsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -extern int handle_dap_apid_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -extern int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); -extern int handle_dap_memaccess_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc); +int dap_info_command(struct command_context_s *cmd_ctx, + swjdp_common_t *swjdp, int apsel); +int dap_baseaddr_command(struct command_context_s *cmd_ctx, + swjdp_common_t *swjdp, char **args, int argc); +int dap_memaccess_command(struct command_context_s *cmd_ctx, + swjdp_common_t *swjdp, char **args, int argc); +int dap_apsel_command(struct command_context_s *cmd_ctx, + swjdp_common_t *swjdp, char **args, int argc); +int dap_apid_command(struct command_context_s *cmd_ctx, + swjdp_common_t *swjdp, char **args, int argc); #endif Modified: trunk/src/target/armv7m.c =================================================================== --- trunk/src/target/armv7m.c 2009-07-16 00:08:21 UTC (rev 2543) +++ trunk/src/target/armv7m.c 2009-07-16 00:08:36 UTC (rev 2544) @@ -554,20 +554,6 @@ return ERROR_OK; } -int armv7m_register_commands(struct command_context_s *cmd_ctx) -{ - command_t *arm_adi_v5_dap_cmd; - - arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", NULL, COMMAND_ANY, "cortex dap specific commands"); - register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", handle_dap_info_command, COMMAND_EXEC, "Displays dap info for ap [num], default currently selected AP"); - register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel", handle_dap_apsel_command, COMMAND_EXEC, "Select a different AP [num] (default 0)"); - register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid", handle_dap_apid_command, COMMAND_EXEC, "Displays id reg from AP [num], default currently selected AP"); - register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr", handle_dap_baseaddr_command, COMMAND_EXEC, "Displays debug base address from AP [num], default currently selected AP"); - register_command(cmd_ctx, arm_adi_v5_dap_cmd, "memaccess", handle_dap_memaccess_command, COMMAND_EXEC, "set/get number of extra tck for mem-ap memory bus access [0-255]"); - - return ERROR_OK; -} - int armv7m_checksum_memory(struct target_s *target, uint32_t address, uint32_t count, uint32_t* checksum) { working_area_t *crc_algorithm; @@ -711,10 +697,12 @@ return ERROR_OK; } -/******************************************************************************************************************** -* Return the debug ap baseaddress in hexadecimal, no extra output to simplify script processing -*********************************************************************************************************************/ -int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +/* + * Return the debug ap baseaddress in hexadecimal; + * no extra output to simplify script processing + */ +static int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv7m_common_t *armv7m = target->arch_info; @@ -746,97 +734,83 @@ } -/******************************************************************************************************************** -* Return the debug ap id in hexadecimal, no extra output to simplify script processing -*********************************************************************************************************************/ -extern int handle_dap_apid_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +/* + * Return the debug ap id in hexadecimal; + * no extra output to simplify script processing + */ +extern int handle_dap_apid_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv7m_common_t *armv7m = target->arch_info; swjdp_common_t *swjdp = &armv7m->swjdp_info; - uint32_t apsel, apselsave, apid; - int retval; - apsel = swjdp->apsel; - apselsave = swjdp->apsel; - if (argc > 0) - { - apsel = strtoul(args[0], NULL, 0); - } - - if (apselsave != apsel) - { - dap_ap_select(swjdp, apsel); - } - - dap_ap_read_reg_u32(swjdp, 0xFC, &apid); - retval = swjdp_transaction_endcheck(swjdp); - command_print(cmd_ctx, "0x%8.8" PRIx32 "", apid); - if (apselsave != apsel) - { - dap_ap_select(swjdp, apselsave); - } - - return retval; + return dap_apid_command(cmd_ctx, swjdp, args, argc); } -int handle_dap_apsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int handle_dap_apsel_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv7m_common_t *armv7m = target->arch_info; swjdp_common_t *swjdp = &armv7m->swjdp_info; - uint32_t apsel, apid; - int retval; - apsel = 0; - if (argc > 0) - { - apsel = strtoul(args[0], NULL, 0); - } - - dap_ap_select(swjdp, apsel); - dap_ap_read_reg_u32(swjdp, 0xFC, &apid); - retval = swjdp_transaction_endcheck(swjdp); - command_print(cmd_ctx, "ap %i selected, identification register 0x%8.8" PRIx32 "", (int)apsel, apid); - - return retval; + return dap_apsel_command(cmd_ctx, swjdp, args, argc); } -int handle_dap_memaccess_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) +static int handle_dap_memaccess_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv7m_common_t *armv7m = target->arch_info; swjdp_common_t *swjdp = &armv7m->swjdp_info; - uint32_t memaccess_tck; - memaccess_tck = swjdp->memaccess_tck; - if (argc > 0) - { - memaccess_tck = strtoul(args[0], NULL, 0); - } - - swjdp->memaccess_tck = memaccess_tck; - command_print(cmd_ctx, "memory bus access delay set to %i tck", (int)(swjdp->memaccess_tck)); - - return ERROR_OK; + return dap_memaccess_command(cmd_ctx, swjdp, args, argc); } -int handle_dap_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) + +static int handle_dap_info_command(struct command_context_s *cmd_ctx, + char *cmd, char **args, int argc) { target_t *target = get_current_target(cmd_ctx); armv7m_common_t *armv7m = target->arch_info; swjdp_common_t *swjdp = &armv7m->swjdp_info; - int retval; uint32_t apsel; apsel = swjdp->apsel; if (argc > 0) - { apsel = strtoul(args[0], NULL, 0); - } - retval = dap_info_command(cmd_ctx, swjdp, apsel); - - return retval; + return dap_info_command(cmd_ctx, swjdp, apsel); } +int armv7m_register_commands(struct command_context_s *cmd_ctx) +{ + command_t *arm_adi_v5_dap_cmd; + + arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", + NULL, COMMAND_ANY, + "cortex dap specific commands"); + + register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", + handle_dap_info_command, COMMAND_EXEC, + "Displays dap info for ap [num]," + "default currently selected AP"); + register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel", + handle_dap_apsel_command, COMMAND_EXEC, + "Select a different AP [num] (default 0)"); + register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid", + handle_dap_apid_command, COMMAND_EXEC, + "Displays id reg from AP [num], " + "default currently selected AP"); + register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr", + handle_dap_baseaddr_command, COMMAND_EXEC, + "Displays debug base address from AP [num]," + "default currently selected AP"); + register_command(cmd_ctx, arm_adi_v5_dap_cmd, "memaccess", + handle_dap_memaccess_command, COMMAND_EXEC, + "set/get number of extra tck for mem-ap " + "memory bus access [0-255]"); + + return ERROR_OK; +} |
From: <zw...@ma...> - 2009-07-16 02:08:32
|
Author: zwelch Date: 2009-07-16 02:08:21 +0200 (Thu, 16 Jul 2009) New Revision: 2543 Modified: trunk/src/target/armv7m.c trunk/src/target/armv7m.h trunk/src/target/cortex_m3.c trunk/src/target/cortex_m3.h Log: Magnus Lundin <lu...@ml...>, Oyvind Harboe <oyv...@zy...>, David Brownell <da...@pa...>: Some cleanup of the ARMv7-M support: - Reference the relevant ARMv7-M ARM doc (DDI 0405C to non-Vendors), and update the Cortex-M3 doc refs (DDI 0337C is no longer available). - Those registers aren't actually general, and some are incorrect (per all public docs anyway). Update comments and code accordingly. * What the Core Debug facility exposes is *implementation-specific* not architectural. These values aren't fully portable. They match Cortex-M3 ... so no current implementation will make trouble, but the next v7m implementation might. * Four of the registers are actually not exposed that way. Before Cortex-M3 r2p0 they are read/written through MRS/MSR instructions. In that newest silicon, they are four bytes in one register, not four separate registers. - Update the CM3 code to report when that one register is available, and not try to access it when it isn't. Also declare the register numbers that an eventual MRS/MSR solution will need to be using. - Stop line wrapping the exception labels. So for parts before r2p0 OpenOCD behavior is effectively unchanged, and still buggy; but for those newer parts a few things might now be correct. Most current Cortex-M3 parts use r1p1 (or earlier); this seems to include most LM3S parts and all STM32 parts. Parts using r2p0 are available, and include fourth generation LM3S parts ("Tempest") plus AT91SAM3 and LPC17xx parts which are now sampling. Modified: trunk/src/target/armv7m.c =================================================================== --- trunk/src/target/armv7m.c 2009-07-15 23:49:12 UTC (rev 2542) +++ trunk/src/target/armv7m.c 2009-07-16 00:08:21 UTC (rev 2543) @@ -25,6 +25,10 @@ * along with this program; if not, write to the * * Free Software Foundation, Inc., * * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * + * * + * ARMv7-M Architecture, Application Level Reference Manual * + * ARM DDI 0405C (September 2008) * + * * ***************************************************************************/ #ifdef HAVE_CONFIG_H #include "config.h" @@ -44,8 +48,10 @@ char* armv7m_exception_strings[] = { - "", "Reset", "NMI", "HardFault", "MemManage", "BusFault", "UsageFault", "RESERVED", "RESERVED", "RESERVED", "RESERVED", - "SVCall", "DebugMonitor", "RESERVED", "PendSV", "SysTick" + "", "Reset", "NMI", "HardFault", + "MemManage", "BusFault", "UsageFault", "RESERVED", + "RESERVED", "RESERVED", "RESERVED", "SVCall", + "DebugMonitor", "RESERVED", "PendSV", "SysTick" }; char* armv7m_core_reg_list[] = @@ -54,8 +60,8 @@ "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", "xPSR", "msp", "psp", - /* Registers accessed through special reg 20 */ - "primask", "basepri", "faultmask", "control" + /* reg 20 has 4 bytes: CONTROL, FAULTMASK, BASEPRI, PRIMASK */ + "spec20", }; uint8_t armv7m_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; @@ -105,11 +111,11 @@ {17, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* MSP */ {18, ARMV7M_REGISTER_CORE_GP, ARMV7M_MODE_ANY, NULL, NULL}, /* PSP */ - /* CORE_SP are accesible using coreregister 20 */ - {19, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* PRIMASK */ - {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* BASEPRI */ - {21, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, /* FAULTMASK */ - {22, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL} /* CONTROL */ + /* FIXME the register numbers here are core-specific. + * Numbers 0..18 above work for all Cortex-M3 revisions. + * Number 20 below works for CM3 r2p0 and later. + */ + {20, ARMV7M_REGISTER_CORE_SP, ARMV7M_MODE_ANY, NULL, NULL}, }; int armv7m_core_reg_arch_type = -1; @@ -381,12 +387,21 @@ armv7m_set_core_reg(reg, reg_params[i].value); } - if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY) + /* NOTE: CONTROL is bits 31:24 of SPEC20 register, if it's present; + * holding a two-bit field. + * + * FIXME need a solution using ARMV7M_T_MSR(). Use it at least for + * earlier cores. + */ + if (armv7m_algorithm_info->core_mode != ARMV7M_MODE_ANY + && armv7m->has_spec20) { LOG_DEBUG("setting core_mode: 0x%2.2x", armv7m_algorithm_info->core_mode); - buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1, armv7m_algorithm_info->core_mode); - armv7m->core_cache->reg_list[ARMV7M_CONTROL].dirty = 1; - armv7m->core_cache->reg_list[ARMV7M_CONTROL].valid = 1; + + buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_SPEC20].value, + 24, 2, armv7m_algorithm_info->core_mode); + armv7m->core_cache->reg_list[ARMV7M_SPEC20].dirty = 1; + armv7m->core_cache->reg_list[ARMV7M_SPEC20].valid = 1; } /* ARMV7M always runs in Thumb state */ Modified: trunk/src/target/armv7m.h =================================================================== --- trunk/src/target/armv7m.h 2009-07-15 23:49:12 UTC (rev 2542) +++ trunk/src/target/armv7m.h 2009-07-16 00:08:21 UTC (rev 2543) @@ -61,10 +61,15 @@ ARMV7M_xPSR = 16, ARMV7M_MSP, ARMV7M_PSP, - ARMV7M_PRIMASK, - ARMV7M_BASEPRI, - ARMV7M_FAULTMASK, - ARMV7M_CONTROL, + + /* FIXME the register numbers here are core-specific. Cortex-M3 + * through r1p1 only defines registers up to PSP; see ARM DDI 0337E. + * + * It's r2p0 (see ARM DDI 0337G) which defines the register that's + * called SPEC20 here, with four single-byte fields with CONTROL + * (highest byte), FAULTMASK, BASEPRI, and PRIMASK (lowest byte). + */ + ARMV7M_SPEC20 = 20, ARMV7NUMCOREREGS }; @@ -78,6 +83,7 @@ int exception_number; swjdp_common_t swjdp_info; + bool has_spec20; /* Direct processor core register read and writes */ int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, uint32_t num, uint32_t *value); Modified: trunk/src/target/cortex_m3.c =================================================================== --- trunk/src/target/cortex_m3.c 2009-07-15 23:49:12 UTC (rev 2542) +++ trunk/src/target/cortex_m3.c 2009-07-16 00:08:21 UTC (rev 2543) @@ -24,7 +24,7 @@ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * * * * * - * Cortex-M3(tm) TRM, ARM DDI 0337C * + * Cortex-M3(tm) TRM, ARM DDI 0337E (r1p1) and 0337G (r2p0) * * * ***************************************************************************/ #ifdef HAVE_CONFIG_H @@ -395,7 +395,7 @@ /* Examine target state and mode */ /* First load register acessible through core debug port*/ - for (i = 0; i < ARMV7M_PRIMASK; i++) + for (i = 0; i < ARMV7NUMCOREREGS; i++) { if (!armv7m->core_cache->reg_list[i].valid) armv7m->read_core_reg(target, i); @@ -418,22 +418,19 @@ cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff); } - /* Now we can load SP core registers */ - for (i = ARMV7M_PRIMASK; i < ARMV7NUMCOREREGS; i++) - { - if (!armv7m->core_cache->reg_list[i].valid) - armv7m->read_core_reg(target, i); - } - /* Are we in an exception handler */ if (xPSR & 0x1FF) { armv7m->core_mode = ARMV7M_MODE_HANDLER; armv7m->exception_number = (xPSR & 0x1FF); } - else + else if (armv7m->has_spec20) { - armv7m->core_mode = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1); + /* NOTE: CONTROL is bits 31:24 of SPEC20 register, holding + * a two-bit field. Unavailable before r2p0... + */ + armv7m->core_mode = buf_get_u32( + armv7m->core_cache->reg_list[ARMV7M_SPEC20].value, 24, 2); armv7m->exception_number = 0; } @@ -636,16 +633,26 @@ if (debug_execution) { /* Disable interrupts */ - /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS, + /* We disable interrupts in the PRIMASK register instead + * of masking with C_MASKINTS, * This is probably the same issue as Cortex-M3 Errata 377493: - * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */ - buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1); - armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1; - armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1; + * C_MASKINTS in parallel with disabled interrupts can cause + * local faults to not be taken. (FIXED in r1p0 and later.) + * + * NOTE: PRIMASK is bits 7:0 of SPEC20 register, holding a + * one bit field. Available this way for r2p0 and later... + */ + if (armv7m->has_spec20) { + buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_SPEC20] + .value, 0, 1, 1); + armv7m->core_cache->reg_list[ARMV7M_SPEC20].dirty = 1; + armv7m->core_cache->reg_list[ARMV7M_SPEC20].valid = 1; + } /* Make sure we are in Thumb mode */ buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32, - buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24)); + buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) + | (1 << 24)); armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1; armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1; } @@ -1467,8 +1474,14 @@ if ((retval = target_read_u32(target, CPUID, &cpuid)) != ERROR_OK) return retval; - if (((cpuid >> 4) & 0xc3f) == 0xc23) + if (((cpuid >> 4) & 0xc3f) == 0xc23) { LOG_DEBUG("CORTEX-M3 processor detected"); + if (((cpuid >> 20) & 0xf) >= 2) { + armv7m->has_spec20 = true; + LOG_DEBUG("r2p0 or later detected"); + } + } else + LOG_WARNING("not a CORTEX-M3 processor?"); LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid); target_read_u32(target, NVIC_ICTR, &ictr); Modified: trunk/src/target/cortex_m3.h =================================================================== --- trunk/src/target/cortex_m3.h 2009-07-15 23:49:12 UTC (rev 2542) +++ trunk/src/target/cortex_m3.h 2009-07-16 00:08:21 UTC (rev 2543) @@ -117,6 +117,21 @@ #define FPCR_REPLACE_BKPT_HIGH (2 << 30) #define FPCR_REPLACE_BKPT_BOTH (3 << 30) +/* Use MRS/MSR to read/write any of these special registers. Some of + * them (xPSR, MSP, PSP) are always available using DCRxR. Starting in + * Cortex-M3 r2p0, some (CONTROL, BASEPRI, and *MASK) are also available + * through DCRxR. + * NOTE: this listing omits xPSR components and other mixtures. + */ +#define SR_XPSR 3 +#define SR_MSP 8 +#define SR_PSP 9 +#define SR_PRIMASK 16 +#define SR_BASEPRI 17 +#define SR_BASEPRI_MAX 18 +#define SR_FAULTMASK 19 +#define SR_CONTROL 20 + typedef struct cortex_m3_fp_comparator_s { int used; |
From: <zw...@ma...> - 2009-07-16 01:49:16
|
Author: zwelch Date: 2009-07-16 01:49:12 +0200 (Thu, 16 Jul 2009) New Revision: 2542 Modified: trunk/src/target/arm_disassembler.c Log: David Brownell <da...@pa...>: More 32-bit Thumb2 instruction decoding: A5.3.7 Load word Modified: trunk/src/target/arm_disassembler.c =================================================================== --- trunk/src/target/arm_disassembler.c 2009-07-15 23:49:05 UTC (rev 2541) +++ trunk/src/target/arm_disassembler.c 2009-07-15 23:49:12 UTC (rev 2542) @@ -3254,6 +3254,80 @@ return ERROR_OK; } +static int t2ev_load_word(uint32_t opcode, uint32_t address, + arm_instruction_t *instruction, char *cp) +{ + int rn = (opcode >> 16) & 0xf; + int immed; + + instruction->type = ARM_LDR; + + if (rn == 0xf) { + immed = opcode & 0x0fff; + if (opcode & (1 << 23)) + immed = -immed; + sprintf(cp, "LDR\tr%d, %#8.8" PRIx32, + (opcode >> 12) & 0xf, + thumb_alignpc4(address) + immed); + return ERROR_OK; + } + + if (opcode & (1 << 23)) { + immed = opcode & 0x0fff; + sprintf(cp, "LDR.W\tr%d, [r%d, #%d]\t; %#3.3x", + (opcode >> 12) & 0xf, + rn, immed, immed); + return ERROR_OK; + } + + if (!(opcode & (0x3f << 6))) { + sprintf(cp, "LDR.W\tr%d, [r%d, r%d, LSL #%d]", + (opcode >> 12) & 0xf, + rn, + (opcode >> 0) & 0xf, + (opcode >> 4) & 0x3); + return ERROR_OK; + } + + + if (((opcode >> 8) & 0xf) == 0xe) { + immed = opcode & 0x00ff; + + sprintf(cp, "LDRT\tr%d, [r%d, #%d]\t; %#2.2x", + (opcode >> 12) & 0xf, + rn, immed, immed); + return ERROR_OK; + } + + if (((opcode >> 8) & 0xf) == 0xc || (opcode & 0x0900) == 0x0900) { + char *p1 = "]", *p2 = ""; + + if (!(opcode & 0x0600)) + return ERROR_INVALID_ARGUMENTS; + + immed = opcode & 0x00ff; + + /* two indexed modes will write back rn */ + if (opcode & 0x100) { + if (opcode & 0x400) /* pre-indexed */ + p2 = "]!"; + else { /* post-indexed */ + p1 = "]"; + p2 = ""; + } + } + + sprintf(cp, "LDR\tr%d, [r%d%s, #%s%u%s\t; %#2.2x", + (opcode >> 12) & 0xf, + rn, p1, + (opcode & 0x200) ? "" : "-", + immed, p2, immed); + return ERROR_OK; + } + + return ERROR_INVALID_ARGUMENTS; +} + /* * REVISIT for Thumb2 instructions, instruction->type and friends aren't * always set. That means eventual arm_simulate_step() support for Thumb2 @@ -3317,6 +3391,10 @@ else if ((opcode & 0x1e400000) == 0x08000000) retval = t2ev_ldm_stm(opcode, address, instruction, cp); + /* ARMv7-M: A5.3.7 Load word */ + else if ((opcode & 0x1f700000) == 0x18500000) + retval = t2ev_load_word(opcode, address, instruction, cp); + /* ARMv7-M: A5.3.10 Store single data item */ else if ((opcode & 0x1f100000) == 0x18000000) retval = t2ev_store_single(opcode, address, instruction, cp); |
From: <zw...@ma...> - 2009-07-16 01:49:09
|
Author: zwelch Date: 2009-07-16 01:49:05 +0200 (Thu, 16 Jul 2009) New Revision: 2541 Modified: trunk/src/target/arm_disassembler.c Log: David Brownell <da...@pa...>: More 32-bit Thumb2 instruction decoding: A5.3.12 Data processing (register) Modified: trunk/src/target/arm_disassembler.c =================================================================== --- trunk/src/target/arm_disassembler.c 2009-07-15 23:49:00 UTC (rev 2540) +++ trunk/src/target/arm_disassembler.c 2009-07-15 23:49:05 UTC (rev 2541) @@ -3153,6 +3153,107 @@ return ERROR_OK; } +static int t2ev_data_reg(uint32_t opcode, uint32_t address, + arm_instruction_t *instruction, char *cp) +{ + char *mnemonic; + char * suffix = ""; + + if (((opcode >> 4) & 0xf) == 0) { + switch ((opcode >> 21) & 0x7) { + case 0: + mnemonic = "LSL"; + break; + case 1: + mnemonic = "LSR"; + break; + case 2: + mnemonic = "ASR"; + break; + case 3: + mnemonic = "ROR"; + break; + default: + return ERROR_INVALID_ARGUMENTS; + } + + instruction->type = ARM_MOV; + if (opcode & (1 << 20)) + suffix = "S"; + sprintf(cp, "%s%s.W\tr%d, r%d, r%d", + mnemonic, suffix, + (opcode >> 8) & 0xf, + (opcode >> 16) & 0xf, + (opcode >> 0) & 0xf); + + } else if (opcode & (1 << 7)) { + switch ((opcode >> 24) & 0xf) { + case 0: + case 1: + case 4: + case 5: + switch ((opcode >> 4) & 0x3) { + case 1: + suffix = ", ROR #8"; + break; + case 2: + suffix = ", ROR #16"; + break; + case 3: + suffix = ", ROR #24"; + break; + } + sprintf(cp, "%cXT%c.W\tr%d, r%d%s", + (opcode & (1 << 24)) ? 'U' : 'S', + (opcode & (1 << 26)) ? 'B' : 'H', + (opcode >> 8) & 0xf, + (opcode >> 16) & 0xf, + suffix); + break; + case 8: + case 9: + case 0xa: + case 0xb: + if (opcode & (1 << 6)) + return ERROR_INVALID_ARGUMENTS; + if (~opcode & (0xff << 12)) + return ERROR_INVALID_ARGUMENTS; + if (!(opcode & (1 << 20))) + return ERROR_INVALID_ARGUMENTS; + + switch (((opcode >> 19) & 0x04) + | ((opcode >> 4) & 0x3)) { + case 0: + mnemonic = "REV.W"; + break; + case 1: + mnemonic = "REV16.W"; + break; + case 2: + mnemonic = "RBIT"; + break; + case 3: + mnemonic = "REVSH.W"; + break; + case 4: + mnemonic = "CLZ"; + break; + default: + return ERROR_INVALID_ARGUMENTS; + } + sprintf(cp, "%s\tr%d, r%d", + mnemonic, + (opcode >> 8) & 0xf, + (opcode >> 0) & 0xf); + break; + default: + return ERROR_INVALID_ARGUMENTS; + } + } + + return ERROR_OK; +} + /* * REVISIT for Thumb2 instructions, instruction->type and friends aren't * always set. That means eventual arm_simulate_step() support for Thumb2 @@ -3224,6 +3325,10 @@ else if ((opcode & 0x1e000000) == 0x0a000000) retval = t2ev_data_shift(opcode, address, instruction, cp); + /* ARMv7-M: A5.3.12 Data processing (register) */ + else if ((opcode & 0x1f000000) == 0x1a000000) + retval = t2ev_data_reg(opcode, address, instruction, cp); + /* ARMv7-M: A5.3.14 Multiply, and multiply accumulate */ else if ((opcode & 0x1f800000) == 0x1b000000) retval = t2ev_mul32(opcode, address, instruction, cp); |
From: <zw...@ma...> - 2009-07-16 01:49:03
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Author: zwelch Date: 2009-07-16 01:49:00 +0200 (Thu, 16 Jul 2009) New Revision: 2540 Modified: trunk/src/target/arm_disassembler.c Log: David Brownell <da...@pa...>: More 32-bit instruction decoding: A5.3.11 Data processing (shifted register) Modified: trunk/src/target/arm_disassembler.c =================================================================== --- trunk/src/target/arm_disassembler.c 2009-07-15 23:48:54 UTC (rev 2539) +++ trunk/src/target/arm_disassembler.c 2009-07-15 23:49:00 UTC (rev 2540) @@ -2989,6 +2989,170 @@ return ERROR_OK; } +static int t2ev_data_shift(uint32_t opcode, uint32_t address, + arm_instruction_t *instruction, char *cp) +{ + int op = (opcode >> 21) & 0xf; + int rd = (opcode >> 8) & 0xf; + int rn = (opcode >> 16) & 0xf; + int type = (opcode >> 4) & 0x3; + int immed = (opcode >> 6) & 0x3; + char *mnemonic; + char *suffix = ""; + + immed |= (opcode >> 10) & 0x7; + if (opcode & (1 << 21)) + suffix = "S"; + + switch (op) { + case 0: + if (rd == 0xf) { + if (!(opcode & (1 << 21))) + return ERROR_INVALID_ARGUMENTS; + instruction->type = ARM_TST; + mnemonic = "TST"; + goto two; + } + instruction->type = ARM_AND; + mnemonic = "AND"; + break; + case 1: + instruction->type = ARM_BIC; + mnemonic = "BIC"; + break; + case 2: + if (rn == 0xf) { + instruction->type = ARM_MOV; + switch (type) { + case 0: + if (immed == 0) { + sprintf(cp, "MOV%s.W\tr%d, r%d", + suffix, rd, (opcode & 0xf)); + return ERROR_OK; + } + mnemonic = "LSL"; + break; + case 1: + mnemonic = "LSR"; + break; + case 2: + mnemonic = "ASR"; + break; + default: + if (immed == 0) { + sprintf(cp, "RRX%s.W\tr%d, r%d", + suffix, rd, (opcode & 0xf)); + return ERROR_OK; + } + mnemonic = "ROR"; + break; + } + goto immediate; + } else { + instruction->type = ARM_ORR; + mnemonic = "ORR"; + } + break; + case 3: + if (rn == 0xf) { + instruction->type = ARM_MVN; + mnemonic = "MVN"; + rn = rd; + goto two; + } else { + // instruction->type = ARM_ORN; + mnemonic = "ORN"; + } + break; + case 4: + if (rd == 0xf) { + if (!(opcode & (1 << 21))) + return ERROR_INVALID_ARGUMENTS; + instruction->type = ARM_TEQ; + mnemonic = "TEQ"; + goto two; + } + instruction->type = ARM_EOR; + mnemonic = "EOR"; + break; + case 8: + if (rd == 0xf) { + if (!(opcode & (1 << 21))) + return ERROR_INVALID_ARGUMENTS; + instruction->type = ARM_CMN; + mnemonic = "CMN"; + goto two; + } + instruction->type = ARM_ADD; + mnemonic = "ADD"; + break; + case 0xa: + instruction->type = ARM_ADC; + mnemonic = "ADC"; + break; + case 0xb: + instruction->type = ARM_SBC; + mnemonic = "SBC"; + break; + case 0xd: + if (rd == 0xf) { + if (!(opcode & (1 << 21))) + return ERROR_INVALID_ARGUMENTS; + instruction->type = ARM_CMP; + mnemonic = "CMP"; + goto two; + } + instruction->type = ARM_SUB; + mnemonic = "SUB"; + break; + case 0xe: + instruction->type = ARM_RSB; + mnemonic = "RSB"; + break; + default: + return ERROR_INVALID_ARGUMENTS; + } + + sprintf(cp, "%s%s.W\tr%d, r%d, r%d", + mnemonic, suffix, rd, rn, (opcode & 0xf)); + +shift: + cp = strchr(cp, 0); + + switch (type) { + case 0: + if (immed == 0) + return ERROR_OK; + suffix = "LSL"; + break; + case 1: + suffix = "LSR"; + break; + case 2: + suffix = "ASR"; + break; + case 3: + if (immed == 0) { + strcpy(cp, "RRX"); + return ERROR_OK; + } + suffix = "ROR"; + break; + } + sprintf(cp, " %s #%d", suffix, immed ? immed : 32); + return ERROR_OK; + +two: + sprintf(cp, "%s%s.W\tr%d, r%d", + mnemonic, suffix, rn, (opcode & 0xf)); + goto shift; + +immediate: + sprintf(cp, "%s%s.W\tr%d, r%d, #%d", + mnemonic, suffix, rd, (opcode & 0xf), immed ? immed : 32); + return ERROR_OK; +} + /* * REVISIT for Thumb2 instructions, instruction->type and friends aren't * always set. That means eventual arm_simulate_step() support for Thumb2 @@ -3056,6 +3220,10 @@ else if ((opcode & 0x1f100000) == 0x18000000) retval = t2ev_store_single(opcode, address, instruction, cp); + /* ARMv7-M: A5.3.11 Data processing (shifted register) */ + else if ((opcode & 0x1e000000) == 0x0a000000) + retval = t2ev_data_shift(opcode, address, instruction, cp); + /* ARMv7-M: A5.3.14 Multiply, and multiply accumulate */ else if ((opcode & 0x1f800000) == 0x1b000000) retval = t2ev_mul32(opcode, address, instruction, cp); |