openocd-commit — OpenOCD commit maling list - read only

[Openocd-svn] r2539 - trunk/src/target

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-16 01:48:54 +0200 (Thu, 16 Jul 2009)
New Revision: 2539

Modified:
   trunk/src/target/arm_disassembler.c
Log:
David Brownell <da...@pa...>:

More instructions decoded:

	A5.3.5 Load/store multiple 

The preferred PUSH/POP syntax is shown when appropriate.


Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c	2009-07-15 23:48:43 UTC (rev 2538)
+++ trunk/src/target/arm_disassembler.c	2009-07-15 23:48:54 UTC (rev 2539)
@@ -2940,6 +2940,55 @@
 	return ERROR_OK;
 }
 
+static int t2ev_ldm_stm(uint32_t opcode, uint32_t address,
+		arm_instruction_t *instruction, char *cp)
+{
+	int rn = (opcode >> 16) & 0xf;
+	int op = (opcode >> 22) & 0x6;
+	int t = (opcode >> 21) & 1;
+	unsigned registers = opcode & 0xffff;
+
+	if (opcode & (1 << 20))
+		op |= 1;
+
+	switch (op) {
+	case 2:
+		sprintf(cp, "STMB\tr%d%s, ", rn, t ? "!" : "");
+		break;
+	case 3:
+		if (rn == 13 && t)
+			sprintf(cp, "POP\t");
+		else
+			sprintf(cp, "LDM\tr%d%s, ", rn, t ? "!" : "");
+		break;
+	case 4:
+		if (rn == 13 && t)
+			sprintf(cp, "PUSH\t");
+		else
+			sprintf(cp, "STM\tr%d%s, ", rn, t ? "!" : "");
+		break;
+	case 5:
+		sprintf(cp, "LDMB\tr%d%s, ", rn, t ? "!" : "");
+		break;
+	default:
+		return ERROR_INVALID_ARGUMENTS;
+	}
+
+	cp = strchr(cp, 0);
+	*cp++ = '{';
+	for (t = 0; registers; t++, registers >>= 1) {
+		if ((registers & 1) == 0)
+			continue;
+		registers &= ~1;
+		sprintf(cp, "r%d%s", t, registers ? "," : "");
+		cp = strchr(cp, 0);
+	}
+	*cp++ = '}';
+	*cp++ = 0;
+
+	return ERROR_OK;
+}
+
 /*
  * REVISIT for Thumb2 instructions, instruction->type and friends aren't
  * always set.  That means eventual arm_simulate_step() support for Thumb2
@@ -2999,6 +3048,10 @@
 	else if ((opcode & 0x18008000) == 0x10008000)
 		retval = t2ev_b_misc(opcode, address, instruction, cp);
 
+	/* ARMv7-M: A5.3.5 Load/store multiple */
+	else if ((opcode & 0x1e400000) == 0x08000000)
+		retval = t2ev_ldm_stm(opcode, address, instruction, cp);
+
 	/* ARMv7-M: A5.3.10 Store single data item */
 	else if ((opcode & 0x1f100000) == 0x18000000)
 		retval = t2ev_store_single(opcode, address, instruction, cp);

[Openocd-svn] r2538 - trunk/src/target

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-16 01:48:43 +0200 (Thu, 16 Jul 2009)
New Revision: 2538

Modified:
   trunk/src/target/arm_disassembler.c
Log:
David Brownell <da...@pa...>:

More instructions decoded:

	A5.3.14 Multiply, and multiply accumulate 
	A5.3.15 Long multiply, long multiply accumulate, divide

The EABI requires *adjacent* register pairs, but the long multiply
ops can use any pair of registers; interesting.


Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c	2009-07-15 23:48:37 UTC (rev 2537)
+++ trunk/src/target/arm_disassembler.c	2009-07-15 23:48:43 UTC (rev 2538)
@@ -2875,6 +2875,71 @@
 	return ERROR_OK;
 }
 
+static int t2ev_mul32(uint32_t opcode, uint32_t address,
+		arm_instruction_t *instruction, char *cp)
+{
+	int ra = (opcode >> 12) & 0xf;
+
+
+	switch (opcode & 0x007000f0) {
+	case 0:
+		if (ra == 0xf)
+			sprintf(cp, "MUL\tr%d, r%d, r%d",
+				(opcode >> 8) & 0xf, (opcode >> 16) & 0xf,
+				(opcode >> 0) & 0xf);
+		else
+			sprintf(cp, "MLA\tr%d, r%d, r%d, r%d",
+				(opcode >> 8) & 0xf, (opcode >> 16) & 0xf,
+				(opcode >> 0) & 0xf, ra);
+		break;
+	case 0x10:
+		sprintf(cp, "MLS\tr%d, r%d, r%d, r%d",
+			(opcode >> 8) & 0xf, (opcode >> 16) & 0xf,
+			(opcode >> 0) & 0xf, ra);
+		break;
+	default:
+		return ERROR_INVALID_ARGUMENTS;
+	}
+	return ERROR_OK;
+}
+
+static int t2ev_mul64_div(uint32_t opcode, uint32_t address,
+		arm_instruction_t *instruction, char *cp)
+{
+	int op = (opcode >> 4) & 0xf;
+	char *infix = "MUL";
+
+	op += (opcode >> 16) & 0x70;
+	switch (op) {
+	case 0x40:
+	case 0x60:
+		infix = "MLA";
+		/* FALLTHROUGH */
+	case 0:
+	case 0x20:
+		sprintf(cp, "%c%sL\tr%d, r%d, r%d, r%d",
+				(op & 0x20) ? 'U' : 'S',
+				infix,
+				(opcode >> 12) & 0xf,
+				(opcode >> 8) & 0xf,
+				(opcode >> 16) & 0xf,
+				(opcode >> 0) & 0xf);
+		break;
+	case 0x1f:
+	case 0x3f:
+		sprintf(cp, "%cDIV\tr%d, r%d, r%d",
+				(op & 0x20) ? 'U' : 'S',
+				(opcode >> 8) & 0xf,
+				(opcode >> 16) & 0xf,
+				(opcode >> 0) & 0xf);
+		break;
+	default:
+		return ERROR_INVALID_ARGUMENTS;
+	}
+
+	return ERROR_OK;
+}
+
 /*
  * REVISIT for Thumb2 instructions, instruction->type and friends aren't
  * always set.  That means eventual arm_simulate_step() support for Thumb2
@@ -2938,6 +3003,14 @@
 	else if ((opcode & 0x1f100000) == 0x18000000)
 		retval = t2ev_store_single(opcode, address, instruction, cp);
 
+	/* ARMv7-M: A5.3.14 Multiply, and multiply accumulate */
+	else if ((opcode & 0x1f800000) == 0x1b000000)
+		retval = t2ev_mul32(opcode, address, instruction, cp);
+
+	/* ARMv7-M: A5.3.15 Long multiply, long multiply accumulate, divide */
+	else if ((opcode & 0x1f800000) == 0x1b800000)
+		retval = t2ev_mul64_div(opcode, address, instruction, cp);
+
 	/* FIXME decode more 32-bit instructions */
 
 	if (retval == ERROR_OK)

[Openocd-svn] r2537 - trunk/src/target

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-16 01:48:37 +0200 (Thu, 16 Jul 2009)
New Revision: 2537

Modified:
   trunk/src/target/arm_disassembler.c
Log:
David Brownell <da...@pa...>:

More Thumb2 32-bit opcode support:

	 A5.3.10 Store single data item 

Byte, word, halfword.  Offset, pre-index, post-index.  And
a "make like you're unprivileged" option when using small
immediate offsets.


Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c	2009-07-15 23:48:32 UTC (rev 2536)
+++ trunk/src/target/arm_disassembler.c	2009-07-15 23:48:37 UTC (rev 2537)
@@ -2783,6 +2783,98 @@
 	return ERROR_OK;
 }
 
+static int t2ev_store_single(uint32_t opcode, uint32_t address,
+		arm_instruction_t *instruction, char *cp)
+{
+	unsigned op = (opcode >> 20) & 0xf;
+	char *size = "";
+	char *suffix = "";
+	char *p1 = "";
+	char *p2 = "]";
+	unsigned immed;
+	unsigned rn = (opcode >> 16) & 0x0f;
+	unsigned rt = (opcode >> 12) & 0x0f;
+
+	if (rn == 0xf)
+		return ERROR_INVALID_ARGUMENTS;
+
+	if (opcode & 0x0800)
+		op |= 1;
+	switch (op) {
+	/* byte */
+	case 0x8:
+	case 0x9:
+		size = "B";
+		goto imm12;
+	case 0x1:
+		size = "B";
+		goto imm8;
+	case 0x0:
+		size = "B";
+		break;
+	/* halfword */
+	case 0xa:
+	case 0xb:
+		size = "H";
+		goto imm12;
+	case 0x3:
+		size = "H";
+		goto imm8;
+	case 0x2:
+		size = "H";
+		break;
+	/* word */
+	case 0xc:
+	case 0xd:
+		goto imm12;
+	case 0x5:
+		goto imm8;
+	case 0x4:
+		break;
+	/* error */
+	default:
+		return ERROR_INVALID_ARGUMENTS;
+	}
+
+	sprintf(cp, "STR%s.W\tr%d, [r%d, r%d, LSL #%d]",
+			size, rt, rn, opcode & 0x0f,
+			(opcode >> 4) & 0x03);
+
+imm12:
+	immed = opcode & 0x0fff;
+	sprintf(cp, "STR%s.W\tr%d, [r%d, #%u]\t; %#3.3x",
+			size, rt, rn, immed, immed);
+	return ERROR_OK;
+
+imm8:
+	immed = opcode & 0x00ff;
+
+	switch (opcode & 0x700) {
+	case 0x600:
+		suffix = "T";
+		break;
+	case 0x000:
+	case 0x200:
+		return ERROR_INVALID_ARGUMENTS;
+	}
+
+	/* two indexed modes will write back rn */
+	if (opcode & 0x100) {
+		if (opcode & 0x400)	/* pre-indexed */
+			p2 = "]!";
+		else {			/* post-indexed */
+			p1 = "]";
+			p2 = "";
+		}
+	}
+
+	sprintf(cp, "STR%s%s\tr%d, [r%d%s, #%s%u%s\t; %#2.2x",
+			size, suffix, rt, rn, p1,
+			(opcode & 0x200) ? "" : "-",
+			immed, p2, immed);
+	return ERROR_OK;
+}
+
 /*
  * REVISIT for Thumb2 instructions, instruction->type and friends aren't
  * always set.  That means eventual arm_simulate_step() support for Thumb2
@@ -2842,6 +2934,10 @@
 	else if ((opcode & 0x18008000) == 0x10008000)
 		retval = t2ev_b_misc(opcode, address, instruction, cp);
 
+	/* ARMv7-M: A5.3.10 Store single data item */
+	else if ((opcode & 0x1f100000) == 0x18000000)
+		retval = t2ev_store_single(opcode, address, instruction, cp);
+
 	/* FIXME decode more 32-bit instructions */
 
 	if (retval == ERROR_OK)

[Openocd-svn] r2536 - trunk/src/target

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-16 01:48:32 +0200 (Thu, 16 Jul 2009)
New Revision: 2536

Modified:
   trunk/src/target/arm_disassembler.c
Log:
David Brownell <da...@pa...>:

Print old-style Thumb NOP instructions as such.  (GCC uses "mov r8, r8"
instead of the architected NOP which is new in Thumb2.)


Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c	2009-07-15 23:48:27 UTC (rev 2535)
+++ trunk/src/target/arm_disassembler.c	2009-07-15 23:48:32 UTC (rev 2536)
@@ -1512,6 +1512,7 @@
 {
 	uint8_t high_reg, op, Rm, Rd,H1,H2;
 	char *mnemonic = NULL;
+	bool nop = false;
 
 	high_reg = (opcode & 0x0400) >> 10;
 	op = (opcode & 0x03C0) >> 6;
@@ -1546,6 +1547,8 @@
 			case 0x2:
 				instruction->type = ARM_MOV;
 				mnemonic = "MOV";
+				if (Rd == Rm)
+					nop = true;
 				break;
 			case 0x3:
 				if ((opcode & 0x7) == 0x0)
@@ -1671,9 +1674,15 @@
 		}
 	}
 
-	snprintf(instruction->text, 128,
-			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, r%i",
-			 address, opcode, mnemonic, Rd, Rm);
+	if (nop)
+		snprintf(instruction->text, 128,
+				"0x%8.8" PRIx32 "  0x%4.4x    \tNOP\t\t\t"
+				"; (%s r%i, r%i)",
+				 address, opcode, mnemonic, Rd, Rm);
+	else
+		snprintf(instruction->text, 128,
+				"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, r%i",
+				 address, opcode, mnemonic, Rd, Rm);
 
 	return ERROR_OK;
 }

[Openocd-svn] r2535 - trunk/src/target

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-16 01:48:27 +0200 (Thu, 16 Jul 2009)
New Revision: 2535

Modified:
   trunk/src/target/arm_disassembler.c
Log:
David Brownell <da...@pa...>:

Make disassembly of the Thumb load-literal instruction show the
address of the literal being loaded (so users can avoid doing
that math themselves).  Add and use an Align(PC,4) utility.


Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c	2009-07-15 23:48:21 UTC (rev 2534)
+++ trunk/src/target/arm_disassembler.c	2009-07-15 23:48:27 UTC (rev 2535)
@@ -1678,6 +1678,12 @@
 	return ERROR_OK;
 }
 
+/* PC-relative data addressing is word-aligned even with Thumb */
+static inline uint32_t thumb_alignpc4(uint32_t addr)
+{
+	return (addr + 4) & ~3;
+}
+
 int evaluate_load_literal_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
 	uint32_t immediate;
@@ -1685,17 +1691,20 @@
 
 	instruction->type = ARM_LDR;
 	immediate = opcode & 0x000000ff;
+	immediate *= 4;
 
-	snprintf(instruction->text, 128,
-		"0x%8.8" PRIx32 "  0x%4.4x    \tLDR\tr%i, [pc, #%#" PRIx32 "]",
-		address, opcode, Rd, immediate*4);
-
 	instruction->info.load_store.Rd = Rd;
 	instruction->info.load_store.Rn = 15 /*PC*/;
 	instruction->info.load_store.index_mode = 0; /*offset*/
 	instruction->info.load_store.offset_mode = 0; /*immediate*/
-	instruction->info.load_store.offset.offset = immediate*4;
+	instruction->info.load_store.offset.offset = immediate;
 
+	snprintf(instruction->text, 128,
+		"0x%8.8" PRIx32 "  0x%4.4x    \t"
+		"LDR\tr%i, [pc, #%#" PRIx32 "]\t; %#8.8x",
+		address, opcode, Rd, immediate,
+		thumb_alignpc4(address) + immediate);
+
 	return ERROR_OK;
 }
 
@@ -2753,8 +2762,7 @@
 	return ERROR_OK;
 
 do_adr:
-	address &= ~0x03;
-	address += 4;
+	address = thumb_alignpc4(address);
 	if (add)
 		address += immed;
 	else

[Openocd-svn] r2534 - trunk/src/target

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-16 01:48:21 +0200 (Thu, 16 Jul 2009)
New Revision: 2534

Modified:
   trunk/src/target/arm_disassembler.c
Log:
David Brownell <da...@pa...>:

Make the Thumb2 disassembler handle more 32-bit instructions:

  A5.3.3 Data processing (plain binary immediate)

These use mostly twelve bit literals, but there are also bitfield
and saturated add primitives.


Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c	2009-07-15 23:48:16 UTC (rev 2533)
+++ trunk/src/target/arm_disassembler.c	2009-07-15 23:48:21 UTC (rev 2534)
@@ -2671,6 +2671,101 @@
 	return ERROR_OK;
 }
 
+static int t2ev_data_immed(uint32_t opcode, uint32_t address,
+		arm_instruction_t *instruction, char *cp)
+{
+	char *mnemonic = NULL;
+	int rn = (opcode >> 16) & 0xf;
+	int rd = (opcode >> 8) & 0xf;
+	unsigned immed;
+	bool add = false;
+	bool is_signed = false;
+
+	immed = (opcode & 0x0ff) | ((opcode & 0x7000) >> 12);
+	if (opcode & (1 << 27))
+		immed |= (1 << 11);
+
+	switch ((opcode >> 20) & 0x1f) {
+	case 0:
+		if (rn == 0xf) {
+			add = true;
+			goto do_adr;
+		}
+		mnemonic = "ADD.W";
+		break;
+	case 4:
+		mnemonic = "MOV.W";
+		break;
+	case 0x0a:
+		if (rn == 0xf)
+			goto do_adr;
+		mnemonic = "SUB.W";
+		break;
+	case 0x0c:
+		/* move constant to top 16 bits of register */
+		immed |= (opcode >> 4) & 0xf000;
+		sprintf(cp, "MOVT\tr%d, #%d\t; %#4.4x", rn, immed, immed);
+		return ERROR_OK;
+	case 0x10:
+	case 0x12:
+		is_signed = true;
+	case 0x18:
+	case 0x1a:
+		/* signed/unsigned saturated add */
+		immed = (opcode >> 6) & 0x03;
+		immed |= (opcode >> 10) & 0x1c;
+		sprintf(cp, "%sSAT\tr%d, #%d, r%d, %s #%d\t",
+				is_signed ? "S" : "U",
+				rd, (opcode & 0x1f) + 1, rn,
+				(opcode & (1 << 21)) ? "ASR" : "LSL",
+				immed ? immed : 32);
+		return ERROR_OK;
+	case 0x14:
+		is_signed = true;
+		/* FALLTHROUGH */
+	case 0x1c:
+		/* signed/unsigned bitfield extract */
+		immed = (opcode >> 6) & 0x03;
+		immed |= (opcode >> 10) & 0x1c;
+		sprintf(cp, "%sBFX\tr%d, r%d, #%d, #%d\t",
+				is_signed ? "S" : "U",
+				rd, rn, immed,
+				(opcode & 0x1f) + 1);
+		return ERROR_OK;
+	case 0x16:
+		immed = (opcode >> 6) & 0x03;
+		immed |= (opcode >> 10) & 0x1c;
+		if (rn == 0xf)		/* bitfield clear */
+			sprintf(cp, "BFC\tr%d, #%d, #%d\t",
+					rd, immed,
+					(opcode & 0x1f) + 1 - immed);
+		else			/* bitfield insert */
+			sprintf(cp, "BFI\tr%d, r%d, #%d, #%d\t",
+					rd, rn, immed,
+					(opcode & 0x1f) + 1 - immed);
+		return ERROR_OK;
+	default:
+		return ERROR_INVALID_ARGUMENTS;
+	}
+
+	sprintf(cp, "%s\tr%d, r%d, #%d\t; %#3.3x", mnemonic,
+			rd, rn, immed, immed);
+	return ERROR_OK;
+
+do_adr:
+	address &= ~0x03;
+	address += 4;
+	if (add)
+		address += immed;
+	else
+		address -= immed;
+	/* REVISIT "ADD/SUB Rd, PC, #const ; 0x..." might be better;
+	 * not hiding the pc-relative stuff will sometimes be useful.
+	 */
+	sprintf(cp, "ADR.W\tr%d, %#8.8" PRIx32, rd, address);
+	return ERROR_OK;
+}
+
 /*
  * REVISIT for Thumb2 instructions, instruction->type and friends aren't
  * always set.  That means eventual arm_simulate_step() support for Thumb2
@@ -2722,6 +2817,10 @@
 	if ((opcode & 0x1a008000) == 0x10000000)
 		retval = t2ev_data_mod_immed(opcode, address, instruction, cp);
 
+	/* ARMv7-M: A5.3.3 Data processing (plain binary immediate) */
+	else if ((opcode & 0x1a008000) == 0x12000000)
+		retval = t2ev_data_immed(opcode, address, instruction, cp);
+
 	/* ARMv7-M: A5.3.4 Branches and miscellaneous control */
 	else if ((opcode & 0x18008000) == 0x10008000)
 		retval = t2ev_b_misc(opcode, address, instruction, cp);

[Openocd-svn] r2533 - trunk/src/target

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-16 01:48:16 +0200 (Thu, 16 Jul 2009)
New Revision: 2533

Modified:
   trunk/src/target/arm_disassembler.c
Log:
David Brownell <da...@pa...>:

Make the Thumb2 disassembler handle more 32-bit instructions:

  A5.3.1 Data processing (modified immediate)

My small sample shows GCC likes to use many of these instructions.


Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c	2009-07-15 23:48:11 UTC (rev 2532)
+++ trunk/src/target/arm_disassembler.c	2009-07-15 23:48:16 UTC (rev 2533)
@@ -2532,7 +2532,145 @@
 	return ERROR_INVALID_ARGUMENTS;
 }
 
+static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address,
+		arm_instruction_t *instruction, char *cp)
+{
+	char *mnemonic = NULL;
+	int rn = (opcode >> 16) & 0xf;
+	int rd = (opcode >> 8) & 0xf;
+	unsigned immed = opcode & 0xff;
+	unsigned func;
+	bool one = false;
+	char *suffix = "";
 
+	/* ARMv7-M: A5.3.2 Modified immediate constants */
+	func = (opcode >> 11) & 0x0e;
+	if (immed & 0x80)
+		func |= 1;
+	if (opcode & (1 << 26))
+		func |= 0x10;
+
+	/* "Modified" immediates */
+	switch (func >> 1) {
+	case 0:
+		break;
+	case 2:
+		immed <<= 8;
+		/* FALLTHROUGH */
+	case 1:
+		immed += immed << 16;
+		break;
+	case 3:
+		immed += immed << 8;
+		immed += immed << 16;
+		break;
+	default:
+		immed |= 0x80;
+		immed = ror(immed, func);
+	}
+
+	if (opcode & (1 << 20))
+		suffix = "S";
+
+	switch ((opcode >> 21) & 0xf) {
+	case 0:
+		if (rd == 0xf) {
+			instruction->type = ARM_TST;
+			mnemonic = "TST";
+			one = true;
+			suffix = "";
+			rd = rn;
+		} else {
+			instruction->type = ARM_AND;
+			mnemonic = "AND";
+		}
+		break;
+	case 1:
+		instruction->type = ARM_BIC;
+		mnemonic = "BIC";
+		break;
+	case 2:
+		if (rn == 0xf) {
+			instruction->type = ARM_MOV;
+			mnemonic = "MOV";
+			one = true;
+		} else {
+			instruction->type = ARM_ORR;
+			mnemonic = "ORR";
+		}
+		break;
+	case 3:
+		if (rn == 0xf) {
+			instruction->type = ARM_MVN;
+			mnemonic = "MVN";
+			one = true;
+		} else {
+			// instruction->type = ARM_ORN;
+			mnemonic = "ORN";
+		}
+		break;
+	case 4:
+		if (rd == 0xf) {
+			instruction->type = ARM_TEQ;
+			mnemonic = "TEQ";
+			one = true;
+			suffix = "";
+			rd = rn;
+		} else {
+			instruction->type = ARM_EOR;
+			mnemonic = "EOR";
+		}
+		break;
+	case 8:
+		if (rd == 0xf) {
+			instruction->type = ARM_CMN;
+			mnemonic = "CMN";
+			one = true;
+			suffix = "";
+			rd = rn;
+		} else {
+			instruction->type = ARM_ADD;
+			mnemonic = "ADD";
+		}
+		break;
+	case 10:
+		instruction->type = ARM_ADC;
+		mnemonic = "ADC";
+		break;
+	case 11:
+		instruction->type = ARM_SBC;
+		mnemonic = "SBC";
+		break;
+	case 13:
+		if (rd == 0xf) {
+			instruction->type = ARM_CMP;
+			mnemonic = "CMP";
+			one = true;
+			suffix = "";
+			rd = rn;
+		} else {
+			instruction->type = ARM_SUB;
+			mnemonic = "SUB";
+		}
+		break;
+	case 14:
+		instruction->type = ARM_RSB;
+		mnemonic = "RSB";
+		break;
+	default:
+		return ERROR_INVALID_ARGUMENTS;
+	}
+
+	if (one)
+		sprintf(cp, "%s\tr%d, #%d\t; %#8.8x",
+				mnemonic, rd, immed, immed);
+	else
+		sprintf(cp, "%s%s\tr%d, r%d, #%d\t; %#8.8x",
+				mnemonic, suffix, rd, rn, immed, immed);
+
+	return ERROR_OK;
+}
+
 /*
  * REVISIT for Thumb2 instructions, instruction->type and friends aren't
  * always set.  That means eventual arm_simulate_step() support for Thumb2
@@ -2580,8 +2718,12 @@
 	cp = strchr(instruction->text, 0);
 	retval = ERROR_FAIL;
 
+	/* ARMv7-M: A5.3.1 Data processing (modified immediate) */
+	if ((opcode & 0x1a008000) == 0x10000000)
+		retval = t2ev_data_mod_immed(opcode, address, instruction, cp);
+
 	/* ARMv7-M: A5.3.4 Branches and miscellaneous control */
-	if ((opcode & 0x18008000) == 0x10008000)
+	else if ((opcode & 0x18008000) == 0x10008000)
 		retval = t2ev_b_misc(opcode, address, instruction, cp);
 
 	/* FIXME decode more 32-bit instructions */

[Openocd-svn] r2532 - trunk/src/target

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-16 01:48:11 +0200 (Thu, 16 Jul 2009)
New Revision: 2532

Modified:
   trunk/src/target/arm_disassembler.c
Log:
David Brownell <da...@pa...>:

Make the Thumb2 disassembler handle a bunch of 32-bit instructions:

  A5.3.4 Branches and miscellaneous control
 
Note that this shifts some responsabililty out of helper functions,
making the code and layout simpler for 32-bit decoders:  they only
need to know how to format the instruction and its parameters.

Also, technical note:  with this patch, Thumb1 decoders could now
call the Thumb2 decoder if they wanted to get nicer treatment of
the exiting 32-bit B/BLX instructions.


Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c	2009-07-15 23:39:48 UTC (rev 2531)
+++ trunk/src/target/arm_disassembler.c	2009-07-15 23:48:11 UTC (rev 2532)
@@ -2292,6 +2292,247 @@
 	return -1;
 }
 
+static int t2ev_b_bl(uint32_t opcode, uint32_t address,
+		arm_instruction_t *instruction, char *cp)
+{
+	unsigned offset;
+	unsigned b21 = 1 << 21;
+	unsigned b22 = 1 << 22;
+
+	/* instead of combining two smaller 16-bit branch instructions,
+	 * Thumb2 uses only one larger 32-bit instruction.
+	 */
+	offset = opcode & 0x7ff;
+	offset |= (opcode & 0x03ff0000) >> 5;
+	if (opcode & (1 << 26)) {
+		offset |= 0xff << 23;
+		if ((opcode & (1 << 11)) == 0)
+			b21 = 0;
+		if ((opcode & (1 << 13)) == 0)
+			b22 = 0;
+	} else {
+		if (opcode & (1 << 11))
+			b21 = 0;
+		if (opcode & (1 << 13))
+			b22 = 0;
+	}
+	offset |= b21;
+	offset |= b22;
+
+
+	address += 4;
+	address += offset << 1;
+
+	instruction->type = (opcode & (1 << 14)) ? ARM_BL : ARM_B;
+	instruction->info.b_bl_bx_blx.reg_operand = -1;
+	instruction->info.b_bl_bx_blx.target_address = address;
+	sprintf(cp, "%s\t%#8.8" PRIx32,
+			(opcode & (1 << 14)) ? "BL" : "B.W",
+			address);
+
+	return ERROR_OK;
+}
+
+static int t2ev_cond_b(uint32_t opcode, uint32_t address,
+		arm_instruction_t *instruction, char *cp)
+{
+	unsigned offset;
+	unsigned b17 = 1 << 17;
+	unsigned b18 = 1 << 18;
+	unsigned cond = (opcode >> 22) & 0x0f;
+
+	offset = opcode & 0x7ff;
+	offset |= (opcode & 0x003f0000) >> 5;
+	if (opcode & (1 << 26)) {
+		offset |= 0xffff << 19;
+		if ((opcode & (1 << 11)) == 0)
+			b17 = 0;
+		if ((opcode & (1 << 13)) == 0)
+			b18 = 0;
+	} else {
+		if (opcode & (1 << 11))
+			b17 = 0;
+		if (opcode & (1 << 13))
+			b18 = 0;
+	}
+	offset |= b17;
+	offset |= b18;
+
+	address += 4;
+	address += offset << 1;
+
+	instruction->type = ARM_B;
+	instruction->info.b_bl_bx_blx.reg_operand = -1;
+	instruction->info.b_bl_bx_blx.target_address = address;
+	sprintf(cp, "B%s.W\t%#8.8" PRIx32,
+			arm_condition_strings[cond],
+			address);
+
+	return ERROR_OK;
+}
+
+static const char *special_name(int number)
+{
+	char *special = "(RESERVED)";
+
+	switch (number) {
+	case 0:
+		special = "apsr";
+		break;
+	case 1:
+		special = "iapsr";
+		break;
+	case 2:
+		special = "eapsr";
+		break;
+	case 3:
+		special = "xpsr";
+		break;
+	case 5:
+		special = "ipsr";
+		break;
+	case 6:
+		special = "epsr";
+		break;
+	case 7:
+		special = "iepsr";
+		break;
+	case 8:
+		special = "msp";
+		break;
+	case 9:
+		special = "psp";
+		break;
+	case 16:
+		special = "primask";
+		break;
+	case 17:
+		special = "basepri";
+		break;
+	case 18:
+		special = "basepri_max";
+		break;
+	case 19:
+		special = "faultmask";
+		break;
+	case 20:
+		special = "control";
+		break;
+	}
+	return special;
+}
+
+static int t2ev_hint(uint32_t opcode, uint32_t address,
+		arm_instruction_t *instruction, char *cp)
+{
+	const char *mnemonic;
+
+	if (opcode & 0x0700) {
+		instruction->type = ARM_UNDEFINED_INSTRUCTION;
+		strcpy(cp, "UNDEFINED");
+		return ERROR_OK;
+	}
+
+	if (opcode & 0x00f0) {
+		sprintf(cp, "DBG\t#%d", opcode & 0xf);
+		return ERROR_OK;
+	}
+
+	switch (opcode & 0x0f) {
+	case 0:
+		mnemonic = "NOP.W";
+		break;
+	case 1:
+		mnemonic = "YIELD.W";
+		break;
+	case 2:
+		mnemonic = "WFE.W";
+		break;
+	case 3:
+		mnemonic = "WFI.W";
+		break;
+	case 4:
+		mnemonic = "SEV.W";
+		break;
+	default:
+		mnemonic = "HINT.W (UNRECOGNIZED)";
+		break;
+	}
+	strcpy(cp, mnemonic);
+	return ERROR_OK;
+}
+
+static int t2ev_misc(uint32_t opcode, uint32_t address,
+		arm_instruction_t *instruction, char *cp)
+{
+	const char *mnemonic;
+
+	switch ((opcode >> 4) & 0x0f) {
+	case 2:
+		mnemonic = "CLREX";
+		break;
+	case 4:
+		mnemonic = "DSB";
+		break;
+	case 5:
+		mnemonic = "DMB";
+		break;
+	case 6:
+		mnemonic = "ISB";
+		break;
+	default:
+		return ERROR_INVALID_ARGUMENTS;
+	}
+	strcpy(cp, mnemonic);
+	return ERROR_OK;
+}
+
+static int t2ev_b_misc(uint32_t opcode, uint32_t address,
+		arm_instruction_t *instruction, char *cp)
+{
+	/* permanently undefined */
+	if ((opcode & 0x07f07000) == 0x07f02000) {
+		instruction->type = ARM_UNDEFINED_INSTRUCTION;
+		strcpy(cp, "UNDEFINED");
+		return ERROR_OK;
+	}
+
+	switch ((opcode >> 12) & 0x5) {
+	case 0x1:
+	case 0x5:
+		return t2ev_b_bl(opcode, address, instruction, cp);
+	case 0x4:
+		goto undef;
+	case 0:
+		if (((opcode >> 23) & 0x07) == 0x07)
+			return t2ev_cond_b(opcode, address, instruction, cp);
+		if (opcode & (1 << 26))
+			goto undef;
+		break;
+	}
+
+	switch ((opcode >> 20) & 0x7f) {
+	case 0x38:
+	case 0x39:
+		sprintf(cp, "MSR\t%s, r%d", special_name(opcode & 0xff),
+				(opcode >> 16) & 0x0f);
+		return ERROR_OK;
+	case 0x3a:
+		return t2ev_hint(opcode, address, instruction, cp);
+	case 0x3b:
+		return t2ev_misc(opcode, address, instruction, cp);
+	case 0x3e:
+	case 0x3f:
+		sprintf(cp, "MRS\tr%d, %s", (opcode >> 16) & 0x0f,
+				special_name(opcode & 0xff));
+		return ERROR_OK;
+	}
+
+undef:
+	return ERROR_INVALID_ARGUMENTS;
+}
+
+
 /*
  * REVISIT for Thumb2 instructions, instruction->type and friends aren't
  * always set.  That means eventual arm_simulate_step() support for Thumb2
@@ -2302,6 +2543,7 @@
 	int retval;
 	uint16_t op;
 	uint32_t opcode;
+	char *cp;
 
 	/* clear low bit ... it's set on function pointers */
 	address &= ~1;
@@ -2332,13 +2574,30 @@
 		return thumb_evaluate_opcode(op, address, instruction);
 	}
 
-	/* FIXME decode the 32-bit instructions */
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "  0x%8.8" PRIx32 "\t",
+			address, opcode);
+	cp = strchr(instruction->text, 0);
+	retval = ERROR_FAIL;
 
+	/* ARMv7-M: A5.3.4 Branches and miscellaneous control */
+	if ((opcode & 0x18008000) == 0x10008000)
+		retval = t2ev_b_misc(opcode, address, instruction, cp);
+
+	/* FIXME decode more 32-bit instructions */
+
+	if (retval == ERROR_OK)
+		return retval;
+
+	if (retval == ERROR_INVALID_ARGUMENTS) {
+		instruction->type = ARM_UNDEFINED_INSTRUCTION;
+		strcpy(cp, "UNDEFINED OPCODE");
+		return ERROR_OK;
+	}
+
 	LOG_DEBUG("Can't decode 32-bit Thumb2 yet (opcode=%08x)", opcode);
 
-	snprintf(instruction->text, 128,
-			"0x%8.8" PRIx32 "  0x%8.8x\t... 32-bit Thumb2 ...",
-			address, opcode);
+	strcpy(cp, "(32-bit Thumb2 ...)");
 	return ERROR_OK;
 }
 

[Openocd-svn] r2531 - trunk/src/target

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-16 01:39:48 +0200 (Thu, 16 Jul 2009)
New Revision: 2531

Modified:
   trunk/src/target/arm_disassembler.c
Log:
David Brownell <da...@pa...>:

Change layout of Thumb disassembly to work better with Thumb2:

 - Move opcode to the left, allowing space for four hex bytes:
    * after address, two spaces not one tab (taking 6 spaces)
    * after 2-byte opcode, four spaces before tab
 - Also, after opcode mnemonic use a tab not a space, to make
   operands line up

Sample output (after some patches decoding a few 32-bit instructions):

0x00003e5a  0xf4423200	ORR	r2, r2, #131072	; 0x20000
0x00003e5e  0x601a    	STR 	r2, [r3, #0x0]
0x00003e60  0x2800    	CMP	r0, #0x00
0x00003e62  0xd1f3    	BNE	0x00003e4c
0x00003e64  0xf008fa38	BL	0x0000c2d8

The affected lines of code now wrap at sane margins too.


Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c	2009-07-15 23:39:37 UTC (rev 2530)
+++ trunk/src/target/arm_disassembler.c	2009-07-15 23:39:48 UTC (rev 2531)
@@ -1367,7 +1367,9 @@
 	 * Might be simplest to always use the Thumb2 decoder.
 	 */
 
-	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s 0x%8.8" PRIx32 , address, opcode,mnemonic, target_address);
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\t%#8.8" PRIx32,
+			address, opcode, mnemonic, target_address);
 
 	instruction->info.b_bl_bx_blx.reg_operand = -1;
 	instruction->info.b_bl_bx_blx.target_address = target_address;
@@ -1403,15 +1405,17 @@
 	{
 		instruction->info.data_proc.variant = 0; /*immediate*/
 		instruction->info.data_proc.shifter_operand.immediate.immediate = Rm_imm;
-		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i, #%d",
-				 address, opcode, mnemonic, Rd, Rn, Rm_imm);
+		snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, r%i, #%d",
+			address, opcode, mnemonic, Rd, Rn, Rm_imm);
 	}
 	else
 	{
 		instruction->info.data_proc.variant = 1; /*immediate shift*/
 		instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm_imm;
-		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i, r%i",
-				 address, opcode, mnemonic, Rd, Rn, Rm_imm);
+		snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, r%i, r%i",
+			address, opcode, mnemonic, Rd, Rn, Rm_imm);
 	}
 
 	return ERROR_OK;
@@ -1455,8 +1459,9 @@
 	instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm;
 	instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = imm;
 
-	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i, #0x%02x" ,
-				 address, opcode, mnemonic, Rd, Rm, imm);
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, r%i, #%#2.2x" ,
+			address, opcode, mnemonic, Rd, Rm, imm);
 
 	return ERROR_OK;
 }
@@ -1496,8 +1501,9 @@
 			break;
 	}
 
-	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, #0x%02x" ,
-				 address, opcode, mnemonic, Rd, imm);
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, #%#2.2x",
+			address, opcode, mnemonic, Rd, imm);
 
 	return ERROR_OK;
 }
@@ -1548,18 +1554,28 @@
 					if (H1)
 					{
 						instruction->type = ARM_BLX;
-						snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tBLX r%i", address, opcode, Rm);
+						snprintf(instruction->text, 128,
+							"0x%8.8" PRIx32
+							"  0x%4.4x    \tBLX\tr%i",
+							address, opcode, Rm);
 					}
 					else
 					{
 						instruction->type = ARM_BX;
-						snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tBX r%i", address, opcode, Rm);
+						snprintf(instruction->text, 128,
+							"0x%8.8" PRIx32
+							"  0x%4.4x    \tBX\tr%i",
+							address, opcode, Rm);
 					}
 				}
 				else
 				{
 					instruction->type = ARM_UNDEFINED_INSTRUCTION;
-					snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
+					snprintf(instruction->text, 128,
+						"0x%8.8" PRIx32
+						"  0x%4.4x    \t"
+						"UNDEFINED INSTRUCTION",
+						address, opcode);
 				}
 				return ERROR_OK;
 				break;
@@ -1655,8 +1671,9 @@
 		}
 	}
 
-	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i",
-				 address, opcode, mnemonic, Rd, Rm);
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, r%i",
+			 address, opcode, mnemonic, Rd, Rm);
 
 	return ERROR_OK;
 }
@@ -1669,7 +1686,9 @@
 	instruction->type = ARM_LDR;
 	immediate = opcode & 0x000000ff;
 
-	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tLDR r%i, [PC, #0x%" PRIx32 "]", address, opcode, Rd, immediate*4);
+	snprintf(instruction->text, 128,
+		"0x%8.8" PRIx32 "  0x%4.4x    \tLDR\tr%i, [pc, #%#" PRIx32 "]",
+		address, opcode, Rd, immediate*4);
 
 	instruction->info.load_store.Rd = Rd;
 	instruction->info.load_store.Rn = 15 /*PC*/;
@@ -1724,7 +1743,9 @@
 			break;
 	}
 
-	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, [r%i, r%i]", address, opcode, mnemonic, Rd, Rn, Rm);
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, [r%i, r%i]",
+			address, opcode, mnemonic, Rd, Rn, Rm);
 
 	instruction->info.load_store.Rd = Rd;
 	instruction->info.load_store.Rn = Rn;
@@ -1768,7 +1789,9 @@
 		shift = 0;
 	}
 
-	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s%c r%i, [r%i, #0x%" PRIx32 "]", address, opcode, mnemonic, suffix, Rd, Rn, offset << shift);
+	snprintf(instruction->text, 128,
+		"0x%8.8" PRIx32 "  0x%4.4x    \t%s%c\tr%i, [r%i, #%#" PRIx32 "]",
+		address, opcode, mnemonic, suffix, Rd, Rn, offset << shift);
 
 	instruction->info.load_store.Rd = Rd;
 	instruction->info.load_store.Rn = Rn;
@@ -1797,7 +1820,9 @@
 		mnemonic = "STR";
 	}
 
-	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, [SP, #0x%" PRIx32 "]", address, opcode, mnemonic, Rd, offset*4);
+	snprintf(instruction->text, 128,
+		"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tr%i, [SP, #%#" PRIx32 "]",
+		address, opcode, mnemonic, Rd, offset*4);
 
 	instruction->info.load_store.Rd = Rd;
 	instruction->info.load_store.Rn = 13 /*SP*/;
@@ -1829,7 +1854,9 @@
 		Rn = 15;
 	}
 
-	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tADD r%i, %s, #0x%" PRIx32 "", address, opcode, Rd,reg_name, imm*4);
+	snprintf(instruction->text, 128,
+		"0x%8.8" PRIx32 "  0x%4.4x  \tADD\tr%i, %s, #%#" PRIx32,
+		address, opcode, Rd, reg_name, imm * 4);
 
 	instruction->info.data_proc.variant = 0 /* immediate */;
 	instruction->info.data_proc.Rd = Rd;
@@ -1857,7 +1884,9 @@
 		mnemonic = "ADD";
 	}
 
-	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s SP, #0x%" PRIx32 "", address, opcode, mnemonic, imm*4);
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "  0x%4.4x    \t%s\tSP, #%#" PRIx32,
+			address, opcode, mnemonic, imm*4);
 
 	instruction->info.data_proc.variant = 0 /* immediate */;
 	instruction->info.data_proc.Rd = 13 /*SP*/;
@@ -1873,7 +1902,9 @@
 
 	instruction->type = ARM_BKPT;
 
-	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tBKPT 0x%02" PRIx32 "", address, opcode, imm);
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "  0x%4.4x  \tBKPT\t%#2.2" PRIx32 "",
+			address, opcode, imm);
 
 	return ERROR_OK;
 }
@@ -1934,9 +1965,11 @@
 	if (reg_names_p > reg_names)
 		reg_names_p[-2] = '\0';
 	else /* invalid op : no registers */
-    		reg_names[0] = '\0';
+		reg_names[0] = '\0';
 
-	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s %s{%s}", address, opcode, mnemonic, ptr_name,reg_names);
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "  0x%4.4x  \t%s\t%s{%s}",
+			address, opcode, mnemonic, ptr_name, reg_names);
 
 	instruction->info.load_store_multiple.register_list = reg_list;
 	instruction->info.load_store_multiple.Rn = Rn;
@@ -1955,14 +1988,16 @@
 	{
 		instruction->type = ARM_SWI;
 		snprintf(instruction->text, 128,
-				"0x%8.8" PRIx32 "\t0x%4.4x\tSVC 0x%02" PRIx32,
+				"0x%8.8" PRIx32 "  0x%4.4x    \tSVC\t%#2.2" PRIx32,
 				address, opcode, offset);
 		return ERROR_OK;
 	}
 	else if (cond == 0xe)
 	{
 		instruction->type = ARM_UNDEFINED_INSTRUCTION;
-		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
+		snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "  0x%4.4x    \tUNDEFINED INSTRUCTION",
+			address, opcode);
 		return ERROR_OK;
 	}
 
@@ -1972,8 +2007,10 @@
 
 	target_address = address + 4 + (offset << 1);
 
-	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tB%s 0x%8.8" PRIx32 , address, opcode,
-			 arm_condition_strings[cond], target_address);
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "  0x%4.4x    \tB%s\t%#8.8" PRIx32,
+			address, opcode,
+			arm_condition_strings[cond], target_address);
 
 	instruction->type = ARM_B;
 	instruction->info.b_bl_bx_blx.reg_operand = -1;
@@ -1992,7 +2029,7 @@
 	offset |= (opcode & 0x0200) >> 4;
 
 	snprintf(instruction->text, 128,
-			"0x%8.8" PRIx32 "\t0x%4.4x\tCB%sZ r%d, %#8.8" PRIx32,
+			"0x%8.8" PRIx32 "  0x%4.4x    \tCB%sZ\tr%d, %#8.8" PRIx32,
 			address, opcode,
 			(opcode & 0x0800) ? "N" : "",
 			opcode & 0x7, address + 4 + (offset << 1));
@@ -2005,7 +2042,7 @@
 {
 	/* added in ARMv6 */
 	snprintf(instruction->text, 128,
-			"0x%8.8" PRIx32 "\t0x%4.4x\t%cXT%c r%d, r%d",
+			"0x%8.8" PRIx32 "  0x%4.4x    \t%cXT%c\tr%d, r%d",
 			address, opcode,
 			(opcode & 0x0080) ? 'U' : 'S',
 			(opcode & 0x0040) ? 'B' : 'H',
@@ -2020,12 +2057,12 @@
 	/* added in ARMv6 */
 	if ((opcode & 0x0ff0) == 0x0650)
 		snprintf(instruction->text, 128,
-				"0x%8.8" PRIx32 "\t0x%4.4x\tSETEND %s",
+				"0x%8.8" PRIx32 "  0x%4.4x    \tSETEND %s",
 				address, opcode,
 				(opcode & 0x80) ? "BE" : "LE");
 	else /* ASSUME (opcode & 0x0fe0) == 0x0660 */
 		snprintf(instruction->text, 128,
-				"0x%8.8" PRIx32 "\t0x%4.4x\tCPSI%c %s%s%s",
+				"0x%8.8" PRIx32 "  0x%4.4x    \tCPSI%c %s%s%s",
 				address, opcode,
 				(opcode & 0x0010) ? 'D' : 'E',
 				(opcode & 0x0004) ? "A" : "",
@@ -2053,7 +2090,7 @@
 		break;
 	}
 	snprintf(instruction->text, 128,
-			"0x%8.8" PRIx32 "\t0x%4.4x\tREV%s r%d, r%d",
+			"0x%8.8" PRIx32 "  0x%4.4x    \tREV%s\tr%d, r%d",
 			address, opcode, suffix,
 			opcode & 0x7, (opcode >> 3) & 0x7);
 
@@ -2087,7 +2124,7 @@
 	}
 
 	snprintf(instruction->text, 128,
-			"0x%8.8" PRIx32 "\t0x%4.4x\t%s",
+			"0x%8.8" PRIx32 "  0x%4.4x    \t%s",
 			address, opcode, hint);
 
 	return ERROR_OK;
@@ -2107,7 +2144,7 @@
 		x = (opcode & 0x08) ? "T" : "E";
 
 	snprintf(instruction->text, 128,
-			"0x%8.8" PRIx32 "\t0x%4.4x\tIT%s%s%s %s",
+			"0x%8.8" PRIx32 "  0x%4.4x    \tIT%s%s%s\t%s",
 			address, opcode,
 			x, y, z, arm_condition_strings[cond]);
 
@@ -2216,7 +2253,7 @@
 
 		instruction->type = ARM_UNDEFINED_INSTRUCTION;
 		snprintf(instruction->text, 128,
-			"0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION",
+			"0x%8.8" PRIx32 "  0x%4.4x    \tUNDEFINED INSTRUCTION",
 			address, opcode);
 		return ERROR_OK;
 	}
@@ -2239,7 +2276,10 @@
 		if ((opcode & 0xf801) == 0xe801)
 		{
 			instruction->type = ARM_UNDEFINED_INSTRUCTION;
-			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8x\tUNDEFINED INSTRUCTION", address, opcode);
+			snprintf(instruction->text, 128,
+					"0x%8.8" PRIx32 "  0x%8.8x\t"
+					"UNDEFINED INSTRUCTION",
+					address, opcode);
 			return ERROR_OK;
 		}
 		else
@@ -2297,7 +2337,7 @@
 	LOG_DEBUG("Can't decode 32-bit Thumb2 yet (opcode=%08x)", opcode);
 
 	snprintf(instruction->text, 128,
-			"0x%8.8" PRIx32 "\t0x%8.8x\t... 32-bit Thumb2 ...",
+			"0x%8.8" PRIx32 "  0x%8.8x\t... 32-bit Thumb2 ...",
 			address, opcode);
 	return ERROR_OK;
 }

[Openocd-svn] r2530 - in trunk: doc src/target

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-16 01:39:37 +0200 (Thu, 16 Jul 2009)
New Revision: 2530

Modified:
   trunk/doc/openocd.texi
   trunk/src/target/arm_disassembler.c
   trunk/src/target/arm_disassembler.h
   trunk/src/target/cortex_m3.c
Log:
David Brownell <da...@pa...>:

Initial support for disassembling Thumb2 code.  This works only for
Cortex-M3 cores so far.  Eventually other cores will also need Thumb2
support ... but they don't yet support any kind of disassembly.

 - Update the 16-bit Thumb decoder:
 
     * Understand CPS, REV*, SETEND, {U,S}XT{B,H} opcodes added
       by ARMv6.  (It already seems to treat CPY as MOV.)

     * Understand CB, CBNZ, WFI, IT, and other opcodes added by
       in Thumb2.

 - A new Thumb2 instruction decode routine is provided.
 
     * This has a different signature:  pass the target, not the
       instruction, so it can fetch a second halfword when needed.  
       The instruction size is likewise returned to the caller.

     * 32-bit instructions are recognized but not yet decoded.
   
 - Start using the current "UAL" syntax in some cases.  "SWI" is
   renamed as "SVC"; "LDMIA" as "LDM"; "STMIA" as "STM".

 - Define a new "cortex_m3 disassemble addr count" command to give
   access to this disassembly.

Sanity checked against "objdump -d" output; a bunch of the new
instructions checked out fine.


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-07-15 12:30:06 UTC (rev 2529)
+++ trunk/doc/openocd.texi	2009-07-15 23:39:37 UTC (rev 2530)
@@ -5003,6 +5003,11 @@
 @subsection Cortex-M3 specific commands
 @cindex Cortex-M3
 
+@deffn Command {cortex_m3 disassemble} address count
+@cindex disassemble
+Disassembles @var{count} Thumb2 instructions starting at @var{address}.
+@end deffn
+
 @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})
 Control masking (disabling) interrupts during target step/resume.
 @end deffn

Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c	2009-07-15 12:30:06 UTC (rev 2529)
+++ trunk/src/target/arm_disassembler.c	2009-07-15 23:39:37 UTC (rev 2530)
@@ -21,6 +21,7 @@
 #include "config.h"
 #endif
 
+#include "target.h"
 #include "arm_disassembler.h"
 #include "log.h"
 
@@ -63,7 +64,9 @@
 {
 	instruction->type = ARM_SWI;
 
-	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSWI 0x%6.6" PRIx32 "", address, opcode, (opcode & 0xffffff));
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSVC %#6.6" PRIx32,
+			address, opcode, (opcode & 0xffffff));
 
 	return ERROR_OK;
 }
@@ -614,7 +617,8 @@
 		if (U)
 		{
 			instruction->info.load_store_multiple.addressing_mode = 0;
-			addressing_mode = "IA";
+			/* "IA" is the default in UAL syntax */
+			addressing_mode = "";
 		}
 		else
 		{
@@ -1180,6 +1184,7 @@
 	/* clear fields, to avoid confusion */
 	memset(instruction, 0, sizeof(arm_instruction_t));
 	instruction->opcode = opcode;
+	instruction->instruction_size = 4;
 
 	/* catch opcodes with condition field [31:28] = b1111 */
 	if ((opcode & 0xf0000000) == 0xf0000000)
@@ -1356,8 +1361,12 @@
 			mnemonic = "BL";
 			break;
 	}
-	/* TODO: deals correctly with dual opcodes BL/BLX ... */
 
+	/* TODO: deal correctly with dual opcode (prefixed) BL/BLX;
+	 * these are effectively 32-bit instructions even in Thumb1.
+	 * Might be simplest to always use the Thumb2 decoder.
+	 */
+
 	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s 0x%8.8" PRIx32 , address, opcode,mnemonic, target_address);
 
 	instruction->info.b_bl_bx_blx.reg_operand = -1;
@@ -1887,12 +1896,12 @@
 		if (L)
 		{
 			instruction->type = ARM_LDM;
-			mnemonic = "LDMIA";
+			mnemonic = "LDM";
 		}
 		else
 		{
 			instruction->type = ARM_STM;
-			mnemonic = "STMIA";
+			mnemonic = "STM";
 		}
 		snprintf(ptr_name,7,"r%i!, ",Rn);
 	}
@@ -1945,7 +1954,9 @@
 	if (cond == 0xf)
 	{
 		instruction->type = ARM_SWI;
-		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tSWI 0x%02" PRIx32 , address, opcode, offset);
+		snprintf(instruction->text, 128,
+				"0x%8.8" PRIx32 "\t0x%4.4x\tSVC 0x%02" PRIx32,
+				address, opcode, offset);
 		return ERROR_OK;
 	}
 	else if (cond == 0xe)
@@ -1971,11 +1982,148 @@
 	return ERROR_OK;
 }
 
+static int evaluate_cb_thumb(uint16_t opcode, uint32_t address,
+		arm_instruction_t *instruction)
+{
+	unsigned offset;
+
+	/* added in Thumb2 */
+	offset = (opcode >> 3) & 0x1f;
+	offset |= (opcode & 0x0200) >> 4;
+
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "\t0x%4.4x\tCB%sZ r%d, %#8.8" PRIx32,
+			address, opcode,
+			(opcode & 0x0800) ? "N" : "",
+			opcode & 0x7, address + 4 + (offset << 1));
+
+	return ERROR_OK;
+}
+
+static int evaluate_extend_thumb(uint16_t opcode, uint32_t address,
+		arm_instruction_t *instruction)
+{
+	/* added in ARMv6 */
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "\t0x%4.4x\t%cXT%c r%d, r%d",
+			address, opcode,
+			(opcode & 0x0080) ? 'U' : 'S',
+			(opcode & 0x0040) ? 'B' : 'H',
+			opcode & 0x7, (opcode >> 3) & 0x7);
+
+	return ERROR_OK;
+}
+
+static int evaluate_cps_thumb(uint16_t opcode, uint32_t address,
+		arm_instruction_t *instruction)
+{
+	/* added in ARMv6 */
+	if ((opcode & 0x0ff0) == 0x0650)
+		snprintf(instruction->text, 128,
+				"0x%8.8" PRIx32 "\t0x%4.4x\tSETEND %s",
+				address, opcode,
+				(opcode & 0x80) ? "BE" : "LE");
+	else /* ASSUME (opcode & 0x0fe0) == 0x0660 */
+		snprintf(instruction->text, 128,
+				"0x%8.8" PRIx32 "\t0x%4.4x\tCPSI%c %s%s%s",
+				address, opcode,
+				(opcode & 0x0010) ? 'D' : 'E',
+				(opcode & 0x0004) ? "A" : "",
+				(opcode & 0x0002) ? "I" : "",
+				(opcode & 0x0001) ? "F" : "");
+
+	return ERROR_OK;
+}
+
+static int evaluate_byterev_thumb(uint16_t opcode, uint32_t address,
+		arm_instruction_t *instruction)
+{
+	char *suffix;
+
+	/* added in ARMv6 */
+	switch (opcode & 0x00c0) {
+	case 0:
+		suffix = "";
+		break;
+	case 1:
+		suffix = "16";
+		break;
+	default:
+		suffix = "SH";
+		break;
+	}
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "\t0x%4.4x\tREV%s r%d, r%d",
+			address, opcode, suffix,
+			opcode & 0x7, (opcode >> 3) & 0x7);
+
+	return ERROR_OK;
+}
+
+static int evaluate_hint_thumb(uint16_t opcode, uint32_t address,
+		arm_instruction_t *instruction)
+{
+	char *hint;
+
+	switch ((opcode >> 4) & 0x0f) {
+	case 0:
+		hint = "NOP";
+		break;
+	case 1:
+		hint = "YIELD";
+		break;
+	case 2:
+		hint = "WFE";
+		break;
+	case 3:
+		hint = "WFI";
+		break;
+	case 4:
+		hint = "SEV";
+		break;
+	default:
+		hint = "HINT (UNRECOGNIZED)";
+		break;
+	}
+
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "\t0x%4.4x\t%s",
+			address, opcode, hint);
+
+	return ERROR_OK;
+}
+
+static int evaluate_ifthen_thumb(uint16_t opcode, uint32_t address,
+		arm_instruction_t *instruction)
+{
+	unsigned cond = (opcode >> 4) & 0x0f;
+	char *x = "", *y = "", *z = "";
+
+	if (opcode & 0x01)
+		z = (opcode & 0x02) ? "T" : "E";
+	if (opcode & 0x03)
+		y = (opcode & 0x04) ? "T" : "E";
+	if (opcode & 0x07)
+		x = (opcode & 0x08) ? "T" : "E";
+
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "\t0x%4.4x\tIT%s%s%s %s",
+			address, opcode,
+			x, y, z, arm_condition_strings[cond]);
+
+	/* NOTE:  strictly speaking, the next 1-4 instructions should
+	 * now be displayed with the relevant conditional suffix...
+	 */
+
+	return ERROR_OK;
+}
+
 int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
 	/* clear fields, to avoid confusion */
 	memset(instruction, 0, sizeof(arm_instruction_t));
 	instruction->opcode = opcode;
+	instruction->instruction_size = 2;
 
 	if ((opcode & 0xe000) == 0x0000)
 	{
@@ -2033,18 +2181,44 @@
 	/* Misc */
 	if ((opcode & 0xf000) == 0xb000)
 	{
-		if ((opcode & 0x0f00) == 0x0000)
+		switch ((opcode >> 8) & 0x0f) {
+		case 0x0:
 			return evaluate_adjust_stack_thumb(opcode, address, instruction);
-		else if ((opcode & 0x0f00) == 0x0e00)
+		case 0x1:
+		case 0x3:
+		case 0x9:
+		case 0xb:
+			return evaluate_cb_thumb(opcode, address, instruction);
+		case 0x2:
+			return evaluate_extend_thumb(opcode, address, instruction);
+		case 0x4:
+		case 0x5:
+		case 0xc:
+		case 0xd:
+			return evaluate_load_store_multiple_thumb(opcode, address,
+						instruction);
+		case 0x6:
+			return evaluate_cps_thumb(opcode, address, instruction);
+		case 0xa:
+			if ((opcode & 0x00c0) == 0x0080)
+				break;
+			return evaluate_byterev_thumb(opcode, address, instruction);
+		case 0xe:
 			return evaluate_breakpoint_thumb(opcode, address, instruction);
-		else if ((opcode & 0x0600) == 0x0400) /* push pop */
-			return evaluate_load_store_multiple_thumb(opcode, address, instruction);
-		else
-		{
-			instruction->type = ARM_UNDEFINED_INSTRUCTION;
-			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
-			return ERROR_OK;
+		case 0xf:
+			if (opcode & 0x000f)
+				return evaluate_ifthen_thumb(opcode, address,
+						instruction);
+			else
+				return evaluate_hint_thumb(opcode, address,
+						instruction);
 		}
+
+		instruction->type = ARM_UNDEFINED_INSTRUCTION;
+		snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION",
+			address, opcode);
+		return ERROR_OK;
 	}
 
 	/* Load/Store multiple */
@@ -2078,6 +2252,56 @@
 	return -1;
 }
 
+/*
+ * REVISIT for Thumb2 instructions, instruction->type and friends aren't
+ * always set.  That means eventual arm_simulate_step() support for Thumb2
+ * will need work in this area.
+ */
+int thumb2_opcode(target_t *target, uint32_t address, arm_instruction_t *instruction)
+{
+	int retval;
+	uint16_t op;
+	uint32_t opcode;
+
+	/* clear low bit ... it's set on function pointers */
+	address &= ~1;
+
+	/* clear fields, to avoid confusion */
+	memset(instruction, 0, sizeof(arm_instruction_t));
+
+	/* read first halfword, see if this is the only one */
+	retval = target_read_u16(target, address, &op);
+	if (retval != ERROR_OK)
+		return retval;
+
+	switch (op & 0xf800) {
+	case 0xf800:
+	case 0xf000:
+	case 0xe800:
+		/* 32-bit instructions */
+		instruction->instruction_size = 4;
+		opcode = op << 16;
+		retval = target_read_u16(target, address + 2, &op);
+		if (retval != ERROR_OK)
+			return retval;
+		opcode |= op;
+		instruction->opcode = opcode;
+		break;
+	default:
+		/* 16-bit:  Thumb1 + IT + CBZ/CBNZ + ... */
+		return thumb_evaluate_opcode(op, address, instruction);
+	}
+
+	/* FIXME decode the 32-bit instructions */
+
+	LOG_DEBUG("Can't decode 32-bit Thumb2 yet (opcode=%08x)", opcode);
+
+	snprintf(instruction->text, 128,
+			"0x%8.8" PRIx32 "\t0x%8.8x\t... 32-bit Thumb2 ...",
+			address, opcode);
+	return ERROR_OK;
+}
+
 int arm_access_size(arm_instruction_t *instruction)
 {
 	if ((instruction->type == ARM_LDRB)

Modified: trunk/src/target/arm_disassembler.h
===================================================================
--- trunk/src/target/arm_disassembler.h	2009-07-15 12:30:06 UTC (rev 2529)
+++ trunk/src/target/arm_disassembler.h	2009-07-15 23:39:37 UTC (rev 2530)
@@ -185,6 +185,9 @@
 	char text[128];
 	uint32_t opcode;
 
+	/* return value ... Thumb-2 sizes vary */
+	unsigned instruction_size;
+
 	union {
 		arm_b_bl_bx_blx_instr_t b_bl_bx_blx;
 		arm_data_proc_instr_t data_proc;
@@ -196,6 +199,8 @@
 
 extern int arm_evaluate_opcode(uint32_t opcode, uint32_t address, arm_instruction_t *instruction);
 extern int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, arm_instruction_t *instruction);
+extern int thumb2_opcode(target_t *target, uint32_t address,
+		arm_instruction_t *instruction);
 extern int arm_access_size(arm_instruction_t *instruction);
 
 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])

Modified: trunk/src/target/cortex_m3.c
===================================================================
--- trunk/src/target/cortex_m3.c	2009-07-15 12:30:06 UTC (rev 2529)
+++ trunk/src/target/cortex_m3.c	2009-07-15 23:39:37 UTC (rev 2530)
@@ -34,6 +34,7 @@
 #include "cortex_m3.h"
 #include "target_request.h"
 #include "target_type.h"
+#include "arm_disassembler.h"
 
 
 /* cli handling */
@@ -1646,6 +1647,47 @@
 	return ERROR_OK;
 }
 
+/*
+ * REVISIT Thumb2 disassembly should work for all ARMv7 cores, as well
+ * as at least ARM-1156T2.  The interesting thing about Cortex-M is
+ * that *only* Thumb2 disassembly matters.  There are also some small
+ * additions to Thumb2 that are specific to ARMv7-M.
+ */
+static int
+handle_cortex_m3_disassemble_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
+{
+	int retval = ERROR_OK;
+	target_t *target = get_current_target(cmd_ctx);
+	uint32_t address;
+	unsigned long count;
+	arm_instruction_t cur_instruction;
+
+	if (argc != 2) {
+		command_print(cmd_ctx,
+			"usage: cortex_m3 disassemble <address> <count>");
+		return ERROR_OK;
+	}
+
+	errno = 0;
+	address = strtoul(args[0], NULL, 0);
+	if (errno)
+		return ERROR_FAIL;
+	count = strtoul(args[1], NULL, 0);
+	if (errno)
+		return ERROR_FAIL;
+
+	while (count--) {
+		retval = thumb2_opcode(target, address, &cur_instruction);
+		if (retval != ERROR_OK)
+			return retval;
+		command_print(cmd_ctx, "%s", cur_instruction.text);
+		address += cur_instruction.instruction_size;
+	}
+
+	return ERROR_OK;
+}
+
 int cortex_m3_register_commands(struct command_context_s *cmd_ctx)
 {
 	int retval;
@@ -1653,9 +1695,16 @@
 
 	retval = armv7m_register_commands(cmd_ctx);
 
-	cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3", NULL, COMMAND_ANY, "cortex_m3 specific commands");
-	register_command(cmd_ctx, cortex_m3_cmd, "maskisr", handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC, "mask cortex_m3 interrupts ['on'|'off']");
+	cortex_m3_cmd = register_command(cmd_ctx, NULL, "cortex_m3",
+			NULL, COMMAND_ANY, "cortex_m3 specific commands");
 
+	register_command(cmd_ctx, cortex_m3_cmd, "disassemble",
+			handle_cortex_m3_disassemble_command, COMMAND_EXEC,
+			"disassemble Thumb2 instructions <address> <count>");
+	register_command(cmd_ctx, cortex_m3_cmd, "maskisr",
+			handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC,
+			"mask cortex_m3 interrupts ['on'|'off']");
+
 	return retval;
 }
 

[Openocd-svn] r2529 - trunk/src/jtag

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-07-15 14:30:06 +0200 (Wed, 15 Jul 2009)
New Revision: 2529

Modified:
   trunk/src/jtag/parport.c
Log:
print errno when parport fails to open.

Modified: trunk/src/jtag/parport.c
===================================================================
--- trunk/src/jtag/parport.c	2009-07-15 06:43:28 UTC (rev 2528)
+++ trunk/src/jtag/parport.c	2009-07-15 12:30:06 UTC (rev 2529)
@@ -247,7 +247,7 @@
 static int parport_register_commands(struct command_context_s *cmd_ctx)
 {
 	register_command(cmd_ctx, NULL, "parport_port", parport_handle_parport_port_command,
-		COMMAND_CONFIG, "either the address of the I/O port or the number of the /dev/parport device");
+		COMMAND_CONFIG, "either the address of the I/O port or the number of the �/dev/parport� device");
 	register_command(cmd_ctx, NULL, "parport_cable", parport_handle_parport_cable_command,
 		COMMAND_CONFIG, "the layout of the parallel port cable used to connect to the target");
 	register_command(cmd_ctx, NULL, "parport_write_on_exit", parport_handle_write_on_exit_command,
@@ -337,7 +337,8 @@
 
 	if (device_handle < 0)
 	{
-		LOG_ERROR("cannot open device. check it exists and that user read and write rights are set");
+		int err = errno;
+		LOG_ERROR("cannot open device. check it exists and that user read and write rights are set. errno=%d", err);
 		return ERROR_JTAG_INIT_FAILED;
 	}
 

[Openocd-svn] r2528 - trunk

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-07-15 08:43:28 +0200 (Wed, 15 Jul 2009)
New Revision: 2528

Removed:
   trunk/.settings/
Log:
retire Eclipse settings, charset will be set elsewhere.

[Openocd-svn] r2527 - in trunk: . .settings

[<oh...@ma...>]

Author: oharboe
Date: 2009-07-14 20:30:00 +0200 (Tue, 14 Jul 2009)
New Revision: 2527

Added:
   trunk/.settings/
   trunk/.settings/org.eclipse.core.resources.prefs
Log:
Eclipse settings include charset.

Added: trunk/.settings/org.eclipse.core.resources.prefs
===================================================================
--- trunk/.settings/org.eclipse.core.resources.prefs	2009-07-14 18:24:59 UTC (rev 2526)
+++ trunk/.settings/org.eclipse.core.resources.prefs	2009-07-14 18:30:00 UTC (rev 2527)
@@ -0,0 +1,3 @@
+#Tue Jul 14 20:27:34 CEST 2009
+eclipse.preferences.version=1
+encoding/<project>=Cp1252

[Openocd-svn] r2526 - trunk

[<oh...@ma...>]

Author: oharboe
Date: 2009-07-14 20:24:59 +0200 (Tue, 14 Jul 2009)
New Revision: 2526

Modified:
   trunk/README
Log:
David Brownell <da...@pa...> mention udev, and correct D2XX speed mentions

Modified: trunk/README
===================================================================
--- trunk/README	2009-07-14 11:57:59 UTC (rev 2525)
+++ trunk/README	2009-07-14 18:24:59 UTC (rev 2526)
@@ -64,6 +64,12 @@
 Installing OpenOCD
 ==================
 
+On Linux, you may have permissions problems to address.  The best
+way to do this is to use the contrib/udev.rules file.  It probably
+belongs somewhere in /etc/udev/rules.d, but consult your operating
+system documentation to be sure.  In particular, make sure that it
+matches the syntax used by your operating system's version of udev.
+
 A Note to OpenOCD Users
 -----------------------
 
@@ -325,7 +331,7 @@
 Using FTDI's FTD2XX
 -------------------
 
-Some claim the (closed) FTDICHIP.COM solution is faster, which
+The (closed source) FTDICHIP.COM solution is faster on MS-Windows.  That
 is the motivation for supporting it even though its licensing restricts
 it to non-redistributable OpenOCD binaries, and it is not available for
 all operating systems used with OpenOCD.  You may, however, build such
@@ -370,6 +376,9 @@
         --with-ft2xx-linux-tardir=../libftd2xx0.4.16 \
 	... other options ...
 
+Note that on Linux there is no good reason to use these FTDI binaries;
+they are no faster (on Linux) than libftdi, and cause licensing issues.
+
 =================================
 Obtaining OpenOCD From Subversion
 ---------------------------------

[Openocd-svn] r2523 - trunk/src/jtag/zy1000

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-07-14 12:38:26 +0200 (Tue, 14 Jul 2009)
New Revision: 2523

Modified:
   trunk/src/jtag/zy1000/zy1000.c
Log:
1.54 snapshot

Modified: trunk/src/jtag/zy1000/zy1000.c
===================================================================
--- trunk/src/jtag/zy1000/zy1000.c	2009-07-14 09:02:00 UTC (rev 2522)
+++ trunk/src/jtag/zy1000/zy1000.c	2009-07-14 10:38:26 UTC (rev 2523)
@@ -28,7 +28,7 @@
 #include <cyg/hal/hal_diag.h>
 
 
-#define ZYLIN_VERSION "1.53"
+#define ZYLIN_VERSION "1.54"
 #define ZYLIN_DATE __DATE__
 #define ZYLIN_TIME __TIME__
 #define ZYLIN_OPENOCD "$Revision$"

[Openocd-svn] r2525 - trunk/doc

[ntfreak at B. <nt...@ma...>]

Author: ntfreak
Date: 2009-07-14 13:57:59 +0200 (Tue, 14 Jul 2009)
New Revision: 2525

Modified:
   trunk/doc/openocd.texi
Log:
- fix small typo in documentation

Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-07-14 10:41:16 UTC (rev 2524)
+++ trunk/doc/openocd.texi	2009-07-14 11:57:59 UTC (rev 2525)
@@ -3135,7 +3135,7 @@
 @subsection Internal Flash (Microcontrollers)
 
 @deffn {Flash Driver} aduc702x
-The ADUC702x analog microcontrollers from ST Micro
+The ADUC702x analog microcontrollers from Analog Devices
 include internal flash and use ARM7TDMI cores.
 The aduc702x flash driver works with models ADUC7019 through ADUC7028.
 The setup command only requires the @var{target} argument

[Openocd-svn] r2522 - trunk

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-14 11:02:00 +0200 (Tue, 14 Jul 2009)
New Revision: 2522

Added:
   trunk/NEWS
   trunk/NEWS-0.2.0
Removed:
   trunk/NEWS
Log:
Archive released NEWS file: NEWS -> NEWS-0.2.0
Create new NEWS file from release script template.


Deleted: trunk/NEWS
===================================================================
--- trunk/NEWS	2009-07-14 08:54:36 UTC (rev 2521)
+++ trunk/NEWS	2009-07-14 09:02:00 UTC (rev 2522)
@@ -1,80 +0,0 @@
-The OpenOCD 0.2.0 source archive release includes numerous improvements
-that were made since the initial 0.1.0 source archive release.  Many
-contributors helped make this release a great success, and the community
-of developers and maintainers look forward to any response.
-
-In addition to the list of changes below, countless bug fixing and
-cleaning was performed across the tree.  Various TCL command parameters
-must past stricter value checks, and many more error conditions have
-been handled correctly.  These efforts helped to make the 0.2.0 release
-more stable and robust, though some changes may expose latent bugs in
-your existing configuration scripts.
- 
-This release does not maintain backward compatibility in all respects,
-so some target or configuration scripts may need to be updated.  In some
-cases, you may also see warnings; resolve those, because they indicate
-commands that will be removed in the future.
-
-The following areas of OpenOCD functionality changed in this release:
-
-JTAG Layer:
-- Improves modularity: core, TCL, driver commands, and interface have
-  been separated, encapsulated, and documented for developers.  Mostly.
-- Improves JTAG TAP transition tables: 
-   * Makes TAP paths variable length, rather than being fixed at 7 steps.
-   * Fixes problems with some targets that did not like longer paths.
-- Improves JTAG driver/minidriver modularity and encapsulation.
-- New drivers:
-   * Adds stub minidriver for developing new embedded JTAG interfaces.
-- Improves drivers:
-   * ft2232+ftd2xx:
-      + Adds initial high-speed device support: --enable-ftd2xx-highspeed
-      + Supports more types of FTDI-based devices.
-   * jlink:
-      + Works with more versions of the firmware (v3 and newer)
-      + Supports dynamically detects device capabilities and limits
-   * vsllink:
-      + Supports very long scan chains
-   * amtjtagaccel:
-      + Fixes broken ID code detection problems.
-
-Target Layer:
-- New devices: AVR, FA526
-- Improved support: ARM ADI, ARM11, MIPS
-- Numerous other bug fixes and improvements
-
-Flash Layer:
-- Improved drivers: mflash
-- New drivers: AT91SAM3, AVR, Davinci NAND
-
-Board, Interface, and Target Configuration Scripts:
-- Many new and improved targets and boards are now available.
-- Better separation of "board" and "target" configuration
-- Moved all TCL files to top-level "tcl" directory in the source tree
-- Installation moved from '$pkglibdir/' to '$pkgdatadir/scripts/'.
-- Site-specific files should be installed under '$pkgdatadir/site/';
-  files that exist this tree will be used in preference to default
-  distribution configurations in '$pkgdatadir/scripts/'.
-
-Documentation:
-- Updated User Guide:     http://openocd.berlios.de/doc/html/index.html
-   * Partially re-written and re-organized.
-   * Standardized presentation for all commands.
-   * Covers many drivers and commands that were previously omitted.
-   * New index for commands and drivers.
-- Added Developer Manual: http://openocd.berlios.de/doc/doxygen/index.html
-   * Now includes architecture, technical primers, style guides, and more.
-   * Available in-tree and on-line.
-
-Build and Release:
-- Increased configuration and compilation warning coverage.
-   * Use --disable-werror to work around build errors caused by warnings.
-- Use libtool to produce helper libraries as a step toward "libopenocd".
-- New processes and scripting to facilitate future source releases.
-
-For more details about what has changed since 0.1.0, see the ChangeLog
-associated with this release.
-
-For more information about contributing test reports, bug fixes, or new
-features and device support, please read the new Developer Manual (or
-the BUGS and PATCHES files in the source archive).

Added: trunk/NEWS
===================================================================
--- trunk/NEWS	2009-07-14 08:54:36 UTC (rev 2521)
+++ trunk/NEWS	2009-07-14 09:02:00 UTC (rev 2522)
@@ -0,0 +1,19 @@
+This file should include items worth mentioning in the
+OpenOCD openocd-0.2.0 source archive release.
+
+The following areas of OpenOCD functionality changed in this release:
+
+JTAG Layer:
+Target Layer:
+Flash Layer:
+Board, Target, and Interface Configuration Scripts:
+Documentation:
+Build and Release:
+
+For more details about what has changed since the last release,
+see the ChangeLog associated with this source archive.  For older NEWS,
+see the NEWS files associated with each release (i.e. NEWS-<version>).
+
+For more information about contributing test reports, bug fixes, or new
+features and device support, please read the new Developer Manual (or
+the BUGS and PATCHES files in the source archive).

Copied: trunk/NEWS-0.2.0 (from rev 2520, trunk/NEWS)

[Openocd-svn] r2521 - trunk

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-14 10:54:36 +0200 (Tue, 14 Jul 2009)
New Revision: 2521

Modified:
   trunk/configure.in
Log:
Bump minor version and add tag:
Bump minor package version number: 0.2.0 -> 0.3.0
Add '-in-development' version tag: 0.3.0 -> 0.3.0-in-development

Modified: trunk/configure.in
===================================================================
--- trunk/configure.in	2009-07-14 08:54:24 UTC (rev 2520)
+++ trunk/configure.in	2009-07-14 08:54:36 UTC (rev 2521)
@@ -1,5 +1,5 @@
 AC_PREREQ(2.60)
-AC_INIT([openocd], [0.2.0],
+AC_INIT([openocd], [0.3.0-in-development],
   [OpenOCD Mailing List <ope...@li...>])
 AC_CONFIG_SRCDIR([src/openocd.c])
 

[Openocd-svn] r2520 - branches/openocd-0.2.0

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-14 10:54:24 +0200 (Tue, 14 Jul 2009)
New Revision: 2520

Modified:
   branches/openocd-0.2.0/configure.in
Log:
Bump micro version and add tag:
Bump micro package version number: 0.2.0 -> 0.2.1
Add '-in-development' version tag: 0.2.1 -> 0.2.1-in-development

Modified: branches/openocd-0.2.0/configure.in
===================================================================
--- branches/openocd-0.2.0/configure.in	2009-07-14 08:54:14 UTC (rev 2519)
+++ branches/openocd-0.2.0/configure.in	2009-07-14 08:54:24 UTC (rev 2520)
@@ -1,5 +1,5 @@
 AC_PREREQ(2.60)
-AC_INIT([openocd], [0.2.0],
+AC_INIT([openocd], [0.2.1-in-development],
   [OpenOCD Mailing List <ope...@li...>])
 AC_CONFIG_SRCDIR([src/openocd.c])
 

[Openocd-svn] r2519 - tags

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-14 10:54:14 +0200 (Tue, 14 Jul 2009)
New Revision: 2519

Added:
   tags/openocd-0.2.0/
Log:
Tagging version 0.2.0

Copied: tags/openocd-0.2.0 (from rev 2518, branches/openocd-0.2.0)

[Openocd-svn] r2518 - branches

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-14 10:53:54 +0200 (Tue, 14 Jul 2009)
New Revision: 2518

Added:
   branches/openocd-0.2.0/
Log:
Branching version 0.2.0

Copied: branches/openocd-0.2.0 (from rev 2517, trunk)

[Openocd-svn] r2517 - trunk

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-14 10:53:40 +0200 (Tue, 14 Jul 2009)
New Revision: 2517

Modified:
   trunk/configure.in
Log:
Remove '-in-development' version tag: 0.2.0-in-development -> 0.2.0

Modified: trunk/configure.in
===================================================================
--- trunk/configure.in	2009-07-14 08:52:28 UTC (rev 2516)
+++ trunk/configure.in	2009-07-14 08:53:40 UTC (rev 2517)
@@ -1,5 +1,5 @@
 AC_PREREQ(2.60)
-AC_INIT([openocd], [0.2.0-in-development],
+AC_INIT([openocd], [0.2.0],
   [OpenOCD Mailing List <ope...@li...>])
 AC_CONFIG_SRCDIR([src/openocd.c])
 

[Openocd-svn] r2516 - trunk/tools

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-14 10:52:28 +0200 (Tue, 14 Jul 2009)
New Revision: 2516

Modified:
   trunk/tools/release.sh
Log:
Improve the release script before 0.2.0:
1) Only archive NEWS file on major and minor relesae, not bug-fixes.
2) Switch back to correct development branch during final release step.
3) Add do_svn_switch helper to ensure package variables are reloaded.


Modified: trunk/tools/release.sh
===================================================================
--- trunk/tools/release.sh	2009-07-14 07:35:29 UTC (rev 2515)
+++ trunk/tools/release.sh	2009-07-14 08:52:28 UTC (rev 2516)
@@ -74,6 +74,10 @@
 	do_svn_echo "$@"
 	[ "${RELEASE_DRY_RUN}" ] || svn "$@"
 }
+do_svn_switch() {
+	do_svn switch "$1"
+	package_info_load
+}
 
 
 package_info_load_name() {
@@ -432,11 +436,9 @@
 	do_version_tag_add in-development
 }
 do_release_step_branch() {
-	do_svn switch "${PACKAGE_BRANCH}"
-	package_info_load
+	do_svn_switch "${PACKAGE_BRANCH}"
 	do_version_commit "$(do_release_step_branch_bump micro)"
-	do_svn switch "${SVN_URL}"
-	package_info_load
+	do_svn_switch "${SVN_URL}"
 }
 do_release_step_bump() {
 	# major and minor releases require branch version update too
@@ -444,6 +446,8 @@
 	# bump the current tree version as required.
 	do_version_commit "$(do_release_step_branch_bump "${RELEASE_TYPE}")"
 
+	[ "${RELEASE_TYPE}" = "micro" ] && return
+
 	# archive NEWS and create new one from template
 	do_svn move "NEWS" "NEWS-${RELEASE_VERSION}"
 
@@ -479,9 +483,10 @@
 	local A=${PACKAGE_TAG}
 	local B=${A/https/http}
 	local PACKAGE_BUILD=${B/${USER}@/}
-	do_svn switch "${PACKAGE_BUILD}"
+	do_svn_switch "${PACKAGE_BUILD}"
 	do_stage
 	do_clean
+	do_svn_switch "${SVN_URL}"
 }
 
 do_release_step_1() { do_release_step_prep; }

[Openocd-svn] r2515 - trunk

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-14 09:35:29 +0200 (Tue, 14 Jul 2009)
New Revision: 2515

Added:
   trunk/README.Win32
Modified:
   trunk/README
Log:
Split Windows README instructions into new file, with a few fixes.

Modified: trunk/README
===================================================================
--- trunk/README	2009-07-14 06:39:55 UTC (rev 2514)
+++ trunk/README	2009-07-14 07:35:29 UTC (rev 2515)
@@ -305,6 +305,10 @@
 Using LIBFTDI
 -------------
 
+The libftdi source code can be download from the following website:
+
+  http://www.intra2net.com/en/developer/libftdi/download.php
+
 For both Linux and Windows, both libusb and libftdi must be built and
 installed.  To use the newer FT2232H chips, supporting RTCK and USB high
 speed (480 Mbps), you need libftdi version 0.16 or newer.  Many Linux
@@ -353,19 +357,6 @@
 _distributing_ copies of OpenOCD built with the FTDI code would violate
 the OpenOCD licensing terms.  
 
-
-Cygwin/Win32 Notes
-******************
-
-The Cygwin/Win32 ZIP file contains a directory named ftd2xx.win32.
-Assuming that you have extracted this archive in the same directory as
-the OpenOCD package, you could configure with options like the following:
-
-   ./configure \
-	--enable-ft2232_ftd2xx \
-	--with-ftd2xx-win32-zipdir=../ftd2xx.win32 \
-	... other options ...
-
 Linux Notes
 ***********
 
@@ -404,82 +395,9 @@
 ************************************************
 
 Building OpenOCD from a repository requires a recent version of the GNU
-autotools (autoconf >= 2.59 and automake >= 1.9).  For building on
-Windows, you have to use Cygwin. Make sure that your PATH
-environment variable contains no other locations with Unix utils (like
-UnxUtils) - these can't handle the Cygwin paths, resulting in obscure
-dependency errors.  This was an observation gathered from the logs of
-one user; please correct us if this is wrong.
+autotools (autoconf >= 2.59 and automake >= 1.9).  
 
 1) Run './bootstrap' to create the 'configure' script and prepare
    the build process for your host system.
 
 2) Run './configure --enable-maintainer-mode' with other options.
-
-The following URL is a good reference if you want to build OpenOCD
-under cygwin.
-http://forum.sparkfun.com/viewtopic.php?t=11221
-
-Alternatively you can build the Windows binary under Linux using
-MinGW cross compiler. The following documents some tips of
-using this cross build option.
-
-a) libusb-win32
-You can choose to use the libusb-win32 binary distribution from
-its Sourceforge page. As of this writing, the latest version
-is 0.1.12.2. This is the recommend version to use since it fixed
-an issue with USB composite device and this is important for FTDI
-based JTAG debuggers.
-http://sourceforge.net/projects/libusb-win32/
-
-You need to download the libusb-win32-device-bin-0.1.12.2.tar.gz 
-package. Please extract this file into a temp directory. 
-
-Copy the file libusb-win32-device-bin-0.1.12.2\include\usb.h
-to your MinGW include directory.
-
-Copy the library libusb-win32-device-bin-0.1.12.2\lib\gcc\libusb.a
-to your MinGW library directory.
-
-Take note that different Linux distros often have different
-MinGW installation directory. Some of them also put the
-library and include into a seperate sys-root directory.
-
-If there is a new svn version of libusb-win32, you can build it
-as well. 
-
-This is the instrunction from the libusb-win32 Makefile.
-# If you're cross-compiling and your mingw32 tools are called
-# i586-mingw32msvc-gcc and so on, then you can compile libusb-win32
-# by running
-#    make host_prefix=i586-mingw32msvc all
-
-b) libftdi
-libftdi source codes can be download from the following website.
-http://www.intra2net.com/en/developer/libftdi/download.php
-
-It does not provide Windows binary. You can build it from the
-source tarball or the git tree.
-
-If you are using the git tree, the following is the instruction 
-from README.mingw. You need to have cmake installed.
-- Edit Toolchain-mingw32.cmake to point to the correct MinGW 
-installation.
-- Create a build directory like "mkdir build-win32", e.g in ../libftdi/
-- cd in that directory and run  
-  "cmake -DCMAKE_TOOLCHAIN_FILE=../Toolchain-mingw32.cmake .."
-- Copy src/ftdi.h to your MinGW include directory.
-- Copy build-win32/src/*.a to your MinGW lib directory.
-
-c) OpenOCD
-Now you can build OpenOCD under Linux using MinGW.
-You need to use --host=your_mingW_prefix in the configure option.
-
-Example for libftdi (in one line, tested under Ubuntu 9.04):
-./configure --host=i586-mingw32msvc --enable-maintainer-mode 
---disable-shared --enable-ft2232_libftdi
-
-Example for ftd2xx (in one line, tested under Ubuntu 9.04)
-./configure --host=i586-mingw32msvc --enable-maintainer-mode 
---disable-shared --enable-ft2232_ftd2xx 
---with-ftd2xx-win32-zipdir=/home/mcuee/Desktop/build/openocd/libftd2xx-win32

Added: trunk/README.Win32
===================================================================
--- trunk/README.Win32	2009-07-14 06:39:55 UTC (rev 2514)
+++ trunk/README.Win32	2009-07-14 07:35:29 UTC (rev 2515)
@@ -0,0 +1,97 @@
+Building OpenOCD for Windows
+----------------------------
+
+For building on Windows, you have to use CygWin. Make sure that your
+PATH environment variable contains no other locations with Unix utilities
+(like UnxUtils).  Those tools can't handle the CygWin paths, resulting
+in obscure dependency errors.  This was an observation gathered from the
+logs of one user; please correct us if this is wrong.
+
+The following URL is a good reference if you want to build OpenOCD
+under CygWin:
+
+	http://forum.sparkfun.com/viewtopic.php?t=11221
+
+Alternatively you can build the Windows binary under Linux using
+MinGW cross compiler. The following documents some tips of
+using this cross build option.
+
+libusb-win32
+------------
+
+You can choose to use the libusb-win32 binary distribution from
+its SourceForge page. As of this writing, the latest version
+is 0.1.12.2. This is the recommend version to use since it fixed
+an issue with USB composite device and this is important for FTDI
+based JTAG debuggers.
+
+	http://sourceforge.net/projects/libusb-win32/
+
+You need to download the libusb-win32-device-bin-0.1.12.2.tar.gz 
+package.  Extract this file into a temp directory. 
+
+Copy the file libusb-win32-device-bin-0.1.12.2\include\usb.h
+to your MinGW include directory.
+
+Copy the library libusb-win32-device-bin-0.1.12.2\lib\gcc\libusb.a
+to your MinGW library directory.
+
+Take note that different Linux distributions often have different MinGW
+installation directory.  Some of them also put the library and include
+into a separate sys-root directory.
+
+If there is a new svn version of libusb-win32, you can build it as well. 
+
+These are the instruction from the libusb-win32 Makefile:
+
+# If you're cross-compiling and your mingw32 tools are called
+# i586-mingw32msvc-gcc and so on, then you can compile libusb-win32
+# by running
+#    make host_prefix=i586-mingw32msvc all
+
+libftdi
+-------
+
+The author does not provide Windows binary. You can build it from a
+released source tarball or the git tree.
+
+If you are using the git tree, the following are the instructions from
+README.mingw. You will need to have the cmake utility installed.
+
+- Edit Toolchain-mingw32.cmake to point to the correct MinGW 
+  installation.
+- Create a build directory like "mkdir build-win32", e.g in ../libftdi/
+- cd into that directory and run  
+  "cmake -DCMAKE_TOOLCHAIN_FILE=../Toolchain-mingw32.cmake .."
+- Copy src/ftdi.h to your MinGW include directory.
+- Copy build-win32/src/*.a to your MinGW lib directory.
+
+libftd2xx
+---------
+
+The Cygwin/Win32 ZIP file contains a directory named ftd2xx.win32.
+After being extracted, the directory does not need further preparation.
+Instead, its path must be provided to the --with-ftd2xx-win32-zipdir
+configure option, as shown in the next section.
+
+OpenOCD
+-------
+
+Now you can build OpenOCD under Linux using MinGW.  You need to use
+--build and --host configure options.
+
+To use libftdi:
+
+  ./configure --build=i686-pc-linux-gnu --host=i586-mingw32msvc \
+        --enable-ft2232_libftdi \
+        ... other options ...
+
+To use ftd2xx:
+
+  ./configure --build=i686-pc-linux-gnu --host=i586-mingw32msvc \
+        --enable-ft2232_ftd2xx \
+        --with-ftd2xx-win32-zipdir=/path/to/libftd2xx-win32 \
+        ... other options ...
+
+If you are using the SVN repository, see the README file for additional
+instructions about configuring and building OpenOCD.


Property changes on: trunk/README.Win32
___________________________________________________________________
Name: svn:eol-style
   + native

[Openocd-svn] r2514 - trunk

[<zw...@ma...>]

Author: zwelch
Date: 2009-07-14 08:39:55 +0200 (Tue, 14 Jul 2009)
New Revision: 2514

Modified:
   trunk/configure.in
Log:
Make the parport-ppdev option enabled by default.  This may require 
giving --disable-parport-ppdev to configure on some platform(s).


Modified: trunk/configure.in
===================================================================
--- trunk/configure.in	2009-07-13 06:36:51 UTC (rev 2513)
+++ trunk/configure.in	2009-07-14 06:39:55 UTC (rev 2514)
@@ -308,7 +308,7 @@
 AC_ARG_ENABLE(parport_ppdev,
   AS_HELP_STRING([--disable-parport-ppdev],
       [Disable use of ppdev (/dev/parportN) for parport (for x86 only)]), 
-    [parport_use_ppdev=$enableval], [parport_use_ppdev=])
+    [parport_use_ppdev=$enableval], [parport_use_ppdev=yes])
 
 AC_ARG_ENABLE(parport_giveio,
     AS_HELP_STRING([--enable-parport-giveio],