openocd-commit — OpenOCD commit maling list - read only

[Openocd-svn] r2614 - trunk/tcl/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 09:12:57 +0200 (Tue, 25 Aug 2009)
New Revision: 2614

Modified:
   trunk/tcl/target/at91sam9260.cfg
Log:
Ferdinand Postema <fer...@po...> increase reset delay to fix regression from 2600 to 2604

Modified: trunk/tcl/target/at91sam9260.cfg
===================================================================
--- trunk/tcl/target/at91sam9260.cfg	2009-08-25 07:09:48 UTC (rev 2613)
+++ trunk/tcl/target/at91sam9260.cfg	2009-08-25 07:12:57 UTC (rev 2614)
@@ -27,7 +27,7 @@
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 jtag_nsrst_delay 300
-jtag_ntrst_delay 10
+jtag_ntrst_delay 200
 
 jtag_rclk 3
 

[Openocd-svn] r2613 - in trunk: doc src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 09:09:48 +0200 (Tue, 25 Aug 2009)
New Revision: 2613

Modified:
   trunk/doc/openocd.texi
   trunk/src/target/xscale.c
Log:
Michael Schwingen <rin...@di...> The attached patch adds a "xscale vector_table" command that allows to set
the values that are written in the mini-IC (plus documentation updates that
describe why this is needed).

Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-08-25 07:04:25 UTC (rev 2612)
+++ trunk/doc/openocd.texi	2009-08-25 07:09:48 UTC (rev 2613)
@@ -4877,6 +4877,52 @@
 @subsection XScale specific commands
 @cindex XScale
 
+Some notes about the debug implementation on the XScale CPUs:
+
+The XScale CPU provides a special debug-only mini-instruction cache
+(mini-IC) in which exception vectors and target-resident debug handler
+code are placed by OpenOCD. In order to get access to the CPU, OpenOCD
+must point vector 0 (the reset vector) to the entry of the debug
+handler. However, this means that the complete first cacheline in the
+mini-IC is marked valid, which makes the CPU fetch all exception
+handlers from the mini-IC, ignoring the code in RAM.
+
+OpenOCD currently does not sync the mini-IC entries with the RAM
+contents (which would fail anyway while the target is running), so
+the user must provide appropriate values using the @code{xscale
+vector_table} command.
+
+It is recommended to place a pc-relative indirect branch in the vector
+table, and put the branch destination somewhere in memory. Doing so
+makes sure the code in the vector table stays constant regardless of
+code layout in memory:
+@example
+_vectors:
+        ldr     pc,[pc,#0x100-8]
+        ldr     pc,[pc,#0x100-8]
+        ldr     pc,[pc,#0x100-8]
+        ldr     pc,[pc,#0x100-8]
+        ldr     pc,[pc,#0x100-8]
+        ldr     pc,[pc,#0x100-8]
+        ldr     pc,[pc,#0x100-8]
+        ldr     pc,[pc,#0x100-8]
+        .org 0x100
+        .long real_reset_vector
+        .long real_ui_handler
+        .long real_swi_handler
+        .long real_pf_abort
+        .long real_data_abort
+        .long 0 /* unused */
+        .long real_irq_handler
+        .long real_fiq_handler
+@end example
+
+The debug handler must be placed somewhere in the address space using
+the @code{xscale debug_handler} command.  The allowed locations for the
+debug handler are either (0x800 - 0x1fef800) or (0xfe000800 -
+0xfffff800). The default value is 0xfe000800.
+
+
 These commands are available to XScale based CPUs,
 which are implementations of the ARMv5TE architecture.
 
@@ -4938,6 +4984,33 @@
 If the optional parameter is provided, first set the bitmask to that value.
 @end deffn
 
+The mask bits correspond with bit 16..23 in the DCSR:
+@example
+0x01    Trap Reset
+0x02    Trap Undefined Instructions
+0x04    Trap Software Interrupt
+0x08    Trap Prefetch Abort
+0x10    Trap Data Abort
+0x20    reserved
+0x40    Trap IRQ
+0x80    Trap FIQ
+@end example
+
+
+@anchor{xscale vector_table}
+@deffn Command {xscale vector_table} [<low|high> <index> <value>]
+@cindex vector_table
+
+Set an entry in the mini-IC vector table. There are two tables: one for
+low vectors (at 0x00000000), and one for high vectors (0xFFFF0000), each
+holding the 8 exception vectors. @var{index} can be 1-7, because vector 0
+points to the debug handler entry and can not be overwritten.
+@var{value} holds the 32-bit opcode that is placed in the mini-IC.
+
+Without arguments, the current settings are displayed.
+
+@end deffn
+
 @section ARMv6 Architecture
 @cindex ARMv6
 

Modified: trunk/src/target/xscale.c
===================================================================
--- trunk/src/target/xscale.c	2009-08-25 07:04:25 UTC (rev 2612)
+++ trunk/src/target/xscale.c	2009-08-25 07:09:48 UTC (rev 2613)
@@ -5,6 +5,9 @@
  *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
  *   oyv...@zy...                                               *
  *                                                                         *
+ *   Copyright (C) 2009 Michael Schwingen                                  *
+ *   mi...@sc...                                                 *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -3384,6 +3387,65 @@
 }
 
 
+int xscale_handle_vector_table_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
+{
+	target_t *target = get_current_target(cmd_ctx);
+	armv4_5_common_t *armv4_5;
+	xscale_common_t *xscale;
+	int err = 0;
+
+	if (xscale_get_arch_pointers(target, &armv4_5, &xscale) != ERROR_OK)
+	{
+		return ERROR_OK;
+	}
+
+	if (argc == 0) /* print current settings */
+	{
+		int idx;
+
+		command_print(cmd_ctx, "active user-set static vectors:");
+		for (idx = 1; idx < 8; idx++)
+			if (xscale->static_low_vectors_set & (1 << idx))
+				command_print(cmd_ctx, "low  %d: 0x%x", idx, xscale->static_low_vectors[idx]);
+		for (idx = 1; idx < 8; idx++)
+			if (xscale->static_high_vectors_set & (1 << idx))
+				command_print(cmd_ctx, "high %d: 0x%x", idx, xscale->static_high_vectors[idx]);
+		return ERROR_OK;
+	}
+
+	if (argc != 3)
+		err = 1;
+	else
+	{
+		int idx;
+		uint32_t vec;
+		idx = strtoul(args[1], NULL, 0);
+		vec = strtoul(args[2], NULL, 0);
+
+		if (idx < 1 || idx >= 8)
+			err = 1;
+
+		if (!err && strcmp(args[0], "low") == 0)
+		{
+			xscale->static_low_vectors_set |= (1<<idx);
+			xscale->static_low_vectors[idx] = vec;
+		}
+		else if (!err && (strcmp(args[0], "high") == 0))
+		{
+			xscale->static_high_vectors_set |= (1<<idx);
+			xscale->static_high_vectors[idx] = vec;
+		}
+		else
+			err = 1;
+	}
+
+	if (err)
+		command_print(cmd_ctx, "usage: xscale vector_table <high|low> <index> <code>");
+
+	return ERROR_OK;
+}
+
+
 int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
 	target_t *target = get_current_target(cmd_ctx);
@@ -3692,6 +3754,7 @@
 	register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
 
 	register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
+	register_command(cmd_ctx, xscale_cmd, "vector_table", xscale_handle_vector_table_command, COMMAND_EXEC, "<high|low> <index> <code> set static code for exception handler entry");
 
 	register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable | disable> ['fill' [n]|'wrap']");
 

[Openocd-svn] r2612 - trunk/src/svf

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 09:04:25 +0200 (Tue, 25 Aug 2009)
New Revision: 2612

Modified:
   trunk/src/svf/svf.c
Log:
Audrius Urmanavi?\196?\141ius <did...@gm...> Latest source (R2606) does not compile under Windows+Cygwin - fails with error about possibly uninitialized use of variable 'ch'. 

Modified: trunk/src/svf/svf.c
===================================================================
--- trunk/src/svf/svf.c	2009-08-25 07:02:50 UTC (rev 2611)
+++ trunk/src/svf/svf.c	2009-08-25 07:04:25 UTC (rev 2612)
@@ -656,7 +656,7 @@
 static int svf_copy_hexstring_to_binary(char *str, uint8_t **bin, int orig_bit_len, int bit_len)
 {
 	int i, str_len = strlen(str), str_hbyte_len = (bit_len + 3) >> 2;
-	uint8_t ch;
+	uint8_t ch = 0;
 
 	if (ERROR_OK != svf_adjust_array_length(bin, orig_bit_len, bit_len))
 	{

[Openocd-svn] r2611 - trunk/tcl/board

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 09:02:50 +0200 (Tue, 25 Aug 2009)
New Revision: 2611

Modified:
   trunk/tcl/board/mini2440.cfg
Log:
Brian Findlay <fin...@gm...> finalize mini2440.cfg

Modified: trunk/tcl/board/mini2440.cfg
===================================================================
--- trunk/tcl/board/mini2440.cfg	2009-08-25 06:59:42 UTC (rev 2610)
+++ trunk/tcl/board/mini2440.cfg	2009-08-25 07:02:50 UTC (rev 2611)
@@ -2,8 +2,8 @@
 # Mini2440 Samsung s3c2440A Processor with 64MB DRAM, 64MB NAND, 2 MB N0R
 # NOTE: Configured for NAND boot (switch S2 in NANDBOOT)
 # 64 MB NAND (Samsung K9D1208V0M) 
-# B Findlay  08/2009
-# Rev 1.0
+# B Findlay  08/09
+#
 #   ----------- Important notes to help you on your way ----------
 # README:
 #     NOR/NAND Boot Switch - I have not read the vivi source, but from
@@ -117,7 +117,6 @@
 #-------------------------------------------------------------------------
 
     jtag_khz 12000  
-    jtag_rclk 3000
     jtag interface   
 
 #-------------------------------------------------------------------------

[Openocd-svn] r2610 - trunk/tcl/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 08:59:42 +0200 (Tue, 25 Aug 2009)
New Revision: 2610

Modified:
   trunk/tcl/target/omap3530.cfg
Log:
use cortex_a8 instead of cortex_m3

Modified: trunk/tcl/target/omap3530.cfg
===================================================================
--- trunk/tcl/target/omap3530.cfg	2009-08-25 06:58:34 UTC (rev 2609)
+++ trunk/tcl/target/omap3530.cfg	2009-08-25 06:59:42 UTC (rev 2610)
@@ -35,10 +35,8 @@
 	-expected-id $_JRC_TAPID
 
 # GDB target:  Cortex-A8, using DAP
+target create omap3.cpu cortex_a8 -chain-position $_CHIPNAME.dap
 
-# FIXME when we have A8 support, use it.  A8 != M3 ...
-target create omap3.cpu cortex_m3 -chain-position $_CHIPNAME.dap
-
 # FIXME much of this should be in reset event handlers
 proc omap3_dbginit { } {
      reset

[Openocd-svn] r2609 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 08:58:34 +0200 (Tue, 25 Aug 2009)
New Revision: 2609

Modified:
   trunk/src/target/cortex_a8.c
   trunk/src/target/cortex_a8.h
Log:
David Brownell The rest of the Cortex-A8 support from Magnus: replace the previous
nonfunctional cortex_a8 code with something that at least basically
works (for halt/step/resume, without MMU) even if it is incomplete.
(With tweaks from ?\195?\152yvind, and cleanup from Dave.)

This code has mainly been developed and tested against R1606, it has 
been built and tested against R2294 where it runs but step and resume 
commands are broken due to regression (which should be fixed now).

This code is really written for OMAP3530.  It doesn't identify debug
resources using generic DAP calls to scan the ROM table, or perform
topology detection.  The OMAP3530 DAP exposes two memory access ports:

 - Port #0 is connected to L3 interconnect (the main bus) with
   passthrough to the L4 EMU bus ... so it will be used for most
   memory accesses.

 - Port #1 is connected to a dedicated debug bus (L4 EMU), with
   access to L4 Wakeup, and holds the ROM table ... so it must
   be used for most debug and control operations.

The are some defines to handle this in cortex_a8.c, which should be
replaced with more general code.  Having access to another Cortex-A8
implementation would help get that right.


Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-08-25 06:57:26 UTC (rev 2608)
+++ trunk/src/target/cortex_a8.c	2009-08-25 06:58:34 UTC (rev 2609)
@@ -34,89 +34,1126 @@
 #endif
 
 #include "cortex_a8.h"
+#include "armv7a.h"
+#include "armv4_5.h"
+
 #include "target_request.h"
 #include "target_type.h"
 
-
 /* cli handling */
 int cortex_a8_register_commands(struct command_context_s *cmd_ctx);
 
 /* forward declarations */
 int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp);
+int cortex_a8_init_target(struct command_context_s *cmd_ctx,
+		struct target_s *target);
+int cortex_a8_examine(struct target_s *target);
+int cortex_a8_poll(target_t *target);
+int cortex_a8_halt(target_t *target);
+int cortex_a8_resume(struct target_s *target, int current, uint32_t address,
+		int handle_breakpoints, int debug_execution);
+int cortex_a8_step(struct target_s *target, int current, uint32_t address,
+		int handle_breakpoints);
+int cortex_a8_debug_entry(target_t *target);
+int cortex_a8_restore_context(target_t *target);
+int cortex_a8_bulk_write_memory(target_t *target, uint32_t address,
+		uint32_t count, uint8_t *buffer);
+int cortex_a8_set_breakpoint(struct target_s *target,
+		breakpoint_t *breakpoint, uint8_t matchmode);
+int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
+int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
+int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
+int cortex_a8_dap_read_coreregister_u32(target_t *target,
+		uint32_t *value, int regnum);
+int cortex_a8_dap_write_coreregister_u32(target_t *target,
+		uint32_t value, int regnum);
 
 target_type_t cortexa8_target =
 {
 	.name = "cortex_a8",
 
-	.poll = NULL,
-	.arch_state = armv7m_arch_state,
+	.poll = cortex_a8_poll,
+	.arch_state = armv7a_arch_state,
 
 	.target_request_data = NULL,
 
-	.halt = NULL,
-	.resume = NULL,
-	.step = NULL,
+	.halt = cortex_a8_halt,
+	.resume = cortex_a8_resume,
+	.step = cortex_a8_step,
 
 	.assert_reset = NULL,
 	.deassert_reset = NULL,
 	.soft_reset_halt = NULL,
 
-	.get_gdb_reg_list = armv7m_get_gdb_reg_list,
+//	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
 
 	.read_memory = cortex_a8_read_memory,
 	.write_memory = cortex_a8_write_memory,
-	.bulk_write_memory = NULL,
-	.checksum_memory = NULL,
-	.blank_check_memory = NULL,
+	.bulk_write_memory = cortex_a8_bulk_write_memory,
+	.checksum_memory = arm7_9_checksum_memory,
+	.blank_check_memory = arm7_9_blank_check_memory,
 
-	.run_algorithm = armv7m_run_algorithm,
+	.run_algorithm = armv4_5_run_algorithm,
 
-	.add_breakpoint = NULL,
-	.remove_breakpoint = NULL,
+	.add_breakpoint = cortex_a8_add_breakpoint,
+	.remove_breakpoint = cortex_a8_remove_breakpoint,
 	.add_watchpoint = NULL,
 	.remove_watchpoint = NULL,
 
 	.register_commands = cortex_a8_register_commands,
 	.target_create = cortex_a8_target_create,
-	.init_target = NULL,
-	.examine = NULL,
+	.init_target = cortex_a8_init_target,
+	.examine = cortex_a8_examine,
 	.quit = NULL
 };
 
-int cortex_a8_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
+/*
+ * FIXME do topology discovery using the ROM; don't
+ * assume this is an OMAP3.
+ */
+#define swjdp_memoryap 0
+#define swjdp_debugap 1
+#define OMAP3530_DEBUG_BASE 0x54011000
+
+/*
+ * Cortex-A8 Basic debug access, very low level assumes state is saved
+ */
+int cortex_a8_init_debug_access(target_t *target)
 {
-	uint16_t dcrdr;
+#if 0
+# Unlocking the debug registers for modification
+mww 0x54011FB0 0xC5ACCE55 4
 
-	mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
-	*ctrl = (uint8_t)dcrdr;
-	*value = (uint8_t)(dcrdr >> 8);
+# Clear Sticky Power Down status Bit to enable access to
+# the registers in the Core Power Domain
+mdw 0x54011314
+# Check that it is cleared
+mdw 0x54011314
+# Now we can read Core Debug Registers at offset 0x080
+mdw 0x54011080 4
+# We can also read RAM.
+mdw 0x80000000 32
 
-	LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
+mdw 0x5401d030
+mdw 0x54011FB8
 
-	/* write ack back to software dcc register
-	 * signify we have read data */
-	if (dcrdr & (1 << 0))
+# Set DBGEN line for hardware debug (OMAP35xx)
+mww 0x5401d030 0x00002000
+
+#Check AUTHSTATUS
+mdw 0x54011FB8
+
+# Instr enable
+mww 0x54011088 0x2000
+mdw 0x54011080 4
+#endif
+	return ERROR_OK;
+}
+
+int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
+{
+	uint32_t dscr;
+	int retvalue;
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+	LOG_DEBUG("exec opcode 0x%08x", opcode);
+	mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
+	do
 	{
-		dcrdr = 0;
-		mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
+		retvalue = mem_ap_read_atomic_u32(swjdp,
+				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
 	}
+	while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
 
+	return retvalue;
+}
+
+/**************************************************************************
+Read core register with very few exec_opcode, fast but needs work_area.
+This can cause problems with MMU active.
+**************************************************************************/
+int cortex_a8_read_regs_through_mem(target_t *target, uint32_t address,
+		uint32_t * regfile)
+{
+	int retval = ERROR_OK;
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+	cortex_a8_dap_read_coreregister_u32(target, regfile, 0);
+	cortex_a8_dap_write_coreregister_u32(target, address, 0);
+	cortex_a8_exec_opcode(target, ARMV4_5_STMIA(0, 0xFFFE, 0, 0));
+	dap_ap_select(swjdp, swjdp_memoryap);
+	mem_ap_read_buf_u32(swjdp, (uint8_t *)(&regfile[1]), 4*15, address);
+	dap_ap_select(swjdp, swjdp_debugap);
+
+	return retval;
+}
+
+int cortex_a8_read_cp(target_t *target, uint32_t *value, uint8_t CP,
+		uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
+{
+	int retval;
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+	cortex_a8_exec_opcode(target, ARMV4_5_MRC(CP, op1, 0, CRn, CRm, op2));
+	/* Move R0 to DTRTX */
+	cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
+
+	/* Read DCCTX */
+	retval = mem_ap_read_atomic_u32(swjdp,
+			OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
+
+	return retval;
+}
+
+int cortex_a8_write_cp(target_t *target, uint32_t value,
+	uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
+/* TODO Fix this */
+{
+	int retval;
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+	retval = mem_ap_write_u32(swjdp,
+			OMAP3530_DEBUG_BASE + CPUDBG_DTRRX, value);
+	/* Move DTRRX to r0 */
+	cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+
+	cortex_a8_exec_opcode(target, ARMV4_5_MCR(CP, 0, 0, 0, 5, 0));
+	return retval;
+}
+
+int cortex_a8_read_cp15(target_t *target, uint32_t op1, uint32_t op2,
+		uint32_t CRn, uint32_t CRm, uint32_t *value)
+{
+	return cortex_a8_read_cp(target, value, 15, op1, CRn, CRm, op2);
+}
+
+int cortex_a8_write_cp15(target_t *target, uint32_t op1, uint32_t op2,
+		uint32_t CRn, uint32_t CRm, uint32_t value)
+{
+	return cortex_a8_write_cp(target, value, 15, op1, CRn, CRm, op2);
+}
+
+int cortex_a8_dap_read_coreregister_u32(target_t *target,
+		uint32_t *value, int regnum)
+{
+	int retval = ERROR_OK;
+	uint8_t reg = regnum&0xFF;
+
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+	swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+	if (reg > 16)
+		return retval;
+
+	if (reg < 15)
+	{
+		/* Rn to DCCTX, MCR p14, 0, Rd, c0, c5, 0,  0xEE000E15 */
+		cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, reg, 0, 5, 0));
+	}
+	else if (reg == 15)
+	{
+		cortex_a8_exec_opcode(target, 0xE1A0000F);
+		cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
+	}
+	else if (reg == 16)
+	{
+		cortex_a8_exec_opcode(target, ARMV4_5_MRS(0, 0));
+		cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
+	}
+
+	/* Read DCCTX */
+	retval = mem_ap_read_atomic_u32(swjdp,
+			OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
+//	retval = mem_ap_read_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
+
+	return retval;
+}
+
+int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int regnum)
+{
+	int retval = ERROR_OK;
+	uint8_t Rd = regnum&0xFF;
+
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+	if (Rd > 16)
+		return retval;
+
+	/* Write to DCCRX */
+	retval = mem_ap_write_u32(swjdp,
+			OMAP3530_DEBUG_BASE + CPUDBG_DTRRX, value);
+
+	if (Rd < 15)
+	{
+		/* DCCRX to Rd, MCR p14, 0, Rd, c0, c5, 0,  0xEE000E15 */
+		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, Rd, 0, 5, 0));
+	}
+	else if (Rd == 15)
+	{
+		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+		cortex_a8_exec_opcode(target, 0xE1A0F000);
+	}
+	else if (Rd == 16)
+	{
+		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+		cortex_a8_exec_opcode(target, ARMV4_5_MSR_GP(0, 0xF, 0));
+		/* Execute a PrefetchFlush instruction through the ITR. */
+		cortex_a8_exec_opcode(target, ARMV4_5_MCR(15, 0, 0, 7, 5, 4));
+	}
+
+	return retval;
+}
+
+/*
+ * Cortex-A8 Run control
+ */
+
+int cortex_a8_poll(target_t *target)
+{
+	int retval = ERROR_OK;
+	uint32_t dscr;
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+
+	enum target_state prev_target_state = target->state;
+
+	uint8_t saved_apsel = dap_ap_get_select(swjdp);
+	dap_ap_select(swjdp, swjdp_debugap);
+	retval = mem_ap_read_atomic_u32(swjdp,
+			OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+	if (retval != ERROR_OK)
+	{
+		dap_ap_select(swjdp, saved_apsel);
+		return retval;
+	}
+	cortex_a8->cpudbg_dscr = dscr;
+
+	if ((dscr & 0x3) == 0x3)
+	{
+		if (prev_target_state != TARGET_HALTED)
+		{
+			/* We have a halting debug event */
+			LOG_DEBUG("Target halted");
+			target->state = TARGET_HALTED;
+			if ((prev_target_state == TARGET_RUNNING)
+					|| (prev_target_state == TARGET_RESET))
+			{
+				retval = cortex_a8_debug_entry(target);
+				if (retval != ERROR_OK)
+					return retval;
+
+				target_call_event_callbacks(target,
+						TARGET_EVENT_HALTED);
+			}
+			if (prev_target_state == TARGET_DEBUG_RUNNING)
+			{
+				LOG_DEBUG(" ");
+
+				retval = cortex_a8_debug_entry(target);
+				if (retval != ERROR_OK)
+					return retval;
+
+				target_call_event_callbacks(target,
+						TARGET_EVENT_DEBUG_HALTED);
+			}
+		}
+	}
+	else if ((dscr & 0x3) == 0x2)
+	{
+		target->state = TARGET_RUNNING;
+	}
+	else
+	{
+		LOG_DEBUG("Unknown target state dscr = 0x%08x", dscr);
+		target->state = TARGET_UNKNOWN;
+	}
+
+	dap_ap_select(swjdp, saved_apsel);
+
+	return retval;
+}
+
+int cortex_a8_halt(target_t *target)
+{
+	int retval = ERROR_OK;
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+	uint8_t saved_apsel = dap_ap_get_select(swjdp);
+	dap_ap_select(swjdp, swjdp_debugap);
+
+	/* Perhaps we should do a read-modify-write here */
+	retval = mem_ap_write_atomic_u32(swjdp,
+			OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x1);
+
+	target->debug_reason = DBG_REASON_DBGRQ;
+	dap_ap_select(swjdp, saved_apsel);
+
+	return retval;
+}
+
+int cortex_a8_resume(struct target_s *target, int current,
+		uint32_t address, int handle_breakpoints, int debug_execution)
+{
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+//	breakpoint_t *breakpoint = NULL;
+	uint32_t resume_pc;
+
+	uint8_t saved_apsel = dap_ap_get_select(swjdp);
+	dap_ap_select(swjdp, swjdp_debugap);
+
+	if (!debug_execution)
+	{
+		target_free_all_working_areas(target);
+//		cortex_m3_enable_breakpoints(target);
+//		cortex_m3_enable_watchpoints(target);
+	}
+
+#if 0
+	if (debug_execution)
+	{
+		/* Disable interrupts */
+		/* We disable interrupts in the PRIMASK register instead of
+		 * masking with C_MASKINTS,
+		 * This is probably the same issue as Cortex-M3 Errata 377493:
+		 * C_MASKINTS in parallel with disabled interrupts can cause
+		 * local faults to not be taken. */
+		buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
+		armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
+		armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
+
+		/* Make sure we are in Thumb mode */
+		buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
+			buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
+		armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
+		armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
+	}
+#endif
+
+	/* current = 1: continue on current pc, otherwise continue at <address> */
+	resume_pc = buf_get_u32(
+			ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+				armv4_5->core_mode, 15).value,
+			0, 32);
+	if (!current)
+		resume_pc = address;
+
+	/* Make sure that the Armv7 gdb thumb fixups does not
+	 * kill the return address
+	 */
+	if (!(cortex_a8->cpudbg_dscr & (1 << 5)))
+	{
+		resume_pc &= 0xFFFFFFFC;
+	}
+	LOG_DEBUG("resume pc = 0x%08x", resume_pc);
+	buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+				armv4_5->core_mode, 15).value,
+			0, 32, resume_pc);
+	ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+			armv4_5->core_mode, 15).dirty = 1;
+	ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+			armv4_5->core_mode, 15).valid = 1;
+
+	cortex_a8_restore_context(target);
+//	arm7_9_restore_context(target); TODO Context is currently NOT Properly restored
+#if 0
+	/* the front-end may request us not to handle breakpoints */
+	if (handle_breakpoints)
+	{
+		/* Single step past breakpoint at current address */
+		if ((breakpoint = breakpoint_find(target, resume_pc)))
+		{
+			LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
+			cortex_m3_unset_breakpoint(target, breakpoint);
+			cortex_m3_single_step_core(target);
+			cortex_m3_set_breakpoint(target, breakpoint);
+		}
+	}
+
+#endif
+	/* Restart core */
+	/* Perhaps we should do a read-modify-write here */
+	mem_ap_write_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x2);
+
+	target->debug_reason = DBG_REASON_NOTHALTED;
+	target->state = TARGET_RUNNING;
+
+	/* registers are now invalid */
+	armv4_5_invalidate_core_regs(target);
+
+	if (!debug_execution)
+	{
+		target->state = TARGET_RUNNING;
+		target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
+		LOG_DEBUG("target resumed at 0x%x", resume_pc);
+	}
+	else
+	{
+		target->state = TARGET_DEBUG_RUNNING;
+		target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
+		LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
+	}
+
+	dap_ap_select(swjdp, saved_apsel);
+
 	return ERROR_OK;
 }
 
-int cortex_a8_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int cortex_a8_debug_entry(target_t *target)
 {
+	int i;
+	uint32_t regfile[16], pc, cpsr;
+	int retval = ERROR_OK;
+	working_area_t *regfile_working_area = NULL;
+
 	/* get pointers to arch-specific information */
-	armv7m_common_t *armv7m = target->arch_info;
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+	if (armv7a->pre_debug_entry)
+		armv7a->pre_debug_entry(target);
+
+	LOG_DEBUG("dscr = 0x%08x", cortex_a8->cpudbg_dscr);
+
+	/* Examine debug reason */
+	switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
+	{
+		case 0:
+		case 4:
+			target->debug_reason = DBG_REASON_DBGRQ;
+			break;
+		case 1:
+		case 3:
+			target->debug_reason = DBG_REASON_BREAKPOINT;
+			break;
+		case 10:
+			target->debug_reason = DBG_REASON_WATCHPOINT;
+			break;
+		default:
+			target->debug_reason = DBG_REASON_UNDEFINED;
+			break;
+	}
+
+	/* Examine target state and mode */
+	dap_ap_select(swjdp, swjdp_memoryap);
+	if (cortex_a8->fast_reg_read)
+		target_alloc_working_area(target, 64, &regfile_working_area);
+
+	/* First load register acessible through core debug port*/
+	if (!regfile_working_area)
+	{
+		for (i = 0; i <= 15; i++)
+			cortex_a8_dap_read_coreregister_u32(target,
+					&regfile[i], i);
+	}
+	else
+	{
+		cortex_a8_read_regs_through_mem(target,
+				regfile_working_area->address, regfile);
+		dap_ap_select(swjdp, swjdp_memoryap);
+		target_free_working_area(target, regfile_working_area);
+	}
+
+	cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
+	pc = regfile[15];
+	dap_ap_select(swjdp, swjdp_debugap);
+	LOG_DEBUG("cpsr: %8.8x", cpsr);
+
+	armv4_5->core_mode = cpsr & 0x3F;
+
+	for (i = 0; i <= ARM_PC; i++)
+	{
+		buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+					armv4_5->core_mode, i).value,
+				0, 32, regfile[i]);
+		ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+				armv4_5->core_mode, i).valid = 1;
+		ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+				armv4_5->core_mode, i).dirty = 0;
+	}
+	buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+				armv4_5->core_mode, 16).value,
+			0, 32, cpsr);
+	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
+	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
+
+	/* Fixup PC Resume Address */
+	/* TODO Her we should use arch->core_state */
+	if (cortex_a8->cpudbg_dscr & (1 << 5))
+	{
+		// T bit set for Thumb or ThumbEE state
+		regfile[ARM_PC] -= 4;
+	}
+	else
+	{
+		// ARM state
+		regfile[ARM_PC] -= 8;
+	}
+	buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+				armv4_5->core_mode, ARM_PC).value,
+			0, 32, regfile[ARM_PC]);
+
+	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0)
+		.dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+				armv4_5->core_mode, 0).valid;
+	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15)
+		.dirty = ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+				armv4_5->core_mode, 15).valid;
+
+#if 0
+/* TODO, Move this */
+	uint32_t cp15_control_register, cp15_cacr, cp15_nacr;
+	cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
+	LOG_DEBUG("cp15_control_register = 0x%08x", cp15_control_register);
+
+	cortex_a8_read_cp(target, &cp15_cacr, 15, 0, 1, 0, 2);
+	LOG_DEBUG("cp15 Coprocessor Access Control Register = 0x%08x", cp15_cacr);
+
+	cortex_a8_read_cp(target, &cp15_nacr, 15, 0, 1, 1, 2);
+	LOG_DEBUG("cp15 Nonsecure Access Control Register = 0x%08x", cp15_nacr);
+#endif
+
+	/* Are we in an exception handler */
+//	armv4_5->exception_number = 0;
+	if (armv7a->post_debug_entry)
+		armv7a->post_debug_entry(target);
+
+
+
+	return retval;
+
+}
+
+void cortex_a8_post_debug_entry(target_t *target)
+{
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+
+//	cortex_a8_read_cp(target, &cp15_control_register, 15, 0, 1, 0, 0);
+	/* examine cp15 control reg */
+	armv7a->read_cp15(target, 0, 0, 1, 0, &cortex_a8->cp15_control_reg);
+	jtag_execute_queue();
+	LOG_DEBUG("cp15_control_reg: %8.8x", cortex_a8->cp15_control_reg);
+
+	if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1)
+	{
+		uint32_t cache_type_reg;
+		/* identify caches */
+		armv7a->read_cp15(target, 0, 1, 0, 0, &cache_type_reg);
+		jtag_execute_queue();
+		/* FIXME the armv4_4 cache info DOES NOT APPLY to Cortex-A8 */
+		armv4_5_identify_cache(cache_type_reg,
+				&armv7a->armv4_5_mmu.armv4_5_cache);
+	}
+
+	armv7a->armv4_5_mmu.mmu_enabled =
+			(cortex_a8->cp15_control_reg & 0x1U) ? 1 : 0;
+	armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
+			(cortex_a8->cp15_control_reg & 0x4U) ? 1 : 0;
+	armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
+			(cortex_a8->cp15_control_reg & 0x1000U) ? 1 : 0;
+
+
+}
+
+int cortex_a8_step(struct target_s *target, int current, uint32_t address,
+		int handle_breakpoints)
+{
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+	breakpoint_t *breakpoint = NULL;
+	breakpoint_t stepbreakpoint;
+
+	int timeout = 100;
+
+	if (target->state != TARGET_HALTED)
+	{
+		LOG_WARNING("target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	/* current = 1: continue on current pc, otherwise continue at <address> */
+	if (!current)
+	{
+		buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+					armv4_5->core_mode, ARM_PC).value,
+				0, 32, address);
+	}
+	else
+	{
+		address = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+					armv4_5->core_mode, ARM_PC).value,
+				0, 32);
+	}
+
+	/* The front-end may request us not to handle breakpoints.
+	 * But since Cortex-A8 uses breakpoint for single step,
+	 * we MUST handle breakpoints.
+	 */
+	handle_breakpoints = 1;
+	if (handle_breakpoints) {
+		breakpoint = breakpoint_find(target,
+				buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+					armv4_5->core_mode, 15).value,
+			0, 32));
+		if (breakpoint)
+			cortex_a8_unset_breakpoint(target, breakpoint);
+	}
+
+	/* Setup single step breakpoint */
+	stepbreakpoint.address = address;
+	stepbreakpoint.length = (cortex_a8->cpudbg_dscr & (1 << 5)) ? 2 : 4;
+	stepbreakpoint.type = BKPT_HARD;
+	stepbreakpoint.set = 0;
+
+	/* Break on IVA mismatch */
+	cortex_a8_set_breakpoint(target, &stepbreakpoint, 0x04);
+
+	target->debug_reason = DBG_REASON_SINGLESTEP;
+
+	cortex_a8_resume(target, 1, address, 0, 0);
+
+	while (target->state != TARGET_HALTED)
+	{
+		cortex_a8_poll(target);
+		if (--timeout == 0)
+		{
+			LOG_WARNING("timeout waiting for target halt");
+			break;
+		}
+	}
+
+	cortex_a8_unset_breakpoint(target, &stepbreakpoint);
+	if (timeout > 0) target->debug_reason = DBG_REASON_BREAKPOINT;
+
+	if (breakpoint)
+		cortex_a8_set_breakpoint(target, breakpoint, 0);
+
+	if (target->state != TARGET_HALTED)
+		LOG_DEBUG("target stepped");
+
+	return ERROR_OK;
+}
+
+int cortex_a8_restore_context(target_t *target)
+{
+	int i;
+	uint32_t value;
+
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+
+	LOG_DEBUG(" ");
+
+	if (armv7a->pre_restore_context)
+		armv7a->pre_restore_context(target);
+
+	for (i = 15; i >= 0; i--)
+	{
+		if (ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+					armv4_5->core_mode, i).dirty)
+		{
+			value = buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+						armv4_5->core_mode, i).value,
+					0, 32);
+			/* TODO Check return values */
+			cortex_a8_dap_write_coreregister_u32(target, value, i);
+		}
+	}
+
+	if (armv7a->post_restore_context)
+		armv7a->post_restore_context(target);
+
+	return ERROR_OK;
+}
+
+
+/*
+ * Cortex-A8 Core register functions
+ */
+
+int cortex_a8_load_core_reg_u32(struct target_s *target, int num,
+		armv4_5_mode_t mode, uint32_t * value)
+{
 	int retval;
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
 
+	if ((num <= ARM_CPSR))
+	{
+		/* read a normal core register */
+		retval = cortex_a8_dap_read_coreregister_u32(target, value, num);
+
+		if (retval != ERROR_OK)
+		{
+			LOG_ERROR("JTAG failure %i", retval);
+			return ERROR_JTAG_DEVICE_ERROR;
+		}
+		LOG_DEBUG("load from core reg %i value 0x%x", num, *value);
+	}
+	else
+	{
+		return ERROR_INVALID_ARGUMENTS;
+	}
+
+	/* Register other than r0 - r14 uses r0 for access */
+	if (num > 14)
+		ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+				armv4_5->core_mode, 0).dirty =
+			ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+				armv4_5->core_mode, 0).valid;
+	ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+				armv4_5->core_mode, 15).dirty =
+			ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+				armv4_5->core_mode, 15).valid;
+
+	return ERROR_OK;
+}
+
+int cortex_a8_store_core_reg_u32(struct target_s *target, int num,
+		armv4_5_mode_t mode, uint32_t value)
+{
+	int retval;
+//	uint32_t reg;
+
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+
+#ifdef ARMV7_GDB_HACKS
+	/* If the LR register is being modified, make sure it will put us
+	 * in "thumb" mode, or an INVSTATE exception will occur. This is a
+	 * hack to deal with the fact that gdb will sometimes "forge"
+	 * return addresses, and doesn't set the LSB correctly (i.e., when
+	 * printing expressions containing function calls, it sets LR=0.) */
+
+	if (num == 14)
+		value |= 0x01;
+#endif
+
+	if ((num <= ARM_CPSR))
+	{
+		retval = cortex_a8_dap_write_coreregister_u32(target, value, num);
+		if (retval != ERROR_OK)
+		{
+			LOG_ERROR("JTAG failure %i", retval);
+			ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+					armv4_5->core_mode, num).dirty =
+				ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+					armv4_5->core_mode, num).valid;
+			return ERROR_JTAG_DEVICE_ERROR;
+		}
+		LOG_DEBUG("write core reg %i value 0x%x", num, value);
+	}
+	else
+	{
+		return ERROR_INVALID_ARGUMENTS;
+	}
+
+	return ERROR_OK;
+}
+
+
+int cortex_a8_read_core_reg(struct target_s *target, int num,
+		enum armv4_5_mode mode)
+{
+	uint32_t value;
+	int retval;
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	cortex_a8_dap_read_coreregister_u32(target, &value, num);
+
+	if ((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		return retval;
+	}
+
+	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
+	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
+	buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+			mode, num).value, 0, 32, value);
+
+	return ERROR_OK;
+}
+
+int cortex_a8_write_core_reg(struct target_s *target, int num,
+		enum armv4_5_mode mode, uint32_t value)
+{
+	int retval;
+	armv4_5_common_t *armv4_5 = target->arch_info;
+
+	cortex_a8_dap_write_coreregister_u32(target, value, num);
+	if ((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		return retval;
+	}
+
+	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).valid = 1;
+	ARMV7A_CORE_REG_MODE(armv4_5->core_cache, mode, num).dirty = 0;
+
+	return ERROR_OK;
+}
+
+
+/*
+ * Cortex-A8 Breakpoint and watchpoint fuctions
+ */
+
+/* Setup hardware Breakpoint Register Pair */
+int cortex_a8_set_breakpoint(struct target_s *target,
+		breakpoint_t *breakpoint, uint8_t matchmode)
+{
+	int retval;
+	int brp_i=0;
+	uint32_t control;
+	uint8_t byte_addr_select = 0x0F;
+
+
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+	cortex_a8_brp_t * brp_list = cortex_a8->brp_list;
+
+	if (breakpoint->set)
+	{
+		LOG_WARNING("breakpoint already set");
+		return ERROR_OK;
+	}
+
+	if (breakpoint->type == BKPT_HARD)
+	{
+		while (brp_list[brp_i].used && (brp_i < cortex_a8->brp_num))
+			brp_i++ ;
+		if (brp_i >= cortex_a8->brp_num)
+		{
+			LOG_ERROR("ERROR Can not find free Breakpoint Register Pair");
+			exit(-1);
+		}
+		breakpoint->set = brp_i + 1;
+		if (breakpoint->length == 2)
+		{
+			byte_addr_select = (3 << (breakpoint->address & 0x02));
+		}
+		control = ((matchmode & 0x7) << 20)
+				| (byte_addr_select << 5)
+				| (3 << 1) | 1;
+		brp_list[brp_i].used = 1;
+		brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
+		brp_list[brp_i].control = control;
+		target_write_u32(target, OMAP3530_DEBUG_BASE
+				+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
+				brp_list[brp_i].value);
+		target_write_u32(target, OMAP3530_DEBUG_BASE
+				+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
+				brp_list[brp_i].control);
+		LOG_DEBUG("brp %i control 0x%0x value 0x%0x", brp_i,
+				brp_list[brp_i].control,
+				brp_list[brp_i].value);
+	}
+	else if (breakpoint->type == BKPT_SOFT)
+	{
+		uint8_t code[4];
+		if (breakpoint->length == 2)
+		{
+			buf_set_u32(code, 0, 32, ARMV5_T_BKPT(0x11));
+		}
+		else
+		{
+			buf_set_u32(code, 0, 32, ARMV5_BKPT(0x11));
+		}
+		retval = target->type->read_memory(target,
+				breakpoint->address & 0xFFFFFFFE,
+				breakpoint->length, 1,
+				breakpoint->orig_instr);
+		if (retval != ERROR_OK)
+			return retval;
+		retval = target->type->write_memory(target,
+				breakpoint->address & 0xFFFFFFFE,
+				breakpoint->length, 1, code);
+		if (retval != ERROR_OK)
+			return retval;
+		breakpoint->set = 0x11; /* Any nice value but 0 */
+	}
+
+	return ERROR_OK;
+}
+
+int cortex_a8_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+{
+	int retval;
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+	cortex_a8_brp_t * brp_list = cortex_a8->brp_list;
+
+	if (!breakpoint->set)
+	{
+		LOG_WARNING("breakpoint not set");
+		return ERROR_OK;
+	}
+
+	if (breakpoint->type == BKPT_HARD)
+	{
+		int brp_i = breakpoint->set - 1;
+		if ((brp_i < 0) || (brp_i >= cortex_a8->brp_num))
+		{
+			LOG_DEBUG("Invalid BRP number in breakpoint");
+			return ERROR_OK;
+		}
+		LOG_DEBUG("rbp %i control 0x%0x value 0x%0x", brp_i,
+				brp_list[brp_i].control, brp_list[brp_i].value);
+		brp_list[brp_i].used = 0;
+		brp_list[brp_i].value = 0;
+		brp_list[brp_i].control = 0;
+		target_write_u32(target, OMAP3530_DEBUG_BASE
+				+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
+				brp_list[brp_i].control);
+		target_write_u32(target, OMAP3530_DEBUG_BASE
+				+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
+				brp_list[brp_i].value);
+	}
+	else
+	{
+		/* restore original instruction (kept in target endianness) */
+		if (breakpoint->length == 4)
+		{
+			retval = target->type->write_memory(target,
+					breakpoint->address & 0xFFFFFFFE,
+					4, 1, breakpoint->orig_instr);
+			if (retval != ERROR_OK)
+				return retval;
+		}
+		else
+		{
+			retval = target->type->write_memory(target,
+					breakpoint->address & 0xFFFFFFFE,
+					2, 1, breakpoint->orig_instr);
+			if (retval != ERROR_OK)
+				return retval;
+		}
+	}
+	breakpoint->set = 0;
+
+	return ERROR_OK;
+}
+
+int cortex_a8_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+{
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+
+	if ((breakpoint->type == BKPT_HARD) && (cortex_a8->brp_num_available < 1))
+	{
+		LOG_INFO("no hardware breakpoint available");
+		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	}
+
+	if (breakpoint->type == BKPT_HARD)
+		cortex_a8->brp_num_available--;
+	cortex_a8_set_breakpoint(target, breakpoint, 0x00); /* Exact match */
+
+	return ERROR_OK;
+}
+
+int cortex_a8_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+{
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+
+#if 0
+/* It is perfectly possible to remove brakpoints while the taget is running */
+	if (target->state != TARGET_HALTED)
+	{
+		LOG_WARNING("target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+#endif
+
+	if (breakpoint->set)
+	{
+		cortex_a8_unset_breakpoint(target, breakpoint);
+		if (breakpoint->type == BKPT_HARD)
+			cortex_a8->brp_num_available++ ;
+	}
+
+
+	return ERROR_OK;
+}
+
+
+
+/*
+ * Cortex-A8 Reset fuctions
+ */
+
+
+/*
+ * Cortex-A8 Memory access
+ *
+ * This is same Cortex M3 but we must also use the correct
+ * ap number for every access.
+ */
+
+int cortex_a8_read_memory(struct target_s *target, uint32_t address,
+		uint32_t size, uint32_t count, uint8_t *buffer)
+{
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+	int retval = ERROR_OK;
+
 	/* sanitize arguments */
 	if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 		return ERROR_INVALID_ARGUMENTS;
 
 	/* cortex_a8 handles unaligned memory access */
 
+// ???	dap_ap_select(swjdp, swjdp_memoryap);
+
 	switch (size)
 	{
 		case 4:
@@ -136,17 +1173,22 @@
 	return retval;
 }
 
-int cortex_a8_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int cortex_a8_write_memory(struct target_s *target, uint32_t address,
+		uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	/* get pointers to arch-specific information */
-	armv7m_common_t *armv7m = target->arch_info;
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
 	int retval;
 
 	/* sanitize arguments */
 	if (((size != 4) && (size != 2) && (size != 1)) || (count == 0) || !(buffer))
 		return ERROR_INVALID_ARGUMENTS;
 
+// ???	dap_ap_select(swjdp, swjdp_memoryap);
+
 	switch (size)
 	{
 		case 4:
@@ -166,21 +1208,53 @@
 	return retval;
 }
 
+int cortex_a8_bulk_write_memory(target_t *target, uint32_t address,
+		uint32_t count, uint8_t *buffer)
+{
+	return cortex_a8_write_memory(target, address, 4, count, buffer);
+}
+
+
+int cortex_a8_dcc_read(swjdp_common_t *swjdp, uint8_t *value, uint8_t *ctrl)
+{
+#if 0
+	u16 dcrdr;
+
+	mem_ap_read_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
+	*ctrl = (uint8_t)dcrdr;
+	*value = (uint8_t)(dcrdr >> 8);
+
+	LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
+
+	/* write ack back to software dcc register
+	 * signify we have read data */
+	if (dcrdr & (1 << 0))
+	{
+		dcrdr = 0;
+		mem_ap_write_buf_u16(swjdp, (uint8_t*)&dcrdr, 1, DCB_DCRDR);
+	}
+#endif
+	return ERROR_OK;
+}
+
+
 int cortex_a8_handle_target_request(void *priv)
 {
 	target_t *target = priv;
-	if (!target_was_examined(target))
+	if (!target->type->examined)
 		return ERROR_OK;
-	armv7m_common_t *armv7m = target->arch_info;
-	swjdp_common_t *swjdp = &armv7m->swjdp_info;
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
+
 	if (!target->dbg_msg_enabled)
 		return ERROR_OK;
 
 	if (target->state == TARGET_RUNNING)
 	{
-		uint8_t data;
-		uint8_t ctrl;
+		uint8_t data = 0;
+		uint8_t ctrl = 0;
 
 		cortex_a8_dcc_read(swjdp, &data, &ctrl);
 
@@ -204,39 +1278,188 @@
 	return ERROR_OK;
 }
 
-int cortex_a8_init_arch_info(target_t *target, cortex_a8_common_t *cortex_a8, jtag_tap_t *tap)
+/*
+ * Cortex-A8 target information and configuration
+ */
+
+int cortex_a8_examine(struct target_s *target)
 {
-	armv7m_common_t *armv7m;
-	armv7m = &cortex_a8->armv7m;
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
+
+	int i;
+	int retval = ERROR_OK;
+	uint32_t didr, ctypr, ttypr, cpuid;
+
+	LOG_DEBUG("TODO");
+
+	/* We do one extra read to ensure DAP is configured,
+	 * we call ahbap_debugport_init(swjdp) instead
+	 */
+	ahbap_debugport_init(swjdp);
+	mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_CPUID, &cpuid);
+	if ((retval = mem_ap_read_atomic_u32(swjdp,
+			OMAP3530_DEBUG_BASE + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
+	{
+		LOG_DEBUG("Examine failed");
+		return retval;
+	}
+
+	if ((retval = mem_ap_read_atomic_u32(swjdp,
+			OMAP3530_DEBUG_BASE + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
+	{
+		LOG_DEBUG("Examine failed");
+		return retval;
+	}
+
+	if ((retval = mem_ap_read_atomic_u32(swjdp,
+			OMAP3530_DEBUG_BASE + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
+	{
+		LOG_DEBUG("Examine failed");
+		return retval;
+	}
+
+	if ((retval = mem_ap_read_atomic_u32(swjdp,
+			OMAP3530_DEBUG_BASE + CPUDBG_DIDR, &didr)) != ERROR_OK)
+	{
+		LOG_DEBUG("Examine failed");
+		return retval;
+	}
+
+	LOG_DEBUG("cpuid = 0x%08x", cpuid);
+	LOG_DEBUG("ctypr = 0x%08x", ctypr);
+	LOG_DEBUG("ttypr = 0x%08x", ttypr);
+	LOG_DEBUG("didr = 0x%08x", didr);
+
+	/* Setup Breakpoint Register Pairs */
+	cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;
+	cortex_a8->brp_num_context = ((didr >> 20) & 0x0F) + 1;
+	cortex_a8->brp_num_available = cortex_a8->brp_num;
+	cortex_a8->brp_list = calloc(cortex_a8->brp_num, sizeof(cortex_a8_brp_t));
+//	cortex_a8->brb_enabled = ????;
+	for (i = 0; i < cortex_a8->brp_num; i++)
+	{
+		cortex_a8->brp_list[i].used = 0;
+		if (i < (cortex_a8->brp_num-cortex_a8->brp_num_context))
+			cortex_a8->brp_list[i].type = BRP_NORMAL;
+		else
+			cortex_a8->brp_list[i].type = BRP_CONTEXT;
+		cortex_a8->brp_list[i].value = 0;
+		cortex_a8->brp_list[i].control = 0;
+		cortex_a8->brp_list[i].BRPn = i;
+	}
+
+	/* Setup Watchpoint Register Pairs */
+	cortex_a8->wrp_num = ((didr >> 28) & 0x0F) + 1;
+	cortex_a8->wrp_num_available = cortex_a8->wrp_num;
+	cortex_a8->wrp_list = calloc(cortex_a8->wrp_num, sizeof(cortex_a8_wrp_t));
+	for (i = 0; i < cortex_a8->wrp_num; i++)
+	{
+		cortex_a8->wrp_list[i].used = 0;
+		cortex_a8->wrp_list[i].type = 0;
+		cortex_a8->wrp_list[i].value = 0;
+		cortex_a8->wrp_list[i].control = 0;
+		cortex_a8->wrp_list[i].WRPn = i;
+	}
+	LOG_DEBUG("Configured %i hw breakpoint pairs and %i hw watchpoint pairs",
+			cortex_a8->brp_num , cortex_a8->wrp_num);
+
+	target->type->examined = 1;
+
+	return retval;
+}
+
+/*
+ *	Cortex-A8 target creation and initialization
+ */
+
+void cortex_a8_build_reg_cache(target_t *target)
+{
+	reg_cache_t **cache_p = register_get_last_cache_p(&target->reg_cache);
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+
+	(*cache_p) = armv4_5_build_reg_cache(target, armv4_5);
+	armv4_5->core_cache = (*cache_p);
+}
+
+
+int cortex_a8_init_target(struct command_context_s *cmd_ctx,
+		struct target_s *target)
+{
+	cortex_a8_build_reg_cache(target);
+	return ERROR_OK;
+}
+
+int cortex_a8_init_arch_info(target_t *target,
+		cortex_a8_common_t *cortex_a8, jtag_tap_t *tap)
+{
+	armv4_5_common_t *armv4_5;
+	armv7a_common_t *armv7a;
+
+	armv7a = &cortex_a8->armv7a_common;
+	armv4_5 = &armv7a->armv4_5_common;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+	/* Setup cortex_a8_common_t */
+	cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
+	cortex_a8->arch_info = NULL;
+	armv7a->arch_info = cortex_a8;
+	armv4_5->arch_info = armv7a;
+
+	armv4_5_init_arch_info(target, armv4_5);
+
 	/* prepare JTAG information for the new target */
 	cortex_a8->jtag_info.tap = tap;
 	cortex_a8->jtag_info.scann_size = 4;
+LOG_DEBUG(" ");
+	swjdp->dp_select_value = -1;
+	swjdp->ap_csw_value = -1;
+	swjdp->ap_tar_value = -1;
+	swjdp->jtag_info = &cortex_a8->jtag_info;
+	swjdp->memaccess_tck = 80;
 
-	armv7m->swjdp_info.dp_select_value = -1;
-	armv7m->swjdp_info.ap_csw_value = -1;
-	armv7m->swjdp_info.ap_tar_value = -1;
-	armv7m->swjdp_info.jtag_info = &cortex_a8->jtag_info;
+	/* Number of bits for tar autoincrement, impl. dep. at least 10 */
+	swjdp->tar_autoincr_block = (1 << 10);
 
-	/* initialize arch-specific breakpoint handling */
+	cortex_a8->fast_reg_read = 0;
 
-	cortex_a8->common_magic = CORTEX_A8_COMMON_MAGIC;
-	cortex_a8->arch_info = NULL;
 
 	/* register arch-specific functions */
-	armv7m->examine_debug_reason = NULL;
+	armv7a->examine_debug_reason = NULL;
 
-	armv7m->pre_debug_entry = NULL;
-	armv7m->post_debug_entry = NULL;
+	armv7a->pre_debug_entry = NULL;
+	armv7a->post_debug_entry = cortex_a8_post_debug_entry;
 
-	armv7m->pre_restore_context = NULL;
-	armv7m->post_restore_context = NULL;
+	armv7a->pre_restore_context = NULL;
+	armv7a->post_restore_context = NULL;
+	armv7a->armv4_5_mmu.armv4_5_cache.ctype = -1;
+//	armv7a->armv4_5_mmu.get_ttb = armv7a_get_ttb;
+	armv7a->armv4_5_mmu.read_memory = cortex_a8_read_memory;
+	armv7a->armv4_5_mmu.write_memory = cortex_a8_write_memory;
+//	armv7a->armv4_5_mmu.disable_mmu_caches = armv7a_disable_mmu_caches;
+//	armv7a->armv4_5_mmu.enable_mmu_caches = armv7a_enable_mmu_caches;
+	armv7a->armv4_5_mmu.has_tiny_pages = 1;
+	armv7a->armv4_5_mmu.mmu_enabled = 0;
+	armv7a->read_cp15 = cortex_a8_read_cp15;
+	armv7a->write_cp15 = cortex_a8_write_cp15;
 
-	armv7m_init_arch_info(target, armv7m);
-	armv7m->arch_info = cortex_a8;
-	armv7m->load_core_reg_u32 = NULL;
-	armv7m->store_core_reg_u32 = NULL;
 
+//	arm7_9->handle_target_request = cortex_a8_handle_target_request;
+
+	armv4_5->read_core_reg = cortex_a8_read_core_reg;
+	armv4_5->write_core_reg = cortex_a8_write_core_reg;
+//	armv4_5->full_context = arm7_9_full_context;
+
+//	armv4_5->load_core_reg_u32 = cortex_a8_load_core_reg_u32;
+//	armv4_5->store_core_reg_u32 = cortex_a8_store_core_reg_u32;
+//	armv4_5->read_core_reg = armv4_5_read_core_reg; /* this is default */
+//	armv4_5->write_core_reg = armv4_5_write_core_reg;
+
 	target_register_timer_callback(cortex_a8_handle_target_request, 1, 1, target);
 
 	return ERROR_OK;
@@ -244,20 +1467,40 @@
 
 int cortex_a8_target_create(struct target_s *target, Jim_Interp *interp)
 {
-	cortex_a8_common_t *cortex_a8 = calloc(1,sizeof(cortex_a8_common_t));
+	cortex_a8_common_t *cortex_a8 = calloc(1, sizeof(cortex_a8_common_t));
 
 	cortex_a8_init_arch_info(target, cortex_a8, target->tap);
 
 	return ERROR_OK;
 }
 
+static int cortex_a8_handle_cache_info_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
+{
+	target_t *target = get_current_target(cmd_ctx);
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+
+	return armv4_5_handle_cache_info_command(cmd_ctx,
+			&armv7a->armv4_5_mmu.armv4_5_cache);
+}
+
+
 int cortex_a8_register_commands(struct command_context_s *cmd_ctx)
 {
-	int retval;
+	command_t *cortex_a8_cmd;
+	int retval = ERROR_OK;
 
-	retval = armv7m_register_commands(cmd_ctx);
+	armv4_5_register_commands(cmd_ctx);
+	armv7a_register_commands(cmd_ctx);
 
-	register_command(cmd_ctx, NULL, "cortex_a8", NULL, COMMAND_ANY, "cortex_a8 specific commands");
+	cortex_a8_cmd =	register_command(cmd_ctx, NULL, "cortex_a8",
+			NULL, COMMAND_ANY,
+			"cortex_a8 specific commands");
 
+	register_command(cmd_ctx, cortex_a8_cmd, "cache_info",
+			cortex_a8_handle_cache_info_command, COMMAND_EXEC,
+			"display information about target caches");
+
 	return retval;
 }

Modified: trunk/src/target/cortex_a8.h
===================================================================
--- trunk/src/target/cortex_a8.h	2009-08-25 06:57:26 UTC (rev 2608)
+++ trunk/src/target/cortex_a8.h	2009-08-25 06:58:34 UTC (rev 2609)
@@ -31,7 +31,8 @@
 
 #include "register.h"
 #include "target.h"
-#include "armv7m.h"
+#include "armv7a.h"
+#include "arm7_9_common.h"
 
 extern char* cortex_a8_state_strings[];
 
@@ -39,56 +40,82 @@
 
 #define CPUID		0x54011D00
 /* Debug Control Block */
-#define DCB_DHCSR	0x54011DF0
-#define DCB_DCRSR	0x54011DF4
-#define DCB_DCRDR	0x54011DF8
-#define DCB_DEMCR	0x54011DFC
+#define CPUDBG_DIDR		0x000
+#define CPUDBG_WFAR		0x018
+#define CPUDBG_DSCCR	0x028
+#define CPUDBG_DTRRX	0x080
+#define CPUDBG_ITR	0x084
+#define CPUDBG_DSCR	0x088
+#define CPUDBG_DTRTX	0x08c
+#define CPUDBG_DRCR	0x090
+#define CPUDBG_BVR_BASE	0x100
+#define CPUDBG_BCR_BASE	0x140
+#define CPUDBG_WVR_BASE	0x180
 
-typedef struct  cortex_a8_fp_comparator_s
+#define CPUDBG_CPUID	0xD00
+#define CPUDBG_CTYPR	0xD04
+#define CPUDBG_TTYPR	0xD0C
+
+#define BRP_NORMAL 0
+#define BRP_CONTEXT 1
+
+typedef struct  cortex_a8_brp_s
 {
 	int used;
 	int type;
-	uint32_t fpcr_value;
-	uint32_t fpcr_address;
-} cortex_a8_fp_comparator_t;
+	uint32_t value;
+	uint32_t control;
+	uint8_t 	BRPn;
+} cortex_a8_brp_t;
 
-typedef struct  cortex_a8_dwt_comparator_s
+typedef struct  cortex_a8_wrp_s
 {
 	int used;
-	uint32_t comp;
-	uint32_t mask;
-	uint32_t function;
-	uint32_t dwt_comparator_address;
-} cortex_a8_dwt_comparator_t;
+	int type;
+	uint32_t value;
+	uint32_t control;
+	uint8_t 	WRPn;
+} cortex_a8_wrp_t;
 
 typedef struct cortex_a8_common_s
 {
 	int common_magic;
 	arm_jtag_t jtag_info;
 
+	/* Core Debug Unit */
+	uint32_t debug_base;
+	uint8_t debug_ap;
+	uint8_t memory_ap;
+
 	/* Context information */
-	uint32_t dcb_dhcsr;
+	uint32_t cpudbg_dscr;
 	uint32_t nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */
 	uint32_t nvic_icsr;  /* Interrupt Control State Register - shows active and pending IRQ */
 
-	/* Flash Patch and Breakpoint (FPB) */
-	int fp_num_lit;
-	int fp_num_code;
-	int fp_code_available;
-	int fpb_enabled;
-	int auto_bp_type;
-	cortex_a8_fp_comparator_t *fp_comparator_list;
+	/* Saved cp15 registers */
+	uint32_t cp15_control_reg;
+	uint32_t cp15_aux_control_reg;
 
-	/* Data Watchpoint and Trace (DWT) */
-	int dwt_num_comp;
-	int dwt_comp_available;
-	cortex_a8_dwt_comparator_t *dwt_comparator_list;
+	/* Breakpoint register pairs */
+	int brp_num_context;
+	int brp_num;
+	int brp_num_available;
+//	int brp_enabled;
+	cortex_a8_brp_t *brp_list;
 
+	/* Watchpoint register pairs */
+	int wrp_num;
+	int wrp_num_available;
+	cortex_a8_wrp_t *wrp_list;
+
 	/* Interrupts */
 	int intlinesnum;
 	uint32_t *intsetenable;
 
-	armv7m_common_t armv7m;
+	/* Use cortex_a8_read_regs_through_mem for fast register reads */
+	int fast_reg_read;
+
+	armv7a_common_t armv7a_common;
 	void *arch_info;
 } cortex_a8_common_t;
 

[Openocd-svn] r2608 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 08:57:26 +0200 (Tue, 25 Aug 2009)
New Revision: 2608

Added:
   trunk/src/target/armv7a.c
   trunk/src/target/armv7a.h
Modified:
   trunk/src/target/Makefile.am
Log:
David Brownell Subset of Cortex-A8 support from Magnus:  create an armv7a file
and seed it with DAP access support using the current ADIv5 code.
(With tweaks and cleanup from ?\195?\152yvind and Dave.)

The ARMv7-AR architecture manual is not publicly available (even
in subset form like the ARMv7-M spec), so it's hard to distinguish
between the Cortex-A8 implementation and the ARMv7-A architecture.

The register set presumably is architectural, and so it's stored
here; it's like earlier ARMs, with small additions.  Ditto the
instruction set, though Thumb2 support is used (extending Thumb
support from ARMv6 with more 32-bit instructions) and there's this
ThumbEE thing too.  There is a new "debug monitor" mode, not yet
fully addressed here, to support debugging in environments (like
motor control) where halting debug mode is inadvisable.

Modified: trunk/src/target/Makefile.am
===================================================================
--- trunk/src/target/Makefile.am	2009-08-25 06:45:40 UTC (rev 2607)
+++ trunk/src/target/Makefile.am	2009-08-25 06:57:26 UTC (rev 2608)
@@ -38,6 +38,7 @@
 	arm_simulator.c \
 	image.c \
 	armv7m.c \
+	armv7a.c \
 	cortex_m3.c \
 	cortex_a8.c \
 	arm_adi_v5.c \
@@ -80,6 +81,7 @@
 	arm_simulator.h \
 	image.h \
 	armv7m.h \
+	armv7a.h \
 	cortex_m3.h \
 	cortex_a8.h \
 	arm_adi_v5.h \

Added: trunk/src/target/armv7a.c
===================================================================
--- trunk/src/target/armv7a.c	2009-08-25 06:45:40 UTC (rev 2607)
+++ trunk/src/target/armv7a.c	2009-08-25 06:57:26 UTC (rev 2608)
@@ -0,0 +1,301 @@
+/***************************************************************************
+ *    Copyright (C) 2009 by David Brownell                                 *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "replacements.h"
+
+#include "armv7a.h"
+
+#include "target.h"
+#include "register.h"
+#include "log.h"
+#include "binarybuffer.h"
+#include "command.h"
+
+#include <stdlib.h>
+#include <string.h>
+#include <unistd.h>
+
+bitfield_desc_t armv7a_psr_bitfield_desc[] =
+{
+	{"M[4:0]", 5},
+	{"T", 1},
+	{"F", 1},
+	{"I", 1},
+	{"A", 1},
+	{"E", 1},
+	{"IT[7:2]", 6},
+	{"GE[3:0]", 4},
+	{"reserved(DNM)", 4},
+	{"J", 1},
+	{"IT[0:1]", 2},
+	{"Q", 1},
+	{"V", 1},
+	{"C", 1},
+	{"Z", 1},
+	{"N", 1},
+};
+
+char* armv7a_core_reg_list[] =
+{
+	"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
+	"r8", "r9", "r10", "r11", "r12", "r13_usr", "lr_usr", "pc",
+	"r8_fiq", "r9_fiq", "r10_fiq", "r11_fiq", "r12_fiq", "r13_fiq", "lr_fiq",
+	"r13_irq", "lr_irq",
+	"r13_svc", "lr_svc",
+	"r13_abt", "lr_abt",
+	"r13_und", "lr_und",
+	"cpsr", "spsr_fiq", "spsr_irq", "spsr_svc", "spsr_abt", "spsr_und",
+	"r13_mon", "lr_mon", "spsr_mon"
+};
+
+char * armv7a_mode_strings_list[] =
+{
+	"Illegal mode value", "System and User", "FIQ", "IRQ",
+	"Supervisor", "Abort", "Undefined", "Monitor"
+};
+
+/* Hack! Yuk! allow -1 index, which simplifies codepaths elsewhere in the code */
+char** armv7a_mode_strings = armv7a_mode_strings_list+1;
+
+char* armv7a_state_strings[] =
+{
+	"ARM", "Thumb", "Jazelle", "ThumbEE"
+};
+
+armv7a_core_reg_t armv7a_core_reg_list_arch_info[] =
+{
+	{0, ARMV4_5_MODE_ANY, NULL, NULL},
+	{1, ARMV4_5_MODE_ANY, NULL, NULL},
+	{2, ARMV4_5_MODE_ANY, NULL, NULL},
+	{3, ARMV4_5_MODE_ANY, NULL, NULL},
+	{4, ARMV4_5_MODE_ANY, NULL, NULL},
+	{5, ARMV4_5_MODE_ANY, NULL, NULL},
+	{6, ARMV4_5_MODE_ANY, NULL, NULL},
+	{7, ARMV4_5_MODE_ANY, NULL, NULL},
+	{8, ARMV4_5_MODE_ANY, NULL, NULL},
+	{9, ARMV4_5_MODE_ANY, NULL, NULL},
+	{10, ARMV4_5_MODE_ANY, NULL, NULL},
+	{11, ARMV4_5_MODE_ANY, NULL, NULL},
+	{12, ARMV4_5_MODE_ANY, NULL, NULL},
+	{13, ARMV4_5_MODE_USR, NULL, NULL},
+	{14, ARMV4_5_MODE_USR, NULL, NULL},
+	{15, ARMV4_5_MODE_ANY, NULL, NULL},
+
+	{8, ARMV4_5_MODE_FIQ, NULL, NULL},
+	{9, ARMV4_5_MODE_FIQ, NULL, NULL},
+	{10, ARMV4_5_MODE_FIQ, NULL, NULL},
+	{11, ARMV4_5_MODE_FIQ, NULL, NULL},
+	{12, ARMV4_5_MODE_FIQ, NULL, NULL},
+	{13, ARMV4_5_MODE_FIQ, NULL, NULL},
+	{14, ARMV4_5_MODE_FIQ, NULL, NULL},
+
+	{13, ARMV4_5_MODE_IRQ, NULL, NULL},
+	{14, ARMV4_5_MODE_IRQ, NULL, NULL},
+
+	{13, ARMV4_5_MODE_SVC, NULL, NULL},
+	{14, ARMV4_5_MODE_SVC, NULL, NULL},
+
+	{13, ARMV4_5_MODE_ABT, NULL, NULL},
+	{14, ARMV4_5_MODE_ABT, NULL, NULL},
+
+	{13, ARMV4_5_MODE_UND, NULL, NULL},
+	{14, ARMV4_5_MODE_UND, NULL, NULL},
+
+	{16, ARMV4_5_MODE_ANY, NULL, NULL},
+	{16, ARMV4_5_MODE_FIQ, NULL, NULL},
+	{16, ARMV4_5_MODE_IRQ, NULL, NULL},
+	{16, ARMV4_5_MODE_SVC, NULL, NULL},
+	{16, ARMV4_5_MODE_ABT, NULL, NULL},
+	{16, ARMV4_5_MODE_UND, NULL, NULL},
+
+	{13, ARMV7A_MODE_MON, NULL, NULL},
+	{14, ARMV7A_MODE_MON, NULL, NULL},
+	{16, ARMV7A_MODE_MON, NULL, NULL}
+};
+
+/* map core mode (USR, FIQ, ...) and register number to indizes into the register cache */
+int armv7a_core_reg_map[8][17] =
+{
+	{	/* USR */
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
+	},
+	{	/* FIQ */
+		0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 15, 32
+	},
+	{	/* IRQ */
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 23, 24, 15, 33
+	},
+	{	/* SVC */
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 25, 26, 15, 34
+	},
+	{	/* ABT */
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 27, 28, 15, 35
+	},
+	{	/* UND */
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 29, 30, 15, 36
+	},
+	{	/* SYS */
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
+	},
+	{	/* MON */
+		/* TODO Fix the register mapping for mon, we need r13_mon,
+		 * r14_mon and spsr_mon
+		 */
+		0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
+	}
+};
+
+uint8_t armv7a_gdb_dummy_fp_value[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+reg_t armv7a_gdb_dummy_fp_reg =
+{
+	"GDB dummy floating-point register", armv7a_gdb_dummy_fp_value,
+			0, 1, 96, NULL, 0, NULL, 0
+};
+
+int armv7a_arch_state(struct target_s *target)
+{
+	static const char *state[] =
+	{
+		"disabled", "enabled"
+	};
+
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+
+	if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC)
+	{
+		LOG_ERROR("BUG: called for a non-ARMv4/5 target");
+		exit(-1);
+	}
+
+	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
+			 "%s: 0x%8.8x pc: 0x%8.8x\n"
+			 "MMU: %s, D-Cache: %s, I-Cache: %s",
+		 armv7a_state_strings[armv4_5->core_state],
+		 Jim_Nvp_value2name_simple(nvp_target_debug_reason,
+				target->debug_reason)->name,
+		 armv7a_mode_strings[
+			armv7a_mode_to_number(armv4_5->core_mode)],
+		 armv7a_core_reg_list[armv7a_core_reg_map[
+			armv7a_mode_to_number(armv4_5->core_mode)][16]],
+		 buf_get_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
+				armv4_5->core_mode, 16).value, 0, 32),
+		 buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32),
+		 state[armv7a->armv4_5_mmu.mmu_enabled],
+		 state[armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
+		 state[armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
+
+	return ERROR_OK;
+}
+
+
+static int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
+{
+	target_t *target = get_current_target(cmd_ctx);
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+	return dap_baseaddr_command(cmd_ctx, swjdp, args, argc);
+}
+
+static int handle_dap_memaccess_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
+{
+	target_t *target = get_current_target(cmd_ctx);
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+	return dap_memaccess_command(cmd_ctx, swjdp, args, argc);
+}
+
+static int handle_dap_apsel_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
+{
+	target_t *target = get_current_target(cmd_ctx);
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+	return dap_apsel_command(cmd_ctx, swjdp, args, argc);
+}
+
+static int handle_dap_apid_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
+{
+	target_t *target = get_current_target(cmd_ctx);
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+	return dap_apid_command(cmd_ctx, swjdp, args, argc);
+}
+
+static int handle_dap_info_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
+{
+	target_t *target = get_current_target(cmd_ctx);
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+	uint32_t apsel;
+
+	apsel =  swjdp->apsel;
+	if (argc > 0)
+		apsel = strtoul(args[0], NULL, 0);
+
+	return dap_info_command(cmd_ctx, swjdp, apsel);
+}
+
+int armv7a_register_commands(struct command_context_s *cmd_ctx)
+{
+	command_t *arm_adi_v5_dap_cmd;
+
+	arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap",
+			NULL, COMMAND_ANY,
+			"cortex dap specific commands");
+
+	register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info",
+			handle_dap_info_command, COMMAND_EXEC,
+			"dap info for ap [num], "
+			"default currently selected AP");
+	register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel",
+			handle_dap_apsel_command, COMMAND_EXEC,
+			"select a different AP [num] (default 0)");
+	register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid",
+			handle_dap_apid_command, COMMAND_EXEC,
+			"return id reg from AP [num], "
+			"default currently selected AP");
+	register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr",
+			handle_dap_baseaddr_command, COMMAND_EXEC,
+			"return debug base address from AP [num], "
+			"default currently selected AP");
+	register_command(cmd_ctx, arm_adi_v5_dap_cmd, "memaccess",
+			handle_dap_memaccess_command, COMMAND_EXEC,
+			"set/get number of extra tck for mem-ap memory "
+			"bus access [0-255]");
+
+	return ERROR_OK;
+}

Added: trunk/src/target/armv7a.h
===================================================================
--- trunk/src/target/armv7a.h	2009-08-25 06:45:40 UTC (rev 2607)
+++ trunk/src/target/armv7a.h	2009-08-25 06:57:26 UTC (rev 2608)
@@ -0,0 +1,176 @@
+/***************************************************************************
+ *    Copyright (C) 2009 by David Brownell                                 *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+#ifndef ARMV7A_H
+#define ARMV7A_H
+
+#include "register.h"
+#include "target.h"
+#include "log.h"
+#include "arm_adi_v5.h"
+#include "armv4_5.h"
+#include "armv4_5_mmu.h"
+#include "armv4_5_cache.h"
+
+typedef enum armv7a_mode
+{
+	ARMV7A_MODE_USR = 16,
+	ARMV7A_MODE_FIQ = 17,
+	ARMV7A_MODE_IRQ = 18,
+	ARMV7A_MODE_SVC = 19,
+	ARMV7A_MODE_ABT = 23,
+	ARMV7A_MODE_UND = 27,
+	ARMV7A_MODE_SYS = 31,
+	ARMV7A_MODE_MON = 22,
+	ARMV7A_MODE_ANY = -1
+} armv7a_t;
+
+char **armv7a_mode_strings;
+
+typedef enum armv7a_state
+{
+	ARMV7A_STATE_ARM,
+	ARMV7A_STATE_THUMB,
+	ARMV7A_STATE_JAZELLE,
+	ARMV7A_STATE_THUMBEE,
+} armv7a_state_t;
+
+extern char *armv7a_state_strings[];
+
+int armv7a_core_reg_map[8][17];
+
+#define ARMV7A_CORE_REG_MODE(cache, mode, num) \
+		cache->reg_list[armv7a_core_reg_map[armv7a_mode_to_number(mode)][num]]
+#define ARMV7A_CORE_REG_MODENUM(cache, mode, num) \
+		cache->reg_list[armv7a_core_reg_map[mode][num]]
+
+enum
+{
+	ARM_PC  = 15,
+	ARM_CPSR = 16
+}
+;
+/* offsets into armv4_5 core register cache */
+enum
+{
+	ARMV7A_CPSR = 31,
+	ARMV7A_SPSR_FIQ = 32,
+	ARMV7A_SPSR_IRQ = 33,
+	ARMV7A_SPSR_SVC = 34,
+	ARMV7A_SPSR_ABT = 35,
+	ARMV7A_SPSR_UND = 36
+};
+
+#define ARMV4_5_COMMON_MAGIC 0x0A450A45
+#define ARMV7_COMMON_MAGIC 0x0A450999
+
+typedef struct armv7a_common_s
+{
+	int common_magic;
+	reg_cache_t *core_cache;
+	enum armv7a_mode core_mode;
+	enum armv7a_state core_state;
+
+	/* arm adp debug port */
+	swjdp_common_t swjdp_info;
+	armv4_5_mmu_common_t armv4_5_mmu;
+	armv4_5_common_t armv4_5_common;
+	void *arch_info;
+
+//	int (*full_context)(struct target_s *target);
+//	int (*read_core_reg)(struct target_s *target, int num, enum armv7a_mode mode);
+//	int (*write_core_reg)(struct target_s *target, int num, enum armv7a_mode mode, u32 value);
+	int (*read_cp15)(struct target_s *target,
+			uint32_t op1, uint32_t op2,
+			uint32_t CRn, uint32_t CRm, uint32_t *value);
+	int (*write_cp15)(struct target_s *target,
+			uint32_t op1, uint32_t op2,
+			uint32_t CRn, uint32_t CRm, uint32_t value);
+
+	int (*examine_debug_reason)(target_t *target);
+	void (*pre_debug_entry)(target_t *target);
+	void (*post_debug_entry)(target_t *target);
+
+	void (*pre_restore_context)(target_t *target);
+	void (*post_restore_context)(target_t *target);
+
+} armv7a_common_t;
+
+typedef struct armv7a_algorithm_s
+{
+	int common_magic;
+
+	enum armv7a_mode core_mode;
+	enum armv7a_state core_state;
+} armv7a_algorithm_t;
+
+typedef struct armv7a_core_reg_s
+{
+	int num;
+	enum armv7a_mode mode;
+	target_t *target;
+	armv7a_common_t *armv7a_common;
+} armv7a_core_reg_t;
+
+int armv7a_arch_state(struct target_s *target);
+reg_cache_t *armv7a_build_reg_cache(target_t *target,
+		armv7a_common_t *armv7a_common);
+int armv7a_register_commands(struct command_context_s *cmd_ctx);
+int armv7a_init_arch_info(target_t *target, armv7a_common_t *armv7a);
+
+/* map psr mode bits to linear number */
+static inline int armv7a_mode_to_number(enum armv7a_mode mode)
+{
+	switch (mode)
+	{
+		case ARMV7A_MODE_USR: return 0; break;
+		case ARMV7A_MODE_FIQ: return 1; break;
+		case ARMV7A_MODE_IRQ: return 2; break;
+		case ARMV7A_MODE_SVC: return 3; break;
+		case ARMV7A_MODE_ABT: return 4; break;
+		case ARMV7A_MODE_UND: return 5; break;
+		case ARMV7A_MODE_SYS: return 6; break;
+		case ARMV7A_MODE_MON: return 7; break;
+		case ARMV7A_MODE_ANY: return 0; break;	/* map MODE_ANY to user mode */
+		default:
+			LOG_ERROR("invalid mode value encountered");
+			return -1;
+	}
+}
+
+/* map linear number to mode bits */
+static inline enum armv7a_mode armv7a_number_to_mode(int number)
+{
+	switch(number)
+	{
+		case 0: return ARMV7A_MODE_USR; break;
+		case 1: return ARMV7A_MODE_FIQ; break;
+		case 2: return ARMV7A_MODE_IRQ; break;
+		case 3: return ARMV7A_MODE_SVC; break;
+		case 4: return ARMV7A_MODE_ABT; break;
+		case 5: return ARMV7A_MODE_UND; break;
+		case 6: return ARMV7A_MODE_SYS; break;
+		case 7: return ARMV7A_MODE_MON; break;
+		default:
+			LOG_ERROR("mode index out of bounds");
+			return ARMV7A_MODE_ANY;
+	}
+};
+
+
+#endif /* ARMV4_5_H */
\ No newline at end of file

[Openocd-svn] r2607 - trunk/src/helper

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 08:45:40 +0200 (Tue, 25 Aug 2009)
New Revision: 2607

Modified:
   trunk/src/helper/types.h
Log:
add missing isblank() for eCos

Modified: trunk/src/helper/types.h
===================================================================
--- trunk/src/helper/types.h	2009-08-24 07:53:46 UTC (rev 2606)
+++ trunk/src/helper/types.h	2009-08-25 06:45:40 UTC (rev 2607)
@@ -153,6 +153,8 @@
 #define UINT64_MAX (__CONCAT(INT64_MAX, U) * 2ULL + 1ULL)
 
 
+/* C99, eCos is C90 compliant (with bits of C99) */
+#define isblank(c) ((c) == ' ' || (c) == '\t')
 
 
 #endif

[Openocd-svn] r2606 - in trunk/src: helper jtag server svf target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-24 09:53:46 +0200 (Mon, 24 Aug 2009)
New Revision: 2606

Modified:
   trunk/src/helper/command.c
   trunk/src/jtag/tcl.c
   trunk/src/jtag/usbprog.c
   trunk/src/server/telnet_server.c
   trunk/src/svf/svf.c
   trunk/src/target/embeddedice.c
   trunk/src/target/etm.c
Log:
Steve Grubb <sg...@re...> fix various and sundry leaks

Modified: trunk/src/helper/command.c
===================================================================
--- trunk/src/helper/command.c	2009-08-24 07:26:05 UTC (rev 2605)
+++ trunk/src/helper/command.c	2009-08-24 07:53:46 UTC (rev 2606)
@@ -117,6 +117,10 @@
 		words[i] = strdup(w);
 		if (words[i] == NULL)
 		{
+			int j;
+			for (j = 0; j < i; j++)
+				free(words[j]);
+			free(words);
 			return JIM_ERR;
 		}
 	}

Modified: trunk/src/jtag/tcl.c
===================================================================
--- trunk/src/jtag/tcl.c	2009-08-24 07:26:05 UTC (rev 2605)
+++ trunk/src/jtag/tcl.c	2009-08-24 07:53:46 UTC (rev 2606)
@@ -220,6 +220,7 @@
 	 * */
 	if (goi->argc < 3) {
 		Jim_SetResult_sprintf(goi->interp, "Missing CHIP TAP OPTIONS ....");
+		free(pTap);
 		return JIM_ERR;
 	}
 	Jim_GetOpt_String(goi, &cp, NULL);
@@ -249,6 +250,8 @@
 		e = Jim_GetOpt_Nvp(goi, opts, &n);
 		if (e != JIM_OK) {
 			Jim_GetOpt_NvpUnknown(goi, opts, 0);
+			free((void *)pTap->dotted_name);
+			free(pTap);
 			return e;
 		}
 		LOG_DEBUG("Processing option: %s", n->name);
@@ -266,12 +269,16 @@
 			e = Jim_GetOpt_Wide(goi, &w);
 			if (e != JIM_OK) {
 				Jim_SetResult_sprintf(goi->interp, "option: %s bad parameter", n->name);
+				free((void *)pTap->dotted_name);
+				free(pTap);
 				return e;
 			}
 
 			new_expected_ids = malloc(sizeof(uint32_t) * (pTap->expected_ids_cnt + 1));
 			if (new_expected_ids == NULL) {
 				Jim_SetResult_sprintf(goi->interp, "no memory");
+				free((void *)pTap->dotted_name);
+				free(pTap);
 				return JIM_ERR;
 			}
 
@@ -290,6 +297,8 @@
 			e = Jim_GetOpt_Wide(goi, &w);
 			if (e != JIM_OK) {
 				Jim_SetResult_sprintf(goi->interp, "option: %s bad parameter", n->name);
+				free((void *)pTap->dotted_name);
+				free(pTap);
 				return e;
 			}
 			switch (n->value) {
@@ -303,6 +312,8 @@
 				if (is_bad_irval(pTap->ir_length, w)) {
 					LOG_ERROR("IR mask %x too big",
 							(int) w);
+					free((void *)pTap->dotted_name);
+					free(pTap);
 					return ERROR_FAIL;
 				}
 				pTap->ir_capture_mask = w;
@@ -312,6 +323,8 @@
 				if (is_bad_irval(pTap->ir_length, w)) {
 					LOG_ERROR("IR capture %x too big",
 							(int) w);
+					free((void *)pTap->dotted_name);
+					free(pTap);
 					return ERROR_FAIL;
 				}
 				pTap->ir_capture_value = w;
@@ -1144,7 +1157,12 @@
 		tap = jtag_tap_by_string(args[i*2]);
 		if (tap == NULL)
 		{
+			int j;
+			for (j = 0; j < i; j++)
+				free(fields[j].out_value);
+                        free(fields);
 			command_print(cmd_ctx, "Tap: %s unknown", args[i*2]);
+
 			return ERROR_FAIL;
 		}
 		int field_size = tap->ir_length;

Modified: trunk/src/jtag/usbprog.c
===================================================================
--- trunk/src/jtag/usbprog.c	2009-08-24 07:26:05 UTC (rev 2605)
+++ trunk/src/jtag/usbprog.c	2009-08-24 07:53:46 UTC (rev 2606)
@@ -435,6 +435,7 @@
 			}
 		}
 	}
+	free(tmp);
 	return 0;
 }
 

Modified: trunk/src/server/telnet_server.c
===================================================================
--- trunk/src/server/telnet_server.c	2009-08-24 07:26:05 UTC (rev 2605)
+++ trunk/src/server/telnet_server.c	2009-08-24 07:53:46 UTC (rev 2606)
@@ -597,6 +597,7 @@
 	if (telnet_port == 0)
 	{
 		LOG_INFO("telnet port disabled");
+		free(telnet_service);
 		return ERROR_OK;
 	}
 

Modified: trunk/src/svf/svf.c
===================================================================
--- trunk/src/svf/svf.c	2009-08-24 07:26:05 UTC (rev 2605)
+++ trunk/src/svf/svf.c	2009-08-24 07:53:46 UTC (rev 2606)
@@ -1322,6 +1322,7 @@
 				if (!svf_tap_state_is_valid(path[i]))
 				{
 					LOG_ERROR("%s is not valid state", svf_tap_state_name[path[i]]);
+					free(path);
 					return ERROR_FAIL;
 				}
 				if (TAP_RESET == path[i])
@@ -1348,6 +1349,7 @@
 				else
 				{
 					LOG_ERROR("%s is not valid state", svf_tap_state_name[path[num_of_argu - 1]]);
+					free(path);
 					return ERROR_FAIL;
 				}
 			}

Modified: trunk/src/target/embeddedice.c
===================================================================
--- trunk/src/target/embeddedice.c	2009-08-24 07:26:05 UTC (rev 2605)
+++ trunk/src/target/embeddedice.c	2009-08-24 07:53:46 UTC (rev 2606)
@@ -197,6 +197,7 @@
 			free(reg_list[i].value);
 		}
 		free(reg_list);
+		free(reg_cache);
 		free(arch_info);
 		return NULL;
 	}

Modified: trunk/src/target/etm.c
===================================================================
--- trunk/src/target/etm.c	2009-08-24 07:26:05 UTC (rev 2605)
+++ trunk/src/target/etm.c	2009-08-24 07:53:46 UTC (rev 2606)
@@ -246,6 +246,12 @@
 		if (!etb)
 		{
 			LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
+			for (i = 0; i < num_regs; i++)
+			{
+				free(reg_list[i].value);
+			}
+			free(reg_cache);
+			free(arch_info);
 			return ERROR_OK;
 		}
 
@@ -1202,6 +1208,7 @@
 
 	if (argc != 5)
 	{
+		free(etm_ctx);
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
@@ -1209,12 +1216,14 @@
 	if (!target)
 	{
 		LOG_ERROR("target '%s' not defined", args[0]);
+		free(etm_ctx);
 		return ERROR_FAIL;
 	}
 
 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
 	{
 		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
+		free(etm_ctx);
 		return ERROR_FAIL;
 	}
 
@@ -1231,6 +1240,7 @@
 			break;
 		default:
 			command_print(cmd_ctx, "unsupported ETM port width '%s', must be 4, 8 or 16", args[1]);
+			free(etm_ctx);
 			return ERROR_FAIL;
 	}
 
@@ -1249,6 +1259,7 @@
 	else
 	{
 		command_print(cmd_ctx, "unsupported ETM port mode '%s', must be 'normal', 'multiplexed' or 'demultiplexed'", args[2]);
+		free(etm_ctx);
 		return ERROR_FAIL;
 	}
 
@@ -1263,6 +1274,7 @@
 	else
 	{
 		command_print(cmd_ctx, "unsupported ETM port clocking '%s', must be 'full' or 'half'", args[3]);
+		free(etm_ctx);
 		return ERROR_FAIL;
 	}
 

[Openocd-svn] r2605 - trunk/src/jtag

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-24 09:26:05 +0200 (Mon, 24 Aug 2009)
New Revision: 2605

Modified:
   trunk/src/jtag/core.c
Log:
Jonas Horberg <jho...@sa...> 
The trunk is currently broken for interfaces without
the speed_div function (interface specific clock speed
value to kHz conversion). Example: parport.

Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-08-21 11:23:24 UTC (rev 2604)
+++ trunk/src/jtag/core.c	2009-08-24 07:26:05 UTC (rev 2605)
@@ -1153,9 +1153,8 @@
 	int actual_khz = requested_khz;
 	int retval = jtag_get_speed_readable(&actual_khz);
 	if (ERROR_OK != retval)
-		return retval;
-
-	if (actual_khz)
+		LOG_INFO("interface specific clock speed value %d", jtag_get_speed());
+	else if (actual_khz)
 	{
 		if ((CLOCK_MODE_RCLK == clock_mode)
 			|| ((CLOCK_MODE_KHZ == clock_mode) && !requested_khz))

[Openocd-svn] r2604 - in trunk/tcl: board target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-21 13:23:24 +0200 (Fri, 21 Aug 2009)
New Revision: 2604

Added:
   trunk/tcl/target/at91sam7sx.cfg
Removed:
   trunk/tcl/board/at91sam7sx.cfg
   trunk/tcl/board/at91sam9260.cfg
   trunk/tcl/board/unknown-board-atmel-at91sam9260.cfg
Modified:
   trunk/tcl/target/at91sam9260.cfg
Log:
Pieter Conradie <Pie...@ps...> shuffle things around to the right spots. Should have been done in previous commit.

Deleted: trunk/tcl/board/at91sam7sx.cfg
===================================================================
--- trunk/tcl/board/at91sam7sx.cfg	2009-08-21 09:01:00 UTC (rev 2603)
+++ trunk/tcl/board/at91sam7sx.cfg	2009-08-21 11:23:24 UTC (rev 2604)
@@ -1,55 +0,0 @@
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only srst_pulls_trst
-
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
-   set  _CHIPNAME at91sam7s
-}
-
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
-   set  _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   set _CPUTAPID 0x3f0f0f0f
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
-$_TARGETNAME configure -event reset-init { 
-        soft_reset_halt
-        # RSTC_CR : Reset peripherals
-        mww 0xfffffd00 0xa5000004
-        # disable watchdog
-	mww 0xfffffd44 0x00008000	
-	# enable user reset
-	mww 0xfffffd08 0xa5000001	
-	# CKGR_MOR : enable the main oscillator
-	mww 0xfffffc20 0x00000601	
-	sleep 10
-	# CKGR_PLLR: 96.1097 MHz
-	mww 0xfffffc2c 0x00481c0e 	
-	sleep 10
-	# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
-	mww 0xfffffc30 0x00000007	
-	sleep 10
-	# MC_FMR: flash mode (FWS=1,FMCN=73)
-	mww 0xffffff60 0x00490100	
-	sleep 100        
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
-flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
-
-# For more information about the configuration files, take a look at:
-# openocd.texi

Deleted: trunk/tcl/board/at91sam9260.cfg
===================================================================
--- trunk/tcl/board/at91sam9260.cfg	2009-08-21 09:01:00 UTC (rev 2603)
+++ trunk/tcl/board/at91sam9260.cfg	2009-08-21 11:23:24 UTC (rev 2604)
@@ -1,44 +0,0 @@
-######################################
-# Target:    Atmel AT91SAM9260
-######################################
-
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
-   set  _CHIPNAME at91sam9260
-}
-
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
-   set  _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-  # force an error till we get a good number
-   set _CPUTAPID 0x0792603f
-}
-
-reset_config trst_and_srst separate trst_push_pull srst_open_drain
-
-#
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-jtag_nsrst_delay 300
-jtag_ntrst_delay 10
-
-jtag_rclk 3
-
-######################
-# Target configuration
-######################
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-
-# Internal sram1 memory
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
-
-

Deleted: trunk/tcl/board/unknown-board-atmel-at91sam9260.cfg
===================================================================
--- trunk/tcl/board/unknown-board-atmel-at91sam9260.cfg	2009-08-21 09:01:00 UTC (rev 2603)
+++ trunk/tcl/board/unknown-board-atmel-at91sam9260.cfg	2009-08-21 11:23:24 UTC (rev 2604)
@@ -1,82 +0,0 @@
-# Thanks to Pieter Conradie for this script! 
-# Target:    Atmel AT91SAM9260
-######################################
-
-# We add to the minimal configuration.
-source [find target/at91sam9260.cfg]
-
-######################
-# Target configuration
-######################
-
-$_TARGETNAME configure -event reset-init {
-	# at reset chip runs at 32khz
-	jtag_khz 8
-	mww 0xfffffd08 0xa5000501         # RSTC_MR : enable user reset
-	mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
-
-	mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
-	sleep 20                          # wait 20 ms
-	mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
-	sleep 10                          # wait 10 ms
-	mww 0xfffffc28 0x2060bf09         # CKGR_PLLAR: Set PLLA Register for 198,656MHz
-	sleep 20                          # wait 20 ms
-	mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler
-	sleep 10                          # wait 10 ms
-	mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected
-	sleep 10                          # wait 10 ms
-
-	# Now run at anything fast... ie: 10mhz!
-	jtag_khz 10000                    # Increase JTAG Speed to 6 MHz
-	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
-
-	mww 0xffffec00 0x01020102         # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
-	mww 0xffffec04 0x09070806         # SMC_PULSE0
-	mww 0xffffec08 0x000d000b         # SMC_CYCLE0
-	mww 0xffffec0c 0x00001003         # SMC_MODE0
-
-	flash probe 0                     # Identify flash bank 0
-
-	mww 0xfffff870 0xffff0000         # PIO_ASR : Select peripheral function for D15..D31
-	mww 0xfffff804 0xffff0000         # PIO_PDR : Disable PIO function for D15..D31
-
-	mww 0xffffef1c 0x2                # EBI_CSA : Assign EBI Chip Select 1 to SDRAM
-
-	#mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
-	mww 0xffffea08 0x85227254         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S641632H-UC75 : 1M x 16Bit x 4 Banks)
-
-	mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
-	mww 0x20000000 0
-	mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
-	mww 0x20000000 0
-	mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
-	mww 0x20000000 0
-	mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
-	mww 0x20000000 0
-	mww 0xffffea04 0x5d2              # SDRAMC_TR : Set refresh timer count to 15us
-}
-
-
-#####################
-# Flash configuration
-#####################
-
-#flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x10000000 0x01000000 2 2 0
-

Copied: trunk/tcl/target/at91sam7sx.cfg (from rev 2603, trunk/tcl/board/at91sam7sx.cfg)

Modified: trunk/tcl/target/at91sam9260.cfg
===================================================================
--- trunk/tcl/target/at91sam9260.cfg	2009-08-21 09:01:00 UTC (rev 2603)
+++ trunk/tcl/target/at91sam9260.cfg	2009-08-21 11:23:24 UTC (rev 2604)
@@ -21,14 +21,16 @@
    set _CPUTAPID 0x0792603f
 }
 
-reset_config trst_and_srst
+reset_config trst_and_srst separate trst_push_pull srst_open_drain
 
 #
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
+jtag_nsrst_delay 300
+jtag_ntrst_delay 10
 
+jtag_rclk 3
+
 ######################
 # Target configuration
 ######################

[Openocd-svn] r2603 - trunk/tcl/board

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-21 11:01:00 +0200 (Fri, 21 Aug 2009)
New Revision: 2603

Modified:
   trunk/tcl/board/at91sam7sx.cfg
   trunk/tcl/board/at91sam9260.cfg
   trunk/tcl/board/atmel_at91sam7s-ek.cfg
   trunk/tcl/board/atmel_at91sam9260-ek.cfg
   trunk/tcl/board/unknown_at91sam9260.cfg
Log:
native line endings

Modified: trunk/tcl/board/at91sam7sx.cfg
===================================================================
--- trunk/tcl/board/at91sam7sx.cfg	2009-08-21 08:58:49 UTC (rev 2602)
+++ trunk/tcl/board/at91sam7sx.cfg	2009-08-21 09:01:00 UTC (rev 2603)
@@ -1,55 +1,55 @@
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only srst_pulls_trst
-
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
-   set  _CHIPNAME at91sam7s
-}
-
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
-   set  _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   set _CPUTAPID 0x3f0f0f0f
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
-$_TARGETNAME configure -event reset-init { 
-        soft_reset_halt
-        # RSTC_CR : Reset peripherals
-        mww 0xfffffd00 0xa5000004
-        # disable watchdog
-	mww 0xfffffd44 0x00008000	
-	# enable user reset
-	mww 0xfffffd08 0xa5000001	
-	# CKGR_MOR : enable the main oscillator
-	mww 0xfffffc20 0x00000601	
-	sleep 10
-	# CKGR_PLLR: 96.1097 MHz
-	mww 0xfffffc2c 0x00481c0e 	
-	sleep 10
-	# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
-	mww 0xfffffc30 0x00000007	
-	sleep 10
-	# MC_FMR: flash mode (FWS=1,FMCN=73)
-	mww 0xffffff60 0x00490100	
-	sleep 100        
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
-
-#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
-flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME at91sam7s
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x3f0f0f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
+$_TARGETNAME configure -event reset-init { 
+        soft_reset_halt
+        # RSTC_CR : Reset peripherals
+        mww 0xfffffd00 0xa5000004
+        # disable watchdog
+	mww 0xfffffd44 0x00008000	
+	# enable user reset
+	mww 0xfffffd08 0xa5000001	
+	# CKGR_MOR : enable the main oscillator
+	mww 0xfffffc20 0x00000601	
+	sleep 10
+	# CKGR_PLLR: 96.1097 MHz
+	mww 0xfffffc2c 0x00481c0e 	
+	sleep 10
+	# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
+	mww 0xfffffc30 0x00000007	
+	sleep 10
+	# MC_FMR: flash mode (FWS=1,FMCN=73)
+	mww 0xffffff60 0x00490100	
+	sleep 100        
+}
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
+flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
+
+# For more information about the configuration files, take a look at:
+# openocd.texi


Property changes on: trunk/tcl/board/at91sam7sx.cfg
___________________________________________________________________
Name: svn:eol-style
   + native

Modified: trunk/tcl/board/at91sam9260.cfg
===================================================================
--- trunk/tcl/board/at91sam9260.cfg	2009-08-21 08:58:49 UTC (rev 2602)
+++ trunk/tcl/board/at91sam9260.cfg	2009-08-21 09:01:00 UTC (rev 2603)
@@ -1,44 +1,44 @@
-######################################
-# Target:    Atmel AT91SAM9260
-######################################
-
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
-   set  _CHIPNAME at91sam9260
-}
-
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
-   set  _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-  # force an error till we get a good number
-   set _CPUTAPID 0x0792603f
-}
-
-reset_config trst_and_srst separate trst_push_pull srst_open_drain
-
-#
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-jtag_nsrst_delay 300
-jtag_ntrst_delay 10
-
-jtag_rclk 3
-
-######################
-# Target configuration
-######################
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-
-# Internal sram1 memory
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
-
-
+######################################
+# Target:    Atmel AT91SAM9260
+######################################
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME at91sam9260
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0x0792603f
+}
+
+reset_config trst_and_srst separate trst_push_pull srst_open_drain
+
+#
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+jtag_nsrst_delay 300
+jtag_ntrst_delay 10
+
+jtag_rclk 3
+
+######################
+# Target configuration
+######################
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+
+# Internal sram1 memory
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
+
+


Property changes on: trunk/tcl/board/at91sam9260.cfg
___________________________________________________________________
Name: svn:eol-style
   + native

Modified: trunk/tcl/board/atmel_at91sam7s-ek.cfg
===================================================================
--- trunk/tcl/board/atmel_at91sam7s-ek.cfg	2009-08-21 08:58:49 UTC (rev 2602)
+++ trunk/tcl/board/atmel_at91sam7s-ek.cfg	2009-08-21 09:01:00 UTC (rev 2603)
@@ -1,8 +1,8 @@
-# Atmel AT91SAM7S-EK
-# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3784
-
-set CHIPNAME at91sam7s256
-
-source [find target/at91sam7sx.cfg]
-
-
+# Atmel AT91SAM7S-EK
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3784
+
+set CHIPNAME at91sam7s256
+
+source [find target/at91sam7sx.cfg]
+
+


Property changes on: trunk/tcl/board/atmel_at91sam7s-ek.cfg
___________________________________________________________________
Name: svn:eol-style
   + native

Modified: trunk/tcl/board/atmel_at91sam9260-ek.cfg
===================================================================
--- trunk/tcl/board/atmel_at91sam9260-ek.cfg	2009-08-21 08:58:49 UTC (rev 2602)
+++ trunk/tcl/board/atmel_at91sam9260-ek.cfg	2009-08-21 09:01:00 UTC (rev 2603)
@@ -1,81 +1,81 @@
-################################################################################
-# Atmel AT91SAM9260-EK eval board
-#
-# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
-#
-# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
-#                     OSCSEL configured for external 32.768 kHz crystal
-#
-# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
-#
-################################################################################
-
-# We add to the minimal configuration.
-source [find target/at91sam9260.cfg]
-
-# By default S1 is open and this means that NTRST is not connected.
-# The reset_config in target/at91sam9260.cfg is overridden here.
-# (or S1 must be populated with a 0 Ohm resistor)
-reset_config srst_only
-
-$_TARGETNAME configure -event reset-start {
-        # At reset CPU runs at 32.768 kHz.
-        # JTAG Frequency must be 6 times slower if RCLK is not supported.
-        jtag_rclk 5
-        halt
-        # RSTC_MR : enable user reset, MMU may be enabled... use physical address
-        arm926ejs mww_phys 0xfffffd08 0xa5000501
-}
-	
-$_TARGETNAME configure -event reset-init {
-        mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
-
-	mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
-        sleep 20                          # wait 20 ms
-        mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
-        sleep 10                          # wait 10 ms
-        mww 0xfffffc28 0x2060bf09         # CKGR_PLLAR: Set PLLA Register for 198.656 MHz
-        sleep 20                          # wait 20 ms
-        mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler (divide by 2)
-        sleep 10                          # wait 10 ms
-        mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
-        sleep 10                          # wait 10 ms
-
-	# Increase JTAG Speed to 6 MHz if RCLK is not supported
-        jtag_rclk 6000
-
-	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
-
-	mww 0xfffff870 0xffff0000         # PIO_ASR  : Select peripheral function for D15..D31
-        mww 0xfffff804 0xffff0000         # PIO_PDR  : Disable PIO function for D15..D31
-        
-        mww 0xffffef1c 0x00010002         # EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
-
-	mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
-
-	mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
-	mww 0x20000000 0
-	mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
-	mww 0x20000000 0
-	mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
-	mww 0x20000000 0
-	mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
-	mww 0x20000000 0
-	mww 0xffffea04 0x2b6              # SDRAMC_TR : Set refresh timer count to 7us
-}
+################################################################################
+# Atmel AT91SAM9260-EK eval board
+#
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
+#
+# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
+#                     OSCSEL configured for external 32.768 kHz crystal
+#
+# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
+#
+################################################################################
+
+# We add to the minimal configuration.
+source [find target/at91sam9260.cfg]
+
+# By default S1 is open and this means that NTRST is not connected.
+# The reset_config in target/at91sam9260.cfg is overridden here.
+# (or S1 must be populated with a 0 Ohm resistor)
+reset_config srst_only
+
+$_TARGETNAME configure -event reset-start {
+        # At reset CPU runs at 32.768 kHz.
+        # JTAG Frequency must be 6 times slower if RCLK is not supported.
+        jtag_rclk 5
+        halt
+        # RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        arm926ejs mww_phys 0xfffffd08 0xa5000501
+}
+	
+$_TARGETNAME configure -event reset-init {
+        mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
+        sleep 20                          # wait 20 ms
+        mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
+        sleep 10                          # wait 10 ms
+        mww 0xfffffc28 0x2060bf09         # CKGR_PLLAR: Set PLLA Register for 198.656 MHz
+        sleep 20                          # wait 20 ms
+        mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler (divide by 2)
+        sleep 10                          # wait 10 ms
+        mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
+        sleep 10                          # wait 10 ms
+
+	# Increase JTAG Speed to 6 MHz if RCLK is not supported
+        jtag_rclk 6000
+
+	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
+
+	mww 0xfffff870 0xffff0000         # PIO_ASR  : Select peripheral function for D15..D31
+        mww 0xfffff804 0xffff0000         # PIO_PDR  : Disable PIO function for D15..D31
+        
+        mww 0xffffef1c 0x00010002         # EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
+
+	mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x2b6              # SDRAMC_TR : Set refresh timer count to 7us
+}


Property changes on: trunk/tcl/board/atmel_at91sam9260-ek.cfg
___________________________________________________________________
Name: svn:eol-style
   + native

Modified: trunk/tcl/board/unknown_at91sam9260.cfg
===================================================================
--- trunk/tcl/board/unknown_at91sam9260.cfg	2009-08-21 08:58:49 UTC (rev 2602)
+++ trunk/tcl/board/unknown_at91sam9260.cfg	2009-08-21 09:01:00 UTC (rev 2603)
@@ -1,96 +1,96 @@
-# Thanks to Pieter Conradie for this script! 
-#
-# Unknown vendor board contains:
-#
-# Atmel AT91SAM9260 : PLLA = 192.512MHz, MCK = 96.256 MHz
-#                     OSCSEL configured for internal RC oscillator (22 to 42 kHz)
-#
-# 16-bit NOR FLASH : Intel JS28F128P30T85 128MBit
-# 32-bit SDRAM : 2 x Samsung K4S561632H-UC75, 4M x 16Bit x 4 Banks
-##################################################################
-
-# We add to the minimal configuration.
-source [find target/at91sam9260.cfg]
-
-$_TARGETNAME configure -event reset-start {
-        # At reset CPU runs at 22 to 42 kHz.
-        # JTAG Frequency must be 6 times slower.
-        jtag_rclk 3                        
-        halt
-	# RSTC_MR : enable user reset, MMU may be enabled... use physical address
-        arm926ejs mww_phys 0xfffffd08 0xa5000501
-}
-	
-
-$_TARGETNAME configure -event reset-init {
-        mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
-
-	mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
-        sleep 20                          # wait 20 ms
-        mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
-        sleep 10                          # wait 10 ms
-        mww 0xfffffc28 0x205dbf09         # CKGR_PLLAR: Set PLLA Register for 192.512MHz
-        sleep 20                          # wait 20 ms
-        mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler (divide by 2)
-        sleep 10                          # wait 10 ms
-        mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected (96.256 MHz)
-        sleep 10                          # wait 10 ms
-
-	# Increase JTAG Speed to 6 MHz if RCLK is not supported
-        jtag_rclk 6000                    
-
-	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
-
-	mww 0xffffec00 0x01020102         # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
-	mww 0xffffec04 0x09070806         # SMC_PULSE0
-	mww 0xffffec08 0x000d000b         # SMC_CYCLE0
-	mww 0xffffec0c 0x00001003         # SMC_MODE0
-
-	flash probe 0                     # Identify flash bank 0
-
-	mww 0xfffff870 0xffff0000         # PIO_ASR  : Select peripheral function for D15..D31
-        mww 0xfffff804 0xffff0000         # PIO_PDR  : Disable PIO function for D15..D31
-        mww 0xfffff860 0xffff0000         # PIO_PUDR : Disable D15..D31 pull-ups
-        
-        mww 0xffffef1c 0x00010102         # EBI_CSA  : Assign EBI Chip Select 1 to SDRAM
-                                          #            VDDIOMSEL set for +3V3 memory
-                                          #            Disable D0..D15 pull-ups
-
-	mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
-
-	mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
-	mww 0x20000000 0
-	mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
-	mww 0x20000000 0
-	mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x4
-	mww 0x20000000 0
-	mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
-	mww 0x20000000 0
-	mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
-	mww 0x20000000 0
-	mww 0xffffea04 0x2a2              # SDRAMC_TR : Set refresh timer count to 7us
-}
-
-
-#####################
-# Flash configuration
-#####################
-
-#flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x10000000 0x01000000 2 2 0
-
-
+# Thanks to Pieter Conradie for this script! 
+#
+# Unknown vendor board contains:
+#
+# Atmel AT91SAM9260 : PLLA = 192.512MHz, MCK = 96.256 MHz
+#                     OSCSEL configured for internal RC oscillator (22 to 42 kHz)
+#
+# 16-bit NOR FLASH : Intel JS28F128P30T85 128MBit
+# 32-bit SDRAM : 2 x Samsung K4S561632H-UC75, 4M x 16Bit x 4 Banks
+##################################################################
+
+# We add to the minimal configuration.
+source [find target/at91sam9260.cfg]
+
+$_TARGETNAME configure -event reset-start {
+        # At reset CPU runs at 22 to 42 kHz.
+        # JTAG Frequency must be 6 times slower.
+        jtag_rclk 3                        
+        halt
+	# RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        arm926ejs mww_phys 0xfffffd08 0xa5000501
+}
+	
+
+$_TARGETNAME configure -event reset-init {
+        mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
+        sleep 20                          # wait 20 ms
+        mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
+        sleep 10                          # wait 10 ms
+        mww 0xfffffc28 0x205dbf09         # CKGR_PLLAR: Set PLLA Register for 192.512MHz
+        sleep 20                          # wait 20 ms
+        mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler (divide by 2)
+        sleep 10                          # wait 10 ms
+        mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected (96.256 MHz)
+        sleep 10                          # wait 10 ms
+
+	# Increase JTAG Speed to 6 MHz if RCLK is not supported
+        jtag_rclk 6000                    
+
+	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
+
+	mww 0xffffec00 0x01020102         # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
+	mww 0xffffec04 0x09070806         # SMC_PULSE0
+	mww 0xffffec08 0x000d000b         # SMC_CYCLE0
+	mww 0xffffec0c 0x00001003         # SMC_MODE0
+
+	flash probe 0                     # Identify flash bank 0
+
+	mww 0xfffff870 0xffff0000         # PIO_ASR  : Select peripheral function for D15..D31
+        mww 0xfffff804 0xffff0000         # PIO_PDR  : Disable PIO function for D15..D31
+        mww 0xfffff860 0xffff0000         # PIO_PUDR : Disable D15..D31 pull-ups
+        
+        mww 0xffffef1c 0x00010102         # EBI_CSA  : Assign EBI Chip Select 1 to SDRAM
+                                          #            VDDIOMSEL set for +3V3 memory
+                                          #            Disable D0..D15 pull-ups
+
+	mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x2a2              # SDRAMC_TR : Set refresh timer count to 7us
+}
+
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank cfi <base> <size> <chip width> <bus width> <target#>
+flash bank cfi 0x10000000 0x01000000 2 2 0
+
+


Property changes on: trunk/tcl/board/unknown_at91sam9260.cfg
___________________________________________________________________
Name: svn:eol-style
   + native

[Openocd-svn] r2602 - trunk/tcl/board

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-21 10:58:49 +0200 (Fri, 21 Aug 2009)
New Revision: 2602

Added:
   trunk/tcl/board/at91sam7sx.cfg
   trunk/tcl/board/at91sam9260.cfg
   trunk/tcl/board/atmel_at91sam7s-ek.cfg
   trunk/tcl/board/atmel_at91sam9260-ek.cfg
   trunk/tcl/board/unknown_at91sam9260.cfg
Log:
Pieter Conradie <Pie...@ps...> Scripts for Atmel AT91SAM7S256 and AT91SAM9260

Added: trunk/tcl/board/at91sam7sx.cfg
===================================================================
--- trunk/tcl/board/at91sam7sx.cfg	2009-08-21 06:22:01 UTC (rev 2601)
+++ trunk/tcl/board/at91sam7sx.cfg	2009-08-21 08:58:49 UTC (rev 2602)
@@ -0,0 +1,55 @@
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME at91sam7s
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x3f0f0f0f
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
+$_TARGETNAME configure -event reset-init { 
+        soft_reset_halt
+        # RSTC_CR : Reset peripherals
+        mww 0xfffffd00 0xa5000004
+        # disable watchdog
+	mww 0xfffffd44 0x00008000	
+	# enable user reset
+	mww 0xfffffd08 0xa5000001	
+	# CKGR_MOR : enable the main oscillator
+	mww 0xfffffc20 0x00000601	
+	sleep 10
+	# CKGR_PLLR: 96.1097 MHz
+	mww 0xfffffc2c 0x00481c0e 	
+	sleep 10
+	# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
+	mww 0xfffffc30 0x00000007	
+	sleep 10
+	# MC_FMR: flash mode (FWS=1,FMCN=73)
+	mww 0xffffff60 0x00490100	
+	sleep 100        
+}
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
+
+#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
+flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
+
+# For more information about the configuration files, take a look at:
+# openocd.texi

Added: trunk/tcl/board/at91sam9260.cfg
===================================================================
--- trunk/tcl/board/at91sam9260.cfg	2009-08-21 06:22:01 UTC (rev 2601)
+++ trunk/tcl/board/at91sam9260.cfg	2009-08-21 08:58:49 UTC (rev 2602)
@@ -0,0 +1,44 @@
+######################################
+# Target:    Atmel AT91SAM9260
+######################################
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME at91sam9260
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0x0792603f
+}
+
+reset_config trst_and_srst separate trst_push_pull srst_open_drain
+
+#
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+jtag_nsrst_delay 300
+jtag_ntrst_delay 10
+
+jtag_rclk 3
+
+######################
+# Target configuration
+######################
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+
+# Internal sram1 memory
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x1000 -work-area-backup 1
+
+

Added: trunk/tcl/board/atmel_at91sam7s-ek.cfg
===================================================================
--- trunk/tcl/board/atmel_at91sam7s-ek.cfg	2009-08-21 06:22:01 UTC (rev 2601)
+++ trunk/tcl/board/atmel_at91sam7s-ek.cfg	2009-08-21 08:58:49 UTC (rev 2602)
@@ -0,0 +1,8 @@
+# Atmel AT91SAM7S-EK
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3784
+
+set CHIPNAME at91sam7s256
+
+source [find target/at91sam7sx.cfg]
+
+

Added: trunk/tcl/board/atmel_at91sam9260-ek.cfg
===================================================================
--- trunk/tcl/board/atmel_at91sam9260-ek.cfg	2009-08-21 06:22:01 UTC (rev 2601)
+++ trunk/tcl/board/atmel_at91sam9260-ek.cfg	2009-08-21 08:58:49 UTC (rev 2602)
@@ -0,0 +1,81 @@
+################################################################################
+# Atmel AT91SAM9260-EK eval board
+#
+# http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
+#
+# Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
+#                     OSCSEL configured for external 32.768 kHz crystal
+#
+# 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
+#
+################################################################################
+
+# We add to the minimal configuration.
+source [find target/at91sam9260.cfg]
+
+# By default S1 is open and this means that NTRST is not connected.
+# The reset_config in target/at91sam9260.cfg is overridden here.
+# (or S1 must be populated with a 0 Ohm resistor)
+reset_config srst_only
+
+$_TARGETNAME configure -event reset-start {
+        # At reset CPU runs at 32.768 kHz.
+        # JTAG Frequency must be 6 times slower if RCLK is not supported.
+        jtag_rclk 5
+        halt
+        # RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        arm926ejs mww_phys 0xfffffd08 0xa5000501
+}
+	
+$_TARGETNAME configure -event reset-init {
+        mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
+        sleep 20                          # wait 20 ms
+        mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
+        sleep 10                          # wait 10 ms
+        mww 0xfffffc28 0x2060bf09         # CKGR_PLLAR: Set PLLA Register for 198.656 MHz
+        sleep 20                          # wait 20 ms
+        mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler (divide by 2)
+        sleep 10                          # wait 10 ms
+        mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
+        sleep 10                          # wait 10 ms
+
+	# Increase JTAG Speed to 6 MHz if RCLK is not supported
+        jtag_rclk 6000
+
+	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
+
+	mww 0xfffff870 0xffff0000         # PIO_ASR  : Select peripheral function for D15..D31
+        mww 0xfffff804 0xffff0000         # PIO_PDR  : Disable PIO function for D15..D31
+        
+        mww 0xffffef1c 0x00010002         # EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
+
+	mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x2b6              # SDRAMC_TR : Set refresh timer count to 7us
+}

Added: trunk/tcl/board/unknown_at91sam9260.cfg
===================================================================
--- trunk/tcl/board/unknown_at91sam9260.cfg	2009-08-21 06:22:01 UTC (rev 2601)
+++ trunk/tcl/board/unknown_at91sam9260.cfg	2009-08-21 08:58:49 UTC (rev 2602)
@@ -0,0 +1,96 @@
+# Thanks to Pieter Conradie for this script! 
+#
+# Unknown vendor board contains:
+#
+# Atmel AT91SAM9260 : PLLA = 192.512MHz, MCK = 96.256 MHz
+#                     OSCSEL configured for internal RC oscillator (22 to 42 kHz)
+#
+# 16-bit NOR FLASH : Intel JS28F128P30T85 128MBit
+# 32-bit SDRAM : 2 x Samsung K4S561632H-UC75, 4M x 16Bit x 4 Banks
+##################################################################
+
+# We add to the minimal configuration.
+source [find target/at91sam9260.cfg]
+
+$_TARGETNAME configure -event reset-start {
+        # At reset CPU runs at 22 to 42 kHz.
+        # JTAG Frequency must be 6 times slower.
+        jtag_rclk 3                        
+        halt
+	# RSTC_MR : enable user reset, MMU may be enabled... use physical address
+        arm926ejs mww_phys 0xfffffd08 0xa5000501
+}
+	
+
+$_TARGETNAME configure -event reset-init {
+        mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
+
+	mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator
+        sleep 20                          # wait 20 ms
+        mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
+        sleep 10                          # wait 10 ms
+        mww 0xfffffc28 0x205dbf09         # CKGR_PLLAR: Set PLLA Register for 192.512MHz
+        sleep 20                          # wait 20 ms
+        mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler (divide by 2)
+        sleep 10                          # wait 10 ms
+        mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected (96.256 MHz)
+        sleep 10                          # wait 10 ms
+
+	# Increase JTAG Speed to 6 MHz if RCLK is not supported
+        jtag_rclk 6000                    
+
+	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
+
+	mww 0xffffec00 0x01020102         # SMC_SETUP0 : Setup SMC for Intel NOR Flash JS28F128P30T85 128MBit
+	mww 0xffffec04 0x09070806         # SMC_PULSE0
+	mww 0xffffec08 0x000d000b         # SMC_CYCLE0
+	mww 0xffffec0c 0x00001003         # SMC_MODE0
+
+	flash probe 0                     # Identify flash bank 0
+
+	mww 0xfffff870 0xffff0000         # PIO_ASR  : Select peripheral function for D15..D31
+        mww 0xfffff804 0xffff0000         # PIO_PDR  : Disable PIO function for D15..D31
+        mww 0xfffff860 0xffff0000         # PIO_PUDR : Disable D15..D31 pull-ups
+        
+        mww 0xffffef1c 0x00010102         # EBI_CSA  : Assign EBI Chip Select 1 to SDRAM
+                                          #            VDDIOMSEL set for +3V3 memory
+                                          #            Disable D0..D15 pull-ups
+
+	mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Samsung K4S561632H-UC75 : 4M x 16Bit x 4 Banks)
+
+	mww 0xffffea00 0x1                # SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2                # SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4                # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0xffffea00 0x3                # SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0                # SDRAMC_MR : normal mode
+	mww 0x20000000 0
+	mww 0xffffea04 0x2a2              # SDRAMC_TR : Set refresh timer count to 7us
+}
+
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank cfi <base> <size> <chip width> <bus width> <target#>
+flash bank cfi 0x10000000 0x01000000 2 2 0
+
+

[Openocd-svn] r2601 - trunk/src/server

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-21 08:22:01 +0200 (Fri, 21 Aug 2009)
New Revision: 2601

Modified:
   trunk/src/server/httpd.c
Log:
Florian Boor <flo...@ke...> fixes a segfault executing commands from the web interface using the
"Run Command" tab.


Modified: trunk/src/server/httpd.c
===================================================================
--- trunk/src/server/httpd.c	2009-08-20 08:55:34 UTC (rev 2600)
+++ trunk/src/server/httpd.c	2009-08-21 06:22:01 UTC (rev 2601)
@@ -223,7 +223,7 @@
 /* append data to each key */
 static int iterate_post(void *con_cls, enum MHD_ValueKind kind,
 		const char *key, const char *filename, const char *content_type,
-		const char *transfer_encoding, const char *data, uint64_t off,
+		const char *transfer_encoding, const char *data, size_t off,
 		size_t size)
 {
 	struct httpd_request *r = (struct httpd_request*) con_cls;

[Openocd-svn] r2600 - trunk/src/svf

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-20 10:55:34 +0200 (Thu, 20 Aug 2009)
New Revision: 2600

Modified:
   trunk/src/svf/svf.c
Log:
Piotr Ziecik <ko...@se...> This patch adds handling blank characters between hex digits in
SVF file, making OpenOCD compatible with files generated by
Altera Quatrus II 9.0.

Modified: trunk/src/svf/svf.c
===================================================================
--- trunk/src/svf/svf.c	2009-08-20 07:54:49 UTC (rev 2599)
+++ trunk/src/svf/svf.c	2009-08-20 08:55:34 UTC (rev 2600)
@@ -655,8 +655,8 @@
 
 static int svf_copy_hexstring_to_binary(char *str, uint8_t **bin, int orig_bit_len, int bit_len)
 {
-	int i, str_len = strlen(str), str_byte_len = (bit_len + 3) >> 2, loop_cnt;
-	uint8_t ch, need_write = 1;
+	int i, str_len = strlen(str), str_hbyte_len = (bit_len + 3) >> 2;
+	uint8_t ch;
 
 	if (ERROR_OK != svf_adjust_array_length(bin, orig_bit_len, bit_len))
 	{
@@ -664,75 +664,54 @@
 		return ERROR_FAIL;
 	}
 
-	if (str_byte_len > str_len)
+	for (i = 0; i < str_hbyte_len; i++)
 	{
-		loop_cnt = str_byte_len;
-	}
-	else
-	{
-		loop_cnt = str_len;
-	}
-
-	for (i = 0; i < loop_cnt; i++)
-	{
-		if (i < str_len)
+		ch = 0;
+		while (str_len > 0)
 		{
-			ch = str[str_len - i - 1];
-			if ((ch >= '0') && (ch <= '9'))
+			ch = str[--str_len];
+
+			if (!isblank(ch))
 			{
-				ch = ch - '0';
+				if ((ch >= '0') && (ch <= '9'))
+				{
+					ch = ch - '0';
+					break;
+				}
+				else if ((ch >= 'A') && (ch <= 'F'))
+				{
+					ch = ch - 'A' + 10;
+					break;
+				}
+				else
+				{
+					LOG_ERROR("invalid hex string");
+					return ERROR_FAIL;
+				}
 			}
-			else if ((ch >= 'A') && (ch <= 'F'))
-			{
-				ch = ch - 'A' + 10;
-			}
-			else
-			{
-				LOG_ERROR("invalid hex string");
-				return ERROR_FAIL;
-			}
-		}
-		else
-		{
+
 			ch = 0;
 		}
 
-		// check valid
-		if (i >= str_byte_len)
+		// write bin
+		if (i % 2)
 		{
-			// all data written, other data should be all '0's and needn't to be written
-			need_write = 0;
-			if (ch != 0)
-			{
-				LOG_ERROR("value execede length");
-				return ERROR_FAIL;
-			}
+			// MSB
+			(*bin)[i / 2] |= ch << 4;
 		}
-		else if (i == (str_byte_len - 1))
+		else
 		{
-			// last data byte, written if valid
-			if ((ch & ~((1 << (bit_len - 4 * i)) - 1)) != 0)
-			{
-				LOG_ERROR("value execede length");
-				return ERROR_FAIL;
-			}
+			// LSB
+			(*bin)[i / 2] = 0;
+			(*bin)[i / 2] |= ch;
 		}
+	}
 
-		if (need_write)
-		{
-			// write bin
-			if (i % 2)
-			{
-				// MSB
-				(*bin)[i / 2] |= ch << 4;
-			}
-			else
-			{
-				// LSB
-				(*bin)[i / 2] = 0;
-				(*bin)[i / 2] |= ch;
-			}
-		}
+	// check valid
+	if (str_len > 0 || (ch & ~((1 << (4 - (bit_len % 4))) - 1)) != 0)
+	{
+		LOG_ERROR("value execede length");
+		return ERROR_FAIL;
 	}
 
 	return ERROR_OK;

[Openocd-svn] r2599 - in trunk: . src/jtag

[ntfreak at B. <nt...@ma...>]

Author: ntfreak
Date: 2009-08-20 09:54:49 +0200 (Thu, 20 Aug 2009)
New Revision: 2599

Modified:
   trunk/README
   trunk/configure.in
   trunk/src/jtag/ft2232.c
Log:
- remove enable-ft2232-highspeed configure option, high speed ftdi support is now detected during the configure stage
- warning now issued if high speed ftdi device found and openocd was built using an old driver

Modified: trunk/README
===================================================================
--- trunk/README	2009-08-20 07:15:46 UTC (rev 2598)
+++ trunk/README	2009-08-20 07:54:49 UTC (rev 2599)
@@ -215,10 +215,6 @@
                           FTD2XX
   --enable-ft2232_ftd2xx  Enable building support for FT2232 based devices
                           using the FTD2XX driver from ftdichip.com
-  --enable-ft2232-highspeed
-                          Enable building support for FT2232H and
-                          FT4232H-based devices (requires >=libftd2xx-0.4.16
-                          or >=libftdi-0.16)
 
   --enable-gw16012        Enable building support for the Gateworks GW16012
                           JTAG Programmer

Modified: trunk/configure.in
===================================================================
--- trunk/configure.in	2009-08-20 07:15:46 UTC (rev 2598)
+++ trunk/configure.in	2009-08-20 07:54:49 UTC (rev 2599)
@@ -323,10 +323,6 @@
   AS_HELP_STRING([--enable-ft2232_ftd2xx], [Enable building support for FT2232 based devices using the FTD2XX driver from ftdichip.com]),
   [build_ft2232_ftd2xx=$enableval], [build_ft2232_ftd2xx=no])
 
-AC_ARG_ENABLE(ft2232_highspeed,
-  AS_HELP_STRING([--enable-ft2232-highspeed], [Enable building support for FT2232H and FT4232H-based devices (requires >=libftd2xx-0.4.16 or >=libftdi-0.16)]),
-  [want_ft2232_highspeed=$enableval], [want_ft2232_highspeed=no])
-
 AC_ARG_ENABLE(amtjtagaccel,
   AS_HELP_STRING([--enable-amtjtagaccel], [Enable building the Amontec JTAG-Accelerator driver]),
   [build_amtjtagaccel=$enableval], [build_amtjtagaccel=no])
@@ -834,11 +830,8 @@
     AC_MSG_RESULT([Skipping as we are cross-compiling])
   ])
 
-AC_MSG_CHECKING([whether to build ftd2xx highspeed device support])
-AC_MSG_RESULT([$want_ft2232_highspeed])
-if test $want_ft2232_highspeed != no; then
-  AC_MSG_CHECKING([for ftd2xx highspeed device support])
-  AC_COMPILE_IFELSE([
+AC_MSG_CHECKING([for ftd2xx highspeed device support])
+AC_COMPILE_IFELSE([
 #include "confdefs.h"
 #if IS_WIN32
 #include "windows.h"
@@ -855,10 +848,9 @@
     ])
   AC_MSG_RESULT([$build_ft2232_highspeed])
 
-  if test $want_ft2232_highspeed = yes -a $build_ft2232_highspeed = no; then
-    AC_MSG_ERROR([You need a newer FTD2XX driver (version 0.4.16 or later).])
+  if test $build_ft2232_highspeed = no; then
+    AC_MSG_WARN([You need a newer FTD2XX driver (version 2.04.16 or later).])
   fi
-fi
 
 LDFLAGS=$LDFLAGS_SAVE
 CFLAGS=$CFLAGS_SAVE
@@ -903,11 +895,8 @@
       AC_MSG_RESULT([Skipping as we are cross-compiling])
     ])
 
-  AC_MSG_CHECKING([whether to build libftdi highspeed device support])
-  AC_MSG_RESULT([$want_ft2232_highspeed])
-  if test $want_ft2232_highspeed != no; then
-    AC_MSG_CHECKING([for libftdi highspeed device support])
-    AC_COMPILE_IFELSE([
+AC_MSG_CHECKING([for libftdi highspeed device support])
+AC_COMPILE_IFELSE([
 #include <stdio.h>
 #include <ftdi.h>
 enum ftdi_chip_type x = TYPE_2232H;
@@ -920,10 +909,9 @@
     ])
     AC_MSG_RESULT([$build_ft2232_highspeed])
 
-    if test $want_ft2232_highspeed = yes -a $build_ft2232_highspeed = no; then
-      AC_MSG_ERROR([You need a newer libftdi version (0.16 or later).])
+    if test $build_ft2232_highspeed = no; then
+      AC_MSG_WARN([You need a newer libftdi version (0.16 or later).])
     fi
-  fi
 
   # Restore the 'unexpanded ldflags'
   LDFLAGS=$LDFLAGS_SAVE

Modified: trunk/src/jtag/ft2232.c
===================================================================
--- trunk/src/jtag/ft2232.c	2009-08-20 07:15:46 UTC (rev 2598)
+++ trunk/src/jtag/ft2232.c	2009-08-20 07:54:49 UTC (rev 2599)
@@ -68,8 +68,15 @@
 /* this speed value tells that RTCK is requested */
 #define RTCK_SPEED -1
 
+#ifndef BUILD_FT2232_HIGHSPEED
+ #if BUILD_FT2232_FTD2XX == 1
+	enum { FT_DEVICE_2232H = 6, FT_DEVICE_4232H };
+ #elif BUILD_FT2232_LIBFTDI == 1
+	enum { TYPE_2232H = 4, TYPE_4232H = 5 };
+ #endif
+#endif
+
 static int ft2232_execute_queue(void);
-
 static int ft2232_speed(int speed);
 static int ft2232_speed_div(int speed, int* khz);
 static int ft2232_khz(int khz, int* jtag_speed);
@@ -416,14 +423,10 @@
 
 static bool ft2232_device_is_highspeed(void)
 {
-#ifdef BUILD_FT2232_HIGHSPEED
-	#if BUILD_FT2232_FTD2XX == 1
+#if BUILD_FT2232_FTD2XX == 1
 	return (ftdi_device == FT_DEVICE_2232H) || (ftdi_device == FT_DEVICE_4232H);
-	#elif BUILD_FT2232_LIBFTDI == 1
+#elif BUILD_FT2232_LIBFTDI == 1
 	return (ftdi_device == TYPE_2232H || ftdi_device == TYPE_4232H);
-	#endif
-#else
-	return false;
 #endif
 }
 
@@ -529,10 +532,6 @@
 		else
 		{
 			LOG_DEBUG("RCLK not supported");
-#ifndef BUILD_FT2232_HIGHSPEED
-			LOG_DEBUG("If you have a high-speed FTDI device, then "
-				"OpenOCD may be built with --enable-ft2232-highspeed.");
-#endif
 			return ERROR_FAIL;
 		}
 	}
@@ -1941,7 +1940,7 @@
 			{"BM", "AM", "100AX", "UNKNOWN", "2232C", "232R", "2232H", "4232H"};
 		unsigned no_of_known_types = sizeof(type_str) / sizeof(type_str[0]) - 1;
 		unsigned type_index = ((unsigned)ftdi_device <= no_of_known_types)
-			? ftdi_device : 3;
+			? ftdi_device : FT_DEVICE_UNKNOWN;
 		LOG_INFO("device: %lu \"%s\"", ftdi_device, type_str[type_index]);
 		LOG_INFO("deviceID: %lu", deviceID);
 		LOG_INFO("SerialNumber: %s", SerialNumber);
@@ -2118,6 +2117,14 @@
 
 	if (ft2232_device_is_highspeed())
 	{
+#ifndef BUILD_FT2232_HIGHSPEED
+ #if BUILD_FT2232_FTD2XX == 1
+		LOG_WARNING("High Speed device found - You need a newer FTD2XX driver (version 2.04.16 or later)");
+ #elif BUILD_FT2232_LIBFTDI == 1
+		LOG_WARNING("High Speed device found - You need a newer libftdi version (0.16 or later)");
+ #endif
+#endif
+		/* make sure the legacy mode is disabled */
 		if (ft2232h_ft4232h_clk_divide_by_5(false) != ERROR_OK)
 			return ERROR_JTAG_INIT_FAILED;
 	}

[Openocd-svn] r2598 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-20 09:15:46 +0200 (Thu, 20 Aug 2009)
New Revision: 2598

Modified:
   trunk/src/target/arm_disassembler.c
Log:
David Brownell <da...@pa...>More Thumb2 disassembly:

  ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch

GCC will generate the table branch instructions, usually with inlined
tables that will confuse this disassembler.  LDREX and STREX are not
issued by GCC without inline assembly.

This means all Thumb2 instructions implemented by Cortex-M3 can now
be disassembled.  Cortex-A8 cores support more Thumb2 instructions,
but most of those aren't yet publicly documented.


Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c	2009-08-19 08:39:06 UTC (rev 2597)
+++ trunk/src/target/arm_disassembler.c	2009-08-20 07:15:46 UTC (rev 2598)
@@ -3007,6 +3007,133 @@
 	return ERROR_OK;
 }
 
+/* load/store dual or exclusive, table branch */
+static int t2ev_ldrex_strex(uint32_t opcode, uint32_t address,
+		arm_instruction_t *instruction, char *cp)
+{
+	unsigned op1op2 = (opcode >> 20) & 0x3;
+	unsigned op3 = (opcode >> 4) & 0xf;
+	char *mnemonic;
+	unsigned rn = (opcode >> 16) & 0xf;
+	unsigned rt = (opcode >> 12) & 0xf;
+	unsigned rd = (opcode >> 8) & 0xf;
+	unsigned imm = opcode & 0xff;
+	char *p1 = "";
+	char *p2 = "]";
+
+	op1op2 |= (opcode >> 21) & 0xc;
+	switch (op1op2) {
+	case 0:
+		mnemonic = "STREX";
+		goto strex;
+	case 1:
+		mnemonic = "LDREX";
+		goto ldrex;
+	case 2:
+	case 6:
+	case 8:
+	case 10:
+	case 12:
+	case 14:
+		mnemonic = "STRD";
+		goto immediate;
+	case 3:
+	case 7:
+	case 9:
+	case 11:
+	case 13:
+	case 15:
+		mnemonic = "LDRD";
+		if (rn == 15)
+			goto literal;
+		else
+			goto immediate;
+	case 4:
+		switch (op3) {
+		case 4:
+			mnemonic = "STREXB";
+			break;
+		case 5:
+			mnemonic = "STREXH";
+			break;
+		default:
+			return ERROR_INVALID_ARGUMENTS;
+		}
+		rd = opcode & 0xf;
+		imm = 0;
+		goto strex;
+	case 5:
+		switch (op3) {
+		case 0:
+			sprintf(cp, "TBB\t[r%u, r%u]", rn, imm & 0xf);
+			return ERROR_OK;
+		case 1:
+			sprintf(cp, "TBH\t[r%u, r%u, LSL #1]", rn, imm & 0xf);
+			return ERROR_OK;
+		case 4:
+			mnemonic = "LDREXB";
+			break;
+		case 5:
+			mnemonic = "LDREXH";
+			break;
+		default:
+			return ERROR_INVALID_ARGUMENTS;
+		}
+		imm = 0;
+		goto ldrex;
+	}
+	return ERROR_INVALID_ARGUMENTS;
+
+strex:
+	imm <<= 2;
+	if (imm)
+		sprintf(cp, "%s\tr%u, r%u, [r%u, #%u]\t; %#2.2x",
+				mnemonic, rd, rt, rn, imm, imm);
+	else
+		sprintf(cp, "%s\tr%u, r%u, [r%u]",
+				mnemonic, rd, rt, rn);
+	return ERROR_OK;
+
+ldrex:
+	imm <<= 2;
+	if (imm)
+		sprintf(cp, "%s\tr%u, [r%u, #%u]\t; %#2.2x",
+				mnemonic, rt, rn, imm, imm);
+	else
+		sprintf(cp, "%s\tr%u, [r%u]",
+				mnemonic, rt, rn);
+	return ERROR_OK;
+
+immediate:
+	/* two indexed modes will write back rn */
+	if (opcode & (1 << 21)) {
+		if (opcode & (1 << 24))	/* pre-indexed */
+			p2 = "]!";
+		else {			/* post-indexed */
+			p1 = "]";
+			p2 = "";
+		}
+	}
+
+	imm <<= 2;
+	sprintf(cp, "%s\tr%u, r%u, [r%u%s, #%s%u%s\t; %#2.2x",
+			mnemonic, rt, rd, rn, p1,
+			(opcode & (1 << 23)) ? "" : "-",
+			imm, p2, imm);
+	return ERROR_OK;
+
+literal:
+	address = thumb_alignpc4(address);
+	imm <<= 2;
+	if (opcode & (1 << 23))
+		address += imm;
+	else
+		address -= imm;
+	sprintf(cp, "%s\tr%u, r%u, %#8.8" PRIx32,
+			mnemonic, rt, rd, address);
+	return ERROR_OK;
+}
+
 static int t2ev_data_shift(uint32_t opcode, uint32_t address,
 		arm_instruction_t *instruction, char *cp)
 {
@@ -3677,6 +3804,10 @@
 	else if ((opcode & 0x1e400000) == 0x08000000)
 		retval = t2ev_ldm_stm(opcode, address, instruction, cp);
 
+	/* ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch */
+	else if ((opcode & 0x1e400000) == 0x08400000)
+		retval = t2ev_ldrex_strex(opcode, address, instruction, cp);
+
 	/* ARMv7-M: A5.3.7 Load word */
 	else if ((opcode & 0x1f700000) == 0x18500000)
 		retval = t2ev_load_word(opcode, address, instruction, cp);
@@ -3711,11 +3842,14 @@
 	else if ((opcode & 0x1f800000) == 0x1b800000)
 		retval = t2ev_mul64_div(opcode, address, instruction, cp);
 
-	/* FIXME decode more 32-bit instructions */
-
 	if (retval == ERROR_OK)
 		return retval;
 
+	/*
+	 * Thumb2 also supports coprocessor, ThumbEE, and DSP/Media (SIMD)
+	 * instructions; not yet handled here.
+	 */
+
 	if (retval == ERROR_INVALID_ARGUMENTS) {
 		instruction->type = ARM_UNDEFINED_INSTRUCTION;
 		strcpy(cp, "UNDEFINED OPCODE");

[Openocd-svn] r2597 - trunk/src/jtag

[ntfreak at B. <nt...@ma...>]

Author: ntfreak
Date: 2009-08-19 10:39:06 +0200 (Wed, 19 Aug 2009)
New Revision: 2597

Modified:
   trunk/src/jtag/ft2232.c
Log:
Jonas Horberg [jho...@sa...]:
Fix small typo in ftd2xx type detection

Modified: trunk/src/jtag/ft2232.c
===================================================================
--- trunk/src/jtag/ft2232.c	2009-08-19 06:31:44 UTC (rev 2596)
+++ trunk/src/jtag/ft2232.c	2009-08-19 08:39:06 UTC (rev 2597)
@@ -1940,7 +1940,7 @@
 		static const char* type_str[] =
 			{"BM", "AM", "100AX", "UNKNOWN", "2232C", "232R", "2232H", "4232H"};
 		unsigned no_of_known_types = sizeof(type_str) / sizeof(type_str[0]) - 1;
-		unsigned type_index = ((unsigned)ftdi_device < no_of_known_types)
+		unsigned type_index = ((unsigned)ftdi_device <= no_of_known_types)
 			? ftdi_device : 3;
 		LOG_INFO("device: %lu \"%s\"", ftdi_device, type_str[type_index]);
 		LOG_INFO("deviceID: %lu", deviceID);

[Openocd-svn] r2596 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-19 08:31:44 +0200 (Wed, 19 Aug 2009)
New Revision: 2596

Modified:
   trunk/src/target/target.c
Log:
David Brownell <da...@pa...>Fix some command helptext:

 - spell "address" right
 - list bp/wp params as optional

And make those source lines wrap at sane margins.

Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c	2009-08-19 06:30:08 UTC (rev 2595)
+++ trunk/src/target/target.c	2009-08-19 06:31:44 UTC (rev 2596)
@@ -1505,10 +1505,19 @@
 	register_command(cmd_ctx,  NULL, "mwh", handle_mw_command, COMMAND_EXEC, "write memory half-word <addr> <value> [count]");
 	register_command(cmd_ctx,  NULL, "mwb", handle_mw_command, COMMAND_EXEC, "write memory byte <addr> <value> [count]");
 
-	register_command(cmd_ctx,  NULL, "bp", handle_bp_command, COMMAND_EXEC, "set breakpoint <address> <length> [hw]");
-	register_command(cmd_ctx,  NULL, "rbp", handle_rbp_command, COMMAND_EXEC, "remove breakpoint <adress>");
-	register_command(cmd_ctx,  NULL, "wp", handle_wp_command, COMMAND_EXEC, "set watchpoint <address> <length> <r/w/a> [value] [mask]");
-	register_command(cmd_ctx,  NULL, "rwp", handle_rwp_command, COMMAND_EXEC, "remove watchpoint <adress>");
+	register_command(cmd_ctx,  NULL, "bp",
+			handle_bp_command, COMMAND_EXEC,
+			"list or set breakpoint [<address> <length> [hw]]");
+	register_command(cmd_ctx,  NULL, "rbp",
+			handle_rbp_command, COMMAND_EXEC,
+			"remove breakpoint <address>");
+	register_command(cmd_ctx,  NULL, "wp",
+			handle_wp_command, COMMAND_EXEC,
+			"list or set watchpoint "
+				"[<address> <length> <r/w/a> [value] [mask]]");
+	register_command(cmd_ctx,  NULL, "rwp",
+			handle_rwp_command, COMMAND_EXEC,
+			"remove watchpoint <address>");
 
 	register_command(cmd_ctx,  NULL, "load_image", handle_load_image_command, COMMAND_EXEC, "load_image <file> <address> ['bin'|'ihex'|'elf'|'s19'] [min_address] [max_length]");
 	register_command(cmd_ctx,  NULL, "dump_image", handle_dump_image_command, COMMAND_EXEC, "dump_image <file> <address> <size>");

[Openocd-svn] r2595 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-19 08:30:08 +0200 (Wed, 19 Aug 2009)
New Revision: 2595

Modified:
   trunk/src/target/cortex_m3.c
Log:
David Brownell <da...@pa...> Clean up some Cortex-M3 reset handling.

 - AIRCR_SYSRESETREQ is generic; use it on any system where
  SRST won't fly, not just on Stellaris-based ones.

 - Reformat and improve comments about the Stellaris quirk; and
  xref the only public docs (an email) about the issue.

It seems that *most* Stellaris chips have this problem.  Tempest
parts aren't yet in general sampling; and if rev B silicon for
earlier chips exists, it's not very visible yet.

Modified: trunk/src/target/cortex_m3.c
===================================================================
--- trunk/src/target/cortex_m3.c	2009-08-18 19:55:01 UTC (rev 2594)
+++ trunk/src/target/cortex_m3.c	2009-08-19 06:30:08 UTC (rev 2595)
@@ -760,11 +760,14 @@
 		target_state_name(target));
 
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
+
+	/*
+	 * We can reset Cortex-M3 targets using just the NVIC without
+	 * requiring SRST, getting a SoC reset (or a core-only reset)
+	 * instead of a system reset.
+	 */
 	if (!(jtag_reset_config & RESET_HAS_SRST))
-	{
-		LOG_ERROR("Can't assert SRST");
-		return ERROR_FAIL;
-	}
+		assert_srst = 0;
 
 	/* Enable debug requests */
 	mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
@@ -794,15 +797,21 @@
 		mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 	}
 
-	/* following hack is to handle luminary reset
-	 * when srst is asserted the luminary device seesm to also clear the debug registers
-	 * which does not match the armv7 debug TRM */
-
+	/*
+	 * When nRST is asserted on most Stellaris devices, it clears some of
+	 * the debug state.  The ARMv7M and Cortex-M3 TRMs say that's wrong;
+	 * and OpenOCD depends on those TRMs.  So we won't use SRST on those
+	 * chips.  (Only power-on reset should affect debug state, beyond a
+	 * few specified bits; not the chip's nRST input, wired to SRST.)
+	 *
+	 * REVISIT current errata specs don't seem to cover this issue.
+	 * Do we have more details than this email?
+	 *   https://lists.berlios.de/pipermail
+	 *	/openocd-development/2008-August/003065.html
+	 */
 	if (strcmp(target->variant, "lm3s") == 0)
 	{
-		/* get revision of lm3s target, only early silicon has this issue
-		 * Fury Rev B, DustDevil Rev B, Tempest all ok */
-
+		/* Check for silicon revisions with the issue. */
 		uint32_t did0;
 
 		if (target_read_u32(target, 0x400fe000, &did0) == ERROR_OK)
@@ -816,10 +825,16 @@
 
 				case 1:
 				case 3:
-					/* only Fury/DustDevil rev A suffer reset problems */
+					/* Fury and DustDevil rev A have
+					 * this nRST problem.  It should
+					 * be fixed in rev B silicon.
+					 */
 					if (((did0 >> 8) & 0xff) == 0)
 						assert_srst = 0;
 					break;
+				case 4:
+					/* Tempest should be fine. */
+					break;
 			}
 		}
 	}
@@ -838,13 +853,20 @@
 	}
 	else
 	{
-		/* this causes the luminary device to reset using the watchdog */
-		mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
-		LOG_DEBUG("Using Luminary Reset: SYSRESETREQ");
+		/* Use a standard Cortex-M3 software reset mechanism.
+		 * SYSRESETREQ will reset SoC peripherals outside the
+		 * core, like watchdog timers, if the SoC wires it up
+		 * correctly.  Else VECRESET can reset just the core.
+		 */
+		mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
+				AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
+		LOG_DEBUG("Using Cortex-M3 SYSRESETREQ");
 
 		{
-			/* I do not know why this is necessary, but it fixes strange effects
-			 * (step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */
+			/* I do not know why this is necessary, but it
+			 * fixes strange effects (step/resume cause NMI
+			 * after reset) on LM3S6918 -- Michael Schwingen
+			 */
 			uint32_t tmp;
 			mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
 		}

[Openocd-svn] r2594 - trunk/src/target

[ntfreak at B. <nt...@ma...>]

Author: ntfreak
Date: 2009-08-18 21:55:01 +0200 (Tue, 18 Aug 2009)
New Revision: 2594

Modified:
   trunk/src/target/target.c
Log:
David Brownell [da...@pa...]:

Simplify dumping of register lists by only printing cached values
if they are marked as valid.  Most of the time, they are invalid;
so printing *any* value is just misleading.

Note that for ARM7 and ARM9 most EmbeddedICE registers (except for
debug status) could be cached most of the time; and their register
cache isn't maintained properly (many accesses seem to bypass that
cache code).

Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c	2009-08-18 17:57:19 UTC (rev 2593)
+++ trunk/src/target/target.c	2009-08-18 19:55:01 UTC (rev 2594)
@@ -1741,17 +1741,28 @@
 		while (cache)
 		{
 			int i;
-			for (i = 0; i < cache->num_regs; i++)
+
+			for (i = 0, reg = cache->reg_list;
+					i < cache->num_regs;
+					i++, reg++, count++)
 			{
-				value = buf_to_str(cache->reg_list[i].value, cache->reg_list[i].size, 16);
-				command_print(cmd_ctx, "(%i) %s (/%i): 0x%s (dirty: %i, valid: %i)",
-							  count++,
-							  cache->reg_list[i].name,
-							  (int)(cache->reg_list[i].size),
-							  value,
-							  cache->reg_list[i].dirty,
-							  cache->reg_list[i].valid);
-				free(value);
+				/* only print cached values if they are valid */
+				if (reg->valid) {
+					value = buf_to_str(reg->value,
+							reg->size, 16);
+					command_print(cmd_ctx,
+							"(%i) %s (/%u): 0x%s%s",
+							count, reg->name,
+							reg->size, value,
+							reg->dirty
+								? " (dirty)"
+								: "");
+					free(value);
+				} else {
+					command_print(cmd_ctx, "(%i) %s (/%u)",
+							  count, reg->name,
+							  reg->size) ;
+				}
 			}
 			cache = cache->next;
 		}

[Openocd-svn] r2593 - trunk/tcl/board

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-18 19:57:19 +0200 (Tue, 18 Aug 2009)
New Revision: 2593

Added:
   trunk/tcl/board/mini2440.cfg
Log:
Brian Findlay <fin...@gm...> Board support for mini2440 (friendlyARM) samsung s3c2440 based board

Added: trunk/tcl/board/mini2440.cfg
===================================================================
--- trunk/tcl/board/mini2440.cfg	2009-08-18 16:46:48 UTC (rev 2592)
+++ trunk/tcl/board/mini2440.cfg	2009-08-18 17:57:19 UTC (rev 2593)
@@ -0,0 +1,321 @@
+#-------------------------------------------------------------------------
+# Mini2440 Samsung s3c2440A Processor with 64MB DRAM, 64MB NAND, 2 MB N0R
+# NOTE: Configured for NAND boot (switch S2 in NANDBOOT)
+# 64 MB NAND (Samsung K9D1208V0M) 
+# B Findlay  08/2009
+# Rev 1.0
+#   ----------- Important notes to help you on your way ----------
+# README:
+#     NOR/NAND Boot Switch - I have not read the vivi source, but from
+#     what I could tell from reading the registers it appears that vivi
+#     loads itself into DRAM and then flips NFCONT (0x4E000004) bits
+#     Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND 
+#     FLASH at the bottom 64MB of memory. This essentially takes the 
+#     NOR Flash out of the circuit so you can't trash it. 
+#
+#     I adapted the samsung_s3c2440.cfg file which is why I did not
+#     include "source [find target/samsung_s3c2440.cfg]".  I believe
+#     the -work-area-phys 0x200000 is incorrect, but also had to pad
+#     some additional resets.  I didn't modify it as if it is working
+#     for someone, the work-area-phys is not used by most.
+#
+#     JTAG ADAPTER SPECIFIC
+#     IMPORTANT! Any JTAG device that uses ADAPTIVE CLOCKING will likely
+#     FAIL as the pin RTCK on the mini2440 10 pin JTAG Conn doesn't exist.
+#     This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is 
+#     necessary to FORCE setting the clock. Normally this should be configured
+#     in the openocd.cfg file, but was placed here as it can be a tough 
+#     problem to figure out.  THIS MAY NOT FIX YOUR PROBLEM.. I modified
+#     the openOCD driver jlink.c and posted it here. It may eventually end
+#     up changed in openOCD, but its a hack in the driver and really should
+#     be in the jtag layer (core.c me thinks), but haven't done it yet. My
+#     hack for jlink.c may be found here.
+#
+#     http://forum.sparkfun.com/viewtopic.php?t=16763&sid=946e65abdd3bab39cc7d90dee33ff135
+#
+#     Note: Also if you have a USB JTAG, you will need the USB library installed
+#     on your system "libusb-dev" or the make of openocd will fail. I *think*
+#     it's apt-get install libusb-dev.  When I made my config I only included
+#     --enable-jlink and --enable-usbdevs
+#
+#     I HAVE NOT Tested this throughly, so there could still be problems.
+#     But it should get you way ahead of the game from where I started.
+#     If you find problems (and fixes) please post them to
+#     ope...@li... and join the developers and
+#     check in fixes to this and anything else you find.  I do not 
+#     provide support, but if you ask really nice and I see anything 
+#     obvious I will tell you.. mostly just dig, fix, and submit to openocd.
+#     
+#     best!   brf...@ya...   Nashua, NH USA
+#
+#     Recommended resources:
+#       - first two are the best Mini2440 resources anywhere
+#       - maintained by buserror... thanks guy!
+#
+#       http://bliterness.blogspot.com/    
+#       http://code.google.com/p/mini2440/
+#
+#       others....
+# 
+#       http://forum.sparkfun.com/viewforum.php?f=18
+#       http://labs.kernelconcepts.de/Publications/Micro24401/
+#       http://www.friendlyarm.net/home
+#       http://www.amontec.com/jtag_pinout.shtml
+#
+#-------------------------------------------------------------------------
+#
+#
+# Your openocd.cfg file should contain:
+# source [find interface/<yourjtag>.cfg]
+# source [find board/mini2440.cfg]
+#
+#
+#
+#-------------------------------------------------------------------------
+# Target configuration for the Samsung 2440 system on chip
+# Tested on a S3C2440 Evaluation board by keesj
+# Processor : ARM920Tid(wb) rev 0 (v4l)
+# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d 
+#  (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
+#-------------------------------------------------------------------------
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME s3c2440
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+  # this defaults to a bigendian
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0x0032409d
+}
+
+#jtag scan chain
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm920t
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000  -work-area-size 0x4000 -work-area-backup 1
+
+#reset configuration
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100 
+reset_config trst_and_srst
+
+#-------------------------------------------------------------------------
+# JTAG ADAPTER SPECIFIC
+# IMPORTANT! See README at top of this file. 
+#-------------------------------------------------------------------------
+
+    jtag_khz 12000  
+    jtag_rclk 3000
+    jtag interface   
+
+#-------------------------------------------------------------------------
+# GDB Setup
+#-------------------------------------------------------------------------
+
+    gdb_port 3333
+    gdb_detach resume
+    gdb_breakpoint_override hard 
+    gdb_memory_map enable
+    gdb_flash_program enable 
+
+#------------------------------------------------
+# ARM SPECIFIC
+#------------------------------------------------
+
+    targets 
+  #  arm7_9 dcc_downloads enable
+  #  arm7_9 fast_memory_access enable
+  
+ 
+    nand device s3c2440 0 
+
+    jtag_nsrst_delay 100
+    jtag_ntrst_delay 100 
+    reset_config trst_and_srst
+    init
+
+    echo " "
+    echo "-------------------------------------------"
+    echo "--- login with - telnet localhost 4444  ---"
+    echo "--- then type help_2440                 ---"
+    echo "-------------------------------------------"
+    echo " "
+
+
+
+#------------------------------------------------
+# Processor Initialialization
+# Note: Processor writes can only occur when
+# the state is in SYSTEM. When you call init_2440
+# one of the first lines will tell you what state
+# you are in. If a linux image is booting
+# when you run this, it will not work
+# a vivi boot loader will run with this just
+# fine. The reg values were obtained by a combination
+# of figuring them out fromt the manual, and looking
+# at post vivi values with the debugger. Don't
+# place too much faith in them, but seem to work.
+#------------------------------------------------
+
+proc init_2440 { } {
+
+    halt
+    s3c2440.cpu curstate
+
+    #-----------------------------------------------
+    # Set Processor Clocks - mini2440 xtal=12mHz
+    # we set main clock for 405mHZ
+    # we set the USB Clock for 48mHz
+    # OM2 OM3 pulled to ground so main clock and
+    # usb clock are off 12mHz xtal
+    #-----------------------------------------------
+   
+    arm920t mww_phys 0x4C000014 0x00000005 #  Clock Divider control Reg
+    arm920t mww_phys 0x4C000000 0xFFFFFFFF #  LOCKTIME count register
+    arm920t mww_phys 0x4C000008 0x00038022 #  UPPLCON  USB clock config Reg
+    arm920t mww_phys 0x4C000004 0x0007F021 #  MPPLCON  Proc clock config Reg
+	
+    #-----------------------------------------------
+    # Configure Memory controller
+    # BWSCON configures all banks, NAND, NOR, DRAM
+    # DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7
+    #-----------------------------------------------
+	
+    arm920t mww_phys 0x48000000 0x22111112 #  BWSCON - Bank and Bus Width
+    arm920t mww_phys 0x48000010 0x00001112 #  BANKCON4 - ?
+    arm920t mww_phys 0x4800001c 0x00018009 #  BANKCON6 - DRAM	
+    arm920t mww_phys 0x48000020 0x00018009 #  BANKCON7 - DRAM	
+    arm920t mww_phys 0x48000024 0x008E04EB #  REFRESH  - DRAM		
+    arm920t mww_phys 0x48000028 0x000000B2 #  BANKSIZE - DRAM		
+    arm920t mww_phys 0x4800002C 0x00000030 #  MRSRB6 - DRAM		
+    arm920t mww_phys 0x48000030 0x00000030 #  MRSRB7 - DRAM					
+		
+    #-----------------------------------------------
+    # Now port configuration for enables for memory
+    # and other stuff.
+    #-----------------------------------------------
+    
+    arm920t mww_phys 0x56000000	0x007FFFFF #  GPACON
+    
+    arm920t mww_phys 0x56000010	0x00295559 #  GPBCON   
+    arm920t mww_phys 0x56000018	0x000003FF #  GPBUP (PULLUP ENABLE)
+    arm920t mww_phys 0x56000014	0x000007C2 #  GPBDAT   	    
+    
+    arm920t mww_phys 0x56000020	0xAAAAA6AA #  GPCCON   	
+    arm920t mww_phys 0x56000028	0x0000FFFF #  GPCUP
+    arm920t mww_phys 0x56000024	0x00000020 #  GPCDAT   	 	   	
+    
+    arm920t mww_phys 0x56000030	0xAAAAAAAA #  GPDCON   	
+    arm920t mww_phys 0x56000038	0x0000FFFF #  GPDUP    
+    
+    arm920t mww_phys 0x56000040	0xAAAAAAAA #  GPECON   	
+    arm920t mww_phys 0x56000048	0x0000FFFF #  GPEUP    
+    
+    arm920t mww_phys 0x56000050	0x00001555 #  GPFCON   	
+    arm920t mww_phys 0x56000058	0x0000007F #  GPFUP    
+    arm920t mww_phys 0x56000054	0x00000000 #  GPFDAT       
+     
+    arm920t mww_phys 0x56000060	0x00150114 #  GPGCON   	
+    arm920t mww_phys 0x56000068	0x0000007F #  GPGUP        
+ 
+    arm920t mww_phys 0x56000070	0x0015AAAA #  GPHCON  
+    arm920t mww_phys 0x56000078	0x000003FF #  GPGUP       
+
+}	
+
+
+
+proc flash_config { } {
+
+    #-----------------------------------------
+    # Finish Flash Configuration
+    #-----------------------------------------
+
+    halt
+    
+    #flash configuration (K9D1208V0M: 512Mbit, x8, 3.3V, Mode: Normal, 1st gen)
+    nand probe 0
+    nand list
+}
+
+proc flash_uboot { } {
+
+	# flash the u-Boot binary and reboot into it
+	init_2440
+	flash_config
+	nand erase 0 0x0 0x40000
+	nand write 0 /tftpboot/u-boot-nand512.bin 0 oob_softecc_kw
+	resume
+}
+
+
+proc load_uboot { } {
+        echo " "
+        echo " "
+        echo "----------------------------------------------------------"
+        echo "---- Load U-Boot into RAM and execute it.              ---"
+        echo "---- NOTE: loads, partially runs, and hangs            ---"
+        echo "---- U-Boot is fine, this image runs from vivi.        ---"
+        echo "---- I burned u-boot into NAND so I didn't finish      ---"
+        echo "---- debugging it. I am leaving this here as it is     ---"
+        echo "---- part of the way there if you want to fix it.      ---"
+        echo "----                                                   ---"
+        echo "---- mini2440 U-boot here:                             ---"
+        echo "---- http://repo.or.cz/w/u-boot-openmoko/mini2440.git  ---"
+        echo "---- Also this:                                        ---"
+        echo "---- http://code.google.com/p/mini2440/wiki/MiniBringup --"
+        echo "----------------------------------------------------------"      
+  
+	init_2440
+	echo "Loading /tftpboot/u-boot-nand512.bin"
+	load_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin
+	echo "Verifying image...."
+	verify_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin
+	echo "jumping to u-boot"
+        #bp 0x33f80068 4 hw
+        reg 0 0
+        reg 1 0
+        reg 2 0
+        reg 3 0
+        reg 4 0x33f80000
+      	resume 0x33f80000
+}
+
+       # this may help a little bit debugging the load_uboot
+proc s {} {
+        step
+        reg
+        armv4_5 disassemble 0x33F80068 0x10
+}
+
+proc help_2440 {} {
+    echo " "
+    echo " "
+    echo "-----------------------------------------------------------"
+    echo "---- The following mini2440 funcs are supported        ----"
+    echo "----   init_2440 - initialize clocks, DRAM, IO         ----"
+    echo "----   flash_config - configures nand flash            ----"
+    echo "----   load_uboot - loads uboot into ram               ----"
+    echo "----   flash_uboot - flashes uboot to nand (untested)  ----"
+    echo "----   help_2440 - this help display                   ----"
+    echo "-----------------------------------------------------------"
+    echo " "
+    echo " "
+}
+
+
+#----------------------------------------------------------------------------
+#----------------------------------- END ------------------------------------
+#----------------------------------------------------------------------------


Property changes on: trunk/tcl/board/mini2440.cfg
___________________________________________________________________
Name: svn:eol-style
   + native

[Openocd-svn] r2592 - in trunk: doc tcl/interface

[ntfreak at B. <nt...@ma...>]

Author: ntfreak
Date: 2009-08-18 18:46:48 +0200 (Tue, 18 Aug 2009)
New Revision: 2592

Added:
   trunk/tcl/interface/jtagkey2.cfg
Modified:
   trunk/doc/openocd.texi
Log:
- add cfg file for Amontec JTAGKey2 jtag interface

Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-08-18 14:41:58 UTC (rev 2591)
+++ trunk/doc/openocd.texi	2009-08-18 16:46:48 UTC (rev 2592)
@@ -281,6 +281,8 @@
 @* Link @url{http://www.hs-augsburg.de/~hhoegl/proj/usbjtag/usbjtag.html}
 @item @b{jtagkey}
 @* See: @url{http://www.amontec.com/jtagkey.shtml}
+@item @b{jtagkey2}
+@* See: @url{http://www.amontec.com/jtagkey2.shtml}
 @item @b{oocdlink}
 @* See: @url{http://www.oocdlink.com} By Joern Kaipf
 @item @b{signalyzer}
@@ -1585,6 +1587,7 @@
 @item @b{flyswatter} Tin Can Tools Flyswatter
 @item @b{icebear} ICEbear JTAG adapter from Section 5
 @item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
+@item @b{jtagkey2} Amontec JTAGkey2 (and compatibles)
 @item @b{m5960} American Microsystems M5960
 @item @b{olimex-jtag} Olimex ARM-USB-OCD and ARM-USB-Tiny
 @item @b{oocdlink} OOCDLink

Added: trunk/tcl/interface/jtagkey2.cfg
===================================================================
--- trunk/tcl/interface/jtagkey2.cfg	2009-08-18 14:41:58 UTC (rev 2591)
+++ trunk/tcl/interface/jtagkey2.cfg	2009-08-18 16:46:48 UTC (rev 2592)
@@ -0,0 +1,11 @@
+#
+# Amontec JTAGkey2
+#
+# http://www.amontec.com/jtagkey2.shtml
+#
+
+interface ft2232
+ft2232_device_desc "Amontec JTAGkey-2"
+ft2232_layout jtagkey
+ft2232_vid_pid 0x0403 0xCFF8
+


Property changes on: trunk/tcl/interface/jtagkey2.cfg
___________________________________________________________________
Name: svn:eol-style
   + native

[Openocd-svn] r2591 - in trunk: . src/jtag

[ntfreak at B. <nt...@ma...>]

Author: ntfreak
Date: 2009-08-18 16:41:58 +0200 (Tue, 18 Aug 2009)
New Revision: 2591

Modified:
   trunk/README
   trunk/configure.in
   trunk/src/jtag/ft2232.c
Log:
Jonas Horberg [jho...@sa...]
https://lists.berlios.de/pipermail/openocd-development/2009-August/009939.html

1. It can only be built with the FTD2XX driver. libftdi supports FT2232H/FT4232H 
since version 0.16 

2. A speed value of 0 is used as a RTCK request indicator. This clashes with the 
valid clock division value 0 that provide the highest fixed clock frequency. 

3. The ft2232_speed_div function return the maximum selectable frequency (30MHz) 
when RTCK is activated. It should return 0. 

4. The ft2232_khz function return ERROR_OK when RTCK is requested even for 
devices lacking RTCK support. It should return ERROR_FAIL so the upper driver layers 
can detect this and try to fallback to a fixed frequency. 

5. FT2232H/FT4232H have a backward compatibility function that divide the clock 
by 5 to get the same frequency range as FT2232D. There is no code that disable 
this functionality. I can not find anything about if this is enabled or disabled by default. 
I think it is safest to actively disable it. 


Modified: trunk/README
===================================================================
--- trunk/README	2009-08-18 12:14:01 UTC (rev 2590)
+++ trunk/README	2009-08-18 14:41:58 UTC (rev 2591)
@@ -125,7 +125,7 @@
 The INSTALL file contains generic instructions for running 'configure'
 and compiling the OpenOCD source code.  That file is provided by default
 for all GNU automake packages.  If you are not familiar with the GNU
-autotools, then you should read those instructions first.  
+autotools, then you should read those instructions first.
 
 The remainder of this document tries to provide some instructions for
 those looking for a quick-install.
@@ -163,7 +163,7 @@
 of commands:
 
    ./configure [with some options listed in the next section]
-   make 
+   make
    make install
 
 The 'configure' step generates the Makefiles required to build OpenOCD,
@@ -180,7 +180,7 @@
 cross-compile on a x86 Linux host to run on Windows (MinGW32), you could
 use the following configuration options:
 
-  ./configure --build=i686-pc-linux-gnu --host=i586-mingw32msvc ... 
+  ./configure --build=i686-pc-linux-gnu --host=i586-mingw32msvc ...
 
 Likewise, the following options allow OpenOCD to be cross-compiled for
 an ARM target on the same x86 host:
@@ -215,9 +215,10 @@
                           FTD2XX
   --enable-ft2232_ftd2xx  Enable building support for FT2232 based devices
                           using the FTD2XX driver from ftdichip.com
-  --enable-ftd2xx-highspeed
+  --enable-ft2232-highspeed
                           Enable building support for FT2232H and
-                          FT4232H-based devices (requires >=libftd2xx-0.4.16)
+                          FT4232H-based devices (requires >=libftd2xx-0.4.16
+                          or >=libftdi-0.16)
 
   --enable-gw16012        Enable building support for the Gateworks GW16012
                           JTAG Programmer
@@ -301,12 +302,12 @@
 option if you want to use giveio instead of ioperm parallel port access
 method.
 
-FT2232C Based USB Dongles 
+FT2232C Based USB Dongles
 -------------------------
 
 There are 2 methods of using the FTD2232, either (1) using the
 FTDICHIP.COM closed source driver, or (2) the open (and free) driver
-libftdi. 
+libftdi.
 
 Using LIBFTDI
 -------------
@@ -320,7 +321,7 @@
 speed (480 Mbps), you need libftdi version 0.16 or newer.  Many Linux
 distributions provide suitable packages for these libraries.
 
-For Windows, libftdi is supported with versions 0.14 and later.  
+For Windows, libftdi is supported with versions 0.14 and later.
 
 With these prerequisites met, configure the libftdi solution like this:
 
@@ -340,7 +341,7 @@
 The FTDICHIP drivers come as either a (win32) ZIP file, or a (Linux)
 TAR.GZ file. You must unpack them ``some where'' convient. As of this
 writing FTDICHIP does not supply means to install these files "in an
-appropriate place."  
+appropriate place."
 
 If your distribution does not package these, there are several
 './configure' options to solve this problem:
@@ -361,7 +362,7 @@
 Remember, this library is binary-only, while OpenOCD is licenced
 according to GNU GPLv2 without any exceptions.  That means that
 _distributing_ copies of OpenOCD built with the FTDI code would violate
-the OpenOCD licensing terms.  
+the OpenOCD licensing terms.
 
 Linux Notes
 ***********
@@ -404,7 +405,7 @@
 ************************************************
 
 Building OpenOCD from a repository requires a recent version of the GNU
-autotools (autoconf >= 2.59 and automake >= 1.9).  
+autotools (autoconf >= 2.59 and automake >= 1.9).
 
 1) Run './bootstrap' to create the 'configure' script and prepare
    the build process for your host system.

Modified: trunk/configure.in
===================================================================
--- trunk/configure.in	2009-08-18 12:14:01 UTC (rev 2590)
+++ trunk/configure.in	2009-08-18 14:41:58 UTC (rev 2591)
@@ -128,7 +128,7 @@
     # Nonstandard --prefix and/or --exec-prefix
     # We have an override of some sort.
     # use build specific install library dir
-    
+
     LDFLAGS="$LDFLAGS -L$OCDxprefix/lib"
     # RPATH becomes an issue on Linux only
     if test $host_os = linux-gnu || test $host_os = linux ; then
@@ -146,7 +146,7 @@
 
 The option: --with-ftd2xx=<PATH> has been removed.
 On Linux, the new option is:
-  
+
   --with-ftd2xx-linux-tardir=/path/to/files
 
 Where <path> is the path the the directory where the "tar.gz" file
@@ -245,7 +245,7 @@
 
 AC_ARG_ENABLE(verbose,
   AS_HELP_STRING([--enable-verbose],
-      [Enable verbose JTAG I/O messages (for debugging).]), 
+      [Enable verbose JTAG I/O messages (for debugging).]),
   [
   debug_jtag_io=$enableval
   debug_usb_io=$enableval
@@ -254,15 +254,15 @@
 
 AC_ARG_ENABLE(verbose_jtag_io,
   AS_HELP_STRING([--enable-verbose-jtag-io],
-      [Enable verbose JTAG I/O messages (for debugging).]), 
+      [Enable verbose JTAG I/O messages (for debugging).]),
   [debug_jtag_io=$enableval], [])
 AC_ARG_ENABLE(verbose_usb_io,
   AS_HELP_STRING([--enable-verbose-usb-io],
-      [Enable verbose USB I/O messages (for debugging)]), 
+      [Enable verbose USB I/O messages (for debugging)]),
   [debug_usb_io=$enableval], [])
 AC_ARG_ENABLE(verbose_usb_comms,
   AS_HELP_STRING([--enable-verbose-usb-comms],
-      [Enable verbose USB communication messages (for debugging)]), 
+      [Enable verbose USB communication messages (for debugging)]),
   [debug_usb_comms=$enableval], [])
 
 AC_MSG_CHECKING([whether to enable verbose JTAG I/O messages]);
@@ -287,7 +287,7 @@
 debug_malloc=no
 AC_ARG_ENABLE(malloc_logging,
   AS_HELP_STRING([--enable-malloc-logging],
-      [Include free space in logging messages (requires malloc.h).]), 
+      [Include free space in logging messages (requires malloc.h).]),
   [debug_malloc=$enableval], [])
 
 AC_MSG_CHECKING([whether to enable malloc free space logging]);
@@ -298,67 +298,67 @@
 
 
 AC_ARG_ENABLE(dummy,
-  AS_HELP_STRING([--enable-dummy], [Enable building the dummy port driver]), 
+  AS_HELP_STRING([--enable-dummy], [Enable building the dummy port driver]),
   [build_dummy=$enableval], [build_dummy=no])
 
 AC_ARG_ENABLE(parport,
-  AS_HELP_STRING([--enable-parport], [Enable building the pc parallel port driver]), 
+  AS_HELP_STRING([--enable-parport], [Enable building the pc parallel port driver]),
   [build_parport=$enableval], [build_parport=no])
 
 AC_ARG_ENABLE(parport_ppdev,
   AS_HELP_STRING([--disable-parport-ppdev],
-      [Disable use of ppdev (/dev/parportN) for parport (for x86 only)]), 
+      [Disable use of ppdev (/dev/parportN) for parport (for x86 only)]),
     [parport_use_ppdev=$enableval], [parport_use_ppdev=yes])
 
 AC_ARG_ENABLE(parport_giveio,
     AS_HELP_STRING([--enable-parport-giveio],
-      [Enable use of giveio for parport (for CygWin only)]), 
+      [Enable use of giveio for parport (for CygWin only)]),
     [parport_use_giveio=$enableval], [parport_use_giveio=])
-    
+
 AC_ARG_ENABLE(ft2232_libftdi,
-  AS_HELP_STRING([--enable-ft2232_libftdi], [Enable building support for FT2232 based devices using the libftdi driver, opensource alternate of FTD2XX]), 
+  AS_HELP_STRING([--enable-ft2232_libftdi], [Enable building support for FT2232 based devices using the libftdi driver, opensource alternate of FTD2XX]),
   [build_ft2232_libftdi=$enableval], [build_ft2232_libftdi=no])
 
 AC_ARG_ENABLE(ft2232_ftd2xx,
-  AS_HELP_STRING([--enable-ft2232_ftd2xx], [Enable building support for FT2232 based devices using the FTD2XX driver from ftdichip.com]), 
+  AS_HELP_STRING([--enable-ft2232_ftd2xx], [Enable building support for FT2232 based devices using the FTD2XX driver from ftdichip.com]),
   [build_ft2232_ftd2xx=$enableval], [build_ft2232_ftd2xx=no])
 
-AC_ARG_ENABLE(ftd2xx_highspeed,
-  AS_HELP_STRING([--enable-ftd2xx-highspeed], [Enable building support for FT2232H and FT4232H-based devices (requires >=libftd2xx-0.4.16)]), 
-  [want_ftd2xx_highspeed=$enableval], [want_ftd2xx_highspeed=no])
- 
+AC_ARG_ENABLE(ft2232_highspeed,
+  AS_HELP_STRING([--enable-ft2232-highspeed], [Enable building support for FT2232H and FT4232H-based devices (requires >=libftd2xx-0.4.16 or >=libftdi-0.16)]),
+  [want_ft2232_highspeed=$enableval], [want_ft2232_highspeed=no])
+
 AC_ARG_ENABLE(amtjtagaccel,
-  AS_HELP_STRING([--enable-amtjtagaccel], [Enable building the Amontec JTAG-Accelerator driver]), 
+  AS_HELP_STRING([--enable-amtjtagaccel], [Enable building the Amontec JTAG-Accelerator driver]),
   [build_amtjtagaccel=$enableval], [build_amtjtagaccel=no])
 
 AC_ARG_ENABLE(ecosboard,
-  AS_HELP_STRING([--enable-ecosboard], [Enable building support for eCos based JTAG debugger]), 
+  AS_HELP_STRING([--enable-ecosboard], [Enable building support for eCos based JTAG debugger]),
   [build_ecosboard=$enableval], [build_ecosboard=no])
 
 AC_ARG_ENABLE(zy1000,
-  AS_HELP_STRING([--enable-zy1000], [Enable ZY1000 interface]), 
+  AS_HELP_STRING([--enable-zy1000], [Enable ZY1000 interface]),
   [build_zy1000=$enableval], [build_zy1000=no])
 
 AC_ARG_ENABLE(ioutil,
-  AS_HELP_STRING([--enable-ioutil], [Enable ioutil functions - useful for standalone OpenOCD implementations]), 
+  AS_HELP_STRING([--enable-ioutil], [Enable ioutil functions - useful for standalone OpenOCD implementations]),
   [build_ioutil=$enableval], [build_ioutil=no])
 
 AC_ARG_ENABLE(httpd,
-  AS_HELP_STRING([--enable-httpd], [Enable builtin httpd server - useful for standalone OpenOCD implementations]), 
+  AS_HELP_STRING([--enable-httpd], [Enable builtin httpd server - useful for standalone OpenOCD implementations]),
   [build_httpd=$enableval], [build_httpd=no])
 
-case "${host_cpu}" in 
+case "${host_cpu}" in
   arm*)
     AC_ARG_ENABLE(ep93xx,
-      AS_HELP_STRING([--enable-ep93xx], [Enable building support for EP93xx based SBCs]), 
+      AS_HELP_STRING([--enable-ep93xx], [Enable building support for EP93xx based SBCs]),
       [build_ep93xx=$enableval], [build_ep93xx=no])
 
     AC_ARG_ENABLE(at91rm9200,
       AS_HELP_STRING([--enable-at91rm9200], [Enable building support for AT91RM9200 based SBCs]),
       [build_at91rm9200=$enableval], [build_at91rm9200=no])
     ;;
-    
-  *) 
+
+  *)
     build_ep93xx=no
     build_at91rm9200=no
     ;;
@@ -439,10 +439,10 @@
   AC_MSG_RESULT([yes])
 fi
 
-case "${host_cpu}" in 
+case "${host_cpu}" in
   i?86|x86*)
     ;;
-  *) 
+  *)
     if test x$parport_use_ppdev = xno; then
       AC_MSG_WARN([--disable-parport-ppdev is not supported by the host CPU])
     fi
@@ -450,8 +450,8 @@
     ;;
 esac
 
-case $host in 
-  *-cygwin*) 
+case $host in
+  *-cygwin*)
     is_win32=yes
     parport_use_ppdev=no
 
@@ -472,11 +472,11 @@
         AC_CHECK_HEADERS(sys/io.h,[],AC_MSG_ERROR([Please install the cygwin ioperm package]))
       fi
     fi
-  
+
     AC_DEFINE(IS_WIN32, 1, [1 if building for Win32.])
     AC_DEFINE(IS_DARWIN, 0, [0 if not building for Darwin.])
-    ;; 
-  *-mingw*) 
+    ;;
+  *-mingw*)
     is_mingw=yes
     is_win32=yes
     parport_use_ppdev=no
@@ -489,7 +489,7 @@
     AC_DEFINE(IS_MINGW, 1, [1 if building for MinGW.])
     AC_DEFINE(IS_WIN32, 1, [1 if building for Win32.])
     AC_DEFINE(IS_DARWIN, 0, [0 if not building for Darwin.])
-    ;; 
+    ;;
   *darwin*)
     is_darwin=yes
 
@@ -502,7 +502,7 @@
     AC_DEFINE(IS_WIN32, 0, [0 if not building for Win32.])
     AC_DEFINE(IS_DARWIN, 1, [1 if building for Darwin.])
     ;;
-  *) 
+  *)
     if test x$parport_use_giveio = xyes; then
       AC_MSG_WARN([--enable-parport-giveio cannot be used by ]$host[ hosts])
     fi
@@ -835,8 +835,8 @@
   ])
 
 AC_MSG_CHECKING([whether to build ftd2xx highspeed device support])
-AC_MSG_RESULT([$want_ftd2xx_highspeed])
-if test $want_ftd2xx_highspeed != no; then
+AC_MSG_RESULT([$want_ft2232_highspeed])
+if test $want_ft2232_highspeed != no; then
   AC_MSG_CHECKING([for ftd2xx highspeed device support])
   AC_COMPILE_IFELSE([
 #include "confdefs.h"
@@ -847,15 +847,15 @@
 #include <ftd2xx.h>
 DWORD x = FT_DEVICE_4232H;
     ], [
-      AC_DEFINE(BUILD_FTD2XX_HIGHSPEED, [1],
-        [Support FT2232H/FT4232HS with FTD2XX.])
-      build_ftd2xx_highspeed=yes
+      AC_DEFINE(BUILD_FT2232_HIGHSPEED, [1],
+        [Support FT2232H/FT4232HS with FTD2XX or libftdi.])
+      build_ft2232_highspeed=yes
     ], [
-      build_ftd2xx_highspeed=no
+      build_ft2232_highspeed=no
     ])
-  AC_MSG_RESULT([$build_ftd2xx_highspeed])
+  AC_MSG_RESULT([$build_ft2232_highspeed])
 
-  if test $want_ftd2xx_highspeed = yes -a $build_ftd2xx_highspeed = no; then
+  if test $want_ft2232_highspeed = yes -a $build_ft2232_highspeed = no; then
     AC_MSG_ERROR([You need a newer FTD2XX driver (version 0.4.16 or later).])
   fi
 fi
@@ -868,7 +868,7 @@
   # We assume: the package is preinstalled in the proper place
   # these present as 2 libraries..
   LIBS="$LIBS -lftdi -lusb"
-  # 
+  #
   # Try to build a small program.
   AC_MSG_CHECKING([Build & Link with libftdi...])
 
@@ -903,6 +903,28 @@
       AC_MSG_RESULT([Skipping as we are cross-compiling])
     ])
 
+  AC_MSG_CHECKING([whether to build libftdi highspeed device support])
+  AC_MSG_RESULT([$want_ft2232_highspeed])
+  if test $want_ft2232_highspeed != no; then
+    AC_MSG_CHECKING([for libftdi highspeed device support])
+    AC_COMPILE_IFELSE([
+#include <stdio.h>
+#include <ftdi.h>
+enum ftdi_chip_type x = TYPE_2232H;
+    ], [
+      AC_DEFINE(BUILD_FT2232_HIGHSPEED, [1],
+        [Support FT2232H/FT4232HS with FTD2XX or libftdi.])
+      build_ft2232_highspeed=yes
+    ], [
+      build_ft2232_highspeed=no
+    ])
+    AC_MSG_RESULT([$build_ft2232_highspeed])
+
+    if test $want_ft2232_highspeed = yes -a $build_ft2232_highspeed = no; then
+      AC_MSG_ERROR([You need a newer libftdi version (0.16 or later).])
+    fi
+  fi
+
   # Restore the 'unexpanded ldflags'
   LDFLAGS=$LDFLAGS_SAVE
   CFLAGS=$CFLAGS_SAVE
@@ -911,7 +933,7 @@
 # check for usb.h when a driver will require it
 if test $build_jlink = yes -o $build_vsllink = yes -o $build_usbprog = yes -o \
   $build_rlink = yes -o $build_armjtagew = yes
-then 
+then
   AC_CHECK_HEADERS([usb.h],[],
   [AC_MSG_ERROR([usb.h is required to build some OpenOCD driver(s)])])
 fi
@@ -976,7 +998,7 @@
   ])
 
 if test "${has_environ}" != "yes" ; then
-  AC_MSG_FAILURE([Could not find 'environ' in unistd.h or available libraries.]) 
+  AC_MSG_FAILURE([Could not find 'environ' in unistd.h or available libraries.])
 fi
 
 AC_DEFINE([_GNU_SOURCE],[1],[Use GNU C library extensions (e.g. stdndup).])

Modified: trunk/src/jtag/ft2232.c
===================================================================
--- trunk/src/jtag/ft2232.c	2009-08-18 12:14:01 UTC (rev 2590)
+++ trunk/src/jtag/ft2232.c	2009-08-18 14:41:58 UTC (rev 2591)
@@ -24,7 +24,6 @@
 *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
 ***************************************************************************/
 
-
 /* This code uses information contained in the MPSSE specification which was
  * found here:
  * http://www.ftdichip.com/Documents/AppNotes/AN2232C-01_MPSSE_Cmnd.pdf
@@ -34,7 +33,6 @@
  * http://www.ftdichip.com/Documents/DataSheets/DS_FT2232D.pdf
  */
 
-
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
@@ -65,6 +63,10 @@
 
 /* max TCK for the high speed devices 30000 kHz */
 #define	FTDI_2232H_4232H_MAX_TCK	30000
+/* max TCK for the full speed devices 6000 kHz */
+#define	FTDI_2232C_MAX_TCK 6000
+/* this speed value tells that RTCK is requested */
+#define RTCK_SPEED -1
 
 static int ft2232_execute_queue(void);
 
@@ -81,7 +83,6 @@
 static int ft2232_handle_vid_pid_command(struct command_context_s* cmd_ctx, char* cmd, char** args, int argc);
 static int ft2232_handle_latency_command(struct command_context_s* cmd_ctx, char* cmd, char** args, int argc);
 
-
 /**
  * Send out \a num_cycles on the TCK line while the TAP(s) are in a
  * stable state.  Calling code must ensure that current state is stable,
@@ -94,17 +95,13 @@
  */
 static int ft2232_stableclocks(int num_cycles, jtag_command_t* cmd);
 
-/* max TCK for the high speed devices 30000 kHz */
-#define	FTDI_2232H_4232H_MAX_TCK	30000
-
 static char *       ft2232_device_desc_A = NULL;
 static char*        ft2232_device_desc = NULL;
 static char*        ft2232_serial  = NULL;
 static char*        ft2232_layout  = NULL;
 static uint8_t		ft2232_latency = 2;
-static unsigned		ft2232_max_tck = 6000;
+static unsigned		ft2232_max_tck = FTDI_2232C_MAX_TCK;
 
-
 #define MAX_USB_IDS 8
 /* vid = pid = 0 marks the end of the list */
 static uint16_t ft2232_vid[MAX_USB_IDS + 1] = { 0x0403, 0 };
@@ -182,13 +179,12 @@
 static FT_DEVICE	ftdi_device = 0;
 #elif BUILD_FT2232_LIBFTDI == 1
 static struct ftdi_context ftdic;
+static enum ftdi_chip_type ftdi_device;
 #endif
 
-
 static jtag_command_t* first_unsent;        /* next command that has to be sent */
 static int             require_send;
 
-
 /*	http://urjtag.wiki.sourceforge.net/Cable + FT2232 says:
 
 	"There is a significant difference between libftdi and libftd2xx. The latter
@@ -232,7 +228,6 @@
 	return ft2232_buffer[ft2232_read_pointer++];
 }
 
-
 /**
  * Clocks out \a bit_count bits on the TMS line, starting with the least
  * significant bit of tms_bits and progressing to more significant bits.
@@ -258,7 +253,9 @@
 
 	assert(tms_count > 0);
 
-//	LOG_DEBUG("mpsse cmd=%02x, tms_bits = 0x%08x, bit_count=%d", mpsse_cmd, tms_bits, tms_count);
+#if 0
+	LOG_DEBUG("mpsse cmd=%02x, tms_bits = 0x%08x, bit_count=%d", mpsse_cmd, tms_bits, tms_count);
+#endif
 
 	for (tms_byte = tms_ndx = i = 0;   i < tms_count;   ++i, tms_bits>>=1)
 	{
@@ -288,7 +285,6 @@
 	}
 }
 
-
 /**
  * Function get_tms_buffer_requirements
  * returns what clock_tms() will consume if called with
@@ -299,7 +295,6 @@
 	return ((bit_count + 6)/7) * 3;
 }
 
-
 /**
  * Function move_to_state
  * moves the TAP controller from the current state to a
@@ -326,7 +321,6 @@
 	clock_tms(0x4b,  tms_bits, tms_count, 0);
 }
 
-
 jtag_interface_t ft2232_interface =
 {
 	.name			= "ft2232",
@@ -343,7 +337,7 @@
 {
 #if BUILD_FT2232_FTD2XX == 1
 	FT_STATUS status;
-	DWORD	dw_bytes_written;
+	DWORD dw_bytes_written;
 	if ((status = FT_Write(ftdih, buf, size, &dw_bytes_written)) != FT_OK)
 	{
 		*bytes_written = dw_bytes_written;
@@ -371,13 +365,12 @@
 #endif
 }
 
-
 static int ft2232_read(uint8_t* buf, uint32_t size, uint32_t* bytes_read)
 {
 #if BUILD_FT2232_FTD2XX == 1
-	DWORD     dw_bytes_read;
+	DWORD dw_bytes_read;
 	FT_STATUS status;
-	int       timeout = 5;
+	int timeout = 5;
 	*bytes_read = 0;
 
 	while ((*bytes_read < size) && timeout--)
@@ -421,59 +414,88 @@
 	return ERROR_OK;
 }
 
-#ifdef BUILD_FTD2XX_HIGHSPEED
 static bool ft2232_device_is_highspeed(void)
 {
+#ifdef BUILD_FT2232_HIGHSPEED
+	#if BUILD_FT2232_FTD2XX == 1
 	return (ftdi_device == FT_DEVICE_2232H) || (ftdi_device == FT_DEVICE_4232H);
+	#elif BUILD_FT2232_LIBFTDI == 1
+	return (ftdi_device == TYPE_2232H || ftdi_device == TYPE_4232H);
+	#endif
+#else
+	return false;
+#endif
 }
 
-static int ft2232_adaptive_clocking(int speed)
-{
-	bool use_adaptive_clocking = FALSE;
-	if (0 == speed)
-	{
-		if (ft2232_device_is_highspeed())
-			use_adaptive_clocking = TRUE;
-		else
-		{
-			LOG_ERROR("ft2232 device %lu does not support RTCK", ftdi_device);
-			return ERROR_OK;
-		}
-	}
+/*
+ * Commands that only apply to the FT2232H and FT4232H devices.
+ * See chapter 6 in http://www.ftdichip.com/Documents/AppNotes/
+ * AN_108_Command_Processor_for_MPSSE_and_MCU_Host_Bus_Emulation_Modes.pdf
+ */
 
-	uint8_t  buf = use_adaptive_clocking ? 0x96 : 0x97;
+static int ft2232h_ft4232h_adaptive_clocking(bool enable)
+{
+	uint8_t buf = enable ? 0x96 : 0x97;
 	LOG_DEBUG("%2.2x", buf);
 
 	uint32_t bytes_written;
 	int retval = ft2232_write(&buf, 1, &bytes_written);
-	if (ERROR_OK != retval || bytes_written != 1)
+	if ((ERROR_OK != retval) || (bytes_written != 1))
 	{
-		LOG_ERROR("unable to set adative clocking: %d", retval);
+		LOG_ERROR("couldn't write command to %s adaptive clocking"
+			, enable ? "enable" : "disable");
 		return retval;
 	}
 
 	return ERROR_OK;
 }
-#else
-static int ft2232_adaptive_clocking(int speed)
+
+/**
+ * Enable/disable the clk divide by 5 of the 60MHz master clock.
+ * This result in a JTAG clock speed range of 91.553Hz-6MHz
+ * respective 457.763Hz-30MHz.
+ */
+static int ft2232h_ft4232h_clk_divide_by_5(bool enable)
 {
-	// not implemented on low-speed devices
-	return speed ? ERROR_OK : -1234;
+	uint32_t bytes_written;
+	uint8_t buf = enable ?  0x8b : 0x8a;
+	int retval = ft2232_write(&buf, 1, &bytes_written);
+	if ((ERROR_OK != retval) || (bytes_written != 1))
+	{
+		LOG_ERROR("couldn't write command to %s clk divide by 5"
+			, enable ? "enable" : "disable");
+		return ERROR_JTAG_INIT_FAILED;
+	}
+	ft2232_max_tck = enable ? FTDI_2232C_MAX_TCK : FTDI_2232H_4232H_MAX_TCK;
+	LOG_INFO("max TCK change to: %u kHz", ft2232_max_tck);
+
+	return ERROR_OK;
 }
-#endif
 
 static int ft2232_speed(int speed)
 {
-	uint8_t  buf[3];
+	uint8_t buf[3];
 	int retval;
 	uint32_t bytes_written;
 
-	ft2232_adaptive_clocking(speed);
+	retval = ERROR_OK;
+	bool enable_adaptive_clocking = (RTCK_SPEED == speed);
+	if (ft2232_device_is_highspeed())
+		retval = ft2232h_ft4232h_adaptive_clocking(enable_adaptive_clocking);
+	else if (enable_adaptive_clocking)
+	{
+		LOG_ERROR("ft2232 device %lu does not support RTCK"
+			, (long unsigned int)ftdi_device);
+		return ERROR_FAIL;
+	}
 
-	buf[0] = 0x86;			/* command "set divisor" */
-	buf[1] = speed & 0xff;          /* valueL (0 = 6MHz, 1 = 3MHz, 2 = 2.0MHz, ...*/
-	buf[2] = (speed >> 8) & 0xff;   /* valueH */
+	if ((enable_adaptive_clocking) || (ERROR_OK != retval))
+		return retval;
 
+	buf[0] = 0x86;					/* command "set divisor" */
+	buf[1] = speed & 0xff;			/* valueL (0 = 6MHz, 1 = 3MHz, 2 = 2.0MHz, ...*/
+	buf[2] = (speed >> 8) & 0xff;	/* valueH */
+
 	LOG_DEBUG("%2.2x %2.2x %2.2x", buf[0], buf[1], buf[2]);
 	if (((retval = ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
 	{
@@ -484,32 +506,35 @@
 	return ERROR_OK;
 }
 
-
 static int ft2232_speed_div(int speed, int* khz)
 {
 	/* Take a look in the FT2232 manual,
 	 * AN2232C-01 Command Processor for
 	 * MPSSE and MCU Host Bus. Chapter 3.8 */
 
-	*khz = ft2232_max_tck / (1 + speed);
+	*khz = (RTCK_SPEED == speed) ? 0 : ft2232_max_tck / (1 + speed);
 
 	return ERROR_OK;
 }
 
-
 static int ft2232_khz(int khz, int* jtag_speed)
 {
 	if (khz == 0)
 	{
-#ifdef BUILD_FTD2XX_HIGHSPEED
-		*jtag_speed = 0;
-		return ERROR_OK;
-#else
-		LOG_DEBUG("RCLK not supported");
-		LOG_DEBUG("If you have a high-speed FTDI device, then "
-			"OpenOCD may be built with --enable-ftd2xx-highspeed.");
-		return ERROR_FAIL;
+		if (ft2232_device_is_highspeed())
+		{
+			*jtag_speed = RTCK_SPEED;
+			return ERROR_OK;
+		}
+		else
+		{
+			LOG_DEBUG("RCLK not supported");
+#ifndef BUILD_FT2232_HIGHSPEED
+			LOG_DEBUG("If you have a high-speed FTDI device, then "
+				"OpenOCD may be built with --enable-ft2232-highspeed.");
 #endif
+			return ERROR_FAIL;
+		}
 	}
 
 	/* Take a look in the FT2232 manual,
@@ -544,7 +569,6 @@
 	return ERROR_OK;
 }
 
-
 static int ft2232_register_commands(struct command_context_s* cmd_ctx)
 {
 	register_command(cmd_ctx, NULL, "ft2232_device_desc", ft2232_handle_device_desc_command,
@@ -560,7 +584,6 @@
 	return ERROR_OK;
 }
 
-
 static void ft2232_end_state(tap_state_t state)
 {
 	if (tap_is_state_stable(state))
@@ -595,11 +618,10 @@
 	buffer[cur_byte] = (buffer[cur_byte] | (((buffer_read()) << 1) & 0x80)) >> (8 - bits_left);
 }
 
-
 static void ft2232_debug_dump_buffer(void)
 {
-	int   i;
-	char  line[256];
+	int i;
+	char line[256];
 	char* line_p = line;
 
 	for (i = 0; i < ft2232_buffer_size; i++)
@@ -616,16 +638,15 @@
 		LOG_DEBUG("%s", line);
 }
 
-
 static int ft2232_send_and_recv(jtag_command_t* first, jtag_command_t* last)
 {
 	jtag_command_t* cmd;
-	uint8_t*             buffer;
-	int             scan_size;
+	uint8_t* buffer;
+	int scan_size;
 	enum scan_type  type;
-	int             retval;
-	uint32_t             bytes_written = 0;
-	uint32_t             bytes_read = 0;
+	int retval;
+	uint32_t bytes_written = 0;
+	uint32_t bytes_read = 0;
 
 #ifdef _DEBUG_USB_IO_
 	struct timeval  start, inter, inter2, end;
@@ -735,7 +756,6 @@
 	return retval;
 }
 
-
 /**
  * Function ft2232_add_pathmove
  * moves the TAP controller from the current state to a new state through the
@@ -777,7 +797,6 @@
 	tap_set_end_state(tap_get_state());
 }
 
-
 static void ft2232_add_scan(bool ir_scan, enum scan_type type, uint8_t* buffer, int scan_size)
 {
 	int num_bytes = (scan_size + 7) / 8;
@@ -936,7 +955,6 @@
 	}
 }
 
-
 static int ft2232_large_scan(scan_command_t* cmd, enum scan_type type, uint8_t* buffer, int scan_size)
 {
 	int num_bytes = (scan_size + 7) / 8;
@@ -1151,7 +1169,6 @@
 	return ERROR_OK;
 }
 
-
 static int ft2232_predict_scan_out(int scan_size, enum scan_type type)
 {
 	int predicted_size = 3;
@@ -1160,7 +1177,7 @@
 	if (tap_get_state() != TAP_DRSHIFT)
 		predicted_size += get_tms_buffer_requirements(tap_get_tms_path_len(tap_get_state(), TAP_DRSHIFT));
 
-	if (type == SCAN_IN)    /* only from device to host */
+	if (type == SCAN_IN)	/* only from device to host */
 	{
 		/* complete bytes */
 		predicted_size += CEIL(num_bytes, 65536) * 3;
@@ -1168,7 +1185,7 @@
 		/* remaining bits - 1 (up to 7) */
 		predicted_size += ((scan_size - 1) % 8) ? 2 : 0;
 	}
-	else                    /* host to device, or bidirectional */
+	else	/* host to device, or bidirectional */
 	{
 		/* complete bytes */
 		predicted_size += num_bytes + CEIL(num_bytes, 65536) * 3;
@@ -1180,7 +1197,6 @@
 	return predicted_size;
 }
 
-
 static int ft2232_predict_scan_in(int scan_size, enum scan_type type)
 {
 	int predicted_size = 0;
@@ -1202,38 +1218,37 @@
 	return predicted_size;
 }
 
-
 static void usbjtag_reset(int trst, int srst)
 {
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
 	if (trst == 1)
 	{
 		if (jtag_reset_config & RESET_TRST_OPEN_DRAIN)
-			low_direction |= nTRSTnOE;  /* switch to output pin (output is low) */
+			low_direction |= nTRSTnOE;	/* switch to output pin (output is low) */
 		else
-			low_output &= ~nTRST;       /* switch output low */
+			low_output &= ~nTRST;		/* switch output low */
 	}
 	else if (trst == 0)
 	{
 		if (jtag_reset_config & RESET_TRST_OPEN_DRAIN)
-			low_direction &= ~nTRSTnOE; /* switch to input pin (high-Z + internal and external pullup) */
+			low_direction &= ~nTRSTnOE;	/* switch to input pin (high-Z + internal and external pullup) */
 		else
-			low_output |= nTRST;        /* switch output high */
+			low_output |= nTRST;		/* switch output high */
 	}
 
 	if (srst == 1)
 	{
 		if (jtag_reset_config & RESET_SRST_PUSH_PULL)
-			low_output &= ~nSRST;       /* switch output low */
+			low_output &= ~nSRST;		/* switch output low */
 		else
-			low_direction |= nSRSTnOE;  /* switch to output pin (output is low) */
+			low_direction |= nSRSTnOE;	/* switch to output pin (output is low) */
 	}
 	else if (srst == 0)
 	{
 		if (jtag_reset_config & RESET_SRST_PUSH_PULL)
-			low_output |= nSRST;        /* switch output high */
+			low_output |= nSRST;		/* switch output high */
 		else
-			low_direction &= ~nSRSTnOE; /* switch to input pin (high-Z) */
+			low_direction &= ~nSRSTnOE;	/* switch to input pin (high-Z) */
 	}
 
 	/* command "set data bits low byte" */
@@ -1242,7 +1257,6 @@
 	buffer_write(low_direction);
 }
 
-
 static void jtagkey_reset(int trst, int srst)
 {
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
@@ -1284,7 +1298,6 @@
 			high_direction);
 }
 
-
 static void olimex_jtag_reset(int trst, int srst)
 {
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
@@ -1320,7 +1333,6 @@
 			high_direction);
 }
 
-
 static void axm0432_jtag_reset(int trst, int srst)
 {
 	if (trst == 1)
@@ -1350,7 +1362,6 @@
 			high_direction);
 }
 
-
 static void flyswatter_reset(int trst, int srst)
 {
 	if (trst == 1)
@@ -1378,7 +1389,6 @@
 	LOG_DEBUG("trst: %i, srst: %i, low_output: 0x%2.2x, low_direction: 0x%2.2x", trst, srst, low_output, low_direction);
 }
 
-
 static void turtle_reset(int trst, int srst)
 {
 	trst = trst;
@@ -1399,7 +1409,6 @@
 	LOG_DEBUG("srst: %i, low_output: 0x%2.2x, low_direction: 0x%2.2x", srst, low_output, low_direction);
 }
 
-
 static void comstick_reset(int trst, int srst)
 {
 	if (trst == 1)
@@ -1428,7 +1437,6 @@
 			high_direction);
 }
 
-
 static void stm32stick_reset(int trst, int srst)
 {
 	if (trst == 1)
@@ -1462,8 +1470,6 @@
 			high_direction);
 }
 
-
-
 static void sheevaplug_reset(int trst, int srst)
 {
 	if (trst == 1)
@@ -1485,8 +1491,8 @@
 
 static int ft2232_execute_runtest(jtag_command_t *cmd)
 {
-	int  retval;
-	int             i;
+	int retval;
+	int i;
 	int predicted_size = 0;
 	retval = ERROR_OK;
 
@@ -1549,7 +1555,6 @@
 	return retval;
 }
 
-
 static int ft2232_execute_statemove(jtag_command_t *cmd)
 {
 	int	predicted_size = 0;
@@ -1588,8 +1593,7 @@
 
 	DEBUG_JTAG_IO("pathmove: %i states, current: %s  end: %s", num_states,
 			tap_state_name(tap_get_state()),
-			tap_state_name(path[num_states-1])
-);
+			tap_state_name(path[num_states-1]));
 
 	/* only send the maximum buffer size that FT2232C can handle */
 	predicted_size = 3 * CEIL(num_states, 7);
@@ -1608,13 +1612,12 @@
 	return retval;
 }
 
-
 static int ft2232_execute_scan(jtag_command_t *cmd)
 {
-	uint8_t*             buffer;
-	int             scan_size;                  /* size of IR or DR scan */
-	int             predicted_size = 0;
-	int				retval = ERROR_OK;
+	uint8_t* buffer;
+	int scan_size;				/* size of IR or DR scan */
+	int predicted_size = 0;
+	int retval = ERROR_OK;
 
 	enum scan_type  type = jtag_scan_type(cmd->cmd.scan);
 
@@ -1667,8 +1670,8 @@
 
 static int ft2232_execute_reset(jtag_command_t *cmd)
 {
-	int             retval;
-	int             predicted_size = 0;
+	int retval;
+	int predicted_size = 0;
 	retval = ERROR_OK;
 
 	DEBUG_JTAG_IO("reset trst: %i srst %i",
@@ -1695,7 +1698,7 @@
 
 static int ft2232_execute_sleep(jtag_command_t *cmd)
 {
-	int             retval;
+	int retval;
 	retval = ERROR_OK;
 
 	DEBUG_JTAG_IO("sleep %i", cmd->cmd.sleep->us);
@@ -1713,7 +1716,7 @@
 
 static int ft2232_execute_stableclocks(jtag_command_t *cmd)
 {
-	int             retval;
+	int retval;
 	retval = ERROR_OK;
 
 	/* this is only allowed while in a stable state.  A check for a stable
@@ -1730,7 +1733,7 @@
 
 static int ft2232_execute_command(jtag_command_t *cmd)
 {
-	int             retval;
+	int retval;
 	retval = ERROR_OK;
 
 	switch (cmd->type)
@@ -1751,10 +1754,10 @@
 
 static int ft2232_execute_queue()
 {
-	jtag_command_t* cmd = jtag_command_queue;   /* currently processed command */
-	int             retval;
+	jtag_command_t* cmd = jtag_command_queue;	/* currently processed command */
+	int retval;
 
-	first_unsent = cmd;         /* next command that has to be sent */
+	first_unsent = cmd;		/* next command that has to be sent */
 	require_send = 0;
 
 	/* return ERROR_OK, unless ft2232_send_and_recv reports a failed check
@@ -1790,7 +1793,6 @@
 	return retval;
 }
 
-
 #if BUILD_FT2232_FTD2XX == 1
 static int ft2232_init_ftd2xx(uint16_t vid, uint16_t pid, int more, int* try_more)
 {
@@ -1838,18 +1840,18 @@
 
 	status = FT_OpenEx(openex_string, openex_flags, &ftdih);
 	if (status != FT_OK) {
-		// under Win32, the FTD2XX driver appends an "A" to the end
-		// of the description, if we tried by the desc, then
-		// try by the alternate "A" description.
+		/* under Win32, the FTD2XX driver appends an "A" to the end
+		 * of the description, if we tried by the desc, then
+		 * try by the alternate "A" description. */
 		if (openex_string == ft2232_device_desc) {
-			// Try the alternate method.
+			/* Try the alternate method. */
 			openex_string = ft2232_device_desc_A;
 			status = FT_OpenEx(openex_string, openex_flags, &ftdih);
 			if (status == FT_OK) {
-				// yea, the "alternate" method worked!
+				/* yea, the "alternate" method worked! */
 			} else {
-				// drat, give the user a meaningfull message.
-				// telling the use we tried *BOTH* methods.
+				/* drat, give the user a meaningfull message.
+				 * telling the use we tried *BOTH* methods. */
 				LOG_WARNING("Unable to open FTDI Device tried: '%s' and '%s'\n",
 							ft2232_device_desc,
 							ft2232_device_desc_A);
@@ -1935,24 +1937,20 @@
 	}
 	else
 	{
-		LOG_INFO("device: %lu", ftdi_device);
+		static const char* type_str[] =
+			{"BM", "AM", "100AX", "UNKNOWN", "2232C", "232R", "2232H", "4232H"};
+		unsigned no_of_known_types = sizeof(type_str) / sizeof(type_str[0]) - 1;
+		unsigned type_index = ((unsigned)ftdi_device < no_of_known_types)
+			? ftdi_device : 3;
+		LOG_INFO("device: %lu \"%s\"", ftdi_device, type_str[type_index]);
 		LOG_INFO("deviceID: %lu", deviceID);
 		LOG_INFO("SerialNumber: %s", SerialNumber);
 		LOG_INFO("Description: %s", Description);
-
-#ifdef BUILD_FTD2XX_HIGHSPEED
-		if (ft2232_device_is_highspeed())
-		{
-			ft2232_max_tck = FTDI_2232H_4232H_MAX_TCK;
-			LOG_INFO("max TCK change to: %u kHz", ft2232_max_tck);
-		}
-#endif
 	}
 
 	return ERROR_OK;
 }
 
-
 static int ft2232_purge_ftd2xx(void)
 {
 	FT_STATUS status;
@@ -1966,7 +1964,6 @@
 	return ERROR_OK;
 }
 
-
 #endif /* BUILD_FT2232_FTD2XX == 1 */
 
 #if BUILD_FT2232_LIBFTDI == 1
@@ -2024,10 +2021,16 @@
 
 	ftdi_set_bitmode(&ftdic, 0x0b, 2); /* ctx, JTAG I/O mask */
 
+	ftdi_device = ftdic.type;
+	static const char* type_str[] =
+		{"AM", "BM", "2232C", "R", "2232H", "4232H", "Unknown"};
+	unsigned no_of_known_types = sizeof(type_str) / sizeof(type_str[0]) - 1;
+	unsigned type_index = ((unsigned)ftdi_device < no_of_known_types)
+		? ftdi_device : no_of_known_types;
+	LOG_DEBUG("FTDI chip type: %i \"%s\"", (int)ftdi_device, type_str[type_index]);
 	return ERROR_OK;
 }
 
-
 static int ft2232_purge_libftdi(void)
 {
 	if (ftdi_usb_purge_buffers(&ftdic) < 0)
@@ -2039,7 +2042,6 @@
 	return ERROR_OK;
 }
 
-
 #endif /* BUILD_FT2232_LIBFTDI == 1 */
 
 static int ft2232_init(void)
@@ -2114,6 +2116,12 @@
 	if (layout->init() != ERROR_OK)
 		return ERROR_JTAG_INIT_FAILED;
 
+	if (ft2232_device_is_highspeed())
+	{
+		if (ft2232h_ft4232h_clk_divide_by_5(false) != ERROR_OK)
+			return ERROR_JTAG_INIT_FAILED;
+	}
+
 	ft2232_speed(jtag_get_speed());
 
 	buf[0] = 0x85; /* Disconnect TDI/DO to TDO/DI for Loopback */
@@ -2132,7 +2140,6 @@
 	return ERROR_OK;
 }
 
-
 static int usbjtag_init(void)
 {
 	uint8_t  buf[3];
@@ -2217,7 +2224,6 @@
 	return ERROR_OK;
 }
 
-
 static int axm0432_jtag_init(void)
 {
 	uint8_t  buf[3];
@@ -2288,7 +2294,6 @@
 	return ERROR_OK;
 }
 
-
 static int jtagkey_init(void)
 {
 	uint8_t  buf[3];
@@ -2371,7 +2376,6 @@
 	return ERROR_OK;
 }
 
-
 static int olimex_jtag_init(void)
 {
 	uint8_t  buf[3];
@@ -2439,7 +2443,6 @@
 	return ERROR_OK;
 }
 
-
 static int flyswatter_init(void)
 {
 	uint8_t  buf[3];
@@ -2486,7 +2489,6 @@
 	return ERROR_OK;
 }
 
-
 static int turtle_init(void)
 {
 	uint8_t  buf[3];
@@ -2527,7 +2529,6 @@
 	return ERROR_OK;
 }
 
-
 static int comstick_init(void)
 {
 	uint8_t  buf[3];
@@ -2571,7 +2572,6 @@
 	return ERROR_OK;
 }
 
-
 static int stm32stick_init(void)
 {
 	uint8_t  buf[3];
@@ -2615,7 +2615,6 @@
 	return ERROR_OK;
 }
 
-
 static int sheevaplug_init(void)
 {
 	uint8_t buf[3];
@@ -2731,7 +2730,6 @@
 	buffer_write(high_direction);
 }
 
-
 static void flyswatter_jtag_blink(void)
 {
 	/*
@@ -2744,7 +2742,6 @@
 	buffer_write(high_direction);
 }
 
-
 static void turtle_jtag_blink(void)
 {
 	/*
@@ -2764,7 +2761,6 @@
 	buffer_write(high_direction);
 }
 
-
 static int ft2232_quit(void)
 {
 #if BUILD_FT2232_FTD2XX == 1
@@ -2783,7 +2779,6 @@
 	return ERROR_OK;
 }
 
-
 static int ft2232_handle_device_desc_command(struct command_context_s* cmd_ctx, char* cmd, char** args, int argc)
 {
 	char *cp;
@@ -2792,20 +2787,20 @@
 	{
 		ft2232_device_desc = strdup(args[0]);
 		cp = strchr(ft2232_device_desc, 0);
-		// under Win32, the FTD2XX driver appends an "A" to the end
-		// of the description, this examines the given desc
-		// and creates the 'missing' _A or non_A variable.
+		/* under Win32, the FTD2XX driver appends an "A" to the end
+		 * of the description, this examines the given desc
+		 * and creates the 'missing' _A or non_A variable. */
 		if ((cp[-1] == 'A') && (cp[-2]==' ')) {
-			// it was, so make this the "A" version.
+			/* it was, so make this the "A" version. */
 			ft2232_device_desc_A = ft2232_device_desc;
-			// and *CREATE* the non-A version.
+			/* and *CREATE* the non-A version. */
 			strcpy(buf, ft2232_device_desc);
 			cp = strchr(buf, 0);
 			cp[-2] = 0;
 			ft2232_device_desc =  strdup(buf);
 		} else {
-			// <space > A not defined
-			// so create it
+			/* <space > A not defined
+			 * so create it */
 			sprintf(buf, "%s A", ft2232_device_desc);
 			ft2232_device_desc_A = strdup(buf);
 		}
@@ -2818,7 +2813,6 @@
 	return ERROR_OK;
 }
 
-
 static int ft2232_handle_serial_command(struct command_context_s* cmd_ctx, char* cmd, char** args, int argc)
 {
 	if (argc == 1)
@@ -2833,7 +2827,6 @@
 	return ERROR_OK;
 }
 
-
 static int ft2232_handle_layout_command(struct command_context_s* cmd_ctx, char* cmd, char** args, int argc)
 {
 	if (argc == 0)
@@ -2845,7 +2838,6 @@
 	return ERROR_OK;
 }
 
-
 static int ft2232_handle_vid_pid_command(struct command_context_s* cmd_ctx, char* cmd, char** args, int argc)
 {
 	if (argc > MAX_USB_IDS * 2)
@@ -2859,7 +2851,7 @@
 		LOG_WARNING("incomplete ft2232_vid_pid configuration directive");
 		if (argc < 2)
 			return ERROR_COMMAND_SYNTAX_ERROR;
-		// remove the incomplete trailing id
+		/* remove the incomplete trailing id */
 		argc -= 1;
 	}
 
@@ -2884,7 +2876,6 @@
 	return retval;
 }
 
-
 static int ft2232_handle_latency_command(struct command_context_s* cmd_ctx, char* cmd, char** args, int argc)
 {
 	if (argc == 1)
@@ -2899,7 +2890,6 @@
 	return ERROR_OK;
 }
 
-
 static int ft2232_stableclocks(int num_cycles, jtag_command_t* cmd)
 {
 	int retval = 0;
@@ -2942,7 +2932,6 @@
 	return retval;
 }
 
-
 /* ---------------------------------------------------------------------
  * Support for IceBear JTAG adapter from Section5:
  *	http://section5.ch/icebear

[Openocd-svn] r2590 - in trunk/src: helper jtag

[ntfreak at B. <nt...@ma...>]

Author: ntfreak
Date: 2009-08-18 14:14:01 +0200 (Tue, 18 Aug 2009)
New Revision: 2590

Modified:
   trunk/src/helper/startup.tcl
   trunk/src/jtag/core.c
   trunk/src/jtag/jtag.h
   trunk/src/jtag/tcl.c
Log:
Jonas Horberg [jho...@sa...]
Change jtag_rclk behaviour so it can be called before the interface init function

Modified: trunk/src/helper/startup.tcl
===================================================================
--- trunk/src/helper/startup.tcl	2009-08-18 10:27:24 UTC (rev 2589)
+++ trunk/src/helper/startup.tcl	2009-08-18 12:14:01 UTC (rev 2590)
@@ -134,15 +134,6 @@
 	reset halt
 }
 
-# If RCLK is not supported, use fallback_speed_khz
-proc jtag_rclk {fallback_speed_khz} {
-	if {[catch {jtag_khz 0}]!=0} {
-		jtag_khz $fallback_speed_khz
-	}
-}
-
-add_help_text jtag_rclk "fallback_speed_khz - set JTAG speed to RCLK or use fallback speed"
-
 proc ocd_process_reset { MODE } {
 
 	# If this target must be halted...

Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-08-18 10:27:24 UTC (rev 2589)
+++ trunk/src/jtag/core.c	2009-08-18 12:14:01 UTC (rev 2590)
@@ -101,8 +101,9 @@
 
 /* speed in kHz*/
 static int speed_khz = 0;
-/* flag if the kHz speed was defined */
-static bool hasKHz = false;
+/* speed to fallback to when RCLK is requested but not supported */
+static int rclk_fallback_speed_khz = 0;
+static enum {CLOCK_MODE_SPEED, CLOCK_MODE_KHZ, CLOCK_MODE_RCLK} clock_mode;
 static int jtag_speed = 0;
 
 static struct jtag_interface_s *jtag = NULL;
@@ -1140,16 +1141,34 @@
 		LOG_ERROR("JTAG interface has to be specified, see \"interface\" command");
 		return ERROR_JTAG_INVALID_INTERFACE;
 	}
-	if (hasKHz)
-	{
-		jtag_interface->khz(jtag_get_speed_khz(), &jtag_speed);
-		hasKHz = false;
-	}
 
+	jtag = jtag_interface;
 	if (jtag_interface->init() != ERROR_OK)
+	{
+		jtag = NULL;
 		return ERROR_JTAG_INIT_FAILED;
+	}
 
-	jtag = jtag_interface;
+	int requested_khz = jtag_get_speed_khz();
+	int actual_khz = requested_khz;
+	int retval = jtag_get_speed_readable(&actual_khz);
+	if (ERROR_OK != retval)
+		return retval;
+
+	if (actual_khz)
+	{
+		if ((CLOCK_MODE_RCLK == clock_mode)
+			|| ((CLOCK_MODE_KHZ == clock_mode) && !requested_khz))
+		{
+			LOG_INFO("RCLK (adaptive clock speed) not supported - fallback to %d kHz"
+				, actual_khz);
+		}
+		else
+			LOG_INFO("clock speed %d kHz", actual_khz);
+	}
+	else
+		LOG_INFO("RCLK (adaptive clock speed)");
+
 	return ERROR_OK;
 }
 
@@ -1255,20 +1274,15 @@
 	return jtag_init_reset(cmd_ctx);
 }
 
-void jtag_set_speed_khz(unsigned khz)
-{
-	speed_khz = khz;
-}
 unsigned jtag_get_speed_khz(void)
 {
 	return speed_khz;
 }
-int jtag_config_khz(unsigned khz)
+
+static int jtag_khz_to_speed(unsigned khz, int* speed)
 {
-	LOG_DEBUG("handle jtag khz");
-	jtag_set_speed_khz(khz);
-
-	int cur_speed = 0;
+	LOG_DEBUG("convert khz to interface specific speed value");
+	speed_khz = khz;
 	if (jtag != NULL)
 	{
 		LOG_DEBUG("have interface set up");
@@ -1276,34 +1290,85 @@
 		int retval = jtag->khz(jtag_get_speed_khz(), &speed_div1);
 		if (ERROR_OK != retval)
 		{
-			jtag_set_speed_khz(0);
 			return retval;
 		}
-		cur_speed = speed_div1;
+		*speed = speed_div1;
 	}
-	return jtag_set_speed(cur_speed);
+	return ERROR_OK;
 }
 
-int jtag_get_speed(void)
+static int jtag_rclk_to_speed(unsigned fallback_speed_khz, int* speed)
 {
-	return jtag_speed;
+	int retval = jtag_khz_to_speed(0, speed);
+	if ((ERROR_OK != retval) && fallback_speed_khz)
+	{
+		LOG_DEBUG("trying fallback speed...");
+		retval = jtag_khz_to_speed(fallback_speed_khz, speed);
+	}
+	return retval;
 }
 
-int jtag_set_speed(int speed)
+static int jtag_set_speed(int speed)
 {
 	jtag_speed = speed;
 	/* this command can be called during CONFIG,
 	 * in which case jtag isn't initialized */
-	hasKHz = !jtag;
 	return jtag ? jtag->speed(speed) : ERROR_OK;
 }
 
-int jtag_get_speed_readable(int *speed)
+int jtag_config_speed(int speed)
 {
-	return jtag ? jtag->speed_div(jtag_get_speed(), speed) : ERROR_OK;
+	LOG_DEBUG("handle jtag speed");
+	clock_mode = CLOCK_MODE_SPEED;
+	return jtag_set_speed(speed);
 }
 
+int jtag_config_khz(unsigned khz)
+{
+	LOG_DEBUG("handle jtag khz");
+	clock_mode = CLOCK_MODE_KHZ;
+	int speed = 0;
+	int retval = jtag_khz_to_speed(khz, &speed);
+	return (ERROR_OK != retval) ? retval : jtag_set_speed(speed);
+}
 
+int jtag_config_rclk(unsigned fallback_speed_khz)
+{
+	LOG_DEBUG("handle jtag rclk");
+	clock_mode = CLOCK_MODE_RCLK;
+	rclk_fallback_speed_khz = fallback_speed_khz;
+	int speed = 0;
+	int retval = jtag_rclk_to_speed(fallback_speed_khz, &speed);
+	return (ERROR_OK != retval) ? retval : jtag_set_speed(speed);
+}
+
+int jtag_get_speed(void)
+{
+	int speed;
+	switch(clock_mode)
+	{
+		case CLOCK_MODE_SPEED:
+			speed = jtag_speed;
+			break;
+		case CLOCK_MODE_KHZ:
+			jtag_khz_to_speed(jtag_get_speed_khz(), &speed);
+			break;
+		case CLOCK_MODE_RCLK:
+			jtag_rclk_to_speed(rclk_fallback_speed_khz, &speed);
+			break;
+		default:
+			LOG_ERROR("BUG: unknown jtag clock mode");
+			speed = 0;
+			break;
+	}
+	return speed;
+}
+
+int jtag_get_speed_readable(int *khz)
+{
+	return jtag ? jtag->speed_div(jtag_get_speed(), khz) : ERROR_OK;
+}
+
 void jtag_set_verify(bool enable)
 {
 	jtag_verify = enable;

Modified: trunk/src/jtag/jtag.h
===================================================================
--- trunk/src/jtag/jtag.h	2009-08-18 10:27:24 UTC (rev 2589)
+++ trunk/src/jtag/jtag.h	2009-08-18 12:14:01 UTC (rev 2590)
@@ -252,13 +252,16 @@
  * @returns ERROR_OK during configuration or on success, or an error
  *   code returned from the interface @c speed callback.
  */
-int jtag_set_speed(int speed);
+int jtag_config_speed(int speed);
 
 
 /// Attempt to configure the interface for the specified KHz.
 int jtag_config_khz(unsigned khz);
-/// Set the clock speed of the JTAG interface in KHz.
-void jtag_set_speed_khz(unsigned speed);
+/**
+ * Attempt to enable RTCK/RCLK. If that fails, fallback to the
+ * specified frequency.
+ */
+int jtag_config_rclk(unsigned fallback_speed_khz);
 /// Retreives the clock speed of the JTAG interface in KHz.
 unsigned jtag_get_speed_khz(void);
 

Modified: trunk/src/jtag/tcl.c
===================================================================
--- trunk/src/jtag/tcl.c	2009-08-18 10:27:24 UTC (rev 2589)
+++ trunk/src/jtag/tcl.c	2009-08-18 12:14:01 UTC (rev 2590)
@@ -55,6 +55,7 @@
 static int handle_interface_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 static int handle_jtag_speed_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 static int handle_jtag_khz_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+static int handle_jtag_rclk_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 static int handle_jtag_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 static int handle_reset_config_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 static int handle_jtag_nsrst_delay_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
@@ -577,6 +578,8 @@
 	register_command(cmd_ctx, NULL, "jtag_khz", handle_jtag_khz_command,
 		COMMAND_ANY, "set maximum jtag speed (if supported); "
 		"parameter is maximum khz, or 0 for adaptive clocking (RTCK).");
+	register_command(cmd_ctx, NULL, "jtag_rclk", handle_jtag_rclk_command,
+		COMMAND_ANY, "fallback_speed_khz - set JTAG speed to RCLK or use fallback speed");
 	register_command(cmd_ctx, NULL, "jtag_device", handle_jtag_device_command,
 		COMMAND_CONFIG, "(DEPRECATED) jtag_device <ir_length> <ir_expected> <ir_mask>");
 	register_command(cmd_ctx, NULL, "reset_config", handle_reset_config_command,
@@ -955,7 +958,7 @@
 		int retval = parse_uint(args[0], &cur_speed);
 		if (ERROR_OK != retval)
 			return retval;
-		retval = jtag_set_speed(cur_speed);
+		retval = jtag_config_speed(cur_speed);
 
 	}
 	command_print(cmd_ctx, "jtag_speed: %d", jtag_get_speed());
@@ -993,6 +996,36 @@
 	return retval;
 }
 
+static int handle_jtag_rclk_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+	if (argc > 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	int retval = ERROR_OK;
+	if (argc == 1)
+	{
+		unsigned khz = 0;
+		int retval = parse_uint(args[0], &khz);
+		if (ERROR_OK != retval)
+			return retval;
+		retval = jtag_config_rclk(khz);
+		if (ERROR_OK != retval)
+			return retval;
+	}
+
+	int cur_khz = jtag_get_speed_khz();
+	retval = jtag_get_speed_readable(&cur_khz);
+	if (ERROR_OK != retval)
+		return retval;
+
+	if (cur_khz)
+		command_print(cmd_ctx, "RCLK not supported - fallback to %d kHz", cur_khz);
+	else
+		command_print(cmd_ctx, "RCLK - adaptive");
+
+	return retval;
+}
+
 static int handle_jtag_reset_command(struct command_context_s *cmd_ctx,
 		char *cmd, char **args, int argc)
 {