openocd-commit — OpenOCD commit maling list - read only

[Openocd-svn] r2639 - trunk

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-26 21:27:33 +0200 (Wed, 26 Aug 2009)
New Revision: 2639

Modified:
   trunk/TODO
Log:
some arm11 stuff that isn't done yet.

Modified: trunk/TODO
===================================================================
--- trunk/TODO	2009-08-26 19:25:44 UTC (rev 2638)
+++ trunk/TODO	2009-08-26 19:27:33 UTC (rev 2639)
@@ -122,6 +122,8 @@
   arm7 code) to know what address to set the breakpoint at for single
   stepping an instruction.
   - implement missing functionality (grep FNC_INFO_NOTIMPLEMENTED ...)
+  - thumb support is missing: ISTR ARMv6 requires Thumb.
+  ARM1156 has Thumb2; ARM1136 doesn't.
 - Cortex A8 support (ML)
   - add target implementation (ML)
 - MC1322x support (JW/DE?)

[Openocd-svn] r2638 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-26 21:25:44 +0200 (Wed, 26 Aug 2009)
New Revision: 2638

Modified:
   trunk/src/target/cortex_a8.c
Log:
Matt Hsu <ma...@0x...> and Holger Hans Peter Freyther <ze...@se...>  cortex-a8: Wait for the CPU to be halted/started

With DCCR we are asking the CPU to halt, we should wait until
the CPU has halted before proceeding with the operation.

Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-08-26 19:24:45 UTC (rev 2637)
+++ trunk/src/target/cortex_a8.c	2009-08-26 19:25:44 UTC (rev 2638)
@@ -413,6 +413,8 @@
 int cortex_a8_halt(target_t *target)
 {
 	int retval = ERROR_OK;
+	uint32_t dscr;
+
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	armv7a_common_t *armv7a = armv4_5->arch_info;
@@ -421,13 +423,25 @@
 	uint8_t saved_apsel = dap_ap_get_select(swjdp);
 	dap_ap_select(swjdp, swjdp_debugap);
 
-	/* Perhaps we should do a read-modify-write here */
+	/*
+	 * Tell the core to be halted by writing DRCR with 0x1
+	 * and then wait for the core to be halted.
+	 */
 	retval = mem_ap_write_atomic_u32(swjdp,
 			OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x1);
 
+	if (retval != ERROR_OK)
+		goto out;
+
+	do {
+		mem_ap_read_atomic_u32(swjdp,
+			OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+	} while ((dscr & (1 << 0)) == 0);
+
 	target->debug_reason = DBG_REASON_DBGRQ;
+
+out:
 	dap_ap_select(swjdp, saved_apsel);
-
 	return retval;
 }
 
@@ -441,7 +455,7 @@
 	swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
 //	breakpoint_t *breakpoint = NULL;
-	uint32_t resume_pc;
+	uint32_t resume_pc, dscr;
 
 	uint8_t saved_apsel = dap_ap_get_select(swjdp);
 	dap_ap_select(swjdp, swjdp_debugap);
@@ -515,10 +529,14 @@
 	}
 
 #endif
-	/* Restart core */
-	/* Perhaps we should do a read-modify-write here */
+	/* Restart core and wait for it to be started */
 	mem_ap_write_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x2);
 
+	do {
+		mem_ap_read_atomic_u32(swjdp,
+			OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+	} while ((dscr & (1 << 1)) == 0);
+
 	target->debug_reason = DBG_REASON_NOTHALTED;
 	target->state = TARGET_RUNNING;
 

[Openocd-svn] r2637 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-26 21:24:45 +0200 (Wed, 26 Aug 2009)
New Revision: 2637

Modified:
   trunk/src/target/armv7a.h
Log:
Matt Hsu <ma...@0x...> and Holger Hans Peter Freyther <ze...@se...>  Print the value that the method didn't like

Modified: trunk/src/target/armv7a.h
===================================================================
--- trunk/src/target/armv7a.h	2009-08-26 19:23:35 UTC (rev 2636)
+++ trunk/src/target/armv7a.h	2009-08-26 19:24:45 UTC (rev 2637)
@@ -148,7 +148,7 @@
 		case ARMV7A_MODE_MON: return 7; break;
 		case ARMV7A_MODE_ANY: return 0; break;	/* map MODE_ANY to user mode */
 		default:
-			LOG_ERROR("invalid mode value encountered");
+			LOG_ERROR("invalid mode value encountered, val %d", mode);
 			return -1;
 	}
 }

[Openocd-svn] r2636 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-26 21:23:35 +0200 (Wed, 26 Aug 2009)
New Revision: 2636

Modified:
   trunk/src/target/cortex_a8.c
Log:
Matt Hsu <ma...@0x...> and Holger Hans Peter Freyther <ze...@se...> Only dap_ap_select when we are going to do a memory access
in the fast reg case.

Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-08-26 19:22:28 UTC (rev 2635)
+++ trunk/src/target/cortex_a8.c	2009-08-26 19:23:35 UTC (rev 2636)
@@ -589,7 +589,6 @@
 	}
 
 	/* Examine target state and mode */
-	dap_ap_select(swjdp, swjdp_memoryap);
 	if (cortex_a8->fast_reg_read)
 		target_alloc_working_area(target, 64, &regfile_working_area);
 
@@ -602,6 +601,7 @@
 	}
 	else
 	{
+		dap_ap_select(swjdp, swjdp_memoryap);
 		cortex_a8_read_regs_through_mem(target,
 				regfile_working_area->address, regfile);
 		dap_ap_select(swjdp, swjdp_memoryap);

[Openocd-svn] r2635 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-26 21:22:28 +0200 (Wed, 26 Aug 2009)
New Revision: 2635

Modified:
   trunk/src/target/cortex_a8.h
Log:
Matt Hsu <ma...@0x...> cortex-a8: Copy some more registers from the documentation

Modified: trunk/src/target/cortex_a8.h
===================================================================
--- trunk/src/target/cortex_a8.h	2009-08-26 19:21:26 UTC (rev 2634)
+++ trunk/src/target/cortex_a8.h	2009-08-26 19:22:28 UTC (rev 2635)
@@ -42,6 +42,7 @@
 /* Debug Control Block */
 #define CPUDBG_DIDR		0x000
 #define CPUDBG_WFAR		0x018
+#define CPUDBG_VCR	0x01C
 #define CPUDBG_DSCCR	0x028
 #define CPUDBG_DTRRX	0x080
 #define CPUDBG_ITR	0x084
@@ -52,6 +53,13 @@
 #define CPUDBG_BCR_BASE	0x140
 #define CPUDBG_WVR_BASE	0x180
 
+#define CPUDBG_OSLAR	0x300
+#define CPUDBG_OSLSR	0x304
+#define CPUDBG_OSSRR	0x308
+
+#define CPUDBG_PRCR	0x310
+#define CPUDBG_PRSR	0x314
+
 #define CPUDBG_CPUID	0xD00
 #define CPUDBG_CTYPR	0xD04
 #define CPUDBG_TTYPR	0xD0C

[Openocd-svn] r2634 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-26 21:21:26 +0200 (Wed, 26 Aug 2009)
New Revision: 2634

Modified:
   trunk/src/target/cortex_a8.c
Log:
Matt Hsu <ma...@0x...> cortex_a8_exec_opcode is writing the ARM instruction into
the ITR register but it will only be executed when the DSCR[13]
bit is set. The documentation is a bit weird as it classifies
the DSCR as read-only but the pseudo code is writing to it as
well. This is working on a beagleboard.

Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-08-26 19:20:25 UTC (rev 2633)
+++ trunk/src/target/cortex_a8.c	2009-08-26 19:21:26 UTC (rev 2634)
@@ -546,7 +546,7 @@
 int cortex_a8_debug_entry(target_t *target)
 {
 	int i;
-	uint32_t regfile[16], pc, cpsr;
+	uint32_t regfile[16], pc, cpsr, dscr;
 	int retval = ERROR_OK;
 	working_area_t *regfile_working_area = NULL;
 
@@ -561,6 +561,14 @@
 
 	LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
+	/* Enable the ITR execution once we are in debug mode */
+	mem_ap_read_atomic_u32(swjdp,
+				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+	dscr |= (1 << 13);
+	retval = mem_ap_write_atomic_u32(swjdp,
+			OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
+
+
 	/* Examine debug reason */
 	switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
 	{

[Openocd-svn] r2633 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-26 21:20:25 +0200 (Wed, 26 Aug 2009)
New Revision: 2633

Modified:
   trunk/src/target/cortex_a8.c
Log:
Matt Hsu <ma...@0x...> Wait for the DTRRX to be full before reading it. Remove the trans_mode change as it is done in the mem_ap_read_atomic_u32 function.

Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-08-26 19:16:08 UTC (rev 2632)
+++ trunk/src/target/cortex_a8.c	2009-08-26 19:20:25 UTC (rev 2633)
@@ -259,14 +259,13 @@
 {
 	int retval = ERROR_OK;
 	uint8_t reg = regnum&0xFF;
+	uint32_t dscr;
 
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	armv7a_common_t *armv7a = armv4_5->arch_info;
 	swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
-	swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
 	if (reg > 16)
 		return retval;
 
@@ -286,10 +285,16 @@
 		cortex_a8_exec_opcode(target, ARMV4_5_MCR(14, 0, 0, 0, 5, 0));
 	}
 
-	/* Read DCCTX */
+	/* Read DTRRTX */
+	do
+	{
+		retval = mem_ap_read_atomic_u32(swjdp,
+				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+	}
+	while ((dscr & (1 << 29)) == 0); /* Wait for DTRRXfull */
+
 	retval = mem_ap_read_atomic_u32(swjdp,
 			OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
-//	retval = mem_ap_read_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
 
 	return retval;
 }

[Openocd-svn] r2632 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-26 21:16:08 +0200 (Wed, 26 Aug 2009)
New Revision: 2632

Modified:
   trunk/src/target/cortex_a8.c
Log:
Matt Hsu <ma...@0x...> and Holger Hans Peter Freyther <ze...@se...> Before executing a new instruction wait for the previous
instruction to be finished. This comes from the pseudo code
of the cortex a8 trm.


Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-08-26 19:06:56 UTC (rev 2631)
+++ trunk/src/target/cortex_a8.c	2009-08-26 19:16:08 UTC (rev 2632)
@@ -161,7 +161,15 @@
 	swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
 	LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
+	do
+	{
+		retvalue = mem_ap_read_atomic_u32(swjdp,
+				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+	}
+	while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+
 	mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
+
 	do
 	{
 		retvalue = mem_ap_read_atomic_u32(swjdp,

[Openocd-svn] r2631 - trunk/src/jtag

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-26 21:06:56 +0200 (Wed, 26 Aug 2009)
New Revision: 2631

Modified:
   trunk/src/jtag/core.c
Log:
David Brownell <da...@pa...> Fix segv in jtag_examine_chain(): exit loop on no-tap.  Keep
"next iteration" step with the rest of the loop overhead.

Cleanup:  remove spurious whitespace, and an overlong line;
only assign "tap->hasidcode" once.

Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-08-26 10:13:51 UTC (rev 2630)
+++ trunk/src/jtag/core.c	2009-08-26 19:06:56 UTC (rev 2631)
@@ -975,10 +975,12 @@
 		return ERROR_JTAG_INIT_FAILED;
 	}
 
-	for (unsigned bit_count = 0; bit_count < (JTAG_MAX_CHAIN_SIZE * 32) - 31;)
+	for (unsigned bit_count = 0;
+			tap && bit_count < (JTAG_MAX_CHAIN_SIZE * 32) - 31;
+			tap = jtag_tap_next_enabled(tap))
 	{
 		uint32_t idcode = buf_get_u32(idcode_buffer, bit_count, 32);
-		tap->hasidcode = true;
+
 		if ((idcode & 1) == 0)
 		{
 			/* LSB must not be 0, this indicates a device in bypass */
@@ -990,7 +992,9 @@
 		}
 		else
 		{
-	 		/*
+			tap->hasidcode = true;
+
+			/*
 			 * End of chain (invalid manufacturer ID) some devices, such
 			 * as AVR will output all 1's instead of TDI input value at
 			 * end of chain.
@@ -1015,10 +1019,8 @@
 		tap->idcode = idcode;
 
 		// ensure the TAP ID does matches what was expected
- 		if (!jtag_examine_chain_match_tap(tap))
+		if (!jtag_examine_chain_match_tap(tap))
 			return ERROR_JTAG_INIT_FAILED;
-
-		tap = jtag_tap_next_enabled(tap);
 	}
 
 	/* see if number of discovered devices matches configuration */

[Openocd-svn] r2630 - trunk/src/jtag

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-26 12:13:51 +0200 (Wed, 26 Aug 2009)
New Revision: 2630

Modified:
   trunk/src/jtag/core.c
Log:
added missing check on jtag_execute

Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-08-26 10:03:54 UTC (rev 2629)
+++ trunk/src/jtag/core.c	2009-08-26 10:13:51 UTC (rev 2630)
@@ -1064,7 +1064,10 @@
 
 
 	jtag_add_plain_ir_scan(1, &field, TAP_RESET);
-	jtag_execute_queue();
+	int retval;
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 
 	tap = NULL;
 	chain_pos = 0;

[Openocd-svn] r2629 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-26 12:03:54 +0200 (Wed, 26 Aug 2009)
New Revision: 2629

Modified:
   trunk/src/target/arm7_9_common.c
Log:
Remove bogus "BUG:". If the PC is pointing to an invalid instruction, then simulation will fail. This is expected.

Modified: trunk/src/target/arm7_9_common.c
===================================================================
--- trunk/src/target/arm7_9_common.c	2009-08-26 08:32:03 UTC (rev 2628)
+++ trunk/src/target/arm7_9_common.c	2009-08-26 10:03:54 UTC (rev 2629)
@@ -1833,7 +1833,7 @@
 			{
 				uint32_t current_opcode;
 				target_read_u32(target, current_pc, &current_opcode);
-				LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
+				LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
 				return retval;
 			}
 
@@ -2038,7 +2038,7 @@
 	{
 		uint32_t current_opcode;
 		target_read_u32(target, current_pc, &current_opcode);
-		LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
+		LOG_ERROR("Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
 		return retval;
 	}
 

[Openocd-svn] r2628 - in trunk: . src/jtag

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-26 10:32:03 +0200 (Wed, 26 Aug 2009)
New Revision: 2628

Modified:
   trunk/TODO
   trunk/src/jtag/core.c
   trunk/src/jtag/jtag.h
Log:
reduce arm11 output noise

Modified: trunk/TODO
===================================================================
--- trunk/TODO	2009-08-26 07:11:16 UTC (rev 2627)
+++ trunk/TODO	2009-08-26 08:32:03 UTC (rev 2628)
@@ -117,7 +117,10 @@
 - ARM923EJS:
   - reset run/halt/step is not robust; needs testing to map out problems.
 - ARM11 improvements (MB?)
-  - fix single stepping  (reported by ØH)
+  - fix single stepping  (reported by ØH). Michael Bruck explained
+  that what's required is to emulate the current instruction(just like the
+  arm7 code) to know what address to set the breakpoint at for single
+  stepping an instruction.
   - implement missing functionality (grep FNC_INFO_NOTIMPLEMENTED ...)
 - Cortex A8 support (ML)
   - add target implementation (ML)

Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-08-26 07:11:16 UTC (rev 2627)
+++ trunk/src/jtag/core.c	2009-08-26 08:32:03 UTC (rev 2628)
@@ -939,7 +939,7 @@
 	/* If none of the expected ids matched, log an error */
 	if (ii != tap->expected_ids_cnt)
 	{
-		LOG_INFO("JTAG Tap/device matched");
+		LOG_DEBUG("JTAG Tap/device matched");
 		return true;
 	}
 	jtag_examine_chain_display(LOG_LVL_ERROR, "got",
@@ -978,11 +978,13 @@
 	for (unsigned bit_count = 0; bit_count < (JTAG_MAX_CHAIN_SIZE * 32) - 31;)
 	{
 		uint32_t idcode = buf_get_u32(idcode_buffer, bit_count, 32);
+		tap->hasidcode = true;
 		if ((idcode & 1) == 0)
 		{
 			/* LSB must not be 0, this indicates a device in bypass */
 			LOG_WARNING("Tap/Device does not have IDCODE");
 			idcode = 0;
+			tap->hasidcode = false;
 
 			bit_count += 1;
 		}
@@ -1074,7 +1076,8 @@
 		}
 
 		val = buf_get_u32(ir_test, chain_pos, 2);
-		if (val != 0x1)
+		/* Only fail this check if we have IDCODE for this device */
+		if ((val != 0x1)&&(tap->hasidcode))
 		{
 			char *cbuf = buf_to_str(ir_test, total_ir_length, 16);
 			LOG_ERROR("Could not validate JTAG scan chain, IR mismatch, scan returned 0x%s. tap=%s pos=%d expected 0x1 got %0x", cbuf, jtag_tap_name(tap), chain_pos, val);

Modified: trunk/src/jtag/jtag.h
===================================================================
--- trunk/src/jtag/jtag.h	2009-08-26 07:11:16 UTC (rev 2627)
+++ trunk/src/jtag/jtag.h	2009-08-26 08:32:03 UTC (rev 2628)
@@ -144,7 +144,7 @@
 
 /* this is really: typedef jtag_tap_t */
 /* But - the typedef is done in "types.h" */
-/* due to "forward decloration reasons" */
+/* due to "forward declaration reasons" */
 struct jtag_tap_s
 {
 	const char* chip;
@@ -161,6 +161,7 @@
 	uint32_t ir_capture_mask;
 	uint8_t* expected_mask; /**< Capture-IR expected mask */
 	uint32_t idcode;
+	bool hasidcode; /* not all devices have idcode, we'll discover this during chain examination */
 	/**< device identification code */
 
 	/// Array of expected identification codes */

[Openocd-svn] r2627 - trunk

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-26 09:11:16 +0200 (Wed, 26 Aug 2009)
New Revision: 2627

Modified:
   trunk/NEWS
Log:
Michael Schwingen <rin...@di...> news about xscale

Modified: trunk/NEWS
===================================================================
--- trunk/NEWS	2009-08-26 06:26:29 UTC (rev 2626)
+++ trunk/NEWS	2009-08-26 07:11:16 UTC (rev 2627)
@@ -12,6 +12,7 @@
 	"cortex_m3 vector_catch" ... traps certain hardware faults
 		without tying up breakpoint resources
     If you're willing to help debug it:  VERY EARLY Cortex-A8 support
+    New commands for use with XScale processors: "xscale vector_table" 
 
 Flash Layer:
     The lpc2000 driver handles the new NXP LPC1700 (Cortex-M3) chips

[Openocd-svn] r2626 - trunk/src/flash

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-26 08:26:29 +0200 (Wed, 26 Aug 2009)
New Revision: 2626

Modified:
   trunk/src/flash/stellaris.c
   trunk/src/flash/stellaris.h
Log:
David Brownell <da...@pa...> Clock updates/fixes for the Stellaris flash driver:

 - Bugfixes:
   * internal osc: it's *12* MHz (not 15 MHz) on _current_ chips
      + except new Tempest parts where it's 16 MHz (and calibrated!)
      + or some old Sandstorm ones, where 15 MHz was valid
   * crystal config:
      + read and use the crystal config, don't assume 6 MHz
      + know when that field is 4 bits vs 5
   * an RCC2 register may be overriding the original RCC
      + more clock source options
      + bigger dividers
      + fractional dividers on Tempest (NYET handled)
   * there's a 30 KHz osc on newer chips (for deep sleep)
   * there's a 32768 Hz osc on newer chips (for hibernation)

 - Cosmetic
   * say "rev A0" not "vA.0", to match vendor docs
   * don't always report master clock as an "estimate":
      + give the error bound if it's approximate, like "?\194?\17730%"
      + else don't say anything
   * fix whitespace and caps in some messages
   * these are not AT91SAM chips!!

Those clock issues might explain problems sometimes reported when
writing to Stellaris flash banks; they affect write timings.

That 12-vs-15 MHz issue is problematic; there's no consolidated doc
showing which chips (and revs!) have which internal oscillator speed.
It's clear that only older silicon had the faster-and-less-accurate
flavor.  What's less clear is which chips are "old" like that.

Lightly tested, on a DustDevil part.

Modified: trunk/src/flash/stellaris.c
===================================================================
--- trunk/src/flash/stellaris.c	2009-08-25 20:03:35 UTC (rev 2625)
+++ trunk/src/flash/stellaris.c	2009-08-26 06:26:29 UTC (rev 2626)
@@ -257,7 +257,10 @@
 	/* part wasn't probed for info yet */
 	stellaris_info->did1 = 0;
 
-	/* TODO Use an optional main oscillator clock rate in kHz from arg[6] */
+	/* TODO Specify the main crystal speed in kHz using an optional
+	 * argument; ditto, the speed of an external oscillator used
+	 * instead of a crystal.  Avoid programming flash using IOSC.
+	 */
 	return ERROR_OK;
 }
 
@@ -294,7 +297,8 @@
 	}
 	printed = snprintf(buf,
 			   buf_size,
-			   "\nLMI Stellaris information: Chip is class %i(%s) %s v%c.%i\n",
+			   "\nTI/LMI Stellaris information: Chip is "
+			   "class %i (%s) %s rev %c%i\n",
 			   device_class,
 			   StellarisClassname[device_class],
 			   stellaris_info->target_name,
@@ -305,10 +309,11 @@
 
 	printed = snprintf(buf,
 			   buf_size,
-			   "did1: 0x%8.8" PRIx32 ", arch: 0x%4.4" PRIx32 ", eproc: %s, ramsize:%ik, flashsize: %ik\n",
+			   "did1: 0x%8.8" PRIx32 ", arch: 0x%4.4" PRIx32
+			   ", eproc: %s, ramsize: %ik, flashsize: %ik\n",
 			   stellaris_info->did1,
 			   stellaris_info->did1,
-			   "ARMV7M",
+			   "ARMv7M",
 			   (int)((1 + ((stellaris_info->dc0 >> 16) & 0xFFFF))/4),
 			   (int)((1 + (stellaris_info->dc0 & 0xFFFF))*2));
 	buf += printed;
@@ -316,9 +321,12 @@
 
 	printed = snprintf(buf,
 			   buf_size,
-			   "master clock(estimated): %ikHz, rcc is 0x%" PRIx32 " \n",
+			   "master clock: %ikHz%s, "
+			   "rcc is 0x%" PRIx32 ", rcc2 is 0x%" PRIx32 "\n",
 			   (int)(stellaris_info->mck_freq / 1000),
-			   stellaris_info->rcc);
+			   stellaris_info->mck_desc,
+			   stellaris_info->rcc,
+			   stellaris_info->rcc2);
 	buf += printed;
 	buf_size -= printed;
 
@@ -353,47 +361,115 @@
 
 /** Read clock configuration and set stellaris_info->usec_clocks*/
 
+static const unsigned rcc_xtal[32] = {
+	[0x00] = 1000000,		/* no pll */
+	[0x01] = 1843200,		/* no pll */
+	[0x02] = 2000000,		/* no pll */
+	[0x03] = 2457600,		/* no pll */
+
+	[0x04] = 3579545,
+	[0x05] = 3686400,
+	[0x06] = 4000000,		/* usb */
+	[0x07] = 4096000,
+
+	[0x08] = 4915200,
+	[0x09] = 5000000,		/* usb */
+	[0x0a] = 5120000,
+	[0x0b] = 6000000,		/* (reset) usb */
+
+	[0x0c] = 6144000,
+	[0x0d] = 7372800,
+	[0x0e] = 8000000,		/* usb */
+	[0x0f] = 8192000,
+
+	/* parts before DustDevil use just 4 bits for xtal spec */
+
+	[0x10] = 10000000,		/* usb */
+	[0x11] = 12000000,		/* usb */
+	[0x12] = 12288000,
+	[0x13] = 13560000,
+
+	[0x14] = 14318180,
+	[0x15] = 16000000,		/* usb */
+	[0x16] = 16384000,
+};
+
 static void stellaris_read_clock_info(flash_bank_t *bank)
 {
 	stellaris_flash_bank_t *stellaris_info = bank->driver_priv;
 	target_t *target = bank->target;
-	uint32_t rcc, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;
+	uint32_t rcc, rcc2, pllcfg, sysdiv, usesysdiv, bypass, oscsrc;
+	unsigned xtal;
 	unsigned long mainfreq;
 
 	target_read_u32(target, SCB_BASE | RCC, &rcc);
 	LOG_DEBUG("Stellaris RCC %" PRIx32 "", rcc);
+
+	target_read_u32(target, SCB_BASE | RCC2, &rcc2);
+	LOG_DEBUG("Stellaris RCC2 %" PRIx32 "", rcc);
+
 	target_read_u32(target, SCB_BASE | PLLCFG, &pllcfg);
 	LOG_DEBUG("Stellaris PLLCFG %" PRIx32 "", pllcfg);
+
 	stellaris_info->rcc = rcc;
+	stellaris_info->rcc = rcc2;
 
 	sysdiv = (rcc >> 23) & 0xF;
 	usesysdiv = (rcc >> 22) & 0x1;
 	bypass = (rcc >> 11) & 0x1;
 	oscsrc = (rcc >> 4) & 0x3;
-	/* xtal = (rcc >> 6)&0xF; */
+	xtal = (rcc >> 6) & stellaris_info->xtal_mask;
+
+	/* NOTE: post-Sandstorm parts have RCC2 which may override
+	 * parts of RCC ... with more sysdiv options, option for
+	 * 32768 Hz mainfreq, PLL controls.  On Sandstorm it reads
+	 * as zero, so the "use RCC2" flag is always clear.
+	 */
+	if (rcc2 & (1 << 31)) {
+		sysdiv = (rcc2 >> 23) & 0x3F;
+		bypass = (rcc2 >> 11) & 0x1;
+		oscsrc = (rcc2 >> 4) & 0x7;
+
+		/* FIXME Tempest parts have an additional lsb for
+		 * fractional sysdiv (200 MHz / 2.5 == 80 MHz)
+		 */
+	}
+
+	stellaris_info->mck_desc = "";
+
 	switch (oscsrc)
 	{
-		case 0:
-			mainfreq = 6000000;  /* Default xtal */
+		case 0:				/* MOSC */
+			mainfreq = rcc_xtal[xtal];
 			break;
-		case 1:
-			mainfreq = 22500000; /* Internal osc. 15 MHz +- 50% */
+		case 1:				/* IOSC */
+			mainfreq = stellaris_info->iosc_freq;
+			stellaris_info->mck_desc = stellaris_info->iosc_desc;
 			break;
-		case 2:
-			mainfreq = 5625000;  /* Internal osc. / 4 */
+		case 2:				/* IOSC/4 */
+			mainfreq = stellaris_info->iosc_freq / 4;
+			stellaris_info->mck_desc = stellaris_info->iosc_desc;
 			break;
-		case 3:
-			LOG_WARNING("Invalid oscsrc (3) in rcc register");
-			mainfreq = 6000000;
+		case 3:				/* lowspeed */
+			/* Sandstorm doesn't have this 30K +/- 30% osc */
+			mainfreq = 30000;
+			stellaris_info->mck_desc = " (±30%)";
 			break;
+		case 8:				/* hibernation osc */
+			/* not all parts support hibernation */
+			mainfreq = 32768;
+			break;
 
 		default: /* NOTREACHED */
 			mainfreq = 0;
 			break;
 	}
 
+	/* PLL is used if it's not bypassed; its output is 200 MHz
+	 * even when it runs at 400 MHz (adds divide-by-two stage).
+	 */
 	if (!bypass)
-		mainfreq = 200000000; /* PLL out frec */
+		mainfreq = 200000000;
 
 	if (usesysdiv)
 		stellaris_info->mck_freq = mainfreq/(1 + sysdiv);
@@ -487,6 +563,48 @@
 		LOG_WARNING("Unknown did1 version/family, cannot positively identify target as a Stellaris");
 	}
 
+	/* For Sandstorm, Fury, DustDevil:  current data sheets say IOSC
+	 * is 12 MHz, but some older parts have 15 MHz.  A few data sheets
+	 * even give _both_ numbers!  We'll use current numbers; IOSC is
+	 * always approximate.
+	 *
+	 * For Tempest:  IOSC is calibrated, 16 MHz
+	 */
+	stellaris_info->iosc_freq = 12000000;
+	stellaris_info->iosc_desc = " (±30%)";
+	stellaris_info->xtal_mask = 0x0f;
+
+	switch ((did0 >> 28) & 0x7) {
+	case 0:				/* Sandstorm */
+		/*
+		 * Current (2009-August) parts seem to be rev C2 and use 12 MHz.
+		 * Parts before rev C0 used 15 MHz; some C0 parts use 15 MHz
+		 * (LM3S618), but some other C0 parts are 12 MHz (LM3S811).
+		 */
+		if (((did0 >> 16) & 0xff) <= 2) {
+			stellaris_info->iosc_freq = 15000000;
+			stellaris_info->iosc_desc = " (±50%)";
+		}
+		break;
+	case 1:
+		switch ((did0 >> 16) & 0xff) {
+		case 1:			/* Fury */
+			break;
+		case 4:			/* Tempest */
+			stellaris_info->iosc_freq = 16000000;	/* +/- 1% */
+			stellaris_info->iosc_desc = " (±1%)";
+			/* FALL THROUGH */
+		case 3:			/* DustDevil */
+			stellaris_info->xtal_mask = 0x1f;
+			break;
+		default:
+			LOG_WARNING("Unknown did0 class");
+		}
+	default:
+		break;
+		LOG_WARNING("Unknown did0 version");
+	}
+
 	for (i = 0; StellarisParts[i].partno; i++)
 	{
 		if (StellarisParts[i].partno == ((did1 >> 16) & 0xFF))
@@ -547,7 +665,7 @@
 
 	if (stellaris_info->did1 == 0)
 	{
-		LOG_WARNING("Cannot identify target as an AT91SAM");
+		LOG_WARNING("Cannot identify target as Stellaris");
 		return ERROR_FLASH_OPERATION_FAILED;
 	}
 

Modified: trunk/src/flash/stellaris.h
===================================================================
--- trunk/src/flash/stellaris.h	2009-08-25 20:03:35 UTC (rev 2625)
+++ trunk/src/flash/stellaris.h	2009-08-26 06:26:29 UTC (rev 2626)
@@ -45,8 +45,13 @@
 
 	/* main clock status */
 	uint32_t rcc;
+	uint32_t rcc2;
 	uint8_t  mck_valid;
+	uint8_t  xtal_mask;
+	uint32_t iosc_freq;
 	uint32_t mck_freq;
+	const char *iosc_desc;
+	const char *mck_desc;
 } stellaris_flash_bank_t;
 
 /* STELLARIS control registers */
@@ -62,6 +67,7 @@
 #define	RIS			0x050
 #define	RCC			0x060
 #define	PLLCFG		0x064
+#define	RCC2		0x070
 
 #define FMPRE		0x130
 #define FMPPE		0x134

[Openocd-svn] r2625 - trunk

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 22:03:35 +0200 (Tue, 25 Aug 2009)
New Revision: 2625

Modified:
   trunk/NEWS
Log:
David Brownell <da...@pa...> Various updates to 0.3.0 NEWS

Modified: trunk/NEWS
===================================================================
--- trunk/NEWS	2009-08-25 20:02:19 UTC (rev 2624)
+++ trunk/NEWS	2009-08-25 20:03:35 UTC (rev 2625)
@@ -1,13 +1,30 @@
-This file should include items worth mentioning in the
-OpenOCD openocd-0.2.0 source archive release.
+This file should include highlights of the changes made in the
+OpenOCD openocd-0.3.0 source archive release.  See the repository
+history for details about what changed, including bugfixes and
+other issues not mentioned here.
 
-The following areas of OpenOCD functionality changed in this release:
+JTAG Layer:
+    FT2232H (high speed USB) support doesn't need separate configuration
 
-JTAG Layer:
 Target Layer:
+    New commands for use with Cortex-M3 processors:
+	"cortex_m3 disassemble" ... Thumb2 disassembly (UAL format)
+	"cortex_m3 vector_catch" ... traps certain hardware faults
+		without tying up breakpoint resources
+    If you're willing to help debug it:  VERY EARLY Cortex-A8 support
+
 Flash Layer:
+    The lpc2000 driver handles the new NXP LPC1700 (Cortex-M3) chips
+
 Board, Target, and Interface Configuration Scripts:
+    Cleanup and additions for the TI/Luminary Stellaris scripts
+    LPC1768 target (and flash) support
+	Keil MCB1700 eval board
+    Samsung s3c2450
+	Mini2440 board
+
 Documentation:
+
 Build and Release:
 
 For more details about what has changed since the last release,

[Openocd-svn] r2624 - in trunk: doc src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 22:02:19 +0200 (Tue, 25 Aug 2009)
New Revision: 2624

Modified:
   trunk/doc/openocd.texi
   trunk/src/target/armv4_5.c
   trunk/src/target/cortex_m3.c
Log:
David Brownell <da...@pa...> Tweak disassembly commands:

 For ARMv4/ARMv5:
  - better command parameter error checking
  - don't require an instruction count; default to one
  - recognize thumb function addresses
  - make function static
  - shorten some too-long lines
 For Cortex-M3:
  - don't require an instruction count; default to one

With the relevant doc updates.
---
Nyet done:  invoke the thumb2 disassembler on v4/v5,
to better handle branch instructions.

Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-08-25 19:59:55 UTC (rev 2623)
+++ trunk/doc/openocd.texi	2009-08-25 20:02:19 UTC (rev 2624)
@@ -4612,10 +4612,12 @@
 that is not currently supported in OpenOCD.)
 @end deffn
 
-@deffn Command {armv4_5 disassemble} address count [thumb]
+@deffn Command {armv4_5 disassemble} address [count [@option{thumb}]]
 @cindex disassemble
 Disassembles @var{count} instructions starting at @var{address}.
-If @option{thumb} is specified, Thumb (16-bit) instructions are used;
+If @var{count} is not specified, a single instruction is disassembled.
+If @option{thumb} is specified, or the low bit of the address is set,
+Thumb (16-bit) instructions are used;
 else ARM (32-bit) instructions are used.
 (Processors may also support the Jazelle state, but
 those instructions are not currently understood by OpenOCD.)
@@ -5086,9 +5088,10 @@
 @subsection Cortex-M3 specific commands
 @cindex Cortex-M3
 
-@deffn Command {cortex_m3 disassemble} address count
+@deffn Command {cortex_m3 disassemble} address [count]
 @cindex disassemble
 Disassembles @var{count} Thumb2 instructions starting at @var{address}.
+If @var{count} is not specified, a single instruction is disassembled.
 @end deffn
 
 @deffn Command {cortex_m3 maskisr} (@option{on}|@option{off})

Modified: trunk/src/target/armv4_5.c
===================================================================
--- trunk/src/target/armv4_5.c	2009-08-25 19:59:55 UTC (rev 2623)
+++ trunk/src/target/armv4_5.c	2009-08-25 20:02:19 UTC (rev 2624)
@@ -387,13 +387,15 @@
 	return ERROR_OK;
 }
 
-int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int
+handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	int retval = ERROR_OK;
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	uint32_t address;
-	int count;
+	int count = 1;
 	int i;
 	arm_instruction_t cur_instruction;
 	uint32_t opcode;
@@ -406,19 +408,32 @@
 		return ERROR_OK;
 	}
 
-	if (argc < 2)
-	{
-		command_print(cmd_ctx, "usage: armv4_5 disassemble <address> <count> ['thumb']");
+	switch (argc) {
+	case 3:
+		if (strcmp(args[2], "thumb") != 0)
+			goto usage;
+		thumb = 1;
+		/* FALL THROUGH */
+	case 2:
+		count = strtoul(args[1], NULL, 0);
+		/* FALL THROUGH */
+	case 1:
+		address = strtoul(args[0], NULL, 0);
+		if (address & 0x01) {
+			if (!thumb) {
+				command_print(cmd_ctx, "Disassemble as Thumb");
+				thumb = 1;
+			}
+			address &= ~1;
+		}
+		break;
+	default:
+usage:
+		command_print(cmd_ctx,
+			"usage: armv4_5 disassemble <address> [<count> ['thumb']]");
 		return ERROR_OK;
 	}
 
-	address = strtoul(args[0], NULL, 0);
-	count = strtoul(args[1], NULL, 0);
-
-	if (argc >= 3)
-		if (strcmp(args[2], "thumb") == 0)
-			thumb = 1;
-
 	for (i = 0; i < count; i++)
 	{
 		if (thumb)
@@ -453,12 +468,20 @@
 {
 	command_t *armv4_5_cmd;
 
-	armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5", NULL, COMMAND_ANY, "armv4/5 specific commands");
+	armv4_5_cmd = register_command(cmd_ctx, NULL, "armv4_5",
+			NULL, COMMAND_ANY,
+			"armv4/5 specific commands");
 
-	register_command(cmd_ctx, armv4_5_cmd, "reg", handle_armv4_5_reg_command, COMMAND_EXEC, "display ARM core registers");
-	register_command(cmd_ctx, armv4_5_cmd, "core_state", handle_armv4_5_core_state_command, COMMAND_EXEC, "display/change ARM core state <arm | thumb>");
+	register_command(cmd_ctx, armv4_5_cmd, "reg",
+			handle_armv4_5_reg_command, COMMAND_EXEC,
+			"display ARM core registers");
+	register_command(cmd_ctx, armv4_5_cmd, "core_state",
+			handle_armv4_5_core_state_command, COMMAND_EXEC,
+			"display/change ARM core state <arm | thumb>");
+	register_command(cmd_ctx, armv4_5_cmd, "disassemble",
+			handle_armv4_5_disassemble_command, COMMAND_EXEC,
+			"disassemble instructions <address> [<count> ['thumb']]");
 
-	register_command(cmd_ctx, armv4_5_cmd, "disassemble", handle_armv4_5_disassemble_command, COMMAND_EXEC, "disassemble instructions <address> <count> ['thumb']");
 	return ERROR_OK;
 }
 

Modified: trunk/src/target/cortex_m3.c
===================================================================
--- trunk/src/target/cortex_m3.c	2009-08-25 19:59:55 UTC (rev 2623)
+++ trunk/src/target/cortex_m3.c	2009-08-25 20:02:19 UTC (rev 2624)
@@ -1702,23 +1702,27 @@
 	int retval = ERROR_OK;
 	target_t *target = get_current_target(cmd_ctx);
 	uint32_t address;
-	unsigned long count;
+	unsigned long count = 1;
 	arm_instruction_t cur_instruction;
 
-	if (argc != 2) {
+	errno = 0;
+	switch (argc) {
+	case 2:
+		count = strtoul(args[1], NULL, 0);
+		if (errno)
+			return ERROR_FAIL;
+		/* FALL THROUGH */
+	case 1:
+		address = strtoul(args[0], NULL, 0);
+		if (errno)
+			return ERROR_FAIL;
+		break;
+	default:
 		command_print(cmd_ctx,
-			"usage: cortex_m3 disassemble <address> <count>");
+			"usage: cortex_m3 disassemble <address> [<count>]");
 		return ERROR_OK;
 	}
 
-	errno = 0;
-	address = strtoul(args[0], NULL, 0);
-	if (errno)
-		return ERROR_FAIL;
-	count = strtoul(args[1], NULL, 0);
-	if (errno)
-		return ERROR_FAIL;
-
 	while (count--) {
 		retval = thumb2_opcode(target, address, &cur_instruction);
 		if (retval != ERROR_OK)
@@ -1809,7 +1813,7 @@
 
 	register_command(cmd_ctx, cortex_m3_cmd, "disassemble",
 			handle_cortex_m3_disassemble_command, COMMAND_EXEC,
-			"disassemble Thumb2 instructions <address> <count>");
+			"disassemble Thumb2 instructions <address> [<count>]");
 	register_command(cmd_ctx, cortex_m3_cmd, "maskisr",
 			handle_cortex_m3_mask_interrupts_command, COMMAND_EXEC,
 			"mask cortex_m3 interrupts ['on'|'off']");

[Openocd-svn] r2623 - trunk/src/jtag

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 21:59:55 +0200 (Tue, 25 Aug 2009)
New Revision: 2623

Modified:
   trunk/src/jtag/core.c
Log:
David Brownell <da...@pa...> More jtag_add_reset() cleanup:

Unify the handling of the req_srst parameter, and rip out a
large NOP branch and its associated FIXME.  (There didn't seem
to be anything that needs fixing; but that was unclear since
the constraints were scattered all over the place not unified.)

Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-08-25 19:58:06 UTC (rev 2622)
+++ trunk/src/jtag/core.c	2009-08-25 19:59:55 UTC (rev 2623)
@@ -585,9 +585,31 @@
 void jtag_add_reset(int req_tlr_or_trst, int req_srst)
 {
 	int trst_with_tlr = 0;
-	int new_srst;
+	int new_srst = 0;
 	int new_trst = 0;
 
+	/* Without SRST, we must use target-specific JTAG operations
+	 * on each target; callers should not be requesting SRST when
+	 * that signal doesn't exist.
+	 *
+	 * RESET_SRST_PULLS_TRST is a board or chip level quirk, which
+	 * can kick in even if the JTAG adapter can't drive TRST.
+	 */
+	if (req_srst) {
+		if (!(jtag_reset_config & RESET_HAS_SRST)) {
+			LOG_ERROR("BUG: can't assert SRST");
+			jtag_set_error(ERROR_FAIL);
+			return;
+		}
+		if ((jtag_reset_config & RESET_SRST_PULLS_TRST) != 0
+				&& !req_tlr_or_trst) {
+			LOG_ERROR("BUG: can't assert only SRST");
+			jtag_set_error(ERROR_FAIL);
+			return;
+		}
+		new_srst = 1;
+	}
+
 	/* JTAG reset (entry to TAP_RESET state) can always be achieved
 	 * using TCK and TMS; that may go through a TAP_{IR,DR}UPDATE
 	 * state first.  TRST accelerates it, and bypasses those states.
@@ -605,41 +627,6 @@
 			new_trst = 1;
 	}
 
-	/* FIX!!! there are *many* different cases here. A better
-	 * approach is needed for legal combinations of transitions...
-	 */
-	if ((jtag_reset_config & RESET_HAS_SRST)&&
-			(jtag_reset_config & RESET_HAS_TRST)&&
-			((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0))
-	{
-		if (((req_tlr_or_trst&&!jtag_trst)||
-				(!req_tlr_or_trst && jtag_trst))&&
-				((req_srst&&!jtag_srst)||
-						(!req_srst && jtag_srst)))
-		{
-			/* FIX!!! srst_pulls_trst allows 1,1 => 0,0 transition.... */
-			//LOG_ERROR("BUG: transition of req_tlr_or_trst and req_srst in the same jtag_add_reset() call is undefined");
-		}
-	}
-
-	/* Make sure that jtag_reset_config allows the requested reset */
-	/* if SRST pulls TRST, we can't fulfill srst == 1 with trst == 0 */
-	if (((jtag_reset_config & RESET_SRST_PULLS_TRST) && (req_srst == 1)) && (!req_tlr_or_trst))
-	{
-		LOG_ERROR("BUG: requested reset would assert trst");
-		jtag_set_error(ERROR_FAIL);
-		return;
-	}
-
-	if (req_srst && !(jtag_reset_config & RESET_HAS_SRST))
-	{
-		LOG_ERROR("BUG: requested SRST assertion, but the current configuration doesn't support this");
-		jtag_set_error(ERROR_FAIL);
-		return;
-	}
-
-	new_srst = req_srst;
-
 	/* Maybe change TRST and/or SRST signal state */
 	if (jtag_srst != new_srst || jtag_trst != new_trst) {
 		int retval;

[Openocd-svn] r2622 - trunk/src/jtag

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 21:58:06 +0200 (Tue, 25 Aug 2009)
New Revision: 2622

Modified:
   trunk/src/jtag/core.c
Log:
David Brownell <da...@pa...> More jtag_add_reset() cleanup:

Unify the handling of the req_tlr_or_trst parameter.  Basically,
JTAG TMS+TCK ops ("TLR") is always used ... unless TRST is a safe
option in this system configuration.

Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-08-25 19:55:32 UTC (rev 2621)
+++ trunk/src/jtag/core.c	2009-08-25 19:58:06 UTC (rev 2622)
@@ -588,6 +588,23 @@
 	int new_srst;
 	int new_trst = 0;
 
+	/* JTAG reset (entry to TAP_RESET state) can always be achieved
+	 * using TCK and TMS; that may go through a TAP_{IR,DR}UPDATE
+	 * state first.  TRST accelerates it, and bypasses those states.
+	 *
+	 * RESET_TRST_PULLS_SRST is a board or chip level quirk, which
+	 * can kick in even if the JTAG adapter can't drive SRST.
+	 */
+	if (req_tlr_or_trst) {
+		if (!(jtag_reset_config & RESET_HAS_TRST))
+			trst_with_tlr = 1;
+		else if ((jtag_reset_config & RESET_TRST_PULLS_SRST) != 0
+				&& !req_srst)
+			trst_with_tlr = 1;
+		else
+			new_trst = 1;
+	}
+
 	/* FIX!!! there are *many* different cases here. A better
 	 * approach is needed for legal combinations of transitions...
 	 */
@@ -614,12 +631,6 @@
 		return;
 	}
 
-	/* if TRST pulls SRST, we reset with TAP T-L-R */
-	if (((jtag_reset_config & RESET_TRST_PULLS_SRST) && (req_tlr_or_trst)) && (req_srst == 0))
-	{
-		trst_with_tlr = 1;
-	}
-
 	if (req_srst && !(jtag_reset_config & RESET_HAS_SRST))
 	{
 		LOG_ERROR("BUG: requested SRST assertion, but the current configuration doesn't support this");
@@ -627,17 +638,6 @@
 		return;
 	}
 
-	if (req_tlr_or_trst)
-	{
-		if (!trst_with_tlr && (jtag_reset_config & RESET_HAS_TRST))
-		{
-			new_trst = 1;
-		} else
-		{
-			trst_with_tlr = 1;
-		}
-	}
-
 	new_srst = req_srst;
 
 	/* Maybe change TRST and/or SRST signal state */
@@ -831,6 +831,7 @@
 	{
 		tap->enabled = !tap->disabled_after_reset;
 
+		/* current instruction is either BYPASS or IDCODE */
 		buf_set_ones(tap->cur_instr, tap->ir_length);
 		tap->bypass = 1;
 	}

[Openocd-svn] r2621 - trunk/src/jtag

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 21:55:32 +0200 (Tue, 25 Aug 2009)
New Revision: 2621

Modified:
   trunk/src/jtag/core.c
Log:
David Brownell <da...@pa...> Some jtag_add_reset() cleanup:

 - Track whether TRST and/or SRST actually change:

    * If they're not changing, don't ask the JTAG adapter to do anything!
      (JTAG TCK/TMS ops might still be used to enter TAP_RESET though.)
    * Don't change their recorded values until after the adapter says it
      did so ... so fault paths can't leave corrupt state.
    * Detect and report jtag_execute_queue() failure mode
    * Only emit messages saying what really changed; this includes adding
      an omitted "deasserted TRST" message.
    * Only apply delays after deasserting SRST/TRST if we *DID* deassert!

 - Messages say "TLR" not "RESET", to be less confusing; there are many
   kinds of reset.  (Though "TLR" isn't quite ideal either, since it's
   the name of the TAP state being entered by TMS+TCK or TRST; it's at
   least non-ambiguous in context.)

So the main effect is to do only the work this routine was told to do;
and to have debug messaging make more sense.

Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-08-25 19:52:02 UTC (rev 2620)
+++ trunk/src/jtag/core.c	2009-08-25 19:55:32 UTC (rev 2621)
@@ -60,11 +60,15 @@
 
 static const char *jtag_event_strings[] =
 {
-	[JTAG_TRST_ASSERTED] = "JTAG controller reset (RESET or TRST)",
+	[JTAG_TRST_ASSERTED] = "JTAG controller reset (TLR or TRST)",
 	[JTAG_TAP_EVENT_ENABLE] = "TAP enabled",
 	[JTAG_TAP_EVENT_DISABLE] = "TAP disabled",
 };
 
+/*
+ * JTAG adapters must initialize with TRST and SRST de-asserted
+ * (they're negative logic, so that means *high*)
+ */
 static int jtag_trst = 0;
 static int jtag_srst = 0;
 
@@ -581,6 +585,8 @@
 void jtag_add_reset(int req_tlr_or_trst, int req_srst)
 {
 	int trst_with_tlr = 0;
+	int new_srst;
+	int new_trst = 0;
 
 	/* FIX!!! there are *many* different cases here. A better
 	 * approach is needed for legal combinations of transitions...
@@ -625,59 +631,73 @@
 	{
 		if (!trst_with_tlr && (jtag_reset_config & RESET_HAS_TRST))
 		{
-			jtag_trst = 1;
+			new_trst = 1;
 		} else
 		{
 			trst_with_tlr = 1;
 		}
-	} else
-	{
-		jtag_trst = 0;
 	}
 
-	jtag_srst = req_srst;
+	new_srst = req_srst;
 
-	int retval = interface_jtag_add_reset(jtag_trst, jtag_srst);
-	if (retval != ERROR_OK)
-	{
-		jtag_set_error(retval);
-		return;
+	/* Maybe change TRST and/or SRST signal state */
+	if (jtag_srst != new_srst || jtag_trst != new_trst) {
+		int retval;
+
+		retval = interface_jtag_add_reset(new_trst, new_srst);
+		if (retval != ERROR_OK)
+			jtag_set_error(retval);
+		else
+			retval = jtag_execute_queue();
+
+		if (retval != ERROR_OK) {
+			LOG_ERROR("TRST/SRST error %d", retval);
+			return;
+		}
 	}
-	jtag_execute_queue();
 
-	if (jtag_srst)
-	{
-		LOG_DEBUG("SRST line asserted");
+	/* SRST resets everything hooked up to that signal */
+	if (jtag_srst != new_srst) {
+		jtag_srst = new_srst;
+		if (jtag_srst)
+			LOG_DEBUG("SRST line asserted");
+		else {
+			LOG_DEBUG("SRST line released");
+			if (jtag_nsrst_delay)
+				jtag_add_sleep(jtag_nsrst_delay * 1000);
+		}
 	}
-	else
-	{
-		LOG_DEBUG("SRST line released");
-		if (jtag_nsrst_delay)
-			jtag_add_sleep(jtag_nsrst_delay * 1000);
-	}
 
-	if (trst_with_tlr)
-	{
-		LOG_DEBUG("JTAG reset with RESET instead of TRST");
+	/* Maybe enter the JTAG TAP_RESET state ...
+	 *  - using only TMS, TCK, and the JTAG state machine
+	 *  - or else more directly, using TRST
+	 *
+	 * TAP_RESET should be invisible to non-debug parts of the system.
+	 */
+	if (trst_with_tlr) {
+		LOG_DEBUG("JTAG reset with TLR instead of TRST");
 		jtag_set_end_state(TAP_RESET);
 		jtag_add_tlr();
-		return;
-	}
 
-	if (jtag_trst)
-	{
-		/* we just asserted nTRST, so we're now in Test-Logic-Reset,
-		 * and inform possible listeners about this
-		 */
-		LOG_DEBUG("TRST line asserted");
-		tap_set_state(TAP_RESET);
-		jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
+	} else if (jtag_trst != new_trst) {
+		jtag_trst = new_trst;
+		if (jtag_trst) {
+			/* we just asserted nTRST, so we're now in TAP_RESET;
+			 * inform possible listeners about this
+			 *
+			 * REVISIT asserting TRST is less significant than
+			 * being in TAP_RESET ... both entries (TRST, TLR)
+			 * should trigger a callback.
+			 */
+			LOG_DEBUG("TRST line asserted");
+			tap_set_state(TAP_RESET);
+			jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
+		} else {
+			LOG_DEBUG("TRST line released");
+			if (jtag_ntrst_delay)
+				jtag_add_sleep(jtag_ntrst_delay * 1000);
+		}
 	}
-	else
-	{
-		if (jtag_ntrst_delay)
-			jtag_add_sleep(jtag_ntrst_delay * 1000);
-	}
 }
 
 tap_state_t jtag_set_end_state(tap_state_t state)
@@ -1223,11 +1243,11 @@
 	if ((retval = jtag_interface_init(cmd_ctx)) != ERROR_OK)
 		return retval;
 
-	LOG_DEBUG("Trying to bring the JTAG controller to life by asserting TRST / RESET");
+	LOG_DEBUG("Trying to bring the JTAG controller to life by asserting TRST / TLR");
 
 	/* Reset can happen after a power cycle.
 	 *
-	 * Ideally we would only assert TRST or run RESET before the target reset.
+	 * Ideally we would only assert TRST or run TLR before the target reset.
 	 *
 	 * However w/srst_pulls_trst, trst is asserted together with the target
 	 * reset whether we want it or not.
@@ -1240,7 +1260,7 @@
 	 * NB! order matters!!!! srst *can* disconnect JTAG circuitry
 	 *
 	 */
-	jtag_add_reset(1, 0); /* RESET or TRST */
+	jtag_add_reset(1, 0); /* TAP_RESET, using TMS+TCK or TRST */
 	if (jtag_reset_config & RESET_HAS_SRST)
 	{
 		jtag_add_reset(1, 1);

[Openocd-svn] r2620 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 21:52:02 +0200 (Tue, 25 Aug 2009)
New Revision: 2620

Modified:
   trunk/src/target/target.c
Log:
David Brownell <da...@pa...> Accomodate targets which don't support various target-specific
reset operations.  Maybe they can't; or it's a "not yet" thing.

Note that the assert/deassert operations can't yet trigger for
OMAP3 because resets currently include JTAG reset in all cases,
resetting the ICEpick and thus disabling the TAP for Cortex-A8.

Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c	2009-08-25 13:00:45 UTC (rev 2619)
+++ trunk/src/target/target.c	2009-08-25 19:52:02 UTC (rev 2620)
@@ -559,6 +559,11 @@
 		LOG_ERROR("Target not examined yet");
 		return ERROR_FAIL;
 	}
+	if (!target->type->soft_reset_halt_imp) {
+		LOG_ERROR("Target %s does not support soft_reset_halt",
+				target->cmd_name);
+		return ERROR_FAIL;
+	}
 	return target->type->soft_reset_halt_imp(target);
 }
 
@@ -4035,6 +4040,13 @@
 		}
 		if (!target->tap->enabled)
 			goto err_tap_disabled;
+		if (!target->type->assert_reset
+				|| !target->type->deassert_reset) {
+			Jim_SetResult_sprintf(interp,
+					"No target-specific reset for %s",
+					target->cmd_name);
+			return JIM_ERR;
+		}
 		/* determine if we should halt or not. */
 		target->reset_halt = !!a;
 		/* When this happens - all workareas are invalid. */

[Openocd-svn] r2619 - trunk/doc

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 15:00:45 +0200 (Tue, 25 Aug 2009)
New Revision: 2619

Modified:
   trunk/doc/openocd.texi
Log:
Michael Schwingen <rin...@di...> fix previous doc patch

Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-08-25 12:19:44 UTC (rev 2618)
+++ trunk/doc/openocd.texi	2009-08-25 13:00:45 UTC (rev 2619)
@@ -4982,7 +4982,6 @@
 @cindex vector_catch
 Display a bitmask showing the hardware vectors to catch.
 If the optional parameter is provided, first set the bitmask to that value.
-@end deffn
 
 The mask bits correspond with bit 16..23 in the DCSR:
 @example
@@ -4995,8 +4994,8 @@
 0x40    Trap IRQ
 0x80    Trap FIQ
 @end example
+@end deffn
 
-
 @anchor{xscale vector_table}
 @deffn Command {xscale vector_table} [<low|high> <index> <value>]
 @cindex vector_table

[Openocd-svn] r2618 - trunk/src/target

[ntfreak at B. <nt...@ma...>]

Author: ntfreak
Date: 2009-08-25 14:19:44 +0200 (Tue, 25 Aug 2009)
New Revision: 2618

Modified:
   trunk/src/target/armv7a.c
   trunk/src/target/armv7a.h
   trunk/src/target/cortex_a8.c
   trunk/src/target/xscale.c
Log:
- fix build warnings
- add svn props to recently added files armv7a.[ch]

Modified: trunk/src/target/armv7a.c
===================================================================
--- trunk/src/target/armv7a.c	2009-08-25 08:21:11 UTC (rev 2617)
+++ trunk/src/target/armv7a.c	2009-08-25 12:19:44 UTC (rev 2618)
@@ -189,7 +189,7 @@
 	}
 
 	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			 "%s: 0x%8.8x pc: 0x%8.8x\n"
+			 "%s: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 			 "MMU: %s, D-Cache: %s, I-Cache: %s",
 		 armv7a_state_strings[armv4_5->core_state],
 		 Jim_Nvp_value2name_simple(nvp_target_debug_reason,


Property changes on: trunk/src/target/armv7a.c
___________________________________________________________________
Name: svn:eol-style
   + native


Property changes on: trunk/src/target/armv7a.h
___________________________________________________________________
Name: svn:eol-style
   + native

Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-08-25 08:21:11 UTC (rev 2617)
+++ trunk/src/target/cortex_a8.c	2009-08-25 12:19:44 UTC (rev 2618)
@@ -160,7 +160,7 @@
 	armv7a_common_t *armv7a = armv4_5->arch_info;
 	swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
-	LOG_DEBUG("exec opcode 0x%08x", opcode);
+	LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
 	mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
 	do
 	{
@@ -388,7 +388,7 @@
 	}
 	else
 	{
-		LOG_DEBUG("Unknown target state dscr = 0x%08x", dscr);
+		LOG_DEBUG("Unknown target state dscr = 0x%08" PRIx32, dscr);
 		target->state = TARGET_UNKNOWN;
 	}
 
@@ -476,7 +476,7 @@
 	{
 		resume_pc &= 0xFFFFFFFC;
 	}
-	LOG_DEBUG("resume pc = 0x%08x", resume_pc);
+	LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
 	buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
 				armv4_5->core_mode, 15).value,
 			0, 32, resume_pc);
@@ -516,13 +516,13 @@
 	{
 		target->state = TARGET_RUNNING;
 		target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
-		LOG_DEBUG("target resumed at 0x%x", resume_pc);
+		LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc);
 	}
 	else
 	{
 		target->state = TARGET_DEBUG_RUNNING;
 		target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
-		LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
+		LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
 	}
 
 	dap_ap_select(swjdp, saved_apsel);
@@ -546,7 +546,7 @@
 	if (armv7a->pre_debug_entry)
 		armv7a->pre_debug_entry(target);
 
-	LOG_DEBUG("dscr = 0x%08x", cortex_a8->cpudbg_dscr);
+	LOG_DEBUG("dscr = 0x%08" PRIx32, cortex_a8->cpudbg_dscr);
 
 	/* Examine debug reason */
 	switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
@@ -590,7 +590,7 @@
 	cortex_a8_dap_read_coreregister_u32(target, &cpsr, 16);
 	pc = regfile[15];
 	dap_ap_select(swjdp, swjdp_debugap);
-	LOG_DEBUG("cpsr: %8.8x", cpsr);
+	LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
 
 	armv4_5->core_mode = cpsr & 0x3F;
 
@@ -668,7 +668,7 @@
 	/* examine cp15 control reg */
 	armv7a->read_cp15(target, 0, 0, 1, 0, &cortex_a8->cp15_control_reg);
 	jtag_execute_queue();
-	LOG_DEBUG("cp15_control_reg: %8.8x", cortex_a8->cp15_control_reg);
+	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a8->cp15_control_reg);
 
 	if (armv7a->armv4_5_mmu.armv4_5_cache.ctype == -1)
 	{
@@ -827,7 +827,7 @@
 			LOG_ERROR("JTAG failure %i", retval);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
-		LOG_DEBUG("load from core reg %i value 0x%x", num, *value);
+		LOG_DEBUG("load from core reg %i value 0x%" PRIx32, num, *value);
 	}
 	else
 	{
@@ -880,7 +880,7 @@
 					armv4_5->core_mode, num).valid;
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
-		LOG_DEBUG("write core reg %i value 0x%x", num, value);
+		LOG_DEBUG("write core reg %i value 0x%" PRIx32, num, value);
 	}
 	else
 	{
@@ -983,7 +983,7 @@
 		target_write_u32(target, OMAP3530_DEBUG_BASE
 				+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
 				brp_list[brp_i].control);
-		LOG_DEBUG("brp %i control 0x%0x value 0x%0x", brp_i,
+		LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
 				brp_list[brp_i].control,
 				brp_list[brp_i].value);
 	}
@@ -1038,7 +1038,7 @@
 			LOG_DEBUG("Invalid BRP number in breakpoint");
 			return ERROR_OK;
 		}
-		LOG_DEBUG("rbp %i control 0x%0x value 0x%0x", brp_i,
+		LOG_DEBUG("rbp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
 				brp_list[brp_i].control, brp_list[brp_i].value);
 		brp_list[brp_i].used = 0;
 		brp_list[brp_i].value = 0;
@@ -1330,10 +1330,10 @@
 		return retval;
 	}
 
-	LOG_DEBUG("cpuid = 0x%08x", cpuid);
-	LOG_DEBUG("ctypr = 0x%08x", ctypr);
-	LOG_DEBUG("ttypr = 0x%08x", ttypr);
-	LOG_DEBUG("didr = 0x%08x", didr);
+	LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
+	LOG_DEBUG("ctypr = 0x%08" PRIx32, ctypr);
+	LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
+	LOG_DEBUG("didr = 0x%08" PRIx32, didr);
 
 	/* Setup Breakpoint Register Pairs */
 	cortex_a8->brp_num = ((didr >> 24) & 0x0F) + 1;

Modified: trunk/src/target/xscale.c
===================================================================
--- trunk/src/target/xscale.c	2009-08-25 08:21:11 UTC (rev 2617)
+++ trunk/src/target/xscale.c	2009-08-25 12:19:44 UTC (rev 2618)
@@ -3406,10 +3406,10 @@
 		command_print(cmd_ctx, "active user-set static vectors:");
 		for (idx = 1; idx < 8; idx++)
 			if (xscale->static_low_vectors_set & (1 << idx))
-				command_print(cmd_ctx, "low  %d: 0x%x", idx, xscale->static_low_vectors[idx]);
+				command_print(cmd_ctx, "low  %d: 0x%" PRIx32, idx, xscale->static_low_vectors[idx]);
 		for (idx = 1; idx < 8; idx++)
 			if (xscale->static_high_vectors_set & (1 << idx))
-				command_print(cmd_ctx, "high %d: 0x%x", idx, xscale->static_high_vectors[idx]);
+				command_print(cmd_ctx, "high %d: 0x%" PRIx32, idx, xscale->static_high_vectors[idx]);
 		return ERROR_OK;
 	}
 

[Openocd-svn] r2617 - trunk/src/flash

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 10:21:11 +0200 (Tue, 25 Aug 2009)
New Revision: 2617

Modified:
   trunk/src/flash/cfi.c
   trunk/src/flash/non_cfi.c
   trunk/src/flash/non_cfi.h
Log:
Michael Schwingen <rin...@di...> a small CFI cleanup

Modified: trunk/src/flash/cfi.c
===================================================================
--- trunk/src/flash/cfi.c	2009-08-25 07:17:19 UTC (rev 2616)
+++ trunk/src/flash/cfi.c	2009-08-25 08:21:11 UTC (rev 2617)
@@ -74,7 +74,7 @@
 static void cfi_fixup_atmel_reversed_erase_regions(flash_bank_t *flash, void *param);
 
 /* fixup after reading cmdset 0002 primary query table */
-static cfi_fixup_t cfi_0002_fixups[] = {
+static const cfi_fixup_t cfi_0002_fixups[] = {
 	{CFI_MFR_SST, 0x00D4, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 	{CFI_MFR_SST, 0x00D5, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
 	{CFI_MFR_SST, 0x00D6, cfi_fixup_0002_unlock_addresses, &cfi_unlock_addresses[CFI_UNLOCK_5555_2AAA]},
@@ -90,14 +90,14 @@
 };
 
 /* fixup after reading cmdset 0001 primary query table */
-static cfi_fixup_t cfi_0001_fixups[] = {
+static const cfi_fixup_t cfi_0001_fixups[] = {
 	{0, 0, NULL, NULL}
 };
 
-static void cfi_fixup(flash_bank_t *bank, cfi_fixup_t *fixups)
+static void cfi_fixup(flash_bank_t *bank, const cfi_fixup_t *fixups)
 {
 	cfi_flash_bank_t *cfi_info = bank->driver_priv;
-	cfi_fixup_t *f;
+	const cfi_fixup_t *f;
 
 	for (f = fixups; f->fixup; f++)
 	{

Modified: trunk/src/flash/non_cfi.c
===================================================================
--- trunk/src/flash/non_cfi.c	2009-08-25 07:17:19 UTC (rev 2616)
+++ trunk/src/flash/non_cfi.c	2009-08-25 08:21:11 UTC (rev 2617)
@@ -32,7 +32,7 @@
 #define ERASE_REGION(num, size) (((size/256) << 16) | (num-1))
 
 /* non-CFI compatible flashes */
-non_cfi_t non_cfi_flashes[] = {
+static non_cfi_t non_cfi_flashes[] = {
 	{
 		.mfr = CFI_MFR_SST,
 		.id = 0xd4,

Modified: trunk/src/flash/non_cfi.h
===================================================================
--- trunk/src/flash/non_cfi.h	2009-08-25 07:17:19 UTC (rev 2616)
+++ trunk/src/flash/non_cfi.h	2009-08-25 08:21:11 UTC (rev 2617)
@@ -35,7 +35,6 @@
 	uint8_t  status_poll_mask;
 } non_cfi_t;
 
-extern non_cfi_t non_cfi_flashes[];
 extern void cfi_fixup_non_cfi(flash_bank_t *bank);
 
 #endif /* NON_CFI_H */

[Openocd-svn] r2616 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 09:17:19 +0200 (Tue, 25 Aug 2009)
New Revision: 2616

Modified:
   trunk/src/target/armv7a.h
Log:
strange.... the code build and links w/Linux GCC target but fails w/arm-elf. The code was clearly broken as it was missing two extern's in the .h file...

Modified: trunk/src/target/armv7a.h
===================================================================
--- trunk/src/target/armv7a.h	2009-08-25 07:14:05 UTC (rev 2615)
+++ trunk/src/target/armv7a.h	2009-08-25 07:17:19 UTC (rev 2616)
@@ -40,7 +40,7 @@
 	ARMV7A_MODE_ANY = -1
 } armv7a_t;
 
-char **armv7a_mode_strings;
+extern char **armv7a_mode_strings;
 
 typedef enum armv7a_state
 {
@@ -52,7 +52,7 @@
 
 extern char *armv7a_state_strings[];
 
-int armv7a_core_reg_map[8][17];
+extern int armv7a_core_reg_map[8][17];
 
 #define ARMV7A_CORE_REG_MODE(cache, mode, num) \
 		cache->reg_list[armv7a_core_reg_map[armv7a_mode_to_number(mode)][num]]
@@ -173,4 +173,4 @@
 };
 
 
-#endif /* ARMV4_5_H */
\ No newline at end of file
+#endif /* ARMV4_5_H */

[Openocd-svn] r2615 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-25 09:14:05 +0200 (Tue, 25 Aug 2009)
New Revision: 2615

Modified:
   trunk/src/target/target.c
Log:
Ferdinand Postema <fer...@po...> fix warnings

Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c	2009-08-25 07:12:57 UTC (rev 2614)
+++ trunk/src/target/target.c	2009-08-25 07:14:05 UTC (rev 2615)
@@ -1760,7 +1760,7 @@
 					value = buf_to_str(reg->value,
 							reg->size, 16);
 					command_print(cmd_ctx,
-							"(%i) %s (/%u): 0x%s%s",
+							"(%i) %s (/%" PRIu32 "): 0x%s%s",
 							count, reg->name,
 							reg->size, value,
 							reg->dirty
@@ -1768,7 +1768,7 @@
 								: "");
 					free(value);
 				} else {
-					command_print(cmd_ctx, "(%i) %s (/%u)",
+					command_print(cmd_ctx, "(%i) %s (/%" PRIu32 ")",
 							  count, reg->name,
 							  reg->size) ;
 				}