openocd-commit — OpenOCD commit maling list - read only

[Openocd-svn] r2664 - trunk/tcl/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-04 07:14:32 +0200 (Fri, 04 Sep 2009)
New Revision: 2664

Modified:
   trunk/tcl/target/ar71xx.cfg
Log:
David Claffey <dnc...@gm...> get rid of reset recursion

Modified: trunk/tcl/target/ar71xx.cfg
===================================================================
--- trunk/tcl/target/ar71xx.cfg	2009-09-03 08:23:39 UTC (rev 2663)
+++ trunk/tcl/target/ar71xx.cfg	2009-09-04 05:14:32 UTC (rev 2664)
@@ -13,16 +13,17 @@
 set TARGETNAME [format "%s.cpu" $CHIPNAME]
 target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
 
-$TARGETNAME configure -event reset-init {
+$TARGETNAME configure -event reset-halt-post {
 	#setup PLL to lowest common denominator 300/300/150 setting
 	mww 0xb8050000 0x000f40a3	# reset val + CPU:3 DDR:3 AHB:0
 	mww 0xb8050000 0x800f40a3	# send to PLL
 
 	#next command will reset for PLL changes to take effect
 	mww 0xb8050008 3		# set reset_switch and clock_switch (resets SoC)
-	reset halt     			# let openocd know that it is in the reset state
+}
 
-	#initialize_pll
+$TARGETNAME configure -event reset-init {
+	#complete pll initialization
 	mww 0xb8050000 0x800f0080	# set sw_update bit
 	mww 0xb8050008 0		# clear reset_switch bit
 	mww 0xb8050000 0x800f00e8       # clr pwrdwn & bypass

[Openocd-svn] r2663 - trunk/src/flash

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-03 10:23:39 +0200 (Thu, 03 Sep 2009)
New Revision: 2663

Added:
   trunk/src/flash/arm_nandio.c
   trunk/src/flash/arm_nandio.h
Modified:
   trunk/src/flash/Makefile.am
   trunk/src/flash/davinci_nand.c
   trunk/src/flash/nand.h
   trunk/src/flash/orion_nand.c
Log:
David Brownell

Abstract the orion_nand_fast_block_write() routine into a separate
routine -- arm_nandwrite() -- so that other ARM cores can reuse it.

Have davinci_nand do so.  This faster than byte-at-a-time ops by a
factor of three (!), even given the slowish interactions to support
hardware ECC (1-bit flavor in that test) each 512 bytes; those could
be read more efficiently by on-chip code.

NOTE that until there's a generic "ARM algorithm" structure, this
can't work on newer ARMv6 (like ARM1136) or ARMv7A (like Cortex-A8)
cores, though the downloaded code itself would work just fine there.

Modified: trunk/src/flash/Makefile.am
===================================================================
--- trunk/src/flash/Makefile.am	2009-09-02 17:34:35 UTC (rev 2662)
+++ trunk/src/flash/Makefile.am	2009-09-03 08:23:39 UTC (rev 2663)
@@ -6,6 +6,7 @@
 METASOURCES = AUTO
 noinst_LTLIBRARIES = libflash.la
 libflash_la_SOURCES = \
+	arm_nandio.c \
 	flash.c \
 	lpc2000.c \
 	cfi.c \
@@ -38,6 +39,7 @@
 	avrf.c
 
 noinst_HEADERS = \
+	arm_nandio.h \
 	flash.h \
 	lpc2000.h \
 	cfi.h \

Added: trunk/src/flash/arm_nandio.c
===================================================================
--- trunk/src/flash/arm_nandio.c	2009-09-02 17:34:35 UTC (rev 2662)
+++ trunk/src/flash/arm_nandio.c	2009-09-03 08:23:39 UTC (rev 2663)
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2009 by Marvell Semiconductors, Inc.
+ * Written by Nicolas Pitre <nico at marvell.com>
+ *
+ * Copyright (C) 2009 by David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the
+ * Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "arm_nandio.h"
+#include "armv4_5.h"
+
+
+/*
+ * ARM-specific bulk write from buffer to address of 8-bit wide NAND.
+ * For now this only supports ARMv4 and ARMv5 cores.
+ *
+ * Enhancements to target_run_algorithm() could enable:
+ *   - faster writes: on ARMv5+ don't setup/teardown hardware breakpoint
+ *   - ARMv6 and ARMv7 cores in ARM mode
+ *
+ * Different code fragments could handle:
+ *   - Thumb2 cores like Cortex-M (needs different byteswapping)
+ *   - 16-bit wide data (needs different setup too)
+ */
+int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
+{
+	target_t		*target = nand->target;
+	armv4_5_algorithm_t	algo;
+	reg_param_t		reg_params[3];
+	uint32_t		target_buf;
+	int			retval;
+
+	/* Inputs:
+	 *  r0	NAND data address (byte wide)
+	 *  r1	buffer address
+	 *  r2	buffer length
+	 */
+	static const uint32_t code[] = {
+		0xe4d13001,	/* s: ldrb  r3, [r1], #1 */
+		0xe5c03000,	/*    strb  r3, [r0]     */
+		0xe2522001,	/*    subs  r2, r2, #1   */
+		0x1afffffb,	/*    bne   s            */
+
+		/* exit: ARMv4 needs hardware breakpoint */
+		0xe1200070,	/* e: bkpt  #0           */
+	};
+
+	if (!nand->copy_area) {
+		uint8_t		code_buf[sizeof(code)];
+		unsigned	i;
+
+		/* make sure we have a working area */
+		if (target_alloc_working_area(target,
+				sizeof(code) + nand->chunk_size,
+				&nand->copy_area) != ERROR_OK) {
+			LOG_DEBUG("%s: no %d byte buffer",
+					__FUNCTION__,
+					(int) sizeof(code) + nand->chunk_size);
+			return ERROR_NAND_NO_BUFFER;
+		}
+
+		/* buffer code in target endianness */
+		for (i = 0; i < sizeof(code) / 4; i++)
+			target_buffer_set_u32(target, code_buf + i * 4, code[i]);
+
+		/* copy code to work area */
+                retval = target_write_memory(target,
+					nand->copy_area->address,
+					4, sizeof(code) / 4, code_buf);
+		if (retval != ERROR_OK)
+			return retval;
+	}
+
+	/* copy data to work area */
+	target_buf = nand->copy_area->address + sizeof(code);
+	retval = target_bulk_write_memory(target, target_buf, size / 4, data);
+	if (retval == ERROR_OK && (size & 3) != 0)
+		retval = target_write_memory(target,
+				target_buf + (size & ~3),
+				1, size & 3, data + (size & ~3));
+	if (retval != ERROR_OK)
+		return retval;
+
+	/* set up algorithm and parameters */
+	algo.common_magic = ARMV4_5_COMMON_MAGIC;
+	algo.core_mode = ARMV4_5_MODE_SVC;
+	algo.core_state = ARMV4_5_STATE_ARM;
+
+	init_reg_param(&reg_params[0], "r0", 32, PARAM_IN);
+	init_reg_param(&reg_params[1], "r1", 32, PARAM_IN);
+	init_reg_param(&reg_params[2], "r2", 32, PARAM_IN);
+
+	buf_set_u32(reg_params[0].value, 0, 32, nand->data);
+	buf_set_u32(reg_params[1].value, 0, 32, target_buf);
+	buf_set_u32(reg_params[2].value, 0, 32, size);
+
+	/* use alg to write data from work area to NAND chip */
+	retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
+			nand->copy_area->address,
+			nand->copy_area->address + sizeof(code) - 4,
+			1000, &algo);
+	if (retval != ERROR_OK)
+		LOG_ERROR("error executing hosted NAND write");
+
+	destroy_reg_param(&reg_params[0]);
+	destroy_reg_param(&reg_params[1]);
+	destroy_reg_param(&reg_params[2]);
+
+	return retval;
+}
+
+/* REVISIT do the same for bulk *read* too ... */
+


Property changes on: trunk/src/flash/arm_nandio.c
___________________________________________________________________
Name: svn:eol-style
   + native

Added: trunk/src/flash/arm_nandio.h
===================================================================
--- trunk/src/flash/arm_nandio.h	2009-09-02 17:34:35 UTC (rev 2662)
+++ trunk/src/flash/arm_nandio.h	2009-09-03 08:23:39 UTC (rev 2663)
@@ -0,0 +1,25 @@
+#ifndef __ARM_NANDIO_H
+#define  __ARM_NANDIO_H
+
+#include "nand.h"
+#include "binarybuffer.h"
+
+struct arm_nand_data {
+	/* target is proxy for some ARM core */
+	struct target_s		*target;
+
+	/* copy_area holds write-to-NAND loop and data to write */
+	struct working_area_s	*copy_area;
+
+	/* chunk_size == page or ECC unit */
+	unsigned		chunk_size;
+
+	/* data == where to write the data */
+	uint32_t		data;
+
+	/* currently implicit:  data width == 8 bits (not 16) */
+};
+
+int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size);
+
+#endif  /* __ARM_NANDIO_H */


Property changes on: trunk/src/flash/arm_nandio.h
___________________________________________________________________
Name: svn:eol-style
   + native

Modified: trunk/src/flash/davinci_nand.c
===================================================================
--- trunk/src/flash/davinci_nand.c	2009-09-02 17:34:35 UTC (rev 2662)
+++ trunk/src/flash/davinci_nand.c	2009-09-03 08:23:39 UTC (rev 2663)
@@ -28,7 +28,7 @@
 #include "config.h"
 #endif
 
-#include "nand.h"
+#include "arm_nandio.h"
 
 
 enum ecc {
@@ -51,6 +51,9 @@
 	uint32_t		cmd;		/* with CLE */
 	uint32_t		addr;		/* with ALE */
 
+	/* write acceleration */
+	struct arm_nand_data	io;
+
 	/* page i/o for the relevant flavor of hardware ECC */
 	int (*read_page)(struct nand_device_s *nand, uint32_t page,
 			uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
@@ -181,7 +184,7 @@
 	return ERROR_OK;
 }
 
-/* REVISIT a bit of native code should let block I/O be MUCH faster */
+/* REVISIT a bit of native code should let block reads be MUCH faster */
 
 static int davinci_read_block_data(struct nand_device_s *nand,
 		uint8_t *data, int data_size)
@@ -223,10 +226,17 @@
 	target_t *target = info->target;
 	uint32_t nfdata = info->data;
 	uint32_t tmp;
+	int status;
 
 	if (!halted(target, "write_block"))
 		return ERROR_NAND_OPERATION_FAILED;
 
+	/* try the fast way first */
+	status = arm_nandwrite(&info->io, data, data_size);
+	if (status != ERROR_NAND_NO_BUFFER)
+		return status;
+
+	/* else do it slowly */
 	while (data_size >= 4) {
 		tmp = le_to_h_u32(data);
 		target_write_u32(target, nfdata, tmp);
@@ -285,6 +295,12 @@
 		memset(oob, 0x0ff, oob_size);
 	}
 
+	/* REVISIT avoid wasting SRAM:  unless nand->use_raw is set,
+	 * use 512 byte chunks.  Read side support will often want
+	 * to include oob_size ...
+	 */
+	info->io.chunk_size = nand->page_size;
+
 	status = info->write_page(nand, page, data, data_size, oob, oob_size);
 	free(ooballoc);
 	return status;
@@ -700,6 +716,9 @@
 
 	nand->controller_priv = info;
 
+	info->io.target = target;
+	info->io.data = info->data;
+
 	/* NOTE:  for now we don't do any error correction on read.
 	 * Nothing else in OpenOCD currently corrects read errors,
 	 * and in any case it's *writing* that we care most about.

Modified: trunk/src/flash/nand.h
===================================================================
--- trunk/src/flash/nand.h	2009-09-02 17:34:35 UTC (rev 2662)
+++ trunk/src/flash/nand.h	2009-09-03 08:23:39 UTC (rev 2663)
@@ -223,5 +223,6 @@
 #define		ERROR_NAND_OPERATION_NOT_SUPPORTED	(-1103)
 #define		ERROR_NAND_DEVICE_NOT_PROBED	(-1104)
 #define		ERROR_NAND_ERROR_CORRECTION_FAILED	(-1105)
+#define		ERROR_NAND_NO_BUFFER			(-1106)
 
 #endif /* NAND_H */

Modified: trunk/src/flash/orion_nand.c
===================================================================
--- trunk/src/flash/orion_nand.c	2009-09-02 17:34:35 UTC (rev 2662)
+++ trunk/src/flash/orion_nand.c	2009-09-03 08:23:39 UTC (rev 2663)
@@ -26,16 +26,16 @@
 #include "config.h"
 #endif
 
-#include "nand.h"
+#include "arm_nandio.h"
 #include "armv4_5.h"
-#include "binarybuffer.h"
 
 
 typedef struct orion_nand_controller_s
 {
 	struct target_s	*target;
-	working_area_t *copy_area;
 
+	struct arm_nand_data	io;
+
 	uint32_t		cmd;
 	uint32_t		addr;
 	uint32_t		data;
@@ -99,78 +99,14 @@
 static int orion_nand_fast_block_write(struct nand_device_s *device, uint8_t *data, int size)
 {
 	orion_nand_controller_t *hw = device->controller_priv;
-	target_t *target = hw->target;
-	armv4_5_algorithm_t algo;
-	reg_param_t reg_params[3];
-	uint32_t target_buf;
 	int retval;
 
-	static const uint32_t code[] = {
-		0xe4d13001,	/* ldrb	r3, [r1], #1	*/
-		0xe5c03000,	/* strb	r3, [r0]	*/
-		0xe2522001,	/* subs	r2, r2, #1	*/
-		0x1afffffb,	/* bne	0		*/
-		0xeafffffe,	/* b	.		*/
-	};
-	int code_size = sizeof(code);
+	hw->io.chunk_size = device->page_size;
 
-	if (!hw->copy_area) {
-		uint8_t code_buf[code_size];
-		int i;
+	retval = arm_nandwrite(&hw->io, data, size);
+	if (retval == ERROR_NAND_NO_BUFFER)
+		retval = orion_nand_slow_block_write(device, data, size);
 
-		/* make sure we have a working area */
-		if (target_alloc_working_area(target,
-					      code_size + device->page_size,
-					      &hw->copy_area) != ERROR_OK)
-		{
-			return orion_nand_slow_block_write(device, data, size);
-		}
-
-		/* copy target instructions to target endianness */
-		for (i = 0; i < code_size/4; i++)
-			target_buffer_set_u32(target, code_buf + i*4, code[i]);
-
-		/* write code to working area */
-                retval = target_write_memory(target,
-					hw->copy_area->address,
-					4, code_size/4, code_buf);
-		if (retval != ERROR_OK)
-			return retval;
-	}
-
-	/* copy data to target's memory */
-	target_buf = hw->copy_area->address + code_size;
-	retval = target_bulk_write_memory(target, target_buf, size/4, data);
-	if (retval == ERROR_OK && size & 3) {
-		retval = target_write_memory(target,
-					target_buf + (size & ~3),
-					1, size & 3, data + (size & ~3));
-	}
-	if (retval != ERROR_OK)
-		return retval;
-
-	algo.common_magic = ARMV4_5_COMMON_MAGIC;
-	algo.core_mode = ARMV4_5_MODE_SVC;
-	algo.core_state = ARMV4_5_STATE_ARM;
-
-	init_reg_param(&reg_params[0], "r0", 32, PARAM_IN);
-	init_reg_param(&reg_params[1], "r1", 32, PARAM_IN);
-	init_reg_param(&reg_params[2], "r2", 32, PARAM_IN);
-
-	buf_set_u32(reg_params[0].value, 0, 32, hw->data);
-	buf_set_u32(reg_params[1].value, 0, 32, target_buf);
-	buf_set_u32(reg_params[2].value, 0, 32, size);
-
-	retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
-					hw->copy_area->address,
-					hw->copy_area->address + code_size - 4,
-					1000, &algo);
-	if (retval != ERROR_OK)
-		LOG_ERROR("error executing hosted NAND write");
-
-	destroy_reg_param(&reg_params[0]);
-	destroy_reg_param(&reg_params[1]);
-	destroy_reg_param(&reg_params[2]);
 	return retval;
 }
 
@@ -224,6 +160,9 @@
 	hw->cmd = base + (1 << cle);
 	hw->addr = base + (1 << ale);
 
+	hw->io.target = hw->target;
+	hw->io.data = hw->data;
+
 	return ERROR_OK;
 }
 

[Openocd-svn] r2662 - trunk/tcl/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-02 19:34:35 +0200 (Wed, 02 Sep 2009)
New Revision: 2662

Added:
   trunk/tcl/target/ar71xx.cfg
Log:
David Claffey <dnc...@gm...> tested with the Atheros reference design "PB44"

Added: trunk/tcl/target/ar71xx.cfg
===================================================================
--- trunk/tcl/target/ar71xx.cfg	2009-09-02 00:17:39 UTC (rev 2661)
+++ trunk/tcl/target/ar71xx.cfg	2009-09-02 17:34:35 UTC (rev 2662)
@@ -0,0 +1,56 @@
+# Atheros AR71xx MIPS 24Kc SoC.
+# tested on PB44 refererence board
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+reset_config trst_and_srst
+
+set CHIPNAME ar71xx
+
+jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1
+
+set TARGETNAME [format "%s.cpu" $CHIPNAME]
+target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME
+
+$TARGETNAME configure -event reset-init {
+	#setup PLL to lowest common denominator 300/300/150 setting
+	mww 0xb8050000 0x000f40a3	# reset val + CPU:3 DDR:3 AHB:0
+	mww 0xb8050000 0x800f40a3	# send to PLL
+
+	#next command will reset for PLL changes to take effect
+	mww 0xb8050008 3		# set reset_switch and clock_switch (resets SoC)
+	reset halt     			# let openocd know that it is in the reset state
+
+	#initialize_pll
+	mww 0xb8050000 0x800f0080	# set sw_update bit
+	mww 0xb8050008 0		# clear reset_switch bit
+	mww 0xb8050000 0x800f00e8       # clr pwrdwn & bypass
+	mww 0xb8050008 1		# set clock_switch bit
+	sleep 1                         # wait for lock
+	
+	# Setup DDR config and flash mapping
+	mww 0xb8000000 0xefbc8cd0       # DDR cfg cdl val (rst: 0x5bfc8d0)
+	mww 0xb8000004 0x8e7156a2       # DDR cfg2 cdl val (rst: 0x80d106a8)
+	
+	mww 0xb8000010 8		# force precharge all banks
+	mww 0xb8000010 1 		# force EMRS update cycle
+	mww 0xb800000c 0                # clr ext. mode register
+	mww 0xb8000010 2 		# force auto refresh all banks
+	mww 0xb8000010 8		# force precharge all banks
+	mww 0xb8000008 0x31             # set DDR mode value CAS=3
+	mww 0xb8000010 1 		# force EMRS update cycle
+	mww 0xb8000014 0x461b           # DDR refresh value
+	mww 0xb8000018 0xffff           # DDR Read Data This Cycle value (16bit: 0xffff)
+	mww 0xb800001c 0x7              # delay added to the DQS line (normal = 7)
+	mww 0xb8000020 0
+	mww 0xb8000024 0
+	mww 0xb8000028 0
+}	
+
+# setup working area somewhere in RAM
+$TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000
+
+# serial SPI capable flash
+# flash bank <driver> <base> <size> <chip_width> <bus_width>
+


Property changes on: trunk/tcl/target/ar71xx.cfg
___________________________________________________________________
Name: svn:eol-style
   + native

[Openocd-svn] r2661 - in trunk/tcl/chip: atmel/at91 st/stm32

[<du...@ma...>]

Author: duane
Date: 2009-09-02 02:17:39 +0200 (Wed, 02 Sep 2009)
New Revision: 2661

Modified:
   trunk/tcl/chip/atmel/at91/at91sam7x128.tcl
   trunk/tcl/chip/atmel/at91/at91sam7x256.tcl
   trunk/tcl/chip/st/stm32/stm32.tcl
Log:
Crusty Code fixes from the tcl directory re-arragements

Modified: trunk/tcl/chip/atmel/at91/at91sam7x128.tcl
===================================================================
--- trunk/tcl/chip/atmel/at91/at91sam7x128.tcl	2009-09-01 10:08:41 UTC (rev 2660)
+++ trunk/tcl/chip/atmel/at91/at91sam7x128.tcl	2009-09-02 00:17:39 UTC (rev 2661)
@@ -1,7 +1,7 @@
-source [find tcl/bitsbytes.tcl]
-source [find tcl/cpu/arm/arm7tdmi.tcl]
-source [find tcl/memory.tcl]
-source [find tcl/mmr_helpers.tcl]
+source [find bitsbytes.tcl]
+source [find cpu/arm/arm7tdmi.tcl]
+source [find memory.tcl]
+source [find mmr_helpers.tcl]
 
 set CHIP_MAKER  atmel
 set CHIP_FAMILY at91sam7
@@ -122,7 +122,7 @@
 set AT91C_ID(30) IRQ0
 set AT91C_ID(31) IRQ1
 
-source [find tcl/chip/atmel/at91/aic.tcl]
-source [find tcl/chip/atmel/at91/usarts.tcl]
-source [find tcl/chip/atmel/at91/pmc.tcl]
-source [find tcl/chip/atmel/at91/rtt.tcl]
+source [find chip/atmel/at91/aic.tcl]
+source [find chip/atmel/at91/usarts.tcl]
+source [find chip/atmel/at91/pmc.tcl]
+source [find chip/atmel/at91/rtt.tcl]

Modified: trunk/tcl/chip/atmel/at91/at91sam7x256.tcl
===================================================================
--- trunk/tcl/chip/atmel/at91/at91sam7x256.tcl	2009-09-01 10:08:41 UTC (rev 2660)
+++ trunk/tcl/chip/atmel/at91/at91sam7x256.tcl	2009-09-02 00:17:39 UTC (rev 2661)
@@ -1,7 +1,7 @@
-source [find tcl/bitsbytes.tcl]
-source [find tcl/cpu/arm/arm7tdmi.tcl]
-source [find tcl/memory.tcl]
-source [find tcl/mmr_helpers.tcl]
+source [find bitsbytes.tcl]
+source [find cpu/arm/arm7tdmi.tcl]
+source [find memory.tcl]
+source [find mmr_helpers.tcl]
 
 set CHIP_MAKER  atmel
 set CHIP_FAMILY at91sam7
@@ -120,7 +120,7 @@
 set AT91C_ID(31)   "IRQ1"
 
 
-source [find tcl/chip/atmel/at91/aic.tcl]
-source [find tcl/chip/atmel/at91/usarts.tcl]
-source [find tcl/chip/atmel/at91/pmc.tcl]
-source [find tcl/chip/atmel/at91/rtt.tcl]
+source [find chip/atmel/at91/aic.tcl]
+source [find chip/atmel/at91/usarts.tcl]
+source [find chip/atmel/at91/pmc.tcl]
+source [find chip/atmel/at91/rtt.tcl]

Modified: trunk/tcl/chip/st/stm32/stm32.tcl
===================================================================
--- trunk/tcl/chip/st/stm32/stm32.tcl	2009-09-01 10:08:41 UTC (rev 2660)
+++ trunk/tcl/chip/st/stm32/stm32.tcl	2009-09-02 00:17:39 UTC (rev 2661)
@@ -1,7 +1,7 @@
-source [find tcl/bitsbytes.tcl]
-source [find tcl/cpu/arm/cortex_m3.tcl]
-source [find tcl/memory.tcl]
-source [find tcl/mmr_helpers.tcl]
+source [find bitsbytes.tcl]
+source [find cpu/arm/cortex_m3.tcl]
+source [find memory.tcl]
+source [find mmr_helpers.tcl]
 
-source [find tcl/chip/st/stm32/stm32_regs.tcl]
-source [find tcl/chip/st/stm32/stm32_rcc.tcl]
+source [find chip/st/stm32/stm32_regs.tcl]
+source [find chip/st/stm32/stm32_rcc.tcl]

[Openocd-svn] r2660 - trunk/src/flash

[ntfreak at B. <nt...@ma...>]

Author: ntfreak
Date: 2009-09-01 12:08:41 +0200 (Tue, 01 Sep 2009)
New Revision: 2660

Modified:
   trunk/src/flash/stellaris.c
Log:
- fixes the incorrect info msg displayed during stellaris flash programming.

Modified: trunk/src/flash/stellaris.c
===================================================================
--- trunk/src/flash/stellaris.c	2009-09-01 10:08:00 UTC (rev 2659)
+++ trunk/src/flash/stellaris.c	2009-09-01 10:08:41 UTC (rev 2660)
@@ -917,8 +917,8 @@
 		buf_set_u32(reg_params[0].value, 0, 32, source->address);
 		buf_set_u32(reg_params[1].value, 0, 32, address);
 		buf_set_u32(reg_params[2].value, 0, 32, 4*thisrun_count);
-		LOG_INFO("Algorithm flash write %" PRIi32 " words to 0x%" PRIx32 ", %" PRIi32 " remaining", thisrun_count, address, wcount);
-		LOG_DEBUG("Algorithm flash write %" PRIi32 " words to 0x%" PRIx32 ", %" PRIi32 " remaining", thisrun_count, address, wcount);
+		LOG_INFO("Algorithm flash write %" PRIi32 " words to 0x%" PRIx32 ", %" PRIi32 " remaining", thisrun_count, address, (wcount - thisrun_count));
+		LOG_DEBUG("Algorithm flash write %" PRIi32 " words to 0x%" PRIx32 ", %" PRIi32 " remaining", thisrun_count, address, (wcount - thisrun_count));
 		if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params, write_algorithm->address, write_algorithm->address + sizeof(stellaris_write_code)-10, 10000, &armv7m_info)) != ERROR_OK)
 		{
 			LOG_ERROR("error executing stellaris flash write algorithm");

[Openocd-svn] r2659 - trunk/src/target

[ntfreak at B. <nt...@ma...>]

Author: ntfreak
Date: 2009-09-01 12:08:00 +0200 (Tue, 01 Sep 2009)
New Revision: 2659

Modified:
   trunk/src/target/cortex_m3.c
Log:
- fix a regression when using cortex_m3 emulated dcc channel


Modified: trunk/src/target/cortex_m3.c
===================================================================
--- trunk/src/target/cortex_m3.c	2009-08-31 12:21:12 UTC (rev 2658)
+++ trunk/src/target/cortex_m3.c	2009-09-01 10:08:00 UTC (rev 2659)
@@ -105,7 +105,7 @@
 	uint32_t dcrdr;
 
 	/* because the DCB_DCRDR is used for the emulated dcc channel
-	 * we gave to save/restore the DCB_DCRDR when used */
+	 * we have to save/restore the DCB_DCRDR when used */
 
 	mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
 
@@ -119,8 +119,13 @@
 	dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
 	dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
 
-	mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr);
 	retval = swjdp_transaction_endcheck(swjdp);
+
+	/* restore DCB_DCRDR - this needs to be in a seperate
+	 * transaction otherwise the emulated DCC channel breaks */
+	if (retval == ERROR_OK)
+		retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
+
 	return retval;
 }
 
@@ -130,7 +135,7 @@
 	uint32_t dcrdr;
 
 	/* because the DCB_DCRDR is used for the emulated dcc channel
-	 * we gave to save/restore the DCB_DCRDR when used */
+	 * we have to save/restore the DCB_DCRDR when used */
 
 	mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
 
@@ -144,12 +149,16 @@
 	dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
 	dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
 
-	mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr);
 	retval = swjdp_transaction_endcheck(swjdp);
+
+	/* restore DCB_DCRDR - this needs to be in a seperate
+	 * transaction otherwise the emulated DCC channel breaks */
+	if (retval == ERROR_OK)
+		retval = mem_ap_write_atomic_u32(swjdp, DCB_DCRDR, dcrdr);
+
 	return retval;
 }
 
-
 int cortex_m3_write_debug_halt_mask(target_t *target, uint32_t mask_on, uint32_t mask_off)
 {
 	/* get pointers to arch-specific information */
@@ -668,7 +677,7 @@
 		/* Single step past breakpoint at current address */
 		if ((breakpoint = breakpoint_find(target, resume_pc)))
 		{
-			LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)", 
+			LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 " (ID: %d)",
 					  breakpoint->address,
 					  breakpoint->unique_id );
 			cortex_m3_unset_breakpoint(target, breakpoint);
@@ -971,7 +980,7 @@
 		breakpoint->set = 0x11; /* Any nice value but 0 */
 	}
 
-	LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", 
+	LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
 			  breakpoint->unique_id,
 			  (int)(breakpoint->type),
 			  breakpoint->address,
@@ -995,7 +1004,7 @@
 		return ERROR_OK;
 	}
 
-	LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)", 
+	LOG_DEBUG("BPID: %d, Type: %d, Address: 0x%08" PRIx32 " Length: %d (set=%d)",
 			  breakpoint->unique_id,
 			  (int)(breakpoint->type),
 			  breakpoint->address,
@@ -1165,7 +1174,7 @@
 				  watchpoint->unique_id );
 		return ERROR_OK;
 	}
-	LOG_DEBUG("Watchpoint (ID: %d) address: 0x%08" PRIx32 " set=%d ", 
+	LOG_DEBUG("Watchpoint (ID: %d) address: 0x%08" PRIx32 " set=%d ",
 			  watchpoint->unique_id, watchpoint->address, watchpoint->set );
 	return ERROR_OK;
 
@@ -1185,7 +1194,7 @@
 		return ERROR_OK;
 	}
 
-	LOG_DEBUG("Watchpoint (ID: %d) address: 0x%08" PRIx32 " set=%d ", 
+	LOG_DEBUG("Watchpoint (ID: %d) address: 0x%08" PRIx32 " set=%d ",
 			  watchpoint->unique_id, watchpoint->address,watchpoint->set );
 
 	dwt_num = watchpoint->set - 1;

[Openocd-svn] r2658 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-08-31 14:21:12 +0200 (Mon, 31 Aug 2009)
New Revision: 2658

Modified:
   trunk/src/target/arm_disassembler.c
Log:
Warning fix

Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c	2009-08-31 09:06:01 UTC (rev 2657)
+++ trunk/src/target/arm_disassembler.c	2009-08-31 12:21:12 UTC (rev 2658)
@@ -445,6 +445,9 @@
 	unsigned rn = (opcode >> 16) & 0xf;
 	char *type, *rot;
 
+	/* GCC 'uninitialized warning removal' */
+	type = rot = NULL;
+	
 	switch ((opcode >> 24) & 0x3) {
 	case 0:
 		type = "B16";

[Openocd-svn] r2657 - trunk/tcl/board

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-31 11:06:01 +0200 (Mon, 31 Aug 2009)
New Revision: 2657

Added:
   trunk/tcl/board/at91sam9g20-ek.cfg
Log:
Gary Carlson <gca...@ca...> config file

Added: trunk/tcl/board/at91sam9g20-ek.cfg
===================================================================
--- trunk/tcl/board/at91sam9g20-ek.cfg	2009-08-31 06:02:01 UTC (rev 2656)
+++ trunk/tcl/board/at91sam9g20-ek.cfg	2009-08-31 09:06:01 UTC (rev 2657)
@@ -0,0 +1,204 @@
+#################################################################################################
+#												#
+# Author: Gary Carlson (gca...@ca...)						#
+# Generated for Atmel AT91SAM9G20-EK evaluation board using Atmel SAM-ICE (J-Link) version 8.	#
+#												#
+#################################################################################################
+
+# Define basic characteristics for the CPU.  The AT91SAM9G20 processor is a subtle variant of
+# the AT91SAM9260 and shares the same tap ID as it.
+
+set _CHIPNAME at91sam9g20
+set _ENDIAN little
+set _CPUTAPID 0x0792603f
+
+# Set reset type.  Note that the AT91SAM9G20-EK board has the trst signal disconnected.  In theory this script
+# therefore should require "srst_only".  With some J-Link debuggers at least, "srst_only" causes a temporary USB
+# communication fault.  This appears to be more likely attributed to an internal proprietary firmware quirk inside the
+# dongle itself.  Using "trst_and_srst" works fine, however.  So if you can't beat them -- join them.  If you are using
+# something other the a J-Link dongle you may be able to change this back to "srst_only".
+
+reset_config trst_and_srst
+
+# Set up the CPU and generate a new jtag tap for AT91SAM9G20.
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# Use caution changing the delays listed below.  These seem to be affected by the board and type of
+# debugger dongle.  A value of 200 ms seems to work reliably for the configuration listed in the file header above.
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+# Set fallback clock to 1/6 of worst-case clock speed (which would be the 32.768 kHz slow clock).
+
+jtag_rclk 5
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+
+# Establish internal SRAM memory work areas that are important to pre-bootstrap loaders, etc.  The
+# AT91SAM9G20 has two SRAM areas, one starting at 0x00200000 and the other starting at 0x00300000.
+# Both areas are 16 kB long.
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 1
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00300000 -work-area-size 0x4000 -work-area-backup 1
+
+# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
+# AT91SAM9 family, the microcontroller is a lump on a log without initialization.  Because this family has
+# some powerful features, we want to have a special function that handles "reset init".  To do this we declare
+# an event handler where these special activities can take place.
+
+scan_chain
+$_TARGETNAME configure -event reset-init {at91sam9g20_init}
+
+# NandFlash configuration and definition
+# Future TBD
+
+proc read_register {register} {
+        set result ""
+        ocd_mem2array result 32 $register 1
+        return $result(0)
+}
+
+proc at91sam9g20_init { } {
+	
+	# At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz).  To shift over to a normal clock requires
+	# a number of steps that must be carefully performed.  The process outline below follows the
+	# recommended procedure outlined in the AT91SAM9G20 technical manual.
+	#
+	# Several key and very important things to keep in mind:
+	# The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts.  This
+	# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur.  The processor
+	# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.
+
+	jtag_khz 2			# Slow-speed oscillator enabled at reset, so run jtag speed slow.
+	halt				# Make sure processor is halted, or error will result in following steps.
+	mww 0xfffffd08 0xa5000501	# RSTC_MR : enable user reset.
+	mww 0xfffffd44 0x00008000	# WDT_MR : disable watchdog.
+
+	# Enable the main 18.432 MHz oscillator in CKGR_MOR register.
+	# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
+
+	mww 0xfffffc20 0x00004001
+	while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }
+
+	# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
+	# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
+
+	mww 0xfffffc28 0x202a3f01
+	while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }
+
+	# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
+	# Wait for MCKRDY signal from PMC_SR to assert.
+
+	mww 0xfffffc30 0x00000101
+	while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
+	
+	# Now change PMC_MCKR register to select PLLA.
+	# Wait for MCKRDY signal from PMC_SR to assert.
+
+	mww 0xfffffc30 0x00001302
+	while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
+
+	# Processor and master clocks are now operating and stable at maximum frequency possible:
+	#	-> MCLK = 132.096 MHz
+	#	-> PCLK = 396.288 MHz
+
+	# Switch over to adaptive clocking.
+
+	jtag_khz 0
+
+	# Enable faster DCC downloads.
+
+	arm7_9 dcc_downloads enable
+
+	# To be able to use external SDRAM, several peripheral configuration registers must
+	# be modified.  The first change is made to PIO_ASR to select peripheral functions
+	# for D15 through D31.  The second change is made to the PIO_PDR register to disable
+	# this for D15 through D31.
+
+	mww 0xfffff870 0xffff0000
+	mww 0xfffff804 0xffff0000
+
+	# The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
+	# using CS1.  Additionally we want CS3 assigned to NandFlash.  Also VDDIO is connected physically on
+	# the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.
+
+	mww 0xffffef1c 0x000100a
+
+	# The AT91SAM9G20-EK evaluation board has built-in NandFlash.  The exact physical timing characteristics
+	# for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
+	# four registers in order:  SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.
+
+	mww 0xffffec30 0x00020002
+	mww 0xffffec34 0x04040404
+	mww 0xffffec38 0x00070007
+	mww 0xffffec3c 0x00030003
+
+	# Identify NandFlash bank 0.  Disabled at the moment because a memory driver is not yet complete.
+
+#	nand probe 0
+
+	# Now setup SDRAM.  This is tricky and configuration is very important for reliability!  The current calculations
+	# are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks).  If you use this file as a reference
+	# for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted
+	# into the SDRAM_CR register.  Using the memory datasheet for the -75 grade part and assuming a master clock
+	# of 132.096 MHz then the SDCLK period is equal to 7.6 ns.  This means the device requires:
+	#
+	#	CAS latency = 3 cycles
+	#	TXSR = 10 cycles
+	#	TRAS = 6 cycles
+	#	TRCD = 3 cycles
+	#	TRP = 3 cycles
+	#	TRC = 9 cycles
+	#	TWR = 2 cycles
+	#	9 column, 13 row, 4 banks
+	#	refresh equal to or less then 7.8 us for commerical/industrial rated devices
+	#
+	#	Thus SDRAM_CR = 0xa6339279
+
+	mww 0xffffea08 0xa6339279
+
+	# Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into
+	# the starting memory location for the SDRAM.
+
+	mww 0xffffea00 0x00000001
+	mww 0x20000000 0
+
+	# Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero
+	# value into the starting memory location for the SDRAM.
+
+	mww 0xffffea00 0x00000002
+	mww 0x20000000 0
+
+	# Now issue an 'Auto-Refresh' command through the SDRAMC_MR register.  Follow this operation by writing
+	# zero values eight times into the starting memory location for the SDRAM.
+
+	mww 0xffffea00 0x4
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+	mww 0x20000000 0
+
+	# Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the
+	# the starting memory location for the SDRAM.
+
+	mww 0xffffea00 0x3
+	mww 0x20000000 0
+
+	# Signal normal mode using the SDRAMC_MR register and follow with a zero value write the the starting
+	# memory location for the SDRAM.
+
+	mww 0xffffea00 0x0
+	mww 0x20000000 0
+
+	# Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).
+
+	mww 0xffffea04 0x0000039c
+}
+


Property changes on: trunk/tcl/board/at91sam9g20-ek.cfg
___________________________________________________________________
Name: svn:eol-style
   + native

[Openocd-svn] r2656 - trunk/tcl/board

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-31 08:02:01 +0200 (Mon, 31 Aug 2009)
New Revision: 2656

Added:
   trunk/tcl/board/propox_mmnet1001.cfg
Log:
Ferdinand Postema <fer...@po...> config script for the MMnet1001 module from Propox.

Added: trunk/tcl/board/propox_mmnet1001.cfg
===================================================================
--- trunk/tcl/board/propox_mmnet1001.cfg	2009-08-30 21:12:50 UTC (rev 2655)
+++ trunk/tcl/board/propox_mmnet1001.cfg	2009-08-31 06:02:01 UTC (rev 2656)
@@ -0,0 +1,83 @@
+
+## Chip:
+set CHIPNAME at91sam9260
+set CPUTAPID 0x0792603f
+set ENDIAN little
+source [find target/at91sam9260.cfg]
+
+$_TARGETNAME configure -event reset-init {at91sam_init}
+
+
+proc at91sam_init { } {
+	
+	# at reset chip runs at 32 kHz => 1/8 * 32 kHz = 4 kHz
+	jtag_rclk 4
+
+	# Enable user reset and disable watchdog
+	mww 0xfffffd08 0xa5000501         # RSTC_MR : enable user reset
+	mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
+
+	# Oscillator setup
+	mww 0xfffffc20 0x00004001         # CKGR_MOR : enable the main oscillator (18.432 MHz)
+	sleep 20                          # wait 20 ms
+	mww 0xfffffc30 0x00000001         # PMC_MCKR : switch to main oscillator
+	sleep 10                          # wait 10 ms
+
+	# now we are running at 18.432 MHz kHz => 1/8 * 18.432 MHz = 2.304 MHz
+	jtag_rclk 2000
+
+	mww 0xfffffc28 0x2060bf09         # CKGR_PLLAR: Set PLLA Register for 198,656MHz
+	sleep 20                          # wait 20 ms
+	mww 0xfffffc2c 0x207c3f0c         # CKGR_PLLBR: Set PLLB Register for USB usage (USB_CLK = 48 MHz)
+	sleep 10                          # wait 10 ms
+	mww 0xfffffc30 0x00000101         # PMC_MCKR : Select prescaler
+	sleep 10                          # wait 10 ms
+	mww 0xfffffc30 0x00000102         # PMC_MCKR : Clock from PLLA is selected
+	sleep 10                          # wait 10 ms
+
+	# now we are running at 198.656 MHz kHz => full speed jtag
+	jtag_rclk 30000
+
+	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
+
+	# Configure PIO Controller for SDRAM data-lines D16-D31
+	# PC16-PC31 = Peripheral A: D16-D32
+	mww 0xfffff844 0xffff0000	# Interrupt Disable
+	mww 0xfffff854 0xffff0000	# Multi-Drive Disable
+	mww 0xfffff860 0xffff0000	# Pull-Up Disable
+	mww 0xfffff870 0xffff0000	# PIO_ASR : Select peripheral A function for D15..D31
+	mww 0xfffff804 0xffff0000	# PIO_PDR : Disable PIO function for D15..D31 (Peripheral function enable)
+	mww 0xfffffc10 0x00000010	# Enable PIO-C Clock in PMC (PID=4)
+
+	# SD-Ram setup
+	mww 0xffffef1c 0x2			# EBI_CSA : Assign EBI Chip Select 1 to SDRAM
+	mww 0xffffea08 0x85227259	# SDRAMC_CR : Configure SDRAM (IS42S32160A: 4M Words x 32 Bits x 4 Banks (512-Mbit))
+	mww 0xffffea00 0x1			# SDRAMC_MR : issue a NOP command
+	mww 0x20000000 0
+	mww 0xffffea00 0x2			# SDRAMC_MR : issue an 'All Banks Precharge' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			# SDRAMC_MR : issue an 'Auto-Refresh' command (1st)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			# SDRAMC_MR : issue an 'Auto-Refresh' command (2nd)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			# SDRAMC_MR : issue an 'Auto-Refresh' command (3th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			# SDRAMC_MR : issue an 'Auto-Refresh' command (4th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			# SDRAMC_MR : issue an 'Auto-Refresh' command (5th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			# SDRAMC_MR : issue an 'Auto-Refresh' command (6th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			# SDRAMC_MR : issue an 'Auto-Refresh' command (7th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x4			# SDRAMC_MR : issue an 'Auto-Refresh' command (8th)
+	mww 0x20000000 0
+	mww 0xffffea00 0x3			# SDRAMC_MR : issue a 'Load Mode Register' command
+	mww 0x20000000 0
+	mww 0xffffea00 0x0			# SDRAMC_MR : Normal Mode
+	mww 0x20000000 0
+	mww 0xFFFFEA04 0x30d		# SDRAM Refresh Time Register
+								#  datasheet: 8k refresh cycles / 64 ms
+								#  MCLK / (8*1024 / 64e-3) = 100e6 / 128000 = 781 = 0x30d
+
+}


Property changes on: trunk/tcl/board/propox_mmnet1001.cfg
___________________________________________________________________
Name: svn:eol-style
   + native

[Openocd-svn] r2655 - trunk/src/flash

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-30 23:12:50 +0200 (Sun, 30 Aug 2009)
New Revision: 2655

Modified:
   trunk/src/flash/davinci_nand.c
Log:
David Brownell <da...@pa...> Minor code bugfix: check right variable.
Via code review by Steve Grubb <sg...@re...>?\194?\160

Almost innocuous; this is value is checked later, this
check being wrong would make it check stack garbage.

Modified: trunk/src/flash/davinci_nand.c
===================================================================
--- trunk/src/flash/davinci_nand.c	2009-08-30 20:08:07 UTC (rev 2654)
+++ trunk/src/flash/davinci_nand.c	2009-08-30 21:12:50 UTC (rev 2655)
@@ -663,7 +663,7 @@
 	}
 
 	aemif = strtoul(argv[4], &ep, 0);
-	if (*ep || chip == 0 || chip == ULONG_MAX) {
+	if (*ep || aemif == 0 || aemif == ULONG_MAX) {
 		LOG_ERROR("Invalid AEMIF controller address %s", argv[4]);
 		goto fail;
 	}

[Openocd-svn] r2654 - trunk/src/helper

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-30 22:08:07 +0200 (Sun, 30 Aug 2009)
New Revision: 2654

Modified:
   trunk/src/helper/startup.tcl
Log:
Dirk Behme <dir...@go...> Fix typo in help text. It has to be 'production_test' instead of 'production' here.

Modified: trunk/src/helper/startup.tcl
===================================================================
--- trunk/src/helper/startup.tcl	2009-08-30 20:05:40 UTC (rev 2653)
+++ trunk/src/helper/startup.tcl	2009-08-30 20:08:07 UTC (rev 2654)
@@ -250,7 +250,7 @@
 proc production_test {} {
 	puts "Imagine nifty test procedure having run to completion here."
 }
-add_help_text production "Runs test procedure. Throws exception if procedure failed. Prints progress messages. Implement in target script."
+add_help_text production_test "Runs test procedure. Throws exception if procedure failed. Prints progress messages. Implement in target script."
 
 add_help_text cpu "<name> - prints out target options and a comment on CPU which matches name"
 

[Openocd-svn] r2653 - trunk/src/flash

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-30 22:05:40 +0200 (Sun, 30 Aug 2009)
New Revision: 2653

Modified:
   trunk/src/flash/stellaris.c
Log:
David Brownell <da...@pa...> Fix Sandstorm revision checking: right bits, right value!

Modified: trunk/src/flash/stellaris.c
===================================================================
--- trunk/src/flash/stellaris.c	2009-08-30 20:04:17 UTC (rev 2652)
+++ trunk/src/flash/stellaris.c	2009-08-30 20:05:40 UTC (rev 2653)
@@ -581,7 +581,7 @@
 		 * Parts before rev C0 used 15 MHz; some C0 parts use 15 MHz
 		 * (LM3S618), but some other C0 parts are 12 MHz (LM3S811).
 		 */
-		if (((did0 >> 16) & 0xff) <= 2) {
+		if (((did0 >> 8) & 0xff) < 2) {
 			stellaris_info->iosc_freq = 15000000;
 			stellaris_info->iosc_desc = " (±50%)";
 		}

[Openocd-svn] r2652 - trunk/src/flash

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-30 22:04:17 +0200 (Sun, 30 Aug 2009)
New Revision: 2652

Modified:
   trunk/src/flash/flash.c
Log:
David Brownell <da...@pa...> Remove duplicate check for flash write status.
Via code review by Steve Grubb <sg...@re...>?\194?\160

Also minor fixes for the message from "fill":  the byte
count is unsigned, not signed; and more importantly,
print the real number of bytes written

Modified: trunk/src/flash/flash.c
===================================================================
--- trunk/src/flash/flash.c	2009-08-30 17:32:56 UTC (rev 2651)
+++ trunk/src/flash/flash.c	2009-08-30 20:04:17 UTC (rev 2652)
@@ -708,15 +708,16 @@
 		image_close(&image);
 		return retvaltemp;
 	}
-	if (retval == ERROR_OK)
-	{
-		command_print(cmd_ctx,
-					  "wrote %" PRIu32 " byte from file %s in %s (%f kb/s)",
-					  written,
-					  args[0],
-					  duration_text,
-					  (float)written / 1024.0 / ((float)duration.duration.tv_sec + ((float)duration.duration.tv_usec / 1000000.0)));
-	}
+
+	float speed;
+
+	speed = written / 1024.0;
+	speed /= ((float)duration.duration.tv_sec
+			+ ((float)duration.duration.tv_usec / 1000000.0));
+	command_print(cmd_ctx,
+			"wrote %" PRIu32 " byte from file %s in %s (%f kb/s)",
+			written, args[0], duration_text, speed);
+
 	free(duration_text);
 
 	image_close(&image);
@@ -828,18 +829,15 @@
 		return retval;
 	}
 
-	if (err == ERROR_OK)
-	{
-		float speed;
-		speed = wrote / 1024.0;
-		speed/=((float)duration.duration.tv_sec + ((float)duration.duration.tv_usec / 1000000.0));
-		command_print(cmd_ctx,
-					  "wrote %" PRId32 " bytes to 0x%8.8" PRIx32 " in %s (%f kb/s)",
-					  count*wordsize,
-					  address,
-					  duration_text,
-					  speed);
-	}
+	float speed;
+
+	speed = wrote / 1024.0;
+	speed /= ((float)duration.duration.tv_sec
+			+ ((float)duration.duration.tv_usec / 1000000.0));
+	command_print(cmd_ctx,
+			"wrote %" PRIu32 " bytes to 0x%8.8" PRIx32 " in %s (%f kb/s)",
+			wrote, address, duration_text, speed);
+
 	free(duration_text);
 	return ERROR_OK;
 }

[Openocd-svn] r2651 - trunk/doc

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-30 19:32:56 +0200 (Sun, 30 Aug 2009)
New Revision: 2651

Modified:
   trunk/doc/openocd.texi
Log:
David Brownell <da...@pa...> Minor doc updates:

 - Itemize the list of private customization examples
  for openocd.cfg

 - Add "override defaults" as a customization, specifically
  for the work area (back it up or relocate it)

 - Highlight some work area location issues

Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-08-30 17:30:14 UTC (rev 2650)
+++ trunk/doc/openocd.texi	2009-08-30 17:32:56 UTC (rev 2651)
@@ -733,11 +733,15 @@
 When you write config files, separate the reusable parts
 (things every user of that interface, chip, or board needs)
 from ones specific to your environment and debugging approach.
+@itemize
 
+@item
 For example, a @code{gdb-attach} event handler that invokes
 the @command{reset init} command will interfere with debugging
 early boot code, which performs some of the same actions
 that the @code{reset-init} event handler does.
+
+@item
 Likewise, the @command{arm9tdmi vector_catch} command (or
 @cindex vector_catch
 its siblings @command{xscale vector_catch}
@@ -747,9 +751,16 @@
 along with messaging and tracing setup.
 (@xref{Software Debug Messages and Tracing}.)
 
+@item
+You might need to override some defaults.
+For example, you might need to move, shrink, or back up the target's
+work area if your application needs much SRAM.
+
+@item
 TCP/IP port configuration is another example of something which
 is environment-specific, and should only appear in
 a user config file.  @xref{TCP/IP Ports}.
+@end itemize
 
 @section Project-Specific Utilities
 
@@ -2614,9 +2625,12 @@
 which OpenOCD needs to know about.
 
 @item @code{-work-area-backup} (@option{0}|@option{1}) -- says
-whether the work area gets backed up; by default, it doesn't.
+whether the work area gets backed up; by default,
+@emph{it is not backed up.}
 When possible, use a working_area that doesn't need to be backed up,
 since performing a backup slows down operations.
+For example, the beginning of an SRAM block is likely to
+be used by most build systems, but the end is often unused.
 
 @item @code{-work-area-size} @var{size} -- specify/set the work area
 

[Openocd-svn] r2650 - in trunk: doc src/flash src/helper src/server src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-30 19:30:14 +0200 (Sun, 30 Aug 2009)
New Revision: 2650

Modified:
   trunk/doc/openocd.texi
   trunk/src/flash/at91sam7.c
   trunk/src/flash/orion_nand.c
   trunk/src/helper/startup.tcl
   trunk/src/server/gdb_server.c
   trunk/src/target/target.c
   trunk/src/target/target.h
Log:
David Brownell <da...@pa...> start phasing out integers as target IDs

Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-08-30 17:27:50 UTC (rev 2649)
+++ trunk/doc/openocd.texi	2009-08-30 17:30:14 UTC (rev 2650)
@@ -2365,6 +2365,10 @@
 Several commands let you examine the list of targets:
 
 @deffn Command {target count}
+@emph{Note: target numbers are deprecated; don't use them.
+They will be removed shortly after August 2010, including this command.
+Iterate target using @command{target names}, not by counting.}
+
 Returns the number of targets, @math{N}.
 The highest numbered target is @math{N - 1}.
 @example
@@ -2390,6 +2394,9 @@
 @end deffn
 
 @deffn Command {target number} number
+@emph{Note: target numbers are deprecated; don't use them.
+They will be removed shortly after August 2010, including this command.}
+
 The list of targets is numbered starting at zero.
 This command returns the name of the target at index @var{number}.
 @example
@@ -2711,8 +2718,7 @@
 all the targets you might use something like this:
 
 @example
-for @{ set x 0 @} @{ $x < [target count] @} @{ incr x @} @{
-    set name [target number $x]
+foreach name [target names] @{
     set y [$name cget -endian]
     set z [$name cget -type]
     puts [format "Chip %d is %s, Endian: %s, type: %s" \

Modified: trunk/src/flash/at91sam7.c
===================================================================
--- trunk/src/flash/at91sam7.c	2009-08-30 17:27:50 UTC (rev 2649)
+++ trunk/src/flash/at91sam7.c	2009-08-30 17:30:14 UTC (rev 2650)
@@ -20,20 +20,30 @@
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
 ****************************************************************************/
 
-/***************************************************************************************************************************************************************************************
+/***************************************************************************
 *
 * New flash setup command:
 *
-* flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
+* flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_id>
+*	[<chip_type> <banks>
+*	 <sectors_per_bank> <pages_per_sector>
+*	 <page_size> <num_nvmbits>
+*	 <ext_freq_khz>]
 *
 *   <ext_freq_khz> - MUST be used if clock is from external source,
-*                    CAN be used if main oscillator frequency is known (recomended)
+*                    CAN be used if main oscillator frequency is known (recommended)
 * Examples:
-*  flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 25000                   ==== RECOMENDED ============
-*  flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 25000    (auto-detection, except for clock)      ==== RECOMENDED ============
-*  flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 0                       ==== NOT RECOMENDED !!! ====
-*  flash bank at91sam7 0 0 0 0 0            (old style, full auto-detection)                    ==== NOT RECOMENDED !!! ====
-****************************************************************************************************************************************************************************************/
+* ==== RECOMMENDED (covers clock speed) ============
+*  flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 25000
+*			(if auto-detect fails; provides clock spec)
+*  flash bank at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 25000
+*			(auto-detect everything except the clock)
+* ==== NOT RECOMMENDED !!! (clock speed is not configured) ====
+*  flash bank at91sam7 0x00100000 0 0 4 $_TARGETNAME AT91SAM7XC256 1 16 64 256 3 0
+*			(if auto-detect fails)
+*  flash bank at91sam7 0 0 0 0 $_TARGETNAME
+*			(old style, auto-detect everything)
+****************************************************************************/
 
 #ifdef HAVE_CONFIG_H
 #include "config.h"
@@ -734,16 +744,6 @@
 	return ERROR_OK;
 }
 
-/***************************************************************************************************************************************************************************************
-# flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
-#   <ext_freq_khz> - MUST be used if clock is from external source
-#                    CAN be used if main oscillator frequency is known
-# Examples:
-#  flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 25000                   ==== RECOMENDED ============
-#  flash bank at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 25000    (auto-detection, except for clock)      ==== RECOMENDED ============
-#  flash bank at91sam7 0x00100000 0 0 4 0 0 AT91SAM7XC256 1 16 64 256 3 0                       ==== NOT RECOMENDED !!! ====
-#  flash bank at91sam7 0 0 0 0 0                        (old style, full auto-detection)        ==== NOT RECOMENDED !!! ====
-****************************************************************************************************************************************************************************************/
 static int at91sam7_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
 {
 	flash_bank_t *t_bank = bank;

Modified: trunk/src/flash/orion_nand.c
===================================================================
--- trunk/src/flash/orion_nand.c	2009-08-30 17:27:50 UTC (rev 2649)
+++ trunk/src/flash/orion_nand.c	2009-08-30 17:30:14 UTC (rev 2650)
@@ -198,7 +198,7 @@
 	uint8_t ale, cle;
 
 	if (argc != 3) {
-		LOG_ERROR("arguments must be: <target_number> <NAND_address>\n");
+		LOG_ERROR("arguments must be: <target_id> <NAND_address>\n");
 		return ERROR_NAND_DEVICE_INVALID;
 	}
 

Modified: trunk/src/helper/startup.tcl
===================================================================
--- trunk/src/helper/startup.tcl	2009-08-30 17:27:50 UTC (rev 2649)
+++ trunk/src/helper/startup.tcl	2009-08-30 17:30:14 UTC (rev 2650)
@@ -128,7 +128,7 @@
 # Handle GDB 'R' packet. Can be overriden by configuration script,
 # but it's not something one would expect target scripts to do
 # normally
-proc ocd_gdb_restart {target_num} {
+proc ocd_gdb_restart {target_id} {
 	# Fix!!! we're resetting all targets here! Really we should reset only
 	# one target
 	reset halt

Modified: trunk/src/server/gdb_server.c
===================================================================
--- trunk/src/server/gdb_server.c	2009-08-30 17:27:50 UTC (rev 2649)
+++ trunk/src/server/gdb_server.c	2009-08-30 17:30:14 UTC (rev 2650)
@@ -2156,7 +2156,9 @@
 					/* handle extended restart packet */
 					breakpoint_clear_target(gdb_service->target);
 					watchpoint_clear_target(gdb_service->target);
-					command_run_linef(connection->cmd_ctx, "ocd_gdb_restart %d", get_num_by_target(target));
+					command_run_linef(connection->cmd_ctx,
+							"ocd_gdb_restart %s",
+							target->cmd_name);
 					break;
 				default:
 					/* ignore unkown packets */
@@ -2230,17 +2232,23 @@
 	}
 	else
 	{
+		unsigned short port = gdb_port;
+
 		while (target)
 		{
 			gdb_service = malloc(sizeof(gdb_service_t));
 			gdb_service->target = target;
 
-			add_service("gdb", CONNECTION_TCP, gdb_port + target->target_number, 1, gdb_new_connection, gdb_input, gdb_connection_closed, gdb_service);
+			add_service("gdb", CONNECTION_TCP,
+					port, 1,
+					gdb_new_connection, gdb_input,
+					gdb_connection_closed, gdb_service);
 
-			LOG_DEBUG("gdb service for target %s at port %i",
+			LOG_DEBUG("gdb service for target %s at TCP port %i",
 					target_get_name(target),
-					gdb_port + target->target_number);
+					port);
 			target = target->next;
+			port++;
 		}
 	}
 

Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c	2009-08-30 17:27:50 UTC (rev 2649)
+++ trunk/src/target/target.c	2009-08-30 17:30:14 UTC (rev 2650)
@@ -249,22 +249,6 @@
 	return cp;
 }
 
-static int max_target_number(void)
-{
-	target_t *t;
-	int x;
-
-	x = -1;
-	t = all_targets;
-	while (t) {
-		if (x < t->target_number) {
-			x = (t->target_number) + 1;
-		}
-		t = t->next;
-	}
-	return x;
-}
-
 /* determine the number of the new target */
 static int new_target_number(void)
 {
@@ -346,14 +330,19 @@
 			return target;
 	}
 
+	/* It's OK to remove this fallback sometime after August 2010 or so */
+
 	/* no match, try as number */
 	unsigned num;
 	if (parse_uint(id, &num) != ERROR_OK)
 		return NULL;
 
 	for (target = all_targets; target; target = target->next) {
-		if (target->target_number == (int)num)
+		if (target->target_number == (int)num) {
+			LOG_WARNING("use '%s' as target identifier, not '%u'",
+					target->cmd_name, num);
 			return target;
+		}
 	}
 
 	return NULL;
@@ -374,11 +363,6 @@
 	return NULL;
 }
 
-int get_num_by_target(target_t *query_target)
-{
-	return query_target->target_number;
-}
-
 target_t* get_current_target(command_context_t *cmd_ctx)
 {
 	target_t *target = get_target_by_num(cmd_ctx->current_target);
@@ -4387,6 +4371,8 @@
 		return target_create(&goi);
 		break;
 	case TG_CMD_NUMBER:
+		/* It's OK to remove this mechanism sometime after August 2010 or so */
+		LOG_WARNING("don't use numbers as target identifiers; use names");
 		if (goi.argc != 1) {
 			Jim_SetResult_sprintf(goi.interp, "expected: target number ?NUMBER?");
 			return JIM_ERR;
@@ -4395,23 +4381,25 @@
 		if (e != JIM_OK) {
 			return JIM_ERR;
 		}
-		{
-			target_t *t;
-			t = get_target_by_num(w);
-			if (t == NULL) {
-				Jim_SetResult_sprintf(goi.interp,"Target: number %d does not exist", (int)(w));
-				return JIM_ERR;
-			}
-			Jim_SetResultString(goi.interp, t->cmd_name, -1);
-			return JIM_OK;
+		for (x = 0, target = all_targets; target; target = target->next, x++) {
+			if (target->target_number == w)
+				break;
 		}
+		if (target == NULL) {
+			Jim_SetResult_sprintf(goi.interp,
+					"Target: number %d does not exist", (int)(w));
+			return JIM_ERR;
+		}
+		Jim_SetResultString(goi.interp, target->cmd_name, -1);
+		return JIM_OK;
 	case TG_CMD_COUNT:
 		if (goi.argc != 0) {
 			Jim_WrongNumArgs(goi.interp, 0, goi.argv, "<no parameters>");
 			return JIM_ERR;
 		}
-		Jim_SetResult(goi.interp,
-					   Jim_NewIntObj(goi.interp, max_target_number()));
+		for (x = 0, target = all_targets; target; target = target->next, x++)
+			continue;
+		Jim_SetResult(goi.interp, Jim_NewIntObj(goi.interp, x));
 		return JIM_OK;
 	}
 

Modified: trunk/src/target/target.h
===================================================================
--- trunk/src/target/target.h	2009-08-30 17:27:50 UTC (rev 2649)
+++ trunk/src/target/target.h	2009-08-30 17:30:14 UTC (rev 2650)
@@ -120,7 +120,7 @@
 {
 	target_type_t *type;				/* target type definition (name, access functions) */
 	const char *cmd_name;				/* tcl Name of target */
-	int target_number;					/* generaly, target index but may not be in order */
+	int target_number;					/* DO NOT USE!  field to be removed in 2010 */
 	jtag_tap_t *tap;					/* where on the jtag chain is this */
 	const char *variant;				/* what varient of this chip is it? */
 	target_event_action_t *event_action;
@@ -250,7 +250,6 @@
 extern int target_call_timer_callbacks_now(void);
 
 extern target_t* get_current_target(struct command_context_s *cmd_ctx);
-extern int get_num_by_target(target_t *query_target);
 extern target_t *get_target(const char *id);
 
 /**

[Openocd-svn] r2649 - in trunk/src: . helper

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-30 19:27:50 +0200 (Sun, 30 Aug 2009)
New Revision: 2649

Modified:
   trunk/src/ecosboard.c
   trunk/src/helper/command.c
   trunk/src/helper/configuration.h
   trunk/src/helper/options.c
Log:
David Brownell <da...@pa...> Be sure the built-in search paths always go *after* ones provided
on the command line ... matching comment in add_default_dirs().

Without this it's impossible to use a private config file which
happens to have the same name as an installed one.  Say, because
you're bugfixing a private copy...

Modified: trunk/src/ecosboard.c
===================================================================
--- trunk/src/ecosboard.c	2009-08-28 17:18:36 UTC (rev 2648)
+++ trunk/src/ecosboard.c	2009-08-30 17:27:50 UTC (rev 2649)
@@ -918,7 +918,7 @@
 
 static const char *zylin_config_dir="/config/settings";
 
-int add_default_dirs(void)
+static int add_default_dirs(void)
 {
 	add_script_search_dir(zylin_config_dir);
 	add_script_search_dir("/rom/lib/openocd");

Modified: trunk/src/helper/command.c
===================================================================
--- trunk/src/helper/command.c	2009-08-28 17:18:36 UTC (rev 2648)
+++ trunk/src/helper/command.c	2009-08-30 17:27:50 UTC (rev 2649)
@@ -744,8 +744,6 @@
 	interp->cb_fflush = openocd_jim_fflush;
 	interp->cb_fgets = openocd_jim_fgets;
 
-	add_default_dirs();
-
 #if !BUILD_ECOSBOARD
 	Jim_EventLoopOnLoad(interp);
 #endif

Modified: trunk/src/helper/configuration.h
===================================================================
--- trunk/src/helper/configuration.h	2009-08-28 17:18:36 UTC (rev 2648)
+++ trunk/src/helper/configuration.h	2009-08-30 17:27:50 UTC (rev 2649)
@@ -32,6 +32,5 @@
 extern int configuration_output_handler(struct command_context_s *context, const char* line);
 extern FILE *open_file_from_path (char *file, char *mode);
 extern char *find_file(const char *name);
-int add_default_dirs(void);
 
 #endif /* CONFIGURATION_H */

Modified: trunk/src/helper/options.c
===================================================================
--- trunk/src/helper/options.c	2009-08-28 17:18:36 UTC (rev 2648)
+++ trunk/src/helper/options.c	2009-08-30 17:27:50 UTC (rev 2649)
@@ -38,7 +38,7 @@
 	{"help",	no_argument,		&help_flag,	1},
 	{"version",	no_argument,		&version_flag,	1},
 	{"debug",	optional_argument,	0,		'd'},
-	{"file", 	required_argument,	0,		'f'},
+	{"file",	required_argument,	0,		'f'},
 	{"search",	required_argument,	0,		's'},
 	{"log_output",	required_argument,	0,	'l'},
 	{"command",	required_argument,	0,		'c'},
@@ -53,7 +53,7 @@
 	return ERROR_OK;
 }
 
-int add_default_dirs(void)
+static void add_default_dirs(void)
 {
 #ifdef _WIN32
 	/* Add the parent of the directory where openocd.exe resides to the
@@ -106,7 +106,6 @@
 	add_script_search_dir(PKGDATADIR "/site");
 	add_script_search_dir(PKGDATADIR "/scripts");
 #endif
-	return ERROR_OK;
 }
 
 int parse_cmdline_args(struct command_context_s *cmd_ctx, int argc, char *argv[])
@@ -196,5 +195,10 @@
 		exit(0);
 	}
 
+	/* paths specified on the command line take precedence over these
+	 * built-in paths
+	 */
+	add_default_dirs();
+
 	return ERROR_OK;
 }

[Openocd-svn] r2648 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-28 19:18:36 +0200 (Fri, 28 Aug 2009)
New Revision: 2648

Modified:
   trunk/src/target/arm11_dbgtap.c
Log:
David Brownell <da...@pa...> fix warnings

Modified: trunk/src/target/arm11_dbgtap.c
===================================================================
--- trunk/src/target/arm11_dbgtap.c	2009-08-28 13:43:26 UTC (rev 2647)
+++ trunk/src/target/arm11_dbgtap.c	2009-08-28 17:18:36 UTC (rev 2648)
@@ -386,7 +386,8 @@
 			if (flag)
 				break;
 
-			long long then;
+			long long then = 0;
+
 			if (i == 1000)
 			{
 				then = timeval_ms();
@@ -465,7 +466,8 @@
 
 			JTAG_DEBUG("DTR  Ready %d  nRetry %d", Ready, nRetry);
 
-			long long then;
+			long long then = 0;
+
 			if (i == 1000)
 			{
 				then = timeval_ms();
@@ -499,7 +501,8 @@
 
 		JTAG_DEBUG("DTR  Data %08x  Ready %d  nRetry %d", Data, Ready, nRetry);
 
-		long long then;
+		long long then = 0;
+
 		if (i == 1000)
 		{
 			then = timeval_ms();
@@ -678,7 +681,8 @@
 
 			JTAG_DEBUG("DTR  Data %08x  Ready %d  nRetry %d", Data, Ready, nRetry);
 
-			long long then;
+			long long then = 0;
+
 			if (i == 1000)
 			{
 				then = timeval_ms();

[Openocd-svn] r2647 - in trunk: . src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-28 15:43:26 +0200 (Fri, 28 Aug 2009)
New Revision: 2647

Modified:
   trunk/TODO
   trunk/src/target/arm11.c
   trunk/src/target/arm11.h
   trunk/src/target/arm11_dbgtap.c
Log:
added arm11 timeout error messages

Modified: trunk/TODO
===================================================================
--- trunk/TODO	2009-08-28 09:47:19 UTC (rev 2646)
+++ trunk/TODO	2009-08-28 13:43:26 UTC (rev 2647)
@@ -117,10 +117,16 @@
 - ARM923EJS:
   - reset run/halt/step is not robust; needs testing to map out problems.
 - ARM11 improvements (MB?)
-  - fix single stepping  (reported by ØH). Michael Bruck explained
-  that what's required is to emulate the current instruction(just like the
-  arm7 code) to know what address to set the breakpoint at for single
-  stepping an instruction.
+  - fix single stepping  (reported by ØH). Need to automatically
+  use hardware stepping if available.
+  - hunt down and add timeouts to all infinite loops, e.g. arm11_run_instr_no_data would
+    lock up in infinite loop if e.g. an "mdh" command tries to read memory from invalid memory location.
+    Try mdh 0x40000000 on i.MX31 PDK
+  - mdb can return garbage data if read byte operation fails for
+  a memory region(16 & 32 byte access modes may be supported). Is this
+  a bug in the .MX31 PDK init script? Try on i.MX31 PDK: 
+  mdw 0xb80005f0 0x8, mdh 0xb80005f0 0x10, mdb 0xb80005f0 0x20. mdb returns
+  garabage.
   - implement missing functionality (grep FNC_INFO_NOTIMPLEMENTED ...)
   - thumb support is missing: ISTR ARMv6 requires Thumb.
   ARM1156 has Thumb2; ARM1136 doesn't.

Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c	2009-08-28 09:47:19 UTC (rev 2646)
+++ trunk/src/target/arm11.c	2009-08-28 13:43:26 UTC (rev 2647)
@@ -2,7 +2,7 @@
  *   Copyright (C) 2008 digenius technology GmbH.                          *
  *   Michael Bruck                                                         *
  *                                                                         *
- *   Copyright (C) 2008 Oyvind Harboe oyv...@zy...              *
+ *   Copyright (C) 2008,2009 Oyvind Harboe oyv...@zy...         *
  *                                                                         *
  *   Copyright (C) 2008 Georg Acher <ac...@in...>                      *
  *                                                                         *
@@ -374,6 +374,7 @@
   */
 static int arm11_on_enter_debug_state(arm11_common_t * arm11)
 {
+	int retval;
 	FNC_INFO;
 
 	for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
@@ -459,7 +460,9 @@
 	for (size_t i = 0; i < 15; i++)
 	{
 		/* MCR p14,0,R?,c0,c5,0 */
-		arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
+		retval = arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
+		if (retval != ERROR_OK)
+			return retval;
 	}
 
 	/* save rDTR */
@@ -484,7 +487,9 @@
 	/* save PC */
 
 	/* MOV R0,PC (move PC -> r0 (-> wDTR -> local var)) */
-	arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
+	retval = arm11_run_instr_data_from_core_via_r0(arm11, 0xE1A0000F, &R(PC));
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* adjust PC depending on ARM state */
 
@@ -665,6 +670,7 @@
 int arm11_poll(struct target_s *target)
 {
 	FNC_INFO;
+	int retval;
 
 	arm11_common_t * arm11 = target->arch_info;
 
@@ -688,7 +694,9 @@
 			LOG_DEBUG("enter TARGET_HALTED");
 			target->state			= TARGET_HALTED;
 			target->debug_reason	= arm11_get_DSCR_debug_reason(dscr);
-			arm11_on_enter_debug_state(arm11);
+			retval = arm11_on_enter_debug_state(arm11);
+			if (retval != ERROR_OK)
+				return retval;
 
 			target_call_event_callbacks(target,
 				old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED);

Modified: trunk/src/target/arm11.h
===================================================================
--- trunk/src/target/arm11.h	2009-08-28 09:47:19 UTC (rev 2646)
+++ trunk/src/target/arm11.h	2009-08-28 13:43:26 UTC (rev 2647)
@@ -257,12 +257,12 @@
 void arm11_run_instr_data_prepare			(arm11_common_t * arm11);
 void arm11_run_instr_data_finish			(arm11_common_t * arm11);
 int arm11_run_instr_no_data					(arm11_common_t * arm11, uint32_t * opcode, size_t count);
-void arm11_run_instr_no_data1				(arm11_common_t * arm11, uint32_t opcode);
+int arm11_run_instr_no_data1				(arm11_common_t * arm11, uint32_t opcode);
 int arm11_run_instr_data_to_core			(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
 int arm11_run_instr_data_to_core_noack		(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
 int arm11_run_instr_data_to_core1			(arm11_common_t * arm11, uint32_t opcode, uint32_t data);
 int arm11_run_instr_data_from_core			(arm11_common_t * arm11, uint32_t opcode, uint32_t * data, size_t count);
-void arm11_run_instr_data_from_core_via_r0	(arm11_common_t * arm11, uint32_t opcode, uint32_t * data);
+int arm11_run_instr_data_from_core_via_r0	(arm11_common_t * arm11, uint32_t opcode, uint32_t * data);
 void arm11_run_instr_data_to_core_via_r0	(arm11_common_t * arm11, uint32_t opcode, uint32_t data);
 
 int arm11_add_dr_scan_vc(int num_fields, scan_field_t *fields, tap_state_t state);

Modified: trunk/src/target/arm11_dbgtap.c
===================================================================
--- trunk/src/target/arm11_dbgtap.c	2009-08-28 09:47:19 UTC (rev 2646)
+++ trunk/src/target/arm11_dbgtap.c	2009-08-28 13:43:26 UTC (rev 2647)
@@ -2,7 +2,7 @@
  *   Copyright (C) 2008 digenius technology GmbH.                          *
  *   Michael Bruck                                                         *
  *                                                                         *
- *   Copyright (C) 2008 Oyvind Harboe oyv...@zy...              *
+ *   Copyright (C) 2008,2009 Oyvind Harboe oyv...@zy...         *
  *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
@@ -26,6 +26,7 @@
 
 #include "arm11.h"
 
+#include "time_support.h"
 
 #if 0
 #define JTAG_DEBUG(expr ...)	DEBUG(expr)
@@ -355,6 +356,7 @@
 }
 
 
+
 /** Execute one or multiple instructions via ITR
  *
  * \pre arm11_run_instr_data_prepare() /  arm11_run_instr_data_finish() block
@@ -372,6 +374,7 @@
 	{
 		arm11_add_debug_INST(arm11, *opcode++, NULL, TAP_IDLE);
 
+		int i = 0;
 		while (1)
 		{
 			uint8_t flag;
@@ -382,6 +385,22 @@
 
 			if (flag)
 				break;
+
+			long long then;
+			if (i == 1000)
+			{
+				then = timeval_ms();
+			}
+			if (i >= 1000)
+			{
+				if ((timeval_ms()-then) > 1000)
+				{
+					LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+					return ERROR_FAIL;
+				}
+			}
+
+			i++;
 		}
 	}
 
@@ -396,9 +415,9 @@
  * \param opcode	ARM opcode
  *
  */
-void arm11_run_instr_no_data1(arm11_common_t * arm11, uint32_t opcode)
+int arm11_run_instr_no_data1(arm11_common_t * arm11, uint32_t opcode)
 {
-	arm11_run_instr_no_data(arm11, &opcode, 1);
+	return arm11_run_instr_no_data(arm11, &opcode, 1);
 }
 
 
@@ -435,6 +454,7 @@
 
 	while (count--)
 	{
+		int i = 0;
 		do
 		{
 			Data	    = *data;
@@ -444,6 +464,22 @@
 			CHECK_RETVAL(jtag_execute_queue());
 
 			JTAG_DEBUG("DTR  Ready %d  nRetry %d", Ready, nRetry);
+
+			long long then;
+			if (i == 1000)
+			{
+				then = timeval_ms();
+			}
+			if (i >= 1000)
+			{
+				if ((timeval_ms()-then) > 1000)
+				{
+					LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+					return ERROR_FAIL;
+				}
+			}
+
+			i++;
 		}
 		while (!Ready);
 
@@ -452,6 +488,7 @@
 
 	arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
 
+	int i = 0;
 	do
 	{
 		Data	    = 0;
@@ -461,6 +498,22 @@
 		CHECK_RETVAL(jtag_execute_queue());
 
 		JTAG_DEBUG("DTR  Data %08x  Ready %d  nRetry %d", Data, Ready, nRetry);
+
+		long long then;
+		if (i == 1000)
+		{
+			then = timeval_ms();
+		}
+		if (i >= 1000)
+		{
+			if ((timeval_ms()-then) > 1000)
+			{
+				LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+				return ERROR_FAIL;
+			}
+		}
+
+		i++;
 	}
 	while (!Ready);
 
@@ -616,6 +669,7 @@
 
 	while (count--)
 	{
+		int i = 0;
 		do
 		{
 			arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
@@ -623,6 +677,22 @@
 			CHECK_RETVAL(jtag_execute_queue());
 
 			JTAG_DEBUG("DTR  Data %08x  Ready %d  nRetry %d", Data, Ready, nRetry);
+
+			long long then;
+			if (i == 1000)
+			{
+				then = timeval_ms();
+			}
+			if (i >= 1000)
+			{
+				if ((timeval_ms()-then) > 1000)
+				{
+					LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+					return ERROR_FAIL;
+				}
+			}
+
+			i++;
 		}
 		while (!Ready);
 
@@ -644,12 +714,17 @@
  * \param data		Pointer to a data word that receives the value from r0 after \p opcode was executed.
  *
  */
-void arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t * data)
+int arm11_run_instr_data_from_core_via_r0(arm11_common_t * arm11, uint32_t opcode, uint32_t * data)
 {
-	arm11_run_instr_no_data1(arm11, opcode);
+	int retval;
+	retval = arm11_run_instr_no_data1(arm11, opcode);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* MCR p14,0,R0,c0,c5,0 (move r0 -> wDTR -> local var) */
 	arm11_run_instr_data_from_core(arm11, 0xEE000E15, data, 1);
+
+	return ERROR_OK;
 }
 
 /** Load data into core via DTR then move it to r0 then

[Openocd-svn] r2646 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-28 11:47:19 +0200 (Fri, 28 Aug 2009)
New Revision: 2646

Modified:
   trunk/src/target/arm7_9_common.c
   trunk/src/target/arm7_9_common.h
Log:
restore ICE watchpoint registers when the *last* software breakpoint is removed

Modified: trunk/src/target/arm7_9_common.c
===================================================================
--- trunk/src/target/arm7_9_common.c	2009-08-28 06:53:35 UTC (rev 2645)
+++ trunk/src/target/arm7_9_common.c	2009-08-28 09:47:19 UTC (rev 2646)
@@ -61,6 +61,7 @@
 	LOG_DEBUG("-");
 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
 	embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
+	arm7_9->sw_breakpoint_count = 0;
 	arm7_9->sw_breakpoints_added = 0;
 	arm7_9->wp0_used = 0;
 	arm7_9->wp1_used = arm7_9->wp1_used_default;
@@ -274,9 +275,6 @@
 	}
 	else if (breakpoint->type == BKPT_SOFT)
 	{
-		if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
-			return retval;
-
 		/* did we already set this breakpoint? */
 		if (breakpoint->set)
 			return ERROR_OK;
@@ -329,6 +327,12 @@
 				return ERROR_OK;
 			}
 		}
+
+		if ((retval = arm7_9_set_software_breakpoints(arm7_9)) != ERROR_OK)
+			return retval;
+
+		arm7_9->sw_breakpoint_count++;
+
 		breakpoint->set = 1;
 	}
 
@@ -415,6 +419,20 @@
 					return retval;
 				}
 		}
+
+		if (--arm7_9->sw_breakpoint_count==0)
+		{
+			/* We have removed the last sw breakpoint, clear the hw breakpoint we used to implement it */
+			if (arm7_9->sw_breakpoints_added == 1)
+			{
+				embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0);
+			}
+			else if (arm7_9->sw_breakpoints_added == 2)
+			{
+				embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0);
+			}
+		}
+
 		breakpoint->set = 0;
 	}
 
@@ -3109,6 +3127,7 @@
 	arm7_9->wp_available = 0; /* this is set up in arm7_9_clear_watchpoints() */
 	arm7_9->wp_available_max = 2;
 	arm7_9->sw_breakpoints_added = 0;
+	arm7_9->sw_breakpoint_count = 0;
 	arm7_9->breakpoint_count = 0;
 	arm7_9->wp0_used = 0;
 	arm7_9->wp1_used = 0;

Modified: trunk/src/target/arm7_9_common.h
===================================================================
--- trunk/src/target/arm7_9_common.h	2009-08-28 06:53:35 UTC (rev 2645)
+++ trunk/src/target/arm7_9_common.h	2009-08-28 09:47:19 UTC (rev 2646)
@@ -47,6 +47,7 @@
 	uint32_t arm_bkpt; /**< ARM breakpoint instruction */
 	uint16_t thumb_bkpt; /**< Thumb breakpoint instruction */
 	int sw_breakpoints_added; /**< Specifies which watchpoint software breakpoints are setup on */
+	int sw_breakpoint_count; /**< keep track of number of software breakpoints we have set */
 	int breakpoint_count; /**< Current number of set breakpoints */
 	int wp_available; /**< Current number of available watchpoint units */
 	int wp_available_max; /**< Maximum number of available watchpoint units */

[Openocd-svn] r2645 - trunk/tcl/board

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-28 08:53:35 +0200 (Fri, 28 Aug 2009)
New Revision: 2645

Modified:
   trunk/tcl/board/ek-lm3s1968.cfg
   trunk/tcl/board/ek-lm3s3748.cfg
   trunk/tcl/board/ek-lm3s811.cfg
   trunk/tcl/board/ek-lm3s9b9x.cfg
Log:
David Brownell <da...@pa...> The Stellaris eval boards don't have TRST signals, so
defining ntrst_delay is pointless; don't.

At least the LM3S3748 eval board doesn't need nsrst_delay
either; remove that too.

Modified: trunk/tcl/board/ek-lm3s1968.cfg
===================================================================
--- trunk/tcl/board/ek-lm3s1968.cfg	2009-08-28 06:52:08 UTC (rev 2644)
+++ trunk/tcl/board/ek-lm3s1968.cfg	2009-08-28 06:53:35 UTC (rev 2645)
@@ -17,7 +17,6 @@
 jtag_khz 3000
 
 jtag_nsrst_delay 100
-jtag_ntrst_delay 100
 
 #LM3S1968 Evaluation Board has only srst
 reset_config srst_only

Modified: trunk/tcl/board/ek-lm3s3748.cfg
===================================================================
--- trunk/tcl/board/ek-lm3s3748.cfg	2009-08-28 06:52:08 UTC (rev 2644)
+++ trunk/tcl/board/ek-lm3s3748.cfg	2009-08-28 06:53:35 UTC (rev 2645)
@@ -9,9 +9,6 @@
 # LM3S parts don't support RTCK
 jtag_khz 500
 
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
 # Board has only srst
 reset_config srst_only
 

Modified: trunk/tcl/board/ek-lm3s811.cfg
===================================================================
--- trunk/tcl/board/ek-lm3s811.cfg	2009-08-28 06:52:08 UTC (rev 2644)
+++ trunk/tcl/board/ek-lm3s811.cfg	2009-08-28 06:53:35 UTC (rev 2645)
@@ -13,7 +13,6 @@
 jtag_khz 500
 
 jtag_nsrst_delay 100
-jtag_ntrst_delay 100
 
 #LM3S811 Evaluation Board has only srst
 reset_config srst_only

Modified: trunk/tcl/board/ek-lm3s9b9x.cfg
===================================================================
--- trunk/tcl/board/ek-lm3s9b9x.cfg	2009-08-28 06:52:08 UTC (rev 2644)
+++ trunk/tcl/board/ek-lm3s9b9x.cfg	2009-08-28 06:53:35 UTC (rev 2645)
@@ -12,7 +12,6 @@
 jtag_khz 500
 
 jtag_nsrst_delay 100
-jtag_ntrst_delay 100
 
 #LM3S9B9x Evaluation Board has only srst
 reset_config srst_only

[Openocd-svn] r2644 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-28 08:52:08 +0200 (Fri, 28 Aug 2009)
New Revision: 2644

Modified:
   trunk/src/target/arm_disassembler.c
Log:
David Brownell <da...@pa...> ARM disassembly support for about five dozen non-Thumb instructions
that were added after ARMv5TE was defined:

 - ARMv5J "BXJ" (for Java/Jazelle)
 - ARMv6 "media" instructions (for OMAP2420, i.MX31, etc)

Compile-tested.  This might not set up the simulator right for the
ARMv6 single step support; only BXJ branches though, and docs to
support Jazelle branching are non-public (still, sigh).

ARMv6 instructions known to be mis-handled by this disassembler
include:  UMAAL, LDREX, STREX, CPS, SETEND, RFE, SRS, MCRR2, MRRC2

Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c	2009-08-27 10:37:01 UTC (rev 2643)
+++ trunk/src/target/arm_disassembler.c	2009-08-28 06:52:08 UTC (rev 2644)
@@ -438,6 +438,323 @@
 	return ERROR_OK;
 }
 
+static int evaluate_extend(uint32_t opcode, uint32_t address, char *cp)
+{
+	unsigned rm = (opcode >> 0) & 0xf;
+	unsigned rd = (opcode >> 12) & 0xf;
+	unsigned rn = (opcode >> 16) & 0xf;
+	char *type, *rot;
+
+	switch ((opcode >> 24) & 0x3) {
+	case 0:
+		type = "B16";
+		break;
+	case 1:
+		sprintf(cp, "UNDEFINED");
+		return ARM_UNDEFINED_INSTRUCTION;
+	case 2:
+		type = "B";
+		break;
+	case 3:
+		type = "H";
+		break;
+	}
+
+	switch ((opcode >> 10) & 0x3) {
+	case 0:
+		rot = "";
+		break;
+	case 1:
+		rot = ", ROR #8";
+		break;
+	case 2:
+		rot = ", ROR #16";
+		break;
+	case 3:
+		rot = ", ROR #24";
+		break;
+	}
+
+	if (rn == 0xf) {
+		sprintf(cp, "%cXT%s%s\tr%d, r%d%s",
+				(opcode & (1 << 22)) ? 'U' : 'S',
+				type, COND(opcode),
+				rd, rm, rot);
+		return ARM_MOV;
+	} else {
+		sprintf(cp, "%cXTA%s%s\tr%d, r%d, r%d%s",
+				(opcode & (1 << 22)) ? 'U' : 'S',
+				type, COND(opcode),
+				rd, rn, rm, rot);
+		return ARM_ADD;
+	}
+}
+
+static int evaluate_p_add_sub(uint32_t opcode, uint32_t address, char *cp)
+{
+	char *prefix;
+	char *op;
+	int type;
+
+	switch ((opcode >> 20) & 0x7) {
+	case 1:
+		prefix = "S";
+		break;
+	case 2:
+		prefix = "Q";
+		break;
+	case 3:
+		prefix = "SH";
+		break;
+	case 5:
+		prefix = "U";
+		break;
+	case 6:
+		prefix = "UQ";
+		break;
+	case 7:
+		prefix = "UH";
+		break;
+	default:
+		goto undef;
+	}
+
+	switch ((opcode >> 5) & 0x7) {
+	case 0:
+		op = "ADD16";
+		type = ARM_ADD;
+		break;
+	case 1:
+		op = "ADDSUBX";
+		type = ARM_ADD;
+		break;
+	case 2:
+		op = "SUBADDX";
+		type = ARM_SUB;
+		break;
+	case 3:
+		op = "SUB16";
+		type = ARM_SUB;
+		break;
+	case 4:
+		op = "ADD8";
+		type = ARM_ADD;
+		break;
+	case 7:
+		op = "SUB8";
+		type = ARM_SUB;
+		break;
+	default:
+		goto undef;
+	}
+
+	sprintf(cp, "%s%s%s\tr%d, r%d, r%d", prefix, op, COND(opcode),
+			(int) (opcode >> 12) & 0xf,
+			(int) (opcode >> 16) & 0xf,
+			(int) (opcode >> 0) & 0xf);
+	return type;
+
+undef:
+	/* these opcodes might be used someday */
+	sprintf(cp, "UNDEFINED");
+	return ARM_UNDEFINED_INSTRUCTION;
+}
+
+/* ARMv6 and later support "media" instructions (includes SIMD) */
+static int evaluate_media(uint32_t opcode, uint32_t address,
+		arm_instruction_t *instruction)
+{
+	char *cp = instruction->text;
+	char *mnemonic = NULL;
+
+	sprintf(cp,
+		"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t",
+		address, opcode);
+	cp = strchr(cp, 0);
+
+	/* parallel add/subtract */
+	if ((opcode & 0x01800000) == 0x00000000) {
+		instruction->type = evaluate_p_add_sub(opcode, address, cp);
+		return ERROR_OK;
+	}
+
+	/* halfword pack */
+	if ((opcode & 0x01f00020) == 0x00800000) {
+		char *type, *shift;
+		unsigned imm = (unsigned) (opcode >> 7) & 0x1f;
+
+		if (opcode & (1 << 6)) {
+			type = "TB";
+			shift = "ASR";
+			if (imm == 0)
+				imm = 32;
+		} else {
+			type = "BT";
+			shift = "LSL";
+		}
+		sprintf(cp, "PKH%s%s\tr%d, r%d, r%d, %s #%d",
+			type, COND(opcode),
+			(int) (opcode >> 12) & 0xf,
+			(int) (opcode >> 16) & 0xf,
+			(int) (opcode >> 0) & 0xf,
+			shift, imm);
+		return ERROR_OK;
+	}
+
+	/* word saturate */
+	if ((opcode & 0x01a00020) == 0x00a00000) {
+		char *shift;
+		unsigned imm = (unsigned) (opcode >> 7) & 0x1f;
+
+		if (opcode & (1 << 6)) {
+			shift = "ASR";
+			if (imm == 0)
+				imm = 32;
+		} else {
+			shift = "LSL";
+		}
+
+		sprintf(cp, "%cSAT%s\tr%d, #%d, r%d, %s #%d",
+			(opcode & (1 << 22)) ? 'U' : 'S',
+			COND(opcode),
+			(int) (opcode >> 12) & 0xf,
+			(int) (opcode >> 16) & 0x1f,
+			(int) (opcode >> 0) & 0xf,
+			shift, imm);
+		return ERROR_OK;
+	}
+
+	/* sign extension */
+	if ((opcode & 0x018000f0) == 0x00800070) {
+		instruction->type = evaluate_extend(opcode, address, cp);
+		return ERROR_OK;
+	}
+
+	/* multiplies */
+	if ((opcode & 0x01f00080) == 0x01000000) {
+		unsigned rn = (opcode >> 12) & 0xf;
+
+		if (rn != 0xf)
+			sprintf(cp, "SML%cD%s%s\tr%d, r%d, r%d, r%d",
+				(opcode & (1 << 6)) ? 'S' : 'A',
+				(opcode & (1 << 5)) ? "X" : "",
+				COND(opcode),
+				(int) (opcode >> 16) & 0xf,
+				(int) (opcode >> 0) & 0xf,
+				(int) (opcode >> 8) & 0xf,
+				rn);
+		else
+			sprintf(cp, "SMU%cD%s%s\tr%d, r%d, r%d",
+				(opcode & (1 << 6)) ? 'S' : 'A',
+				(opcode & (1 << 5)) ? "X" : "",
+				COND(opcode),
+				(int) (opcode >> 16) & 0xf,
+				(int) (opcode >> 0) & 0xf,
+				(int) (opcode >> 8) & 0xf);
+		return ERROR_OK;
+	}
+	if ((opcode & 0x01f00000) == 0x01400000) {
+		sprintf(cp, "SML%cLD%s%s\tr%d, r%d, r%d, r%d",
+			(opcode & (1 << 6)) ? 'S' : 'A',
+			(opcode & (1 << 5)) ? "X" : "",
+			COND(opcode),
+			(int) (opcode >> 12) & 0xf,
+			(int) (opcode >> 16) & 0xf,
+			(int) (opcode >> 0) & 0xf,
+			(int) (opcode >> 8) & 0xf);
+		return ERROR_OK;
+	}
+	if ((opcode & 0x01f00000) == 0x01500000) {
+		unsigned rn = (opcode >> 12) & 0xf;
+
+		switch (opcode & 0xc0) {
+		case 3:
+			if (rn == 0xf)
+				goto undef;
+			/* FALL THROUGH */
+		case 0:
+			break;
+		default:
+			goto undef;
+		}
+
+		if (rn != 0xf)
+			sprintf(cp, "SMML%c%s%s\tr%d, r%d, r%d, r%d",
+				(opcode & (1 << 6)) ? 'S' : 'A',
+				(opcode & (1 << 5)) ? "R" : "",
+				COND(opcode),
+				(int) (opcode >> 16) & 0xf,
+				(int) (opcode >> 0) & 0xf,
+				(int) (opcode >> 8) & 0xf,
+				rn);
+		else
+			sprintf(cp, "SMMUL%s%s\tr%d, r%d, r%d",
+				(opcode & (1 << 5)) ? "R" : "",
+				COND(opcode),
+				(int) (opcode >> 16) & 0xf,
+				(int) (opcode >> 0) & 0xf,
+				(int) (opcode >> 8) & 0xf);
+		return ERROR_OK;
+	}
+
+
+	/* simple matches against the remaining decode bits */
+	switch (opcode & 0x01f000f0) {
+	case 0x00a00030:
+	case 0x00e00030:
+		/* parallel halfword saturate */
+		sprintf(cp, "%cSAT16%s\tr%d, #%d, r%d",
+			(opcode & (1 << 22)) ? 'U' : 'S',
+			COND(opcode),
+			(int) (opcode >> 12) & 0xf,
+			(int) (opcode >> 16) & 0xf,
+			(int) (opcode >> 0) & 0xf);
+		return ERROR_OK;
+	case 0x00b00030:
+		mnemonic = "REV";
+		break;
+	case 0x00b000b0:
+		mnemonic = "REV16";
+		break;
+	case 0x00f000b0:
+		mnemonic = "REVSH";
+		break;
+	case 0x008000b0:
+		/* select bytes */
+		sprintf(cp, "SEL%s\tr%d, r%d, r%d", COND(opcode),
+			(int) (opcode >> 12) & 0xf,
+			(int) (opcode >> 16) & 0xf,
+			(int) (opcode >> 0) & 0xf);
+		return ERROR_OK;
+	case 0x01800010:
+		/* unsigned sum of absolute differences */
+		if (((opcode >> 12) & 0xf) == 0xf)
+			sprintf(cp, "USAD8%s\tr%d, r%d, r%d", COND(opcode),
+				(int) (opcode >> 16) & 0xf,
+				(int) (opcode >> 0) & 0xf,
+				(int) (opcode >> 8) & 0xf);
+		else
+			sprintf(cp, "USADA8%s\tr%d, r%d, r%d, r%d", COND(opcode),
+				(int) (opcode >> 16) & 0xf,
+				(int) (opcode >> 0) & 0xf,
+				(int) (opcode >> 8) & 0xf,
+				(int) (opcode >> 12) & 0xf);
+		return ERROR_OK;
+	}
+	if (mnemonic) {
+		unsigned rm = (opcode >> 0) & 0xf;
+		unsigned rd = (opcode >> 12) & 0xf;
+
+		sprintf(cp, "%s%s\tr%d, r%d", mnemonic, COND(opcode), rm, rd);
+		return ERROR_OK;
+	}
+
+undef:
+	/* these opcodes might be used someday */
+	sprintf(cp, "UNDEFINED");
+	return ERROR_OK;
+}
+
 /* Miscellaneous load/store instructions */
 int evaluate_misc_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
 {
@@ -821,6 +1138,21 @@
 		instruction->info.b_bl_bx_blx.target_address = -1;
 	}
 
+	/* BXJ - "Jazelle" support (ARMv5-J) */
+	if ((opcode & 0x006000f0) == 0x00200020)
+	{
+		uint8_t Rm;
+		instruction->type = ARM_BX;
+		Rm = opcode & 0xf;
+
+		snprintf(instruction->text, 128,
+				"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBXJ%s r%i",
+				 address, opcode, COND(opcode), Rm);
+
+		instruction->info.b_bl_bx_blx.reg_operand = Rm;
+		instruction->info.b_bl_bx_blx.target_address = -1;
+	}
+
 	/* CLZ */
 	if ((opcode & 0x006000f0) == 0x00600010)
 	{
@@ -1272,17 +1604,24 @@
 	/* catch opcodes with [27:25] = b011 */
 	if ((opcode & 0x0e000000) == 0x06000000)
 	{
-		/* Undefined instruction */
-		if ((opcode & 0x00000010) == 0x00000010)
+		/* Load/store register offset */
+		if ((opcode & 0x00000010) == 0x00000000)
+			return evaluate_load_store(opcode, address, instruction);
+
+		/* Architecturally Undefined instruction
+		 * ... don't expect these to ever be used
+		 */
+		if ((opcode & 0x07f000f0) == 0x07f000f0)
 		{
 			instruction->type = ARM_UNDEFINED_INSTRUCTION;
-			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode);
+			snprintf(instruction->text, 128,
+				"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEF",
+				address, opcode);
 			return ERROR_OK;
 		}
 
-		/* Load/store register offset */
-		return evaluate_load_store(opcode, address, instruction);
-
+		/* "media" instructions */
+		return evaluate_media(opcode, address, instruction);
 	}
 
 	/* catch opcodes with [27:25] = b100 */

[Openocd-svn] r2643 - in trunk: . src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-27 12:37:01 +0200 (Thu, 27 Aug 2009)
New Revision: 2643

Modified:
   trunk/NEWS
   trunk/src/target/arm11.c
Log:
arm11 hardware step using simulation + breakpoint. Use "hardware_step enable" command to revert to hardware stepping. Ideally we could retire the "hardware_step enable" command once we no longer believe it to be necessary. 

Modified: trunk/NEWS
===================================================================
--- trunk/NEWS	2009-08-27 07:37:07 UTC (rev 2642)
+++ trunk/NEWS	2009-08-27 10:37:01 UTC (rev 2643)
@@ -12,7 +12,8 @@
 	"cortex_m3 vector_catch" ... traps certain hardware faults
 		without tying up breakpoint resources
     If you're willing to help debug it:  VERY EARLY Cortex-A8 support
-    New commands for use with XScale processors: "xscale vector_table" 
+    New commands for use with XScale processors: "xscale vector_table"
+    ARM11 single stepping support for i.MX31 
 
 Flash Layer:
     The lpc2000 driver handles the new NXP LPC1700 (Cortex-M3) chips

Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c	2009-08-27 07:37:07 UTC (rev 2642)
+++ trunk/src/target/arm11.c	2009-08-27 10:37:01 UTC (rev 2643)
@@ -55,6 +55,7 @@
 uint32_t		arm11_vcr								= 0;
 bool	arm11_config_memrw_no_increment			= false;
 bool	arm11_config_step_irq_enable			= false;
+bool	arm11_config_hardware_step				= false;
 
 #define ARM11_HANDLER(x)	\
 	.x				= arm11_##x
@@ -976,7 +977,6 @@
 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
 {
 	FNC_INFO;
-	int retval;
 
 	LOG_DEBUG("target->state: %s",
 		target_state_name(target));
@@ -995,15 +995,6 @@
 	LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
 
 
-	/* TODO: to implement single stepping on arm11 devices that can't
-	 * do single stepping in hardware we need to calculate the next
-	 * pc and set up breakpoints accordingingly. */
-	uint32_t next_pc;
-	retval = arm11_simulate_step(target, &next_pc);
-	if (retval != ERROR_OK)
-		return retval;
-
-
 	/** \todo TODO: Thumb not supported here */
 
 	uint32_t	next_instruction;
@@ -1047,11 +1038,31 @@
 
 		brp[0].write	= 1;
 		brp[0].address	= ARM11_SC7_BVR0;
-		brp[0].value	= R(PC);
 		brp[1].write	= 1;
 		brp[1].address	= ARM11_SC7_BCR0;
-		brp[1].value	= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
 
+		if (arm11_config_hardware_step)
+		{
+			/* hardware single stepping be used if possible or is it better to
+			 * always use the same code path? Hardware single stepping is not supported
+			 * on all hardware
+			 */
+			 brp[0].value	= R(PC);
+			 brp[1].value	= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
+		} else
+		{
+			/* sets a breakpoint on the next PC(calculated by simulation),
+			 */
+			uint32_t next_pc;
+			int retval;
+			retval = arm11_simulate_step(target, &next_pc);
+			if (retval != ERROR_OK)
+				return retval;
+				
+			brp[0].value	= next_pc;
+			brp[1].value	= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
+		}
+
 		CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
 
 		/* resume */
@@ -1102,11 +1113,6 @@
 
 	CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
 
-	if (R(PC) != next_pc)
-	{
-		LOG_WARNING("next pc != simulated address %08" PRIx32 "!=%08" PRIx32, R(PC), next_pc);
-	}
-
 	return ERROR_OK;
 }
 
@@ -1908,6 +1914,7 @@
 BOOL_WRAPPER(memwrite_error_fatal,		"fatal error mode for memory writes")
 BOOL_WRAPPER(memrw_no_increment,		"\"no increment\" mode for memory transfers")
 BOOL_WRAPPER(step_irq_enable,			"IRQs while stepping")
+BOOL_WRAPPER(hardware_step,			"hardware single step")
 
 int arm11_handle_vcr(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
@@ -2070,8 +2077,10 @@
 	RC_FINAL_BOOL("no_increment",			"Don't increment address on multi-read/-write (default: disabled)",
 						memrw_no_increment)
 
-	RC_FINAL_BOOL("step_irq_enable",		"Enable interrupts while stepping (default: disabled)",
-						step_irq_enable)
+RC_FINAL_BOOL("step_irq_enable",		"Enable interrupts while stepping (default: disabled)",
+					step_irq_enable)
+RC_FINAL_BOOL("hardware_step",		"hardware single stepping. By default use simulate + breakpoint. This command is only here to check if simulate + breakpoint implementation is broken.",
+					hardware_step)
 
 	RC_FINAL("vcr",					"Control (Interrupt) Vector Catch Register",
 						arm11_handle_vcr)

[Openocd-svn] r2642 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-27 09:37:07 +0200 (Thu, 27 Aug 2009)
New Revision: 2642

Modified:
   trunk/src/target/arm11.c
Log:
arm11 single stepping wip - at least we know the next PC now

Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c	2009-08-27 07:35:47 UTC (rev 2641)
+++ trunk/src/target/arm11.c	2009-08-27 07:37:07 UTC (rev 2642)
@@ -994,6 +994,10 @@
 
 	LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
 
+
+	/* TODO: to implement single stepping on arm11 devices that can't
+	 * do single stepping in hardware we need to calculate the next
+	 * pc and set up breakpoints accordingingly. */
 	uint32_t next_pc;
 	retval = arm11_simulate_step(target, &next_pc);
 	if (retval != ERROR_OK)

[Openocd-svn] r2641 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-27 09:35:47 +0200 (Thu, 27 Aug 2009)
New Revision: 2641

Modified:
   trunk/src/target/arm11.c
Log:
arm11 single stepping wip

Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c	2009-08-27 06:50:36 UTC (rev 2640)
+++ trunk/src/target/arm11.c	2009-08-27 07:35:47 UTC (rev 2641)
@@ -27,6 +27,8 @@
 #endif
 
 #include "arm11.h"
+#include "armv4_5.h"
+#include "arm_simulator.h"
 #include "target_type.h"
 
 
@@ -884,9 +886,97 @@
 	return ERROR_OK;
 }
 
+
+static int armv4_5_to_arm11(int reg)
+{
+	if (reg < 16)
+		return reg;
+	switch (reg)
+	{
+	case ARMV4_5_CPSR:
+		return ARM11_RC_CPSR;
+	case 16:
+		/* FIX!!! handle thumb better! */
+		return ARM11_RC_CPSR;
+	default:
+		LOG_ERROR("BUG: register translation from armv4_5 to arm11 not supported %d", reg);
+		exit(-1);
+	}
+}
+
+
+static uint32_t arm11_sim_get_reg(struct arm_sim_interface *sim, int reg)
+{
+	arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+
+	reg=armv4_5_to_arm11(reg);
+
+	return buf_get_u32(arm11->reg_list[reg].value, 0, 32);
+}
+
+static void arm11_sim_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
+{
+	arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+
+	reg=armv4_5_to_arm11(reg);
+
+	buf_set_u32(arm11->reg_list[reg].value, 0, 32, value);
+}
+
+static uint32_t arm11_sim_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
+{
+	arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+
+	return buf_get_u32(arm11->reg_list[ARM11_RC_CPSR].value, pos, bits);
+}
+
+static enum armv4_5_state arm11_sim_get_state(struct arm_sim_interface *sim)
+{
+//	arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+
+	/* FIX!!!! we should implement thumb for arm11 */
+	return ARMV4_5_STATE_ARM;
+}
+
+static void arm11_sim_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
+{
+//	arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+
+	/* FIX!!!! we should implement thumb for arm11 */
+	LOG_ERROR("Not implemetned!");
+}
+
+
+static enum armv4_5_mode arm11_sim_get_mode(struct arm_sim_interface *sim)
+{
+	//arm11_common_t * arm11 = (arm11_common_t *)sim->user_data;
+
+	/* FIX!!!! we should implement something that returns the current mode here!!! */
+	return ARMV4_5_MODE_USR;
+}
+
+static int arm11_simulate_step(target_t *target, uint32_t *dry_run_pc)
+{
+	struct arm_sim_interface sim;
+
+	sim.user_data=target->arch_info;
+	sim.get_reg=&arm11_sim_get_reg;
+	sim.set_reg=&arm11_sim_set_reg;
+	sim.get_reg_mode=&arm11_sim_get_reg;
+	sim.set_reg_mode=&arm11_sim_set_reg;
+	sim.get_cpsr=&arm11_sim_get_cpsr;
+	sim.get_mode=&arm11_sim_get_mode;
+	sim.get_state=&arm11_sim_get_state;
+	sim.set_state=&arm11_sim_set_state;
+
+	return arm_simulate_step_core(target, dry_run_pc, &sim);
+
+}
+
 int arm11_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
 {
 	FNC_INFO;
+	int retval;
 
 	LOG_DEBUG("target->state: %s",
 		target_state_name(target));
@@ -904,6 +994,12 @@
 
 	LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
 
+	uint32_t next_pc;
+	retval = arm11_simulate_step(target, &next_pc);
+	if (retval != ERROR_OK)
+		return retval;
+
+
 	/** \todo TODO: Thumb not supported here */
 
 	uint32_t	next_instruction;
@@ -1002,6 +1098,11 @@
 
 	CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
 
+	if (R(PC) != next_pc)
+	{
+		LOG_WARNING("next pc != simulated address %08" PRIx32 "!=%08" PRIx32, R(PC), next_pc);
+	}
+
 	return ERROR_OK;
 }
 

[Openocd-svn] r2640 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-08-27 08:50:36 +0200 (Thu, 27 Aug 2009)
New Revision: 2640

Modified:
   trunk/src/target/arm_simulator.c
   trunk/src/target/arm_simulator.h
Log:
refactor arm simulator to allow arm11 code to use it as well - no observable changes otherwise.

Modified: trunk/src/target/arm_simulator.c
===================================================================
--- trunk/src/target/arm_simulator.c	2009-08-26 19:27:33 UTC (rev 2639)
+++ trunk/src/target/arm_simulator.c	2009-08-27 06:50:36 UTC (rev 2640)
@@ -122,17 +122,18 @@
 	return return_value;
 }
 
-uint32_t arm_shifter_operand(armv4_5_common_t *armv4_5, int variant, union arm_shifter_operand shifter_operand, uint8_t *shifter_carry_out)
+
+uint32_t arm_shifter_operand(struct arm_sim_interface *sim, int variant, union arm_shifter_operand shifter_operand, uint8_t *shifter_carry_out)
 {
 	uint32_t return_value;
 	int instruction_size;
 
-	if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+	if (sim->get_state(sim) == ARMV4_5_STATE_ARM)
 		instruction_size = 4;
 	else
 		instruction_size = 2;
 
-	*shifter_carry_out = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
+	*shifter_carry_out = sim->get_cpsr(sim, 29, 1);
 
 	if (variant == 0) /* 32-bit immediate */
 	{
@@ -140,7 +141,7 @@
 	}
 	else if (variant == 1) /* immediate shift */
 	{
-		uint32_t Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.immediate_shift.Rm).value, 0, 32);
+		uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.immediate_shift.Rm);
 
 		/* adjust RM in case the PC is being read */
 		if (shifter_operand.immediate_shift.Rm == 15)
@@ -150,8 +151,8 @@
 	}
 	else if (variant == 2) /* register shift */
 	{
-		uint32_t Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.register_shift.Rm).value, 0, 32);
-		uint32_t Rs = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, shifter_operand.register_shift.Rs).value, 0, 32);
+		uint32_t Rm = sim->get_reg_mode(sim, shifter_operand.register_shift.Rm);
+		uint32_t Rs = sim->get_reg_mode(sim, shifter_operand.register_shift.Rs);
 
 		/* adjust RM in case the PC is being read */
 		if (shifter_operand.register_shift.Rm == 15)
@@ -267,15 +268,14 @@
  * if the dry_run_pc argument is provided, no state is changed,
  * but the new pc is stored in the variable pointed at by the argument
  */
-int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
+int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_sim_interface *sim)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	uint32_t current_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
+	uint32_t current_pc = sim->get_reg(sim, 15);
 	arm_instruction_t instruction;
 	int instruction_size;
 	int retval = ERROR_OK;
 
-	if (armv4_5->core_state == ARMV4_5_STATE_ARM)
+	if (sim->get_state(sim) == ARMV4_5_STATE_ARM)
 	{
 		uint32_t opcode;
 
@@ -291,7 +291,7 @@
 		instruction_size = 4;
 
 		/* check condition code (for all instructions) */
-		if (!pass_condition(buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), opcode))
+		if (!pass_condition(sim->get_cpsr(sim, 0, 32), opcode))
 		{
 			if (dry_run_pc)
 			{
@@ -299,7 +299,7 @@
 			}
 			else
 			{
-				buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size);
+				sim->set_reg(sim, 15, current_pc + instruction_size);
 			}
 
 			return ERROR_OK;
@@ -320,7 +320,7 @@
 		instruction_size = 2;
 
 		/* check condition code (only for branch instructions) */
-		if ((!thumb_pass_branch_condition(buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32), opcode)) &&
+		if ((!thumb_pass_branch_condition(sim->get_cpsr(sim, 0, 32), opcode)) &&
 			(instruction.type == ARM_B))
 		{
 			if (dry_run_pc)
@@ -329,7 +329,7 @@
 			}
 			else
 			{
-				buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size);
+				sim->set_reg(sim, 15, current_pc + instruction_size);
 			}
 
 			return ERROR_OK;
@@ -349,7 +349,7 @@
 		}
 		else
 		{
-			target = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.b_bl_bx_blx.reg_operand).value, 0, 32);
+			target = sim->get_reg_mode(sim, instruction.info.b_bl_bx_blx.reg_operand);
 			if (instruction.info.b_bl_bx_blx.reg_operand == 15)
 			{
 				target += 2 * instruction_size;
@@ -365,40 +365,40 @@
 		{
 			if (instruction.type == ARM_B)
 			{
-				buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target);
+				sim->set_reg(sim, 15, target);
 			}
 			else if (instruction.type == ARM_BL)
 			{
-				uint32_t old_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
-				buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 14).value, 0, 32, old_pc + 4);
-				buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target);
+				uint32_t old_pc = sim->get_reg(sim, 15);
+				sim->set_reg_mode(sim, 14, old_pc + 4);
+				sim->set_reg(sim, 15, target);
 			}
 			else if (instruction.type == ARM_BX)
 			{
 				if (target & 0x1)
 				{
-					armv4_5->core_state = ARMV4_5_STATE_THUMB;
+					sim->set_state(sim, ARMV4_5_STATE_THUMB);
 				}
 				else
 				{
-					armv4_5->core_state = ARMV4_5_STATE_ARM;
+					sim->set_state(sim, ARMV4_5_STATE_ARM);
 				}
-				buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target & 0xfffffffe);
+				sim->set_reg(sim, 15, target & 0xfffffffe);
 			}
 			else if (instruction.type == ARM_BLX)
 			{
-				uint32_t old_pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
-				buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 14).value, 0, 32, old_pc + 4);
+				uint32_t old_pc = sim->get_reg(sim, 15);
+				sim->set_reg_mode(sim, 14, old_pc + 4);
 
 				if (target & 0x1)
 				{
-					armv4_5->core_state = ARMV4_5_STATE_THUMB;
+					sim->set_state(sim, ARMV4_5_STATE_THUMB);
 				}
 				else
 				{
-					armv4_5->core_state = ARMV4_5_STATE_ARM;
+					sim->set_state(sim, ARMV4_5_STATE_ARM);
 				}
-				buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, target & 0xfffffffe);
+				sim->set_reg(sim, 15, target & 0xfffffffe);
 			}
 
 			return ERROR_OK;
@@ -409,17 +409,17 @@
 			|| ((instruction.type >= ARM_ORR) && (instruction.type <= ARM_MVN)))
 	{
 		uint32_t Rd, Rn, shifter_operand;
-		uint8_t C = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
+		uint8_t C = sim->get_cpsr(sim, 29, 1);
 		uint8_t carry_out;
 
 		Rd = 0x0;
 		/* ARM_MOV and ARM_MVN does not use Rn */
 		if ((instruction.type != ARM_MOV) && (instruction.type != ARM_MVN))
-			Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rn).value, 0, 32);
+			Rn = sim->get_reg_mode(sim, instruction.info.data_proc.Rn);
 		else
 			Rn = 0;
 
-		shifter_operand = arm_shifter_operand(armv4_5, instruction.info.data_proc.variant, instruction.info.data_proc.shifter_operand, &carry_out);
+		shifter_operand = arm_shifter_operand(sim, instruction.info.data_proc.variant, instruction.info.data_proc.shifter_operand, &carry_out);
 
 		/* adjust Rn in case the PC is being read */
 		if (instruction.info.data_proc.Rn == 15)
@@ -468,7 +468,7 @@
 		}
 		else
 		{
-			buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.data_proc.Rd).value, 0, 32, Rd);
+			sim->set_reg_mode(sim, instruction.info.data_proc.Rd, Rd);
 			LOG_WARNING("no updating of flags yet");
 
 			if (instruction.info.data_proc.Rd == 15)
@@ -492,7 +492,7 @@
 	else if ((instruction.type >= ARM_LDR) && (instruction.type <= ARM_LDRSH))
 	{
 		uint32_t load_address = 0, modified_address = 0, load_value;
-		uint32_t Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rn).value, 0, 32);
+		uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store.Rn);
 
 		/* adjust Rn in case the PC is being read */
 		if (instruction.info.load_store.Rn == 15)
@@ -508,10 +508,10 @@
 		else if (instruction.info.load_store.offset_mode == 1)
 		{
 			uint32_t offset;
-			uint32_t Rm = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.offset.reg.Rm).value, 0, 32);
+			uint32_t Rm = sim->get_reg_mode(sim, instruction.info.load_store.offset.reg.Rm);
 			uint8_t shift = instruction.info.load_store.offset.reg.shift;
 			uint8_t shift_imm = instruction.info.load_store.offset.reg.shift_imm;
-			uint8_t carry = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 29, 1);
+			uint8_t carry = sim->get_cpsr(sim, 29, 1);
 
 			offset = arm_shift(shift, Rm, shift_imm, &carry);
 
@@ -572,9 +572,9 @@
 			if ((instruction.info.load_store.index_mode == 1) ||
 				(instruction.info.load_store.index_mode == 2))
 			{
-				buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rn).value, 0, 32, modified_address);
+				sim->set_reg_mode(sim, instruction.info.load_store.Rn, modified_address);
 			}
-			buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store.Rd).value, 0, 32, load_value);
+			sim->set_reg_mode(sim, instruction.info.load_store.Rd, load_value);
 
 			if (instruction.info.load_store.Rd == 15)
 				return ERROR_OK;
@@ -584,7 +584,7 @@
 	else if (instruction.type == ARM_LDM)
 	{
 		int i;
-		uint32_t Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32);
+		uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.Rn);
 		uint32_t load_values[16];
 		int bits_set = 0;
 
@@ -632,7 +632,7 @@
 		}
 		else
 		{
-			enum armv4_5_mode mode = armv4_5->core_mode;
+			enum armv4_5_mode mode = sim->get_mode(sim);
 			int update_cpsr = 0;
 
 			if (instruction.info.load_store_multiple.S)
@@ -647,19 +647,19 @@
 			{
 				if (instruction.info.load_store_multiple.register_list & (1 << i))
 				{
-					buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, mode, i).value, 0, 32, load_values[i]);
+					sim->set_reg_mode(sim, i, load_values[i]);
 				}
 			}
 
 			if (update_cpsr)
 			{
-				uint32_t spsr = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32);
-				buf_set_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32, spsr);
+				uint32_t spsr = sim->get_reg_mode(sim, 16);
+				sim->set_reg(sim, ARMV4_5_CPSR, spsr);
 			}
 
 			/* base register writeback */
 			if (instruction.info.load_store_multiple.W)
-				buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32, Rn);
+				sim->set_reg_mode(sim, instruction.info.load_store_multiple.Rn, Rn);
 
 			if (instruction.info.load_store_multiple.register_list & 0x8000)
 				return ERROR_OK;
@@ -676,9 +676,9 @@
 		}
 		else
 		{
-			uint32_t Rn = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32);
+			uint32_t Rn = sim->get_reg_mode(sim, instruction.info.load_store_multiple.Rn);
 			int bits_set = 0;
-			enum armv4_5_mode mode = armv4_5->core_mode;
+			enum armv4_5_mode mode = sim->get_mode(sim);
 
 			for (i = 0; i < 16; i++)
 			{
@@ -711,14 +711,14 @@
 			{
 				if (instruction.info.load_store_multiple.register_list & (1 << i))
 				{
-					target_write_u32(target, Rn, buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32));
+					target_write_u32(target, Rn, sim->get_reg_mode(sim, i));
 					Rn += 4;
 				}
 			}
 
 			/* base register writeback */
 			if (instruction.info.load_store_multiple.W)
-				buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, instruction.info.load_store_multiple.Rn).value, 0, 32, Rn);
+				sim->set_reg_mode(sim, instruction.info.load_store_multiple.Rn, Rn);
 
 		}
 	}
@@ -726,7 +726,8 @@
 	{
 		/* the instruction wasn't handled, but we're supposed to simulate it
 		 */
-		return ERROR_ARM_SIMULATOR_NOT_IMPLEMENTED;
+		LOG_ERROR("Unimplemented instruction, could not simulate it.");
+		return ERROR_FAIL;
 	}
 
 	if (dry_run_pc)
@@ -736,8 +737,88 @@
 	}
 	else
 	{
-		buf_set_u32(armv4_5->core_cache->reg_list[15].value, 0, 32, current_pc + instruction_size);
+		sim->set_reg(sim, 15, current_pc + instruction_size);
 		return ERROR_OK;
 	}
 
 }
+
+static uint32_t armv4_5_get_reg(struct arm_sim_interface *sim, int reg)
+{
+	armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+	return buf_get_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32);
+}
+
+static void armv4_5_set_reg(struct arm_sim_interface *sim, int reg, uint32_t value)
+{
+	armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+	buf_set_u32(armv4_5->core_cache->reg_list[reg].value, 0, 32, value);
+}
+
+static uint32_t armv4_5_get_reg_mode(struct arm_sim_interface *sim, int reg)
+{
+	armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+	return buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, reg).value, 0, 32);
+}
+
+static void armv4_5_set_reg_mode(struct arm_sim_interface *sim, int reg, uint32_t value)
+{
+	armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+	buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, reg).value, 0, 32, value);
+}
+
+static uint32_t armv4_5_get_cpsr(struct arm_sim_interface *sim, int pos, int bits)
+{
+	armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+	return buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, pos, bits);
+}
+
+static enum armv4_5_state armv4_5_get_state(struct arm_sim_interface *sim)
+{
+	armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+	return armv4_5->core_state;
+}
+
+static void armv4_5_set_state(struct arm_sim_interface *sim, enum armv4_5_state mode)
+{
+	armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+	armv4_5->core_state = mode;
+}
+
+
+static enum armv4_5_mode armv4_5_get_mode(struct arm_sim_interface *sim)
+{
+	armv4_5_common_t *armv4_5 = (armv4_5_common_t *)sim->user_data;
+
+	return armv4_5->core_mode;
+}
+
+
+
+int arm_simulate_step(target_t *target, uint32_t *dry_run_pc)
+{
+	armv4_5_common_t *armv4_5 = target->arch_info;
+
+	struct arm_sim_interface sim;
+
+	sim.user_data=armv4_5;
+	sim.get_reg=&armv4_5_get_reg;
+	sim.set_reg=&armv4_5_set_reg;
+	sim.get_reg_mode=&armv4_5_get_reg_mode;
+	sim.set_reg_mode=&armv4_5_set_reg_mode;
+	sim.get_cpsr=&armv4_5_get_cpsr;
+	sim.get_mode=&armv4_5_get_mode;
+	sim.get_state=&armv4_5_get_state;
+	sim.set_state=&armv4_5_set_state;
+
+	return arm_simulate_step_core(target, dry_run_pc, &sim);
+
+}
+

Modified: trunk/src/target/arm_simulator.h
===================================================================
--- trunk/src/target/arm_simulator.h	2009-08-26 19:27:33 UTC (rev 2639)
+++ trunk/src/target/arm_simulator.h	2009-08-27 06:50:36 UTC (rev 2640)
@@ -24,8 +24,25 @@
 
 struct target_s;
 
+struct arm_sim_interface
+{
+	void *user_data;
+	uint32_t (*get_reg)(struct arm_sim_interface *sim, int reg);
+	void (*set_reg)(struct arm_sim_interface *sim, int reg, uint32_t value);
+	uint32_t (*get_reg_mode)(struct arm_sim_interface *sim, int reg);
+	void (*set_reg_mode)(struct arm_sim_interface *sim, int reg, uint32_t value);
+	uint32_t (*get_cpsr)(struct arm_sim_interface *sim, int pos, int bits);
+	enum armv4_5_state (*get_state)(struct arm_sim_interface *sim);
+	void (*set_state)(struct arm_sim_interface *sim, enum armv4_5_state mode);
+	enum armv4_5_mode (*get_mode)(struct arm_sim_interface *sim);
+};
+
+
+/* armv4_5 version */
 extern int arm_simulate_step(struct target_s *target, uint32_t *dry_run_pc);
 
-#define ERROR_ARM_SIMULATOR_NOT_IMPLEMENTED	(-700)
+/* a generic arm simulator. Caller must implement the sim interface */
+extern int arm_simulate_step_core(target_t *target, uint32_t *dry_run_pc, struct arm_sim_interface *sim);
 
+
 #endif /* ARM_SIMULATOR_H */