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|
From: oharboe at B. <oh...@ma...> - 2009-09-11 08:08:54
|
Author: oharboe
Date: 2009-09-11 08:08:51 +0200 (Fri, 11 Sep 2009)
New Revision: 2689
Modified:
trunk/tcl/target/c100helper.tcl
Log:
syntax error fix
Modified: trunk/tcl/target/c100helper.tcl
===================================================================
--- trunk/tcl/target/c100helper.tcl 2009-09-11 06:01:28 UTC (rev 2688)
+++ trunk/tcl/target/c100helper.tcl 2009-09-11 06:08:51 UTC (rev 2689)
@@ -328,6 +328,7 @@
configureDDR2regs_256B
} else {
puts "Don't know how to configure DDR2 setup?"
+ }
}
|
|
From: oharboe at B. <oh...@ma...> - 2009-09-11 08:01:28
|
Author: oharboe
Date: 2009-09-11 08:01:28 +0200 (Fri, 11 Sep 2009)
New Revision: 2688
Modified:
trunk/src/flash/mx3_nand.c
trunk/src/flash/mx3_nand.h
Log:
Alexei Babich <a.b...@re...> cleanup
Modified: trunk/src/flash/mx3_nand.c
===================================================================
--- trunk/src/flash/mx3_nand.c 2009-09-11 05:57:51 UTC (rev 2687)
+++ trunk/src/flash/mx3_nand.c 2009-09-11 06:01:28 UTC (rev 2688)
@@ -43,8 +43,6 @@
"minimal granularity is one half-word, %d is incorrect";
static const char sram_buffer_bounds_err_msg[] =
"trying to access out of SRAM buffer bound (addr=0x%x)";
-static const char invalid_command_sequense_err_msg[] =
- "invalid command sequence in %s";
static const char get_status_register_err_msg[] = "can't get NAND status";
static uint32_t in_sram_address;
unsigned char sign_of_sequental_byte_read;
@@ -237,7 +235,7 @@
* testing IOMUX settings; must be in "functional-mode output and
* functional-mode input" mode
*/
- uint8_t test_iomux;
+ int test_iomux;
test_iomux = ERROR_OK;
test_iomux |=
test_iomux_settings (target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
@@ -438,10 +436,6 @@
mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
break;
- case NAND_CMD_SEQIN:
- LOG_ERROR ("aaa");
- return ERROR_FAIL;
- break;
default:
mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
}
Modified: trunk/src/flash/mx3_nand.h
===================================================================
--- trunk/src/flash/mx3_nand.h 2009-09-11 05:57:51 UTC (rev 2687)
+++ trunk/src/flash/mx3_nand.h 2009-09-11 06:01:28 UTC (rev 2688)
@@ -1,3 +1,30 @@
+
+/***************************************************************************
+ * Copyright (C) 2009 by Alexei Babich *
+ * Rezonans plc., Chelyabinsk, Russia *
+ * im...@ma... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+
+/*
+ * Freescale iMX3* OpenOCD NAND Flash controller support.
+ *
+ * Many thanks to Ben Dooks for writing s3c24xx driver.
+ */
#include <nand.h>
#define MX3_NF_BASE_ADDR 0xb8000000
|
|
From: oharboe at B. <oh...@ma...> - 2009-09-11 07:57:53
|
Author: oharboe
Date: 2009-09-11 07:57:51 +0200 (Fri, 11 Sep 2009)
New Revision: 2687
Modified:
trunk/src/target/feroceon.c
Log:
Nicolas Pitre <ni...@ca...> tighten error checking in bulk_write
Modified: trunk/src/target/feroceon.c
===================================================================
--- trunk/src/target/feroceon.c 2009-09-10 13:35:08 UTC (rev 2686)
+++ trunk/src/target/feroceon.c 2009-09-11 05:57:51 UTC (rev 2687)
@@ -591,9 +591,20 @@
buffer += 4;
}
- target_halt(target);
- while (target->state != TARGET_HALTED)
- target_poll(target);
+ retval = target_halt(target);
+ if (retval == ERROR_OK)
+ retval = target_wait_state(target, TARGET_HALTED, 500);
+ if (retval == ERROR_OK) {
+ uint32_t endaddress =
+ buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
+ if (endaddress != address + count*4) {
+ LOG_ERROR("DCC write failed,"
+ " expected end address 0x%08" PRIx32
+ " got 0x%0" PRIx32 "",
+ address + count*4, endaddress);
+ retval = ERROR_FAIL;
+ }
+ }
/* restore target state */
for (i = 0; i <= 5; i++)
@@ -607,7 +618,7 @@
armv4_5->core_cache->reg_list[15].dirty = 1;
armv4_5->core_state = core_state;
- return ERROR_OK;
+ return retval;
}
int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
|
|
From: oharboe at B. <oh...@ma...> - 2009-09-10 15:35:10
|
Author: oharboe Date: 2009-09-10 15:35:08 +0200 (Thu, 10 Sep 2009) New Revision: 2686 Modified: trunk/src/flash/mx3_nand.c trunk/src/flash/mx3_nand.h Log: eol-style:native Property changes on: trunk/src/flash/mx3_nand.c ___________________________________________________________________ Name: svn:eol-style + native Property changes on: trunk/src/flash/mx3_nand.h ___________________________________________________________________ Name: svn:eol-style + native |
|
From: oharboe at B. <oh...@ma...> - 2009-09-10 15:17:26
|
Author: oharboe
Date: 2009-09-10 15:17:25 +0200 (Thu, 10 Sep 2009)
New Revision: 2685
Added:
trunk/src/flash/mx3_nand.c
trunk/src/flash/mx3_nand.h
Modified:
trunk/src/flash/Makefile.am
trunk/src/flash/nand.c
Log:
Alexei Babich <a.b...@re...> imx31 nand flash controller support
Modified: trunk/src/flash/Makefile.am
===================================================================
--- trunk/src/flash/Makefile.am 2009-09-10 13:17:05 UTC (rev 2684)
+++ trunk/src/flash/Makefile.am 2009-09-10 13:17:25 UTC (rev 2685)
@@ -36,7 +36,8 @@
ocl.c \
mflash.c \
pic32mx.c \
- avrf.c
+ avrf.c \
+ mx3_nand.c
noinst_HEADERS = \
arm_nandio.h \
@@ -60,6 +61,7 @@
mflash.h \
ocl.h \
pic32mx.h \
- avrf.h
+ avrf.h \
+ mx3_nand.h
MAINTAINERCLEANFILES = $(srcdir)/Makefile.in
Added: trunk/src/flash/mx3_nand.c
===================================================================
--- trunk/src/flash/mx3_nand.c 2009-09-10 13:17:05 UTC (rev 2684)
+++ trunk/src/flash/mx3_nand.c 2009-09-10 13:17:25 UTC (rev 2685)
@@ -0,0 +1,908 @@
+
+/***************************************************************************
+ * Copyright (C) 2009 by Alexei Babich *
+ * Rezonans plc., Chelyabinsk, Russia *
+ * im...@ma... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+
+/*
+ * Freescale iMX3* OpenOCD NAND Flash controller support.
+ *
+ * Many thanks to Ben Dooks for writing s3c24xx driver.
+ */
+
+/*
+driver tested with STMicro NAND512W3A @imx31
+tested "nand probe #", "nand erase # 0 #", "nand dump # file 0 #", "nand write # file 0"
+get_next_halfword_from_sram_buffer() not tested
+*/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "mx3_nand.h"
+
+static const char target_not_halted_err_msg[] =
+ "target must be halted to use mx3 NAND flash controller";
+static const char data_block_size_err_msg[] =
+ "minimal granularity is one half-word, %d is incorrect";
+static const char sram_buffer_bounds_err_msg[] =
+ "trying to access out of SRAM buffer bound (addr=0x%x)";
+static const char invalid_command_sequense_err_msg[] =
+ "invalid command sequence in %s";
+static const char get_status_register_err_msg[] = "can't get NAND status";
+static uint32_t in_sram_address;
+unsigned char sign_of_sequental_byte_read;
+
+static int test_iomux_settings (target_t * target, uint32_t value,
+ uint32_t mask, const char *text);
+static int initialize_nf_controller (struct nand_device_s *device);
+static int get_next_byte_from_sram_buffer (target_t * target, uint8_t * value);
+static int get_next_halfword_from_sram_buffer (target_t * target,
+ uint16_t * value);
+static int poll_for_complete_op (target_t * target, const char *text);
+static int validate_target_state (struct nand_device_s *device);
+static int do_data_output (struct nand_device_s *device);
+
+static int imx31_nand_device_command (struct command_context_s *cmd_ctx,
+ char *cmd, char **args, int argc,
+ struct nand_device_s *device);
+static int imx31_init (struct nand_device_s *device);
+static int imx31_read_data (struct nand_device_s *device, void *data);
+static int imx31_write_data (struct nand_device_s *device, uint16_t data);
+static int imx31_nand_ready (struct nand_device_s *device, int timeout);
+static int imx31_register_commands (struct command_context_s *cmd_ctx);
+static int imx31_reset (struct nand_device_s *device);
+static int imx31_command (struct nand_device_s *device, uint8_t command);
+static int imx31_address (struct nand_device_s *device, uint8_t address);
+static int imx31_controller_ready (struct nand_device_s *device, int tout);
+static int imx31_write_page (struct nand_device_s *device, uint32_t page,
+ uint8_t * data, uint32_t data_size, uint8_t * oob,
+ uint32_t oob_size);
+static int imx31_read_page (struct nand_device_s *device, uint32_t page,
+ uint8_t * data, uint32_t data_size, uint8_t * oob,
+ uint32_t oob_size);
+
+nand_flash_controller_t imx31_nand_flash_controller = {
+ .name = "imx31",
+ .nand_device_command = imx31_nand_device_command,
+ .register_commands = imx31_register_commands,
+ .init = imx31_init,
+ .reset = imx31_reset,
+ .command = imx31_command,
+ .address = imx31_address,
+ .write_data = imx31_write_data,
+ .read_data = imx31_read_data,
+ .write_page = imx31_write_page,
+ .read_page = imx31_read_page,
+ .controller_ready = imx31_controller_ready,
+ .nand_ready = imx31_nand_ready,
+};
+
+static int imx31_nand_device_command (struct command_context_s *cmd_ctx,
+ char *cmd, char **args, int argc,
+ struct nand_device_s *device)
+{
+ mx3_nf_controller_t *mx3_nf_info;
+ mx3_nf_info = malloc (sizeof (mx3_nf_controller_t));
+ if (mx3_nf_info == NULL)
+ {
+ LOG_ERROR ("no memory for nand controller");
+ return ERROR_FAIL;
+ }
+
+ device->controller_priv = mx3_nf_info;
+
+ mx3_nf_info->target = get_target (args[1]);
+ if (mx3_nf_info->target == NULL)
+ {
+ LOG_ERROR ("target '%s' not defined", args[1]);
+ return ERROR_FAIL;
+ }
+ if (argc < 3)
+ {
+ LOG_ERROR ("use \"nand device imx31 target noecc|hwecc\"");
+ return ERROR_FAIL;
+ }
+ /*
+ * check hwecc requirements
+ */
+ {
+ int hwecc_needed;
+ hwecc_needed = strcmp (args[2], "hwecc");
+ if (hwecc_needed == 0)
+ {
+ mx3_nf_info->flags.hw_ecc_enabled = 1;
+ }
+ else
+ {
+ mx3_nf_info->flags.hw_ecc_enabled = 0;
+ }
+ }
+
+ mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
+ mx3_nf_info->fin = MX3_NF_FIN_NONE;
+ mx3_nf_info->flags.target_little_endian =
+ (mx3_nf_info->target->endianness == TARGET_LITTLE_ENDIAN);
+ /*
+ * testing host endianess
+ */
+ {
+ int x = 1;
+ if (*(char *) &x == 1)
+ {
+ mx3_nf_info->flags.host_little_endian = 1;
+ }
+ else
+ {
+ mx3_nf_info->flags.host_little_endian = 0;
+ }
+ }
+ return ERROR_OK;
+}
+
+static int imx31_init (struct nand_device_s *device)
+{
+ mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
+ target_t *target = mx3_nf_info->target;
+
+ {
+ /*
+ * validate target state
+ */
+ int validate_target_result;
+ validate_target_result = validate_target_state (device);
+ if (validate_target_result != ERROR_OK)
+ {
+ return validate_target_result;
+ }
+ }
+
+ {
+ uint16_t buffsize_register_content;
+ target_read_u16 (target, MX3_NF_BUFSIZ, &buffsize_register_content);
+ mx3_nf_info->flags.one_kb_sram = !(buffsize_register_content & 0x000f);
+ }
+
+ {
+ uint32_t pcsr_register_content;
+ target_read_u32 (target, MX3_PCSR, &pcsr_register_content);
+ if (!device->bus_width)
+ {
+ device->bus_width =
+ (pcsr_register_content & 0x80000000) ? 16 : 8;
+ }
+ else
+ {
+ pcsr_register_content |=
+ ((device->bus_width == 16) ? 0x80000000 : 0x00000000);
+ target_write_u32 (target, MX3_PCSR, pcsr_register_content);
+ }
+
+ if (!device->page_size)
+ {
+ device->page_size =
+ (pcsr_register_content & 0x40000000) ? 2048 : 512;
+ }
+ else
+ {
+ pcsr_register_content |=
+ ((device->page_size == 2048) ? 0x40000000 : 0x00000000);
+ target_write_u32 (target, MX3_PCSR, pcsr_register_content);
+ }
+ if (mx3_nf_info->flags.one_kb_sram && (device->page_size == 2048))
+ {
+ LOG_ERROR
+ ("NAND controller have only 1 kb SRAM, so pagesize 2048 is incompatible with it");
+ }
+ }
+
+ {
+ uint32_t cgr_register_content;
+ target_read_u32 (target, MX3_CCM_CGR2, &cgr_register_content);
+ if (!(cgr_register_content & 0x00000300))
+ {
+ LOG_ERROR ("clock gating to EMI disabled");
+ return ERROR_FAIL;
+ }
+ }
+
+ {
+ uint32_t gpr_register_content;
+ target_read_u32 (target, MX3_GPR, &gpr_register_content);
+ if (gpr_register_content & 0x00000060)
+ {
+ LOG_ERROR ("pins mode overrided by GPR");
+ return ERROR_FAIL;
+ }
+ }
+
+ {
+ /*
+ * testing IOMUX settings; must be in "functional-mode output and
+ * functional-mode input" mode
+ */
+ uint8_t test_iomux;
+ test_iomux = ERROR_OK;
+ test_iomux |=
+ test_iomux_settings (target, 0x43fac0c0, 0x7f7f7f00, "d0,d1,d2");
+ test_iomux |=
+ test_iomux_settings (target, 0x43fac0c4, 0x7f7f7f7f, "d3,d4,d5,d6");
+ test_iomux |=
+ test_iomux_settings (target, 0x43fac0c8, 0x0000007f, "d7");
+ if (device->bus_width == 16)
+ {
+ test_iomux |=
+ test_iomux_settings (target, 0x43fac0c8, 0x7f7f7f00,
+ "d8,d9,d10");
+ test_iomux |=
+ test_iomux_settings (target, 0x43fac0cc, 0x7f7f7f7f,
+ "d11,d12,d13,d14");
+ test_iomux |=
+ test_iomux_settings (target, 0x43fac0d0, 0x0000007f, "d15");
+ }
+ test_iomux |=
+ test_iomux_settings (target, 0x43fac0d0, 0x7f7f7f00,
+ "nfwp,nfce,nfrb");
+ test_iomux |=
+ test_iomux_settings (target, 0x43fac0d4, 0x7f7f7f7f,
+ "nfwe,nfre,nfale,nfcle");
+ if (test_iomux != ERROR_OK)
+ {
+ return ERROR_FAIL;
+ }
+ }
+
+ initialize_nf_controller (device);
+
+ {
+ int retval;
+ uint16_t nand_status_content;
+ retval = ERROR_OK;
+ retval |= imx31_command (device, NAND_CMD_STATUS);
+ retval |= imx31_address (device, 0x00);
+ retval |= do_data_output (device);
+ if (retval != ERROR_OK)
+ {
+ LOG_ERROR (get_status_register_err_msg);
+ return ERROR_FAIL;
+ }
+ target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
+ if (!(nand_status_content & 0x0080))
+ {
+ /*
+ * is host-big-endian correctly ??
+ */
+ LOG_INFO ("NAND read-only");
+ mx3_nf_info->flags.nand_readonly = 1;
+ }
+ else
+ {
+ mx3_nf_info->flags.nand_readonly = 0;
+ }
+ }
+ return ERROR_OK;
+}
+
+static int imx31_read_data (struct nand_device_s *device, void *data)
+{
+ mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
+ target_t *target = mx3_nf_info->target;
+ {
+ /*
+ * validate target state
+ */
+ int validate_target_result;
+ validate_target_result = validate_target_state (device);
+ if (validate_target_result != ERROR_OK)
+ {
+ return validate_target_result;
+ }
+ }
+
+ {
+ /*
+ * get data from nand chip
+ */
+ int try_data_output_from_nand_chip;
+ try_data_output_from_nand_chip = do_data_output (device);
+ if (try_data_output_from_nand_chip != ERROR_OK)
+ {
+ return try_data_output_from_nand_chip;
+ }
+ }
+
+ if (device->bus_width == 16)
+ {
+ get_next_halfword_from_sram_buffer (target, data);
+ }
+ else
+ {
+ get_next_byte_from_sram_buffer (target, data);
+ }
+
+ return ERROR_OK;
+}
+
+static int imx31_write_data (struct nand_device_s *device, uint16_t data)
+{
+ LOG_ERROR ("write_data() not implemented");
+ return ERROR_NAND_OPERATION_FAILED;
+}
+
+static int imx31_nand_ready (struct nand_device_s *device, int timeout)
+{
+ return imx31_controller_ready (device, timeout);
+}
+
+static int imx31_register_commands (struct command_context_s *cmd_ctx)
+{
+ return ERROR_OK;
+}
+
+static int imx31_reset (struct nand_device_s *device)
+{
+ /*
+ * validate target state
+ */
+ int validate_target_result;
+ validate_target_result = validate_target_state (device);
+ if (validate_target_result != ERROR_OK)
+ {
+ return validate_target_result;
+ }
+ initialize_nf_controller (device);
+ return ERROR_OK;
+}
+
+static int imx31_command (struct nand_device_s *device, uint8_t command)
+{
+ mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
+ target_t *target = mx3_nf_info->target;
+ {
+ /*
+ * validate target state
+ */
+ int validate_target_result;
+ validate_target_result = validate_target_state (device);
+ if (validate_target_result != ERROR_OK)
+ {
+ return validate_target_result;
+ }
+ }
+
+ switch (command)
+ {
+ case NAND_CMD_READOOB:
+ command = NAND_CMD_READ0;
+ in_sram_address = MX3_NF_SPARE_BUFFER0; /* set read point for
+ * data_read() and
+ * read_block_data() to
+ * spare area in SRAM
+ * buffer */
+ break;
+ case NAND_CMD_READ1:
+ command = NAND_CMD_READ0;
+ /*
+ * offset == one half of page size
+ */
+ in_sram_address =
+ MX3_NF_MAIN_BUFFER0 + (device->page_size >> 1);
+ default:
+ in_sram_address = MX3_NF_MAIN_BUFFER0;
+ }
+
+ target_write_u16 (target, MX3_NF_FCMD, command);
+ /*
+ * start command input operation (set MX3_NF_BIT_OP_DONE==0)
+ */
+ target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FCI);
+ {
+ int poll_result;
+ poll_result = poll_for_complete_op (target, "command");
+ if (poll_result != ERROR_OK)
+ {
+ return poll_result;
+ }
+ }
+ /*
+ * reset cursor to begin of the buffer
+ */
+ sign_of_sequental_byte_read = 0;
+ switch (command)
+ {
+ case NAND_CMD_READID:
+ mx3_nf_info->optype = MX3_NF_DATAOUT_NANDID;
+ mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
+ break;
+ case NAND_CMD_STATUS:
+ mx3_nf_info->optype = MX3_NF_DATAOUT_NANDSTATUS;
+ mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
+ break;
+ case NAND_CMD_READ0:
+ mx3_nf_info->fin = MX3_NF_FIN_DATAOUT;
+ mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
+ break;
+ case NAND_CMD_SEQIN:
+ LOG_ERROR ("aaa");
+ return ERROR_FAIL;
+ break;
+ default:
+ mx3_nf_info->optype = MX3_NF_DATAOUT_PAGE;
+ }
+ return ERROR_OK;
+}
+
+static int imx31_address (struct nand_device_s *device, uint8_t address)
+{
+ mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
+ target_t *target = mx3_nf_info->target;
+ {
+ /*
+ * validate target state
+ */
+ int validate_target_result;
+ validate_target_result = validate_target_state (device);
+ if (validate_target_result != ERROR_OK)
+ {
+ return validate_target_result;
+ }
+ }
+
+ target_write_u16 (target, MX3_NF_FADDR, address);
+ /*
+ * start address input operation (set MX3_NF_BIT_OP_DONE==0)
+ */
+ target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FAI);
+ {
+ int poll_result;
+ poll_result = poll_for_complete_op (target, "address");
+ if (poll_result != ERROR_OK)
+ {
+ return poll_result;
+ }
+ }
+ return ERROR_OK;
+}
+
+static int imx31_controller_ready (struct nand_device_s *device, int tout)
+{
+ uint16_t poll_complete_status;
+ mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
+ target_t *target = mx3_nf_info->target;
+
+ {
+ /*
+ * validate target state
+ */
+ int validate_target_result;
+ validate_target_result = validate_target_state (device);
+ if (validate_target_result != ERROR_OK)
+ {
+ return validate_target_result;
+ }
+ }
+
+ do
+ {
+ target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
+ if (poll_complete_status & MX3_NF_BIT_OP_DONE)
+ {
+ return tout;
+ }
+ alive_sleep (1);
+ }
+ while (tout-- > 0);
+ return tout;
+}
+
+static int imx31_write_page (struct nand_device_s *device, uint32_t page,
+ uint8_t * data, uint32_t data_size, uint8_t * oob,
+ uint32_t oob_size)
+{
+ mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
+ target_t *target = mx3_nf_info->target;
+
+ if (data_size % 2)
+ {
+ LOG_ERROR (data_block_size_err_msg, data_size);
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+ if (oob_size % 2)
+ {
+ LOG_ERROR (data_block_size_err_msg, oob_size);
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+ if (!data)
+ {
+ LOG_ERROR ("nothing to program");
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+ {
+ /*
+ * validate target state
+ */
+ int retval;
+ retval = validate_target_state (device);
+ if (retval != ERROR_OK)
+ {
+ return retval;
+ }
+ }
+ {
+ int retval = ERROR_OK;
+ retval |= imx31_command (device, NAND_CMD_SEQIN);
+ retval |= imx31_address (device, 0x00);
+ retval |= imx31_address (device, page & 0xff);
+ retval |= imx31_address (device, (page >> 8) & 0xff);
+ if (device->address_cycles >= 4)
+ {
+ retval |= imx31_address (device, (page >> 16) & 0xff);
+ if (device->address_cycles >= 5)
+ {
+ retval |= imx31_address (device, (page >> 24) & 0xff);
+ }
+ }
+ target_write_buffer (target, MX3_NF_MAIN_BUFFER0, data_size, data);
+ if (oob)
+ {
+ if (mx3_nf_info->flags.hw_ecc_enabled)
+ {
+ /*
+ * part of spare block will be overrided by hardware
+ * ECC generator
+ */
+ LOG_DEBUG
+ ("part of spare block will be overrided by hardware ECC generator");
+ }
+ target_write_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
+ oob);
+ }
+ /*
+ * start data input operation (set MX3_NF_BIT_OP_DONE==0)
+ */
+ target_write_u16 (target, MX3_NF_CFG2, MX3_NF_BIT_OP_FDI);
+ {
+ int poll_result;
+ poll_result = poll_for_complete_op (target, "data input");
+ if (poll_result != ERROR_OK)
+ {
+ return poll_result;
+ }
+ }
+ retval |= imx31_command (device, NAND_CMD_PAGEPROG);
+ if (retval != ERROR_OK)
+ {
+ return retval;
+ }
+
+ /*
+ * check status register
+ */
+ {
+ uint16_t nand_status_content;
+ retval = ERROR_OK;
+ retval |= imx31_command (device, NAND_CMD_STATUS);
+ retval |= imx31_address (device, 0x00);
+ retval |= do_data_output (device);
+ if (retval != ERROR_OK)
+ {
+ LOG_ERROR (get_status_register_err_msg);
+ return retval;
+ }
+ target_read_u16 (target, MX3_NF_MAIN_BUFFER0, &nand_status_content);
+ if (nand_status_content & 0x0001)
+ {
+ /*
+ * is host-big-endian correctly ??
+ */
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+ }
+ }
+ return ERROR_OK;
+}
+
+static int imx31_read_page (struct nand_device_s *device, uint32_t page,
+ uint8_t * data, uint32_t data_size, uint8_t * oob,
+ uint32_t oob_size)
+{
+ mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
+ target_t *target = mx3_nf_info->target;
+
+ if (data_size % 2)
+ {
+ LOG_ERROR (data_block_size_err_msg, data_size);
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+ if (oob_size % 2)
+ {
+ LOG_ERROR (data_block_size_err_msg, oob_size);
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ {
+ /*
+ * validate target state
+ */
+ int retval;
+ retval = validate_target_state (device);
+ if (retval != ERROR_OK)
+ {
+ return retval;
+ }
+ }
+ {
+ int retval = ERROR_OK;
+ retval |= imx31_command (device, NAND_CMD_READ0);
+ retval |= imx31_address (device, 0x00);
+ retval |= imx31_address (device, page & 0xff);
+ retval |= imx31_address (device, (page >> 8) & 0xff);
+ if (device->address_cycles >= 4)
+ {
+ retval |= imx31_address (device, (page >> 16) & 0xff);
+ if (device->address_cycles >= 5)
+ {
+ retval |= imx31_address (device, (page >> 24) & 0xff);
+ retval |= imx31_command (device, NAND_CMD_READSTART);
+ }
+ }
+ retval |= do_data_output (device);
+ if (retval != ERROR_OK)
+ {
+ return retval;
+ }
+
+ if (data)
+ {
+ target_read_buffer (target, MX3_NF_MAIN_BUFFER0, data_size,
+ data);
+ }
+ if (oob)
+ {
+ target_read_buffer (target, MX3_NF_SPARE_BUFFER0, oob_size,
+ oob);
+ }
+ }
+ return ERROR_OK;
+}
+
+static int test_iomux_settings (target_t * target, uint32_t address,
+ uint32_t mask, const char *text)
+{
+ uint32_t register_content;
+ target_read_u32 (target, address, ®ister_content);
+ if ((register_content & mask) != (0x12121212 & mask))
+ {
+ LOG_ERROR ("IOMUX for {%s} is bad", text);
+ return ERROR_FAIL;
+ }
+ return ERROR_OK;
+}
+
+static int initialize_nf_controller (struct nand_device_s *device)
+{
+ mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
+ target_t *target = mx3_nf_info->target;
+ /*
+ * resets NAND flash controller in zero time ? I dont know.
+ */
+ target_write_u16 (target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
+ {
+ uint16_t work_mode;
+ work_mode = MX3_NF_BIT_INT_DIS; /* disable interrupt */
+ if (target->endianness == TARGET_BIG_ENDIAN)
+ {
+ work_mode |= MX3_NF_BIT_BE_EN;
+ }
+ if (mx3_nf_info->flags.hw_ecc_enabled)
+ {
+ work_mode |= MX3_NF_BIT_ECC_EN;
+ }
+ target_write_u16 (target, MX3_NF_CFG1, work_mode);
+ }
+ /*
+ * unlock SRAM buffer for write; 2 mean "Unlock", other values means "Lock"
+ */
+ target_write_u16 (target, MX3_NF_BUFCFG, 2);
+ {
+ uint16_t temp;
+ target_read_u16 (target, MX3_NF_FWP, &temp);
+ if ((temp & 0x0007) == 1)
+ {
+ LOG_ERROR ("NAND flash is tight-locked, reset needed");
+ return ERROR_FAIL;
+ }
+
+ }
+ /*
+ * unlock NAND flash for write
+ */
+ target_write_u16 (target, MX3_NF_FWP, 4);
+ target_write_u16 (target, MX3_NF_LOCKSTART, 0x0000);
+ target_write_u16 (target, MX3_NF_LOCKEND, 0xFFFF);
+ /*
+ * 0x0000 means that first SRAM buffer @0xB800_0000 will be used
+ */
+ target_write_u16 (target, MX3_NF_BUFADDR, 0x0000);
+ /*
+ * address of SRAM buffer
+ */
+ in_sram_address = MX3_NF_MAIN_BUFFER0;
+ sign_of_sequental_byte_read = 0;
+ return ERROR_OK;
+}
+
+static int get_next_byte_from_sram_buffer (target_t * target, uint8_t * value)
+{
+ static uint8_t even_byte = 0;
+ /*
+ * host-big_endian ??
+ */
+ if (sign_of_sequental_byte_read == 0)
+ {
+ even_byte = 0;
+ }
+ if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
+ {
+ LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
+ *value = 0;
+ sign_of_sequental_byte_read = 0;
+ even_byte = 0;
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+ else
+ {
+ uint16_t temp;
+ target_read_u16 (target, in_sram_address, &temp);
+ if (even_byte)
+ {
+ *value = temp >> 8;
+ even_byte = 0;
+ in_sram_address += 2;
+ }
+ else
+ {
+ *value = temp & 0xff;
+ even_byte = 1;
+ }
+ }
+ sign_of_sequental_byte_read = 1;
+ return ERROR_OK;
+}
+
+static int get_next_halfword_from_sram_buffer (target_t * target,
+ uint16_t * value)
+{
+ if (in_sram_address > MX3_NF_LAST_BUFFER_ADDR)
+ {
+ LOG_ERROR (sram_buffer_bounds_err_msg, in_sram_address);
+ *value = 0;
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+ else
+ {
+ target_read_u16 (target, in_sram_address, value);
+ in_sram_address += 2;
+ }
+ return ERROR_OK;
+}
+
+static int poll_for_complete_op (target_t * target, const char *text)
+{
+ uint16_t poll_complete_status;
+ for (int poll_cycle_count = 0; poll_cycle_count < 100; poll_cycle_count++)
+ {
+ usleep (25);
+ target_read_u16 (target, MX3_NF_CFG2, &poll_complete_status);
+ if (poll_complete_status & MX3_NF_BIT_OP_DONE)
+ {
+ break;
+ }
+ }
+ if (!(poll_complete_status & MX3_NF_BIT_OP_DONE))
+ {
+ LOG_ERROR ("%s sending timeout", text);
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+ return ERROR_OK;
+}
+
+static int validate_target_state (struct nand_device_s *device)
+{
+ mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
+ target_t *target = mx3_nf_info->target;
+
+ if (target->state != TARGET_HALTED)
+ {
+ LOG_ERROR (target_not_halted_err_msg);
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ if (mx3_nf_info->flags.target_little_endian !=
+ (target->endianness == TARGET_LITTLE_ENDIAN))
+ {
+ /*
+ * endianness changed after NAND controller probed
+ */
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+ return ERROR_OK;
+}
+
+static int do_data_output (struct nand_device_s *device)
+{
+ mx3_nf_controller_t *mx3_nf_info = device->controller_priv;
+ target_t *target = mx3_nf_info->target;
+ switch (mx3_nf_info->fin)
+ {
+ case MX3_NF_FIN_DATAOUT:
+ /*
+ * start data output operation (set MX3_NF_BIT_OP_DONE==0)
+ */
+ target_write_u16 (target, MX3_NF_CFG2,
+ MX3_NF_BIT_DATAOUT_TYPE (mx3_nf_info->
+ optype));
+ {
+ int poll_result;
+ poll_result = poll_for_complete_op (target, "data output");
+ if (poll_result != ERROR_OK)
+ {
+ return poll_result;
+ }
+ }
+ mx3_nf_info->fin = MX3_NF_FIN_NONE;
+ /*
+ * ECC stuff
+ */
+ if ((mx3_nf_info->optype == MX3_NF_DATAOUT_PAGE)
+ && mx3_nf_info->flags.hw_ecc_enabled)
+ {
+ uint16_t ecc_status;
+ target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
+ switch (ecc_status & 0x000c)
+ {
+ case 1 << 2:
+ LOG_DEBUG
+ ("main area readed with 1 (correctable) error");
+ break;
+ case 2 << 2:
+ LOG_DEBUG
+ ("main area readed with more than 1 (incorrectable) error");
+ return ERROR_NAND_OPERATION_FAILED;
+ break;
+ }
+ switch (ecc_status & 0x0003)
+ {
+ case 1:
+ LOG_DEBUG
+ ("spare area readed with 1 (correctable) error");
+ break;
+ case 2:
+ LOG_DEBUG
+ ("main area readed with more than 1 (incorrectable) error");
+ return ERROR_NAND_OPERATION_FAILED;
+ break;
+ }
+ }
+ break;
+ case MX3_NF_FIN_NONE:
+ break;
+ }
+ return ERROR_OK;
+}
Added: trunk/src/flash/mx3_nand.h
===================================================================
--- trunk/src/flash/mx3_nand.h 2009-09-10 13:17:05 UTC (rev 2684)
+++ trunk/src/flash/mx3_nand.h 2009-09-10 13:17:25 UTC (rev 2685)
@@ -0,0 +1,90 @@
+#include <nand.h>
+
+#define MX3_NF_BASE_ADDR 0xb8000000
+#define MX3_NF_BUFSIZ (MX3_NF_BASE_ADDR + 0xe00)
+#define MX3_NF_BUFADDR (MX3_NF_BASE_ADDR + 0xe04)
+#define MX3_NF_FADDR (MX3_NF_BASE_ADDR + 0xe06)
+#define MX3_NF_FCMD (MX3_NF_BASE_ADDR + 0xe08)
+#define MX3_NF_BUFCFG (MX3_NF_BASE_ADDR + 0xe0a)
+#define MX3_NF_ECCSTATUS (MX3_NF_BASE_ADDR + 0xe0c)
+#define MX3_NF_ECCMAINPOS (MX3_NF_BASE_ADDR + 0xe0e)
+#define MX3_NF_ECCSPAREPOS (MX3_NF_BASE_ADDR + 0xe10)
+#define MX3_NF_FWP (MX3_NF_BASE_ADDR + 0xe12)
+#define MX3_NF_LOCKSTART (MX3_NF_BASE_ADDR + 0xe14)
+#define MX3_NF_LOCKEND (MX3_NF_BASE_ADDR + 0xe16)
+#define MX3_NF_FWPSTATUS (MX3_NF_BASE_ADDR + 0xe18)
+ /*
+ * all bits not marked as self-clearing bit
+ */
+#define MX3_NF_CFG1 (MX3_NF_BASE_ADDR + 0xe1a)
+#define MX3_NF_CFG2 (MX3_NF_BASE_ADDR + 0xe1c)
+
+#define MX3_NF_MAIN_BUFFER0 (MX3_NF_BASE_ADDR + 0x0000)
+#define MX3_NF_MAIN_BUFFER1 (MX3_NF_BASE_ADDR + 0x0200)
+#define MX3_NF_MAIN_BUFFER2 (MX3_NF_BASE_ADDR + 0x0400)
+#define MX3_NF_MAIN_BUFFER3 (MX3_NF_BASE_ADDR + 0x0600)
+#define MX3_NF_SPARE_BUFFER0 (MX3_NF_BASE_ADDR + 0x0800)
+#define MX3_NF_SPARE_BUFFER1 (MX3_NF_BASE_ADDR + 0x0810)
+#define MX3_NF_SPARE_BUFFER2 (MX3_NF_BASE_ADDR + 0x0820)
+#define MX3_NF_SPARE_BUFFER3 (MX3_NF_BASE_ADDR + 0x0830)
+#define MX3_NF_MAIN_BUFFER_LEN 512
+#define MX3_NF_SPARE_BUFFER_LEN 16
+#define MX3_NF_LAST_BUFFER_ADDR ((MX3_NF_SPARE_BUFFER3) + MX3_NF_SPARE_BUFFER_LEN - 2)
+
+/* bits in MX3_NF_CFG1 register */
+#define MX3_NF_BIT_SPARE_ONLY_EN (1<<2)
+#define MX3_NF_BIT_ECC_EN (1<<3)
+#define MX3_NF_BIT_INT_DIS (1<<4)
+#define MX3_NF_BIT_BE_EN (1<<5)
+#define MX3_NF_BIT_RESET_EN (1<<6)
+#define MX3_NF_BIT_FORCE_CE (1<<7)
+
+/* bits in MX3_NF_CFG2 register */
+
+/*Flash Command Input*/
+#define MX3_NF_BIT_OP_FCI (1<<0)
+ /*
+ * Flash Address Input
+ */
+#define MX3_NF_BIT_OP_FAI (1<<1)
+ /*
+ * Flash Data Input
+ */
+#define MX3_NF_BIT_OP_FDI (1<<2)
+
+/* see "enum mx_dataout_type" below */
+#define MX3_NF_BIT_DATAOUT_TYPE(x) ((x)<<3)
+#define MX3_NF_BIT_OP_DONE (1<<15)
+
+#define MX3_CCM_CGR2 0x53f80028
+#define MX3_GPR 0x43fac008
+#define MX3_PCSR 0x53f8000c
+
+enum mx_dataout_type
+{
+ MX3_NF_DATAOUT_PAGE = 1,
+ MX3_NF_DATAOUT_NANDID = 2,
+ MX3_NF_DATAOUT_NANDSTATUS = 4,
+};
+enum mx_nf_finalize_action
+{
+ MX3_NF_FIN_NONE,
+ MX3_NF_FIN_DATAOUT,
+};
+
+struct mx3_nf_flags
+{
+ unsigned host_little_endian:1;
+ unsigned target_little_endian:1;
+ unsigned nand_readonly:1;
+ unsigned one_kb_sram:1;
+ unsigned hw_ecc_enabled:1;
+};
+
+typedef struct mx3_nf_controller_s
+{
+ struct target_s *target;
+ enum mx_dataout_type optype;
+ enum mx_nf_finalize_action fin;
+ struct mx3_nf_flags flags;
+} mx3_nf_controller_t;
Modified: trunk/src/flash/nand.c
===================================================================
--- trunk/src/flash/nand.c 2009-09-10 13:17:05 UTC (rev 2684)
+++ trunk/src/flash/nand.c 2009-09-10 13:17:25 UTC (rev 2685)
@@ -52,6 +52,7 @@
extern nand_flash_controller_t s3c2412_nand_controller;
extern nand_flash_controller_t s3c2440_nand_controller;
extern nand_flash_controller_t s3c2443_nand_controller;
+extern nand_flash_controller_t imx31_nand_flash_controller;
/* extern nand_flash_controller_t boundary_scan_nand_controller; */
@@ -64,6 +65,7 @@
&s3c2412_nand_controller,
&s3c2440_nand_controller,
&s3c2443_nand_controller,
+ &imx31_nand_flash_controller,
/* &boundary_scan_nand_controller, */
NULL
};
|
|
From: oharboe at B. <oh...@ma...> - 2009-09-10 15:17:06
|
Author: oharboe
Date: 2009-09-10 15:17:05 +0200 (Thu, 10 Sep 2009)
New Revision: 2684
Modified:
trunk/src/target/target.c
Log:
Alexei Babich <a.b...@re...> fix problems with unecessary tailend byte accesses. Use 16 bit access on tailend of a memory read if possible.
Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c 2009-09-10 08:06:22 UTC (rev 2683)
+++ trunk/src/target/target.c 2009-09-10 13:17:05 UTC (rev 2684)
@@ -1239,7 +1239,19 @@
address += aligned;
size -= aligned;
}
+
+ /*prevent byte access when possible (avoid AHB access limitations in some cases)*/
+ if(size >=2)
+ {
+ int aligned = size - (size%2);
+ retval = target_read_memory(target, address, 2, aligned / 2, buffer);
+ if (retval != ERROR_OK)
+ return retval;
+ buffer += aligned;
+ address += aligned;
+ size -= aligned;
+ }
/* handle tail writes of less than 4 bytes */
if (size > 0)
{
|
|
From: oharboe at B. <oh...@ma...> - 2009-09-10 10:06:24
|
Author: oharboe
Date: 2009-09-10 10:06:22 +0200 (Thu, 10 Sep 2009)
New Revision: 2683
Added:
trunk/tcl/board/telo.cfg
trunk/tcl/target/c100config.tcl
trunk/tcl/target/c100helper.tcl
trunk/tcl/target/c100regs.tcl
Modified:
trunk/tcl/target/c100.cfg
Log:
michal smulski <mic...@oo...> telo target/board scripts
Added: trunk/tcl/board/telo.cfg
===================================================================
--- trunk/tcl/board/telo.cfg 2009-09-09 16:11:33 UTC (rev 2682)
+++ trunk/tcl/board/telo.cfg 2009-09-10 08:06:22 UTC (rev 2683)
@@ -0,0 +1,54 @@
+source [find target/c100.cfg]
+# basic register defintion for C100
+source [find target/c100regs.tcl]
+# board-config info
+source [find target/c100config.tcl]
+# C100 helper functions
+source [find target/c100helper.tcl]
+
+
+# Telo board & C100 support trst and srst
+# however openocd does not support
+# 1. setting srst reset pulse width
+# 2. setting delay between srst pulse and JTAG access
+# This really makes the srst useless for now.
+reset_config trst_and_srst separate
+
+
+
+# issue telnet: reset init
+# issue gdb: monitor reset init
+$_TARGETNAME configure -event reset-init {
+ jtag_khz 100
+ # setup GPIO used as control signals for C100
+ setupGPIO
+ # This will allow acces to lower 8MB or NOR
+ lowGPIO5
+ # setup NOR size,timing,etc.
+ setupNOR
+ # setup internals + PLL + DDR2
+ initC100
+ #turn up the JTAG speed
+ jtag_khz 3000
+ puts "JTAG speek now 3MHz"
+ puts "type helpC100 to get help on C100"
+}
+
+$_TARGETNAME configure -event reset-deassert-post {
+ # Force target into ARM state.
+# soft_reset_halt # not implemented on ARM11
+ puts "Detected SRSRT asserted on C100.CPU"
+
+}
+
+proc power_restore {} { puts "Sensed power restore. No action." }
+proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
+
+
+# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
+# it's really 16MB but the upper 8mb is controller via gpio
+# openocd does not support 'complex reads/writes' to NOR
+flash bank cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
+
+# writing data to memory does not work without this
+memwrite burst disable
\ No newline at end of file
Property changes on: trunk/tcl/board/telo.cfg
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/tcl/target/c100.cfg
===================================================================
--- trunk/tcl/target/c100.cfg 2009-09-09 16:11:33 UTC (rev 2682)
+++ trunk/tcl/target/c100.cfg 2009-09-10 08:06:22 UTC (rev 2683)
@@ -1,11 +1,10 @@
-# c100 config
-#
-#jtag_nsrst_delay 5000
-#jtag_ntrst_delay 3000
-#reset_config none
-reset_config trst_and_srst separate
-#reset_config srst_only srst_pulls_trst
+# c100 config.
+# This is ARM1136 dual core
+# this script only configures one core (that is used to run Linux)
+# assume no PLL lock, start slowly
+jtag_khz 100
+
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
@@ -36,30 +35,8 @@
# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
-set _TARGETNAME $_CHIPNAME.cpu
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
# C100's ARAM 64k SRAM
$_TARGETNAME configure -work-area-phys 0x0a000000 -work-area-size 0x10000 -work-area-backup 0
-
-
-proc power_restore {} { puts "Sensed power restore. No action." }
-proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
-
-
-# issue telnet: reset init
-# issue gdb: monitor reset init
-$_TARGETNAME configure -event reset-init {
- # Force target into ARM state.
-# soft_reset_halt # not implemented on ARM11
- puts "Halting C100.CPU"
- halt
-}
-
-$_TARGETNAME configure -event reset-deassert-post {
- # Force target into ARM state.
-# soft_reset_halt # not implemented on ARM11
- puts "Detected SRSRT asserted on C100.CPU"
-
-}
-# Valid events: old-gdb_program_config, old-pre_resume, early-halted, halted, resumed, resume-start, resume-end, gdb-start, gdb-end, reset-start, reset-assert-pre, reset-assert-post, reset-deassert-pre, reset-deassert-post, reset-halt-pre, reset-halt-post, reset-wait-pre, reset-wait-post, reset-init, reset-end, examine-start, examine-end, debug-halted, debug-resumed, gdb-attach, gdb-detach, gdb-flash-write-start, gdb-flash-write-end, gdb-flash-erase-start, gdb-flash-erase-end, resume-start, resume-ok, or resume-end
Added: trunk/tcl/target/c100config.tcl
===================================================================
--- trunk/tcl/target/c100config.tcl 2009-09-09 16:11:33 UTC (rev 2682)
+++ trunk/tcl/target/c100config.tcl 2009-09-10 08:06:22 UTC (rev 2683)
@@ -0,0 +1,324 @@
+
+# board(-config) specfic parameters file.
+
+# set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
+proc config {label} {
+ return [dict get [configC100] $label ]
+}
+
+# show the value for the param. with label
+proc showconfig {label} {
+ puts [format "0x%x" [dict get [configC100] $label ]]
+}
+
+# Telo board config
+# when there are more then one board config
+# use soft links to c100board-config.tcl
+# so that only the right board-config gets
+# included (just like include/configs/board-configs.h
+# in u-boot.
+proc configC100 {} {
+ # xtal freq. 24MHz
+ dict set configC100 CFG_REFCLKFREQ 24000000
+
+ # Amba Clk 165MHz
+ dict set configC100 CONFIG_SYS_HZ_CLOCK 165000000
+ dict set configC100 w_amba 1
+ dict set configC100 x_amba 1
+ # y = amba_clk * (w+1)*(x+1)*2/xtal_clk
+ dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
+
+ # Arm Clk 450MHz, must be a multiple of 25 MHz
+ dict set configC100 CFG_ARM_CLOCK 450000000
+ dict set configC100 w_arm 0
+ dict set configC100 x_arm 1
+ # y = arm_clk * (w+1)*(x+1)*2/xtal_clk
+ dict set configC100 y_arm [expr ([dict get $configC100 CFG_ARM_CLOCK] * ( ([dict get $configC100 w_arm]+1 ) * ([dict get $configC100 x_arm]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
+
+
+}
+
+proc setupNOR {} {
+ puts "Setting up NOR: 16MB, 16-bit wide bus, CS0"
+ # this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
+ set EX_CSEN_REG [regs EX_CSEN_REG ]
+ set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
+ set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
+ set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
+ set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
+ set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
+ set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
+ set EX_MFSM_REG [regs EX_MFSM_REG ]
+ set EX_CSFSM_REG [regs EX_CSFSM_REG ]
+ set EX_WRFSM_REG [regs EX_WRFSM_REG ]
+ set EX_RDFSM_REG [regs EX_RDFSM_REG ]
+
+ # enable Expansion Bus Clock + CS0 (NOR)
+ mww $EX_CSEN_REG 0x3
+ # set the address space for CS0=16MB
+ mww $EX_CS0_SEG_REG 0x7ff
+ # set the CS0 bus width to 16-bit
+ mww $EX_CS0_CFG_REG 0x202
+ # set timings to NOR
+ mww $EX_CS0_TMG1_REG 0x03034006
+ mww $EX_CS0_TMG2_REG 0x04040002
+ #mww $EX_CS0_TMG3_REG
+ # set EBUS clock 165/5=33MHz
+ mww $EX_CLOCK_DIV_REG 0x5
+ # everthing else is OK with default
+}
+
+proc bootNOR {} {
+ set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
+ set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
+ set DDR_RST [regs DDR_RST]
+
+ # put DDR controller in reset (so that it comes reset in u-boot)
+ mmw $BLOCK_RESET_REG 0x0 $DDR_RST
+ # setup CS0 controller for NOR
+ setupNOR
+ # make sure we are accessing the lower part of NOR
+ lowGPIO5
+ # set PC to start of NOR (at boot 0x20000000 = 0x0)
+ reg pc $EXP_CS0_BASEADDR
+ # run
+ resume
+}
+proc setupGPIO {} {
+ puts "Setting up GPIO block for Telo"
+ # This is current setup for Telo (see sch. for details):
+ #GPIO0 reset for FXS-FXO IC, leave as input, the IC has internal pullup
+ #GPIO1 irq line for FXS-FXO
+ #GPIO5 addr22 for NOR flash (access to upper 8MB)
+ #GPIO17 reset for DECT module.
+ #GPIO29 CS_n for NAND
+
+ set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
+ set GPIO_OE_REG [regs GPIO_OE_REG]
+
+ # set GPIO29=GPIO17=1, GPIO5=0
+ mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17]
+ # enable [as output] GPIO29,GPIO17,GPIO5
+ mww $GPIO_OE_REG [expr 1<<29 | 1<<17 | 1<<5]
+}
+
+proc highGPIO5 {} {
+ puts "GPIO5 high"
+ set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
+ # set GPIO5=1
+ mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0
+}
+
+proc lowGPIO5 {} {
+ puts "GPIO5 low"
+ set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
+ # set GPIO5=0
+ mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5]
+}
+
+proc boardID {id} {
+ # so far built:
+ # 4'b1111
+ dict set boardID 15 name "EVT1"
+ dict set boardID 15 ddr2size 128M
+ # dict set boardID 15 nandsize 1G
+ # dict set boardID 15 norsize 16M
+ # 4'b0000
+ dict set boardID 0 name "EVT2"
+ dict set boardID 0 ddr2size 128M
+ # 4'b0001
+ dict set boardID 1 name "EVT3"
+ dict set boardID 1 ddr2size 256M
+ # 4'b1110
+ dict set boardID 14 name "EVT3_old"
+ dict set boardID 14 ddr2size 128M
+ # 4'b0010
+ dict set boardID 2 name "EVT4"
+ dict set boardID 2 ddr2size 256M
+
+ return $boardID
+}
+
+# converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()
+# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
+proc ooma_board_detect {} {
+ set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
+
+ # read the current value of the BOOTSRAP pins
+ set tmp [mrw $GPIO_BOOTSTRAP_REG]
+ puts [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
+ # extract the GPBP bits
+ set gpbt [expr ($tmp &0x1C00) >> 10 | ($tmp & 0x40) >>3]
+
+ # display board ID
+ puts [format "This is %s (0x%x)" [dict get [boardID $gpbt] $gpbt name] $gpbt]
+ # return the ddr2 size, used to configure DDR2 on a given board.
+ return [dict get [boardID $gpbt] $gpbt ddr2size]
+}
+
+proc configureDDR2regs_256M {} {
+ puts "ConfigureDDR2regs_256M TBD"
+}
+
+# converted from u-boot/cpu/arm1136/comcerto/bsp100.c:config_board99()
+# The values are computed based on Mindspeed and Nanya datasheets
+proc configureDDR2regs_128M {} {
+
+ set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
+ set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
+ set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
+ set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
+ set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
+ set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
+ set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
+ set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
+ set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
+ set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
+ set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
+ set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
+ set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
+ set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
+ set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
+ set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
+ set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
+ set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
+ set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
+ set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
+ set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
+
+
+ set DENALI_CTL_02_VAL 0x0100010000010100
+ set DENALI_CTL_11_VAL 0x433A42124A650A37
+ # set some default values
+ mw64bit $DENALI_CTL_00_DATA 0x0100000101010101
+ mw64bit $DENALI_CTL_01_DATA 0x0100000100000101
+ mw64bit $DENALI_CTL_02_DATA $DENALI_CTL_02_VAL
+ mw64bit $DENALI_CTL_03_DATA 0x0102020202020201
+ mw64bit $DENALI_CTL_04_DATA 0x0201010100000201
+ mw64bit $DENALI_CTL_05_DATA 0x0203010300010101
+ mw64bit $DENALI_CTL_06_DATA 0x050A020200020202
+ mw64bit $DENALI_CTL_07_DATA 0x000000030E0B0205
+ mw64bit $DENALI_CTL_08_DATA 0x6427003F3F0A0209
+ mw64bit $DENALI_CTL_09_DATA 0x1A00002F00001A00
+ mw64bit $DENALI_CTL_10_DATA 0x01202020201A1A1A
+ mw64bit $DENALI_CTL_11_DATA $DENALI_CTL_11_VAL
+ mw64bit $DENALI_CTL_12_DATA 0x0000080000000800
+ mw64bit $DENALI_CTL_13_DATA 0x0010002000100040
+ mw64bit $DENALI_CTL_14_DATA 0x0010004000100040
+ mw64bit $DENALI_CTL_15_DATA 0x0508000000000000
+ mw64bit $DENALI_CTL_16_DATA 0x000020472D200000
+ mw64bit $DENALI_CTL_17_DATA 0x0000000008000000
+ mw64bit $DENALI_CTL_18_DATA 0x0302000000000000
+ mw64bit $DENALI_CTL_19_DATA 0x00001400C8030604
+ mw64bit $DENALI_CTL_20_DATA 0x00000000823600C8
+
+ set wr_dqs_shift 0x40
+ # start DDRC
+ mw64bit $DENALI_CTL_02_DATA [expr $DENALI_CTL_02_VAL | (1 << 32)]
+ # wait int_status[2] (DRAM init complete)
+ puts -nonewline "Waiting for DDR2 controller to init..."
+ set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
+ while { [expr $tmp & 0x040000] == 0 } {
+ sleep 1
+ set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
+ }
+ mw64bit $DENALI_CTL_11_DATA [expr ($DENALI_CTL_11_VAL & ~0x00007F0000000000) | ($wr_dqs_shift << 40) ]
+ puts "done."
+
+ # do ddr2 training sequence
+ # TBD (for now, if you need it, run trainDDR command)
+}
+
+
+
+proc setupUART0 {} {
+ # configure UART0 to 115200, 8N1
+ set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
+ set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
+ set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
+ set GPIO_IOCTRL_UART0 [regs GPIO_IOCTRL_UART0]
+ set UART0_LCR [regs UART0_LCR]
+ set LCR_DLAB [regs LCR_DLAB]
+ set UART0_DLL [regs UART0_DLL]
+ set UART0_DLH [regs UART0_DLH]
+ set UART0_IIR [regs UART0_IIR]
+ set UART0_IER [regs UART0_IER]
+ set LCR_ONE_STOP [regs LCR_ONE_STOP]
+ set LCR_CHAR_LEN_8 [regs LCR_CHAR_LEN_8]
+ set FCR_XMITRES [regs FCR_XMITRES]
+ set FCR_RCVRRES [regs FCR_RCVRRES]
+ set FCR_FIFOEN [regs FCR_FIFOEN]
+ set IER_UUE [regs IER_UUE]
+
+ # unlock writing to IOCTRL register
+ mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
+ # enable UART0
+ mmw $GPIO_IOCTRL_REG $GPIO_IOCTRL_UART0 0x0
+ # baudrate 115200
+ # This should really be amba_clk/(16*115200) but amba_clk=165MHz
+ set tmp 89
+ # Enable Divisor Latch access
+ mmw $UART0_LCR $LCR_DLAB 0x0
+ # set the divisor to $tmp
+ mww $UART0_DLL [expr $tmp & 0xff]
+ mww $UART0_DLH [expr $tmp >> 8]
+ # Disable Divisor Latch access
+ mmw $UART0_LCR 0x0 $LCR_DLAB
+ # set the UART to 8N1
+ mmw $UART0_LCR [expr $LCR_ONE_STOP | $LCR_CHAR_LEN_8 ] 0x0
+ # reset FIFO
+ mmw $UART0_IIR [expr $FCR_XMITRES | $FCR_RCVRRES | $FCR_FIFOEN ] 0x0
+ # enable FFUART
+ mww $UART0_IER $IER_UUE
+}
+
+proc putcUART0 {char} {
+
+ set UART0_LSR [regs UART0_LSR]
+ set UART0_THR [regs UART0_THR]
+ set LSR_TEMT [regs LSR_TEMT]
+
+ # convert the 'char' to digit
+ set tmp [ scan $char %c ]
+ # /* wait for room in the tx FIFO on FFUART */
+ while {[expr [mrw $UART0_LSR] & $LSR_TEMT] == 0} { sleep 1 }
+ mww $UART0_THR $tmp
+ if { $char == "\n" } { putcUART0 \r }
+}
+
+proc putsUART0 {str} {
+ set index 0
+ set len [string length $str]
+ while { $index < $len } {
+ putcUART0 [string index $str $index]
+ set index [expr $index + 1]
+ }
+}
+
+
+proc trainDDR2 {} {
+ set ARAM_BASEADDR [regs ARAM_BASEADDR]
+
+ # you must have run 'reset init' or u-boot
+ # load the training code to ARAM
+ load_image ./images/ddr2train.bin $ARAM_BASEADDR bin
+ # set PC to start of NOR (at boot 0x20000000 = 0x0)
+ reg pc $ARAM_BASEADDR
+ # run
+ resume
+}
+
+proc flashUBOOT {} {
+ # this will update uboot on NOR partition
+ set EXP_CS0_BASEADDR [regs EXP_CS0_BASEADDR]
+
+ # setup CS0 controller for NOR
+ setupNOR
+ # make sure we are accessing the lower part of NOR
+ lowGPIO5
+ flash probe 0
+ puts "Erasing sectors 0-3 for uboot"
+ flash erase_sector 0 0 3
+ puts "Programming u-boot, takes about 4-5 min for 256kb"
+ flash write_image ./images/u-boot.bin $EXP_CS0_BASEADDR
+}
\ No newline at end of file
Property changes on: trunk/tcl/target/c100config.tcl
___________________________________________________________________
Name: svn:eol-style
+ native
Added: trunk/tcl/target/c100helper.tcl
===================================================================
--- trunk/tcl/target/c100helper.tcl 2009-09-09 16:11:33 UTC (rev 2682)
+++ trunk/tcl/target/c100helper.tcl 2009-09-10 08:06:22 UTC (rev 2683)
@@ -0,0 +1,518 @@
+
+proc helpC100 {} {
+ puts "List of useful functions for C100 processor:"
+ puts "1) reset init: will set up your Telo board"
+ puts "2) setupNOR: will setup NOR access"
+ puts "3) showNOR: will show current NOR config registers for 16-bit, 16MB NOR"
+ puts "4) setupGPIO: will setup GPIOs for Telo board"
+ puts "5) showGPIO: will show current GPIO config registers"
+ puts "6) highGPIO5: will set GPIO5=NOR_addr22=1 to access upper 8MB"
+ puts "7) lowGPIO5: will set GPIO5=NOR_addr22=0 to access lower 8MB"
+ puts "8) showAmbaClk: will show current config registers for Amba Bus Clock"
+ puts "9) setupAmbaClk: will setup Amba Bus Clock=165MHz"
+ puts "10) showArmClk: will show current config registers for Arm Bus Clock"
+ puts "11) setupArmClk: will setup Amba Bus Clock=450MHz"
+ puts "12) ooma_board_detect: will show which version of Telo you have"
+ puts "13) setupDDR2: will configure DDR2 controller, you must have PLLs configureg"
+ puts "14) showDDR2: will show DDR2 config registers"
+ puts "15) showWatchdog: will show current regster config for watchdog"
+ puts "16) reboot: will trigger watchdog and reboot Telo (hw reset)"
+ puts "17) bootNOR: will boot Telo from NOR"
+ puts "18) setupUART0: will configure UART0 for 115200 8N1, PLLs have to be confiured"
+ puts "19) putcUART0: will print a character on UART0"
+ puts "20) putsUART0: will print a string on UART0"
+ puts "21) trainDDR2: will run DDR2 training program"
+ puts "22) flashUBOOT: will prgram NOR sectors 0-3 with u-boot.bin"
+}
+
+# mrw,mmw from davinci.cfg
+# mrw: "memory read word", returns value of $reg
+proc mrw {reg} {
+ set value ""
+ ocd_mem2array value 32 $reg 1
+ return $value(0)
+}
+
+# read a 64-bit register (memory mapped)
+proc mr64bit {reg} {
+ set value ""
+ ocd_mem2array value 32 $reg 2
+ return $value
+}
+
+
+# write a 64-bit register (memory mapped)
+proc mw64bit {reg value} {
+ set high [expr $value >> 32]
+ set low [expr $value & 0xffffffff]
+ #puts [format "mw64bit(0x%x): 0x%08x%08x" $reg $high $low]
+ mww $reg $low
+ mww [expr $reg+4] $high
+}
+
+# mmw: "memory modify word", updates value of $reg
+# $reg <== ((value & ~$clearbits) | $setbits)
+proc mmw {reg setbits clearbits} {
+ set old [mrw $reg]
+ set new [expr ($old & ~$clearbits) | $setbits]
+ mww $reg $new
+}
+
+
+proc showNOR {} {
+ puts "This is the current NOR setup"
+ set EX_CSEN_REG [regs EX_CSEN_REG ]
+ set EX_CS0_SEG_REG [regs EX_CS0_SEG_REG ]
+ set EX_CS0_CFG_REG [regs EX_CS0_CFG_REG ]
+ set EX_CS0_TMG1_REG [regs EX_CS0_TMG1_REG ]
+ set EX_CS0_TMG2_REG [regs EX_CS0_TMG2_REG ]
+ set EX_CS0_TMG3_REG [regs EX_CS0_TMG3_REG ]
+ set EX_CLOCK_DIV_REG [regs EX_CLOCK_DIV_REG ]
+ set EX_MFSM_REG [regs EX_MFSM_REG ]
+ set EX_CSFSM_REG [regs EX_CSFSM_REG ]
+ set EX_WRFSM_REG [regs EX_WRFSM_REG ]
+ set EX_RDFSM_REG [regs EX_RDFSM_REG ]
+
+ puts [format "EX_CSEN_REG (0x%x): 0x%x" $EX_CSEN_REG [mrw $EX_CSEN_REG]]
+ puts [format "EX_CS0_SEG_REG (0x%x): 0x%x" $EX_CS0_SEG_REG [mrw $EX_CS0_SEG_REG]]
+ puts [format "EX_CS0_CFG_REG (0x%x): 0x%x" $EX_CS0_CFG_REG [mrw $EX_CS0_CFG_REG]]
+ puts [format "EX_CS0_TMG1_REG (0x%x): 0x%x" $EX_CS0_TMG1_REG [mrw $EX_CS0_TMG1_REG]]
+ puts [format "EX_CS0_TMG2_REG (0x%x): 0x%x" $EX_CS0_TMG2_REG [mrw $EX_CS0_TMG2_REG]]
+ puts [format "EX_CS0_TMG3_REG (0x%x): 0x%x" $EX_CS0_TMG3_REG [mrw $EX_CS0_TMG3_REG]]
+ puts [format "EX_CLOCK_DIV_REG (0x%x): 0x%x" $EX_CLOCK_DIV_REG [mrw $EX_CLOCK_DIV_REG]]
+ puts [format "EX_MFSM_REG (0x%x): 0x%x" $EX_MFSM_REG [mrw $EX_MFSM_REG]]
+ puts [format "EX_CSFSM_REG (0x%x): 0x%x" $EX_CSFSM_REG [mrw $EX_CSFSM_REG]]
+ puts [format "EX_WRFSM_REG (0x%x): 0x%x" $EX_WRFSM_REG [mrw $EX_WRFSM_REG]]
+ puts [format "EX_RDFSM_REG (0x%x): 0x%x" $EX_RDFSM_REG [mrw $EX_RDFSM_REG]]
+}
+
+
+
+proc showGPIO {} {
+ puts "This is the current GPIO register setup"
+ # GPIO outputs register
+ set GPIO_OUTPUT_REG [regs GPIO_OUTPUT_REG]
+ # GPIO Output Enable register
+ set GPIO_OE_REG [regs GPIO_OE_REG]
+ set GPIO_HI_INT_ENABLE_REG [regs GPIO_HI_INT_ENABLE_REG]
+ set GPIO_LO_INT_ENABLE_REG [regs GPIO_LO_INT_ENABLE_REG]
+ # GPIO input register
+ set GPIO_INPUT_REG [regs GPIO_INPUT_REG]
+ set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
+ set MUX_CONF_REG [regs MUX_CONF_REG]
+ set SYSCONF_REG [regs SYSCONF_REG]
+ set GPIO_ARM_ID_REG [regs GPIO_ARM_ID_REG]
+ set GPIO_BOOTSTRAP_REG [regs GPIO_BOOTSTRAP_REG]
+ set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
+ set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
+ set GPIO_DEVID_REG [regs GPIO_DEVID_REG]
+
+ puts [format "GPIO_OUTPUT_REG (0x%x): 0x%x" $GPIO_OUTPUT_REG [mrw $GPIO_OUTPUT_REG]]
+ puts [format "GPIO_OE_REG (0x%x): 0x%x" $GPIO_OE_REG [mrw $GPIO_OE_REG]]
+ puts [format "GPIO_HI_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_HI_INT_ENABLE_REG [mrw $GPIO_HI_INT_ENABLE_REG]]
+ puts [format "GPIO_LO_INT_ENABLE_REG(0x%x): 0x%x" $GPIO_LO_INT_ENABLE_REG [mrw $GPIO_LO_INT_ENABLE_REG]]
+ puts [format "GPIO_INPUT_REG (0x%x): 0x%x" $GPIO_INPUT_REG [mrw $GPIO_INPUT_REG]]
+ puts [format "APB_ACCESS_WS_REG (0x%x): 0x%x" $APB_ACCESS_WS_REG [mrw $APB_ACCESS_WS_REG]]
+ puts [format "MUX_CONF_REG (0x%x): 0x%x" $MUX_CONF_REG [mrw $MUX_CONF_REG]]
+ puts [format "SYSCONF_REG (0x%x): 0x%x" $SYSCONF_REG [mrw $SYSCONF_REG]]
+ puts [format "GPIO_ARM_ID_REG (0x%x): 0x%x" $GPIO_ARM_ID_REG [mrw $GPIO_ARM_ID_REG]]
+ puts [format "GPIO_BOOTSTRAP_REG (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG [mrw $GPIO_BOOTSTRAP_REG]]
+ puts [format "GPIO_LOCK_REG (0x%x): 0x%x" $GPIO_LOCK_REG [mrw $GPIO_LOCK_REG]]
+ puts [format "GPIO_IOCTRL_REG (0x%x): 0x%x" $GPIO_IOCTRL_REG [mrw $GPIO_IOCTRL_REG]]
+ puts [format "GPIO_DEVID_REG (0x%x): 0x%x" $GPIO_DEVID_REG [mrw $GPIO_DEVID_REG]]
+}
+
+
+
+# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_amba_clk())
+proc showAmbaClk {} {
+ set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
+ set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
+ set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
+
+ puts [format "CLKCORE_AHB_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_AHB_CLK_CNTRL [mrw $CLKCORE_AHB_CLK_CNTRL]]
+ ocd_mem2array value 32 $CLKCORE_AHB_CLK_CNTRL 1
+ # see if the PLL is in bypass mode
+ set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
+ puts [format "PLL bypass bit: %d" $bypass]
+ if {$bypass == 1} {
+ puts [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]
+ } else {
+ # nope, extract x,y,w and compute the PLL output freq.
+ set x [expr ($value(0) & 0x0001F0000) >> 16]
+ puts [format "x: %d" $x]
+ set y [expr ($value(0) & 0x00000007F)]
+ puts [format "y: %d" $y]
+ set w [expr ($value(0) & 0x000000300) >> 8]
+ puts [format "w: %d" $w]
+ puts [format "Amba PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]
+ }
+}
+
+
+# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_amba_clk())
+# this clock is useb by all peripherals (DDR2, ethernet, ebus, etc)
+proc setupAmbaClk {} {
+ set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
+ set CLKCORE_AHB_CLK_CNTRL [regs CLKCORE_AHB_CLK_CNTRL]
+ set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
+ set ARM_AHB_BYP [regs ARM_AHB_BYP]
+ set PLL_DISABLE [regs PLL_DISABLE]
+ set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
+ set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
+ set DIV_BYPASS [regs DIV_BYPASS]
+ set AHBCLK_PLL_LOCK [regs AHBCLK_PLL_LOCK]
+ set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
+ set CONFIG_SYS_HZ_CLOCK [config CONFIG_SYS_HZ_CLOCK]
+ set w [config w_amba]
+ set x [config x_amba]
+ set y [config y_amba]
+
+ puts [format "Setting Amba PLL to lock to %d MHz" [expr $CONFIG_SYS_HZ_CLOCK/1000000]]
+ #puts [format "setupAmbaClk: w= %d" $w]
+ #puts [format "setupAmbaClk: x= %d" $x]
+ #puts [format "setupAmbaClk: y= %d" $y]
+ # set PLL into BYPASS mode using MUX
+ mmw $CLKCORE_AHB_CLK_CNTRL $PLL_CLK_BYPASS 0x0
+ # do an internal PLL bypass
+ mmw $CLKCORE_AHB_CLK_CNTRL $AHB_PLL_BY_CTRL 0x0
+ # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
+ # openocd smallest resolution is 1ms so, wait 1ms
+ sleep 1
+ # disable the PLL
+ mmw $CLKCORE_AHB_CLK_CNTRL $PLL_DISABLE 0x0
+ # wait 1ms
+ sleep 1
+ # enable the PLL
+ mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_DISABLE
+ sleep 1
+ # set X, W and X
+ mmw $CLKCORE_AHB_CLK_CNTRL 0x0 0xFFFFFF
+ mmw $CLKCORE_AHB_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
+ # wait for PLL to lock
+ puts "Wating for Amba PLL to lock"
+ while {[expr [mrw $CLKCORE_PLL_STATUS] & $AHBCLK_PLL_LOCK] == 0} { sleep 1 }
+ # remove the internal PLL bypass
+ mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $AHB_PLL_BY_CTRL
+ # remove PLL from BYPASS mode using MUX
+ mmw $CLKCORE_AHB_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
+}
+
+
+# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_get_arm_clk())
+proc showArmClk {} {
+ set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
+ set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
+ set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
+
+ puts [format "CLKCORE_ARM_CLK_CNTRL (0x%x): 0x%x" $CLKCORE_ARM_CLK_CNTRL [mrw $CLKCORE_ARM_CLK_CNTRL]]
+ ocd_mem2array value 32 $CLKCORE_ARM_CLK_CNTRL 1
+ # see if the PLL is in bypass mode
+ set bypass [expr ($value(0) & $PLL_CLK_BYPASS) >> 24 ]
+ puts [format "PLL bypass bit: %d" $bypass]
+ if {$bypass == 1} {
+ puts [format "Amba Clk is set to REFCLK: %d (MHz)" [expr $CFG_REFCLKFREQ/1000000]]
+ } else {
+ # nope, extract x,y,w and compute the PLL output freq.
+ set x [expr ($value(0) & 0x0001F0000) >> 16]
+ puts [format "x: %d" $x]
+ set y [expr ($value(0) & 0x00000007F)]
+ puts [format "y: %d" $y]
+ set w [expr ($value(0) & 0x000000300) >> 8]
+ puts [format "w: %d" $w]
+ puts [format "Arm PLL Clk: %d (MHz)" [expr ($CFG_REFCLKFREQ * $y / (($w + 1) * ($x + 1) * 2))/1000000]]
+ }
+}
+
+# converted from u-boot/cpu/arm1136/comcerto/bsp100.c (HAL_set_arm_clk())
+# Arm Clock is used by two ARM1136 cores
+proc setupArmClk {} {
+ set CLKCORE_PLL_STATUS [regs CLKCORE_PLL_STATUS]
+ set CLKCORE_ARM_CLK_CNTRL [regs CLKCORE_ARM_CLK_CNTRL]
+ set ARM_PLL_BY_CTRL [regs ARM_PLL_BY_CTRL]
+ set ARM_AHB_BYP [regs ARM_AHB_BYP]
+ set PLL_DISABLE [regs PLL_DISABLE]
+ set PLL_CLK_BYPASS [regs PLL_CLK_BYPASS]
+ set AHB_PLL_BY_CTRL [regs AHB_PLL_BY_CTRL]
+ set DIV_BYPASS [regs DIV_BYPASS]
+ set FCLK_PLL_LOCK [regs FCLK_PLL_LOCK]
+ set CFG_REFCLKFREQ [config CFG_REFCLKFREQ]
+ set CFG_ARM_CLOCK [config CFG_ARM_CLOCK]
+ set w [config w_arm]
+ set x [config x_arm]
+ set y [config y_arm]
+
+ puts [format "Setting Arm PLL to lock to %d MHz" [expr $CFG_ARM_CLOCK/1000000]]
+ #puts [format "setupArmClk: w= %d" $w]
+ #puts [format "setupArmaClk: x= %d" $x]
+ #puts [format "setupArmaClk: y= %d" $y]
+ # set PLL into BYPASS mode using MUX
+ mmw $CLKCORE_ARM_CLK_CNTRL $PLL_CLK_BYPASS 0x0
+ # do an internal PLL bypass
+ mmw $CLKCORE_ARM_CLK_CNTRL $ARM_PLL_BY_CTRL 0x0
+ # wait 500us (ARM running @24Mhz -> 12000 cycles => 500us)
+ # openocd smallest resolution is 1ms so, wait 1ms
+ sleep 1
+ # disable the PLL
+ mmw $CLKCORE_ARM_CLK_CNTRL $PLL_DISABLE 0x0
+ # wait 1ms
+ sleep 1
+ # enable the PLL
+ mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_DISABLE
+ sleep 1
+ # set X, W and X
+ mmw $CLKCORE_ARM_CLK_CNTRL 0x0 0xFFFFFF
+ mmw $CLKCORE_ARM_CLK_CNTRL [expr (($x << 16) + ($w << 8) + $y)] 0x0
+ # wait for PLL to lock
+ puts "Wating for Amba PLL to lock"
+ while {[expr [mrw $CLKCORE_PLL_STATUS] & $FCLK_PLL_LOCK] == 0} { sleep 1 }
+ # remove the internal PLL bypass
+ mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $ARM_PLL_BY_CTRL
+ # remove PLL from BYPASS mode using MUX
+ mmw $CLKCORE_ARM_CLK_CNTRL 0x0 $PLL_CLK_BYPASS
+}
+
+
+
+proc setupPLL {} {
+ puts "PLLs setup"
+ setupAmbaClk
+ setupArmClk
+}
+
+# converted from u-boot/cpu/arm1136/bsp100.c:SoC_mem_init()
+proc setupDDR2 {} {
+ puts "Configuring DDR2"
+
+ set MEMORY_BASE_ADDR [regs MEMORY_BASE_ADDR]
+ set MEMORY_MAX_ADDR [regs MEMORY_MAX_ADDR]
+ set MEMORY_CR [regs MEMORY_CR]
+ set BLOCK_RESET_REG [regs BLOCK_RESET_REG]
+ set DDR_RST [regs DDR_RST]
+
+ # put DDR controller in reset (so that it is reset and correctly configured)
+ # this is only necessary if DDR was previously confiured
+ # and not reset.
+ mmw $BLOCK_RESET_REG 0x0 $DDR_RST
+
+ set M [expr 1024 * 1024]
+ set DDR_SZ_1024M [expr 1024 * $M]
+ set DDR_SZ_256M [expr 256 * $M]
+ set DDR_SZ_128M [expr 128 * $M]
+ set DDR_SZ_64M [expr 64 * $M]
+ # ooma_board_detect returns DDR2 memory size
+ set tmp [ooma_board_detect]
+ if {$tmp == "128M"} {
+ puts "DDR2 size 128MB"
+ set ddr_size $DDR_SZ_128M
+ } elseif {$tmp == "256M"} {
+ puts "DDR2 size 256MB"
+ set ddr_size $DDR_SZ_256M
+ } else {
+ puts "Don't know how to handle this DDR2 size?"
+ }
+
+ # Memory setup register
+ mww $MEMORY_MAX_ADDR [expr ($ddr_size - 1) + $MEMORY_BASE_ADDR]
+ # disbale ROM remap
+ mww $MEMORY_CR 0x0
+ # Take DDR controller out of reset
+ mmw $BLOCK_RESET_REG $DDR_RST 0x0
+ # min. 20 ops delay
+ sleep 1
+
+ # This will setup Denali DDR2 controller
+ if {$tmp == "128M"} {
+ configureDDR2regs_128M
+ } elseif {$tmp == "256M"} {
+ configureDDR2regs_256B
+ } else {
+ puts "Don't know how to configure DDR2 setup?"
+}
+
+
+
+proc showDDR2 {} {
+
+ set DENALI_CTL_00_DATA [regs DENALI_CTL_00_DATA]
+ set DENALI_CTL_01_DATA [regs DENALI_CTL_01_DATA]
+ set DENALI_CTL_02_DATA [regs DENALI_CTL_02_DATA]
+ set DENALI_CTL_03_DATA [regs DENALI_CTL_03_DATA]
+ set DENALI_CTL_04_DATA [regs DENALI_CTL_04_DATA]
+ set DENALI_CTL_05_DATA [regs DENALI_CTL_05_DATA]
+ set DENALI_CTL_06_DATA [regs DENALI_CTL_06_DATA]
+ set DENALI_CTL_07_DATA [regs DENALI_CTL_07_DATA]
+ set DENALI_CTL_08_DATA [regs DENALI_CTL_08_DATA]
+ set DENALI_CTL_09_DATA [regs DENALI_CTL_09_DATA]
+ set DENALI_CTL_10_DATA [regs DENALI_CTL_10_DATA]
+ set DENALI_CTL_11_DATA [regs DENALI_CTL_11_DATA]
+ set DENALI_CTL_12_DATA [regs DENALI_CTL_12_DATA]
+ set DENALI_CTL_13_DATA [regs DENALI_CTL_13_DATA]
+ set DENALI_CTL_14_DATA [regs DENALI_CTL_14_DATA]
+ set DENALI_CTL_15_DATA [regs DENALI_CTL_15_DATA]
+ set DENALI_CTL_16_DATA [regs DENALI_CTL_16_DATA]
+ set DENALI_CTL_17_DATA [regs DENALI_CTL_17_DATA]
+ set DENALI_CTL_18_DATA [regs DENALI_CTL_18_DATA]
+ set DENALI_CTL_19_DATA [regs DENALI_CTL_19_DATA]
+ set DENALI_CTL_20_DATA [regs DENALI_CTL_20_DATA]
+
+ set tmp [mr64bit $DENALI_CTL_00_DATA]
+ puts [format "DENALI_CTL_00_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_00_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_01_DATA]
+ puts [format "DENALI_CTL_01_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_01_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_02_DATA]
+ puts [format "DENALI_CTL_02_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_02_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_03_DATA]
+ puts [format "DENALI_CTL_03_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_03_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_04_DATA]
+ puts [format "DENALI_CTL_04_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_04_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_05_DATA]
+ puts [format "DENALI_CTL_05_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_05_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_06_DATA]
+ puts [format "DENALI_CTL_06_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_06_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_07_DATA]
+ puts [format "DENALI_CTL_07_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_07_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_08_DATA]
+ puts [format "DENALI_CTL_08_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_08_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_09_DATA]
+ puts [format "DENALI_CTL_09_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_09_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_10_DATA]
+ puts [format "DENALI_CTL_10_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_10_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_11_DATA]
+ puts [format "DENALI_CTL_11_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_11_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_12_DATA]
+ puts [format "DENALI_CTL_12_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_12_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_13_DATA]
+ puts [format "DENALI_CTL_13_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_13_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_14_DATA]
+ puts [format "DENALI_CTL_14_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_14_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_15_DATA]
+ puts [format "DENALI_CTL_15_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_15_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_16_DATA]
+ puts [format "DENALI_CTL_16_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_16_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_17_DATA]
+ puts [format "DENALI_CTL_17_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_17_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_18_DATA]
+ puts [format "DENALI_CTL_18_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_18_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_19_DATA]
+ puts [format "DENALI_CTL_19_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_19_DATA $tmp(1) $tmp(0)]
+ set tmp [mr64bit $DENALI_CTL_20_DATA]
+ puts [format "DENALI_CTL_20_DATA (0x%x): 0x%08x%08x" $DENALI_CTL_20_DATA $tmp(1) $tmp(0)]
+
+}
+
+proc initC100 {} {
+ # this follows u-boot/cpu/arm1136/start.S
+ set GPIO_LOCK_REG [regs GPIO_LOCK_REG]
+ set GPIO_IOCTRL_REG [regs GPIO_IOCTRL_REG]
+ set GPIO_IOCTRL_VAL [regs GPIO_IOCTRL_VAL]
+ set APB_ACCESS_WS_REG [regs APB_ACCESS_WS_REG]
+ set ASA_ARAM_BASEADDR [regs ASA_ARAM_BASEADDR]
+ set ASA_ARAM_TC_CR_REG [regs ASA_ARAM_TC_CR_REG]
+ set ASA_EBUS_BASEADDR [regs ASA_EBUS_BASEADDR]
+ set ASA_EBUS_TC_CR_REG [regs ASA_EBUS_TC_CR_REG]
+ set ASA_TC_REQIDMAEN [regs ASA_TC_REQIDMAEN]
+ set ASA_TC_REQTDMEN [regs ASA_TC_REQTDMEN]
+ set ASA_TC_REQIPSECUSBEN [regs ASA_TC_REQIPSECUSBEN]
+ set ASA_TC_REQARM0EN [regs ASA_TC_REQARM0EN]
+ set ASA_TC_REQARM1EN [regs ASA_TC_REQARM1EN]
+ set ASA_TC_REQMDMAEN [regs ASA_TC_REQMDMAEN]
+ set INTC_ARM1_CONTROL_REG [regs INTC_ARM1_CONTROL_REG]
+
+
+ # unlock writing to IOCTRL register
+ mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
+ # enable address lines A15-A21
+ mmw $GPIO_IOCTRL_REG 0xf 0x0
+ # set ARM into supervisor mode (SVC32)
+ # disable IRQ, FIQ
+ # Do I need this in JTAG mode?
+ # it really should be done as 'and ~0x1f | 0xd3 but
+ # openocd does not support this yet
+ reg cpsr 0xd3
+ # /*
+ # * flush v4 I/D caches
+ # */
+ # mov r0, #0
+ # mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
+ arm11 mcr c100.cpu 15 0 7 7 0 0x0
+ # mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
+ arm11 mcr c100.cpu 15 0 8 7 0 0x0
+
+ # /*
+ # * disable MMU stuff and caches
+ # */
+ # mrc p15, 0, r0, c1, c0, 0
+ arm11 mrc c100.cpu 15 0 1 0 0
+ # bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
+ # bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
+ # orr r0, r0, #0x00000002 @ set bit 2 (A) Align
+ # orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
+ # orr r0, r0, #0x00400000 @ set bit 22 (U)
+ # mcr p15, 0, r0, c1, c0, 0
+ arm11 mcr c100.cpu 15 0 1 0 0 0x401002
+ # This is from bsp_init() in u-boot/boards/mindspeed/ooma-darwin/board.c
+ # APB init
+ # // Setting APB Bus Wait states to 1, set post write
+ # (*(volatile u32*)(APB_ACCESS_WS_REG)) = 0x40;
+ mww [expr $APB_ACCESS_WS_REG] 0x40
+ # AHB init
+ # // enable all 6 masters for ARAM
+ mmw $ASA_ARAM_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0
+ # // enable all 6 masters for EBUS
+ mmw $ASA_EBUS_TC_CR_REG [expr $ASA_TC_REQIDMAEN | $ASA_TC_REQTDMEN | $ASA_TC_REQIPSECUSBEN | $ASA_TC_REQARM0EN | $ASA_TC_REQARM1EN | $ASA_TC_REQMDMAEN] 0x0
+
+ # ARAM init
+ # // disable pipeline mode in ARAM
+ # I don't think this is documented anywhere?
+ mww $INTC_ARM1_CONTROL_REG 0x1
+ # configure clocks
+ setupPLL
+ # enable cache
+ # ? (u-boot does nothing here)
+ # DDR2 memory init
+ setupDDR2
+ setupUART0
+ putsUART0 "C100 initialization complete.\n"
+ puts "C100 initialization complete."
+}
+
+# show current state of watchdog timer
+proc showWatchdog {} {
+ set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
+ set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
+ set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
+
+ puts [format "TIMER_WDT_HIGH_BOUND (0x%x): 0x%x" $TIMER_WDT_HIGH_BOUND [mrw $TIMER_WDT_HIGH_BOUND]]
+ puts [format "TIMER_WDT_CONTROL (0x%x): 0x%x" $TIMER_WDT_CONTROL [mrw $TIMER_WDT_CONTROL]]
+ puts [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
+}
+
+# converted from u-boot/cpu/arm1136/comcerto/intrrupts.c:void reset_cpu (ulong ignored)
+# this will trigger watchdog reset
+# the sw. reset does not work on C100
+# watchdog reset effectively works as hw. reset
+proc reboot {} {
+ set TIMER_WDT_HIGH_BOUND [regs TIMER_WDT_HIGH_BOUND]
+ set TIMER_WDT_CONTROL [regs TIMER_WDT_CONTROL]
+ set TIMER_WDT_CURRENT_COUNT [regs TIMER_WDT_CURRENT_COUNT]
+
+ # allow the counter to count to high value before triggering
+ # this is because regsiter writes are slow over JTAG and
+ # I don't want to miss the high_bound==curr_count condition
+ mww $TIMER_WDT_HIGH_BOUND 0xffffff
+ mww $TIMER_WDT_CURRENT_COUNT 0x0
+ puts "JTAG speed lowered to 100kHz"
+ jtag_khz 100
+ mww $TIMER_WDT_CONTROL 0x1
+ # wait until the reset
+ puts -nonewline "Wating for watchdog to trigger..."
+ #while {[mrw $TIMER_WDT_CONTROL] == 1} {
+ # puts [format "TIMER_WDT_CURRENT_COUNT (0x%x): 0x%x" $TIMER_WDT_CURRENT_COUNT [mrw $TIMER_WDT_CURRENT_COUNT]]
+ # sleep 1
+ #
+ #}
+ while {[c100.cpu curstate] != "running"} { sleep 1}
+ puts "done."
+ puts [format "Note that C100 is in %s state, type halt to stop" [c100.cpu curstate]]
+}
Property changes on: trunk/tcl/target/c100helper.tcl
___________________________________________________________________
Name: svn:eol-style
+ native
Added: trunk/tcl/target/c100regs.tcl
===================================================================
--- trunk/tcl/target/c100regs.tcl 2009-09-09 16:11:33 UTC (rev 2682)
+++ trunk/tcl/target/c100regs.tcl 2009-09-10 08:06:22 UTC (rev 2683)
@@ -0,0 +1,493 @@
+# Note that I basically converted
+# u-boot/include/asm-arm/arch/comcerto_100.h
+# defines
+
+# this is a work-around for 'global' not working under Linux
+# access registers by calling this routine.
+# For example:
+# set EX_CS_TMG1_REG [regs EX_CS0_TMG1_REG]
+proc regs {reg} {
+ return [dict get [regsC100] $reg ]
+}
+
+proc showreg {reg} {
+ puts [format "0x%x" [dict get [regsC100] $reg ]]
+}
+
+proc regsC100 {} {
+#/* memcore */
+#/* device memory base addresses */
+#// device memory sizes
+#/* ARAM SIZE=64K */
+dict set regsC100 ARAM_SIZE 0x00010000
+dict set regsC100 ARAM_BASEADDR 0x0A000000
+
+#/* Hardware Interface Units */
+dict set regsC100 APB_BASEADDR 0x10000000
+#/* APB_SIZE=16M address range */
+dict set regsC100 APB_SIZE 0x01000000
+
+dict set regsC100 EXP_CS0_BASEADDR 0x20000000
+dict set regsC100 EXP_CS1_BASEADDR 0x24000000
+dict set regsC100 EXP_CS2_BASEADDR 0x28000000
+dict set regsC100 EXP_CS3_BASEADDR 0x2C000000
+dict set regsC100 EXP_CS4_BASEADDR 0x30000000
+
+dict set regsC100 DDR_BASEADDR 0x80000000
+
+dict set regsC100 TDM_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x000000]
+dict set regsC100 PHI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x010000]
+dict set regsC100 TDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x020000]
+dict set regsC100 ASA_DDR_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x040000]
+dict set regsC100 ASA_ARAM_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x048000]
+dict set regsC100 TIMER_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x050000]
+dict set regsC100 ASD_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x060000]
+dict set regsC100 GPIO_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x070000]
+dict set regsC100 UART0_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x090000]
+dict set regsC100 UART1_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x094000]
+dict set regsC100 SPI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x098000]
+dict set regsC100 I2C_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x09C000]
+dict set regsC100 INTC_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0A0000]
+dict set regsC100 CLKCORE_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000]
+dict set regsC100 PUI_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0B0000]
+dict set regsC100 GEMAC_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0D0000]
+dict set regsC100 IDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0E0000]
+dict set regsC100 MEMCORE_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x0F0000]
+dict set regsC100 ASA_EBUS_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x100000]
+dict set regsC100 ASA_AAB_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x108000]
+dict set regsC100 GEMAC1_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x190000]
+dict set regsC100 EBUS_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x1A0000]
+dict set regsC100 MDMA_BASEADDR [expr [dict get $regsC100 APB_BASEADDR ] + 0x1E0000]
+
+
+#////////////////////////////////////////////////////////////
+#// AHB block //
+#////////////////////////////////////////////////////////////
+dict set regsC100 ASA_ARAM_PRI_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x00]
+dict set regsC100 ASA_ARAM_TC_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x04]
+dict set regsC100 ASA_ARAM_TC_CR_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x08]
+dict set regsC100 ASA_ARAM_STAT_REG [expr [dict get $regsC100 ASA_ARAM_BASEADDR ] + 0x0C]
+
+dict set regsC100 ASA_EBUS_PRI_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x00]
+dict set regsC100 ASA_EBUS_TC_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x04]
+dict set regsC100 ASA_EBUS_TC_CR_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x08]
+dict set regsC100 ASA_EBUS_STAT_REG [expr [dict get $regsC100 ASA_EBUS_BASEADDR ] + 0x0C]
+
+dict set regsC100 IDMA_MASTER 0
+dict set regsC100 TDMA_MASTER 1
+dict set regsC100 USBIPSEC_MASTER 2
+dict set regsC100 ARM0_MASTER 3
+dict set regsC100 ARM1_MASTER 4
+dict set regsC100 MDMA_MASTER 5
+
+#define IDMA_PRIORITY(level) (level)
+#define TDM_PRIORITY(level) (level << 4)
+#define USBIPSEC_PRIORITY(level) (level << 8)
+#define ARM0_PRIORITY(level) (level << 12)
+#define ARM1_PRIORITY(level) (level << 16)
+#define MDMA_PRIORITY(level) (level << 20)
+
+dict set regsC100 ASA_TC_REQIDMAEN [expr 1<<18]
+dict set regsC100 ASA_TC_REQTDMEN [expr 1<<19]
+dict set regsC100 ASA_TC_REQIPSECUSBEN [expr 1<<20]
+dict set regsC100 ASA_TC_REQARM0EN [expr 1<<21]
+dict set regsC100 ASA_TC_REQARM1EN [expr 1<<22]
+dict set regsC100 ASA_TC_REQMDMAEN [expr 1<<23]
+
+dict set regsC100 MEMORY_BASE_ADDR 0x80000000
+dict set regsC100 MEMORY_MAX_ADDR [expr [dict get $regsC100 ASD_BASEADDR ] + 0x10]
+dict set regsC100 MEMORY_CR [expr [dict get $regsC100 ASD_BASEADDR ] + 0x14]
+dict set regsC100 ROM_REMAP_EN 0x1
+
+#define HAL_asb_priority(level) \
+#*(volatile unsigned *)ASA_PRI_REG = level
+
+#define HAL_aram_priority(level) \
+#*(volatile unsigned *)ASA_ARAM_PRI_REG = level
+
+#define HAL_aram_arbitration(arbitration_mask) \
+#*(volatile unsigned *)ASA_ARAM_TC_CR_REG |= arbitration_mask
+
+#define HAL_aram_defmaster(mask) \
+#*(volatile unsigned *)ASA_ARAM_TC_CR_REG = (*(volatile unsigned *)ASA_TC_CR_REG & 0xFFFF) | (mask << 24)
+
+#////////////////////////////////////////////////////////////
+#// INTC block //
+#////////////////////////////////////////////////////////////
+
+dict set regsC100 INTC_ARM1_CONTROL_REG [expr [dict get $regsC100 INTC_BASEADDR ] + 0x18]
+
+#////////////////////////////////////////////////////////////
+#// TIMER block //
+#////////////////////////////////////////////////////////////
+
+dict set regsC100 TIMER0_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x00]
+dict set regsC100 TIMER0_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x04]
+dict set regsC100 TIMER1_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x08]
+dict set regsC100 TIMER1_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x0C]
+
+dict set regsC100 TIMER2_CNTR_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x18]
+dict set regsC100 TIMER2_LBOUND_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x10]
+dict set regsC100 TIMER2_HBOUND_REG [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x14]
+dict set regsC100 TIMER2_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x1C]
+
+dict set regsC100 TIMER3_LOBND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x20]
+dict set regsC100 TIMER3_HIBND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x24]
+dict set regsC100 TIMER3_CTRL [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x28]
+dict set regsC100 TIMER3_CURR_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x2C]
+
+dict set regsC100 TIMER_MASK [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x40]
+dict set regsC100 TIMER_STATUS [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50]
+dict set regsC100 TIMER_ACK [expr [dict get $regsC100 TIMER_BASEADDR ] + 0x50]
+dict set regsC100 TIMER_WDT_HIGH_BOUND [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD0]
+dict set regsC100 TIMER_WDT_CONTROL [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD4]
+dict set regsC100 TIMER_WDT_CURRENT_COUNT [expr [dict get $regsC100 TIMER_BASEADDR ] + 0xD8]
+
+
+
+#////////////////////////////////////////////////////////////
+#// EBUS block
+#////////////////////////////////////////////////////////////
+
+dict set regsC100 EX_SWRST_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x00]
+dict set regsC100 EX_CSEN_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x04]
+dict set regsC100 EX_CS0_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x08]
+dict set regsC100 EX_CS1_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x0C]
+dict set regsC100 EX_CS2_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x10]
+dict set regsC100 EX_CS3_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x14]
+dict set regsC100 EX_CS4_SEG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x18]
+dict set regsC100 EX_CS0_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x1C]
+dict set regsC100 EX_CS1_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x20]
+dict set regsC100 EX_CS2_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x24]
+dict set regsC100 EX_CS3_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x28]
+dict set regsC100 EX_CS4_CFG_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x2C]
+dict set regsC100 EX_CS0_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x30]
+dict set regsC100 EX_CS1_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x34]
+dict set regsC100 EX_CS2_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x38]
+dict set regsC100 EX_CS3_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x3C]
+dict set regsC100 EX_CS4_TMG1_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x40]
+dict set regsC100 EX_CS0_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x44]
+dict set regsC100 EX_CS1_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x48]
+dict set regsC100 EX_CS2_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x4C]
+dict set regsC100 EX_CS3_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x50]
+dict set regsC100 EX_CS4_TMG2_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x54]
+dict set regsC100 EX_CS0_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x58]
+dict set regsC100 EX_CS1_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x5C]
+dict set regsC100 EX_CS2_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x60]
+dict set regsC100 EX_CS3_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x64]
+dict set regsC100 EX_CS4_TMG3_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x68]
+dict set regsC100 EX_CLOCK_DIV_REG [expr [dict get $regsC100 EBUS_BASEADDR ] + 0x6C]
+
+dict set regsC100 EX_MFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100]
+dict set regsC100 EX_MFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x100]
+dict set regsC100 EX_CSFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x104]
+dict set regsC100 EX_WRFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x108]
+dict set regsC100 EX_RDFSM_REG [expr [dict get $regsC100 EBUS_BASEADDR] + 0x10C]
+
+
+dict set regsC100 EX_CLK_EN 0x00000001
+dict set regsC100 EX_CSBOOT_EN 0x00000002
+dict set regsC100 EX_CS0_EN 0x00000002
+dict set regsC100 EX_CS1_EN 0x00000004
+dict set regsC100 EX_CS2_EN 0x00000008
+dict set regsC100 EX_CS3_EN 0x00000010
+dict set regsC100 EX_CS4_EN 0x00000020
+
+dict set regsC100 EX_MEM_BUS_8 0x00000000
+dict set regsC100 EX_MEM_BUS_16 0x00000002
+dict set regsC100 EX_MEM_BUS_32 0x00000004
+dict set regsC100 EX_CS_HIGH 0x00000008
+dict set regsC100 EX_WE_HIGH 0x00000010
+dict set regsC100 EX_RE_HIGH 0x00000020
+dict set regsC100 EX_ALE_MODE 0x00000040
+dict set regsC100 EX_STRB_MODE 0x00000080
+dict set regsC100 EX_DM_MODE 0x00000100
+dict set regsC100 EX_NAND_MODE 0x00000200
+dict set regsC100 EX_RDY_EN 0x00000400
+dict set regsC100 EX_RDY_EDGE 0x00000800
+
+#////////////////////////////////////////////////////////////
+#// GPIO block
+#////////////////////////////////////////////////////////////
+
+# GPIO outputs register
+dict set regsC100 GPIO_OUTPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x00]
+# GPIO Output Enable register
+dict set regsC100 GPIO_OE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x04]
+dict set regsC100 GPIO_HI_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x08]
+dict set regsC100 GPIO_LO_INT_ENABLE_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x0C]
+# GPIO input register
+dict set regsC100 GPIO_INPUT_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x10]
+dict set regsC100 APB_ACCESS_WS_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x14]
+dict set regsC100 MUX_CONF_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x18]
+dict set regsC100 SYSCONF_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x1C]
+dict set regsC100 GPIO_ARM_ID_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x30]
+dict set regsC100 GPIO_BOOTSTRAP_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x40]
+dict set regsC100 GPIO_LOCK_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x38]
+dict set regsC100 GPIO_IOCTRL_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x44]
+dict set regsC100 GPIO_DEVID_REG [expr [dict get $regsC100 GPIO_BASEADDR ] + 0x50]
+
+dict set regsC100 GPIO_IOCTRL_A15A16 0x00000001
+dict set regsC100 GPIO_IOCTRL_A17A18 0x00000002
+dict set regsC100 GPIO_IOCTRL_A19A21 0x00000004
+dict set regsC100 GPIO_IOCTRL_TMREVT0 0x00000008
+dict set regsC100 GPIO_IOCTRL_TMREVT1 0x00000010
+dict set regsC100 GPIO_IOCTRL_GPBT3 0x00000020
+dict set regsC100 GPIO_IOCTRL_I2C 0x00000040
+dict set regsC100 GPIO_IOCTRL_UART0 0x00000080
+dict set regsC100 GPIO_IOCTRL_UART1 0x00000100
+dict set regsC100 GPIO_IOCTRL_SPI 0x00000200
+dict set regsC100 GPIO_IOCTRL_HBMODE 0x00000400
+
+dict set regsC100 GPIO_IOCTRL_VAL 0x55555555
+
+dict set regsC100 GPIO_0 0x01
+dict set regsC100 GPIO_1 0x02
+dict set regsC100 GPIO_2 0x04
+dict set regsC100 GPIO_3 0x08
+dict set regsC100 GPIO_4 0x10
+dict set regsC100 GPIO_5 0x20
+dict set regsC100 GPIO_6 0x40
+dict set regsC100 GPIO_7 0x80
+
+dict set regsC100 GPIO_RISING_EDGE 1
+dict set regsC100 GPIO_FALLING_EDGE 2
+dict set regsC100 GPIO_BOTH_EDGES 3
+
+#////////////////////////////////////////////////////////////
+#// UART
+#////////////////////////////////////////////////////////////
+
+dict set regsC100 UART0_RBR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00]
+dict set regsC100 UART0_THR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00]
+dict set regsC100 UART0_DLL [expr [dict get $regsC100 UART0_BASEADDR ] + 0x00]
+dict set regsC100 UART0_IER [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04]
+dict set regsC100 UART0_DLH [expr [dict get $regsC100 UART0_BASEADDR ] + 0x04]
+dict set regsC100 UART0_IIR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08]
+dict set regsC100 UART0_FCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x08]
+dict set regsC100 UART0_LCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x0C]
+dict set regsC100 UART0_MCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x10]
+dict set regsC100 UART0_LSR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x14]
+dict set regsC100 UART0_MSR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x18]
+dict set regsC100 UART0_SCR [expr [dict get $regsC100 UART0_BASEADDR ] + 0x1C]
+
+dict set regsC100 UART1_RBR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00]
+dict set regsC100 UART1_THR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00]
+dict set regsC100 UART1_DLL [expr [dict get $regsC100 UART1_BASEADDR ] + 0x00]
+dict set regsC100 UART1_IER [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04]
+dict set regsC100 UART1_DLH [expr [dict get $regsC100 UART1_BASEADDR ] + 0x04]
+dict set regsC100 UART1_IIR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08]
+dict set regsC100 UART1_FCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x08]
+dict set regsC100 UART1_LCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x0C]
+dict set regsC100 UART1_MCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x10]
+dict set regsC100 UART1_LSR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x14]
+dict set regsC100 UART1_MSR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x18]
+dict set regsC100 UART1_SCR [expr [dict get $regsC100 UART1_BASEADDR ] + 0x1C]
+
+# /* default */
+dict set regsC100 LCR_CHAR_LEN_5 0x00
+dict set regsC100 LCR_CHAR_LEN_6 0x01
+dict set regsC100 LCR_CHAR_LEN_7 0x02
+dict set regsC100 LCR_CHAR_LEN_8 0x03
+#/* One stop bit! - default */
+dict set regsC100 LCR_ONE_STOP 0x00
+#/* Two stop bit! */
+dict set regsC100 LCR_TWO_STOP 0x04
+#/* Parity Enable */
+dict set regsC100 LCR_PEN 0x08
+dict set regsC100 LCR_PARITY_NONE 0x00
+#/* Even Parity Select */
+dict set regsC100 LCR_EPS 0x10
+#/* Enable Parity Stuff */
+dict set regsC100 LCR_PS 0x20
+#/* Start Break */
+dict set regsC100 LCR_SBRK 0x40
+#/* Parity Stuff Bit */
+dict set regsC100 LCR_PSB 0x80
+#/* UART 16550 Divisor Latch Assess */
+dict set regsC100 LCR_DLAB 0x80
+
+#/* FIFO Error Status */
+dict set regsC100 LSR_FIFOE [expr 1 << 7]
+#/* Transmitter Empty */
+dict set regsC100 LSR_TEMT [expr 1 << 6]
+#/* Transmit Data Request */
+dict set regsC100 LSR_TDRQ [expr 1 << 5]
+#/* Break Interrupt */
+dict set regsC100 LSR_BI [expr 1 << 4]
+#/* Framing Error */
+dict set regsC100 LSR_FE [expr 1 << 3]
+#/* Parity Error */
+dict set regsC100 LSR_PE [expr 1 << 2]
+#/* Overrun Error */
+dict set regsC100 LSR_OE [expr 1 << 1]
+#/* Data Ready */
+dict set regsC100 LSR_DR [expr 1 << 0]
+
+#/* DMA Requests Enable */
+dict set regsC100 IER_DMAE [expr 1 << 7]
+#/* UART Unit Enable */
+dict set regsC100 IER_UUE [expr 1 << 6]
+#/* NRZ coding Enable */
+dict set regsC100 IER_NRZE [expr 1 << 5]
+#/* Receiver Time Out Interrupt Enable */
+dict set regsC100 IER_RTIOE [expr 1 << 4]
+#/* Modem Interrupt Enable */
+dict set regsC100 IER_MIE [expr 1 << 3]
+#/* Receiver Line Status Interrupt Enable */
+dict set regsC100 IER_RLSE [expr 1 << 2]
+#/* Transmit Data request Interrupt Enable */
+dict set regsC100 IER_TIE [expr 1 << 1]
+#/* Receiver Data Available Interrupt Enable */
+dict set regsC100 IER_RAVIE [expr 1 << 0]
+
+#/* FIFO Mode Enable Status */
+dict set regsC100 IIR_FIFOES1 [expr 1 << 7]
+#/* FIFO Mode Enable Status */
+dict set regsC100 IIR_FIFOES0 [expr 1 << 6]
+#/* Time Out Detected */
+dict set regsC100 IIR_TOD [expr 1 << 3]
+#/* Interrupt Source Encoded */
+dict set regsC100 IIR_IID2 [expr 1 << 2]
+#/* Interrupt Source Encoded */
+dict set regsC100 IIR_IID1 [expr 1 << 1]
+#/* Interrupt Pending (active low) */
+dict set regsC100 IIR_IP [expr 1 << 0]
+
+#/* UART 16550 FIFO Control Register */
+dict set regsC100 FCR_FIFOEN 0x01
+dict set regsC100 FCR_RCVRRES 0x02
+dict set regsC100 FCR_XMITRES 0x04
+
+#/* Interrupt Enable Register */
+#// UART 16550
+#// Enable Received Data Available Interrupt
+dict set regsC100 IER_RXTH 0x01
+#// Enable Transmitter Empty Interrupt
+dict set regsC100 IER_TXTH 0x02
+
+
+
+#////////////////////////////////////////////////////////////
+#// CLK + RESET block
+#////////////////////////////////////////////////////////////
+
+dict set regsC100 CLKCORE_ARM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x00]
+dict set regsC100 CLKCORE_AHB_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x04]
+dict set regsC100 CLKCORE_PLL_STATUS [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x08]
+dict set regsC100 CLKCORE_CLKDIV_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x0C]
+dict set regsC100 CLKCORE_TDM_CLK_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x10]
+dict set regsC100 CLKCORE_FSYNC_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x14]
+dict set regsC100 CLKCORE_CLK_PWR_DWN [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x18]
+dict set regsC100 CLKCORE_RNG_CNTRL [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x1C]
+dict set regsC100 CLKCORE_RNG_STATUS [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x20]
+dict set regsC100 CLKCORE_ARM_CLK_CNTRL2 [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x24]
+dict set regsC100 CLKCORE_TDM_REF_DIV_RST [expr [dict get $regsC100 CLKCORE_BASEADDR ] + 0x40]
+
+dict set regsC100 ARM_PLL_BY_CTRL 0x80000000
+dict set regsC100 ARM_AHB_BYP 0x04000000
+dict set regsC100 PLL_DISABLE 0x02000000
+dict set regsC100 PLL_CLK_BYPAS...
[truncated message content] |
|
From: oharboe at B. <oh...@ma...> - 2009-09-09 18:11:34
|
Author: oharboe
Date: 2009-09-09 18:11:33 +0200 (Wed, 09 Sep 2009)
New Revision: 2682
Modified:
trunk/src/flash/cfi.c
trunk/src/flash/non_cfi.c
Log:
Rolf Meeser <rol...@ya...>
This patch adds target algorithm support for those flash devices that do not support DQ5 polling. So far they could only be programmed with host algorithm, but this was way too slow.
Modified: trunk/src/flash/cfi.c
===================================================================
--- trunk/src/flash/cfi.c 2009-09-09 07:09:14 UTC (rev 2681)
+++ trunk/src/flash/cfi.c 2009-09-09 16:11:33 UTC (rev 2682)
@@ -1384,6 +1384,31 @@
0xeafffffe /* b 81ac <sp_16_done> */
};
+ static const uint32_t word_16_code_dq7only[] = {
+ /* <sp_16_code>: */
+ 0xe0d050b2, /* ldrh r5, [r0], #2 */
+ 0xe1c890b0, /* strh r9, [r8] */
+ 0xe1cab0b0, /* strh r11, [r10] */
+ 0xe1c830b0, /* strh r3, [r8] */
+ 0xe1c150b0, /* strh r5, [r1] */
+ 0xe1a00000, /* nop (mov r0,r0) */
+ /* */
+ /* <sp_16_busy>: */
+ 0xe1d160b0, /* ldrh r6, [r1] */
+ 0xe0257006, /* eor r7, r5, r6 */
+ 0xe2177080, /* ands r7, #0x80 */
+ 0x1afffffb, /* bne 8168 <sp_16_busy> */
+ /* */
+ 0xe2522001, /* subs r2, r2, #1 ; 0x1 */
+ 0x03a05080, /* moveq r5, #128 ; 0x80 */
+ 0x0a000001, /* beq 81ac <sp_16_done> */
+ 0xe2811002, /* add r1, r1, #2 ; 0x2 */
+ 0xeafffff0, /* b 8158 <sp_16_code> */
+ /* */
+ /* 000081ac <sp_16_done>: */
+ 0xeafffffe /* b 81ac <sp_16_done> */
+ };
+
static const uint32_t word_8_code[] = {
/* 000081b0 <sp_16_code_end>: */
0xe4d05001, /* ldrb r5, [r0], #1 */
@@ -1423,10 +1448,10 @@
armv4_5_info.core_state = ARMV4_5_STATE_ARM;
/* flash write code */
+ int target_code_size;
if (!cfi_info->write_algorithm)
{
uint8_t *target_code;
- int target_code_size;
const uint32_t *src;
/* convert bus-width dependent algorithm code to correct endiannes */
@@ -1437,8 +1462,18 @@
target_code_size = sizeof(word_8_code);
break;
case 2:
- src = word_16_code;
- target_code_size = sizeof(word_16_code);
+ /* Check for DQ5 support */
+ if( cfi_info->status_poll_mask & (1 << 5) )
+ {
+ src = word_16_code;
+ target_code_size = sizeof(word_16_code);
+ }
+ else
+ {
+ /* No DQ5 support. Use DQ7 DATA# polling only. */
+ src = word_16_code_dq7only;
+ target_code_size = sizeof(word_16_code_dq7only);
+ }
break;
case 4:
src = word_32_code;
@@ -1515,7 +1550,7 @@
retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
cfi_info->write_algorithm->address,
- cfi_info->write_algorithm->address + ((24 * 4) - 4),
+ cfi_info->write_algorithm->address + ((target_code_size) - 4),
10000, &armv4_5_info);
status = buf_get_u32(reg_params[5].value, 0, 32);
@@ -1532,7 +1567,7 @@
count -= thisrun_count;
}
- target_free_working_area(target, source);
+ target_free_all_working_areas(target);
destroy_reg_param(®_params[0]);
destroy_reg_param(®_params[1]);
Modified: trunk/src/flash/non_cfi.c
===================================================================
--- trunk/src/flash/non_cfi.c 2009-09-09 07:09:14 UTC (rev 2681)
+++ trunk/src/flash/non_cfi.c 2009-09-09 16:11:33 UTC (rev 2682)
@@ -140,7 +140,10 @@
/* SST 39VF* do not support DQ5 status polling - this currently is
only supported by the host algorithm, not by the target code using
- the work area. */
+ the work area.
+ Only true for 8-bit and 32-bit wide memories. 16-bit wide memories
+ without DQ5 status polling are supported by the target code.
+ */
{
.mfr = CFI_MFR_SST,
.id = 0x2782, /* SST39xF160 */
|
|
From: oharboe at B. <oh...@ma...> - 2009-09-09 09:09:15
|
Author: oharboe
Date: 2009-09-09 09:09:14 +0200 (Wed, 09 Sep 2009)
New Revision: 2681
Modified:
trunk/src/jtag/tcl.c
Log:
- Fix bug-in-waiting when adding more than one TAP event type
- Infinite loop bugfix when running tap configure a second time
Modified: trunk/src/jtag/tcl.c
===================================================================
--- trunk/src/jtag/tcl.c 2009-09-09 06:28:49 UTC (rev 2680)
+++ trunk/src/jtag/tcl.c 2009-09-09 07:09:14 UTC (rev 2681)
@@ -141,9 +141,11 @@
}
if (goi->isconfigure) {
+ bool replace = true;
if (jteap == NULL) {
/* create new */
jteap = calloc(1, sizeof (*jteap));
+ replace = false;
}
jteap->event = n->value;
Jim_GetOpt_Obj(goi, &o);
@@ -153,9 +155,12 @@
jteap->body = Jim_DuplicateObj(goi->interp, o);
Jim_IncrRefCount(jteap->body);
- /* add to head of event list */
- jteap->next = tap->event_action;
- tap->event_action = jteap;
+ if (!replace)
+ {
+ /* add to head of event list */
+ jteap->next = tap->event_action;
+ tap->event_action = jteap;
+ }
Jim_SetEmptyResult(goi->interp);
} else {
/* get */
@@ -374,7 +379,8 @@
* can't fail. That presumes later code
* will be verifying the scan chains ...
*/
- tap->enabled = (e == JTAG_TAP_EVENT_ENABLE);
+ if (e == JTAG_TAP_EVENT_ENABLE)
+ tap->enabled = true;
}
}
|
|
From: oharboe at B. <oh...@ma...> - 2009-09-09 08:28:50
|
Author: oharboe
Date: 2009-09-09 08:28:49 +0200 (Wed, 09 Sep 2009)
New Revision: 2680
Modified:
trunk/src/flash/arm_nandio.c
trunk/src/target/arm7tdmi.c
trunk/src/target/arm9tdmi.c
trunk/src/target/armv4_5.c
trunk/src/target/armv4_5.h
Log:
David Brownell <da...@pa...>
Optionally shave time off the armv4_5 run_algorithm() code: let
them terminate using software breakpoints, avoiding roundtrips
to manage hardware ones.
Enable this by using BKPT to terminate execution instead of "branch
to here" loops. Then pass zero as the exit address, except when
running on an ARMv4 core. ARM7TDMI, ARM9TDMI, and derived cores
now set a flag saying they're ARMv4.
Use that mechanism in arm_nandwrite(), for about 3% speedup on a
DaVinci ARM926 core; not huge, but it helps. Some other algorithms
could use this too (mostly flavors of flash operation).
Modified: trunk/src/flash/arm_nandio.c
===================================================================
--- trunk/src/flash/arm_nandio.c 2009-09-09 06:27:47 UTC (rev 2679)
+++ trunk/src/flash/arm_nandio.c 2009-09-09 06:28:49 UTC (rev 2680)
@@ -33,7 +33,6 @@
* For now this only supports ARMv4 and ARMv5 cores.
*
* Enhancements to target_run_algorithm() could enable:
- * - faster writes: on ARMv5+ don't setup/teardown hardware breakpoint
* - ARMv6 and ARMv7 cores in ARM mode
*
* Different code fragments could handle:
@@ -44,8 +43,10 @@
{
target_t *target = nand->target;
armv4_5_algorithm_t algo;
+ armv4_5_common_t *armv4_5 = target->arch_info;
reg_param_t reg_params[3];
uint32_t target_buf;
+ uint32_t exit = 0;
int retval;
/* Inputs:
@@ -112,11 +113,13 @@
buf_set_u32(reg_params[1].value, 0, 32, target_buf);
buf_set_u32(reg_params[2].value, 0, 32, size);
+ /* armv4 must exit using a hardware breakpoint */
+ if (armv4_5->is_armv4)
+ exit = nand->copy_area->address + sizeof(code) - 4;
+
/* use alg to write data from work area to NAND chip */
retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
- nand->copy_area->address,
- nand->copy_area->address + sizeof(code) - 4,
- 1000, &algo);
+ nand->copy_area->address, exit, 1000, &algo);
if (retval != ERROR_OK)
LOG_ERROR("error executing hosted NAND write");
Modified: trunk/src/target/arm7tdmi.c
===================================================================
--- trunk/src/target/arm7tdmi.c 2009-09-09 06:27:47 UTC (rev 2679)
+++ trunk/src/target/arm7tdmi.c 2009-09-09 06:28:49 UTC (rev 2680)
@@ -828,6 +828,7 @@
arm7tdmi = calloc(1,sizeof(arm7tdmi_common_t));
arm7tdmi_init_arch_info(target, arm7tdmi, target->tap);
+ arm7tdmi->arm7_9_common.armv4_5_common.is_armv4 = true;
return ERROR_OK;
}
Modified: trunk/src/target/arm9tdmi.c
===================================================================
--- trunk/src/target/arm9tdmi.c 2009-09-09 06:27:47 UTC (rev 2679)
+++ trunk/src/target/arm9tdmi.c 2009-09-09 06:28:49 UTC (rev 2680)
@@ -956,6 +956,7 @@
arm9tdmi_common_t *arm9tdmi = calloc(1,sizeof(arm9tdmi_common_t));
arm9tdmi_init_arch_info(target, arm9tdmi, target->tap);
+ arm9tdmi->arm7_9_common.armv4_5_common.is_armv4 = true;
return ERROR_OK;
}
Modified: trunk/src/target/armv4_5.c
===================================================================
--- trunk/src/target/armv4_5.c 2009-09-09 06:27:47 UTC (rev 2679)
+++ trunk/src/target/armv4_5.c 2009-09-09 06:28:49 UTC (rev 2680)
@@ -532,7 +532,10 @@
}
return ERROR_TARGET_TIMEOUT;
}
- if (buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != exit_point)
+
+ /* fast exit: ARMv5+ code can use BKPT */
+ if (exit_point && buf_get_u32(armv4_5->core_cache->reg_list[15].value,
+ 0, 32) != exit_point)
{
LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
@@ -570,6 +573,13 @@
if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
return ERROR_FAIL;
+ /* armv5 and later can terminate with BKPT instruction; less overhead */
+ if (!exit_point && armv4_5->is_armv4)
+ {
+ LOG_ERROR("ARMv4 target needs HW breakpoint location");
+ return ERROR_FAIL;
+ }
+
for (i = 0; i <= 16; i++)
{
if (!ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid)
@@ -626,9 +636,11 @@
armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
}
- if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
+ /* terminate using a hardware or (ARMv5+) software breakpoint */
+ if (exit_point && (retval = breakpoint_add(target, exit_point,
+ exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
{
- LOG_ERROR("can't add breakpoint to finish algorithm execution");
+ LOG_ERROR("can't add HW breakpoint to terminate algorithm");
return ERROR_TARGET_FAILURE;
}
@@ -639,7 +651,8 @@
int retvaltemp;
retval = run_it(target, exit_point, timeout_ms, arch_info);
- breakpoint_remove(target, exit_point);
+ if (exit_point)
+ breakpoint_remove(target, exit_point);
if (retval != ERROR_OK)
return retval;
Modified: trunk/src/target/armv4_5.h
===================================================================
--- trunk/src/target/armv4_5.h 2009-09-09 06:27:47 UTC (rev 2679)
+++ trunk/src/target/armv4_5.h 2009-09-09 06:28:49 UTC (rev 2680)
@@ -76,6 +76,7 @@
reg_cache_t *core_cache;
enum armv4_5_mode core_mode;
enum armv4_5_state core_state;
+ bool is_armv4;
int (*full_context)(struct target_s *target);
int (*read_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode);
int (*write_core_reg)(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value);
|
|
From: oharboe at B. <oh...@ma...> - 2009-09-09 08:27:50
|
Author: oharboe
Date: 2009-09-09 08:27:47 +0200 (Wed, 09 Sep 2009)
New Revision: 2679
Modified:
trunk/doc/openocd.texi
Log:
David Brownell <da...@pa...>
Fix docs on ARM11 MCR and MRC coprocessor commands:
correct read-vs-write; and describe the params.
(ARM920 and ARM926 have cp15-specific commands; this
approach is more generic. MCR2, MRC2, MCRR, MCRR2,
MRRC, and MRRC2 instructions could also get exposed.)
Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi 2009-09-08 15:32:18 UTC (rev 2678)
+++ trunk/doc/openocd.texi 2009-09-09 06:27:47 UTC (rev 2679)
@@ -5038,8 +5038,13 @@
@subsection ARM11 specific commands
@cindex ARM11
-@deffn Command {arm11 mcr} p1 p2 p3 p4 p5
-Read coprocessor register
+@deffn Command {arm11 mcr} pX opc1 CRn CRm opc2 value
+Write @var{value} to a coprocessor @var{pX} register
+passing parameters @var{CRn},
+@var{CRm}, opcodes @var{opc1} and @var{opc2},
+and the MCR instruction.
+(The difference beween this and the MCR2 instruction is
+one bit in the encoding, effecively a fifth parameter.)
@end deffn
@deffn Command {arm11 memwrite burst} [value]
@@ -5054,8 +5059,13 @@
If @var{value} is defined, first assigns that.
@end deffn
-@deffn Command {arm11 mrc} p1 p2 p3 p4 p5 value
-Write coprocessor register
+@deffn Command {arm11 mrc} pX opc1 CRn CRm opc2
+Read a coprocessor @var{pX} register passing parameters @var{CRn},
+@var{CRm}, opcodes @var{opc1} and @var{opc2},
+and the MRC instruction.
+(The difference beween this and the MRC2 instruction is
+one bit in the encoding, effecively a fifth parameter.)
+Displays the result.
@end deffn
@deffn Command {arm11 no_increment} [value]
|
|
From: <ml...@ma...> - 2009-09-08 17:32:19
|
Author: mlu
Date: 2009-09-08 17:32:18 +0200 (Tue, 08 Sep 2009)
New Revision: 2678
Modified:
trunk/src/target/armv7a.c
Log:
Report correct core instruction state for ARMv/A targets
Modified: trunk/src/target/armv7a.c
===================================================================
--- trunk/src/target/armv7a.c 2009-09-08 15:31:24 UTC (rev 2677)
+++ trunk/src/target/armv7a.c 2009-09-08 15:32:18 UTC (rev 2678)
@@ -192,7 +192,7 @@
LOG_USER("target halted in %s state due to %s, current mode: %s\n"
"%s: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
"MMU: %s, D-Cache: %s, I-Cache: %s",
- armv7a_state_strings[armv4_5->core_state],
+ armv7a_state_strings[armv7a->core_state],
Jim_Nvp_value2name_simple(nvp_target_debug_reason,
target->debug_reason)->name,
armv7a_mode_strings[
|
|
From: <ml...@ma...> - 2009-09-08 17:31:29
|
Author: mlu
Date: 2009-09-08 17:31:24 +0200 (Tue, 08 Sep 2009)
New Revision: 2677
Modified:
trunk/src/target/cortex_a8.c
Log:
Load PC with bit 0 set to 1 when resuming to say in Thumb instruction state.
Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c 2009-09-08 06:18:45 UTC (rev 2676)
+++ trunk/src/target/cortex_a8.c 2009-09-08 15:31:24 UTC (rev 2677)
@@ -85,7 +85,6 @@
.deassert_reset = NULL,
.soft_reset_halt = NULL,
-// .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
.read_memory = cortex_a8_read_memory,
@@ -509,6 +508,13 @@
{
resume_pc &= 0xFFFFFFFC;
}
+ /* When the return address is loaded into PC
+ * bit 0 must be 1 to stay in Thumb state
+ */
+ if (armv7a->core_state == ARMV7A_STATE_THUMB)
+ {
+ resume_pc |= 0x1;
+ }
LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
buf_set_u32(ARMV7A_CORE_REG_MODE(armv4_5->core_cache,
armv4_5->core_mode, 15).value,
@@ -592,7 +598,6 @@
retval = mem_ap_write_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
-
/* Examine debug reason */
switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
{
|
|
From: oharboe at B. <oh...@ma...> - 2009-09-08 08:18:52
|
Author: oharboe
Date: 2009-09-08 08:18:45 +0200 (Tue, 08 Sep 2009)
New Revision: 2676
Modified:
trunk/doc/openocd.texi
trunk/src/target/armv7a.c
Log:
David Brownell <da...@pa...>
Provide an "armv7a disassemble" command. Current omissions include
VFP (except as coprocessor instructions), Neon, and various Thumb2
opcodes that are not available in ARMv7-M processors.
Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi 2009-09-08 06:17:33 UTC (rev 2675)
+++ trunk/doc/openocd.texi 2009-09-08 06:18:45 UTC (rev 2676)
@@ -5105,6 +5105,23 @@
If @var{value} is defined, first assigns that.
@end deffn
+@subsection ARMv7-A specific commands
+@cindex ARMv7-A
+
+@deffn Command {armv7a disassemble} address [count [@option{thumb}]]
+@cindex disassemble
+Disassembles @var{count} instructions starting at @var{address}.
+If @var{count} is not specified, a single instruction is disassembled.
+If @option{thumb} is specified, or the low bit of the address is set,
+Thumb2 (mixed 16/32-bit) instructions are used;
+else ARM (32-bit) instructions are used.
+With a handful of exceptions, ThumbEE instructions are the same as Thumb2;
+ThumbEE disassembly currently has no explicit support.
+(Processors may also support the Jazelle state, but
+those instructions are not currently understood by OpenOCD.)
+@end deffn
+
+
@subsection Cortex-M3 specific commands
@cindex Cortex-M3
Modified: trunk/src/target/armv7a.c
===================================================================
--- trunk/src/target/armv7a.c 2009-09-08 06:17:33 UTC (rev 2675)
+++ trunk/src/target/armv7a.c 2009-09-08 06:18:45 UTC (rev 2676)
@@ -23,6 +23,7 @@
#include "replacements.h"
#include "armv7a.h"
+#include "arm_disassembler.h"
#include "target.h"
#include "register.h"
@@ -269,9 +270,86 @@
return dap_info_command(cmd_ctx, swjdp, apsel);
}
+static int
+handle_armv7a_disassemble_command(struct command_context_s *cmd_ctx,
+ char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ int thumb = 0;
+ int count = 1;
+ uint32_t address;
+ int i;
+
+ if (armv4_5->common_magic != ARMV4_5_COMMON_MAGIC) {
+ command_print(cmd_ctx, "current target isn't an ARM target");
+ return ERROR_OK;
+ }
+
+ /* REVISIT: eventually support ThumbEE disassembly too;
+ * some opcodes work differently.
+ */
+
+ switch (argc) {
+ case 3:
+ if (strcmp(args[2], "thumb") != 0)
+ goto usage;
+ thumb = 1;
+ /* FALL THROUGH */
+ case 2:
+ count = strtoul(args[1], NULL, 0);
+ /* FALL THROUGH */
+ case 1:
+ address = strtoul(args[0], NULL, 0);
+ if (address & 0x01) {
+ if (!thumb) {
+ command_print(cmd_ctx, "Disassemble as Thumb");
+ thumb = 1;
+ }
+ address &= ~1;
+ }
+ break;
+ default:
+usage:
+ command_print(cmd_ctx,
+ "usage: armv4_5 disassemble <address> [<count> ['thumb']]");
+ return ERROR_OK;
+ }
+
+ for (i = 0; i < count; i++) {
+ arm_instruction_t cur_instruction;
+ int retval;
+
+ if (thumb) {
+ retval = thumb2_opcode(target, address, &cur_instruction);
+ if (retval != ERROR_OK)
+ return retval;
+
+ address += cur_instruction.instruction_size;
+ } else {
+ uint32_t opcode;
+
+ retval = target_read_u32(target, address, &opcode);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = arm_evaluate_opcode(opcode, address,
+ &cur_instruction);
+ if (retval != ERROR_OK)
+ return retval;
+
+ address += 4;
+ }
+ command_print(cmd_ctx, "%s", cur_instruction.text);
+ }
+
+ return ERROR_OK;
+}
+
int armv7a_register_commands(struct command_context_s *cmd_ctx)
{
command_t *arm_adi_v5_dap_cmd;
+ command_t *armv7a_cmd;
arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap",
NULL, COMMAND_ANY,
@@ -297,5 +375,13 @@
"set/get number of extra tck for mem-ap memory "
"bus access [0-255]");
+ armv7a_cmd = register_command(cmd_ctx, NULL, "armv7a",
+ NULL, COMMAND_ANY,
+ "ARMv7-A specific commands");
+
+ register_command(cmd_ctx, armv7a_cmd, "disassemble",
+ handle_armv7a_disassemble_command, COMMAND_EXEC,
+ "disassemble instructions <address> [<count> ['thumb']]");
+
return ERROR_OK;
}
|
|
From: oharboe at B. <oh...@ma...> - 2009-09-08 08:17:36
|
Author: oharboe
Date: 2009-09-08 08:17:33 +0200 (Tue, 08 Sep 2009)
New Revision: 2675
Modified:
trunk/src/target/arm_disassembler.c
Log:
David Brownell <da...@pa...>
lean up some loose ends with the ARM disassembler
- Add a header comment describing its current state and uses
and referencing the now-generally-available V7 arch spec
- Support some mode switch instructions:
* Thumb to Jazelle (BXJ)
* Thumb to ThumbEE (ENTERX)
* ThumbEE to Thumb (LEAVEX)
- Improve that recent warning fix (and associated whitespace goof)
- Declare the rest of the internal code and data "static". A
compiler may use this, and it helps clarify the scope of these
routines (e.g. what changes to them could affect).
Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c 2009-09-07 20:19:17 UTC (rev 2674)
+++ trunk/src/target/arm_disassembler.c 2009-09-08 06:17:33 UTC (rev 2675)
@@ -28,20 +28,86 @@
#include "log.h"
+/*
+ * This disassembler supports two main functions for OpenOCD:
+ *
+ * - Various "disassemble" commands. OpenOCD can serve as a
+ * machine-language debugger, without help from GDB.
+ *
+ * - Single stepping. Not all ARM cores support hardware single
+ * stepping. To work without that support, the debugger must
+ * be able to decode instructions to find out where to put a
+ * "next instruction" breakpoint.
+ *
+ * In addition, interpretation of ETM trace data needs some of the
+ * decoding mechanisms.
+ *
+ * At this writing (September 2009) neither function is complete.
+ *
+ * - ARM decoding
+ * * Old-style syntax (not UAL) is generally used
+ * * VFP instructions are not understood (ARMv5 and later)
+ * except as coprocessor 10/11 operations
+ * * Most ARM instructions through ARMv6 are decoded, but some
+ * of the post-ARMv4 opcodes may not be handled yet
+ * * NEON instructions are not understood (ARMv7-A)
+ *
+ * - Thumb/Thumb2 decoding
+ * * UAL syntax should be consistently used
+ * * Any Thumb2 instructions used in Cortex-M3 (ARMv7-M) should
+ * be handled properly. Accordingly, so should the subset
+ * used in Cortex-M0/M1; and "original" 16-bit Thumb from
+ * ARMv4T and ARMv5T.
+ * * Conditional effects of Thumb2 "IT" (if-then) instructions
+ * are not handled: the affected instructions are not shown
+ * with their now-conditional suffixes.
+ * * Some ARMv6 and ARMv7-M Thumb2 instructions may not be
+ * handled (minimally for coprocessor access).
+ * * SIMD instructions, and some other Thumb2 instructions
+ * from ARMv7-A, are not understood.
+ *
+ * - ThumbEE decoding
+ * * As a Thumb2 variant, the Thumb2 comments (above) apply.
+ * * Opcodes changed by ThumbEE mode are not handled; these
+ * instructions wrongly decode as LDM and STM.
+ *
+ * - Jazelle decoding ... no support whatsoever for Jazelle mode
+ * or decoding. ARM encourages use of the more generic ThumbEE
+ * mode, instead of Jazelle mode, in current chips.
+ *
+ * - Single-step/emulation ... spotty support, which is only weakly
+ * tested. Thumb2 is not supported. (Arguably a full simulator
+ * is not needed to support just single stepping. Recognizing
+ * branch vs non-branch instructions suffices, except when the
+ * instruction faults and triggers a synchronous exception which
+ * can be intercepted using other means.)
+ *
+ * ARM DDI 0406B "ARM Architecture Reference Manual, ARM v7-A and
+ * ARM v7-R edition" gives the most complete coverage of the various
+ * generations of ARM instructions. At this writing it is publicly
+ * accessible to anyone willing to create an account at the ARM
+ * web site; see http://www.arm.com/documentation/ for information.
+ *
+ * ARM DDI 0403C "ARMv7-M Architecture Reference Manual" provides
+ * more details relevant to the Thumb2-only processors (such as
+ * the Cortex-M implementations).
+ */
+
/* textual represenation of the condition field */
/* ALways (default) is ommitted (empty string) */
-char *arm_condition_strings[] =
+static const char *arm_condition_strings[] =
{
"EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT", "LE", "", "NV"
};
/* make up for C's missing ROR */
-uint32_t ror(uint32_t value, int places)
+static uint32_t ror(uint32_t value, int places)
{
return (value >> places) | (value << (32 - places));
}
-int evaluate_pld(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_pld(uint32_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
/* PLD */
if ((opcode & 0x0d70f0000) == 0x0550f000)
@@ -62,7 +128,8 @@
return -1;
}
-int evaluate_swi(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_swi(uint32_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
instruction->type = ARM_SWI;
@@ -73,7 +140,8 @@
return ERROR_OK;
}
-int evaluate_blx_imm(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_blx_imm(uint32_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
int offset;
uint32_t immediate;
@@ -105,7 +173,8 @@
return ERROR_OK;
}
-int evaluate_b_bl(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_b_bl(uint32_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint8_t L;
uint32_t immediate;
@@ -142,7 +211,8 @@
/* Coprocessor load/store and double register transfers */
/* both normal and extended instruction space (condition field b1111) */
-int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_ldc_stc_mcrr_mrrc(uint32_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint8_t cp_num = (opcode & 0xf00) >> 8;
@@ -222,9 +292,10 @@
/* Coprocessor data processing instructions */
/* Coprocessor register transfer instructions */
/* both normal and extended instruction space (condition field b1111) */
-int evaluate_cdp_mcr_mrc(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_cdp_mcr_mrc(uint32_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
- char* cond;
+ const char *cond;
char* mnemonic;
uint8_t cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2;
@@ -271,7 +342,8 @@
}
/* Load/store instructions */
-int evaluate_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_load_store(uint32_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint8_t I, P, U, B, W, L;
uint8_t Rn, Rd;
@@ -445,9 +517,6 @@
unsigned rn = (opcode >> 16) & 0xf;
char *type, *rot;
- /* GCC 'uninitialized warning removal' */
- type = rot = NULL;
-
switch ((opcode >> 24) & 0x3) {
case 0:
type = "B16";
@@ -458,7 +527,7 @@
case 2:
type = "B";
break;
- case 3:
+ default:
type = "H";
break;
}
@@ -473,7 +542,7 @@
case 2:
rot = ", ROR #16";
break;
- case 3:
+ default:
rot = ", ROR #24";
break;
}
@@ -759,7 +828,8 @@
}
/* Miscellaneous load/store instructions */
-int evaluate_misc_load_store(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_misc_load_store(uint32_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint8_t P, U, I, W, L, S, H;
uint8_t Rn, Rd;
@@ -886,7 +956,8 @@
}
/* Load/store multiples instructions */
-int evaluate_ldm_stm(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_ldm_stm(uint32_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint8_t P, U, S, W, L, Rn;
uint32_t register_list;
@@ -974,7 +1045,8 @@
}
/* Multiplies, extra load/stores */
-int evaluate_mul_and_extra_ld_st(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_mul_and_extra_ld_st(uint32_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
/* Multiply (accumulate) (long) and Swap/swap byte */
if ((opcode & 0x000000f0) == 0x00000090)
@@ -1065,7 +1137,8 @@
return evaluate_misc_load_store(opcode, address, instruction);
}
-int evaluate_mrs_msr(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_mrs_msr(uint32_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
int R = (opcode & 0x00400000) >> 22;
char *PSR = (R) ? "SPSR" : "CPSR";
@@ -1119,7 +1192,8 @@
}
/* Miscellaneous instructions */
-int evaluate_misc_instr(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_misc_instr(uint32_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
/* MRS/MSR */
if ((opcode & 0x000000f0) == 0x00000000)
@@ -1309,7 +1383,8 @@
return ERROR_OK;
}
-int evaluate_data_proc(uint32_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_data_proc(uint32_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint8_t I, op, S, Rn, Rd;
char *mnemonic = NULL;
@@ -1668,7 +1743,8 @@
return -1;
}
-int evaluate_b_bl_blx_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_b_bl_blx_thumb(uint16_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint32_t offset = opcode & 0x7ff;
uint32_t opc = (opcode >> 11) & 0x3;
@@ -1721,7 +1797,8 @@
return ERROR_OK;
}
-int evaluate_add_sub_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_add_sub_thumb(uint16_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint8_t Rd = (opcode >> 0) & 0x7;
uint8_t Rn = (opcode >> 3) & 0x7;
@@ -1766,7 +1843,8 @@
return ERROR_OK;
}
-int evaluate_shift_imm_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_shift_imm_thumb(uint16_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint8_t Rd = (opcode >> 0) & 0x7;
uint8_t Rm = (opcode >> 3) & 0x7;
@@ -1811,7 +1889,8 @@
return ERROR_OK;
}
-int evaluate_data_proc_imm_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_data_proc_imm_thumb(uint16_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint8_t imm = opcode & 0xff;
uint8_t Rd = (opcode >> 8) & 0x7;
@@ -1853,7 +1932,8 @@
return ERROR_OK;
}
-int evaluate_data_proc_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_data_proc_thumb(uint16_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint8_t high_reg, op, Rm, Rd,H1,H2;
char *mnemonic = NULL;
@@ -2038,7 +2118,8 @@
return (addr + 4) & ~3;
}
-int evaluate_load_literal_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_load_literal_thumb(uint16_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint32_t immediate;
uint8_t Rd = (opcode >> 8) & 0x7;
@@ -2062,7 +2143,8 @@
return ERROR_OK;
}
-int evaluate_load_store_reg_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_load_store_reg_thumb(uint16_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint8_t Rd = (opcode >> 0) & 0x7;
uint8_t Rn = (opcode >> 3) & 0x7;
@@ -2119,7 +2201,8 @@
return ERROR_OK;
}
-int evaluate_load_store_imm_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_load_store_imm_thumb(uint16_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint32_t offset = (opcode >> 6) & 0x1f;
uint8_t Rd = (opcode >> 0) & 0x7;
@@ -2165,7 +2248,8 @@
return ERROR_OK;
}
-int evaluate_load_store_stack_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_load_store_stack_thumb(uint16_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint32_t offset = opcode & 0xff;
uint8_t Rd = (opcode >> 8) & 0x7;
@@ -2196,7 +2280,8 @@
return ERROR_OK;
}
-int evaluate_add_sp_pc_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_add_sp_pc_thumb(uint16_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint32_t imm = opcode & 0xff;
uint8_t Rd = (opcode >> 8) & 0x7;
@@ -2229,7 +2314,8 @@
return ERROR_OK;
}
-int evaluate_adjust_stack_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_adjust_stack_thumb(uint16_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint32_t imm = opcode & 0x7f;
uint8_t opc = opcode & (1 << 7);
@@ -2259,7 +2345,8 @@
return ERROR_OK;
}
-int evaluate_breakpoint_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_breakpoint_thumb(uint16_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint32_t imm = opcode & 0xff;
@@ -2272,7 +2359,8 @@
return ERROR_OK;
}
-int evaluate_load_store_multiple_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_load_store_multiple_thumb(uint16_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint32_t reg_list = opcode & 0xff;
uint32_t L = opcode & (1 << 11);
@@ -2285,6 +2373,10 @@
char ptr_name[7] = "";
int i;
+ /* REVISIT: in ThumbEE mode, there are no LDM or STM instructions.
+ * The STMIA and LDMIA opcodes are used for other instructions.
+ */
+
if ((opcode & 0xf000) == 0xc000)
{ /* generic load/store multiple */
char *wback = "!";
@@ -2345,7 +2437,8 @@
return ERROR_OK;
}
-int evaluate_cond_branch_thumb(uint16_t opcode, uint32_t address, arm_instruction_t *instruction)
+static int evaluate_cond_branch_thumb(uint16_t opcode,
+ uint32_t address, arm_instruction_t *instruction)
{
uint32_t offset = opcode & 0xff;
uint8_t cond = (opcode >> 8) & 0xf;
@@ -2835,6 +2928,12 @@
const char *mnemonic;
switch ((opcode >> 4) & 0x0f) {
+ case 0:
+ mnemonic = "LEAVEX";
+ break;
+ case 1:
+ mnemonic = "ENTERX";
+ break;
case 2:
mnemonic = "CLREX";
break;
@@ -2888,6 +2987,9 @@
return t2ev_hint(opcode, address, instruction, cp);
case 0x3b:
return t2ev_misc(opcode, address, instruction, cp);
+ case 0x3c:
+ sprintf(cp, "BXJ\tr%d", (int) (opcode >> 16) & 0x0f);
+ return ERROR_OK;
case 0x3e:
case 0x3f:
sprintf(cp, "MRS\tr%d, %s", (int) (opcode >> 8) & 0x0f,
|
|
From: <ml...@ma...> - 2009-09-07 22:19:37
|
Author: mlu
Date: 2009-09-07 22:19:17 +0200 (Mon, 07 Sep 2009)
New Revision: 2674
Modified:
trunk/src/target/cortex_a8.c
Log:
Improved handling of instruction set state, helps for debugging Thumb state.
Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c 2009-09-04 19:35:10 UTC (rev 2673)
+++ trunk/src/target/cortex_a8.c 2009-09-07 20:19:17 UTC (rev 2674)
@@ -458,7 +458,6 @@
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
swjdp_common_t *swjdp = &armv7a->swjdp_info;
// breakpoint_t *breakpoint = NULL;
@@ -506,7 +505,7 @@
/* Make sure that the Armv7 gdb thumb fixups does not
* kill the return address
*/
- if (!(cortex_a8->cpudbg_dscr & (1 << 5)))
+ if (armv7a->core_state == ARMV7A_STATE_ARM)
{
resume_pc &= 0xFFFFFFFC;
}
@@ -638,7 +637,8 @@
dap_ap_select(swjdp, swjdp_debugap);
LOG_DEBUG("cpsr: %8.8" PRIx32, cpsr);
- armv4_5->core_mode = cpsr & 0x3F;
+ armv4_5->core_mode = cpsr & 0x1F;
+ armv7a->core_state = (cpsr & 0x20)?ARMV7A_STATE_THUMB:ARMV7A_STATE_ARM;
for (i = 0; i <= ARM_PC; i++)
{
@@ -657,8 +657,7 @@
ARMV7A_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
/* Fixup PC Resume Address */
- /* TODO Her we should use arch->core_state */
- if (cortex_a8->cpudbg_dscr & (1 << 5))
+ if (armv7a->core_state == ARMV7A_STATE_THUMB)
{
// T bit set for Thumb or ThumbEE state
regfile[ARM_PC] -= 4;
@@ -743,7 +742,6 @@
/* get pointers to arch-specific information */
armv4_5_common_t *armv4_5 = target->arch_info;
armv7a_common_t *armv7a = armv4_5->arch_info;
- cortex_a8_common_t *cortex_a8 = armv7a->arch_info;
breakpoint_t *breakpoint = NULL;
breakpoint_t stepbreakpoint;
@@ -785,7 +783,7 @@
/* Setup single step breakpoint */
stepbreakpoint.address = address;
- stepbreakpoint.length = (cortex_a8->cpudbg_dscr & (1 << 5)) ? 2 : 4;
+ stepbreakpoint.length = (armv7a->core_state == ARMV7A_STATE_THUMB) ? 2 : 4;
stepbreakpoint.type = BKPT_HARD;
stepbreakpoint.set = 0;
|
|
From: oharboe at B. <oh...@ma...> - 2009-09-04 21:35:12
|
Author: oharboe
Date: 2009-09-04 21:35:10 +0200 (Fri, 04 Sep 2009)
New Revision: 2673
Modified:
trunk/src/target/mips_m4k.c
Log:
Mahr, Stefan <Ste...@sp...> removes the endianness swapping in mips_m4k.c Swapping is already done in target.c
Modified: trunk/src/target/mips_m4k.c
===================================================================
--- trunk/src/target/mips_m4k.c 2009-09-04 11:03:26 UTC (rev 2672)
+++ trunk/src/target/mips_m4k.c 2009-09-04 19:35:10 UTC (rev 2673)
@@ -874,28 +874,6 @@
if (ERROR_OK != retval)
return retval;
- /* TAP data register is loaded LSB first (little endian) */
- if (target->endianness == TARGET_BIG_ENDIAN)
- {
- uint32_t i, t32;
- uint16_t t16;
-
- for (i = 0; i < (count*size); i += size)
- {
- switch (size)
- {
- case 4:
- t32 = le_to_h_u32(&buffer[i]);
- h_u32_to_be(&buffer[i], t32);
- break;
- case 2:
- t16 = le_to_h_u16(&buffer[i]);
- h_u16_to_be(&buffer[i], t16);
- break;
- }
- }
- }
-
return ERROR_OK;
}
@@ -919,28 +897,6 @@
if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
return ERROR_TARGET_UNALIGNED_ACCESS;
- /* TAP data register is loaded LSB first (little endian) */
- if (target->endianness == TARGET_BIG_ENDIAN)
- {
- uint32_t i, t32;
- uint16_t t16;
-
- for (i = 0; i < (count*size); i += size)
- {
- switch (size)
- {
- case 4:
- t32 = be_to_h_u32(&buffer[i]);
- h_u32_to_le(&buffer[i], t32);
- break;
- case 2:
- t16 = be_to_h_u16(&buffer[i]);
- h_u16_to_le(&buffer[i], t16);
- break;
- }
- }
- }
-
/* if noDMA off, use DMAACC mode for memory write */
if (ejtag_info->impcode & EJTAG_IMP_NODMA)
return mips32_pracc_write_mem(ejtag_info, address, size, count, (void *)buffer);
|
|
From: oharboe at B. <oh...@ma...> - 2009-09-04 13:03:30
|
Author: oharboe
Date: 2009-09-04 13:03:26 +0200 (Fri, 04 Sep 2009)
New Revision: 2672
Modified:
trunk/tcl/target/lpc1768.cfg
trunk/tcl/target/lpc2148.cfg
trunk/tcl/target/lpc2378.cfg
Log:
use "armv4_5 core_state arm" instead of soft_reset_halt, fewer side effects
Modified: trunk/tcl/target/lpc1768.cfg
===================================================================
--- trunk/tcl/target/lpc1768.cfg 2009-09-04 08:27:27 UTC (rev 2671)
+++ trunk/tcl/target/lpc1768.cfg 2009-09-04 11:03:26 UTC (rev 2672)
@@ -34,7 +34,8 @@
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x10000000 -work-area-size 0x8000 -work-area-backup 0
$_TARGETNAME configure -event reset-init {
- soft_reset_halt
+ # Force target into ARM state
+ armv4_5 core_state arm
#do not remap 0x0000-0x0020 to anything but the flash
# mwb 0xE01FC040 0x01
mwb 0xE000ED08 0x00
Modified: trunk/tcl/target/lpc2148.cfg
===================================================================
--- trunk/tcl/target/lpc2148.cfg 2009-09-04 08:27:27 UTC (rev 2671)
+++ trunk/tcl/target/lpc2148.cfg 2009-09-04 11:03:26 UTC (rev 2672)
@@ -38,8 +38,8 @@
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
$_TARGETNAME configure -event reset-init {
- # Force target into ARM state.
- soft_reset_halt
+ # Force target into ARM state
+ armv4_5 core_state arm
# Do not remap 0x0000-0x0020 to anything but the flash (i.e. select
# "User Flash Mode" where interrupt vectors are _not_ remapped,
Modified: trunk/tcl/target/lpc2378.cfg
===================================================================
--- trunk/tcl/target/lpc2378.cfg 2009-09-04 08:27:27 UTC (rev 2671)
+++ trunk/tcl/target/lpc2378.cfg 2009-09-04 11:03:26 UTC (rev 2672)
@@ -35,7 +35,7 @@
$_TARGETNAME configure -event reset-init {
# Force target into ARM state
- soft_reset_halt
+ armv4_5 core_state arm
#do not remap 0x0000-0x0020 to anything but the flash
mwb 0xE01FC040 0x01
}
|
|
From: oharboe at B. <oh...@ma...> - 2009-09-04 10:27:32
|
Author: oharboe Date: 2009-09-04 10:27:27 +0200 (Fri, 04 Sep 2009) New Revision: 2671 Modified: trunk/tcl/interface/flyswatter.cfg Log: Dirk Behme <dir...@go...> retire jtag_speed usage Modified: trunk/tcl/interface/flyswatter.cfg =================================================================== --- trunk/tcl/interface/flyswatter.cfg 2009-09-04 08:27:08 UTC (rev 2670) +++ trunk/tcl/interface/flyswatter.cfg 2009-09-04 08:27:27 UTC (rev 2671) @@ -8,5 +8,3 @@ ft2232_device_desc "Flyswatter" ft2232_layout "flyswatter" ft2232_vid_pid 0x0403 0x6010 -jtag_speed 1 - |
|
From: oharboe at B. <oh...@ma...> - 2009-09-04 10:27:12
|
Author: oharboe Date: 2009-09-04 10:27:08 +0200 (Fri, 04 Sep 2009) New Revision: 2670 Modified: trunk/tcl/board/ti_beagleboard.cfg Log: Dirk Behme <dir...@go...> Add default fall back freqency. Modified: trunk/tcl/board/ti_beagleboard.cfg =================================================================== --- trunk/tcl/board/ti_beagleboard.cfg 2009-09-04 08:23:24 UTC (rev 2669) +++ trunk/tcl/board/ti_beagleboard.cfg 2009-09-04 08:27:08 UTC (rev 2670) @@ -1,6 +1,9 @@ # OMAP3 BeagleBoard # http://beagleboard.org +# Fall back to 6MHz if RTCK is not supported +jtag_rclk 6000 + source [find target/omap3530.cfg] # TI-14 JTAG connector |
|
From: oharboe at B. <oh...@ma...> - 2009-09-04 10:23:25
|
Author: oharboe
Date: 2009-09-04 10:23:24 +0200 (Fri, 04 Sep 2009)
New Revision: 2669
Modified:
trunk/tcl/target/lpc2478.cfg
Log:
set ARM mode using explicit command rather than soft_reset_halt which has lots of side effects.
Modified: trunk/tcl/target/lpc2478.cfg
===================================================================
--- trunk/tcl/target/lpc2478.cfg 2009-09-04 08:22:02 UTC (rev 2668)
+++ trunk/tcl/target/lpc2478.cfg 2009-09-04 08:23:24 UTC (rev 2669)
@@ -35,7 +35,7 @@
$_TARGETNAME configure -event reset-init {
# Force target into ARM state
- soft_reset_halt
+ armv4_5 core_state arm
# Do not remap 0x0000-0x0020 to anything but the Flash
mwb 0xE01FC040 0x01
}
|
|
From: oharboe at B. <oh...@ma...> - 2009-09-04 10:22:03
|
Author: oharboe Date: 2009-09-04 10:22:02 +0200 (Fri, 04 Sep 2009) New Revision: 2668 Modified: trunk/src/target/cortex_a8.c Log: Matt Hsu <ma...@0x...> This patch simply enables the halting debug mode. By enabling this bit, the processor halts when a debug event such as breakpoint occurs. Modified: trunk/src/target/cortex_a8.c =================================================================== --- trunk/src/target/cortex_a8.c 2009-09-04 08:21:18 UTC (rev 2667) +++ trunk/src/target/cortex_a8.c 2009-09-04 08:22:02 UTC (rev 2668) @@ -430,6 +430,13 @@ retval = mem_ap_write_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x1); + /* + * enter halting debug mode + */ + mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr); + retval = mem_ap_write_atomic_u32(swjdp, + OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE)); + if (retval != ERROR_OK) goto out; |
|
From: oharboe at B. <oh...@ma...> - 2009-09-04 10:21:20
|
Author: oharboe
Date: 2009-09-04 10:21:18 +0200 (Fri, 04 Sep 2009)
New Revision: 2667
Modified:
trunk/src/target/arm7_9_common.c
Log:
more debug output for breakpoints
Modified: trunk/src/target/arm7_9_common.c
===================================================================
--- trunk/src/target/arm7_9_common.c 2009-09-04 05:20:45 UTC (rev 2666)
+++ trunk/src/target/arm7_9_common.c 2009-09-04 08:21:18 UTC (rev 2667)
@@ -228,9 +228,10 @@
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
int retval = ERROR_OK;
- LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32,
+ LOG_DEBUG("BPID: %d, Address: 0x%08" PRIx32 ", Type: %d" ,
breakpoint->unique_id,
- breakpoint->address );
+ breakpoint->address,
+ breakpoint->type);
if (target->state != TARGET_HALTED)
{
@@ -1187,6 +1188,13 @@
int i;
int retval;
+ /* FIX!!! replace some of this code with tcl commands
+ *
+ * halt # the halt command is synchronous
+ * armv4_5 core_state arm
+ *
+ */
+
if ((retval = target_halt(target)) != ERROR_OK)
return retval;
|
|
From: oharboe at B. <oh...@ma...> - 2009-09-04 07:20:48
|
Author: oharboe
Date: 2009-09-04 07:20:45 +0200 (Fri, 04 Sep 2009)
New Revision: 2666
Modified:
trunk/src/target/cortex_a8.c
trunk/src/target/cortex_a8.h
Log:
Matt Hsu <ma...@0x...> Tidy up the bit-offset operation for DSCR register
Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c 2009-09-04 05:17:03 UTC (rev 2665)
+++ trunk/src/target/cortex_a8.c 2009-09-04 05:20:45 UTC (rev 2666)
@@ -166,7 +166,7 @@
retvalue = mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
}
- while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+ while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
@@ -175,7 +175,7 @@
retvalue = mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
}
- while ((dscr & (1 << 24)) == 0); /* Wait for InstrCompl bit to be set */
+ while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
return retvalue;
}
@@ -291,7 +291,7 @@
retval = mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
}
- while ((dscr & (1 << 29)) == 0); /* Wait for DTRRXfull */
+ while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0); /* Wait for DTRRXfull */
retval = mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
@@ -436,7 +436,7 @@
do {
mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
- } while ((dscr & (1 << 0)) == 0);
+ } while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
target->debug_reason = DBG_REASON_DBGRQ;
@@ -535,7 +535,7 @@
do {
mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
- } while ((dscr & (1 << 1)) == 0);
+ } while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
target->debug_reason = DBG_REASON_NOTHALTED;
target->state = TARGET_RUNNING;
@@ -582,7 +582,7 @@
/* Enable the ITR execution once we are in debug mode */
mem_ap_read_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
- dscr |= (1 << 13);
+ dscr |= (1 << DSCR_EXT_INT_EN);
retval = mem_ap_write_atomic_u32(swjdp,
OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
Modified: trunk/src/target/cortex_a8.h
===================================================================
--- trunk/src/target/cortex_a8.h 2009-09-04 05:17:03 UTC (rev 2665)
+++ trunk/src/target/cortex_a8.h 2009-09-04 05:20:45 UTC (rev 2666)
@@ -67,6 +67,15 @@
#define BRP_NORMAL 0
#define BRP_CONTEXT 1
+/* DSCR Bit offset */
+#define DSCR_CORE_HALTED 0
+#define DSCR_CORE_RESTARTED 1
+#define DSCR_EXT_INT_EN 13
+#define DSCR_HALT_DBG_MODE 14
+#define DSCR_MON_DBG_MODE 15
+#define DSCR_INSTR_COMP 24
+#define DSCR_DTR_TX_FULL 29
+
typedef struct cortex_a8_brp_s
{
int used;
|
|
From: oharboe at B. <oh...@ma...> - 2009-09-04 07:17:09
|
Author: oharboe
Date: 2009-09-04 07:17:03 +0200 (Fri, 04 Sep 2009)
New Revision: 2665
Modified:
trunk/tcl/target/aduc702x.cfg
trunk/tcl/target/at91eb40a.cfg
trunk/tcl/target/at91r40008.cfg
trunk/tcl/target/at91sam3uXX.cfg
trunk/tcl/target/at91sam7sx.cfg
trunk/tcl/target/at91sam9260.cfg
trunk/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
trunk/tcl/target/c100.cfg
trunk/tcl/target/cs351x.cfg
trunk/tcl/target/epc9301.cfg
trunk/tcl/target/feroceon.cfg
trunk/tcl/target/imx21.cfg
trunk/tcl/target/imx27.cfg
trunk/tcl/target/imx31.cfg
trunk/tcl/target/imx35.cfg
trunk/tcl/target/is5114.cfg
trunk/tcl/target/ixp42x.cfg
trunk/tcl/target/lpc1768.cfg
trunk/tcl/target/lpc2103.cfg
trunk/tcl/target/lpc2124.cfg
trunk/tcl/target/lpc2129.cfg
trunk/tcl/target/lpc2148.cfg
trunk/tcl/target/lpc2294.cfg
trunk/tcl/target/lpc2378.cfg
trunk/tcl/target/lpc2478.cfg
trunk/tcl/target/mega128.cfg
trunk/tcl/target/netx500.cfg
trunk/tcl/target/pic32mx.cfg
trunk/tcl/target/pxa270.cfg
trunk/tcl/target/sam7se512.cfg
trunk/tcl/target/sam7x256.cfg
trunk/tcl/target/samsung_s3c2410.cfg
trunk/tcl/target/samsung_s3c2440.cfg
trunk/tcl/target/samsung_s3c2450.cfg
trunk/tcl/target/samsung_s3c4510.cfg
trunk/tcl/target/samsung_s3c6410.cfg
trunk/tcl/target/sharp_lh79532.cfg
trunk/tcl/target/smp8634.cfg
trunk/tcl/target/stm32.cfg
trunk/tcl/target/str710.cfg
trunk/tcl/target/str730.cfg
trunk/tcl/target/str750.cfg
trunk/tcl/target/str912.cfg
trunk/tcl/target/test_reset_syntax_error.cfg
trunk/tcl/target/xba_revA3.cfg
Log:
David Brownell <da...@pa...> "set _TARGETNAME ..." cleanup
Modified: trunk/tcl/target/aduc702x.cfg
===================================================================
--- trunk/tcl/target/aduc702x.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/aduc702x.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -36,7 +36,7 @@
##
## Target configuration
##
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
# allocate the entire SRAM as working area
Modified: trunk/tcl/target/at91eb40a.cfg
===================================================================
--- trunk/tcl/target/at91eb40a.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/at91eb40a.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -34,7 +34,7 @@
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
#target configuration
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
# speed up memory downloads
Modified: trunk/tcl/target/at91r40008.cfg
===================================================================
--- trunk/tcl/target/at91r40008.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/at91r40008.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -28,7 +28,8 @@
#jtag scan chain
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
Modified: trunk/tcl/target/at91sam3uXX.cfg
===================================================================
--- trunk/tcl/target/at91sam3uXX.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/at91sam3uXX.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -29,7 +29,7 @@
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
# 16K is plenty, the smallest chip has this much
Modified: trunk/tcl/target/at91sam7sx.cfg
===================================================================
--- trunk/tcl/target/at91sam7sx.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/at91sam7sx.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -21,7 +21,7 @@
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
$_TARGETNAME configure -event reset-init {
Modified: trunk/tcl/target/at91sam9260.cfg
===================================================================
--- trunk/tcl/target/at91sam9260.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/at91sam9260.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -35,7 +35,7 @@
# Target configuration
######################
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
# Internal sram1 memory
Modified: trunk/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
===================================================================
--- trunk/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -41,7 +41,7 @@
# Target configuration
######################
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
$_TARGETNAME invoke-event halted
Modified: trunk/tcl/target/c100.cfg
===================================================================
--- trunk/tcl/target/c100.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/c100.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -36,7 +36,7 @@
# Per ARM: DDI0211J_arm1136_r1p5_trm.pdf - the ARM 1136 as a 5 bit IR register
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
# C100's ARAM 64k SRAM
Modified: trunk/tcl/target/cs351x.cfg
===================================================================
--- trunk/tcl/target/cs351x.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/cs351x.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -19,8 +19,9 @@
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
# Create the GDB Target.
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME fa526 -endian $_ENDIAN -chain-position $_TARGETNAME -variant fa526
+
# There is 16K of SRAM on this chip
# FIXME: flash programming is not working by using this work area. So comment this out for now.
#$_TARGETNAME configure -work-area-virt 0x00000000 -work-area-phys 0x00000000 -work-area-size 0x4000 -work-area-backup 1
Modified: trunk/tcl/target/epc9301.cfg
===================================================================
--- trunk/tcl/target/epc9301.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/epc9301.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -23,7 +23,7 @@
jtag_nsrst_delay 100
jtag_ntrst_delay 100
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -work-area-virt 0 -work-area-phys 0x80014000 -work-area-size 0x1000 -work-area-backup 1
#flash configuration
Modified: trunk/tcl/target/feroceon.cfg
===================================================================
--- trunk/tcl/target/feroceon.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/feroceon.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -21,7 +21,8 @@
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME feroceon -endian $_ENDIAN -chain-position $_TARGETNAME
reset_config trst_and_srst
Modified: trunk/tcl/target/imx21.cfg
===================================================================
--- trunk/tcl/target/imx21.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/imx21.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -28,7 +28,7 @@
# Create the GDB Target.
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
arm7_9 dcc_downloads enable
Modified: trunk/tcl/target/imx27.cfg
===================================================================
--- trunk/tcl/target/imx27.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/imx27.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -38,7 +38,7 @@
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
# Create the GDB Target.
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
$_TARGETNAME configure -work-area-virt 0xffff4c00 -work-area-phys 0xffff4c00 -work-area-size 0x8000 -work-area-backup 1
# Internal to the chip, there is 45K of SRAM
Modified: trunk/tcl/target/imx31.cfg
===================================================================
--- trunk/tcl/target/imx31.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/imx31.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -54,7 +54,7 @@
# But this conflicts with Diagram 6-13, "3bits ir and drs"
jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
Modified: trunk/tcl/target/imx35.cfg
===================================================================
--- trunk/tcl/target/imx35.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/imx35.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -43,7 +43,7 @@
jtag newtap $_CHIPNAME smda -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_SDMATAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
proc power_restore {} { puts "Sensed power restore. No action." }
Modified: trunk/tcl/target/is5114.cfg
===================================================================
--- trunk/tcl/target/is5114.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/is5114.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -38,7 +38,7 @@
#arm946e-s and
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
Modified: trunk/tcl/target/ixp42x.cfg
===================================================================
--- trunk/tcl/target/ixp42x.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/ixp42x.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -27,6 +27,6 @@
jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ixp42x
Modified: trunk/tcl/target/lpc1768.cfg
===================================================================
--- trunk/tcl/target/lpc1768.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/lpc1768.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -27,7 +27,7 @@
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
# LPC1768 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
Modified: trunk/tcl/target/lpc2103.cfg
===================================================================
--- trunk/tcl/target/lpc2103.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/lpc2103.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -27,8 +27,7 @@
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
# 8kB of internal SRAM
Modified: trunk/tcl/target/lpc2124.cfg
===================================================================
--- trunk/tcl/target/lpc2124.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/lpc2124.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -32,7 +32,7 @@
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
Modified: trunk/tcl/target/lpc2129.cfg
===================================================================
--- trunk/tcl/target/lpc2129.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/lpc2129.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -32,7 +32,7 @@
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
Modified: trunk/tcl/target/lpc2148.cfg
===================================================================
--- trunk/tcl/target/lpc2148.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/lpc2148.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -32,8 +32,7 @@
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
Modified: trunk/tcl/target/lpc2294.cfg
===================================================================
--- trunk/tcl/target/lpc2294.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/lpc2294.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -26,7 +26,7 @@
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x40000000 -work-area-size 0x4000 -work-area-backup 0
Modified: trunk/tcl/target/lpc2378.cfg
===================================================================
--- trunk/tcl/target/lpc2378.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/lpc2378.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -27,7 +27,7 @@
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
# LPC2378 has 32kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
Modified: trunk/tcl/target/lpc2478.cfg
===================================================================
--- trunk/tcl/target/lpc2478.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/lpc2478.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -27,7 +27,7 @@
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
# LPC2478 has 64kB of SRAM on its main system bus (so-called Local On-Chip SRAM)
Modified: trunk/tcl/target/mega128.cfg
===================================================================
--- trunk/tcl/target/mega128.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/mega128.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -17,7 +17,7 @@
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
#$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
Modified: trunk/tcl/target/netx500.cfg
===================================================================
--- trunk/tcl/target/netx500.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/netx500.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -29,6 +29,6 @@
jtag_nsrst_delay 100
jtag_ntrst_delay 100
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
Modified: trunk/tcl/target/pic32mx.cfg
===================================================================
--- trunk/tcl/target/pic32mx.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/pic32mx.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -28,7 +28,7 @@
#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0xa0000000 -work-area-size 16384 -work-area-backup 0
Modified: trunk/tcl/target/pxa270.cfg
===================================================================
--- trunk/tcl/target/pxa270.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/pxa270.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -30,7 +30,7 @@
# the rest of the needed delays are built into the openocd program
jtag_ntrst_delay 0
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa27x
Modified: trunk/tcl/target/sam7se512.cfg
===================================================================
--- trunk/tcl/target/sam7se512.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/sam7se512.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -29,7 +29,7 @@
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
# The target
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0
Modified: trunk/tcl/target/sam7x256.cfg
===================================================================
--- trunk/tcl/target/sam7x256.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/sam7x256.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -21,9 +21,9 @@
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
$_TARGETNAME configure -event reset-init {
# disable watchdog
mww 0xfffffd44 0x00008000
Modified: trunk/tcl/target/samsung_s3c2410.cfg
===================================================================
--- trunk/tcl/target/samsung_s3c2410.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/samsung_s3c2410.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -25,7 +25,7 @@
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm920t
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x30800000 -work-area-size 0x20000 -work-area-backup 0
Modified: trunk/tcl/target/samsung_s3c2440.cfg
===================================================================
--- trunk/tcl/target/samsung_s3c2440.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/samsung_s3c2440.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -26,8 +26,9 @@
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm920t
+
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x200000 -work-area-size 0x4000 -work-area-backup 1
#reset configuration
Modified: trunk/tcl/target/samsung_s3c2450.cfg
===================================================================
--- trunk/tcl/target/samsung_s3c2450.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/samsung_s3c2450.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -36,7 +36,7 @@
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0xE -irmask 0x0f -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
# FIX!!!!! should this really use srst_pulls_trst?
@@ -46,4 +46,4 @@
# However, without "srst_pulls_trst", then "reset halt" produces weird
# errors:
# WARNING: unknown debug reason: 0x0
-reset_config trst_and_srst
\ No newline at end of file
+reset_config trst_and_srst
Modified: trunk/tcl/target/samsung_s3c4510.cfg
===================================================================
--- trunk/tcl/target/samsung_s3c4510.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/samsung_s3c4510.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -20,6 +20,6 @@
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
Modified: trunk/tcl/target/samsung_s3c6410.cfg
===================================================================
--- trunk/tcl/target/samsung_s3c6410.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/samsung_s3c6410.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -39,7 +39,7 @@
jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0xe -expected-id $_BSTAPID
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm1176
jtag_nsrst_delay 500
Modified: trunk/tcl/target/sharp_lh79532.cfg
===================================================================
--- trunk/tcl/target/sharp_lh79532.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/sharp_lh79532.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -20,7 +20,7 @@
}
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME
Modified: trunk/tcl/target/smp8634.cfg
===================================================================
--- trunk/tcl/target/smp8634.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/smp8634.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -28,5 +28,5 @@
# format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME mips_m4k -endian $_ENDIAN -variant
Modified: trunk/tcl/target/stm32.cfg
===================================================================
--- trunk/tcl/target/stm32.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/stm32.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -57,7 +57,7 @@
}
jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 -expected-id $_BSTAPID3 -expected-id $_BSTAPID4 -expected-id $_BSTAPID5
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
Modified: trunk/tcl/target/str710.cfg
===================================================================
--- trunk/tcl/target/str710.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/str710.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -26,8 +26,9 @@
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0x0f -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
+
$_TARGETNAME configure -event reset-start { jtag_khz 10 }
$_TARGETNAME configure -event reset-init { jtag_khz 6000 }
$_TARGETNAME configure -event gdb-flash-erase-start {
Modified: trunk/tcl/target/str730.cfg
===================================================================
--- trunk/tcl/target/str730.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/str730.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -31,8 +31,9 @@
jtag_nsrst_delay 500
jtag_ntrst_delay 500
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
+
$_TARGETNAME configure -event reset-start { jtag_khz 10 }
$_TARGETNAME configure -event reset-init { jtag_khz 3000 }
$_TARGETNAME configure -event gdb-flash-erase-start {
Modified: trunk/tcl/target/str750.cfg
===================================================================
--- trunk/tcl/target/str750.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/str750.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -33,7 +33,7 @@
jtag_nsrst_delay 500
jtag_ntrst_delay 500
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
$_TARGETNAME configure -event reset-start { jtag_khz 10 }
Modified: trunk/tcl/target/str912.cfg
===================================================================
--- trunk/tcl/target/str912.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/str912.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -43,7 +43,7 @@
}
jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
$_TARGETNAME configure -event reset-start { jtag_rclk 16 }
Modified: trunk/tcl/target/test_reset_syntax_error.cfg
===================================================================
--- trunk/tcl/target/test_reset_syntax_error.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/test_reset_syntax_error.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -8,7 +8,7 @@
jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf
#target configuration
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
$_TARGETNAME configure -event reset-init {
Modified: trunk/tcl/target/xba_revA3.cfg
===================================================================
--- trunk/tcl/target/xba_revA3.cfg 2009-09-04 05:14:32 UTC (rev 2664)
+++ trunk/tcl/target/xba_revA3.cfg 2009-09-04 05:17:03 UTC (rev 2665)
@@ -28,8 +28,9 @@
#jtag scan chain
jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant ixp42x
+
$_TARGETNAME configure -event reset-init {
#############################################################################
# setup expansion bus CS, disable external wdt
|
