openocd-commit — OpenOCD commit maling list - read only

[Openocd-svn] r2714 - trunk/src/target

[<ml...@ma...>]

Author: mlu
Date: 2009-09-15 18:20:39 +0200 (Tue, 15 Sep 2009)
New Revision: 2714

Modified:
   trunk/src/target/armv7a.h
Log:
Define debug_base, debug_ap, memory_ap in armv7a_common_t

Modified: trunk/src/target/armv7a.h
===================================================================
--- trunk/src/target/armv7a.h	2009-09-15 15:50:09 UTC (rev 2713)
+++ trunk/src/target/armv7a.h	2009-09-15 16:20:39 UTC (rev 2714)
@@ -98,6 +98,13 @@
 
 	/* arm adp debug port */
 	swjdp_common_t swjdp_info;
+
+	/* Core Debug Unit */
+	uint32_t debug_base;
+	uint8_t debug_ap;
+	uint8_t memory_ap;
+
+	/* Cache and Memory Management Unit */
 	armv4_5_mmu_common_t armv4_5_mmu;
 	armv4_5_common_t armv4_5_common;
 	void *arch_info;

[Openocd-svn] r2713 - trunk/src/target

[<ml...@ma...>]

Author: mlu
Date: 2009-09-15 17:50:09 +0200 (Tue, 15 Sep 2009)
New Revision: 2713

Modified:
   trunk/src/target/armv7a.c
Log:
Updated mode string list.

Modified: trunk/src/target/armv7a.c
===================================================================
--- trunk/src/target/armv7a.c	2009-09-15 15:41:14 UTC (rev 2712)
+++ trunk/src/target/armv7a.c	2009-09-15 15:50:09 UTC (rev 2713)
@@ -70,8 +70,8 @@
 
 char * armv7a_mode_strings_list[] =
 {
-	"Illegal mode value", "System and User", "FIQ", "IRQ",
-	"Supervisor", "Abort", "Undefined", "Monitor"
+	"Illegal mode value", "User", "FIQ", "IRQ",
+	"Supervisor", "Abort", "Undefined", "System", "Monitor"
 };
 
 /* Hack! Yuk! allow -1 index, which simplifies codepaths elsewhere in the code */

[Openocd-svn] r2712 - trunk/src/target

[<ml...@ma...>]

Author: mlu
Date: 2009-09-15 17:41:14 +0200 (Tue, 15 Sep 2009)
New Revision: 2712

Modified:
   trunk/src/target/armv7a.h
Log:
Definy symbolic values for VA to PA address translation operations

Modified: trunk/src/target/armv7a.h
===================================================================
--- trunk/src/target/armv7a.h	2009-09-15 14:20:37 UTC (rev 2711)
+++ trunk/src/target/armv7a.h	2009-09-15 15:41:14 UTC (rev 2712)
@@ -79,6 +79,16 @@
 #define ARMV4_5_COMMON_MAGIC 0x0A450A45
 #define ARMV7_COMMON_MAGIC 0x0A450999
 
+/* VA to PA translation operations opc2 values*/
+#define V2PCWPR  0
+#define V2PCWPW  1
+#define V2PCWUR  2
+#define V2PCWUW  3
+#define V2POWPR  4
+#define V2POWPW  5
+#define V2POWUR  6
+#define V2POWUW  7
+
 typedef struct armv7a_common_s
 {
 	int common_magic;

[Openocd-svn] r2711 - trunk/src/server

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-15 16:20:37 +0200 (Tue, 15 Sep 2009)
New Revision: 2711

Modified:
   trunk/src/server/httpd.c
Log:
fix bug when using 32 instead of 64 bit value in callback, caught by -Wall

Modified: trunk/src/server/httpd.c
===================================================================
--- trunk/src/server/httpd.c	2009-09-15 09:41:09 UTC (rev 2710)
+++ trunk/src/server/httpd.c	2009-09-15 14:20:37 UTC (rev 2711)
@@ -223,7 +223,7 @@
 /* append data to each key */
 static int iterate_post(void *con_cls, enum MHD_ValueKind kind,
 		const char *key, const char *filename, const char *content_type,
-		const char *transfer_encoding, const char *data, size_t off,
+		const char *transfer_encoding, const char *data, uint64_t off,
 		size_t size)
 {
 	struct httpd_request *r = (struct httpd_request*) con_cls;

[Openocd-svn] r2710 - trunk

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-15 11:41:09 +0200 (Tue, 15 Sep 2009)
New Revision: 2710

Modified:
   trunk/TODO
Log:
added embedded ice programming while srst is asserted todo item

Modified: trunk/TODO
===================================================================
--- trunk/TODO	2009-09-14 22:41:47 UTC (rev 2709)
+++ trunk/TODO	2009-09-15 09:41:09 UTC (rev 2710)
@@ -114,6 +114,10 @@
   https://lists.berlios.de/pipermail/openocd-development/2009-July/009426.html
 - regression: "reset halt" between 729(works) and 788(fails): @par
 https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
+- ARM7/9:
+  - add reset option to allow programming embedded ice while srst is asserted.
+  Some CPUs will gate the JTAG clock when srst is asserted and in this case,
+  it is necessary to program embedded ice and then assert srst afterwards.
 - ARM923EJS:
   - reset run/halt/step is not robust; needs testing to map out problems.
 - ARM11 improvements (MB?)

[Openocd-svn] r2709 - trunk/src/target

[<ml...@ma...>]

Author: mlu
Date: 2009-09-15 00:41:47 +0200 (Tue, 15 Sep 2009)
New Revision: 2709

Modified:
   trunk/src/target/cortex_a8.c
Log:
Check return values to avoid infinite wait in loop on error.

Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-09-14 22:36:27 UTC (rev 2708)
+++ trunk/src/target/cortex_a8.c	2009-09-14 22:41:47 UTC (rev 2709)
@@ -153,7 +153,7 @@
 int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
 {
 	uint32_t dscr;
-	int retvalue;
+	int retval;
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	armv7a_common_t *armv7a = armv4_5->arch_info;
@@ -162,8 +162,10 @@
 	LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
 	do
 	{
-		retvalue = mem_ap_read_atomic_u32(swjdp,
+		retval = mem_ap_read_atomic_u32(swjdp,
 				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+		if (retval != ERROR_OK)
+			return retval;
 	}
 	while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
@@ -171,12 +173,14 @@
 
 	do
 	{
-		retvalue = mem_ap_read_atomic_u32(swjdp,
+		retval = mem_ap_read_atomic_u32(swjdp,
 				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+		if (retval != ERROR_OK)
+			return retval;
 	}
 	while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
-	return retvalue;
+	return retval;
 }
 
 /**************************************************************************

[Openocd-svn] r2708 - trunk/src/target

[<ml...@ma...>]

Author: mlu
Date: 2009-09-15 00:36:27 +0200 (Tue, 15 Sep 2009)
New Revision: 2708

Modified:
   trunk/src/target/cortex_a8.c
Log:
Cache invalidation when writing to memory

Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-09-14 13:54:49 UTC (rev 2707)
+++ trunk/src/target/cortex_a8.c	2009-09-14 22:36:27 UTC (rev 2708)
@@ -1253,6 +1253,24 @@
 			exit(-1);
 	}
 
+	/* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
+	/* invalidate I-Cache */
+	if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
+	{
+		/* Invalidate ICache single entry with MVA, repeat this for all cache
+		   lines in the address range, Cortex-A8 has fixed 64 byte line length */
+		/* Invalidate Cache single entry with MVA to PoU */
+		for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
+			armv7a->write_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */
+	}
+	/* invalidate D-Cache */
+	if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
+	{
+		/* Invalidate Cache single entry with MVA to PoC */
+		for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
+			armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */
+	}
+
 	return retval;
 }
 

[Openocd-svn] r2707 - trunk/src/helper

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-14 15:54:49 +0200 (Mon, 14 Sep 2009)
New Revision: 2707

Modified:
   trunk/src/helper/startup.tcl
Log:
error message upon recursive invocation of reset from reset event handlers

Modified: trunk/src/helper/startup.tcl
===================================================================
--- trunk/src/helper/startup.tcl	2009-09-14 08:03:57 UTC (rev 2706)
+++ trunk/src/helper/startup.tcl	2009-09-14 13:54:49 UTC (rev 2707)
@@ -134,8 +134,30 @@
 	reset halt
 }
 
+global in_process_reset
+set in_process_reset 0
+
+# Catch reset recursion
 proc ocd_process_reset { MODE } {
+	global in_process_reset
+	if {$in_process_reset} {
+		set in_process_reset 0
+		return -code error "'reset' can not be invoked recursively"
+	}
+	
+	set in_process_reset 1
+	set success [expr [catch {ocd_process_reset_inner $MODE} result]==0] 
+	set in_process_reset 0
+	
+	if {$success} {
+		return $result
+	} else {
+		return -code error $result
+	}
+}
 
+proc ocd_process_reset_inner { MODE } {
+
 	# If this target must be halted...
 	set halt -1
 	if { 0 == [string compare $MODE halt] } {

[Openocd-svn] r2706 - trunk/src/flash

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-14 10:03:57 +0200 (Mon, 14 Sep 2009)
New Revision: 2706

Modified:
   trunk/src/flash/nand_ecc_kw.c
Log:
fix email address

Modified: trunk/src/flash/nand_ecc_kw.c
===================================================================
--- trunk/src/flash/nand_ecc_kw.c	2009-09-14 07:48:28 UTC (rev 2705)
+++ trunk/src/flash/nand_ecc_kw.c	2009-09-14 08:03:57 UTC (rev 2706)
@@ -3,7 +3,7 @@
  * Copyright (C) 2009 Marvell Semiconductor, Inc.
  *
  * Authors: Lennert Buytenhek <bu...@wa...>
- *          Nicolas Pitre <ni...@ca...>
+ *          Nicolas Pitre <ni...@fl...>
  *
  * This file is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License as published by the

[Openocd-svn] r2705 - trunk/src/flash

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-14 09:48:28 +0200 (Mon, 14 Sep 2009)
New Revision: 2705

Modified:
   trunk/src/flash/cfi.c
Log:
Rolf Meeser <rol...@ya...> warning fix in previous commit was wrong. target_code_size needs the real value later.

Modified: trunk/src/flash/cfi.c
===================================================================
--- trunk/src/flash/cfi.c	2009-09-14 06:06:35 UTC (rev 2704)
+++ trunk/src/flash/cfi.c	2009-09-14 07:48:28 UTC (rev 2705)
@@ -1125,12 +1125,12 @@
 	armv4_5_info.core_state = ARMV4_5_STATE_ARM;
 
 	/* If we are setting up the write_algorith, we need target_code_src */
-	/* if not we only need target_code_size.														*/
-	/* 																																	*/
-	/* However, we don't want to create multiple code paths, so we			*/
-	/* do the unecessary evaluation of target_code_src, which the 			*/
-	/* compiler will probably nicely optimize away if not needed				*/
+	/* if not we only need target_code_size. */
 
+	/* However, we don't want to create multiple code paths, so we */
+	/* do the unecessary evaluation of target_code_src, which the */
+	/* compiler will probably nicely optimize away if not needed */
+
 	/* prepare algorithm code for target endian */
 	switch (bank->bus_width)
 	{
@@ -1447,44 +1447,46 @@
 	armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
 	armv4_5_info.core_state = ARMV4_5_STATE_ARM;
 
+	int target_code_size;
+	const uint32_t *target_code_src;
+
+	switch (bank->bus_width)
+	{
+	case 1 :
+		target_code_src = word_8_code;
+		target_code_size = sizeof(word_8_code);
+		break;
+	case 2 :
+		/* Check for DQ5 support */
+		if( cfi_info->status_poll_mask & (1 << 5) )
+		{
+			target_code_src = word_16_code;
+			target_code_size = sizeof(word_16_code);
+		}
+		else
+		{
+			/* No DQ5 support. Use DQ7 DATA# polling only. */
+			target_code_src = word_16_code_dq7only;
+			target_code_size = sizeof(word_16_code_dq7only);
+		}
+		break;
+	case 4 :
+		target_code_src = word_32_code;
+		target_code_size = sizeof(word_32_code);
+		break;
+	default:
+		LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
+		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+	}
+
 	/* flash write code */
-	int target_code_size = 0;
 	if (!cfi_info->write_algorithm)
 	{
 		uint8_t *target_code;
-		const uint32_t *src;
 
 		/* convert bus-width dependent algorithm code to correct endiannes */
-		switch (bank->bus_width)
-		{
-		case 1:
-			src = word_8_code;
-			target_code_size = sizeof(word_8_code);
-			break;
-		case 2:
-			/* Check for DQ5 support */
-			if( cfi_info->status_poll_mask & (1 << 5) )
-			{
-				src = word_16_code;
-				target_code_size = sizeof(word_16_code);
-			}
-			else
-			{
-				/* No DQ5 support. Use DQ7 DATA# polling only. */
-				src = word_16_code_dq7only;
-				target_code_size = sizeof(word_16_code_dq7only);
-			}
-			break;
-		case 4:
-			src = word_32_code;
-			target_code_size = sizeof(word_32_code);
-			break;
-		default:
-			LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes", bank->bus_width);
-			return ERROR_FLASH_OPERATION_FAILED;
-		}
 		target_code = malloc(target_code_size);
-		cfi_fix_code_endian(target, target_code, src, target_code_size / 4);
+		cfi_fix_code_endian(target, target_code, target_code_src, target_code_size / 4);
 
 		/* allocate working area */
 		retval = target_alloc_working_area(target, target_code_size,

[Openocd-svn] r2704 - trunk/src/flash

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-14 08:06:35 +0200 (Mon, 14 Sep 2009)
New Revision: 2704

Modified:
   trunk/src/flash/cfi.c
Log:
fix warning

Modified: trunk/src/flash/cfi.c
===================================================================
--- trunk/src/flash/cfi.c	2009-09-13 20:07:13 UTC (rev 2703)
+++ trunk/src/flash/cfi.c	2009-09-14 06:06:35 UTC (rev 2704)
@@ -1448,7 +1448,7 @@
 	armv4_5_info.core_state = ARMV4_5_STATE_ARM;
 
 	/* flash write code */
-	int target_code_size;
+	int target_code_size = 0;
 	if (!cfi_info->write_algorithm)
 	{
 		uint8_t *target_code;

[Openocd-svn] r2703 - trunk/tcl/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-13 22:07:13 +0200 (Sun, 13 Sep 2009)
New Revision: 2703

Modified:
   trunk/tcl/target/omap3530.cfg
Log:
Magnus Lundin <lu...@ml...> Disable poll while core register initialization

Modified: trunk/tcl/target/omap3530.cfg
===================================================================
--- trunk/tcl/target/omap3530.cfg	2009-09-13 17:26:07 UTC (rev 2702)
+++ trunk/tcl/target/omap3530.cfg	2009-09-13 20:07:13 UTC (rev 2703)
@@ -41,6 +41,7 @@
 
 # FIXME much of this should be in reset event handlers
 proc omap3_dbginit { } {
+     poll off
      reset
      sleep 500
 
@@ -65,4 +66,5 @@
      # omap3.cpu mdw 0x54011080
 
      omap3.cpu mww 0x5401d030 0x00002000
+     poll on
 }

[Openocd-svn] r2702 - trunk/src/target

[<ml...@ma...>]

Author: mlu
Date: 2009-09-13 19:26:07 +0200 (Sun, 13 Sep 2009)
New Revision: 2702

Modified:
   trunk/src/target/cortex_a8.h
Log:
More CortexA8 debug register definitions.

Modified: trunk/src/target/cortex_a8.h
===================================================================
--- trunk/src/target/cortex_a8.h	2009-09-13 13:57:50 UTC (rev 2701)
+++ trunk/src/target/cortex_a8.h	2009-09-13 17:26:07 UTC (rev 2702)
@@ -43,6 +43,7 @@
 #define CPUDBG_DIDR		0x000
 #define CPUDBG_WFAR		0x018
 #define CPUDBG_VCR	0x01C
+#define CPUDBG_ECR	0x024
 #define CPUDBG_DSCCR	0x028
 #define CPUDBG_DTRRX	0x080
 #define CPUDBG_ITR	0x084
@@ -63,6 +64,9 @@
 #define CPUDBG_CPUID	0xD00
 #define CPUDBG_CTYPR	0xD04
 #define CPUDBG_TTYPR	0xD0C
+#define CPUDBG_LOCKACCESS 0xFB0
+#define CPUDBG_LOCKSTATUS 0xFB4
+#define CPUDBG_AUTHSTATUS 0xFB8
 
 #define BRP_NORMAL 0
 #define BRP_CONTEXT 1

[Openocd-svn] r2701 - trunk/src/target

[<ml...@ma...>]

Author: mlu
Date: 2009-09-13 15:57:50 +0200 (Sun, 13 Sep 2009)
New Revision: 2701

Modified:
   trunk/src/target/cortex_a8.c
Log:
Fix argument passing in cortex_a8_write_cp.

Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-09-12 13:05:20 UTC (rev 2700)
+++ trunk/src/target/cortex_a8.c	2009-09-13 13:57:50 UTC (rev 2701)
@@ -224,7 +224,6 @@
 
 int cortex_a8_write_cp(target_t *target, uint32_t value,
 	uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
-/* TODO Fix this */
 {
 	int retval;
 	/* get pointers to arch-specific information */
@@ -237,7 +236,7 @@
 	/* Move DTRRX to r0 */
 	cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
 
-	cortex_a8_exec_opcode(target, ARMV4_5_MCR(CP, 0, 0, 0, 5, 0));
+	cortex_a8_exec_opcode(target, ARMV4_5_MCR(CP, op1, 0, CRn, CRm, op2));
 	return retval;
 }
 

[Openocd-svn] r2700 - trunk/doc

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-12 15:05:20 +0200 (Sat, 12 Sep 2009)
New Revision: 2700

Modified:
   trunk/doc/openocd.texi
Log:
Dirk Behme <dir...@go...> document post TAP reset event

Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-09-12 08:11:45 UTC (rev 2699)
+++ trunk/doc/openocd.texi	2009-09-12 13:05:20 UTC (rev 2700)
@@ -2289,14 +2289,14 @@
 
 @deffn Command {jtag cget} dotted.name @option{-event} name
 @deffnx Command {jtag configure} dotted.name @option{-event} name string
-At this writing this mechanism is used only for event handling,
-and the only two events relate to TAP enabling and disabling.
+At this writing this mechanism is used only for event handling.
+Three events are available. Two events relate to TAP enabling
+and disabling, one to post reset handling.
 
 The @code{configure} subcommand assigns an event handler,
 a TCL string which is evaluated when the event is triggered.
 The @code{cget} subcommand returns that handler.
-The two possible values for an event @var{name}
-are @option{tap-disable} and @option{tap-enable}.
+The three possible values for an event @var{name} are @option{tap-disable}, @option{tap-enable} and @option{post-reset}.
 
 So for example, when defining a TAP for a CPU connected to
 a JTAG router, you should define TAP event handlers using
@@ -2312,6 +2312,15 @@
   ... jtag operations using CHIP.jrc
 @}
 @end example
+
+If you need some post reset action, you can do:
+
+@example
+jtag configure CHIP.cpu -event post-reset @{
+  echo "Reset done"
+  ... jtag operations to be done after reset
+@}
+@end example
 @end deffn
 
 @deffn Command {jtag tapdisable} dotted.name

[Openocd-svn] r2699 - in trunk/tcl: board target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-12 10:11:45 +0200 (Sat, 12 Sep 2009)
New Revision: 2699

Modified:
   trunk/tcl/board/dm355evm.cfg
   trunk/tcl/target/davinci.cfg
   trunk/tcl/target/ti_dm355.cfg
Log:
David Brownell <da...@pa...> 
Update the board config for the DaVinci DM355 EVM so the reset-init
event handler does the rest of the work it should do:

 - minor PLL setup bugfixes
 - initialize the DDR2 controller
 - probe both NAND banks
 - initialize UART0
 - enable the icache


Modified: trunk/tcl/board/dm355evm.cfg
===================================================================
--- trunk/tcl/board/dm355evm.cfg	2009-09-12 08:10:19 UTC (rev 2698)
+++ trunk/tcl/board/dm355evm.cfg	2009-09-12 08:11:45 UTC (rev 2699)
@@ -35,7 +35,7 @@
 	set addr [dict get $dm355 pllc1]
 	set pll_divs [dict create]
 	dict set pll_divs div3 16
-	dict set pll_divs div4 8
+	dict set pll_divs div4 4
 	pll_v02_setup $addr 144 $pll_divs
 
 	# ARM is now running at 216 MHz, so JTAG can go faster
@@ -48,6 +48,7 @@
 
 	set addr [dict get $dm355 pllc2]
 	set pll_divs [dict create]
+	dict set pll_divs div1 1
 	dict set pll_divs prediv 8
 	pll_v02_setup $addr 114 $pll_divs
 
@@ -77,8 +78,55 @@
 	########################
 	# DDR2 EMIF
 
-	# FIXME setup
+	# VTPIOCR impedance calibration
+	set addr [dict get $dm355 sysbase]
+	set addr [expr $addr + 0x70]
 
+	# clear CLR, LOCK, PWRDN; wait a clock; set CLR
+	mmw $addr 0 0x20c0
+	mmw $addr 0x2000 0
+
+	# wait for READY
+        while { [expr [mrw $addr] & 0x8000] == 0 } { sleep 1 }
+
+	# set IO_READY; then LOCK and PWRSAVE; then PWRDN
+	mmw $addr 0x4000 0
+	mmw $addr 0x0180 0
+	mmw $addr 0x0040 0
+
+	# NOTE:  this DDR2 initialization sequence borrows from
+	# both UBL 1.50 and the SPRUEH7D DDR2 EMIF spec.
+
+	# reset (then re-enable) DDR controller
+	psc_reset 13
+	psc_go
+	psc_enable 13
+	psc_go
+
+	# now set it up for Micron MT47H64M16HR-37E @ 171 MHz
+
+	set addr [dict get $dm355 ddr_emif]
+
+	# DDRPHYCR1
+	mww [expr $addr + 0xe4] 0x50006404
+
+	# PBBPR -- burst priority
+	mww [expr $addr + 0x20] 0xfe
+
+	# SDCR -- unlock boot config; init for DDR2, relock, unlock SDTIM*
+	mmw [expr $addr + 0x08] 0x00800000 0
+	mmw [expr $addr + 0x08] 0x0013c632 0x03870fff
+
+	# SDTIMR, SDTIMR2
+	mww [expr $addr + 0x10] 0x2a923249
+	mww [expr $addr + 0x14] 0x4c17c763
+
+	# SDCR -- relock SDTIM*
+	mmw [expr $addr + 0x08] 0 0x00008000
+
+	# SDRCR -- refresh rate (171 MHz * 7.8usec)
+	mww [expr $addr + 0x0c] 1336
+
 	########################
 	# ASYNC EMIF
 
@@ -98,10 +146,43 @@
 	# NANDFCR -- only CS0 has NAND
 	mww [expr $addr + 0x60] 0x01
 
+	# default: both chipselects to the NAND socket are used
+	nand probe 0
+	nand probe 1
+
 	########################
 	# UART0
 
-	# FIXME setup
+	set addr [dict get $dm355 uart0]
+
+	# PWREMU_MGNT -- rx + tx in reset
+	mww [expr $addr + 0x30] 0
+
+	# DLL, DLH -- 115200 baud
+	mwb [expr $addr + 0x20] 0x0d
+	mwb [expr $addr + 0x24] 0x00
+
+	# FCR - clear and disable FIFOs
+	mwb [expr $addr + 0x08] 0x07
+	mwb [expr $addr + 0x08] 0x00
+
+	# IER - disable IRQs
+	mwb [expr $addr + 0x04] 0x00
+
+	# LCR - 8-N-1
+	mwb [expr $addr + 0x0c] 0x03
+
+	# MCR - no flow control or loopback
+	mwb [expr $addr + 0x10] 0x00
+
+	# PWREMU_MGNT -- rx + tx normal, free running during JTAG halt
+	mww [expr $addr + 0x30] 0xe001
+
+
+	########################
+
+	# turn on icache - set I bit in cp15 register c1
+	arm926ejs cp15 0 0 1 0 0x00051078
 }
 
 # NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.

Modified: trunk/tcl/target/davinci.cfg
===================================================================
--- trunk/tcl/target/davinci.cfg	2009-09-12 08:10:19 UTC (rev 2698)
+++ trunk/tcl/target/davinci.cfg	2009-09-12 08:11:45 UTC (rev 2699)
@@ -125,6 +125,7 @@
 		set pllstat [expr $pll_addr + 0x013c]
 		while {[expr [mrw $pllstat] & 0x01] != 0} { sleep 1 }
 	}
+	mww [expr $pll_addr + 0x0138] 0x00
 
 	# 11 - wait at least 5 usec for reset to finish
 	# (assume covered by overheads including JTAG messaging)
@@ -152,7 +153,14 @@
 	mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x03 0x1f
 }
 
-# execute non-DSP PSC transition(s) set up by psc_enable
+# prepare a non-DSP module to be reset; finish with psc_go
+proc psc_reset {module} {
+	set psc_addr 0x01c41000
+	# write MDCTL
+	mmw [expr $psc_addr + 0x0a00 + (4 * $module)] 0x01 0x1f
+}
+
+# execute non-DSP PSC transition(s) set up by psc_enable, psc_reset, etc
 proc psc_go {} {
 	set psc_addr 0x01c41000
 	set ptstat_addr [expr $psc_addr + 0x0128]

Modified: trunk/tcl/target/ti_dm355.cfg
===================================================================
--- trunk/tcl/target/ti_dm355.cfg	2009-09-12 08:10:19 UTC (rev 2698)
+++ trunk/tcl/target/ti_dm355.cfg	2009-09-12 08:11:45 UTC (rev 2699)
@@ -65,6 +65,9 @@
 dict set dm355 a_emif_cs1	0x04000000
 dict set dm355 ddr_emif		0x20000000
 dict set dm355 ddr		0x80000000
+dict set dm355 uart0		0x01c20000
+dict set dm355 uart1		0x01c20400
+dict set dm355 uart2		0x01e06000
 
 source [find target/davinci.cfg]
 

[Openocd-svn] r2698 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-12 10:10:19 +0200 (Sat, 12 Sep 2009)
New Revision: 2698

Modified:
   trunk/src/target/arm7_9_common.c
   trunk/src/target/arm7_9_common.h
   trunk/src/target/armv7m.c
Log:
David Brownell <da...@pa...> 
Cleanup some the downloaded ARM target algorithm code:

 - Provide more complete disassembly of the DCC bulk write code

 - Make code blocks "static const", in case GCC doesn't

 - Fix some tabbing/layout issues

 - Make some arm7_9_common.h flags be "bool" not "int"; and compact
   the layout a bit (group most bools together)

Modified: trunk/src/target/arm7_9_common.c
===================================================================
--- trunk/src/target/arm7_9_common.c	2009-09-11 21:14:31 UTC (rev 2697)
+++ trunk/src/target/arm7_9_common.c	2009-09-12 08:10:19 UTC (rev 2698)
@@ -2657,8 +2657,21 @@
 
 static const uint32_t dcc_code[] =
 {
-	/* MRC      TST         BNE         MRC         STR         B */
-	0xee101e10, 0xe3110001, 0x0afffffc, 0xee111e10, 0xe4801004, 0xeafffff9
+	/* r0 == input, points to memory buffer
+	 * r1 == scratch
+	 */
+
+	/* spin until DCC control (c0) reports data arrived */
+	0xee101e10,	/* w: mrc p14, #0, r1, c0, c0 */
+	0xe3110001,	/*    tst r1, #1              */
+	0x0afffffc,	/*    bne w                   */
+
+	/* read word from DCC (c1), write to memory */
+	0xee111e10,	/*    mrc p14, #0, r1, c1, c0 */
+	0xe4801004,	/*    str r1, [r0], #4        */
+
+	/* repeat */
+	0xeafffff9	/*    b   w                   */
 };
 
 int armv4_5_run_algorithm_inner(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target_s *target, uint32_t exit_point, int timeout_ms, void *arch_info));
@@ -2736,7 +2749,7 @@
 	reg_param_t reg_params[2];
 	int retval;
 
-	uint32_t arm7_9_crc_code[] = {
+	static const uint32_t arm7_9_crc_code[] = {
 		0xE1A02000,				/* mov		r2, r0 */
 		0xE3E00000,				/* mov		r0, #0xffffffff */
 		0xE1A03001,				/* mov		r3, r1 */
@@ -2818,15 +2831,15 @@
 	int retval;
 	uint32_t i;
 
-	uint32_t erase_check_code[] =
+	static const uint32_t erase_check_code[] =
 	{
-						/* loop: */
-		0xe4d03001,		/* ldrb r3, [r0], #1	*/
-		0xe0022003,		/* and r2, r2, r3 		*/
-		0xe2511001, 	/* subs r1, r1, #1		*/
-		0x1afffffb,		/* bne loop				*/
-						/* end: */
-		0xeafffffe		/* b end				*/
+		/* loop: */
+		0xe4d03001,		/* ldrb r3, [r0], #1 */
+		0xe0022003,		/* and r2, r2, r3    */
+		0xe2511001,		/* subs r1, r1, #1   */
+		0x1afffffb,		/* bne loop          */
+		/* end: */
+		0xeafffffe		/* b end             */
 	};
 
 	/* make sure we have a working area */

Modified: trunk/src/target/arm7_9_common.h
===================================================================
--- trunk/src/target/arm7_9_common.h	2009-09-11 21:14:31 UTC (rev 2697)
+++ trunk/src/target/arm7_9_common.h	2009-09-12 08:10:19 UTC (rev 2698)
@@ -46,6 +46,8 @@
 
 	uint32_t arm_bkpt; /**< ARM breakpoint instruction */
 	uint16_t thumb_bkpt; /**< Thumb breakpoint instruction */
+	bool force_hw_bkpts;
+
 	int sw_breakpoints_added; /**< Specifies which watchpoint software breakpoints are setup on */
 	int sw_breakpoint_count; /**< keep track of number of software breakpoints we have set */
 	int breakpoint_count; /**< Current number of set breakpoints */
@@ -54,24 +56,23 @@
 	int wp0_used; /**< Specifies if and how watchpoint unit 0 is used */
 	int wp1_used; /**< Specifies if and how watchpoint unit 1 is used */
 	int wp1_used_default; /**< Specifies if and how watchpoint unit 1 is used by default */
-	int force_hw_bkpts;
 	int dbgreq_adjust_pc; /**< Amount of PC adjustment caused by a DBGREQ */
-	int use_dbgrq; /**< Specifies if DBGRQ should be used to halt the target */
-	int need_bypass_before_restart; /**< Specifies if there should be a bypass before a JTAG restart */
+	bool use_dbgrq; /**< Specifies if DBGRQ should be used to halt the target */
+	bool need_bypass_before_restart; /**< Specifies if there should be a bypass before a JTAG restart */
 
-	etm_context_t *etm_ctx;
+	bool has_single_step;
+	bool has_monitor_mode;
+	bool has_vector_catch; /**< Specifies if the target has a reset vector catch */
 
-	int has_single_step;
-	int has_monitor_mode;
-	int has_vector_catch; /**< Specifies if the target has a reset vector catch */
+	bool debug_entry_from_reset; /**< Specifies if debug entry was from a reset */
 
-	int debug_entry_from_reset; /**< Specifies if debug entry was from a reset */
+	bool fast_memory_access;
+	bool dcc_downloads;
 
+	etm_context_t *etm_ctx;
+
 	struct working_area_s *dcc_working_area;
 
-	int fast_memory_access;
-	int dcc_downloads;
-
 	int (*examine_debug_reason)(target_t *target); /**< Function for determining why debug state was entered */
 
 	void (*change_to_arm)(target_t *target, uint32_t *r0, uint32_t *pc); /**< Function for changing from Thumb to ARM mode */

Modified: trunk/src/target/armv7m.c
===================================================================
--- trunk/src/target/armv7m.c	2009-09-11 21:14:31 UTC (rev 2697)
+++ trunk/src/target/armv7m.c	2009-09-12 08:10:19 UTC (rev 2698)
@@ -573,7 +573,7 @@
 	reg_param_t reg_params[2];
 	int retval;
 
-	uint16_t cortex_m3_crc_code[] = {
+	static const uint16_t cortex_m3_crc_code[] = {
 		0x4602,					/* mov	r2, r0 */
 		0xF04F, 0x30FF,			/* mov	r0, #0xffffffff */
 		0x460B,					/* mov	r3, r1 */
@@ -655,11 +655,11 @@
 	int retval;
 	uint32_t i;
 
-	uint16_t erase_check_code[] =
+	static const uint16_t erase_check_code[] =
 	{
 							/* loop: */
-		0xF810, 0x3B01,		/* ldrb 	r3, [r0], #1 */
-		0xEA02, 0x0203,		/* and 	r2, r2, r3 */
+		0xF810, 0x3B01,		/* ldrb r3, [r0], #1 */
+		0xEA02, 0x0203,		/* and  r2, r2, r3 */
 		0x3901,				/* subs 	r1, r1, #1 */
 		0xD1F9,				/* bne		loop */
 							/* end: */

[Openocd-svn] r2697 - trunk

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-11 23:14:31 +0200 (Fri, 11 Sep 2009)
New Revision: 2697

Modified:
   trunk/TODO
Log:
David Brownell <da...@pa...> some early todo items on run_algorithm

Modified: trunk/TODO
===================================================================
--- trunk/TODO	2009-09-11 18:34:15 UTC (rev 2696)
+++ trunk/TODO	2009-09-11 21:14:31 UTC (rev 2697)
@@ -132,6 +132,10 @@
   ARM1156 has Thumb2; ARM1136 doesn't.
 - Cortex A8 support (ML)
   - add target implementation (ML)
+- Generic ARM run_algorithm() interface
+  - tagged struct wrapping ARM instructions and metadata
+  - not revision-specific (current: ARMv4+ARMv5 -or- ARMv6 -or- ARMv7)
+  - usable with at least arm_nandwrite() and generic CFI drivers
 - MC1322x support (JW/DE?)
   - integrate and test support from JW (and DE?)
   - get working with a known good interface (i.e. not today's jlink)

[Openocd-svn] r2696 - in trunk: src/flash src/jtag tcl/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-11 20:34:15 +0200 (Fri, 11 Sep 2009)
New Revision: 2696

Modified:
   trunk/src/flash/str9xpec.c
   trunk/src/jtag/core.c
   trunk/src/jtag/jtag.h
   trunk/src/jtag/tcl.c
   trunk/tcl/target/omap3530.cfg
Log:
tap post reset event added. Allows omap3530 to send 100 runtest idle tickle's after a TAP_RESET.

Modified: trunk/src/flash/str9xpec.c
===================================================================
--- trunk/src/flash/str9xpec.c	2009-09-11 14:08:28 UTC (rev 2695)
+++ trunk/src/flash/str9xpec.c	2009-09-11 18:34:15 UTC (rev 2696)
@@ -1254,7 +1254,8 @@
 		return ERROR_FAIL;
 
 	/* exit turbo mode via RESET */
-	str9xpec_set_instr(tap, ISC_NOOP, TAP_RESET);
+	str9xpec_set_instr(tap, ISC_NOOP, TAP_IDLE);
+	jtag_add_tlr();
 	jtag_execute_queue();
 
 	/* restore previous scan chain */

Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-09-11 14:08:28 UTC (rev 2695)
+++ trunk/src/jtag/core.c	2009-09-11 18:34:15 UTC (rev 2696)
@@ -62,6 +62,7 @@
 {
 	[JTAG_TRST_ASSERTED] = "JTAG controller reset (TLR or TRST)",
 	[JTAG_TAP_EVENT_ENABLE] = "TAP enabled",
+	[JTAG_TAP_EVENT_POST_RESET] = "post reset",
 	[JTAG_TAP_EVENT_DISABLE] = "TAP disabled",
 };
 
@@ -339,6 +340,8 @@
 
 void jtag_add_ir_scan(int in_num_fields, scan_field_t *in_fields, tap_state_t state)
 {
+	assert(state != TAP_RESET);
+
 	if (jtag_verify && jtag_verify_capture_ir)
 	{
 		/* 8 x 32 bit id's is enough for all invocations */
@@ -361,6 +364,8 @@
 void jtag_add_plain_ir_scan(int in_num_fields, const scan_field_t *in_fields,
 		tap_state_t state)
 {
+	assert(state != TAP_RESET);
+
 	jtag_prelude(state);
 
 	int retval = interface_jtag_add_plain_ir_scan(
@@ -439,6 +444,8 @@
 void jtag_add_dr_scan(int in_num_fields, const scan_field_t *in_fields,
 		tap_state_t state)
 {
+	assert(state != TAP_RESET);
+	
 	jtag_prelude(state);
 
 	int retval;
@@ -449,6 +456,8 @@
 void jtag_add_plain_dr_scan(int in_num_fields, const scan_field_t *in_fields,
 		tap_state_t state)
 {
+	assert(state != TAP_RESET);
+	
 	jtag_prelude(state);
 
 	int retval;
@@ -460,6 +469,8 @@
 		int num_fields, const int* num_bits, const uint32_t* value,
 		tap_state_t end_state)
 {
+	assert(end_state != TAP_RESET);
+	
 	assert(end_state != TAP_INVALID);
 
 	cmd_queue_cur_state = end_state;
@@ -473,6 +484,9 @@
 {
 	jtag_prelude(TAP_RESET);
 	jtag_set_error(interface_jtag_add_tlr());
+
+	jtag_notify_reset();
+
 	jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
 }
 
@@ -683,6 +697,8 @@
 			LOG_DEBUG("TRST line released");
 			if (jtag_ntrst_delay)
 				jtag_add_sleep(jtag_ntrst_delay * 1000);
+
+			jtag_notify_reset();
 		}
 	}
 }
@@ -851,7 +867,8 @@
 	for (unsigned i = 0; i < JTAG_MAX_CHAIN_SIZE; i++)
 		buf_set_u32(idcode_buffer, i * 32, 32, 0x000000FF);
 
-	jtag_add_plain_dr_scan(1, &field, TAP_RESET);
+	jtag_add_plain_dr_scan(1, &field, TAP_DRPAUSE);
+	jtag_add_tlr();
 	return jtag_execute_queue();
 }
 
@@ -1065,7 +1082,9 @@
 	field.in_value = ir_test;
 
 
-	jtag_add_plain_ir_scan(1, &field, TAP_RESET);
+	jtag_add_plain_ir_scan(1, &field, TAP_IRPAUSE);
+	jtag_add_tlr();
+
 	int retval;
 	retval = jtag_execute_queue();
 	if (retval != ERROR_OK)

Modified: trunk/src/jtag/jtag.h
===================================================================
--- trunk/src/jtag/jtag.h	2009-09-11 14:08:28 UTC (rev 2695)
+++ trunk/src/jtag/jtag.h	2009-09-11 18:34:15 UTC (rev 2696)
@@ -208,6 +208,7 @@
 	JTAG_TRST_ASSERTED,
 	JTAG_TAP_EVENT_ENABLE,
 	JTAG_TAP_EVENT_DISABLE,
+	JTAG_TAP_EVENT_POST_RESET,
 };
 
 struct jtag_tap_event_action_s
@@ -635,7 +636,10 @@
 /// @returns the number of times the scan queue has been flushed
 int jtag_get_flush_queue_count(void);
 
+/// Notify all TAP's about a TLR reset
+void jtag_notify_reset(void);
 
+
 /* can be implemented by hw + sw */
 extern int jtag_power_dropout(int* dropout);
 extern int jtag_srst_asserted(int* srst_asserted);

Modified: trunk/src/jtag/tcl.c
===================================================================
--- trunk/src/jtag/tcl.c	2009-09-11 14:08:28 UTC (rev 2695)
+++ trunk/src/jtag/tcl.c	2009-09-11 18:34:15 UTC (rev 2696)
@@ -41,6 +41,7 @@
 #endif
 
 static const Jim_Nvp nvp_jtag_tap_event[] = {
+	{ .value = JTAG_TAP_EVENT_POST_RESET,   .name = "post-reset" },
 	{ .value = JTAG_TAP_EVENT_ENABLE,       .name = "tap-enable" },
 	{ .value = JTAG_TAP_EVENT_DISABLE,      .name = "tap-disable" },
 
@@ -583,6 +584,17 @@
 	return JIM_ERR;
 }
 
+
+void jtag_notify_reset(void)
+{
+	jtag_tap_t *tap;
+	for (tap = jtag_all_taps(); tap; tap = tap->next_tap)
+	{
+		jtag_tap_handle_event(tap, JTAG_TAP_EVENT_POST_RESET);
+	}
+}
+
+
 int jtag_register_commands(struct command_context_s *cmd_ctx)
 {
 	register_jim(cmd_ctx, "jtag", jim_jtag_command, "perform jtag tap actions");

Modified: trunk/tcl/target/omap3530.cfg
===================================================================
--- trunk/tcl/target/omap3530.cfg	2009-09-11 14:08:28 UTC (rev 2695)
+++ trunk/tcl/target/omap3530.cfg	2009-09-11 18:34:15 UTC (rev 2696)
@@ -34,6 +34,8 @@
 jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
 	-expected-id $_JRC_TAPID
 
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
+
 # GDB target:  Cortex-A8, using DAP
 target create omap3.cpu cortex_a8 -chain-position $_CHIPNAME.dap
 

[Openocd-svn] r2695 - trunk/tcl/interface

[ntfreak at B. <nt...@ma...>]

Author: ntfreak
Date: 2009-09-11 16:08:28 +0200 (Fri, 11 Sep 2009)
New Revision: 2695

Modified:
   trunk/tcl/interface/sheevaplug.cfg
Log:
- revert change made to sheevaplug.cfg in rev2573

Modified: trunk/tcl/interface/sheevaplug.cfg
===================================================================
--- trunk/tcl/interface/sheevaplug.cfg	2009-09-11 08:04:50 UTC (rev 2694)
+++ trunk/tcl/interface/sheevaplug.cfg	2009-09-11 14:08:28 UTC (rev 2695)
@@ -7,6 +7,6 @@
 interface ft2232
 ft2232_layout sheevaplug
 ft2232_vid_pid 0x9e88 0x9e8f
-ft2232_device_desc "SheevaPlug JTAGKey FT2232D"
+ft2232_device_desc "SheevaPlug JTAGKey FT2232D B"
 jtag_khz 2000
 

[Openocd-svn] r2694 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-11 10:04:50 +0200 (Fri, 11 Sep 2009)
New Revision: 2694

Modified:
   trunk/src/target/feroceon.c
Log:
Nicolas Pitre <ni...@ca...> put feroceon target definition at the end so to avoid a
bunch of useless forward declarations.

Modified: trunk/src/target/feroceon.c
===================================================================
--- trunk/src/target/feroceon.c	2009-09-11 08:03:46 UTC (rev 2693)
+++ trunk/src/target/feroceon.c	2009-09-11 08:04:50 UTC (rev 2694)
@@ -56,14 +56,6 @@
 #include "arm966e.h"
 #include "target_type.h"
 
-
-int feroceon_examine(struct target_s *target);
-int feroceon_target_create(struct target_s *target, Jim_Interp *interp);
-int dragonite_target_create(struct target_s *target, Jim_Interp *interp);
-int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer);
-int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
-int feroceon_quit(void);
-
 int feroceon_assert_reset(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -77,84 +69,6 @@
 	return arm7_9_assert_reset(target);
 }
 
-target_type_t feroceon_target =
-{
-	.name = "feroceon",
-
-	.poll = arm7_9_poll,
-	.arch_state = arm926ejs_arch_state,
-
-	.target_request_data = arm7_9_target_request_data,
-
-	.halt = arm7_9_halt,
-	.resume = arm7_9_resume,
-	.step = arm7_9_step,
-
-	.assert_reset = feroceon_assert_reset,
-	.deassert_reset = arm7_9_deassert_reset,
-	.soft_reset_halt = arm926ejs_soft_reset_halt,
-
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
-
-	.read_memory = arm7_9_read_memory,
-	.write_memory = arm926ejs_write_memory,
-	.bulk_write_memory = feroceon_bulk_write_memory,
-	.checksum_memory = arm7_9_checksum_memory,
-	.blank_check_memory = arm7_9_blank_check_memory,
-
-	.run_algorithm = armv4_5_run_algorithm,
-
-	.add_breakpoint = arm7_9_add_breakpoint,
-	.remove_breakpoint = arm7_9_remove_breakpoint,
-	.add_watchpoint = arm7_9_add_watchpoint,
-	.remove_watchpoint = arm7_9_remove_watchpoint,
-
-	.register_commands = arm926ejs_register_commands,
-	.target_create = feroceon_target_create,
-	.init_target = feroceon_init_target,
-	.examine = feroceon_examine,
-	.quit = feroceon_quit
-};
-
-target_type_t dragonite_target =
-{
-	.name = "dragonite",
-
-	.poll = arm7_9_poll,
-	.arch_state = armv4_5_arch_state,
-
-	.target_request_data = arm7_9_target_request_data,
-
-	.halt = arm7_9_halt,
-	.resume = arm7_9_resume,
-	.step = arm7_9_step,
-
-	.assert_reset = feroceon_assert_reset,
-	.deassert_reset = arm7_9_deassert_reset,
-	.soft_reset_halt = arm7_9_soft_reset_halt,
-
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
-
-	.read_memory = arm7_9_read_memory,
-	.write_memory = arm7_9_write_memory,
-	.bulk_write_memory = feroceon_bulk_write_memory,
-	.checksum_memory = arm7_9_checksum_memory,
-	.blank_check_memory = arm7_9_blank_check_memory,
-
-	.run_algorithm = armv4_5_run_algorithm,
-
-	.add_breakpoint = arm7_9_add_breakpoint,
-	.remove_breakpoint = arm7_9_remove_breakpoint,
-	.add_watchpoint = arm7_9_add_watchpoint,
-	.remove_watchpoint = arm7_9_remove_watchpoint,
-
-	.register_commands = arm966e_register_commands,
-	.target_create = dragonite_target_create,
-	.init_target = feroceon_init_target,
-	.examine = feroceon_examine,
-	.quit = feroceon_quit
-};
-
 int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, uint32_t instr)
 {
 	scan_field_t fields[3];
@@ -765,3 +679,82 @@
 
 	return ERROR_OK;
 }
+
+target_type_t feroceon_target =
+{
+	.name = "feroceon",
+
+	.poll = arm7_9_poll,
+	.arch_state = arm926ejs_arch_state,
+
+	.target_request_data = arm7_9_target_request_data,
+
+	.halt = arm7_9_halt,
+	.resume = arm7_9_resume,
+	.step = arm7_9_step,
+
+	.assert_reset = feroceon_assert_reset,
+	.deassert_reset = arm7_9_deassert_reset,
+	.soft_reset_halt = arm926ejs_soft_reset_halt,
+
+	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+
+	.read_memory = arm7_9_read_memory,
+	.write_memory = arm926ejs_write_memory,
+	.bulk_write_memory = feroceon_bulk_write_memory,
+	.checksum_memory = arm7_9_checksum_memory,
+	.blank_check_memory = arm7_9_blank_check_memory,
+
+	.run_algorithm = armv4_5_run_algorithm,
+
+	.add_breakpoint = arm7_9_add_breakpoint,
+	.remove_breakpoint = arm7_9_remove_breakpoint,
+	.add_watchpoint = arm7_9_add_watchpoint,
+	.remove_watchpoint = arm7_9_remove_watchpoint,
+
+	.register_commands = arm926ejs_register_commands,
+	.target_create = feroceon_target_create,
+	.init_target = feroceon_init_target,
+	.examine = feroceon_examine,
+	.quit = feroceon_quit
+};
+
+target_type_t dragonite_target =
+{
+	.name = "dragonite",
+
+	.poll = arm7_9_poll,
+	.arch_state = armv4_5_arch_state,
+
+	.target_request_data = arm7_9_target_request_data,
+
+	.halt = arm7_9_halt,
+	.resume = arm7_9_resume,
+	.step = arm7_9_step,
+
+	.assert_reset = feroceon_assert_reset,
+	.deassert_reset = arm7_9_deassert_reset,
+	.soft_reset_halt = arm7_9_soft_reset_halt,
+
+	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+
+	.read_memory = arm7_9_read_memory,
+	.write_memory = arm7_9_write_memory,
+	.bulk_write_memory = feroceon_bulk_write_memory,
+	.checksum_memory = arm7_9_checksum_memory,
+	.blank_check_memory = arm7_9_blank_check_memory,
+
+	.run_algorithm = armv4_5_run_algorithm,
+
+	.add_breakpoint = arm7_9_add_breakpoint,
+	.remove_breakpoint = arm7_9_remove_breakpoint,
+	.add_watchpoint = arm7_9_add_watchpoint,
+	.remove_watchpoint = arm7_9_remove_watchpoint,
+
+	.register_commands = arm966e_register_commands,
+	.target_create = dragonite_target_create,
+	.init_target = feroceon_init_target,
+	.examine = feroceon_examine,
+	.quit = feroceon_quit
+};
+

[Openocd-svn] r2693 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-11 10:03:46 +0200 (Fri, 11 Sep 2009)
New Revision: 2693

Modified:
   trunk/src/target/arm966e.c
   trunk/src/target/arm966e.h
   trunk/src/target/feroceon.c
   trunk/src/target/target.c
Log:
Nicolas Pitre <ni...@ca...> Dragonite support

Modified: trunk/src/target/arm966e.c
===================================================================
--- trunk/src/target/arm966e.c	2009-09-11 07:46:50 UTC (rev 2692)
+++ trunk/src/target/arm966e.c	2009-09-11 08:03:46 UTC (rev 2693)
@@ -32,9 +32,6 @@
 #define _DEBUG_INSTRUCTION_EXECUTION_
 #endif
 
-/* cli handling */
-int arm966e_register_commands(struct command_context_s *cmd_ctx);
-
 /* forward declarations */
 int arm966e_target_create(struct target_s *target, Jim_Interp *interp);
 int arm966e_init_target(struct command_context_s *cmd_ctx, struct target_s *target);

Modified: trunk/src/target/arm966e.h
===================================================================
--- trunk/src/target/arm966e.h	2009-09-11 07:46:50 UTC (rev 2692)
+++ trunk/src/target/arm966e.h	2009-09-11 08:03:46 UTC (rev 2693)
@@ -34,6 +34,8 @@
 	uint32_t cp15_control_reg;
 } arm966e_common_t;
 
+extern int arm966e_init_arch_info(target_t *target, arm966e_common_t *arm966e, jtag_tap_t *tap);
+extern int arm966e_register_commands(struct command_context_s *cmd_ctx);
 extern int arm966e_read_cp15(target_t *target, int reg_addr, uint32_t *value);
 extern int arm966e_write_cp15(target_t *target, int reg_addr, uint32_t value);
 

Modified: trunk/src/target/feroceon.c
===================================================================
--- trunk/src/target/feroceon.c	2009-09-11 07:46:50 UTC (rev 2692)
+++ trunk/src/target/feroceon.c	2009-09-11 08:03:46 UTC (rev 2693)
@@ -1,5 +1,5 @@
 /***************************************************************************
- *   Copyright (C) 2008 by Marvell Semiconductors, Inc.                    *
+ *   Copyright (C) 2008-2009 by Marvell Semiconductors, Inc.                    *
  *   Written by Nicolas Pitre <ni...@ma...>                           *
  *                                                                         *
  *   Copyright (C) 2008 by Hongtao Zheng                                   *
@@ -22,10 +22,10 @@
  ***************************************************************************/
 
 /*
- * Marvell Feroceon support, including Orion and Kirkwood SOCs.
+ * Marvell Feroceon/Dragonite support.
  *
- * The Feroceon core mimics the ARM926 ICE interface with the following
- * differences:
+ * The Feroceon core, as found in the Orion and Kirkwood SoCs amongst others,
+ * mimics the ARM926 ICE interface with the following differences:
  *
  * - the MOE (method of entry) reporting is not implemented
  *
@@ -43,6 +43,9 @@
  *
  * - the DCC channel is half duplex (only one FIFO for both directions) with
  *   seemingly no proper flow control.
+ *
+ * The Dragonite core is the non-mmu version based on the ARM966 model, and
+ * it shares the above issues as well.
  */
 
 #ifdef HAVE_CONFIG_H
@@ -50,11 +53,13 @@
 #endif
 
 #include "arm926ejs.h"
+#include "arm966e.h"
 #include "target_type.h"
 
 
 int feroceon_examine(struct target_s *target);
 int feroceon_target_create(struct target_s *target, Jim_Interp *interp);
+int dragonite_target_create(struct target_s *target, Jim_Interp *interp);
 int feroceon_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer);
 int feroceon_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
 int feroceon_quit(void);
@@ -111,7 +116,45 @@
 	.quit = feroceon_quit
 };
 
+target_type_t dragonite_target =
+{
+	.name = "dragonite",
 
+	.poll = arm7_9_poll,
+	.arch_state = armv4_5_arch_state,
+
+	.target_request_data = arm7_9_target_request_data,
+
+	.halt = arm7_9_halt,
+	.resume = arm7_9_resume,
+	.step = arm7_9_step,
+
+	.assert_reset = feroceon_assert_reset,
+	.deassert_reset = arm7_9_deassert_reset,
+	.soft_reset_halt = arm7_9_soft_reset_halt,
+
+	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+
+	.read_memory = arm7_9_read_memory,
+	.write_memory = arm7_9_write_memory,
+	.bulk_write_memory = feroceon_bulk_write_memory,
+	.checksum_memory = arm7_9_checksum_memory,
+	.blank_check_memory = arm7_9_blank_check_memory,
+
+	.run_algorithm = armv4_5_run_algorithm,
+
+	.add_breakpoint = arm7_9_add_breakpoint,
+	.remove_breakpoint = arm7_9_remove_breakpoint,
+	.add_watchpoint = arm7_9_add_watchpoint,
+	.remove_watchpoint = arm7_9_remove_watchpoint,
+
+	.register_commands = arm966e_register_commands,
+	.target_create = dragonite_target_create,
+	.init_target = feroceon_init_target,
+	.examine = feroceon_examine,
+	.quit = feroceon_quit
+};
+
 int feroceon_dummy_clock_out(arm_jtag_t *jtag_info, uint32_t instr)
 {
 	scan_field_t fields[3];
@@ -632,17 +675,11 @@
 	return ERROR_OK;
 }
 
-int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
+void feroceon_common_setup(struct target_s *target)
 {
-	armv4_5_common_t *armv4_5;
-	arm7_9_common_t *arm7_9;
-	arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 
-	arm926ejs_init_arch_info(target, arm926ejs, target->tap);
-
-	armv4_5 = target->arch_info;
-	arm7_9 = armv4_5->arch_info;
-
 	/* override some insn sequence functions */
 	arm7_9->change_to_arm = feroceon_change_to_arm;
 	arm7_9->read_core_regs = feroceon_read_core_regs;
@@ -661,10 +698,6 @@
 	/* MOE is not implemented */
 	arm7_9->examine_debug_reason = feroceon_examine_debug_reason;
 
-	/* the standard ARM926 methods don't always work (don't ask...) */
-	arm926ejs->read_cp15 = feroceon_read_cp15;
-	arm926ejs->write_cp15 = feroceon_write_cp15;
-
 	/* Note: asserting DBGRQ might not win over the undef exception.
 	   If that happens then just use "arm7_9 dbgrq disable". */
 	arm7_9->use_dbgrq = 1;
@@ -673,10 +706,32 @@
 	/* only one working comparator */
 	arm7_9->wp_available_max = 1;
 	arm7_9->wp1_used_default = -1;
+}
 
+int feroceon_target_create(struct target_s *target, Jim_Interp *interp)
+{
+	arm926ejs_common_t *arm926ejs = calloc(1,sizeof(arm926ejs_common_t));
+
+	arm926ejs_init_arch_info(target, arm926ejs, target->tap);
+	feroceon_common_setup(target);
+
+	/* the standard ARM926 methods don't always work (don't ask...) */
+	arm926ejs->read_cp15 = feroceon_read_cp15;
+	arm926ejs->write_cp15 = feroceon_write_cp15;
+
 	return ERROR_OK;
 }
 
+int dragonite_target_create(struct target_s *target, Jim_Interp *interp)
+{
+	arm966e_common_t *arm966e = calloc(1,sizeof(arm966e_common_t));
+
+	arm966e_init_arch_info(target, arm966e, target->tap);
+	feroceon_common_setup(target);
+
+	return ERROR_OK;
+}
+
 int feroceon_examine(struct target_s *target)
 {
 	armv4_5_common_t *armv4_5;

Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c	2009-09-11 07:46:50 UTC (rev 2692)
+++ trunk/src/target/target.c	2009-09-11 08:03:46 UTC (rev 2693)
@@ -84,6 +84,7 @@
 extern target_type_t arm926ejs_target;
 extern target_type_t fa526_target;
 extern target_type_t feroceon_target;
+extern target_type_t dragonite_target;
 extern target_type_t xscale_target;
 extern target_type_t cortexm3_target;
 extern target_type_t cortexa8_target;
@@ -101,6 +102,7 @@
 	&arm926ejs_target,
 	&fa526_target,
 	&feroceon_target,
+	&dragonite_target,
 	&xscale_target,
 	&cortexm3_target,
 	&cortexa8_target,

[Openocd-svn] r2692 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-11 09:46:50 +0200 (Fri, 11 Sep 2009)
New Revision: 2692

Modified:
   trunk/src/target/target.c
Log:
spelling mistake

Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c	2009-09-11 07:43:36 UTC (rev 2691)
+++ trunk/src/target/target.c	2009-09-11 07:46:50 UTC (rev 2692)
@@ -2334,7 +2334,7 @@
 				break;
 			}
 			image_size += length;
-			command_print(cmd_ctx, "%u byte written at address 0x%8.8" PRIx32 "",
+			command_print(cmd_ctx, "%u bytes written at address 0x%8.8" PRIx32 "",
 						  (unsigned int)length,
 						  image.sections[i].base_address + offset);
 		}
@@ -4537,7 +4537,7 @@
 			fastload[i].length = length;
 
 			image_size += length;
-			command_print(cmd_ctx, "%u byte written at address 0x%8.8x",
+			command_print(cmd_ctx, "%u bytes written at address 0x%8.8x",
 						  (unsigned int)length,
 						  ((unsigned int)(image.sections[i].base_address + offset)));
 		}

[Openocd-svn] r2691 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-11 09:43:36 +0200 (Fri, 11 Sep 2009)
New Revision: 2691

Modified:
   trunk/src/target/arm11_dbgtap.c
Log:
do not use dynamically sized stack arrays, not compatible with embedded OS's

Modified: trunk/src/target/arm11_dbgtap.c
===================================================================
--- trunk/src/target/arm11_dbgtap.c	2009-09-11 06:58:49 UTC (rev 2690)
+++ trunk/src/target/arm11_dbgtap.c	2009-09-11 07:43:36 UTC (rev 2691)
@@ -576,7 +576,15 @@
 	arm11_setup_field(arm11,  1,    NULL,			NULL /*&Ready*/,	chain5_fields + 1);
 	arm11_setup_field(arm11,  1,    NULL,			NULL,				chain5_fields + 2);
 
-	uint8_t			Readies[count + 1];
+	uint8_t			*Readies;
+	int bytes = sizeof(*Readies)*(count + 1);
+	Readies = (uint8_t *) malloc(bytes);
+	if (Readies == NULL)
+	{
+		LOG_ERROR("Out of memory allocating %d bytes", bytes);
+		return ERROR_FAIL;
+	}
+
 	uint8_t	*		ReadyPos			= Readies;
 
 	while (count--)
@@ -603,22 +611,28 @@
 
 	arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
 
-	CHECK_RETVAL(jtag_execute_queue());
+	int retval = jtag_execute_queue();
+	if (retval == ERROR_OK)
+	{
 
-	size_t error_count = 0;
+		size_t error_count = 0;
 
-	for (size_t i = 0; i < asizeof(Readies); i++)
-	{
-		if (Readies[i] != 1)
+		for (size_t i = 0; i < asizeof(Readies); i++)
 		{
-			error_count++;
+			if (Readies[i] != 1)
+			{
+				error_count++;
+			}
 		}
+
+		if (error_count)
+			LOG_ERROR("Transfer errors " ZU, error_count);
+
 	}
 
-	if (error_count)
-		LOG_ERROR("Transfer errors " ZU, error_count);
+	free(Readies);
 
-	return ERROR_OK;
+	return retval;
 }
 
 

[Openocd-svn] r2690 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-11 08:58:49 +0200 (Fri, 11 Sep 2009)
New Revision: 2690

Modified:
   trunk/src/target/target.c
Log:
registering a target event twice caused infinite loop. Same bug as in jtag/core.c copy & pasted.

Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c	2009-09-11 06:08:51 UTC (rev 2689)
+++ trunk/src/target/target.c	2009-09-11 06:58:49 UTC (rev 2690)
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dom...@gm...                                                   *
  *                                                                         *
- *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
+ *   Copyright (C) 2007-2009 Øyvind Harboe                                 *
  *   oyv...@zy...                                               *
  *                                                                         *
  *   Copyright (C) 2008, Duane Ellis                                       *
@@ -3547,9 +3547,11 @@
 				}
 
 				if (goi->isconfigure) {
+					bool replace = true;
 					if (teap == NULL) {
 						/* create new */
 						teap = calloc(1, sizeof(*teap));
+						replace = false;
 					}
 					teap->event = n->value;
 					Jim_GetOpt_Obj(goi, &o);
@@ -3569,9 +3571,12 @@
 					 */
 					Jim_IncrRefCount(teap->body);
 
-					/* add to head of event list */
-					teap->next = target->event_action;
-					target->event_action = teap;
+					if (!replace)
+					{
+						/* add to head of event list */
+						teap->next = target->event_action;
+						target->event_action = teap;
+					}
 					Jim_SetEmptyResult(goi->interp);
 				} else {
 					/* get */