openocd-commit — OpenOCD commit maling list - read only

[Openocd-svn] r2764 - trunk

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-27 19:08:42 +0200 (Sun, 27 Sep 2009)
New Revision: 2764

Modified:
   trunk/TODO
Log:
Add list of JTAG adapter drivers with TAP_RESET statemove bug.


Modified: trunk/TODO
===================================================================
--- trunk/TODO	2009-09-27 16:55:52 UTC (rev 2763)
+++ trunk/TODO	2009-09-27 17:08:42 UTC (rev 2764)
@@ -60,6 +60,22 @@
 
 @subsection thelistjtaginterfaces JTAG Interfaces
 
+There are some known bugs to fix in JTAG adapter drivers:
+
+- For JTAG_STATEMOVE to TAP_RESET, all drivers must ignore the current
+  recorded state.  The tap_get_state() call won't necessarily return
+  the correct value, especially at server startup.  Fix is easy:  in
+  that case, always issue five clocks with TMS high.
+  - amt_jtagaccel.c
+  - arm-jtag-ew.c
+  - bitbang.c
+  - bitq.c
+  - gw16012.c
+  - jlink.c
+  - usbprog.c
+  - vsllink.c
+  - rlink/rlink.c
+
 The following tasks have been suggeted for improving OpenOCD's JTAG
 interface support:
 
@@ -69,7 +85,7 @@
 - J-Link driver:
   - fix to work with long scan chains, such as R.Doss's svf test.
 - FT2232 (libftdi):
-  - make performance comparable to alternatives
+  - make performance comparable to alternatives (on Win32, D2XX is faster)
   - make usability comparable to alternatives
 
 The following tasks have been suggested for adding new JTAG interfaces:

[Openocd-svn] r2763 - trunk/src/jtag

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-27 18:55:52 +0200 (Sun, 27 Sep 2009)
New Revision: 2763

Modified:
   trunk/src/jtag/ft2232.c
Log:
Update FT2232 driver so that it reliably enters TAP_RESET.

When the OpenOCD server starts up it records its state as TAP_RESET,
even though it could be anything.  Then when it starts to examine
the scan chain, it calls jtag_add_tlr() which sees it doesn't have
any work to do, and so it does nothing.  This can make the next
operations fail because they start from the wrong TAP state...

Instead of caring about the current recorded state, always enter
TAP_RESET by forcing five clocks with TMS high.

(NOTE:  it seems most other JTAG adapter drivers have this same bug.)


Modified: trunk/src/jtag/ft2232.c
===================================================================
--- trunk/src/jtag/ft2232.c	2009-09-27 07:59:10 UTC (rev 2762)
+++ trunk/src/jtag/ft2232.c	2009-09-27 16:55:52 UTC (rev 2763)
@@ -1587,8 +1587,16 @@
 	}
 	ft2232_end_state(cmd->cmd.statemove->end_state);
 
-	/* move to end state */
-	if (tap_get_state() != tap_get_end_state())
+	/* For TAP_RESET, ignore the current recorded state.  It's often
+	 * wrong at server startup, and this transation is critical whenever
+	 * it's requested.
+	 */
+	if (tap_get_end_state() == TAP_RESET) {
+		clock_tms(0x4b,  0xff, 5, 0);
+		require_send = 1;
+
+	/* shortest-path move to desired end state */
+	} else if (tap_get_state() != tap_get_end_state())
 	{
 		move_to_state(tap_get_end_state());
 		require_send = 1;

[Openocd-svn] r2762 - trunk/tcl/target

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-27 09:59:10 +0200 (Sun, 27 Sep 2009)
New Revision: 2762

Modified:
   trunk/tcl/target/omap5912.cfg
Log:
Don't provide invalid OMAP5912 IR capture value/mask attributes


Modified: trunk/tcl/target/omap5912.cfg
===================================================================
--- trunk/tcl/target/omap5912.cfg	2009-09-26 22:08:50 UTC (rev 2761)
+++ trunk/tcl/target/omap5912.cfg	2009-09-27 07:59:10 UTC (rev 2762)
@@ -25,9 +25,9 @@
 # its standalone siblings (like TMS320VC5502) of the same era
 
 #jtag scan chain
-jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x0 -irmask 0x0 -expected-id 0x03df1d81
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0x0 -expected-id $_CPUTAPID
-jtag newtap $_CHIPNAME unknown -irlen 8 -ircapture  0x0 -irmask 0x0
+jtag newtap $_CHIPNAME dsp -irlen 38 -expected-id 0x03df1d81
+jtag newtap $_CHIPNAME arm -irlen 4 -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME unknown -irlen 8
 
 set _TARGETNAME $_CHIPNAME.arm
 target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME

[Openocd-svn] r2761 - trunk/tcl/board

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-27 00:08:50 +0200 (Sun, 27 Sep 2009)
New Revision: 2761

Modified:
   trunk/tcl/board/dm355evm.cfg
Log:
On DM355 EVM board, associate NAND chips with $_TARGETNAME
instead of a target number.


Modified: trunk/tcl/board/dm355evm.cfg
===================================================================
--- trunk/tcl/board/dm355evm.cfg	2009-09-26 22:01:24 UTC (rev 2760)
+++ trunk/tcl/board/dm355evm.cfg	2009-09-26 22:08:50 UTC (rev 2761)
@@ -191,8 +191,8 @@
 # you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
 # use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
 # needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
-nand device davinci 0 0x02000000 hwecc4 0x01e10000
-nand device davinci 0 0x02004000 hwecc4 0x01e10000
+nand device davinci $_TARGETNAME 0x02000000 hwecc4 0x01e10000
+nand device davinci $_TARGETNAME 0x02004000 hwecc4 0x01e10000
 
 # FIXME
 #  - support writing UBL with its header (new layout only with new ROMs)

[Openocd-svn] r2760 - trunk/src/jtag

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-27 00:01:24 +0200 (Sun, 27 Sep 2009)
New Revision: 2760

Modified:
   trunk/src/jtag/core.c
Log:
Diagnostics tweaks for jtag_examine_chain() failure paths.


Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-09-26 19:18:42 UTC (rev 2759)
+++ trunk/src/jtag/core.c	2009-09-26 22:01:24 UTC (rev 2760)
@@ -885,8 +885,9 @@
 	 * the scan is not valid */
 	if (zero_check == 0x00 || one_check == 0xff)
 	{
-		LOG_ERROR("JTAG communication failure: check connection, "
-			"JTAG interface, target power etc.");
+		LOG_ERROR("JTAG scan chain interrogation failed: all %s",
+				(zero_check == 0x00) ? "zeroes" : "ones");
+		LOG_ERROR("Check JTAG interface, timings, target power, etc.");
 		return false;
 	}
 	return true;
@@ -1238,7 +1239,7 @@
 	/* examine chain first, as this could discover the real chain layout */
 	if (jtag_examine_chain() != ERROR_OK)
 	{
-		LOG_ERROR("trying to validate configured JTAG chain anyway...");
+		LOG_ERROR("Trying to use configured scan chain anyway...");
 	}
 
 	if (jtag_validate_ircapture() != ERROR_OK)

[Openocd-svn] r2759 - in trunk/src: helper jtag

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-26 21:18:42 +0200 (Sat, 26 Sep 2009)
New Revision: 2759

Modified:
   trunk/src/helper/binarybuffer.h
   trunk/src/jtag/core.c
Log:
Updates to the initial scanchain validation code:
  - minor bug fixes
  - code cleanup
  - update comments
  - improve diagnostics
  - etc


Modified: trunk/src/helper/binarybuffer.h
===================================================================
--- trunk/src/helper/binarybuffer.h	2009-09-26 19:08:34 UTC (rev 2758)
+++ trunk/src/helper/binarybuffer.h	2009-09-26 19:18:42 UTC (rev 2759)
@@ -86,7 +86,7 @@
 struct scan_field_s;
 extern int buf_to_u32_handler(uint8_t *in_buf, void *priv, struct scan_field_s *field);
 
-#define CEIL(m, n)	((m + n - 1) / n)
+#define CEIL(m, n)	(((m) + (n) - 1) / (n))
 
 /* read a uint32_t from a buffer in target memory endianness */
 static inline uint32_t fast_target_buffer_get_u32(const uint8_t *buffer, int little)

Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-09-26 19:08:34 UTC (rev 2758)
+++ trunk/src/jtag/core.c	2009-09-26 19:18:42 UTC (rev 2759)
@@ -847,6 +847,9 @@
 #define EXTRACT_PART(X) (((X) & 0xffff000) >> 12)
 #define EXTRACT_VER(X)  (((X) & 0xf0000000) >> 28)
 
+/* A reserved manufacturer ID is used in END_OF_CHAIN_FLAG, so we
+ * know that no valid TAP will have it as an IDCODE value.
+ */
 #define END_OF_CHAIN_FLAG	0x000000ff
 
 static int jtag_examine_chain_execute(uint8_t *idcode_buffer, unsigned num_idcode)
@@ -964,6 +967,7 @@
 }
 
 /* Try to examine chain layout according to IEEE 1149.1 §12
+ * This is called a "blind interrogation" of the scan chain.
  */
 static int jtag_examine_chain(void)
 {
@@ -1037,7 +1041,12 @@
 	return ERROR_OK;
 }
 
-int jtag_validate_chain(void)
+/*
+ * Validate the date loaded by entry to the Capture-IR state, to help
+ * find errors related to scan chain configuration (wrong IR lengths)
+ * or communication.
+ */
+static int jtag_validate_ircapture(void)
 {
 	jtag_tap_t *tap;
 	int total_ir_length = 0;
@@ -1056,7 +1065,11 @@
 	}
 
 	total_ir_length += 2;
+
 	ir_test = malloc(CEIL(total_ir_length, 8));
+	if (ir_test == NULL)
+		return ERROR_FAIL;
+
 	buf_set_ones(ir_test, total_ir_length);
 
 	field.tap = NULL;
@@ -1082,24 +1095,37 @@
 			break;
 		}
 
+		/* Validate the two LSBs, which must be 01 per JTAG spec.
+		 * REVISIT we might be able to verify some MSBs too, using
+		 * ircapture/irmask attributes.
+		 */
 		val = buf_get_u32(ir_test, chain_pos, 2);
-		/* Only fail this check if we have IDCODE for this device */
-		if ((val != 0x1)&&(tap->hasidcode))
-		{
+		if (val != 1) {
 			char *cbuf = buf_to_str(ir_test, total_ir_length, 16);
-			LOG_ERROR("Could not validate JTAG scan chain, IR mismatch, scan returned 0x%s. tap=%s pos=%d expected 0x1 got %0x", cbuf, jtag_tap_name(tap), chain_pos, val);
-			free(cbuf);
-			free(ir_test);
-			return ERROR_JTAG_INIT_FAILED;
+
+			LOG_ERROR("%s: IR capture error; saw 0x%s not 0x..1",
+					jtag_tap_name(tap), cbuf);
+
+			/* Fail only if we have IDCODE for this device.
+			 * REVISIT -- why not fail-always?
+			 */
+			if (tap->hasidcode) {
+				free(cbuf);
+				free(ir_test);
+				return ERROR_JTAG_INIT_FAILED;
+			}
 		}
 		chain_pos += tap->ir_length;
 	}
 
+	/* verify the '11' sentinel we wrote is returned at the end */
 	val = buf_get_u32(ir_test, chain_pos, 2);
 	if (val != 0x3)
 	{
 		char *cbuf = buf_to_str(ir_test, total_ir_length, 16);
-		LOG_ERROR("Could not validate end of JTAG scan chain, IR mismatch, scan returned 0x%s. pos=%d expected 0x3 got %0x", cbuf, chain_pos, val);
+
+		LOG_ERROR("IR capture error at bit %d, saw 0x%s not 0x...3",
+				chain_pos, cbuf);
 		free(cbuf);
 		free(ir_test);
 		return ERROR_JTAG_INIT_FAILED;
@@ -1115,6 +1141,7 @@
 {
 	assert(0 != tap->ir_length);
 
+	/// @todo fix, this allocates one byte per bit for all three fields!
 	tap->expected = malloc(tap->ir_length);
 	tap->expected_mask = malloc(tap->ir_length);
 	tap->cur_instr = malloc(tap->ir_length);
@@ -1132,7 +1159,8 @@
 	LOG_DEBUG("Created Tap: %s @ abs position %d, "
 			"irlen %d, capture: 0x%x mask: 0x%x", tap->dotted_name,
 				tap->abs_chain_position, tap->ir_length,
-			  (unsigned int)(tap->ir_capture_value), (unsigned int)(tap->ir_capture_mask));
+				(unsigned) tap->ir_capture_value,
+				(unsigned) tap->ir_capture_mask);
 	jtag_tap_add(tap);
 }
 
@@ -1141,6 +1169,7 @@
 	jtag_unregister_event_callback(&jtag_reset_callback, tap);
 
 	/// @todo is anything missing? no memory leaks please
+	free((void *)tap->expected);
 	free((void *)tap->expected_ids);
 	free((void *)tap->chip);
 	free((void *)tap->tapname);
@@ -1212,9 +1241,9 @@
 		LOG_ERROR("trying to validate configured JTAG chain anyway...");
 	}
 
-	if (jtag_validate_chain() != ERROR_OK)
+	if (jtag_validate_ircapture() != ERROR_OK)
 	{
-		LOG_WARNING("Could not validate JTAG chain, continuing anyway...");
+		LOG_WARNING("Errors during IR capture, continuing anyway...");
 	}
 
 	return ERROR_OK;

[Openocd-svn] r2758 - in trunk: doc src/jtag

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-26 21:08:34 +0200 (Sat, 26 Sep 2009)
New Revision: 2758

Modified:
   trunk/doc/openocd.texi
   trunk/src/jtag/tcl.c
Log:
Streamline Capture-IR handling and integrity test.

Change the handling of the "-ircapture" and "-irmask" parameters
to be slightly more sensible, given that the JTAG spec describes
what is required, and that we already require that conformance in
one place.  IR scan returns some bitstring with LSBs "01".

 - First, provide and use default values that satisfy the IEEE spec.
   Existing TAP configs will override the defaults, but those parms
   are no longer required.

 - Second, warn if any TAP gets set up to violate the JTAG spec.
   It's likely a bug, but maybe not; else this should be an error.
   Improve the related diagnostics to say which TAP is affected.

And associated minor fixes/cleanups to comments and diagnostics.


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-09-25 17:02:59 UTC (rev 2757)
+++ trunk/doc/openocd.texi	2009-09-26 19:08:34 UTC (rev 2758)
@@ -2309,19 +2309,9 @@
 Every TAP requires at least the following @var{configparams}:
 
 @itemize @bullet
-@item @code{-ircapture} @var{NUMBER}
-@*The bit pattern loaded by the TAP into the JTAG shift register
-on entry to the @sc{ircapture} state, such as 0x01.
-JTAG requires the two LSBs of this value to be 01.
-The value is used to verify that instruction scans work correctly.
 @item @code{-irlen} @var{NUMBER}
 @*The length in bits of the
 instruction register, such as 4 or 5 bits.
-@item @code{-irmask} @var{NUMBER}
-@*A mask for the IR register.
-For some devices, there are bits in the IR that aren't used.
-This lets OpenOCD mask them off when doing IDCODE comparisons.
-In general, this should just be all ones for the size of the IR.
 @end itemize
 
 A TAP may also provide optional @var{configparams}:
@@ -2340,6 +2330,18 @@
 These codes are not required by all JTAG devices.
 @emph{Repeat the option} as many times as required if more than one
 ID code could appear (for example, multiple versions).
+@item @code{-ircapture} @var{NUMBER}
+@*The bit pattern loaded by the TAP into the JTAG shift register
+on entry to the @sc{ircapture} state, such as 0x01.
+JTAG requires the two LSBs of this value to be 01.
+By default, @code{-ircapture} and @code{-irmask} are set
+up to verify that two-bit value; but you may provide
+additional bits, if you know them.
+@item @code{-irmask} @var{NUMBER}
+@*A mask used with @code{-ircapture}
+to verify that instruction scans work correctly.
+Such scans are not used by OpenOCD except to verify that
+there seems to be no problems with JTAG scan chain operations.
 @end itemize
 @end deffn
 

Modified: trunk/src/jtag/tcl.c
===================================================================
--- trunk/src/jtag/tcl.c	2009-09-25 17:02:59 UTC (rev 2757)
+++ trunk/src/jtag/tcl.c	2009-09-26 19:08:34 UTC (rev 2758)
@@ -242,13 +242,15 @@
 	LOG_DEBUG("Creating New Tap, Chip: %s, Tap: %s, Dotted: %s, %d params",
 			  pTap->chip, pTap->tapname, pTap->dotted_name, goi->argc);
 
-	/* deal with options */
-#define NTREQ_IRLEN      1
-#define NTREQ_IRCAPTURE  2
-#define NTREQ_IRMASK     4
+	/* IEEE specifies that the two LSBs of an IR scan are 01, so make
+	 * that the default.  The "-irlen" and "-irmask" options are only
+	 * needed to cope with nonstandard TAPs, or to specify more bits.
+	 */
+	pTap->ir_capture_mask = 0x03;
+	pTap->ir_capture_value = 0x01;
 
-	/* clear them as we find them */
-	reqbits = (NTREQ_IRLEN | NTREQ_IRCAPTURE | NTREQ_IRMASK);
+	/* clear flags for "required options" them as we find them */
+	reqbits = 1;
 
 	while (goi->argc) {
 		e = Jim_GetOpt_Nvp(goi, opts, &n);
@@ -308,31 +310,39 @@
 			switch (n->value) {
 			case NTAP_OPT_IRLEN:
 				if (w > (jim_wide) (8 * sizeof(pTap->ir_capture_value)))
-					LOG_WARNING("huge IR length %d", (int) w);
+					LOG_WARNING("%s: huge IR length %d",
+							pTap->dotted_name,
+							(int) w);
 				pTap->ir_length = w;
-				reqbits &= (~(NTREQ_IRLEN));
+				reqbits = 0;
 				break;
 			case NTAP_OPT_IRMASK:
 				if (is_bad_irval(pTap->ir_length, w)) {
-					LOG_ERROR("IR mask %x too big",
+					LOG_ERROR("%s: IR mask %x too big",
+							pTap->dotted_name,
 							(int) w);
 					free((void *)pTap->dotted_name);
 					free(pTap);
 					return ERROR_FAIL;
 				}
+				if ((w & 3) != 3)
+					LOG_WARNING("%s: nonstandard IR mask",
+							pTap->dotted_name);
 				pTap->ir_capture_mask = w;
-				reqbits &= (~(NTREQ_IRMASK));
 				break;
 			case NTAP_OPT_IRCAPTURE:
 				if (is_bad_irval(pTap->ir_length, w)) {
-					LOG_ERROR("IR capture %x too big",
+					LOG_ERROR("%s: IR capture %x too big",
+							pTap->dotted_name,
 							(int) w);
 					free((void *)pTap->dotted_name);
 					free(pTap);
 					return ERROR_FAIL;
 				}
+				if ((w & 3) != 1)
+					LOG_WARNING("%s: nonstandard IR value",
+							pTap->dotted_name);
 				pTap->ir_capture_value = w;
-				reqbits &= (~(NTREQ_IRCAPTURE));
 				break;
 			}
 		} /* switch (n->value) */

[Openocd-svn] r2757 - trunk/tcl/target

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-25 19:02:59 +0200 (Fri, 25 Sep 2009)
New Revision: 2757

Modified:
   trunk/tcl/target/ti_dm355.cfg
Log:
Update DM355 target config to know about ICEpick.
Still defaults to nonstandard EMU0/EMU1 settings.


Modified: trunk/tcl/target/ti_dm355.cfg
===================================================================
--- trunk/tcl/target/ti_dm355.cfg	2009-09-25 16:48:15 UTC (rev 2756)
+++ trunk/tcl/target/ti_dm355.cfg	2009-09-25 17:02:59 UTC (rev 2757)
@@ -12,10 +12,17 @@
    set  _ENDIAN little
 }
 
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+#set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+set EMU01 "-enable"
+
+source [find target/icepick.cfg]
+
 #
-# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
-# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
-#
 # Also note:  when running without RTCK before the PLLs are set up, you
 # may need to slow the JTAG clock down quite a lot (under 2 MHz).
 #
@@ -26,7 +33,10 @@
 } else {
    set _ETB_TAPID 0x2b900f0f
 }
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID
+jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_ETB_TAPID $EMU01
+jtag configure $_CHIPNAME.etb -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 1"
 
 # Subsidiary TAP: ARM926ejs with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
 if { [info exists CPU_TAPID ] } {
@@ -34,7 +44,10 @@
 } else {
    set _CPU_TAPID 0x07926001
 }
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU_TAPID
+jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
+	-expected-id $_CPU_TAPID $EMU01
+jtag configure $_CHIPNAME.arm -event tap-enable \
+	"icepick_c_tapenable $_CHIPNAME.jrc 0"
 
 # Primary TAP: ICEpick (JTAG route controller) and boundary scan
 if { [info exists JRC_TAPID ] } {

[Openocd-svn] r2756 - in trunk/tcl: board target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-25 18:48:15 +0200 (Fri, 25 Sep 2009)
New Revision: 2756

Added:
   trunk/tcl/board/topas910.cfg
   trunk/tcl/board/topasa900.cfg
   trunk/tcl/target/tmpa900.cfg
   trunk/tcl/target/tmpa910.cfg
Log:
Michael Hasselberg <mh...@op...> target configuration files for Toshiba TX09 familiy

Added: trunk/tcl/board/topas910.cfg
===================================================================
--- trunk/tcl/board/topas910.cfg	2009-09-25 11:11:39 UTC (rev 2755)
+++ trunk/tcl/board/topas910.cfg	2009-09-25 16:48:15 UTC (rev 2756)
@@ -0,0 +1,118 @@
+######################################
+# Target:    Toshiba TOPAS910 -- TMPA910 Starterkit
+#
+######################################
+
+# We add to the minimal configuration.
+source [find target/tmpa910.cfg]
+
+######################
+# Target configuration
+######################
+
+#$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { topas910_init }
+
+proc topas910_init { } {
+# Init PLL
+# my settings
+	mww 0xf005000c 0x00000007
+	mww 0xf0050010 0x00000065
+	mww 0xf005000c 0x000000a7
+	sleep 10
+	mdw 0xf0050008
+	mww 0xf0050008 0x00000002
+	mww 0xf0050004 0x00000000
+# NEW: set CLKCR5
+	mww 0xf0050054 0x00000040
+#
+	sleep 10
+# Init SDRAM
+#  _PMCDRV          = 0x00000071;
+#  //
+#  // Initialize SDRAM timing paramater
+#  //
+#  _DMC_CAS_LATENCY = 0x00000006;
+#  _DMC_T_DQSS      = 0x00000000;
+#  _DMC_T_MRD       = 0x00000002;
+#  _DMC_T_RAS       = 0x00000007;
+#
+#  _DMC_T_RC        = 0x0000000A;
+#  _DMC_T_RCD       = 0x00000013;
+#
+#  _DMC_T_RFC       = 0x0000010A;
+#
+#  _DMC_T_RP        = 0x00000013;
+#  _DMC_T_RRD       = 0x00000002;
+#  _DMC_T_WR        = 0x00000002;
+#  _DMC_T_WTR       = 0x00000001;
+#  _DMC_T_XP        = 0x0000000A;
+#  _DMC_T_XSR       = 0x0000000B;
+#  _DMC_T_ESR       = 0x00000014;
+#
+#  //
+#  // Configure SDRAM type parameter
+#  _DMC_MEMORY_CFG  = 0x00008011;
+#  _DMC_USER_CONFIG = 0x00000011;   
+#  // 32 bit memory interface
+#
+#
+#  _DMC_REFRESH_PRD = 0x00000A60;
+#  _DMC_CHIP_0_CFG  = 0x000140FC;
+#
+#  _DMC_DIRECT_CMD  = 0x000C0000;
+#  _DMC_DIRECT_CMD  = 0x00000000;
+#
+#  _DMC_DIRECT_CMD  = 0x00040000;
+#  _DMC_DIRECT_CMD  = 0x00040000;
+#  _DMC_DIRECT_CMD  = 0x00080031;
+#  //
+#  // Finally start SDRAM
+#  //
+#  _DMC_MEMC_CMD    = MEMC_CMD_GO;
+#  */
+
+	mww 0xf0020260 0x00000071
+	mww 0xf4300014 0x00000006
+	mww 0xf4300018 0x00000000
+	mww 0xf430001C 0x00000002
+	mww 0xf4300020 0x00000007
+	mww 0xf4300024 0x0000000A
+	mww 0xf4300028 0x00000013
+	mww 0xf430002C 0x0000010A
+	mww 0xf4300030 0x00000013
+	mww 0xf4300034 0x00000002
+	mww 0xf4300038 0x00000002
+	mww 0xf430003C 0x00000001
+	mww 0xf4300040 0x0000000A
+	mww 0xf4300044 0x0000000B
+	mww 0xf4300048 0x00000014
+	mww 0xf430000C 0x00008011
+	mww 0xf4300304 0x00000011
+	mww 0xf4300010 0x00000A60
+	mww 0xf4300200 0x000140FC
+	mww 0xf4300008 0x000C0000
+	mww 0xf4300008 0x00000000
+	mww 0xf4300008 0x00040000
+	mww 0xf4300008 0x00040000
+	mww 0xf4300008 0x00080031
+	mww 0xf4300004 0x00000000
+
+	sleep 10
+#	jtag_speed 10000
+
+# remap off in case of IROM boot 
+	mww 0xf0000004 0x00000001
+
+}
+
+# comment the following out if usinf J-Link, it soes not support DCC
+arm7_9 dcc_downloads enable       # Enable faster DCC downloads
+
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank cfi <base> <size> <chip width> <bus width> <target#>
+flash bank cfi 0x20000000 0x2000000 2 2 0


Property changes on: trunk/tcl/board/topas910.cfg
___________________________________________________________________
Name: svn:eol-style
   + native

Added: trunk/tcl/board/topasa900.cfg
===================================================================
--- trunk/tcl/board/topasa900.cfg	2009-09-25 11:11:39 UTC (rev 2755)
+++ trunk/tcl/board/topasa900.cfg	2009-09-25 16:48:15 UTC (rev 2756)
@@ -0,0 +1,125 @@
+# Thanks to Pieter Conradie for this script! 
+# Target:    Toshiba TOPAS900 -- TMPA900 Starterkit
+######################################
+
+# We add to the minimal configuration.
+source [find target/tmpa900.cfg]
+
+######################
+# Target configuration
+######################
+
+#$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { topasa900_init }
+
+proc topasa900_init { } {
+# Init PLL
+# my settings
+	mww 0xf005000c 0x00000007
+	mww 0xf0050010 0x00000065
+	mww 0xf005000c 0x000000a7
+	sleep 10
+	mdw 0xf0050008
+	mww 0xf0050008 0x00000002
+	mww 0xf0050004 0x00000000
+# NEW: set CLKCR5
+	mww 0xf0050054 0x00000040
+#
+# bplan settings
+#	mww 0xf0050004 0x00000000
+#	mww 0xf005000c 0x000000a7
+#	sleep 10
+#	mdw 0xf0050008
+#	mww 0xf0050008 0x00000002
+#	mww 0xf0050010 0x00000065
+#	mww 0xf0050054 0x00000040
+	sleep 10
+# Init SDRAM
+#  _PMCDRV          = 0x00000071;
+#  //
+#  // Initialize SDRAM timing paramater
+#  //
+#  _DMC_CAS_LATENCY = 0x00000006;
+#  _DMC_T_DQSS      = 0x00000000;
+#  _DMC_T_MRD       = 0x00000002;
+#  _DMC_T_RAS       = 0x00000007;
+#
+#  _DMC_T_RC        = 0x0000000A;
+#  _DMC_T_RCD       = 0x00000013;
+#
+#  _DMC_T_RFC       = 0x0000010A;
+#
+#  _DMC_T_RP        = 0x00000013;
+#  _DMC_T_RRD       = 0x00000002;
+#  _DMC_T_WR        = 0x00000002;
+#  _DMC_T_WTR       = 0x00000001;
+#  _DMC_T_XP        = 0x0000000A;
+#  _DMC_T_XSR       = 0x0000000B;
+#  _DMC_T_ESR       = 0x00000014;
+#
+#  //
+#  // Configure SDRAM type parameter
+#  _DMC_MEMORY_CFG  = 0x00008011;
+#  _DMC_USER_CONFIG = 0x00000011;   // 32 bit memory interface
+#
+#
+#  _DMC_REFRESH_PRD = 0x00000A60;
+#  _DMC_CHIP_0_CFG  = 0x000140FC;
+#
+#  _DMC_DIRECT_CMD  = 0x000C0000;
+#  _DMC_DIRECT_CMD  = 0x00000000;
+#
+#  _DMC_DIRECT_CMD  = 0x00040000;
+#  _DMC_DIRECT_CMD  = 0x00040000;
+#  _DMC_DIRECT_CMD  = 0x00080031;
+#  //
+#  // Finally start SDRAM
+#  //
+#  _DMC_MEMC_CMD    = MEMC_CMD_GO;
+#  */
+
+	mww 0xf0020260 0x00000071
+	mww 0xf4300014 0x00000006
+	mww 0xf4300018 0x00000000
+	mww 0xf430001C 0x00000002
+	mww 0xf4300020 0x00000007
+	mww 0xf4300024 0x0000000A
+	mww 0xf4300028 0x00000013
+	mww 0xf430002C 0x0000010A
+	mww 0xf4300030 0x00000013
+	mww 0xf4300034 0x00000002
+	mww 0xf4300038 0x00000002
+	mww 0xf430003C 0x00000001
+	mww 0xf4300040 0x0000000A
+	mww 0xf4300044 0x0000000B
+	mww 0xf4300048 0x00000014
+	mww 0xf430000C 0x00008011
+	mww 0xf4300304 0x00000011
+	mww 0xf4300010 0x00000A60
+	mww 0xf4300200 0x000140FC
+	mww 0xf4300008 0x000C0000
+	mww 0xf4300008 0x00000000
+	mww 0xf4300008 0x00040000
+	mww 0xf4300008 0x00040000
+	mww 0xf4300008 0x00080031
+	mww 0xf4300004 0x00000000
+
+	sleep 10
+#	jtag_speed 10000
+
+# remap off in case of IROM boot 
+	mww 0xf0000004 0x00000001
+
+}
+
+# comment the following out if usinf J-Link, it soes not support DCC
+arm7_9 dcc_downloads enable       # Enable faster DCC downloads
+
+
+#####################
+# Flash configuration
+#####################
+
+#flash bank cfi <base> <size> <chip width> <bus width> <target#>
+flash bank cfi 0x20000000 0x1000000 2 2 0
+


Property changes on: trunk/tcl/board/topasa900.cfg
___________________________________________________________________
Name: svn:eol-style
   + native

Added: trunk/tcl/target/tmpa900.cfg
===================================================================
--- trunk/tcl/target/tmpa900.cfg	2009-09-25 11:11:39 UTC (rev 2755)
+++ trunk/tcl/target/tmpa900.cfg	2009-09-25 16:48:15 UTC (rev 2756)
@@ -0,0 +1,56 @@
+######################################
+# Target:    Toshiba TMPA910
+######################################
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME tmpa910
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0x07926031
+}
+
+#TMPA910 has following IDs:
+# CP15.0 register 0x41069265
+# CP15.1 register 0x1d152152
+# ARM core 0x07926031
+
+
+#
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+jtag_nsrst_delay 20
+jtag_ntrst_delay 20
+
+######################
+# Target configuration
+######################
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+
+# built-in RAM0
+#working_area 0 0xf8004000 0x4000 nobackup
+# built-in RAM1
+#working_area 1 0xf8008000 0x4000 nobackup
+# built-in RAM2
+#working_area 2 0xf800c000 0x4000 nobackup
+# built-in RAM 0-2 48k total
+#working_area 0 0xf8004000 0xc000 nobackup
+
+# Internal sram1 memory
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0xf8004000 -work-area-size 0x8000 \
+-work-area-backup 0


Property changes on: trunk/tcl/target/tmpa900.cfg
___________________________________________________________________
Name: svn:eol-style
   + native

Added: trunk/tcl/target/tmpa910.cfg
===================================================================
--- trunk/tcl/target/tmpa910.cfg	2009-09-25 11:11:39 UTC (rev 2755)
+++ trunk/tcl/target/tmpa910.cfg	2009-09-25 16:48:15 UTC (rev 2756)
@@ -0,0 +1,56 @@
+######################################
+# Target:    Toshiba TMPA910
+######################################
+
+if { [info exists CHIPNAME] } {	
+   set  _CHIPNAME $CHIPNAME    
+} else {	 
+   set  _CHIPNAME tmpa910
+}
+
+if { [info exists ENDIAN] } {	
+   set  _ENDIAN $ENDIAN    
+} else {	 
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+  # force an error till we get a good number
+   set _CPUTAPID 0x07926031
+}
+
+#TMPA910 has following IDs:
+# CP15.0 register 0x41069265
+# CP15.1 register 0x1d152152
+# ARM core 0x07926031
+
+
+#
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+jtag_nsrst_delay 20
+jtag_ntrst_delay 20
+
+######################
+# Target configuration
+######################
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+
+# built-in RAM0
+#working_area 0 0xf8004000 0x4000 nobackup
+# built-in RAM1
+#working_area 1 0xf8008000 0x4000 nobackup
+# built-in RAM2
+#working_area 2 0xf800c000 0x4000 nobackup
+# built-in RAM 0-2 48k total
+#working_area 0 0xf8004000 0xc000 nobackup
+
+# Internal sram1 memory
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0xf8004000 -work-area-size 0xc000 \
+-work-area-backup 0


Property changes on: trunk/tcl/target/tmpa910.cfg
___________________________________________________________________
Name: svn:eol-style
   + native

[Openocd-svn] r2755 - trunk/src/helper

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-25 13:11:39 +0200 (Fri, 25 Sep 2009)
New Revision: 2755

Modified:
   trunk/src/helper/log.c
   trunk/src/helper/log.h
Log:
Try/catch scheme. Typed up the functionality and regression tested.
Ready for discussion and tiny patches that tries out this scheme.

Modified: trunk/src/helper/log.c
===================================================================
--- trunk/src/helper/log.c	2009-09-24 06:34:23 UTC (rev 2754)
+++ trunk/src/helper/log.c	2009-09-25 11:11:39 UTC (rev 2755)
@@ -64,6 +64,95 @@
 
 static int count = 0;
 
+
+static struct store_log_forward * log_head = NULL;
+static int log_forward_count = 0;
+
+struct store_log_forward
+{
+	struct store_log_forward * next;
+	const char * file;
+	int line;
+	const char * function;
+	const char * string;
+};
+
+/* either forward the log to the listeners or store it for possible forwarding later */
+static void log_forward(const char *file, int line, const char *function, const char *string)
+{
+	if (log_forward_count==0)
+	{
+		log_callback_t *cb, *next;
+		cb = log_callbacks;
+		/* DANGER!!!! the log callback can remove itself!!!! */
+		while (cb)
+		{
+			next = cb->next;
+			cb->fn(cb->priv, file, line, function, string);
+			cb = next;
+		}
+	} else
+	{
+		struct store_log_forward *log = malloc(sizeof (struct store_log_forward));
+		log->file = strdup(file);
+		log->line = line;
+		log->function = strdup(function);
+		log->string = strdup(string);
+		log->next = NULL;
+		if (log_head==NULL)
+			log_head = log;
+		else
+		{
+			/* append to tail */
+			struct store_log_forward * t;
+			t = log_head;
+			while (t->next!=NULL)
+			{
+				t = t->next;
+			}
+			t->next = log;
+		}
+	}
+}
+
+void log_try(void)
+{
+	log_forward_count++;
+}
+
+void log_catch(void)
+{
+	assert(log_forward_count>0);
+	log_forward_count--;
+}
+
+void log_rethrow(void)
+{
+	log_catch();
+	if (log_forward_count==0)
+	{
+		struct store_log_forward *log;
+
+		log = log_head;
+		while (log != NULL)
+		{
+			log_forward(log->file, log->line, log->function, log->string);
+
+			struct store_log_forward *t=log;
+			log = log->next;
+
+			free((void *)t->file);
+			free((void *)t->function);
+			free((void *)t->string);
+			free(t);
+
+		}
+
+		log_head = NULL;
+	}
+}
+
+
 /* The log_puts() serves to somewhat different goals:
  *
  * - logging
@@ -131,18 +220,11 @@
 	/* Never forward LOG_LVL_DEBUG, too verbose and they can be found in the log if need be */
 	if (level <= LOG_LVL_INFO)
 	{
-		log_callback_t *cb, *next;
-		cb = log_callbacks;
-		/* DANGER!!!! the log callback can remove itself!!!! */
-		while (cb)
-		{
-			next = cb->next;
-			cb->fn(cb->priv, file, line, function, string);
-			cb = next;
-		}
+		log_forward(file, line, function, string);
 	}
 }
 
+
 void log_printf(enum log_levels level, const char *file, int line, const char *function, const char *format, ...)
 {
 	char *string;

Modified: trunk/src/helper/log.h
===================================================================
--- trunk/src/helper/log.h	2009-09-24 06:34:23 UTC (rev 2754)
+++ trunk/src/helper/log.h	2009-09-25 11:11:39 UTC (rev 2755)
@@ -64,6 +64,15 @@
 extern void alive_sleep(int ms);
 extern void busy_sleep(int ms);
 
+
+/* log entries can be paused and replayed roughly according to the try/catch/rethrow
+ * concepts in C++
+ */
+void log_try(void);
+void log_catch(void);
+void log_rethrow(void);
+
+
 typedef void (*log_callback_fn)(void *priv, const char *file, int line,
 		const char *function, const char *string);
 

[Openocd-svn] r2754 - trunk/src/server

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-24 08:34:23 +0200 (Thu, 24 Sep 2009)
New Revision: 2754

Modified:
   trunk/src/server/gdb_server.c
   trunk/src/server/gdb_server.h
Log:
When attaching GDB to OpenOCD, the target state is no longer affected.
Added gdb_sync feature that allows GDB to sync up to target state.
Issue "monitor gdb_sync" and the next stepi, will return immediately
with updated register values to GDB.


Modified: trunk/src/server/gdb_server.c
===================================================================
--- trunk/src/server/gdb_server.c	2009-09-23 22:03:41 UTC (rev 2753)
+++ trunk/src/server/gdb_server.c	2009-09-24 06:34:23 UTC (rev 2754)
@@ -40,6 +40,8 @@
 #define _DEBUG_GDB_IO_
 #endif
 
+static gdb_connection_t *current_gdb_connection;
+
 static int gdb_breakpoint_override;
 static enum breakpoint_type gdb_breakpoint_override_type;
 
@@ -750,6 +752,7 @@
 	gdb_connection->closed = 0;
 	gdb_connection->busy = 0;
 	gdb_connection->noack_mode = 0;
+	gdb_connection->sync = true;
 
 	/* send ACK to GDB for debug request */
 	gdb_write(connection, "+", 1);
@@ -767,30 +770,6 @@
 	/* register callback to be informed about target events */
 	target_register_event_callback(gdb_target_callback_event_handler, connection);
 
-	/* a gdb session just attached, try to put the target in halt mode.
-	 *
-	 * DANGER!!!!
-	 *
-	 * If the halt fails(e.g. target needs a reset, JTAG communication not
-	 * working, etc.), then the GDB connect will succeed as
-	 * the get_gdb_reg_list() will lie and return a register list with
-	 * dummy values.
-	 *
-	 * This allows GDB monitor commands to be run from a GDB init script to
-	 * initialize the target
-	 *
-	 * Also, since the halt() is asynchronous target connect will be
-	 * instantaneous and thus avoiding annoying timeout problems during
-	 * connect.
-	 */
-	target_halt(gdb_service->target);
-	/* FIX!!!! could extended-remote work better here?
-	 *
-	 *  wait a tiny bit for halted state or we just continue. The
-	 * GDB register packet will then contain garbage
-	 */
-	target_wait_state(gdb_service->target, TARGET_HALTED, 500);
-
 	/* remove the initial ACK from the incoming buffer */
 	if ((retval = gdb_get_char(connection, &initial_ack)) != ERROR_OK)
 		return retval;
@@ -1609,7 +1588,11 @@
 			/* We want to print all debug output to GDB connection */
 			log_add_callback(gdb_log_callback, connection);
 			target_call_timer_callbacks_now();
+			/* some commands need to know the GDB connection, make note of current
+			 * GDB connection. */
+			current_gdb_connection = gdb_connection;
 			command_run_line(cmd_ctx, cmd);
+			current_gdb_connection = NULL;
 			target_call_timer_callbacks_now();
 			log_remove_callback(gdb_log_callback, connection);
 			free(cmd);
@@ -2107,20 +2090,52 @@
 				case 'c':
 				case 's':
 					{
-						if (target->state != TARGET_HALTED)
+						int retval = ERROR_OK;
+
+						gdb_connection_t *gdb_con = connection->priv;
+						log_add_callback(gdb_log_callback, connection);
+
+						bool nostep = false;
+						if (target->state == TARGET_RUNNING)
 						{
-							/* If the target isn't in the halted state, then we can't
+							LOG_WARNING("The target is already running. Halt target before stepi/continue.");
+							retval = target_halt(target);
+							if (retval == ERROR_OK)
+								retval = target_wait_state(target, TARGET_HALTED, 100);
+						} else if (target->state != TARGET_HALTED)
+						{
+							LOG_WARNING("The target is not in the halted nor running stated, stepi/continue ignored.");
+							nostep = true;
+						} else if ((packet[0] == 's') && gdb_con->sync)
+						{
+							/* Hmm..... when you issue a continue in GDB, then a "stepi" is
+							 * sent by GDB first to OpenOCD, thus defeating the check to
+							 * make only the single stepping have the sync feature...
+							 */
+							nostep = true;
+							LOG_WARNING("stepi ignored. GDB will now fetch the register state from the target.");
+						}
+						gdb_con->sync = false;
+
+						if ((retval!=ERROR_OK) || nostep)
+						{
+							/* Either the target isn't in the halted state, then we can't
 							 * step/continue. This might be early setup, etc.
+							 *
+							 * Or we want to allow GDB to pick up a fresh set of
+							 * register values without modifying the target state.
+							 *
 							 */
 							gdb_sig_halted(connection);
+
+							/* stop forwarding log packets! */
+							log_remove_callback(gdb_log_callback, connection);
 						} else
 						{
 							/* We're running/stepping, in which case we can
 							 * forward log output until the target is halted
 							 */
-							gdb_connection_t *gdb_con = connection->priv;
 							gdb_con->frontend_state = TARGET_RUNNING;
-							log_add_callback(gdb_log_callback, connection);
 							target_call_event_callbacks(target, TARGET_EVENT_GDB_START);
 							int retval = gdb_step_continue_packet(connection, target, packet, packet_size);
 							if (retval != ERROR_OK)
@@ -2255,6 +2270,25 @@
 	return ERROR_OK;
 }
 
+int handle_gdb_sync_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+	if (argc != 0)
+	{
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+
+	if (current_gdb_connection == NULL)
+	{
+		command_print(cmd_ctx,
+				"gdb_sync command can only be run from within gdb using \"monitor gdb_sync\"");
+		return ERROR_FAIL;
+	}
+
+	current_gdb_connection->sync = true;
+
+	return ERROR_OK;
+}
+
 /* daemon configuration command gdb_port */
 int handle_gdb_port_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
@@ -2399,6 +2433,8 @@
 
 int gdb_register_commands(command_context_t *command_context)
 {
+	register_command(command_context, NULL, "gdb_sync", handle_gdb_sync_command,
+			COMMAND_ANY, "next stepi will return immediately allowing GDB fetch register state without affecting target state");
 	register_command(command_context, NULL, "gdb_port", handle_gdb_port_command,
 			COMMAND_ANY, "daemon configuration command gdb_port");
 	register_command(command_context, NULL, "gdb_detach", handle_gdb_detach_command,

Modified: trunk/src/server/gdb_server.h
===================================================================
--- trunk/src/server/gdb_server.h	2009-09-23 22:03:41 UTC (rev 2753)
+++ trunk/src/server/gdb_server.h	2009-09-24 06:34:23 UTC (rev 2754)
@@ -43,6 +43,10 @@
 	int closed;
 	int busy;
 	int noack_mode;
+	bool sync; 	/* set flag to true if you want the next stepi to return immediately.
+	               allowing GDB to pick up a fresh set of register values from the target
+	               without modifying the target state. */
+
 } gdb_connection_t;
 
 typedef struct gdb_service_s

[Openocd-svn] r2753 - trunk/src/helper

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-24 00:03:41 +0200 (Thu, 24 Sep 2009)
New Revision: 2753

Modified:
   trunk/src/helper/startup.tcl
Log:
Start handling the (second) SRST stage of reset better:
make sure that when there are two or more targets, their
various pre/post event reports are correctly ordered.

Previously, only the first target always saw its "pre"
method before SRST was asserted or deasserted.


Modified: trunk/src/helper/startup.tcl
===================================================================
--- trunk/src/helper/startup.tcl	2009-09-23 21:52:40 UTC (rev 2752)
+++ trunk/src/helper/startup.tcl	2009-09-23 22:03:41 UTC (rev 2753)
@@ -202,27 +202,32 @@
 	}
 
 	# Assert SRST, and report the pre/post events.
-	#
-	# REVISIT this presumes a single-target config, since SRST
-	# applies to the whole device-under-test.  When two targets
-	# both need special setup before SRST, it's only done for
-	# the first one...
+	# Note:  no target sees SRST before "pre" or after "post".
 	foreach t $targets {
 		$t invoke-event reset-assert-pre
+	}
+	foreach t $targets {
 		# C code needs to know if we expect to 'halt'
 		if {[jtag tapisenabled [$t cget -chain-position]]} {
 			$t arp_reset assert $halt
 		}
+	}
+	foreach t $targets {
 		$t invoke-event reset-assert-post
 	}
 
 	# Now de-assert SRST, and report the pre/post events.
+	# Note:  no target sees !SRST before "pre" or after "post".
 	foreach t $targets {
 		$t invoke-event reset-deassert-pre
-		# Again, de-assert code needs to know..
+	}
+	foreach t $targets {
+		# Again, de-assert code needs to know if we 'halt'
 		if {[jtag tapisenabled [$t cget -chain-position]]} {
 			$t arp_reset deassert $halt
 		}
+	}
+	foreach t $targets {
 		$t invoke-event reset-deassert-post
 	}
 

[Openocd-svn] r2752 - in trunk: doc src/target

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-23 23:52:40 +0200 (Wed, 23 Sep 2009)
New Revision: 2752

Modified:
   trunk/doc/openocd.texi
   trunk/src/target/etm.c
   trunk/src/target/etm.h
Log:
When setting up an ETM, cache its ETM_CONFIG register.  Then
only expose the registers which are actually present.  They
could be missing for two basic reasons:

 - This version might not support them at all; e.g. ETMv1.1
   doesn't have some control/status registers.  (My sample of
   ARM9 boards shows all with ETMv1.3 support, FWIW.)

 - The configuration on this chip may not populate as many
   registers as possible; e.g. only two data value comparators
   instead of eight.

Includes a bugfix in the "etm info" command:  only one of the
two registers is missing on older silicon, so show the first
one before bailing.

Update ETM usage docs to explain that those registers need to be
written to configure what is traced, and that some ETM configs
are not yet handled.  Also, give some examples of the kinds of
constrained trace which could be arranged.


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-09-23 09:16:00 UTC (rev 2751)
+++ trunk/doc/openocd.texi	2009-09-23 21:52:40 UTC (rev 2752)
@@ -4807,6 +4807,10 @@
 It's unclear how much of a common interface is shared
 with the current XScale trace support, or should be
 shared with eventual Nexus-style trace module support.
+At this writing (September 2009) only ARM7 and ARM9 support
+for ETM modules is available.  The code should be able to
+work with some newer cores; but not all of them support
+this original style of JTAG access.
 @end quotation
 
 @subsection ETM Configuration
@@ -4823,8 +4827,10 @@
 The @var{clocking} must be @option{half} or @option{full}.
 
 @quotation Note
-You can see the ETM registers using the @command{reg} command, although
-not all of those possible registers are present in every ETM.
+You can see the ETM registers using the @command{reg} command.
+Not all possible registers are present in every ETM.
+Most of the registers are write-only, and are used to configure
+what CPU activities are traced.
 @end quotation
 @end deffn
 
@@ -4867,6 +4873,36 @@
 That data can be exported to files for later analysis.
 It can also be parsed with OpenOCD, for basic sanity checking.
 
+To configure what is being traced, you will need to write
+various trace registers using @command{reg ETM_*} commands.
+For the definitions of these registers, read ARM publication
+@emph{IHI 0014, ``Embedded Trace Macrocell, Architecture Specification''}.
+Be aware that most of the relevant registers are write-only,
+and that ETM resources are limited.  There are only a handful
+of address comparators, data comparators, counters, and so on.
+
+Examples of scenarios you might arrange to trace include:
+
+@itemize
+@item Code flow within a function, @emph{excluding} subroutines
+it calls.  Use address range comparators to enable tracing
+for instruction access within that function's body.
+@item Code flow within a function, @emph{including} subroutines
+it calls.  Use the sequencer and address comparators to activate
+tracing on an ``entered function'' state, then deactivate it by
+exiting that state when the function's exit code is invoked.
+@item Code flow starting at the fifth invocation of a function,
+combining one of the above models with a counter.
+@item CPU data accesses to the registers for a particular device,
+using address range comparators and the ViewData logic.
+@item Such data accesses only during IRQ handling, combining the above
+model with sequencer triggers which on entry and exit to the IRQ handler.
+@item @emph{... more}
+@end itemize
+
+At this writing, September 2009, there are no Tcl utility
+procedures to help set up any common tracing scenarios.
+
 @deffn Command {etm analyze}
 Reads trace data into memory, if it wasn't already present.
 Decodes and prints the data that was collected.

Modified: trunk/src/target/etm.c
===================================================================
--- trunk/src/target/etm.c	2009-09-23 09:16:00 UTC (rev 2751)
+++ trunk/src/target/etm.c	2009-09-23 21:52:40 UTC (rev 2752)
@@ -71,10 +71,14 @@
  * Newer versions of ETM make some W/O registers R/W, and
  * provide definitions for some previously-unused bits.
  */
-static const struct etm_reg_info reg[] = {
+
+/* basic registers that are always there given the right ETM version */
+static const struct etm_reg_info etm_core[] = {
+	/* NOTE: we "know" ETM_CONFIG is listed first */
+	{ ETM_CONFIG, 32, RO, 0x10, "ETM_CONFIG", },
+
 	/* ETM Trace Registers */
 	{ ETM_CTRL, 32, RW, 0x10, "ETM_CTRL", },
-	{ ETM_CONFIG, 32, RO, 0x10, "ETM_CONFIG", },
 	{ ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_TRIG_EVENT", },
 	{ ETM_ASIC_CTRL,  8, WO, 0x10, "ETM_ASIC_CTRL", },
 	{ ETM_STATUS,  3, RO, 0x11, "ETM_STATUS", },
@@ -86,16 +90,25 @@
 	{ ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_TRACE_EN_EVENT", },
 	{ ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_TRACE_EN_CTRL1", },
 
-	/* FIFOFULL configuration */
-	{ ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_FIFOFULL_REGION", },
-	{ ETM_FIFOFULL_LEVEL,  8, WO, 0x10, "ETM_FIFOFULL_LEVEL", },
-
 	/* ViewData configuration (data trace) */
 	{ ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_VIEWDATA_EVENT", },
 	{ ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_VIEWDATA_CTRL1", },
 	{ ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_VIEWDATA_CTRL2", },
 	{ ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_VIEWDATA_CTRL3", },
 
+	/* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
+
+	{ 0x78, 12, WO, 0x20, "ETM_SYNC_FREQ", },
+	{ 0x79, 32, RO, 0x20, "ETM_ID", },
+};
+
+static const struct etm_reg_info etm_fifofull[] = {
+	/* FIFOFULL configuration */
+	{ ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_FIFOFULL_REGION", },
+	{ ETM_FIFOFULL_LEVEL,  8, WO, 0x10, "ETM_FIFOFULL_LEVEL", },
+};
+
+static const struct etm_reg_info etm_addr_comp[] = {
 	/* Address comparator register pairs */
 #define ADDR_COMPARATOR(i) \
 		{ ETM_ADDR_COMPARATOR_VALUE + (i), 32, WO, 0x10, \
@@ -120,7 +133,9 @@
 	ADDR_COMPARATOR(14),
 	ADDR_COMPARATOR(15),
 #undef ADDR_COMPARATOR
+};
 
+static const struct etm_reg_info etm_data_comp[] = {
 	/* Data Value Comparators (NOTE: odd addresses are reserved) */
 #define DATA_COMPARATOR(i) \
 		{ ETM_DATA_COMPARATOR_VALUE + 2*(i), 32, WO, 0x10, \
@@ -136,8 +151,9 @@
 	DATA_COMPARATOR(6),
 	DATA_COMPARATOR(7),
 #undef DATA_COMPARATOR
+};
 
-	/* Counters */
+static const struct etm_reg_info etm_counters[] = {
 #define COUNTER(i) \
 		{ ETM_COUNTER_RELOAD_VALUE + (i), 16, WO, 0x10, \
 				"ETM_COUNTER_RELOAD_VALUE" #i, }, \
@@ -152,8 +168,9 @@
 	COUNTER(2),
 	COUNTER(3),
 #undef COUNTER
+};
 
-	/* Sequencers */
+static const struct etm_reg_info etm_sequencer[] = {
 #define SEQ(i) \
 		{ ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
 				"ETM_SEQUENCER_EVENT" #i, }
@@ -166,7 +183,9 @@
 #undef SEQ
 	/* 0x66 reserved */
 	{ ETM_SEQUENCER_STATE,  2, RO, 0x10, "ETM_SEQUENCER_STATE", },
+};
 
+static const struct etm_reg_info etm_outputs[] = {
 #define OUT(i) \
 		{ ETM_EXTERNAL_OUTPUT + (i), 17, WO, 0x10, \
 				"ETM_EXTERNAL_OUTPUT" #i, }
@@ -176,6 +195,7 @@
 	OUT(2),
 	OUT(3),
 #undef OUT
+};
 
 #if 0
 	/* registers from 0x6c..0x7f were added after ETMv1.3 */
@@ -185,11 +205,7 @@
 	{ 0x6d, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
 	{ 0x6e, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
 	{ 0x6f, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_MASK", }
-
-	{ 0x78, 12, WO, 0x20, "ETM_SYNC_FREQ", },
-	{ 0x79, 32, RO, 0x20, "ETM_ID", },
 #endif
-};
 
 static int etm_reg_arch_type = -1;
 
@@ -224,44 +240,138 @@
 	return NULL;
 }
 
+static void etm_reg_add(unsigned bcd_vers, arm_jtag_t *jtag_info,
+		reg_cache_t *cache, etm_reg_t *ereg,
+		const struct etm_reg_info *r, unsigned nreg)
+{
+	reg_t *reg = cache->reg_list;
+
+	reg += cache->num_regs;
+	ereg += cache->num_regs;
+
+	/* add up to "nreg" registers from "r", if supported by this
+	 * version of the ETM, to the specified cache.
+	 */
+	for (; nreg--; r++) {
+
+		/* this ETM may be too old to have some registers */
+		if (r->bcd_vers > bcd_vers)
+			continue;
+
+		reg->name = r->name;
+		reg->size = r->size;
+		reg->value = &ereg->value;
+		reg->arch_info = ereg;
+		reg->arch_type = etm_reg_arch_type;
+		reg++;
+		cache->num_regs++;
+
+		ereg->reg_info = r;
+		ereg->jtag_info = jtag_info;
+		ereg++;
+	}
+}
+
 reg_cache_t *etm_build_reg_cache(target_t *target,
 		arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
 {
 	reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 	reg_t *reg_list = NULL;
 	etm_reg_t *arch_info = NULL;
-	int num_regs = ARRAY_SIZE(reg);
-	int i;
+	unsigned bcd_vers, config;
 
 	/* register a register arch-type for etm registers only once */
 	if (etm_reg_arch_type == -1)
-		etm_reg_arch_type = register_reg_arch_type(etm_get_reg, etm_set_reg_w_exec);
+		etm_reg_arch_type = register_reg_arch_type(etm_get_reg,
+				etm_set_reg_w_exec);
 
 	/* the actual registers are kept in two arrays */
-	reg_list = calloc(num_regs, sizeof(reg_t));
-	arch_info = calloc(num_regs, sizeof(etm_reg_t));
+	reg_list = calloc(128, sizeof(reg_t));
+	arch_info = calloc(128, sizeof(etm_reg_t));
 
 	/* fill in values for the reg cache */
 	reg_cache->name = "etm registers";
 	reg_cache->next = NULL;
 	reg_cache->reg_list = reg_list;
-	reg_cache->num_regs = num_regs;
+	reg_cache->num_regs = 0;
 
-	/* set up registers */
-	for (i = 0; i < num_regs; i++)
-	{
-		const struct etm_reg_info *r = reg + i;
+	/* add ETM_CONFIG, then parse its values to see
+	 * which other registers exist in this ETM
+	 */
+	etm_reg_add(0x10, jtag_info, reg_cache, arch_info,
+			etm_core, 1);
 
-		reg_list[i].name = r->name;
-		reg_list[i].size = r->size;
-		reg_list[i].value = &arch_info[i].value;
-		reg_list[i].arch_info = &arch_info[i];
-		reg_list[i].arch_type = etm_reg_arch_type;
+	etm_get_reg(reg_list);
+	etm_ctx->config = buf_get_u32((void *)&arch_info->value, 0, 32);
+	config = etm_ctx->config;
 
-		arch_info[i].reg_info = r;
-		arch_info[i].jtag_info = jtag_info;
+	/* figure ETM version then add base registers */
+	if (config & (1 << 31)) {
+		bcd_vers = 0x20;
+		LOG_WARNING("ETMv2+ support is incomplete");
+
+		/* REVISIT read ID register, distinguish ETMv3.3 etc;
+		 * don't presume trace start/stop support is present;
+		 * and include any context ID comparator registers.
+		 */
+	} else {
+		switch (config >> 28) {
+		case 7:
+		case 5:
+		case 3:
+			bcd_vers = 0x13;
+			break;
+		case 4:
+		case 2:
+			bcd_vers = 0x12;
+			break;
+		case 1:
+			bcd_vers = 0x11;
+			break;
+		case 0:
+			bcd_vers = 0x10;
+			break;
+		default:
+			LOG_WARNING("Bad ETMv1 protocol %d", config >> 28);
+			free(reg_cache);
+			free(reg_list);
+			free(arch_info);
+			return ERROR_OK;
+		}
 	}
+	etm_ctx->bcd_vers = bcd_vers;
+	LOG_INFO("ETM v%d.%d", bcd_vers >> 4, bcd_vers & 0xf);
 
+	etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
+			etm_core + 1, ARRAY_SIZE(etm_core) - 1);
+
+	/* address and data comparators; counters; outputs */
+	etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
+			etm_addr_comp, 4 * (0x0f & (config >> 0)));
+	etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
+			etm_data_comp, 2 * (0x0f & (config >> 4)));
+	etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
+			etm_counters, 4 * (0x07 & (config >> 13)));
+	etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
+			etm_outputs, (0x07 & (config >> 20)));
+
+	/* FIFOFULL presence is optional
+	 * REVISIT for ETMv1.2 and later, don't bother adding this
+	 * unless ETM_SYS_CONFIG says it's also *supported* ...
+	 */
+	if (config & (1 << 23))
+		etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
+				etm_fifofull, ARRAY_SIZE(etm_fifofull));
+
+	/* sequencer is optional (for state-dependant triggering) */
+	if (config & (1 << 16))
+		etm_reg_add(bcd_vers, jtag_info, reg_cache, arch_info,
+				etm_sequencer, ARRAY_SIZE(etm_sequencer));
+
+	/* REVISIT could realloc and likely save half the memory
+	 * in the two chunks we allocated...
+	 */
+
 	/* the ETM might have an ETB connected */
 	if (strcmp(etm_ctx->capture_driver->name, "etb") == 0)
 	{
@@ -271,6 +381,7 @@
 		{
 			LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
 			free(reg_cache);
+			free(reg_list);
 			free(arch_info);
 			return ERROR_OK;
 		}
@@ -1362,7 +1473,7 @@
 	target_t *target;
 	armv4_5_common_t *armv4_5;
 	arm7_9_common_t *arm7_9;
-	reg_t *etm_config_reg;
+	etm_context_t *etm;
 	reg_t *etm_sys_config_reg;
 
 	int max_port_size;
@@ -1375,32 +1486,46 @@
 		return ERROR_OK;
 	}
 
-	if (!arm7_9->etm_ctx)
+	etm = arm7_9->etm_ctx;
+	if (!etm)
 	{
 		command_print(cmd_ctx, "current target doesn't have an ETM configured");
 		return ERROR_OK;
 	}
 
-	etm_config_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_CONFIG);
-	if (!etm_config_reg)
-		return ERROR_OK;
-	etm_sys_config_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_SYS_CONFIG);
+	command_print(cmd_ctx, "ETM v%d.%d",
+			etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
+	command_print(cmd_ctx, "pairs of address comparators: %i",
+			(etm->config >> 0) & 0x0f);
+	command_print(cmd_ctx, "data comparators: %i",
+			(etm->config >> 4) & 0x0f);
+	command_print(cmd_ctx, "memory map decoders: %i",
+			(etm->config >> 8) & 0x1f);
+	command_print(cmd_ctx, "number of counters: %i",
+			(etm->config >> 13) & 0x07);
+	command_print(cmd_ctx, "sequencer %spresent",
+			(etm->config & (1 << 16)) ? "" : "not ");
+	command_print(cmd_ctx, "number of ext. inputs: %i",
+			(etm->config >> 17) & 0x07);
+	command_print(cmd_ctx, "number of ext. outputs: %i",
+			(etm->config >> 20) & 0x07);
+	command_print(cmd_ctx, "FIFO full %spresent",
+			(etm->config & (1 << 23)) ? "" : "not ");
+	if (etm->bcd_vers < 0x20)
+		command_print(cmd_ctx, "protocol version: %i",
+				(etm->config >> 28) & 0x07);
+	else {
+		command_print(cmd_ctx, "trace start/stop %spresent",
+				(etm->config & (1 << 26)) ? "" : "not ");
+		command_print(cmd_ctx, "number of context comparators: %i",
+				(etm->config >> 24) & 0x03);
+	}
+
+	/* SYS_CONFIG isn't present before ETMv1.2 */
+	etm_sys_config_reg = etm_reg_lookup(etm, ETM_SYS_CONFIG);
 	if (!etm_sys_config_reg)
 		return ERROR_OK;
 
-	etm_get_reg(etm_config_reg);
-	command_print(cmd_ctx, "pairs of address comparators: %i", (int)buf_get_u32(etm_config_reg->value, 0, 4));
-	command_print(cmd_ctx, "pairs of data comparators: %i", (int)buf_get_u32(etm_config_reg->value, 4, 4));
-	command_print(cmd_ctx, "memory map decoders: %i", (int)buf_get_u32(etm_config_reg->value, 8, 5));
-	command_print(cmd_ctx, "number of counters: %i", (int)buf_get_u32(etm_config_reg->value, 13, 3));
-	command_print(cmd_ctx, "sequencer %spresent",
-			(buf_get_u32(etm_config_reg->value, 16, 1) == 1) ? "" : "not ");
-	command_print(cmd_ctx, "number of ext. inputs: %i", (int)buf_get_u32(etm_config_reg->value, 17, 3));
-	command_print(cmd_ctx, "number of ext. outputs: %i",(int) buf_get_u32(etm_config_reg->value, 20, 3));
-	command_print(cmd_ctx, "FIFO full %spresent",
-			(buf_get_u32(etm_config_reg->value, 23, 1) == 1) ? "" : "not ");
-	command_print(cmd_ctx, "protocol version: %i", (int)buf_get_u32(etm_config_reg->value, 28, 3));
-
 	etm_get_reg(etm_sys_config_reg);
 
 	switch (buf_get_u32(etm_sys_config_reg->value, 0, 3))

Modified: trunk/src/target/etm.h
===================================================================
--- trunk/src/target/etm.h	2009-09-23 09:16:00 UTC (rev 2751)
+++ trunk/src/target/etm.h	2009-09-23 21:52:40 UTC (rev 2752)
@@ -165,6 +165,8 @@
 	bool data_half;			/* port half on a 16 bit port */
 	bool pc_ok;			/* full PC has been acquired */
 	bool ptr_ok;			/* whether last_ptr is valid */
+	uint8_t bcd_vers;		/* e.g. 0x13 == ETMv1.3 */
+	uint32_t config;		/* cache of ETM_CONFIG value */
 	uint32_t current_pc;		/* current program counter */
 	uint32_t last_branch;		/* last branch address output */
 	uint32_t last_branch_reason;	/* type of last branch encountered */

[Openocd-svn] r2751 - trunk/src/target

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-23 11:16:00 +0200 (Wed, 23 Sep 2009)
New Revision: 2751

Modified:
   trunk/src/target/etm.c
   trunk/src/target/etm.h
Log:
Start cleaning up ETM register handling.  On one ARM926 ETM+ETB
system, removes 20 non-existent registers ... but still includes
over 45 (!) ETM registers which don't even exist there ...

 - Integrate the various tables to get one struct per register
 - Get rid of needless per-register dynamic allocation
 - Double check list of registers:
    * Remove sixteen (!) non-registers for data comparators
    * Remove four registers that imply newer ETM than we support
    * Change some names to match current architecture specs
 - Handle more register info
    * some are write-only
    * some are read-only
    * record which versions have them, just in case
 - Reorganize the registers to facilitate removing the extras
    * group e.g. comparator/counter #N registers together
    * add and use lookup-by-ID


Modified: trunk/src/target/etm.c
===================================================================
--- trunk/src/target/etm.c	2009-09-23 07:49:38 UTC (rev 2750)
+++ trunk/src/target/etm.c	2009-09-23 09:16:00 UTC (rev 2751)
@@ -50,155 +50,145 @@
  *  ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
  */
 
-static int etm_reg_arch_info[] =
-{
-	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
-	0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
-	0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
-	0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f,
-	0x20, 0x21, 0x22, 0x23, 0x24, 0x25, 0x26, 0x27,
-	0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f,
-	0x30, 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37,
-	0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
-	0x40, 0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47,
-	0x48, 0x49, 0x4a, 0x4b, 0x4c, 0x4d, 0x4e, 0x4f,
-	0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57,
-	0x58, 0x59, 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f,
-	0x60, 0x61, 0x62, 0x63, 0x64, 0x65, 0x67,
-	0x68, 0x69, 0x6a, 0x6b, 0x6c, 0x6d, 0x6e, 0x6f,
+#define ARRAY_SIZE(x)	((int)(sizeof(x)/sizeof((x)[0])))
+
+enum {
+	RO,				/* read/only */
+	WO,				/* write/only */
+	RW,				/* read/write */
 };
 
-static int etm_reg_arch_size_info[] =
-{
-	32, 32, 17, 8, 3, 9, 32, 16,
-	17, 26, 25, 8, 17, 32, 32, 17,
-	32, 32, 32, 32, 32, 32, 32, 32,
-	32, 32, 32, 32, 32, 32, 32, 32,
-	7, 7, 7, 7, 7, 7, 7, 7,
-	7, 7, 7, 7, 7, 7, 7, 7,
-	32, 32, 32, 32, 32, 32, 32, 32,
-	32, 32, 32, 32, 32, 32, 32, 32,
-	32, 32, 32, 32, 32, 32, 32, 32,
-	32, 32, 32, 32, 32, 32, 32, 32,
-	16, 16, 16, 16, 18, 18, 18, 18,
-	17, 17, 17, 17, 16, 16, 16, 16,
-	17, 17, 17, 17, 17, 17, 2,
-	17, 17, 17, 17, 32, 32, 32, 32
+struct etm_reg_info {
+	uint8_t		addr;
+	uint8_t		size;		/* low-N of 32 bits */
+	uint8_t		mode;		/* RO, WO, RW */
+	uint8_t		bcd_vers;	/* 1.0, 2.0, etc */
+	char		*name;
 };
 
-static char* etm_reg_list[] =
-{
-	"ETM_CTRL",
-	"ETM_CONFIG",
-	"ETM_TRIG_EVENT",
-	"ETM_MMD_CTRL",
-	"ETM_STATUS",
-	"ETM_SYS_CONFIG",
-	"ETM_TRACE_RESOURCE_CTRL",
-	"ETM_TRACE_EN_CTRL2",
-	"ETM_TRACE_EN_EVENT",
-	"ETM_TRACE_EN_CTRL1",
-	"ETM_FIFOFULL_REGION",
-	"ETM_FIFOFULL_LEVEL",
-	"ETM_VIEWDATA_EVENT",
-	"ETM_VIEWDATA_CTRL1",
-	"ETM_VIEWDATA_CTRL2",
-	"ETM_VIEWDATA_CTRL3",
-	"ETM_ADDR_COMPARATOR_VALUE1",
-	"ETM_ADDR_COMPARATOR_VALUE2",
-	"ETM_ADDR_COMPARATOR_VALUE3",
-	"ETM_ADDR_COMPARATOR_VALUE4",
-	"ETM_ADDR_COMPARATOR_VALUE5",
-	"ETM_ADDR_COMPARATOR_VALUE6",
-	"ETM_ADDR_COMPARATOR_VALUE7",
-	"ETM_ADDR_COMPARATOR_VALUE8",
-	"ETM_ADDR_COMPARATOR_VALUE9",
-	"ETM_ADDR_COMPARATOR_VALUE10",
-	"ETM_ADDR_COMPARATOR_VALUE11",
-	"ETM_ADDR_COMPARATOR_VALUE12",
-	"ETM_ADDR_COMPARATOR_VALUE13",
-	"ETM_ADDR_COMPARATOR_VALUE14",
-	"ETM_ADDR_COMPARATOR_VALUE15",
-	"ETM_ADDR_COMPARATOR_VALUE16",
-	"ETM_ADDR_ACCESS_TYPE1",
-	"ETM_ADDR_ACCESS_TYPE2",
-	"ETM_ADDR_ACCESS_TYPE3",
-	"ETM_ADDR_ACCESS_TYPE4",
-	"ETM_ADDR_ACCESS_TYPE5",
-	"ETM_ADDR_ACCESS_TYPE6",
-	"ETM_ADDR_ACCESS_TYPE7",
-	"ETM_ADDR_ACCESS_TYPE8",
-	"ETM_ADDR_ACCESS_TYPE9",
-	"ETM_ADDR_ACCESS_TYPE10",
-	"ETM_ADDR_ACCESS_TYPE11",
-	"ETM_ADDR_ACCESS_TYPE12",
-	"ETM_ADDR_ACCESS_TYPE13",
-	"ETM_ADDR_ACCESS_TYPE14",
-	"ETM_ADDR_ACCESS_TYPE15",
-	"ETM_ADDR_ACCESS_TYPE16",
-	"ETM_DATA_COMPARATOR_VALUE1",
-	"ETM_DATA_COMPARATOR_VALUE2",
-	"ETM_DATA_COMPARATOR_VALUE3",
-	"ETM_DATA_COMPARATOR_VALUE4",
-	"ETM_DATA_COMPARATOR_VALUE5",
-	"ETM_DATA_COMPARATOR_VALUE6",
-	"ETM_DATA_COMPARATOR_VALUE7",
-	"ETM_DATA_COMPARATOR_VALUE8",
-	"ETM_DATA_COMPARATOR_VALUE9",
-	"ETM_DATA_COMPARATOR_VALUE10",
-	"ETM_DATA_COMPARATOR_VALUE11",
-	"ETM_DATA_COMPARATOR_VALUE12",
-	"ETM_DATA_COMPARATOR_VALUE13",
-	"ETM_DATA_COMPARATOR_VALUE14",
-	"ETM_DATA_COMPARATOR_VALUE15",
-	"ETM_DATA_COMPARATOR_VALUE16",
-	"ETM_DATA_COMPARATOR_MASK1",
-	"ETM_DATA_COMPARATOR_MASK2",
-	"ETM_DATA_COMPARATOR_MASK3",
-	"ETM_DATA_COMPARATOR_MASK4",
-	"ETM_DATA_COMPARATOR_MASK5",
-	"ETM_DATA_COMPARATOR_MASK6",
-	"ETM_DATA_COMPARATOR_MASK7",
-	"ETM_DATA_COMPARATOR_MASK8",
-	"ETM_DATA_COMPARATOR_MASK9",
-	"ETM_DATA_COMPARATOR_MASK10",
-	"ETM_DATA_COMPARATOR_MASK11",
-	"ETM_DATA_COMPARATOR_MASK12",
-	"ETM_DATA_COMPARATOR_MASK13",
-	"ETM_DATA_COMPARATOR_MASK14",
-	"ETM_DATA_COMPARATOR_MASK15",
-	"ETM_DATA_COMPARATOR_MASK16",
-	"ETM_COUNTER_INITAL_VALUE1",
-	"ETM_COUNTER_INITAL_VALUE2",
-	"ETM_COUNTER_INITAL_VALUE3",
-	"ETM_COUNTER_INITAL_VALUE4",
-	"ETM_COUNTER_ENABLE1",
-	"ETM_COUNTER_ENABLE2",
-	"ETM_COUNTER_ENABLE3",
-	"ETM_COUNTER_ENABLE4",
-	"ETM_COUNTER_RELOAD_VALUE1",
-	"ETM_COUNTER_RELOAD_VALUE2",
-	"ETM_COUNTER_RELOAD_VALUE3",
-	"ETM_COUNTER_RELOAD_VALUE4",
-	"ETM_COUNTER_VALUE1",
-	"ETM_COUNTER_VALUE2",
-	"ETM_COUNTER_VALUE3",
-	"ETM_COUNTER_VALUE4",
-	"ETM_SEQUENCER_CTRL1",
-	"ETM_SEQUENCER_CTRL2",
-	"ETM_SEQUENCER_CTRL3",
-	"ETM_SEQUENCER_CTRL4",
-	"ETM_SEQUENCER_CTRL5",
-	"ETM_SEQUENCER_CTRL6",
-	"ETM_SEQUENCER_STATE",
-	"ETM_EXTERNAL_OUTPUT1",
-	"ETM_EXTERNAL_OUTPUT2",
-	"ETM_EXTERNAL_OUTPUT3",
-	"ETM_EXTERNAL_OUTPUT4",
-	"ETM_CONTEXTID_COMPARATOR_VALUE1",
-	"ETM_CONTEXTID_COMPARATOR_VALUE2",
-	"ETM_CONTEXTID_COMPARATOR_VALUE3",
-	"ETM_CONTEXTID_COMPARATOR_MASK"
+/*
+ * Registers 0..0x7f are JTAG-addressable using scanchain 6.
+ * Newer versions of ETM make some W/O registers R/W, and
+ * provide definitions for some previously-unused bits.
+ */
+static const struct etm_reg_info reg[] = {
+	/* ETM Trace Registers */
+	{ ETM_CTRL, 32, RW, 0x10, "ETM_CTRL", },
+	{ ETM_CONFIG, 32, RO, 0x10, "ETM_CONFIG", },
+	{ ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_TRIG_EVENT", },
+	{ ETM_ASIC_CTRL,  8, WO, 0x10, "ETM_ASIC_CTRL", },
+	{ ETM_STATUS,  3, RO, 0x11, "ETM_STATUS", },
+	{ ETM_SYS_CONFIG,  9, RO, 0x12, "ETM_SYS_CONFIG", },
+
+	/* TraceEnable configuration */
+	{ ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_TRACE_RESOURCE_CTRL", },
+	{ ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_TRACE_EN_CTRL2", },
+	{ ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_TRACE_EN_EVENT", },
+	{ ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_TRACE_EN_CTRL1", },
+
+	/* FIFOFULL configuration */
+	{ ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_FIFOFULL_REGION", },
+	{ ETM_FIFOFULL_LEVEL,  8, WO, 0x10, "ETM_FIFOFULL_LEVEL", },
+
+	/* ViewData configuration (data trace) */
+	{ ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_VIEWDATA_EVENT", },
+	{ ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_VIEWDATA_CTRL1", },
+	{ ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_VIEWDATA_CTRL2", },
+	{ ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_VIEWDATA_CTRL3", },
+
+	/* Address comparator register pairs */
+#define ADDR_COMPARATOR(i) \
+		{ ETM_ADDR_COMPARATOR_VALUE + (i), 32, WO, 0x10, \
+				"ETM_ADDR_COMPARATOR_VALUE" #i, }, \
+		{ ETM_ADDR_ACCESS_TYPE + (i),  7, WO, 0x10, \
+				"ETM_ADDR_ACCESS_TYPE" #i, }
+	ADDR_COMPARATOR(0),
+	ADDR_COMPARATOR(1),
+	ADDR_COMPARATOR(2),
+	ADDR_COMPARATOR(3),
+	ADDR_COMPARATOR(4),
+	ADDR_COMPARATOR(5),
+	ADDR_COMPARATOR(6),
+	ADDR_COMPARATOR(7),
+
+	ADDR_COMPARATOR(8),
+	ADDR_COMPARATOR(9),
+	ADDR_COMPARATOR(10),
+	ADDR_COMPARATOR(11),
+	ADDR_COMPARATOR(12),
+	ADDR_COMPARATOR(13),
+	ADDR_COMPARATOR(14),
+	ADDR_COMPARATOR(15),
+#undef ADDR_COMPARATOR
+
+	/* Data Value Comparators (NOTE: odd addresses are reserved) */
+#define DATA_COMPARATOR(i) \
+		{ ETM_DATA_COMPARATOR_VALUE + 2*(i), 32, WO, 0x10, \
+				"ETM_DATA_COMPARATOR_VALUE" #i, }, \
+		{ ETM_DATA_COMPARATOR_MASK + 2*(i), 32, WO, 0x10, \
+				"ETM_DATA_COMPARATOR_MASK" #i, }
+	DATA_COMPARATOR(0),
+	DATA_COMPARATOR(1),
+	DATA_COMPARATOR(2),
+	DATA_COMPARATOR(3),
+	DATA_COMPARATOR(4),
+	DATA_COMPARATOR(5),
+	DATA_COMPARATOR(6),
+	DATA_COMPARATOR(7),
+#undef DATA_COMPARATOR
+
+	/* Counters */
+#define COUNTER(i) \
+		{ ETM_COUNTER_RELOAD_VALUE + (i), 16, WO, 0x10, \
+				"ETM_COUNTER_RELOAD_VALUE" #i, }, \
+		{ ETM_COUNTER_ENABLE + (i), 18, WO, 0x10, \
+				"ETM_COUNTER_ENABLE" #i, }, \
+		{ ETM_COUNTER_RELOAD_EVENT + (i), 17, WO, 0x10, \
+				"ETM_COUNTER_RELOAD_EVENT" #i, }, \
+		{ ETM_COUNTER_VALUE + (i), 16, RO, 0x10, \
+				"ETM_COUNTER_VALUE" #i, }
+	COUNTER(0),
+	COUNTER(1),
+	COUNTER(2),
+	COUNTER(3),
+#undef COUNTER
+
+	/* Sequencers */
+#define SEQ(i) \
+		{ ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
+				"ETM_SEQUENCER_EVENT" #i, }
+	SEQ(0),				/* 1->2 */
+	SEQ(1),				/* 2->1 */
+	SEQ(2),				/* 2->3 */
+	SEQ(3),				/* 3->1 */
+	SEQ(4),				/* 3->2 */
+	SEQ(5),				/* 1->3 */
+#undef SEQ
+	/* 0x66 reserved */
+	{ ETM_SEQUENCER_STATE,  2, RO, 0x10, "ETM_SEQUENCER_STATE", },
+
+#define OUT(i) \
+		{ ETM_EXTERNAL_OUTPUT + (i), 17, WO, 0x10, \
+				"ETM_EXTERNAL_OUTPUT" #i, }
+
+	OUT(0),
+	OUT(1),
+	OUT(2),
+	OUT(3),
+#undef OUT
+
+#if 0
+	/* registers from 0x6c..0x7f were added after ETMv1.3 */
+
+	/* Context ID Comparators */
+	{ 0x6c, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
+	{ 0x6d, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
+	{ 0x6e, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
+	{ 0x6f, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_MASK", }
+
+	{ 0x78, 12, WO, 0x20, "ETM_SYNC_FREQ", },
+	{ 0x79, 32, RO, 0x20, "ETM_ID", },
+#endif
 };
 
 static int etm_reg_arch_type = -1;
@@ -224,7 +214,7 @@
 	for (i = 0; i < cache->num_regs; i++) {
 		struct etm_reg_s *reg = cache->reg_list[i].arch_info;
 
-		if (reg->addr == (int) id)
+		if (reg->reg_info->addr == id)
 			return &cache->reg_list[i];
 	}
 
@@ -240,7 +230,7 @@
 	reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 	reg_t *reg_list = NULL;
 	etm_reg_t *arch_info = NULL;
-	int num_regs = sizeof(etm_reg_arch_info)/sizeof(int);
+	int num_regs = ARRAY_SIZE(reg);
 	int i;
 
 	/* register a register arch-type for etm registers only once */
@@ -260,13 +250,15 @@
 	/* set up registers */
 	for (i = 0; i < num_regs; i++)
 	{
-		reg_list[i].name = etm_reg_list[i];
-		reg_list[i].size = 32;
-		reg_list[i].value = calloc(1, 4);
+		const struct etm_reg_info *r = reg + i;
+
+		reg_list[i].name = r->name;
+		reg_list[i].size = r->size;
+		reg_list[i].value = &arch_info[i].value;
 		reg_list[i].arch_info = &arch_info[i];
 		reg_list[i].arch_type = etm_reg_arch_type;
-		reg_list[i].size = etm_reg_arch_size_info[i];
-		arch_info[i].addr = etm_reg_arch_info[i];
+
+		arch_info[i].reg_info = r;
 		arch_info[i].jtag_info = jtag_info;
 	}
 
@@ -278,10 +270,6 @@
 		if (!etb)
 		{
 			LOG_ERROR("etb selected as etm capture driver, but no ETB configured");
-			for (i = 0; i < num_regs; i++)
-			{
-				free(reg_list[i].value);
-			}
 			free(reg_cache);
 			free(arch_info);
 			return ERROR_OK;
@@ -368,11 +356,17 @@
 		uint8_t* check_value, uint8_t* check_mask)
 {
 	etm_reg_t *etm_reg = reg->arch_info;
-	uint8_t reg_addr = etm_reg->addr & 0x7f;
+	const struct etm_reg_info *r = etm_reg->reg_info;
+	uint8_t reg_addr = r->addr & 0x7f;
 	scan_field_t fields[3];
 
-	LOG_DEBUG("%i", etm_reg->addr);
+	if (etm_reg->reg_info->mode == WO) {
+		LOG_ERROR("BUG: can't read write-only register %s", r->name);
+		return ERROR_INVALID_ARGUMENTS;
+	}
 
+	LOG_DEBUG("%s (%u)", r->name, reg_addr);
+
 	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(etm_reg->jtag_info, 0x6);
 	arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
@@ -448,11 +442,17 @@
 static int etm_write_reg(reg_t *reg, uint32_t value)
 {
 	etm_reg_t *etm_reg = reg->arch_info;
-	uint8_t reg_addr = etm_reg->addr & 0x7f;
+	const struct etm_reg_info *r = etm_reg->reg_info;
+	uint8_t reg_addr = r->addr & 0x7f;
 	scan_field_t fields[3];
 
-	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", etm_reg->addr, value);
+	if (etm_reg->reg_info->mode == RO) {
+		LOG_ERROR("BUG: can't write read--only register %s", r->name);
+		return ERROR_INVALID_ARGUMENTS;
+	}
 
+	LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
+
 	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(etm_reg->jtag_info, 0x6);
 	arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);

Modified: trunk/src/target/etm.h
===================================================================
--- trunk/src/target/etm.h	2009-09-23 07:49:38 UTC (rev 2750)
+++ trunk/src/target/etm.h	2009-09-23 09:16:00 UTC (rev 2751)
@@ -29,43 +29,52 @@
 
 struct image_s;
 
-/* ETM registers (V1.3 protocol) */
+/* ETM registers (JTAG protocol) */
 enum
 {
 	ETM_CTRL = 0x00,
 	ETM_CONFIG = 0x01,
 	ETM_TRIG_EVENT = 0x02,
-	ETM_MMD_CTRL = 0x03,
+	ETM_ASIC_CTRL = 0x03,
 	ETM_STATUS = 0x04,
 	ETM_SYS_CONFIG = 0x05,
 	ETM_TRACE_RESOURCE_CTRL = 0x06,
 	ETM_TRACE_EN_CTRL2 = 0x07,
 	ETM_TRACE_EN_EVENT = 0x08,
 	ETM_TRACE_EN_CTRL1 = 0x09,
+	/* optional FIFOFULL */
 	ETM_FIFOFULL_REGION = 0x0a,
 	ETM_FIFOFULL_LEVEL = 0x0b,
+	/* viewdata support */
 	ETM_VIEWDATA_EVENT = 0x0c,
 	ETM_VIEWDATA_CTRL1 = 0x0d,
-	ETM_VIEWDATA_CTRL2 = 0x0e,
+	ETM_VIEWDATA_CTRL2 = 0x0e,	/* optional */
 	ETM_VIEWDATA_CTRL3 = 0x0f,
+	/* N pairs of ADDR_{COMPARATOR,ACCESS} registers */
 	ETM_ADDR_COMPARATOR_VALUE = 0x10,
 	ETM_ADDR_ACCESS_TYPE = 0x20,
+	/* N pairs of DATA_COMPARATOR_{VALUE,MASK} registers */
 	ETM_DATA_COMPARATOR_VALUE = 0x30,
 	ETM_DATA_COMPARATOR_MASK = 0x40,
-	ETM_COUNTER_INITAL_VALUE = 0x50,
+	/* N quads of COUNTER_{RELOAD_{VALUE,EVENT},ENABLE,VALUE} registers */
+	ETM_COUNTER_RELOAD_VALUE = 0x50,
 	ETM_COUNTER_ENABLE = 0x54,
-	ETM_COUNTER_RELOAD_VALUE = 0x58,
+	ETM_COUNTER_RELOAD_EVENT = 0x58,
 	ETM_COUNTER_VALUE = 0x5c,
-	ETM_SEQUENCER_CTRL = 0x60,
+	/* 6 sequencer event transitions */
+	ETM_SEQUENCER_EVENT = 0x60,
 	ETM_SEQUENCER_STATE = 0x67,
+	/* N triggered outputs */
 	ETM_EXTERNAL_OUTPUT = 0x68,
+	/* N task contexts */
 	ETM_CONTEXTID_COMPARATOR_VALUE = 0x6c,
 	ETM_CONTEXTID_COMPARATOR_MASK = 0x6f,
 };
 
 typedef struct etm_reg_s
 {
-	int addr;
+	uint32_t value;
+	const struct etm_reg_info *reg_info;
 	arm_jtag_t *jtag_info;
 } etm_reg_t;
 

[Openocd-svn] r2750 - trunk/src/target

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-23 09:49:38 +0200 (Wed, 23 Sep 2009)
New Revision: 2750

Modified:
   trunk/src/target/etm.c
   trunk/src/target/etm.h
Log:
Initial ETM cleanups.  Most of these are cosmetic:

 - Add a header comment
 - Line up the ETM context struct, pack it a bit
 - Remove unused context_id (this doesn't support ETMv2 yet)
 - Make most functions static
 - Remove unused string table and other needless lines of code
 - Correct "tracemode" helptext

Also provide and use an etm_reg_lookup() to find entries in the ETM
register cache.  This will help cope with corrected contents of that
cache, which doesn't include entires for non-existent registers.


Modified: trunk/src/target/etm.c
===================================================================
--- trunk/src/target/etm.c	2009-09-23 07:14:03 UTC (rev 2749)
+++ trunk/src/target/etm.c	2009-09-23 07:49:38 UTC (rev 2750)
@@ -28,20 +28,28 @@
 #include "arm_disassembler.h"
 
 
-/* ETM register access functionality
+/*
+ * ARM "Embedded Trace Macrocell" (ETM) support -- direct JTAG access.
  *
+ * ETM modules collect instruction and/or data trace information, compress
+ * it, and transfer it to a debugging host through either a (buffered) trace
+ * port (often a 38-pin Mictor connector) or an Embedded Trace Buffer (ETB).
+ *
+ * There are several generations of these modules.  Original versions have
+ * JTAG access through a dedicated scan chain.  Recent versions have added
+ * access via coprocessor instructions, memory addressing, and the ARM Debug
+ * Interface v5 (ADIv5); and phased out direct JTAG access.
+ *
+ * This code supports up to the ETMv1.3 architecture, as seen in ETM9 and
+ * most common ARM9 systems.  Note: "CoreSight ETM9" implements ETMv3.2,
+ * implying non-JTAG connectivity options.
+ *
+ * Relevant documentation includes:
+ *  ARM DDI 0157G ... ETM9 (r2p2) Technical Reference Manual
+ *  ARM DDI 0315B ... CoreSight ETM9 (r0p1) Technical Reference Manual
+ *  ARM IHI 0014O ... Embedded Trace Macrocell, Architecture Specification
  */
 
-#if 0
-static bitfield_desc_t etm_comms_ctrl_bitfield_desc[] =
-{
-	{"R", 1},
-	{"W", 1},
-	{"reserved", 26},
-	{"version", 4}
-};
-#endif
-
 static int etm_reg_arch_info[] =
 {
 	0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
@@ -196,11 +204,39 @@
 static int etm_reg_arch_type = -1;
 
 static int etm_get_reg(reg_t *reg);
+static int etm_read_reg_w_check(reg_t *reg,
+		uint8_t* check_value, uint8_t* check_mask);
+static int etm_register_user_commands(struct command_context_s *cmd_ctx);
+static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
+static int etm_write_reg(reg_t *reg, uint32_t value);
 
-static command_t *etm_cmd = NULL;
+static command_t *etm_cmd;
 
-reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
+
+/* Look up register by ID ... most ETM instances only
+ * support a subset of the possible registers.
+ */
+static reg_t *etm_reg_lookup(etm_context_t *etm_ctx, unsigned id)
 {
+	reg_cache_t *cache = etm_ctx->reg_cache;
+	int i;
+
+	for (i = 0; i < cache->num_regs; i++) {
+		struct etm_reg_s *reg = cache->reg_list[i].arch_info;
+
+		if (reg->addr == (int) id)
+			return &cache->reg_list[i];
+	}
+
+	/* caller asking for nonexistent register is a bug! */
+	/* REVISIT say which of the N targets was involved */
+	LOG_ERROR("ETM: register 0x%02x not available", id);
+	return NULL;
+}
+
+reg_cache_t *etm_build_reg_cache(target_t *target,
+		arm_jtag_t *jtag_info, etm_context_t *etm_ctx)
+{
 	reg_cache_t *reg_cache = malloc(sizeof(reg_cache_t));
 	reg_t *reg_list = NULL;
 	etm_reg_t *arch_info = NULL;
@@ -226,10 +262,6 @@
 	{
 		reg_list[i].name = etm_reg_list[i];
 		reg_list[i].size = 32;
-		reg_list[i].dirty = 0;
-		reg_list[i].valid = 0;
-		reg_list[i].bitfield_desc = NULL;
-		reg_list[i].num_bitfields = 0;
 		reg_list[i].value = calloc(1, 4);
 		reg_list[i].arch_info = &arch_info[i];
 		reg_list[i].arch_type = etm_reg_arch_type;
@@ -264,6 +296,16 @@
 	return reg_cache;
 }
 
+static int etm_read_reg(reg_t *reg)
+{
+	return etm_read_reg_w_check(reg, NULL, NULL);
+}
+
+static int etm_store_reg(reg_t *reg)
+{
+	return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
+}
+
 int etm_setup(target_t *target)
 {
 	int retval;
@@ -271,8 +313,12 @@
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	etm_context_t *etm_ctx = arm7_9->etm_ctx;
-	reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
+	reg_t *etm_ctrl_reg;
 
+	etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
+	if (!etm_ctrl_reg)
+		return ERROR_OK;
+
 	/* initialize some ETM control register settings */
 	etm_get_reg(etm_ctrl_reg);
 	etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
@@ -299,7 +345,7 @@
 	return ERROR_OK;
 }
 
-int etm_get_reg(reg_t *reg)
+static int etm_get_reg(reg_t *reg)
 {
 	int retval;
 
@@ -318,7 +364,8 @@
 	return ERROR_OK;
 }
 
-int etm_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask)
+static int etm_read_reg_w_check(reg_t *reg,
+		uint8_t* check_value, uint8_t* check_mask)
 {
 	etm_reg_t *etm_reg = reg->arch_info;
 	uint8_t reg_addr = etm_reg->addr & 0x7f;
@@ -367,13 +414,8 @@
 	return ERROR_OK;
 }
 
-int etm_read_reg(reg_t *reg)
+static int etm_set_reg(reg_t *reg, uint32_t value)
 {
-	return etm_read_reg_w_check(reg, NULL, NULL);
-}
-
-int etm_set_reg(reg_t *reg, uint32_t value)
-{
 	int retval;
 
 	if ((retval = etm_write_reg(reg, value)) != ERROR_OK)
@@ -389,7 +431,7 @@
 	return ERROR_OK;
 }
 
-int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
+static int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf)
 {
 	int retval;
 
@@ -403,7 +445,7 @@
 	return ERROR_OK;
 }
 
-int etm_write_reg(reg_t *reg, uint32_t value)
+static int etm_write_reg(reg_t *reg, uint32_t value)
 {
 	etm_reg_t *etm_reg = reg->arch_info;
 	uint8_t reg_addr = etm_reg->addr & 0x7f;
@@ -441,10 +483,6 @@
 	return ERROR_OK;
 }
 
-int etm_store_reg(reg_t *reg)
-{
-	return etm_write_reg(reg, buf_get_u32(reg->value, 0, reg->size));
-}
 
 /* ETM trace analysis functionality
  *
@@ -464,18 +502,6 @@
 	NULL
 };
 
-char *etmv1v1_branch_reason_strings[] =
-{
-	"normal PC change",
-	"tracing enabled",
-	"trace restarted after overflow",
-	"exit from debug",
-	"periodic synchronization",
-	"reserved",
-	"reserved",
-	"reserved",
-};
-
 static int etm_read_instruction(etm_context_t *ctx, arm_instruction_t *instruction)
 {
 	int i;
@@ -1172,8 +1198,12 @@
 	/* only update ETM_CTRL register if tracemode changed */
 	if (arm7_9->etm_ctx->tracemode != tracemode)
 	{
-		reg_t *etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
+		reg_t *etm_ctrl_reg;
 
+		etm_ctrl_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_CTRL);
+		if (!etm_ctrl_reg)
+			return ERROR_OK;
+
 		etm_get_reg(etm_ctrl_reg);
 
 		buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
@@ -1319,7 +1349,6 @@
 	etm_ctx->last_branch_reason = 0x0;
 	etm_ctx->last_ptr = 0x0;
 	etm_ctx->ptr_ok = 0x0;
-	etm_ctx->context_id = 0x0;
 	etm_ctx->last_instruction = 0;
 
 	arm7_9->etm_ctx = etm_ctx;
@@ -1327,7 +1356,8 @@
 	return etm_register_user_commands(cmd_ctx);
 }
 
-int handle_etm_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int handle_etm_info_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target;
 	armv4_5_common_t *armv4_5;
@@ -1351,8 +1381,12 @@
 		return ERROR_OK;
 	}
 
-	etm_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CONFIG];
-	etm_sys_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_SYS_CONFIG];
+	etm_config_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_CONFIG);
+	if (!etm_config_reg)
+		return ERROR_OK;
+	etm_sys_config_reg = etm_reg_lookup(arm7_9->etm_ctx, ETM_SYS_CONFIG);
+	if (!etm_sys_config_reg)
+		return ERROR_OK;
 
 	etm_get_reg(etm_config_reg);
 	command_print(cmd_ctx, "pairs of address comparators: %i", (int)buf_get_u32(etm_config_reg->value, 0, 4));
@@ -1732,7 +1766,10 @@
 	}
 	arm7_9->etm_ctx->trace_depth = 0;
 
-	etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
+	etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
+	if (!etm_ctrl_reg)
+		return ERROR_OK;
+
 	etm_get_reg(etm_ctrl_reg);
 
 	/* Clear programming bit (10), set port selection bit (11) */
@@ -1768,7 +1805,10 @@
 		return ERROR_OK;
 	}
 
-	etm_ctrl_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_CTRL];
+	etm_ctrl_reg = etm_reg_lookup(etm_ctx, ETM_CTRL);
+	if (!etm_ctrl_reg)
+		return ERROR_OK;
+
 	etm_get_reg(etm_ctrl_reg);
 
 	/* Set programming bit (10), clear port selection bit (11) */
@@ -1835,10 +1875,11 @@
 	return ERROR_OK;
 }
 
-int etm_register_user_commands(struct command_context_s *cmd_ctx)
+static int etm_register_user_commands(struct command_context_s *cmd_ctx)
 {
 	register_command(cmd_ctx, etm_cmd, "tracemode", handle_etm_tracemode_command,
-		COMMAND_EXEC, "configure trace mode <none | data | address | all> "
+		COMMAND_EXEC, "configure/display trace mode: "
+			"<none | data | address | all> "
 			"<context_id_bits> <cycle_accurate> <branch_output>");
 
 	register_command(cmd_ctx, etm_cmd, "info", handle_etm_info_command,

Modified: trunk/src/target/etm.h
===================================================================
--- trunk/src/target/etm.h	2009-09-23 07:14:03 UTC (rev 2749)
+++ trunk/src/target/etm.h	2009-09-23 07:49:38 UTC (rev 2750)
@@ -139,29 +139,28 @@
  */
 typedef struct etm_context_s
 {
-	target_t *target;				/* target this ETM is connected to */
-	reg_cache_t *reg_cache;			/* ETM register cache */
+	target_t *target;		/* target this ETM is connected to */
+	reg_cache_t *reg_cache;		/* ETM register cache */
 	etm_capture_driver_t *capture_driver;	/* driver used to access ETM data */
-	void *capture_driver_priv;		/* capture driver private data */
-	uint32_t trigger_percent;			/* percent of trace buffer to be filled after the trigger */
+	void *capture_driver_priv;	/* capture driver private data */
+	uint32_t trigger_percent;	/* how much trace buffer to fill after trigger */
 	trace_status_t capture_status;	/* current state of capture run */
 	etmv1_trace_data_t *trace_data;	/* trace data */
-	uint32_t trace_depth;				/* number of trace cycles to be analyzed, 0 if no trace data available */
-	etm_portmode_t portmode;		/* normal, multiplexed or demultiplexed */
-	etmv1_tracemode_t tracemode;	/* type of information the trace contains (data, addres, contextID, ...) */
-	armv4_5_state_t core_state;		/* current core state (ARM, Thumb, Jazelle) */
-	struct image_s *image;					/* source for target opcodes */
-	uint32_t pipe_index;					/* current trace cycle */
-	uint32_t data_index;					/* cycle holding next data packet */
-	int data_half;					/* port half on a 16 bit port */
-	uint32_t current_pc;					/* current program counter */
-	uint32_t pc_ok;						/* full PC has been acquired */
-	uint32_t last_branch;				/* last branch address output */
-	uint32_t last_branch_reason;			/* branch reason code for the last branch encountered */
-	uint32_t last_ptr;					/* address of the last data access */
-	uint32_t ptr_ok;						/* whether last_ptr is valid */
-	uint32_t context_id;					/* context ID of the code being traced */
-	uint32_t last_instruction;			/* index of last instruction executed (to calculate cycle timings) */
+	uint32_t trace_depth;		/* number of cycles to be analyzed, 0 if no data available */
+	etm_portmode_t portmode;	/* normal, multiplexed or demultiplexed */
+	etmv1_tracemode_t tracemode;	/* type of info trace contains */
+	armv4_5_state_t core_state;	/* current core state */
+	struct image_s *image;		/* source for target opcodes */
+	uint32_t pipe_index;		/* current trace cycle */
+	uint32_t data_index;		/* cycle holding next data packet */
+	bool data_half;			/* port half on a 16 bit port */
+	bool pc_ok;			/* full PC has been acquired */
+	bool ptr_ok;			/* whether last_ptr is valid */
+	uint32_t current_pc;		/* current program counter */
+	uint32_t last_branch;		/* last branch address output */
+	uint32_t last_branch_reason;	/* type of last branch encountered */
+	uint32_t last_ptr;		/* address of the last data access */
+	uint32_t last_instruction;	/* index of last executed (to calc timings) */
 } etm_context_t;
 
 /* PIPESTAT values */
@@ -190,20 +189,10 @@
 	BR_RSVD7   = 0x7, /* reserved */
 } etmv1_branch_reason_t;
 
-extern char *etmv1v1_branch_reason_strings[];
-
 extern reg_cache_t* etm_build_reg_cache(target_t *target, arm_jtag_t *jtag_info, etm_context_t *etm_ctx);
-extern int etm_read_reg(reg_t *reg);
-extern int etm_write_reg(reg_t *reg, uint32_t value);
-extern int etm_read_reg_w_check(reg_t *reg, uint8_t* check_value, uint8_t* check_mask);
-extern int etm_store_reg(reg_t *reg);
-extern int etm_set_reg(reg_t *reg, uint32_t value);
-extern int etm_set_reg_w_exec(reg_t *reg, uint8_t *buf);
 extern int etm_setup(target_t *target);
 
 int etm_register_commands(struct command_context_s *cmd_ctx);
-int etm_register_user_commands(struct command_context_s *cmd_ctx);
-extern etm_context_t* etm_create_context(etm_portmode_t portmode, char *capture_driver_name);
 
 #define ERROR_ETM_INVALID_DRIVER	(-1300)
 #define ERROR_ETM_PORTMODE_NOT_SUPPORTED	(-1301)

[Openocd-svn] r2749 - in trunk/src: flash helper

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-23 09:14:03 +0200 (Wed, 23 Sep 2009)
New Revision: 2749

Modified:
   trunk/src/flash/at91sam3.c
   trunk/src/helper/jim.c
Log:
Nico Coesel <nc...@de...> fix warnings. . I'm wondering why these
didn't turn up earlier. Is everyone still using gcc 3.x? Or is the x86
version of gcc 4.x much more relaxed?

Modified: trunk/src/flash/at91sam3.c
===================================================================
--- trunk/src/flash/at91sam3.c	2009-09-22 15:39:23 UTC (rev 2748)
+++ trunk/src/flash/at91sam3.c	2009-09-23 07:14:03 UTC (rev 2749)
@@ -1609,7 +1609,7 @@
 sam3_protect_check(struct flash_bank_s *bank)
 {
 	int r;
-	uint32_t v;
+	uint32_t v=0;
 	unsigned x;
 	struct sam3_bank_private *pPrivate;
 

Modified: trunk/src/helper/jim.c
===================================================================
--- trunk/src/helper/jim.c	2009-09-22 15:39:23 UTC (rev 2748)
+++ trunk/src/helper/jim.c	2009-09-23 07:14:03 UTC (rev 2749)
@@ -3235,7 +3235,7 @@
             Jim_InitHashTable(cmdPtr->staticVars, getJimVariablesHashTableType(),
                     interp);
             for (i = 0; i < len; i++) {
-                Jim_Obj *objPtr, *initObjPtr, *nameObjPtr;
+                Jim_Obj *objPtr=NULL, *initObjPtr=NULL, *nameObjPtr=NULL;
                 Jim_Var *varPtr;
                 int subLen;
 
@@ -7739,7 +7739,7 @@
     int scanned = 1;
     const char *str = Jim_GetString(strObjPtr, 0);
     Jim_Obj *resultList = 0;
-    Jim_Obj **resultVec;
+    Jim_Obj **resultVec =NULL;
     int resultc;
     Jim_Obj *emptyStr = 0;
     ScanFmtStringObj *fmtObj;
@@ -8823,9 +8823,9 @@
     }
 
     for (i = 0; i < num_args; i++) {
-        Jim_Obj *argObjPtr;
-        Jim_Obj *nameObjPtr;
-        Jim_Obj *valueObjPtr;
+        Jim_Obj *argObjPtr=NULL;
+        Jim_Obj *nameObjPtr=NULL;
+        Jim_Obj *valueObjPtr=NULL;
 
         Jim_ListIndex(interp, cmd->argListObjPtr, i, &argObjPtr, JIM_NONE);
         if (i + 1 >= cmd->arityMin) {
@@ -8849,7 +8849,7 @@
     }
     /* Set optional arguments */
     if (cmd->arityMax == -1) {
-        Jim_Obj *listObjPtr, *objPtr;
+        Jim_Obj *listObjPtr=NULL, *objPtr=NULL;
 
         i++;
         listObjPtr = Jim_NewListObj(interp, argv + i, argc-i);
@@ -9421,7 +9421,7 @@
     Jim_HashEntry *he;
     Jim_Obj *listObjPtr = Jim_NewListObj(interp, NULL, 0);
     const char *pattern;
-    int patternLen;
+    int patternLen=0;
 
     pattern = patternObjPtr ? Jim_GetString(patternObjPtr, &patternLen) : NULL;
     htiter = Jim_GetHashTableIterator(&interp->commands);
@@ -9447,7 +9447,7 @@
     Jim_HashEntry *he;
     Jim_Obj *listObjPtr = Jim_NewListObj(interp, NULL, 0);
     const char *pattern;
-    int patternLen;
+    int patternLen=0;
 
     pattern = patternObjPtr ? Jim_GetString(patternObjPtr, &patternLen) : NULL;
     if (mode == JIM_VARLIST_GLOBALS) {
@@ -9816,7 +9816,7 @@
         exprLen = expr->len;
 
         if (exprLen == 1) {
-            jim_wide wideValue;
+            jim_wide wideValue=0;
 
             if (expr->opcode[0] == JIM_EXPROP_VARIABLE) {
                 varAObjPtr = expr->obj[0];
@@ -9856,7 +9856,7 @@
             if (varAObjPtr)
                 Jim_DecrRefCount(interp, varAObjPtr);
         } else if (exprLen == 3) {
-            jim_wide wideValueA, wideValueB, cmpRes = 0;
+            jim_wide wideValueA, wideValueB=0, cmpRes = 0;
             int cmpType = expr->opcode[2];
 
             varAObjPtr = expr->obj[0];
@@ -9983,7 +9983,7 @@
     {
         ScriptObj *initScript, *incrScript;
         ExprByteCode *expr;
-        jim_wide start, stop, currentVal;
+        jim_wide start, stop=0, currentVal;
         unsigned jim_wide procEpoch = interp->procEpoch;
         Jim_Obj *varNamePtr, *stopVarNamePtr = NULL, *objPtr;
         int cmpType;
@@ -11013,7 +11013,7 @@
     if (argListLen) {
         const char *str;
         int len;
-        Jim_Obj *argPtr;
+        Jim_Obj *argPtr=NULL;
 
         /* Check for 'args' and adjust arityMin and arityMax if necessary */
         Jim_ListIndex(interp, argv[2], argListLen-1, &argPtr, JIM_NONE);
@@ -11132,7 +11132,7 @@
     value = Jim_Alloc(sizeof(Jim_Obj*)*numMaps);
     resultObjPtr = Jim_NewStringObj(interp, "", 0);
     for (i = 0; i < numMaps; i++) {
-        Jim_Obj *eleObjPtr;
+        Jim_Obj *eleObjPtr=NULL;
 
         Jim_ListIndex(interp, mapListObjPtr, i*2, &eleObjPtr, JIM_NONE);
         key[i] = Jim_GetString(eleObjPtr, &keyLen[i]);
@@ -11855,7 +11855,7 @@
     resObjPtr = Jim_NewStringObj(interp, NULL, 0);
     /* Split */
     for (i = 0; i < listLen; i++) {
-        Jim_Obj *objPtr;
+        Jim_Obj *objPtr=NULL;
 
         Jim_ListIndex(interp, argv[1], i, &objPtr, JIM_NONE);
         Jim_AppendObj(interp, resObjPtr, objPtr);
@@ -12119,7 +12119,7 @@
 static int Jim_RandCoreCommand(Jim_Interp *interp, int argc,
         Jim_Obj *const *argv)
 {
-    jim_wide min = 0, max, len, maxMul;
+    jim_wide min = 0, max =0, len, maxMul;
 
     if (argc < 1 || argc > 3) {
         Jim_WrongNumArgs(interp, 1, argv, "?min? max");
@@ -12311,7 +12311,7 @@
             Jim_GetString(interp->result, NULL));
     Jim_ListLength(interp, interp->stackTrace, &len);
     for (i = len-3; i >= 0; i-= 3) {
-        Jim_Obj *objPtr;
+        Jim_Obj *objPtr=NULL;
         const char *proc, *file, *line;
 
         Jim_ListIndex(interp, interp->stackTrace, i, &objPtr, JIM_NONE);

[Openocd-svn] r2748 - trunk/src/flash

[ntfreak at B. <nt...@ma...>]

Author: ntfreak
Date: 2009-09-22 17:39:23 +0200 (Tue, 22 Sep 2009)
New Revision: 2748

Modified:
   trunk/src/flash/flash.c
Log:
- fix build issue under win32 (cygwin/msys) from svn r2746


Modified: trunk/src/flash/flash.c
===================================================================
--- trunk/src/flash/flash.c	2009-09-22 14:50:46 UTC (rev 2747)
+++ trunk/src/flash/flash.c	2009-09-22 15:39:23 UTC (rev 2748)
@@ -560,7 +560,7 @@
 }
 
 static int flash_check_sector_parameters(struct command_context_s *cmd_ctx,
-		uint32_t first, uint32_t last, uint num_sectors)
+		uint32_t first, uint32_t last, uint32_t num_sectors)
 {
 	if (!(first <= last)) {
 		command_print(cmd_ctx, "ERROR: "

[Openocd-svn] r2747 - in trunk: src/flash tcl/board

[ntfreak at B. <nt...@ma...>]

Author: ntfreak
Date: 2009-09-22 16:50:46 +0200 (Tue, 22 Sep 2009)
New Revision: 2747

Modified:
   trunk/src/flash/lpc2900.c
   trunk/src/flash/lpc2900.h
   trunk/tcl/board/csb337.cfg
   trunk/tcl/board/ek-lm3s3748.cfg
Log:
- add missing svn props from previous commit

Modified: trunk/src/flash/lpc2900.c
===================================================================
--- trunk/src/flash/lpc2900.c	2009-09-22 05:39:06 UTC (rev 2746)
+++ trunk/src/flash/lpc2900.c	2009-09-22 14:50:46 UTC (rev 2747)
@@ -1,1926 +1,1926 @@
-/***************************************************************************
- *   Copyright (C) 2009 by                                                 *
- *   Rolf Meeser <rol...@ya...>                                      *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
- ***************************************************************************/
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-
-#include "image.h"
-
-#include "lpc2900.h"
-#include "binarybuffer.h"
-#include "armv4_5.h"
-
-
-/* 1024 bytes */
-#define KiB                 1024
-
-/* Some flash constants */
-#define FLASH_PAGE_SIZE     512     /* bytes */
-#define FLASH_ERASE_TIME    100000  /* microseconds */
-#define FLASH_PROGRAM_TIME  1000    /* microseconds */
-
-/* Chip ID / Feature Registers */
-#define CHIPID          0xE0000000  /* Chip ID */
-#define FEAT0           0xE0000100  /* Chip feature 0 */
-#define FEAT1           0xE0000104  /* Chip feature 1 */
-#define FEAT2           0xE0000108  /* Chip feature 2 (contains flash size indicator) */
-#define FEAT3           0xE000010C  /* Chip feature 3 */
-
-#define EXPECTED_CHIPID 0x209CE02B  /* Chip ID of all LPC2900 devices */
-
-/* Flash/EEPROM Control Registers */
-#define FCTR            0x20200000  /* Flash control */
-#define FPTR            0x20200008  /* Flash program-time */
-#define FTCTR           0x2020000C  /* Flash test control */
-#define FBWST           0x20200010  /* Flash bridge wait-state */
-#define FCRA            0x2020001C  /* Flash clock divider */
-#define FMSSTART        0x20200020  /* Flash Built-In Selft Test start address */
-#define FMSSTOP         0x20200024  /* Flash Built-In Selft Test stop address */
-#define FMS16           0x20200028  /* Flash 16-bit signature */
-#define FMSW0           0x2020002C  /* Flash 128-bit signature Word 0 */
-#define FMSW1           0x20200030  /* Flash 128-bit signature Word 1 */
-#define FMSW2           0x20200034  /* Flash 128-bit signature Word 2 */
-#define FMSW3           0x20200038  /* Flash 128-bit signature Word 3 */
-
-#define EECMD           0x20200080  /* EEPROM command */
-#define EEADDR          0x20200084  /* EEPROM address */
-#define EEWDATA         0x20200088  /* EEPROM write data */
-#define EERDATA         0x2020008C  /* EEPROM read data */
-#define EEWSTATE        0x20200090  /* EEPROM wait state */
-#define EECLKDIV        0x20200094  /* EEPROM clock divider */
-#define EEPWRDWN        0x20200098  /* EEPROM power-down/start */
-#define EEMSSTART       0x2020009C  /* EEPROM BIST start address */
-#define EEMSSTOP        0x202000A0  /* EEPROM BIST stop address */
-#define EEMSSIG         0x202000A4  /* EEPROM 24-bit BIST signature */
-
-#define INT_CLR_ENABLE  0x20200FD8  /* Flash/EEPROM interrupt clear enable */
-#define INT_SET_ENABLE  0x20200FDC  /* Flash/EEPROM interrupt set enable */
-#define INT_STATUS      0x20200FE0  /* Flash/EEPROM interrupt status */
-#define INT_ENABLE      0x20200FE4  /* Flash/EEPROM interrupt enable */
-#define INT_CLR_STATUS  0x20200FE8  /* Flash/EEPROM interrupt clear status */
-#define INT_SET_STATUS  0x20200FEC  /* Flash/EEPROM interrupt set status */
-
-/* Interrupt sources */
-#define INTSRC_END_OF_PROG    (1 << 28)
-#define INTSRC_END_OF_BIST    (1 << 27)
-#define INTSRC_END_OF_RDWR    (1 << 26)
-#define INTSRC_END_OF_MISR    (1 << 2)
-#define INTSRC_END_OF_BURN    (1 << 1)
-#define INTSRC_END_OF_ERASE   (1 << 0)
-
-
-/* FCTR bits */
-#define FCTR_FS_LOADREQ       (1 << 15)
-#define FCTR_FS_CACHECLR      (1 << 14)
-#define FCTR_FS_CACHEBYP      (1 << 13)
-#define FCTR_FS_PROGREQ       (1 << 12)
-#define FCTR_FS_RLS           (1 << 11)
-#define FCTR_FS_PDL           (1 << 10)
-#define FCTR_FS_PD            (1 << 9)
-#define FCTR_FS_WPB           (1 << 7)
-#define FCTR_FS_ISS           (1 << 6)
-#define FCTR_FS_RLD           (1 << 5)
-#define FCTR_FS_DCR           (1 << 4)
-#define FCTR_FS_WEB           (1 << 2)
-#define FCTR_FS_WRE           (1 << 1)
-#define FCTR_FS_CS            (1 << 0)
-/* FPTR bits */
-#define FPTR_EN_T             (1 << 15)
-/* FTCTR bits */
-#define FTCTR_FS_BYPASS_R     (1 << 29)
-#define FTCTR_FS_BYPASS_W     (1 << 28)
-/* FMSSTOP bits */
-#define FMSSTOP_MISR_START    (1 << 17)
-/* EEMSSTOP bits */
-#define EEMSSTOP_STRTBIST     (1 << 31)
-
-/* Index sector */
-#define ISS_CUSTOMER_START1   (0x830)
-#define ISS_CUSTOMER_END1     (0xA00)
-#define ISS_CUSTOMER_SIZE1    (ISS_CUSTOMER_END1 - ISS_CUSTOMER_START1)
-#define ISS_CUSTOMER_NWORDS1  (ISS_CUSTOMER_SIZE1 / 4)
-#define ISS_CUSTOMER_START2   (0xA40)
-#define ISS_CUSTOMER_END2     (0xC00)
-#define ISS_CUSTOMER_SIZE2    (ISS_CUSTOMER_END2 - ISS_CUSTOMER_START2)
-#define ISS_CUSTOMER_NWORDS2  (ISS_CUSTOMER_SIZE2 / 4)
-#define ISS_CUSTOMER_SIZE     (ISS_CUSTOMER_SIZE1 + ISS_CUSTOMER_SIZE2)
-
-
-
-/**
- * Private data for \c lpc2900 flash driver.
- */
-typedef struct lpc2900_flash_bank_s
-{
-	/**
-	 * Holds the value read from CHIPID register.
-	 * The driver will not load if the chipid doesn't match the expected
-	 * value of 0x209CE02B of the LPC2900 family. A probe will only be done
-	 * if the chipid does not yet contain the expected value.
-	 */
-	uint32_t chipid;
-
-	/**
-	 * String holding device name.
-	 * This string is set by the probe function to the type number of the
-	 * device. It takes the form "LPC29xx".
-	 */
-	char * target_name;
-
-	/**
-	 * System clock frequency.
-	 * Holds the clock frequency in Hz, as passed by the configuration file
-	 * to the <tt>flash bank</tt> command.
-	 */
-	uint32_t clk_sys_fmc;
-
-	/**
-	 * Flag to indicate that dangerous operations are possible.
-	 * This flag can be set by passing the correct password to the
-	 * <tt>lpc2900 password</tt> command. If set, other dangerous commands,
-	 * which operate on the index sector, can be executed.
-	 */
-	uint32_t risky;
-
-	/**
-	 * Maximum contiguous block of internal SRAM (bytes).
-	 * Autodetected by the driver. Not the total amount of SRAM, only the
-	 * the largest \em contiguous block!
-	 */
-	uint32_t max_ram_block;
-
-} lpc2900_flash_bank_t;
-
-
-
-
-static int lpc2900_register_commands(struct command_context_s *cmd_ctx);
-static int lpc2900_flash_bank_command(struct command_context_s *cmd_ctx,
-                                      char *cmd, char **args, int argc,
-                                      struct flash_bank_s *bank);
-static int lpc2900_erase(struct flash_bank_s *bank, int first, int last);
-static int lpc2900_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int lpc2900_write(struct flash_bank_s *bank,
-                         uint8_t *buffer, uint32_t offset, uint32_t count);
-static int lpc2900_probe(struct flash_bank_s *bank);
-static int lpc2900_erase_check(struct flash_bank_s *bank);
-static int lpc2900_protect_check(struct flash_bank_s *bank);
-static int lpc2900_info(struct flash_bank_s *bank, char *buf, int buf_size);
-
-static uint32_t lpc2900_wait_status(flash_bank_t *bank, uint32_t mask, int timeout);
-static void lpc2900_setup(struct flash_bank_s *bank);
-static uint32_t lpc2900_is_ready(struct flash_bank_s *bank);
-static uint32_t lpc2900_read_security_status(struct flash_bank_s *bank);
-static uint32_t lpc2900_run_bist128(struct flash_bank_s *bank,
-                                    uint32_t addr_from, uint32_t addr_to,
-                                    uint32_t (*signature)[4] );
-static uint32_t lpc2900_address2sector(struct flash_bank_s *bank, uint32_t offset);
-static uint32_t lpc2900_calc_tr( uint32_t clock, uint32_t time );
-
-
-/***********************  Helper functions  **************************/
-
-
-/**
- * Wait for an event in mask to occur in INT_STATUS.
- *
- * Return when an event occurs, or after a timeout.
- *
- * @param[in] bank Pointer to the flash bank descriptor
- * @param[in] mask Mask to be used for INT_STATUS
- * @param[in] timeout Timeout in ms
- */
-static uint32_t lpc2900_wait_status( flash_bank_t *bank,
-                                     uint32_t mask,
-                                     int timeout )
-{
-	uint32_t int_status;
-	target_t *target = bank->target;
-
-
-	do
-	{
-		alive_sleep(1);
-		timeout--;
-		target_read_u32(target, INT_STATUS, &int_status);
-	}
-	while( ((int_status & mask) == 0) && (timeout != 0) );
-
-	if (timeout == 0)
-	{
-		LOG_DEBUG("Timeout!");
-		return ERROR_FLASH_OPERATION_FAILED;
-	}
-
-	return ERROR_OK;
-}
-
-
-
-/**
- * Set up the flash for erase/program operations.
- *
- * Enable the flash, and set the correct CRA clock of 66 kHz.
- *
- * @param bank Pointer to the flash bank descriptor
- */
-static void lpc2900_setup( struct flash_bank_s *bank )
-{
-	uint32_t fcra;
-	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
-
-
-	/* Power up the flash block */
-	target_write_u32( bank->target, FCTR, FCTR_FS_WEB | FCTR_FS_CS );
-
-
-	fcra = (lpc2900_info->clk_sys_fmc / (3 * 66000)) - 1;
-	target_write_u32( bank->target, FCRA, fcra );
-}
-
-
-
-/**
- * Check if device is ready.
- *
- * Check if device is ready for flash operation:
- * Must have been successfully probed.
- * Must be halted.
- */
-static uint32_t lpc2900_is_ready( struct flash_bank_s *bank )
-{
-	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
-
-	if( lpc2900_info->chipid != EXPECTED_CHIPID )
-	{
-		return ERROR_FLASH_BANK_NOT_PROBED;
-	}
-
-	if( bank->target->state != TARGET_HALTED )
-	{
-		LOG_ERROR( "Target not halted" );
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	return ERROR_OK;
-}
-
-
-/**
- * Read the status of sector security from the index sector.
- *
- * @param bank Pointer to the flash bank descriptor
- */
-static uint32_t lpc2900_read_security_status( struct flash_bank_s *bank )
-{
-	uint32_t status;
-	if( (status = lpc2900_is_ready( bank )) != ERROR_OK )
-	{
-		return status;
-	}
-
-	target_t *target = bank->target;
-
-	/* Enable ISS access */
-	target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB | FCTR_FS_ISS);
-
-	/* Read the relevant block of memory from the ISS sector */
-	uint32_t iss_secured_field[ 0x230/16 ][ 4 ];
-	target_read_memory(target, bank->base + 0xC00, 4, 0x230/4,
-	                           (uint8_t *)iss_secured_field);
-
-	/* Disable ISS access */
-	target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
-
-	/* Check status of each sector. Note that the sector numbering in the LPC2900
-	 * is different from the logical sector numbers used in OpenOCD!
-	 * Refer to the user manual for details.
-	 *
-	 * All zeros (16x 0x00) are treated as a secured sector (is_protected = 1)
-	 * All ones (16x 0xFF) are treated as a non-secured sector (is_protected = 0)
-	 * Anything else is undefined (is_protected = -1). This is treated as
-	 * a protected sector!
-	 */
-	int sector;
-	int index;
-	for( sector = 0; sector < bank->num_sectors; sector++ )
-	{
-		/* Convert logical sector number to physical sector number */
-		if( sector <= 4 )
-		{
-			index = sector + 11;
-		}
-		else if( sector <= 7 )
-		{
-			index = sector + 27;
-		}
-		else
-		{
-			index = sector - 8;
-		}
-
-		bank->sectors[sector].is_protected = -1;
-
-		if (
-		    (iss_secured_field[index][0] == 0x00000000) &&
-		    (iss_secured_field[index][1] == 0x00000000) &&
-		    (iss_secured_field[index][2] == 0x00000000) &&
-		    (iss_secured_field[index][3] == 0x00000000) )
-		{
-			bank->sectors[sector].is_protected = 1;
-		}
-
-		if (
-		    (iss_secured_field[index][0] == 0xFFFFFFFF) &&
-		    (iss_secured_field[index][1] == 0xFFFFFFFF) &&
-		    (iss_secured_field[index][2] == 0xFFFFFFFF) &&
-		    (iss_secured_field[index][3] == 0xFFFFFFFF) )
-		{
-			bank->sectors[sector].is_protected = 0;
-		}
-	}
-
-	return ERROR_OK;
-}
-
-
-/**
- * Use BIST to calculate a 128-bit hash value over a range of flash.
- *
- * @param bank Pointer to the flash bank descriptor
- * @param addr_from
- * @param addr_to
- * @param signature
- */
-static uint32_t lpc2900_run_bist128(struct flash_bank_s *bank,
-                                    uint32_t addr_from,
-                                    uint32_t addr_to,
-                                    uint32_t (*signature)[4] )
-{
-	target_t *target = bank->target;
-
-	/* Clear END_OF_MISR interrupt status */
-	target_write_u32( target, INT_CLR_STATUS, INTSRC_END_OF_MISR );
-
-	/* Start address */
-	target_write_u32( target, FMSSTART, addr_from >> 4);
-	/* End address, and issue start command */
-	target_write_u32( target, FMSSTOP, (addr_to >> 4) | FMSSTOP_MISR_START );
-
-	/* Poll for end of operation. Calculate a reasonable timeout. */
-	if( lpc2900_wait_status( bank, INTSRC_END_OF_MISR, 1000 ) != ERROR_OK )
-	{
-		return ERROR_FLASH_OPERATION_FAILED;
-	}
-
-	/* Return the signature */
-	target_read_memory( target, FMSW0, 4, 4, (uint8_t *)signature );
-
-	return ERROR_OK;
-}
-
-
-/**
- * Return sector number for given address.
- *
- * Return the (logical) sector number for a given relative address.
- * No sanity check is done. It assumed that the address is valid.
- *
- * @param bank Pointer to the flash bank descriptor
- * @param offset Offset address relative to bank start
- */
-static uint32_t lpc2900_address2sector( struct flash_bank_s *bank,
-                                        uint32_t offset )
-{
-	uint32_t address = bank->base + offset;
-
-
-	/* Run through all sectors of this bank */
-	int sector;
-	for( sector = 0; sector < bank->num_sectors; sector++ )
-	{
-		/* Return immediately if address is within the current sector */
-		if( address < (bank->sectors[sector].offset + bank->sectors[sector].size) )
-		{
-			return sector;
-		}
-	}
-
-	/* We should never come here. If we do, return an arbitrary sector number. */
-	return 0;
-}
-
-
-
-
-/**
- * Write one page to the index sector.
- *
- * @param bank Pointer to the flash bank descriptor
- * @param pagenum Page number (0...7)
- * @param page Page array (FLASH_PAGE_SIZE bytes)
- */
-static int lpc2900_write_index_page( struct flash_bank_s *bank,
-                                     int pagenum,
-                                     uint8_t (*page)[FLASH_PAGE_SIZE] )
-{
-	/* Only pages 4...7 are user writable */
-	if( (pagenum < 4) || (pagenum > 7) )
-	{
-		LOG_ERROR( "Refuse to burn index sector page %" PRIu32, pagenum );
-		return ERROR_COMMAND_ARGUMENT_INVALID;
-	}
-
-	/* Get target, and check if it's halted */
-	target_t *target = bank->target;
-	if( target->state != TARGET_HALTED )
-	{
-		LOG_ERROR( "Target not halted" );
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	/* Private info */
-	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
-
-	/* Enable flash block and set the correct CRA clock of 66 kHz */
-	lpc2900_setup( bank );
-
-	/* Un-protect the index sector */
-	target_write_u32( target, bank->base, 0 );
-	target_write_u32( target, FCTR,
-	                  FCTR_FS_LOADREQ | FCTR_FS_WPB | FCTR_FS_ISS |
-	                  FCTR_FS_WEB | FCTR_FS_WRE | FCTR_FS_CS );
-
-	/* Set latch load mode */
-	target_write_u32( target, FCTR,
-	                  FCTR_FS_ISS | FCTR_FS_WEB | FCTR_FS_WRE | FCTR_FS_CS );
-
-	/* Write whole page to flash data latches */
-	if( target_write_memory( target,
-	                         bank->base + pagenum * FLASH_PAGE_SIZE,
-	                         4, FLASH_PAGE_SIZE / 4, (uint8_t *)page) != ERROR_OK )
-	{
-		LOG_ERROR( "Index sector write failed @ page %" PRIu32, pagenum );
-		target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB );
-
-		return ERROR_FLASH_OPERATION_FAILED;
-	}
-
-	/* Clear END_OF_BURN interrupt status */
-	target_write_u32( target, INT_CLR_STATUS, INTSRC_END_OF_BURN );
-
-	/* Set the program/erase time to FLASH_PROGRAM_TIME */
-	target_write_u32(target, FPTR,
-	                 FPTR_EN_T | lpc2900_calc_tr( lpc2900_info->clk_sys_fmc,
-	                                              FLASH_PROGRAM_TIME ));
-
-	/* Trigger flash write */
-	target_write_u32( target, FCTR,
-	                  FCTR_FS_PROGREQ | FCTR_FS_ISS |
-	                  FCTR_FS_WPB | FCTR_FS_WRE | FCTR_FS_CS );
-
-	/* Wait for the end of the write operation. If it's not over after one
-	 * second, something went dreadfully wrong... :-(
-	 */
-	if( lpc2900_wait_status( bank, INTSRC_END_OF_BURN, 1000 ) != ERROR_OK )
-	{
-		LOG_ERROR( "Index sector write failed @ page %" PRIu32, pagenum );
-		target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB );
-
-		return ERROR_FLASH_OPERATION_FAILED;
-	}
-
-	target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB );
-
-	return ERROR_OK;
-}
-
-
-
-/**
- * Calculate FPTR.TR register value for desired program/erase time.
- *
- * @param clock System clock in Hz
- * @param time Program/erase time in µs
- */
-static uint32_t lpc2900_calc_tr( uint32_t clock, uint32_t time )
-{
-	/*           ((time[µs]/1e6) * f[Hz]) + 511
-	 * FPTR.TR = -------------------------------
-	 *                         512
-	 *
-	 * The result is the 
-	 */
-
-	uint32_t tr_val = (uint32_t)((((time / 1e6) * clock) + 511.0) / 512.0);
-
-	return tr_val;
-}
-
-
-/***********************  Private flash commands  **************************/
-
-
-/**
- * Command to determine the signature of the whole flash.
- *
- * Uses the Built-In-Self-Test (BIST) to generate a 128-bit hash value
- * of the flash content.
- *
- * @param cmd_ctx
- * @param cmd
- * @param args
- * @param argc
- */
-static int lpc2900_handle_signature_command( struct command_context_s *cmd_ctx,
-                                             char *cmd, char **args, int argc )
-{
-	flash_bank_t *bank;
-	uint32_t status;
-	uint32_t signature[4];
-
-
-	if( argc < 1 )
-	{
-		LOG_WARNING( "Too few arguments. Call: lpc2900 signature <bank#>" );
-		return ERROR_FLASH_BANK_INVALID;
-	}
-
-	/* Get the bank descriptor */
-	bank = get_flash_bank_by_num( strtoul(args[0], NULL, 0) );
-	if( !bank )
-	{
-		command_print( cmd_ctx, "flash bank '#%s' is out of bounds", args[0] );
-		return ERROR_OK;
-	}
-
-	if( bank->target->state != TARGET_HALTED )
-	{
-		LOG_ERROR( "Target not halted" );
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	/* Run BIST over whole flash range */
-	if( (status = lpc2900_run_bist128( bank,
-	                                   bank->base,
-	                                   bank->base + (bank->size - 1),
-	                                   &signature)
-	                                 ) != ERROR_OK )
-	{
-		return status;
-	}
-
-	command_print( cmd_ctx, "signature: 0x%8.8" PRIx32
-	                                  ":0x%8.8" PRIx32
-	                                  ":0x%8.8" PRIx32
-	                                  ":0x%8.8" PRIx32,
-	              signature[3], signature[2], signature[1], signature[0] );
-
-	return ERROR_OK;
-}
-
-
-
-/**
- * Store customer info in file.
- *
- * Read customer info from index sector, and store that block of data into
- * a disk file. The format is binary.
- *
- * @param cmd_ctx
- * @param cmd
- * @param args
- * @param argc
- */
-static int lpc2900_handle_read_custom_command( struct command_context_s *cmd_ctx,
-                                               char *cmd, char **args, int argc )
-{
-	flash_bank_t *bank;
-
-
-	if( argc < 2 )
-	{
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	/* Get the bank descriptor */
-	bank = get_flash_bank_by_num( strtoul(args[0], NULL, 0) );
-	if( !bank )
-	{
-		command_print( cmd_ctx, "flash bank '#%s' is out of bounds", args[0] );
-		return ERROR_OK;
-	}
-	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
-	lpc2900_info->risky = 0;
-
-	/* Get target, and check if it's halted */
-	target_t *target = bank->target;
-	if( target->state != TARGET_HALTED )
-	{
-		LOG_ERROR( "Target not halted" );
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	/* Storage for customer info. Read in two parts */
-	uint32_t customer[ ISS_CUSTOMER_NWORDS1 + ISS_CUSTOMER_NWORDS2 ];
-
-	/* Enable access to index sector */
-	target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB | FCTR_FS_ISS );
-
-	/* Read two parts */
-	target_read_memory( target, bank->base+ISS_CUSTOMER_START1, 4,
-	                            ISS_CUSTOMER_NWORDS1,
-	                            (uint8_t *)&customer[0] );
-	target_read_memory( target, bank->base+ISS_CUSTOMER_START2, 4,
-	                            ISS_CUSTOMER_NWORDS2,
-	                            (uint8_t *)&customer[ISS_CUSTOMER_NWORDS1] );
-
-	/* Deactivate access to index sector */
-	target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB );
-
-	/* Try and open the file */
-	fileio_t fileio;
-	char *filename = args[1];
-	int ret = fileio_open( &fileio, filename, FILEIO_WRITE, FILEIO_BINARY );
-	if( ret != ERROR_OK )
-	{
-		LOG_WARNING( "Could not open file %s", filename );
-		return ret;
-	}
-
-	uint32_t nwritten;
-	ret = fileio_write( &fileio, sizeof(customer),
-                        (const uint8_t *)customer, &nwritten );
-	if( ret != ERROR_OK )
-	{
-		LOG_ERROR( "Write operation to file %s failed", filename );
-		fileio_close( &fileio );
-		return ret;
-	}
-
-	fileio_close( &fileio );
-
-	return ERROR_OK;
-}
-
-
-
-
-/**
- * Enter password to enable potentially dangerous options.
- *
- * @param cmd_ctx
- * @param cmd
- * @param args
- * @param argc
- */
-static int lpc2900_handle_password_command(struct command_context_s *cmd_ctx,
-                                           char *cmd, char **args, int argc)
-{
-	flash_bank_t *bank;
-
-
-	if (argc < 2)
-	{
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	/* Get the bank descriptor */
-	bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
-	if (!bank)
-	{
-		command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
-		return ERROR_OK;
-	}
-	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
-
-#define ISS_PASSWORD "I_know_what_I_am_doing"
-
-	lpc2900_info->risky = !strcmp( args[1], ISS_PASSWORD );
-
-	if( !lpc2900_info->risky )
-	{
-		command_print(cmd_ctx, "Wrong password (use '%s')", ISS_PASSWORD);
-		return ERROR_COMMAND_ARGUMENT_INVALID;
-	}
-
-	command_print(cmd_ctx,
-                  "Potentially dangerous operation allowed in next command!");
-
-	return ERROR_OK;
-}
-
-
-
-/**
- * Write customer info from file to the index sector.
- *
- * @param cmd_ctx
- * @param cmd
- * @param args
- * @param argc
- */
-static int lpc2900_handle_write_custom_command( struct command_context_s *cmd_ctx,
-                                                char *cmd, char **args, int argc )
-{
-	if (argc < 2)
-	{
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	/* Get the bank descriptor */
-	flash_bank_t *bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
-	if (!bank)
-	{
-		command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
-		return ERROR_OK;
-	}
-	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
-
-	/* Check if command execution is allowed. */
-	if( !lpc2900_info->risky )
-	{
-		command_print( cmd_ctx, "Command execution not allowed!" );
-		return ERROR_COMMAND_ARGUMENT_INVALID;
-	}
-	lpc2900_info->risky = 0;
-
-	/* Get target, and check if it's halted */
-	target_t *target = bank->target;
-	if (target->state != TARGET_HALTED)
-	{
-		LOG_ERROR("Target not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	/* The image will always start at offset 0 */
-	image_t image;
-	image.base_address_set = 1;
-	image.base_address = 0;
-	image.start_address_set = 0;
-
-	char *filename = args[1];
-	char *type = (argc >= 3) ? args[2] : NULL;
-	int retval = image_open(&image, filename, type);
-	if (retval != ERROR_OK)
-	{
-		return retval;
-	}
-
-	/* Do a sanity check: The image must be exactly the size of the customer
-	   programmable area. Any other size is rejected. */
-	if( image.num_sections != 1 )
-	{
-		LOG_ERROR("Only one section allowed in image file.");
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-	if( (image.sections[0].base_address != 0) ||
-        (image.sections[0].size != ISS_CUSTOMER_SIZE) )
-	{
-		LOG_ERROR("Incorrect image file size. Expected %" PRIu32 ", got %" PRIu32,
-                   ISS_CUSTOMER_SIZE, image.sections[0].size);
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	/* Well boys, I reckon this is it... */
-
-	/* Customer info is split into two blocks in pages 4 and 5. */
-	uint8_t page[FLASH_PAGE_SIZE];
-
-	/* Page 4 */
-	uint32_t offset = ISS_CUSTOMER_START1 % FLASH_PAGE_SIZE;
-	memset( page, 0xff, FLASH_PAGE_SIZE );
-	uint32_t size_read;
-	retval = image_read_section( &image, 0, 0,
-	                             ISS_CUSTOMER_SIZE1, &page[offset], &size_read);
-	if( retval != ERROR_OK )
-	{
-		LOG_ERROR("couldn't read from file '%s'", filename);
-		image_close(&image);
-		return retval;
-	}
-	if( (retval = lpc2900_write_index_page( bank, 4, &page )) != ERROR_OK )
-	{
-		image_close(&image);
-		return retval;
-	}
-
-	/* Page 5 */
-	offset = ISS_CUSTOMER_START2 % FLASH_PAGE_SIZE;
-	memset( page, 0xff, FLASH_PAGE_SIZE );
-	retval = image_read_section( &image, 0, ISS_CUSTOMER_SIZE1,
-	                             ISS_CUSTOMER_SIZE2, &page[offset], &size_read);
-	if( retval != ERROR_OK )
-	{
-		LOG_ERROR("couldn't read from file '%s'", filename);
-		image_close(&image);
-		return retval;
-	}
-	if( (retval = lpc2900_write_index_page( bank, 5, &page )) != ERROR_OK )
-	{
-		image_close(&image);
-		return retval;
-	}
-
-	image_close(&image);
-
-	return ERROR_OK;
-}
-
-
-
-/**
- * Activate 'sector security' for a range of sectors.
- *
- * @param cmd_ctx
- * @param cmd
- * @param args
- * @param argc
- */
-static int lpc2900_handle_secure_sector_command(struct command_context_s *cmd_ctx,
-                                                char *cmd, char **args, int argc)
-{
-	if (argc < 3)
-	{
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	/* Get the bank descriptor */
-	flash_bank_t *bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
-	if (!bank)
-	{
-		command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
-		return ERROR_OK;
-	}
-	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
-
-	/* Check if command execution is allowed. */
-	if( !lpc2900_info->risky )
-	{
-		command_print( cmd_ctx, "Command execution not allowed! "
-		"(use 'password' command first)");
-		return ERROR_COMMAND_ARGUMENT_INVALID;
-	}
-	lpc2900_info->risky = 0;
-
-	/* Read sector range, and do a sanity check. */
-	int first = strtoul(args[1], NULL, 0);
-	int last = strtoul(args[2], NULL, 0);
-	if( (first >= bank->num_sectors) ||
-	    (last >= bank->num_sectors) ||
-	    (first > last) )
-	{
-		command_print( cmd_ctx, "Illegal sector range" );
-		return ERROR_COMMAND_ARGUMENT_INVALID;
-	}
-
-	uint8_t page[FLASH_PAGE_SIZE];
-	int sector;
-	int retval;
-
-	/* Sectors in page 6 */
-	if( (first <= 4) || (last >= 8) )
-	{
-		memset( &page, 0xff, FLASH_PAGE_SIZE );
-		for( sector = first; sector <= last; sector++ )
-		{
-			if( sector <= 4 )
-			{
-				memset( &page[0xB0 + 16*sector], 0, 16 );
-			}
-			else if( sector >= 8 )
-			{
-				memset( &page[0x00 + 16*(sector - 8)], 0, 16 );
-			}
-		}
-
-		if( (retval = lpc2900_write_index_page( bank, 6, &page )) != ERROR_OK )
-		{
-			LOG_ERROR("failed to update index sector page 6");
-			return retval;
-		}
-	}
-
-	/* Sectors in page 7 */
-	if( (first <= 7) && (last >= 5) )
-	{
-		memset( &page, 0xff, FLASH_PAGE_SIZE );
-		for( sector = first; sector <= last; sector++ )
-		{
-			if( (sector >= 5) && (sector <= 7) )
-			{
-				memset( &page[0x00 + 16*(sector - 5)], 0, 16 );
-			}
-		}
-
-		if( (retval = lpc2900_write_index_page( bank, 7, &page )) != ERROR_OK )
-		{
-			LOG_ERROR("failed to update index sector page 7");
-			return retval;
-		}
-	}
-
-	command_print( cmd_ctx,
-	        "Sectors security will become effective after next power cycle");
-
-	/* Update the sector security status */
-	if ( lpc2900_read_security_status(bank) != ERROR_OK )
-	{
-		LOG_ERROR( "Cannot determine sector security status" );
-		return ERROR_FLASH_OPERATION_FAILED;
-	}
-
-	return ERROR_OK;
-}
-
-
-
-/**
- * Activate JTAG protection.
- *
- * @param cmd_ctx
- * @param cmd
- * @param args
- * @param argc
- */
-static int lpc2900_handle_secure_jtag_command(struct command_context_s *cmd_ctx,
-                                              char *cmd, char **args, int argc)
-{
-	if (argc < 1)
-	{
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	/* Get the bank descriptor */
-	flash_bank_t *bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
-	if (!bank)
-	{
-		command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
-		return ERROR_OK;
-	}
-	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
-
-	/* Check if command execution is allowed. */
-	if( !lpc2900_info->risky )
-	{
-		command_print( cmd_ctx, "Command execution not allowed! "
-		                        "(use 'password' command first)");
-		return ERROR_COMMAND_ARGUMENT_INVALID;
-	}
-	lpc2900_info->risky = 0;
-
-	/* Prepare page */
-	uint8_t page[FLASH_PAGE_SIZE];
-	memset( &page, 0xff, FLASH_PAGE_SIZE );
-
-
-	/* Insert "soft" protection word */
-	page[0x30 + 15] = 0x7F;
-	page[0x30 + 11] = 0x7F;
-	page[0x30 +  7] = 0x7F;
-	page[0x30 +  3] = 0x7F;
-
-	/* Write to page 5 */
-	int retval;
-	if( (retval = lpc2900_write_index_page( bank, 5, &page ))
-			!= ERROR_OK )
-	{
-		LOG_ERROR("failed to update index sector page 5");
-		return retval;
-	}
-
-	LOG_INFO("JTAG security set. Good bye!");
-
-	return ERROR_OK;
-}
-
-
-
-/***********************  Flash interface functions  **************************/
-
-
-/**
- * Register private command handlers.
- *
- * @param cmd_ctx
- */
-static int lpc2900_register_commands(struct command_context_s *cmd_ctx)
-{
-	command_t *lpc2900_cmd = register_command(cmd_ctx, NULL, "lpc2900",
-	                                          NULL, COMMAND_ANY, NULL);
-
-	register_command(
-	    cmd_ctx,
-	    lpc2900_cmd,
-	    "signature",
-	    lpc2900_handle_signature_command,
-	    COMMAND_EXEC,
-	    "<bank> | "
-            "print device signature of flash bank");
-
-	register_command(
-	    cmd_ctx,
-	    lpc2900_cmd,
-	    "read_custom",
-	    lpc2900_handle_read_custom_command,
-	    COMMAND_EXEC,
-	    "<bank> <filename> | "
-            "read customer information from index sector to file");
-
-	register_command(
-	    cmd_ctx,
-	    lpc2900_cmd,
-	    "password",
-	    lpc2900_handle_password_command,
-	    COMMAND_EXEC,
-	    "<bank> <password> | "
-            "enter password to enable 'dangerous' options");
-
-	register_command(
-	    cmd_ctx,
-	    lpc2900_cmd,
-	    "write_custom",
-	    lpc2900_handle_write_custom_command,
-	    COMMAND_EXEC,
-	    "<bank> <filename> [<type>] | "
-            "write customer info from file to index sector");
-
-	register_command(
-	    cmd_ctx,
-	    lpc2900_cmd,
-	    "secure_sector",
-	    lpc2900_handle_secure_sector_command,
-	    COMMAND_EXEC,
-	    "<bank> <first> <last> | "
-            "activate sector security for a range of sectors");
-
-	register_command(
-	    cmd_ctx,
-	    lpc2900_cmd,
-	    "secure_jtag",
-	    lpc2900_handle_secure_jtag_command,
-	    COMMAND_EXEC,
-	    "<bank> <level> | "
-            "activate JTAG security");
-
-	return ERROR_OK;
-}
-
-
-/**
- * Evaluate flash bank command.
- *
- * Syntax: flash bank lpc2900 0 0 0 0 target# system_base_clock
- *
- * @param cmd_ctx
- * @param cmd
- * @param args
- * @param argc
- * @param bank Pointer to the flash bank descriptor
- */
-static int lpc2900_flash_bank_command(struct command_context_s *cmd_ctx,
-                                      char *cmd, char **args, int argc,
-                                      struct flash_bank_s *bank)
-{
-	lpc2900_flash_bank_t *lpc2900_info;
-
-	if (argc < 6)
-	{
-		LOG_WARNING("incomplete flash_bank LPC2900 configuration");
-		return ERROR_FLASH_BANK_INVALID;
-	}
-
-	lpc2900_info = malloc(sizeof(lpc2900_flash_bank_t));
-	bank->driver_priv = lpc2900_info;
-
-	/* Get flash clock.
-	 * Reject it if we can't meet the requirements for program time
-	 * (if clock too slow), or for erase time (clock too fast).
-	 */
-	lpc2900_info->clk_sys_fmc = strtoul(args[6], NULL, 0) * 1000;
-
-	uint32_t clock_limit;
-	/* Check program time limit */
-	clock_limit = 512000000l / FLASH_PROGRAM_TIME;
-	if (lpc2900_info->clk_sys_fmc < clock_limit)
-	{
-		LOG_WARNING("flash clock must be at least %" PRIu32 " kHz",
-                    (clock_limit / 1000));
-		return ERROR_FLASH_BANK_INVALID;
-	}
-
-	/* Check erase time limit */
-	clock_limit = (uint32_t)((32767.0 * 512.0 * 1e6) / FLASH_ERASE_TIME);
-	if (lpc2900_info->clk_sys_fmc > clock_limit)
-	{
-		LOG_WARNING("flash clock must be a maximum of %" PRIu32" kHz",
-                    (clock_limit / 1000));
-		return ERROR_FLASH_BANK_INVALID;
-	}
-
-	/* Chip ID will be obtained by probing the device later */
-	lpc2900_info->chipid = 0;
-
-	return ERROR_OK;
-}
-
-
-/**
- * Erase sector(s).
- *
- * @param bank Pointer to the flash bank descriptor
- * @param first First sector to be erased
- * @param last Last sector (including) to be erased
- */
-static int lpc2900_erase(struct flash_bank_s *bank, int first, int last)
-{
-	uint32_t status;
-	int sector;
-	int last_unsecured_sector;
-	target_t *target = bank->target;
-	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
-
-
-	status = lpc2900_is_ready(bank);
-	if (status != ERROR_OK)
-	{
-		return status;
-	}
-
-	/* Sanity check on sector range */
-	if ((first < 0) || (last < first) || (last >= bank->num_sectors))
-	{
-		LOG_INFO("Bad sector range");
-		return ERROR_FLASH_SECTOR_INVALID;
-	}
-
-	/* Update the info about secured sectors */
-	lpc2900_read_security_status( bank );
-
-	/* The selected sector range might include secured sectors. An attempt
-	 * to erase such a sector will cause the erase to fail also for unsecured
-	 * sectors. It is necessary to determine the last unsecured sector now,
-	 * because we have to treat the last relevant sector in the list in
-	 * a special way.
-	 */
-	last_unsecured_sector = -1;
-	for (sector = first; sector <= last; sector++)
-	{
-		if ( !bank->sectors[sector].is_protected )
-		{
-			last_unsecured_sector = sector;
-		}
-	}
-
-	/* Exit now, in case of the rare constellation where all sectors in range
-	 * are secured. This is regarded a success, since erasing/programming of
-	 * secured sectors shall be handled transparently.
-	 */
-	if ( last_unsecured_sector == -1 )
-	{
-		return ERROR_OK;
-	}
-
-	/* Enable flash block and set the correct CRA clock of 66 kHz */
-	lpc2900_setup(bank);
-
-	/* Clear END_OF_ERASE interrupt status */
-	target_write_u32(target, INT_CLR_STATUS, INTSRC_END_OF_ERASE);
-
-	/* Set the program/erase timer to FLASH_ERASE_TIME */
-	target_write_u32(target, FPTR,
-	                 FPTR_EN_T | lpc2900_calc_tr( lpc2900_info->clk_sys_fmc,
-	                                              FLASH_ERASE_TIME ));
-
-	/* Sectors are marked for erasure, then erased all together */
-	for (sector = first; sector <= last_unsecured_sector; sector++)
-	{
-		/* Only mark sectors that aren't secured. Any attempt to erase a group
-		 * of sectors will fail if any single one of them is secured!
-		 */
-		if ( !bank->sectors[sector].is_protected )
-		{
-			/* Unprotect the sector */
-			target_write_u32(target, bank->sectors[sector].offset, 0);
-			target_write_u32(target, FCTR,
-			                 FCTR_FS_LOADREQ | FCTR_FS_WPB |
-			                 FCTR_FS_WEB | FCTR_FS_WRE | FCTR_FS_CS);
-
-			/* Mark the sector for erasure. The last sector in the list
-			   triggers the erasure. */
-			target_write_u32(target, bank->sectors[sector].offset, 0);
-			if ( sector == last_unsecured_sector )
-			{
-				target_write_u32(target, FCTR,
-				                 FCTR_FS_PROGREQ | FCTR_FS_WPB | FCTR_FS_CS);
-			}
-			else
-			{
-				target_write_u32(target, FCTR,
-				                 FCTR_FS_LOADREQ | FCTR_FS_WPB |
-				                 FCTR_FS_WEB | FCTR_FS_CS);
-			}
-		}
-	}
-
-	/* Wait for the end of the erase operation. If it's not over after two seconds,
-	 * something went dreadfully wrong... :-(
-	 */
-	if( lpc2900_wait_status(bank, INTSRC_END_OF_ERASE, 2000) != ERROR_OK )
-	{
-		return ERROR_FLASH_OPERATION_FAILED;
-	}
-
-	/* Normal flash operating mode */
-	target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
-
-	return ERROR_OK;
-}
-
-
-
-static int lpc2900_protect(struct flash_bank_s *bank, int set, int first, int last)
-{
-	/* This command is not supported.
-     * "Protection" in LPC2900 terms is handled transparently. Sectors will
-     * automatically be unprotected as needed.
-     * Instead we use the concept of sector security. A secured sector is shown
-     * as "protected" in OpenOCD. Sector security is a permanent feature, and
-     * cannot be disabled once activated.
-     */
-
-	return ERROR_OK;
-}
-
-
-/**
- * Write data to flash.
- *
- * @param bank Pointer to the flash bank descriptor
- * @param buffer Buffer with data
- * @param offset Start address (relative to bank start)
- * @param count Number of bytes to be programmed
- */
-static int lpc2900_write(struct flash_bank_s *bank, uint8_t *buffer,
-                         uint32_t offset, uint32_t count)
-{
-	uint8_t page[FLASH_PAGE_SIZE];
-	uint32_t status;
-	uint32_t num_bytes;
-	target_t *target = bank->target;
-	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
-	int sector;
-	int retval;
-
-	static const uint32_t write_target_code[] = {
-		/* Set auto latch mode: FCTR=CS|WRE|WEB */
-		0xe3a0a007,   /* loop       mov r10, #0x007 */
-		0xe583a000,   /*            str r10,[r3,#0] */
-
-		/* Load complete page into latches */
-		0xe3a06020,   /*            mov r6,#(512/16) */
-		0xe8b00f00,   /* next       ldmia r0!,{r8-r11} */
-		0xe8a10f00,   /*            stmia r1!,{r8-r11} */
-		0xe2566001,   /*            subs r6,#1 */
-		0x1afffffb,   /*            bne next */
-
-		/* Clear END_OF_BURN interrupt status */
-		0xe3a0a002,   /*            mov r10,#(1 << 1) */
-		0xe583afe8,   /*            str r10,[r3,#0xfe8] */
-
-		/* Set the erase time to FLASH_PROGRAM_TIME */
-		0xe5834008,   /*            str r4,[r3,#8] */
-
-		/* Trigger flash write
-			FCTR = CS | WRE | WPB | PROGREQ */
-		0xe3a0a083,   /*            mov r10,#0x83 */
-		0xe38aaa01,   /*            orr r10,#0x1000 */
-		0xe583a000,   /*            str r10,[r3,#0] */
-
-		/* Wait for end of burn */
-		0xe593afe0,   /* wait       ldr r10,[r3,#0xfe0] */
-		0xe21aa002,   /*            ands r10,#(1 << 1) */
-		0x0afffffc,   /*            beq wait */
-
-		/* End? */
-		0xe2522001,   /*            subs r2,#1 */
-		0x1affffed,   /*            bne loop */
-
-		0xeafffffe    /* done       b done */
-	};
-
-
-	status = lpc2900_is_ready(bank);
-	if (status != ERROR_OK)
-	{
-		return status;
-	}
-
-	/* Enable flash block and set the correct CRA clock of 66 kHz */
-	lpc2900_setup(bank);
-
-	/* Update the info about secured sectors */
-	lpc2900_read_security_status( bank );
-
-	/* Unprotect all involved sectors */
-	for (sector = 0; sector < bank->num_sectors; sector++)
-	{
-		/* Start address in or before this sector? */
-		/* End address in or behind this sector? */
-		if ( ((bank->base + offset) <
-		          (bank->sectors[sector].offset + bank->sectors[sector].size)) &&
-		     ((bank->base + (offset + count - 1)) >= bank->sectors[sector].offset) )
-		{
-			/* This sector is involved and needs to be unprotected.
-				* Don't do it for secured sectors.
-				*/
-			if ( !bank->sectors[sector].is_protected )
-			{
-				target_write_u32(target, bank->sectors[sector].offset, 0);
-				target_write_u32(target, FCTR,
-				                 FCTR_FS_LOADREQ | FCTR_FS_WPB |
-				                 FCTR_FS_WEB | FCTR_FS_WRE | FCTR_FS_CS);
-			}
-		}
-	}
-
-	/* Set the program/erase time to FLASH_PROGRAM_TIME */
-	uint32_t prog_time = FPTR_EN_T | lpc2900_calc_tr( lpc2900_info->clk_sys_fmc,
-	                                                  FLASH_PROGRAM_TIME );
-
-	/* If there is a working area of reasonable size, use it to program via
-	   a target algorithm. If not, fall back to host programming. */
-
-	/* We need some room for target code. */
-	uint32_t target_code_size = sizeof(write_target_code);
-
-	/* Try working area allocation. Start with a large buffer, and try with
-	   reduced size if that fails. */
-	working_area_t *warea;
-	uint32_t buffer_size = lpc2900_info->max_ram_block - 1 * KiB;
-	while( (retval = target_alloc_working_area(target,
-	                                           buffer_size + target_code_size,
-	                                           &warea)) != ERROR_OK )
-	{
-		/* Try a smaller buffer now, and stop if it's too small. */
-		buffer_size -= 1 * KiB;
-		if (buffer_size < 2 * KiB)
-		{
-			LOG_INFO( "no (large enough) working area"
-			          ", falling back to host mode" );
-			warea = NULL;
-			break;
-		}
-	};
-
-	if( warea )
-	{
-		reg_param_t reg_params[5];
-		armv4_5_algorithm_t armv4_5_info;
-
-		/* We can use target mode. Download the algorithm. */
-		retval = target_write_buffer( target,
-		                              (warea->address)+buffer_size,
-		                              target_code_size,
-		                              (uint8_t *)write_target_code);
-		if (retval != ERROR_OK)
-		{
-			LOG_ERROR("Unable to write block write code to target");
-			target_free_all_working_areas(target);
-			return ERROR_FLASH_OPERATION_FAILED;
-		}
-
-		init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
-		init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
-		init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
-		init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
-		init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
-
-		/* Write to flash in large blocks */
-		while ( count != 0 )
-		{
-			uint32_t this_npages;
-			uint8_t *this_buffer;
-			int start_sector = lpc2900_address2sector( bank, offset );
-
-			/* First page / last page / rest */
-			if( offset % FLASH_PAGE_SIZE )
-			{
-				/* Block doesn't start on page boundary.
-				   Burn first partial page separately. */
-				memset( &page, 0xff, sizeof(page) );
-				memcpy( &page[offset % FLASH_PAGE_SIZE],
-				        buffer,
-				        FLASH_PAGE_SIZE - (offset % FLASH_PAGE_SIZE) );
-				this_npages = 1;
-				this_buffer = &page[0];
-				count = count + (offset % FLASH_PAGE_SIZE);
-				offset = offset - (offset % FLASH_PAGE_SIZE);
-			}
-			else if( count < FLASH_PAGE_SIZE )
-			{
-				/* Download last incomplete page separately. */
-				memset( &page, 0xff, sizeof(page) );
-				memcpy( &page, buffer, count );
-				this_npages = 1;
-				this_buffer = &page[0];
-				count = FLASH_PAGE_SIZE;
-			}
-			else
-			{
-				/* Download as many full pages as possible */
-				this_npages = (count < buffer_size) ?
-				               count / FLASH_PAGE_SIZE :
-				               buffer_size / FLASH_PAGE_SIZE;
-				this_buffer = buffer;
-
-				/* Make sure we stop at the next secured sector */
-				int sector = start_sector + 1;
-				while( sector < bank->num_sectors )
-				{
-					/* Secured? */
-					if( bank->sectors[sector].is_protected )
-					{
-						/* Is that next sector within the current block? */
-						if( (bank->sectors[sector].offset - bank->base) <
-							(offset + (this_npages * FLASH_PAGE_SIZE)) )
-						{
-							/* Yes! Split the block */
-							this_npages =
-							  (bank->sectors[sector].offset - bank->base - offset)
-							      / FLASH_PAGE_SIZE;
-							break;
-						}
-					}
-
-					sector++;
-				}
-			}
-
-			/* Skip the current sector if it is secured */
-			if( bank->sectors[start_sector].is_protected )
-			{
-				LOG_DEBUG( "Skip secured sector %" PRIu32, start_sector );
-
-				/* Stop if this is the last sector */
-				if( start_sector == bank->num_sectors - 1 )
-				{
-					break;
-				}
-
-				/* Skip */
-				uint32_t nskip = bank->sectors[start_sector].size -
-				                 (offset % bank->sectors[start_sector].size);
-				offset += nskip;
-				buffer += nskip;
-				count = (count >= nskip) ? (count - nskip) : 0;
-				continue;
-			}
-
-			/* Execute buffer download */
-			if ((retval = target_write_buffer(target,
-			                                  warea->address,
-			                                  this_npages * FLASH_PAGE_SIZE,
-			                                  this_buffer)) != ERROR_OK)
-			{
-				LOG_ERROR("Unable to write data to target");
-				target_free_all_working_areas(target);
-				return ERROR_FLASH_OPERATION_FAILED;
-			}
-
-			/* Prepare registers */
-			buf_set_u32(reg_params[0].value, 0, 32, warea->address);
-			buf_set_u32(reg_params[1].value, 0, 32, offset);
-			buf_set_u32(reg_params[2].value, 0, 32, this_npages);
-			buf_set_u32(reg_params[3].value, 0, 32, FCTR);
-			buf_set_u32(reg_params[4].value, 0, 32, FPTR_EN_T | prog_time);
-
-			/* Execute algorithm, assume breakpoint for last instruction */
-			armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
-			armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
-			armv4_5_info.core_state = ARMV4_5_STATE_ARM;
-
-			retval = target_run_algorithm(target, 0, NULL, 5, reg_params,
-				(warea->address) + buffer_size,
-				(warea->address) + buffer_size + target_code_size - 4,
-				10000, /* 10s should be enough for max. 16 KiB of data */
-				&armv4_5_info);
-
-			if (retval != ERROR_OK)
-			{
-				LOG_ERROR("Execution of flash algorithm failed.");
-				target_free_all_working_areas(target);
-				retval = ERROR_FLASH_OPERATION_FAILED;
-				break;
-			}
-
-			count -= this_npages * FLASH_PAGE_SIZE;
-			buffer += this_npages * FLASH_PAGE_SIZE;
-			offset += this_npages * FLASH_PAGE_SIZE;
-		}
-
-		/* Free all resources */
-		destroy_reg_param(&reg_params[0]);
-		destroy_reg_param(&reg_params[1]);
-		destroy_reg_param(&reg_params[2]);
-		destroy_reg_param(&reg_params[3]);
-		destroy_reg_param(&reg_params[4]);
-		target_free_all_working_areas(target);
-	}
-	else
-	{
-		/* Write to flash memory page-wise */
-		while ( count != 0 )
-		{
-			/* How many bytes do we copy this time? */
-			num_bytes = (count >= FLASH_PAGE_SIZE) ?
-			            FLASH_PAGE_SIZE - (offset % FLASH_PAGE_SIZE) :
-			            count;
-
-			/* Don't do anything with it if the page is in a secured sector. */
-			if ( !bank->sectors[lpc2900_address2sector(bank, offset)].is_protected )
-			{
-				/* Set latch load mode */
-				target_write_u32(target, FCTR,
-				                 FCTR_FS_CS | FCTR_FS_WRE | FCTR_FS_WEB);
-
-				/* Always clear the buffer (a little overhead, but who cares) */
-				memset(page, 0xFF, FLASH_PAGE_SIZE);
-
-				/* Copy them to the buffer */
-				memcpy( &page[offset % FLASH_PAGE_SIZE],
-				        &buffer[offset % FLASH_PAGE_SIZE],
-				        num_bytes );
-
-				/* Write whole page to flash data latches */
-				if (target_write_memory(
-				                 target,
-				                 bank->base + (offset - (offset % FLASH_PAGE_SIZE)),
-				                 4, FLASH_PAGE_SIZE / 4, page) != ERROR_OK)
-				{
-					LOG_ERROR("Write failed @ 0x%8.8" PRIx32, offset);
-					target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
-
-					return ERROR_FLASH_OPERATION_FAILED;
-				}
-
-				/* Clear END_OF_BURN interrupt status */
-				target_write_u32(target, INT_CLR_STATUS, INTSRC_END_OF_BURN);
-
-				/* Set the programming time */
-				target_write_u32(target, FPTR, FPTR_EN_T | prog_time);
-
-				/* Trigger flash write */
-				target_write_u32(target, FCTR,
-				    FCTR_FS_CS | FCTR_FS_WRE | FCTR_FS_WPB | FCTR_FS_PROGREQ);
-
-				/* Wait for the end of the write operation. If it's not over
-				 * after one second, something went dreadfully wrong... :-(
-				 */
-				if (lpc2900_wait_status(bank, INTSRC_END_OF_BURN, 1000) != ERROR_OK)
-				{
-					LOG_ERROR("Write failed @ 0x%8.8" PRIx32, offset);
-					target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
-
-					return ERROR_FLASH_OPERATION_FAILED;
-				}
-			}
-
-			/* Update pointers and counters */
-			offset += num_bytes;
-			buffer += num_bytes;
-			count -= num_bytes;
-		}
-
-		retval = ERROR_OK;
-	}
-
-	/* Normal flash operating mode */
-	target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
-
-	return retval;
-}
-
-
-/**
- * Try and identify the device.
- *
- * Determine type number and its memory layout.
- *
- * @param bank Pointer to the flash bank descriptor
- */
-static int lpc2900_probe(struct flash_bank_s *bank)
-{
-	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
-	target_t *target = bank->target;
-	int i = 0;
-	uint32_t offset;
-
-
-	if (target->state != TARGET_HALTED)
-	{
-		LOG_ERROR("Target not halted");
-		return ERROR_TARGET_NOT_HALTED;
-	}
-
-	/* We want to do this only once. Check if we already have a valid CHIPID,
-	 * because then we will have already successfully probed the device.
-	 */
-	if (lpc2900_info->chipid == EXPECTED_CHIPID)
-	{
-		return ERROR_OK;
-	}
-
-	/* Probing starts with reading the CHIPID register. We will continue only
-	 * if this identifies as an LPC2900 device.
-	 */
-	target_read_u32(target, CHIPID, &lpc2900_info->chipid);
-
-	if (lpc2900_info->chipid != EXPECTED_CHIPID)
-	{
-		LOG_WARNING("Device is not an LPC29xx");
-		return ERROR_FLASH_OPERATION_FAILED;
-	}
-
-	/* It's an LPC29xx device. Now read the feature register FEAT0...FEAT3. */
-	uint32_t feat0, feat1, feat2, feat3;
-	target_read_u32(target, FEAT0, &feat0);
-	target_read_u32(target, FEAT1, &feat1);
-	target_read_u32(target, FEAT2, &feat2);
-	target_read_u32(target, FEAT3, &feat3);
-
-	/* Base address */
-	bank->base = 0x20000000;
-
-	/* Determine flash layout from FEAT2 register */
-	uint32_t num_64k_sectors = (feat2 >> 16) & 0xFF;
-	uint32_t num_8k_sectors = (feat2 >> 0) & 0xFF;
-	bank->num_sectors = num_64k_sectors + num_8k_sectors;
-	bank->size = KiB * (64 * num_64k_sectors + 8 * num_8k_sectors);
-
-	/* Determine maximum contiguous RAM block */
-	lpc2900_info->max_ram_block = 16 * KiB;
-	if( (feat1 & 0x30) == 0x30 )
-	{
-		lpc2900_info->max_ram_block = 32 * KiB;
-		if( (feat1 & 0x0C) == 0x0C )
-		{
-			lpc2900_info->max_ram_block = 48 * KiB;
-		}
-	}
-
-	/* Determine package code and ITCM size */
-	uint32_t package_code = feat0 & 0x0F;
-	uint32_t itcm_code = (feat1 >> 16) & 0x1F;
-
-	/* Determine the exact type number. */
-	uint32_t found = 1;
-	if ( (package_code == 4) && (itcm_code == 5) )
-	{
-		/* Old LPC2917 or LPC2919 (non-/01 devices) */
-		lpc2900_info->target_name = (bank->size == 768*KiB) ? "LPC2919" : "LPC2917";
-	}
-	else
-	{
-		if ( package_code == 2 )
-		{
-			/* 100-pin package */
-			if ( bank->size == 128*KiB )
-			{
-				lpc2900_info->target_name = "LPC2921";
-			}
-			else if ( bank->size == 256*KiB )
-			{
-				lpc2900_info->target_name = "LPC2923";
-			}
-			else if ( bank->size == 512*KiB )
-			{
-				lpc2900_info->target_name = "LPC2925";
-			}
-			else
-			{
-				found = 0;
-			}
-		}
-		else if ( package_code == 4 )
-		{
-			/* 144-pin package */
-			if ( (bank->size == 512*KiB) && (feat3 == 0xFFFFFCF0) )
-			{
-				lpc2900_info->target_name = "LPC2917/01";
-			}
-			else if ( (bank->size == 512*KiB) && (feat3 == 0xFFFFFFF1) )
-			{
-				lpc2900_info->target_name = "LPC2927";
-			}
-			else if ( (bank->size == 768*KiB) && (feat3 == 0xFFFFFCF8) )
-			{
-				lpc2900_info->target_name = "LPC2919/01";
-			}
-			else if ( (bank->size == 768*KiB) && (feat3 == 0xFFFFFFF9) )
-			{
-				lpc2900_info->target_name = "LPC2929";
-			}
-			else
-			{
-				found = 0;
-			}
-		}
-		else if ( package_code == 5 )
-		{
-			/* 208-pin package */
-			lpc2900_info->target_name = (bank->size == 0) ? "LPC2930" : "LPC2939";
-		}
-		else
-		{
-			found = 0;
-		}
-	}
-
-	if ( !found )
-	{
-		LOG_WARNING("Unknown LPC29xx derivative");
-		return ERROR_FLASH_OPERATION_FAILED;
-	}
-
-	/* Show detected device */
-	LOG_INFO("Flash bank %" PRIu32
-	         ": Device %s, %" PRIu32
-	         " KiB in %" PRIu32 " sectors",
-	         bank->bank_number,
-	         lpc2900_info->target_name, bank->size / KiB,
-	         bank->num_sectors);
-
-	/* Flashless devices cannot be handled */
-	if ( bank->num_sectors == 0 )
-	{
-		LOG_WARNING("Flashless device cannot be handled");
-		return ERROR_FLASH_OPERATION_FAILED;
-	}
-
-	/* Sector layout.
-	 * These are logical sector numbers. When doing real flash operations,
-	 * the logical flash number are translated into the physical flash numbers
-	 * of the device.
-	 */
-	bank->sectors = malloc(sizeof(flash_sector_t) * bank->num_sectors);
-
-	offset = 0;
-	for (i = 0; i < bank->num_sectors; i++)
-	{
-		bank->sectors[i].offset = offset;
-		bank->sectors[i].is_erased = -1;
-		bank->sectors[i].is_protected = -1;
-
-		if ( i <= 7 )
-		{
-			bank->sectors[i].size = 8 * KiB;
-		}
-		else if ( i <= 18 )
-		{
-			bank->sectors[i].size = 64 * KiB;
-		}
-		else
-		{
-			/* We shouldn't come here. But there might be a new part out there
-			 * that has more than 19 sectors. Politely ask for a fix then.
-			 */
-			bank->sectors[i].size = 0;
-			LOG_ERROR("Never heard about sector %" PRIu32 " (FIXME please)", i);
-		}
-
-		offset += bank->sectors[i].size;
-	}
-
-	/* Read sector security status */
-	if ( lpc2900_read_security_status(bank) != ERROR_OK )
-	{
-		LOG_ERROR("Cannot determine sector security status");
-		return ERROR_FLASH_OPERATION_FAILED;
-	}
-
-	return ERROR_OK;
-}
-
-
-/**
- * Run a blank check for each sector.
- *
- * For speed reasons, the device isn't read word by word.
- * A hash value is calculated by the hardware ("BIST") for each sector.
- * This value is then compared against the known hash of an empty sector.
- *
- * @param bank Pointer to the flash bank descriptor
- */
-static int lpc2900_erase_check(struct flash_bank_s *bank)
-{
-	uint32_t status = lpc2900_is_ready(bank);
-	if (status != ERROR_OK)
-	{
-		LOG_INFO("Processor not halted/not probed");
-		return status;
-	}
-
-	/* Use the BIST (Built-In Selft Test) to generate a signature of each flash
-	 * sector. Compare against the expected signature of an empty sector.
-	 */
-	int sector;
-	for ( sector = 0; sector < bank->num_sectors; sector++ )
-	{
-		uint32_t signature[4];
-		if ( (status = lpc2900_run_bist128( bank,
-		                                    bank->sectors[sector].offset,
-		                                    bank->sectors[sector].offset +
-		                                       (bank->sectors[sector].size - 1),
-		                                    &signature)) != ERROR_OK )
-		{
-			return status;
-		}
-
-		/* The expected signatures for an empty sector are different
-		 * for 8 KiB and 64 KiB sectors.
-		 */
-		if ( bank->sectors[sector].size == 8*KiB )
-		{
-			bank->sectors[sector].is_erased =
-			    (signature[3] == 0x01ABAAAA) &&
-			    (signature[2] == 0xAAAAAAAA) &&
-			    (signature[1] == 0xAAAAAAAA) &&
-			    (signature[0] == 0xAAA00AAA);
-		}
-		if ( bank->sectors[sector].size == 64*KiB )
-		{
-			bank->sectors[sector].is_erased =
-			    (signature[3] == 0x11801222) &&
-			    (signature[2] == 0xB88844FF) &&
-			    (signature[1] == 0x11A22008) &&
-			    (signature[0] == 0x2B1BFE44);
-		}
-	}
-
-	return ERROR_OK;
-}
-
-
-/**
- * Get protection (sector security) status.
- *
- * Determine the status of "sector security" for each sector.
- * A secured sector is one that can never be erased/programmed again.
- *
- * @param bank Pointer to the flash bank descriptor
- */
-static int lpc2900_protect_check(struct flash_bank_s *bank)
-{
-	return lpc2900_read_security_status(bank);
-}
-
-
-/**
- * Print info about the driver (not the device).
- *
- * @param bank Pointer to the flash bank descriptor
- * @param buf Buffer to take the string
- * @param buf_size Maximum number of characters that the buffer can take
- */
-static int lpc2900_info(struct flash_bank_s *bank, char *buf, int buf_size)
-{
-	snprintf(buf, buf_size, "lpc2900 flash driver");
-
-	return ERROR_OK;
-}
-
-
-flash_driver_t lpc2900_flash =
-{
-	.name               = "lpc2900",
-	.register_commands  = lpc2900_register_commands,
-	.flash_bank_command = lpc2900_flash_bank_command,
-	.erase              = lpc2900_erase,
-	.protect            = lpc2900_protect,
-	.write              = lpc2900_write,
-	.probe              = lpc2900_probe,
-	.auto_probe         = lpc2900_probe,
-	.erase_check        = lpc2900_erase_check,
-	.protect_check      = lpc2900_protect_check,
-	.info               = lpc2900_info
-};
+/***************************************************************************
+ *   Copyright (C) 2009 by                                                 *
+ *   Rolf Meeser <rol...@ya...>                                      *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+
+#include "image.h"
+
+#include "lpc2900.h"
+#include "binarybuffer.h"
+#include "armv4_5.h"
+
+
+/* 1024 bytes */
+#define KiB                 1024
+
+/* Some flash constants */
+#define FLASH_PAGE_SIZE     512     /* bytes */
+#define FLASH_ERASE_TIME    100000  /* microseconds */
+#define FLASH_PROGRAM_TIME  1000    /* microseconds */
+
+/* Chip ID / Feature Registers */
+#define CHIPID          0xE0000000  /* Chip ID */
+#define FEAT0           0xE0000100  /* Chip feature 0 */
+#define FEAT1           0xE0000104  /* Chip feature 1 */
+#define FEAT2           0xE0000108  /* Chip feature 2 (contains flash size indicator) */
+#define FEAT3           0xE000010C  /* Chip feature 3 */
+
+#define EXPECTED_CHIPID 0x209CE02B  /* Chip ID of all LPC2900 devices */
+
+/* Flash/EEPROM Control Registers */
+#define FCTR            0x20200000  /* Flash control */
+#define FPTR            0x20200008  /* Flash program-time */
+#define FTCTR           0x2020000C  /* Flash test control */
+#define FBWST           0x20200010  /* Flash bridge wait-state */
+#define FCRA            0x2020001C  /* Flash clock divider */
+#define FMSSTART        0x20200020  /* Flash Built-In Selft Test start address */
+#define FMSSTOP         0x20200024  /* Flash Built-In Selft Test stop address */
+#define FMS16           0x20200028  /* Flash 16-bit signature */
+#define FMSW0           0x2020002C  /* Flash 128-bit signature Word 0 */
+#define FMSW1           0x20200030  /* Flash 128-bit signature Word 1 */
+#define FMSW2           0x20200034  /* Flash 128-bit signature Word 2 */
+#define FMSW3      ...
 
[truncated message content]

[Openocd-svn] r2746 - in trunk: doc src/flash

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-22 07:39:06 +0200 (Tue, 22 Sep 2009)
New Revision: 2746

Modified:
   trunk/doc/openocd.texi
   trunk/src/flash/flash.c
Log:
Make it easier to erase or protect through to the end
of a (NOR) flash chip: allow passing "last" as an alias
for the number of the last sector.

Improve several aspects of error checking while we're at it.

From: Johnny Halfmoon <jha...@mi...>


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-09-21 21:35:56 UTC (rev 2745)
+++ trunk/doc/openocd.texi	2009-09-22 05:39:06 UTC (rev 2746)
@@ -3187,8 +3187,11 @@
 
 @anchor{flash erase_sector}
 @deffn Command {flash erase_sector} num first last
-Erase sectors in bank @var{num}, starting at sector @var{first} up to and including
-@var{last}. Sector numbering starts at 0.
+Erase sectors in bank @var{num}, starting at sector @var{first}
+up to and including @var{last}.
+Sector numbering starts at 0.
+Providing a @var{last} sector of @option{last}
+specifies "to the end of the flash bank".
 The @var{num} parameter is a value shown by @command{flash banks}.
 @end deffn
 
@@ -3247,7 +3250,7 @@
 The @var{num} parameter is a value shown by @command{flash banks}.
 This is the only operation that
 updates the erase state information displayed by @option{flash info}. That means you have
-to issue an @command{flash erase_check} command after erasing or programming the device
+to issue a @command{flash erase_check} command after erasing or programming the device
 to get updated information.
 (Code execution may have invalidated any state records kept by OpenOCD.)
 @end deffn
@@ -3259,9 +3262,12 @@
 @end deffn
 
 @anchor{flash protect}
-@deffn Command {flash protect} num first last (on|off)
-Enable (@var{on}) or disable (@var{off}) protection of flash sectors
-@var{first} to @var{last} of flash bank @var{num}.
+@deffn Command {flash protect} num first last (@option{on}|@option{off})
+Enable (@option{on}) or disable (@option{off}) protection of flash sectors
+in flash bank @var{num}, starting at sector @var{first}
+and continuing up to and including @var{last}.
+Providing a @var{last} sector of @option{last}
+specifies "to the end of the flash bank".
 The @var{num} parameter is a value shown by @command{flash banks}.
 @end deffn
 

Modified: trunk/src/flash/flash.c
===================================================================
--- trunk/src/flash/flash.c	2009-09-21 21:35:56 UTC (rev 2745)
+++ trunk/src/flash/flash.c	2009-09-22 05:39:06 UTC (rev 2746)
@@ -559,82 +559,121 @@
 	return ERROR_OK;
 }
 
-static int handle_flash_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int flash_check_sector_parameters(struct command_context_s *cmd_ctx,
+		uint32_t first, uint32_t last, uint num_sectors)
 {
+	if (!(first <= last)) {
+		command_print(cmd_ctx, "ERROR: "
+				"first sector must be <= last sector");
+		return ERROR_FAIL;
+	}
+
+	if (!(last <= (num_sectors - 1))) {
+		command_print(cmd_ctx, "ERROR: "
+				"last sector must be <= %d", num_sectors - 1);
+		return ERROR_FAIL;
+	}
+
+	return ERROR_OK;
+}
+
+static int handle_flash_erase_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
+{
 	if (argc > 2)
 	{
-		int first = strtoul(args[1], NULL, 0);
-		int last = strtoul(args[2], NULL, 0);
+		uint32_t bank_nr;
+		uint32_t first;
+		uint32_t last;
 		int retval;
-		flash_bank_t *p = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
-		duration_t duration;
-		char *duration_text;
 
-		duration_start_measure(&duration);
+		if ((retval = parse_u32(args[0], &bank_nr)) != ERROR_OK)
+			return retval;
 
+		flash_bank_t *p = get_flash_bank_by_num(bank_nr);
 		if (!p)
-		{
-			return ERROR_COMMAND_SYNTAX_ERROR;
-		}
+			return ERROR_OK;
 
-		if ((retval = flash_driver_erase(p, first, last)) == ERROR_OK)
-		{
-			if ((retval = duration_stop_measure(&duration, &duration_text)) != ERROR_OK)
-			{
+		if ((retval = parse_u32(args[1], &first)) != ERROR_OK)
+			return retval;
+		if (strcmp(args[2], "last") == 0)
+			last = p->num_sectors - 1;
+		else
+			if ((retval = parse_u32(args[2], &last)) != ERROR_OK)
 				return retval;
-			}
 
-			command_print(cmd_ctx, "erased sectors %i through %i on flash bank %li in %s",
-				first, last, strtoul(args[0], 0, 0), duration_text);
+		if ((retval = flash_check_sector_parameters(cmd_ctx,
+				first, last, p->num_sectors)) != ERROR_OK)
+			return retval;
+
+		duration_t duration;
+		char *duration_text;
+		duration_start_measure(&duration);
+
+		if ((retval = flash_driver_erase(p, first, last)) == ERROR_OK) {
+			if ((retval = duration_stop_measure(&duration,
+						&duration_text)) != ERROR_OK)
+				return retval;
+			command_print(cmd_ctx, "erased sectors %i through %i "
+					"on flash bank %i in %s",
+				first, last, bank_nr, duration_text);
 			free(duration_text);
 		}
 	}
 	else
-	{
 		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
 
 	return ERROR_OK;
 }
 
-static int handle_flash_protect_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int handle_flash_protect_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	if (argc > 3)
 	{
-		int first = strtoul(args[1], NULL, 0);
-		int last = strtoul(args[2], NULL, 0);
+		uint32_t bank_nr;
+		uint32_t first;
+		uint32_t last;
+		int retval;
 		int set;
-		int retval;
-		flash_bank_t *p = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
+
+		if ((retval = parse_u32(args[0], &bank_nr)) != ERROR_OK)
+			return retval;
+
+		flash_bank_t *p = get_flash_bank_by_num(bank_nr);
 		if (!p)
-		{
-			command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
 			return ERROR_OK;
-		}
 
+		if ((retval = parse_u32(args[1], &first)) != ERROR_OK)
+			return retval;
+		if (strcmp(args[2], "last") == 0)
+			last = p->num_sectors - 1;
+		else
+			if ((retval = parse_u32(args[2], &last)) != ERROR_OK)
+				return retval;
+
 		if (strcmp(args[3], "on") == 0)
 			set = 1;
 		else if (strcmp(args[3], "off") == 0)
 			set = 0;
 		else
-		{
 			return ERROR_COMMAND_SYNTAX_ERROR;
-		}
 
+		if ((retval = flash_check_sector_parameters(cmd_ctx,
+				first, last, p->num_sectors)) != ERROR_OK)
+			return retval;
+
 		retval = flash_driver_protect(p, set, first, last);
-		if (retval == ERROR_OK)
-		{
-			command_print(cmd_ctx, "%s protection for sectors %i through %i on flash bank %li",
+		if (retval == ERROR_OK) {
+			command_print(cmd_ctx, "%s protection for sectors %i "
+					"through %i on flash bank %i",
 				(set) ? "set" : "cleared", first,
-				last, strtoul(args[0], 0, 0));
+				last, bank_nr);
 		}
 	}
 	else
-	{
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	}
-
 	return ERROR_OK;
 }
 

[Openocd-svn] r2745 - trunk/doc

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-21 23:35:56 +0200 (Mon, 21 Sep 2009)
New Revision: 2745

Modified:
   trunk/doc/openocd.texi
Log:
Update presentation of TAP events and tap enable/disable.

Highlight that the "post-reset" event kicks in before the
scan chain is validated, which limits what can be done
in a post-reset handler.


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-09-21 18:52:45 UTC (rev 2744)
+++ trunk/doc/openocd.texi	2009-09-21 21:35:56 UTC (rev 2745)
@@ -2343,12 +2343,69 @@
 @end itemize
 @end deffn
 
+@section Other TAP commands
+
 @c @deffn Command {jtag arp_init-reset}
-@c ... more or less "init" ?
+@c ... more or less "toggle TRST ... and SRST too, what the heck"
 
+@deffn Command {jtag cget} dotted.name @option{-event} name
+@deffnx Command {jtag configure} dotted.name @option{-event} name string
+At this writing this TAP attribute
+mechanism is used only for event handling.
+(It is not a direct analogue of the @code{cget}/@code{configure}
+mechanism for debugger targets.)
+See the next section for information about the available events.
+
+The @code{configure} subcommand assigns an event handler,
+a TCL string which is evaluated when the event is triggered.
+The @code{cget} subcommand returns that handler.
+@end deffn
+
+@anchor{TAP Events}
+@section TAP Events
+@cindex events
+@cindex TAP events
+
+OpenOCD includes two event mechanisms.
+The one presented here applies to all JTAG TAPs.
+The other applies to debugger targets,
+which are associated with certain TAPs.
+
+The TAP events currently defined are:
+
+@itemize @bullet
+@item @b{post-reset}
+@* The TAP has just completed a JTAG reset.
+For the first such handler called, the tap is still
+in the JTAG @sc{reset} state.
+Because the scan chain has not yet been verified, handlers for these events
+@emph{should not issue commands which scan the JTAG IR or DR registers}
+of any particular target.
+@b{NOTE:} As this is written (September 2009), nothing prevents such access.
+@item @b{tap-disable}
+@* The TAP needs to be disabled.  This handler should
+implement @command{jtag tapdisable}
+by issuing the relevant JTAG commands.
+@item @b{tap-enable}
+@* The TAP needs to be enabled.  This handler should
+implement @command{jtag tapenable}
+by issuing the relevant JTAG commands.
+@end itemize
+
+If you need some action after each JTAG reset, which isn't actually
+specific to any TAP (since you can't yet trust the scan chain's
+contents to be accurate), you might:
+
+@example
+jtag configure CHIP.jrc -event post-reset @{
+  echo "Reset done"
+  ... non-scan jtag operations to be done after reset
+@}
+@end example
+
+
 @anchor{Enabling and Disabling TAPs}
 @section Enabling and Disabling TAPs
-@cindex TAP events
 @cindex JTAG Route Controller
 @cindex jrc
 
@@ -2380,20 +2437,9 @@
 
 @c (a) currently the event handlers don't seem to be able to
 @c     fail in a way that could lead to no-change-of-state.
-@c (b) eventually non-event configuration should be possible,
-@c     in which case some this documentation must move.
 
-@deffn Command {jtag cget} dotted.name @option{-event} name
-@deffnx Command {jtag configure} dotted.name @option{-event} name string
-At this writing this mechanism is used only for event handling.
-Three events are available. Two events relate to TAP enabling
-and disabling, one to post reset handling.
-
-The @code{configure} subcommand assigns an event handler,
-a TCL string which is evaluated when the event is triggered.
-The @code{cget} subcommand returns that handler.
-The three possible values for an event @var{name} are @option{tap-disable}, @option{tap-enable} and @option{post-reset}.
-
+In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
+shown below, and is implemented using TAP event handlers.
 So for example, when defining a TAP for a CPU connected to
 a JTAG router, you should define TAP event handlers using
 code that looks something like this:
@@ -2409,30 +2455,29 @@
 @}
 @end example
 
-If you need some post reset action, you can do:
+@deffn Command {jtag tapdisable} dotted.name
+If necessary, disables the tap
+by sending it a @option{tap-disable} event.
+Returns the string "1" if the tap
+specified by @var{dotted.name} is enabled,
+and "0" if it is disbabled.
+@end deffn
 
-@example
-jtag configure CHIP.cpu -event post-reset @{
-  echo "Reset done"
-  ... jtag operations to be done after reset
-@}
-@end example
+@deffn Command {jtag tapenable} dotted.name
+If necessary, enables the tap
+by sending it a @option{tap-enable} event.
+Returns the string "1" if the tap
+specified by @var{dotted.name} is enabled,
+and "0" if it is disbabled.
 @end deffn
 
-@deffn Command {jtag tapdisable} dotted.name
-@deffnx Command {jtag tapenable} dotted.name
-@deffnx Command {jtag tapisenabled} dotted.name
-These three commands all return the string "1" if the tap
+@deffn Command {jtag tapisenabled} dotted.name
+Returns the string "1" if the tap
 specified by @var{dotted.name} is enabled,
 and "0" if it is disbabled.
-The @command{tapenable} variant first enables the tap
-by sending it a @option{tap-enable} event.
-The @command{tapdisable} variant first disables the tap
-by sending it a @option{tap-disable} event.
 
 @quotation Note
 Humans will find the @command{scan_chain} command more helpful
-than the script-oriented @command{tapisenabled}
 for querying the state of the JTAG taps.
 @end quotation
 @end deffn
@@ -2889,6 +2934,7 @@
 
 @anchor{Target Events}
 @section Target Events
+@cindex target events
 @cindex events
 At various times, certain things can happen, or you want them to happen.
 For example:

[Openocd-svn] r2744 - in trunk/doc: . manual manual/primer manual/target

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-21 20:52:45 +0200 (Mon, 21 Sep 2009)
New Revision: 2744

Modified:
   trunk/doc/INSTALL.txt
   trunk/doc/manual/flash.txt
   trunk/doc/manual/jtag.txt
   trunk/doc/manual/primer/autotools.txt
   trunk/doc/manual/primer/docs.txt
   trunk/doc/manual/primer/jtag.txt
   trunk/doc/manual/primer/patches.txt
   trunk/doc/manual/primer/tcl.txt
   trunk/doc/manual/release.txt
   trunk/doc/manual/scripting.txt
   trunk/doc/manual/server.txt
   trunk/doc/manual/style.txt
   trunk/doc/manual/target/notarm.txt
   trunk/doc/openocd.1
   trunk/doc/openocd.texi
Log:
Remove annoying end-of-line whitespace from doc/* files.


Modified: trunk/doc/INSTALL.txt
===================================================================
--- trunk/doc/INSTALL.txt	2009-09-21 18:48:22 UTC (rev 2743)
+++ trunk/doc/INSTALL.txt	2009-09-21 18:52:45 UTC (rev 2744)
@@ -16,7 +16,7 @@
 Basic Installation
 ==================
 
-   OpenOCD is distributed without autotools generated files, i.e. without a 
+   OpenOCD is distributed without autotools generated files, i.e. without a
 configure script. Run ./bootstrap in the openocd directory to have all
 necessary files generated.
 
@@ -77,7 +77,7 @@
      documentation.
 
   4. You can remove the program binaries and object files from the
-     source code directory by typing `make clean'.  
+     source code directory by typing `make clean'.
 
 Compilers and Options
 =====================

Modified: trunk/doc/manual/flash.txt
===================================================================
--- trunk/doc/manual/flash.txt	2009-09-21 18:48:22 UTC (rev 2743)
+++ trunk/doc/manual/flash.txt	2009-09-21 18:52:45 UTC (rev 2744)
@@ -7,7 +7,7 @@
 
 The Flash module provides the following APIs:
 
-  - @subpage flashcfi 
+  - @subpage flashcfi
   - @subpage flashnand
   - @subpage flashtarget
 

Modified: trunk/doc/manual/jtag.txt
===================================================================
--- trunk/doc/manual/jtag.txt	2009-09-21 18:48:22 UTC (rev 2743)
+++ trunk/doc/manual/jtag.txt	2009-09-21 18:52:45 UTC (rev 2744)
@@ -32,7 +32,7 @@
     - includes the Cable/TAP API (commands starting with @c tap_)
 
 - @subpage jtagdriver
-  - @b private minidriver API 
+  - @b private minidriver API
   - declared in @c src/jtag/minidriver.h
   - used @a only by the core and minidriver implementations:
     - @c jtag_driver.c (in-tree OpenOCD drivers)

Modified: trunk/doc/manual/primer/autotools.txt
===================================================================
--- trunk/doc/manual/primer/autotools.txt	2009-09-21 18:48:22 UTC (rev 2743)
+++ trunk/doc/manual/primer/autotools.txt	2009-09-21 18:52:45 UTC (rev 2744)
@@ -144,7 +144,7 @@
 The <code>make distcheck</code> command produces an archive of the
 project deliverables (using <code>make dist</code>) and verifies its
 integrity for distribution by attemptng to use the package in the same
-manner as a user.  
+manner as a user.
 
 These checks includes the following steps:
 -# Unpack the project archive into its expected directory.

Modified: trunk/doc/manual/primer/docs.txt
===================================================================
--- trunk/doc/manual/primer/docs.txt	2009-09-21 18:48:22 UTC (rev 2743)
+++ trunk/doc/manual/primer/docs.txt	2009-09-21 18:52:45 UTC (rev 2744)
@@ -90,7 +90,7 @@
 To support out-of-tree building of the documentation, the @c Doxyfile.in
 @c INPUT values will have all instances of the string @c "@srcdir@"
 replaced with the current value of the make variable
-<code>$(srcdir)</code>.  The Makefile uses a rule to convert 
+<code>$(srcdir)</code>.  The Makefile uses a rule to convert
 @c Doxyfile.in into the @c Doxyfile used by <code>make doxygen</code>.
 
 @section primerdoxyoocd OpenOCD Input Files
@@ -105,7 +105,7 @@
 New files containing valid Doxygen markup that are placed in or under
 that directory will be detected and included in The Manual automatically.
 
-@section primerdoxyman Doxygen Reference Manual 
+@section primerdoxyman Doxygen Reference Manual
 
 The full documentation for Doxygen can be referenced on-line at the project
 home page: http://www.doxygen.org/index.html.  In HTML versions of this

Modified: trunk/doc/manual/primer/jtag.txt
===================================================================
--- trunk/doc/manual/primer/jtag.txt	2009-09-21 18:48:22 UTC (rev 2743)
+++ trunk/doc/manual/primer/jtag.txt	2009-09-21 18:52:45 UTC (rev 2744)
@@ -1,14 +1,14 @@
 /** @page primerjtag OpenOCD JTAG Primer
 
-JTAG is unnecessarily confusing, because JTAG is often confused with 
+JTAG is unnecessarily confusing, because JTAG is often confused with
 boundary scan, which is just one of its possible functions.
 
-JTAG is simply a communication interface designed to allow communication 
-to functions contained on devices, for the designed purposes of 
-initialisation, programming, testing, debugging, and anything else you 
+JTAG is simply a communication interface designed to allow communication
+to functions contained on devices, for the designed purposes of
+initialisation, programming, testing, debugging, and anything else you
 want to use it for (as a chip designer).
 
-Think of JTAG as I2C for testing.  It doesn't define what it can do, 
+Think of JTAG as I2C for testing.  It doesn't define what it can do,
 just a logical interface that allows a uniform channel for communication.
 
 See @par
@@ -17,42 +17,42 @@
 and @par
 	http://www.inaccessnetworks.com/projects/ianjtag/jtag-intro/jtag-state-machine-large.png
 
-The first page (among other things) shows a logical representation 
-describing how multiple devices are wired up using JTAG.  JTAG does not 
-specify, data rates or interface levels (3.3V/1.8V, etc) each device can 
-support different data rates/interface logic levels.  How to wire them 
+The first page (among other things) shows a logical representation
+describing how multiple devices are wired up using JTAG.  JTAG does not
+specify, data rates or interface levels (3.3V/1.8V, etc) each device can
+support different data rates/interface logic levels.  How to wire them
 in a compatible way is an exercise for an engineer.
 
-Basically TMS controls which shift register is placed on the device, 
-between TDI and TDO.  The second diagram shows the state transitions on 
+Basically TMS controls which shift register is placed on the device,
+between TDI and TDO.  The second diagram shows the state transitions on
 TMS which will select different shift registers.
 
-The first thing you need to do is reset the state machine, because when 
-you connect to a chip you do not know what state the controller is in,you need 
-to clock TMS as 1, at least 7 times.  This will put you into "Test Logic 
-Reset" State.  Knowing this, you can, once reset, then track what each 
-transition on TMS will do, and hence know what state the JTAG state 
+The first thing you need to do is reset the state machine, because when
+you connect to a chip you do not know what state the controller is in,you need
+to clock TMS as 1, at least 7 times.  This will put you into "Test Logic
+Reset" State.  Knowing this, you can, once reset, then track what each
+transition on TMS will do, and hence know what state the JTAG state
 machine is in.
 
-There are 2 "types" of shift registers.  The Instruction shift register 
-and the data shift register.  The sizes of these are undefined, and can 
-change from chip to chip.  The Instruction register is used to select 
-which Data register/data register function is used, and the data 
+There are 2 "types" of shift registers.  The Instruction shift register
+and the data shift register.  The sizes of these are undefined, and can
+change from chip to chip.  The Instruction register is used to select
+which Data register/data register function is used, and the data
 register is used to read data from that function or write data to it.
 
-Each of the states control what happens to either the data register or 
+Each of the states control what happens to either the data register or
 instruction register.
 
-For example, one of the data registers will be known as "bypass" this is 
-(usually) a single bit which has no function and is used to bypass the 
-chip.  Assume we have 3 identical chips, wired up like the picture 
-and each has a 3 bit instruction register, and there are 2 known 
-instructions (110 = bypass, 010 = some other function) if we want to use 
-"some other function", on the second chip in the line, and not change 
+For example, one of the data registers will be known as "bypass" this is
+(usually) a single bit which has no function and is used to bypass the
+chip.  Assume we have 3 identical chips, wired up like the picture
+and each has a 3 bit instruction register, and there are 2 known
+instructions (110 = bypass, 010 = some other function) if we want to use
+"some other function", on the second chip in the line, and not change
 the other chips we would do the following transitions.
 
 From Test Logic Reset, TMS goes:
- 
+
   0 1 1 0 0
 
 which puts every chip in the chain into the "Shift IR state"
@@ -60,7 +60,7 @@
 
   0 1 1  0 1 0  0 1 1
 
-which puts the following values in the instruction shift register for 
+which puts the following values in the instruction shift register for
 each chip [110] [010] [110]
 
 The order is reversed, because we shift out the least significant bit
@@ -70,18 +70,18 @@
 
 which puts us in the "Shift DR state".
 
-Now when we clock data onto TDI (again while holding TMS to 0) , the 
-data shifts through the data registers, and because of the instruction 
-registers we selected (some other function has 8 bits in its data 
+Now when we clock data onto TDI (again while holding TMS to 0) , the
+data shifts through the data registers, and because of the instruction
+registers we selected (some other function has 8 bits in its data
 register), our total data register in the chain looks like this:
 
   0 00000000 0
 
-The first and last bit are in the "bypassed" chips, so values read from 
-them are irrelevant and data written to them is ignored.  But we need to 
+The first and last bit are in the "bypassed" chips, so values read from
+them are irrelevant and data written to them is ignored.  But we need to
 write bits for those registers, because they are in the chain.
 
-If we wanted to write 0xF5 to the data register we would clock out of 
+If we wanted to write 0xF5 to the data register we would clock out of
 TDI (holding TMS to 0):
 
   0 1 0 1 0 1 1 1 1 0
@@ -91,13 +91,13 @@
 
   1 1 0
 
-which updates the selected data register with the value 0xF5 and returns 
+which updates the selected data register with the value 0xF5 and returns
 us to run test idle.
 
-If we needed to read the data register before over-writing it with F5, 
-no sweat, that's already done, because the TDI/TDO are set up as a 
-circular shift register, so if you write enough bits to fill the shift 
-register, you will receive the "captured" contents of the data registers 
+If we needed to read the data register before over-writing it with F5,
+no sweat, that's already done, because the TDI/TDO are set up as a
+circular shift register, so if you write enough bits to fill the shift
+register, you will receive the "captured" contents of the data registers
 simultaneously on TDO.
 
 That's JTAG in a nutshell.  On top of this, you need to get specs for

Modified: trunk/doc/manual/primer/patches.txt
===================================================================
--- trunk/doc/manual/primer/patches.txt	2009-09-21 18:48:22 UTC (rev 2743)
+++ trunk/doc/manual/primer/patches.txt	2009-09-21 18:52:45 UTC (rev 2744)
@@ -8,7 +8,7 @@
 The standard method for creating patches requires developers to:
 - checkout the Subversion repository (or bring a copy up-to-date),
 - make the necessary modifications to a working copy,
-- check with 'svn status' to see which files will be modified/added, and 
+- check with 'svn status' to see which files will be modified/added, and
 - use 'svn diff' to review the changes and produce a patch.
 
 It is important to minimize the changes to only those lines that contain
@@ -67,7 +67,7 @@
 <code>svn diff</code>.  Overlapping patches will be discussed in the
 next section.
 
-The remainder of this section provides 
+The remainder of this section provides
 
 @subsection primerpatchprops Subversion Properties
 
@@ -110,7 +110,7 @@
 svn diff foo | unix2dos | patch -R
 @endcode
 
-This is not a bug. 
+This is not a bug.
 
 @todo Does Subversion's treatment of line-endings for files marked with
 svn:eol-style=native continue to pose the problems described here, or

Modified: trunk/doc/manual/primer/tcl.txt
===================================================================
--- trunk/doc/manual/primer/tcl.txt	2009-09-21 18:48:22 UTC (rev 2743)
+++ trunk/doc/manual/primer/tcl.txt	2009-09-21 18:52:45 UTC (rev 2744)
@@ -115,7 +115,7 @@
 
        set x "2 * 6"
        set foo([expr $x])  "twelve"
-       
+
 **************************************************
 ***************************************************
 === TCL TOUR ===
@@ -133,7 +133,7 @@
 In TCL, "FOR" is a funny thing, it is not what you think it is.
 
 Syntactically - FOR is a just a command, it is not language
-construct like for(;;) in C... 
+construct like for(;;) in C...
 
 The "for" command takes 4 parameters.
    (1) The "initial command" to execute.
@@ -215,7 +215,7 @@
  (2)  NAME( array )
       And the array must have some specific names:
           ( <idx>, THING )
-	    Where: THING is one of: 
+	    Where: THING is one of:
 		   CHIPSELECT
 		   BASE
 		   LEN
@@ -224,7 +224,7 @@
 		   RWX - the access ability.
 		   WIDTH - the accessible width.
 
-        ie: Some regions of memory are not 'word' 
+        ie: Some regions of memory are not 'word'
 	accessible.
 
 The function "address_info" - given an address should
@@ -237,14 +237,14 @@
 MAJOR FUNCTION:
 ==
 
-proc memread32 { ADDR } 
-proc memread16 { ADDR } 
-proc memread8 { ADDR } 
+proc memread32 { ADDR }
+proc memread16 { ADDR }
+proc memread8 { ADDR }
 
 All read memory - and return the contents.
 
 [ FIXME: 7/5/2008 - I need to create "memwrite" functions]
-		 
+
 **************************************************
 ***************************************************
 === TCL TOUR ===
@@ -265,13 +265,13 @@
      FOO_linux = "Penguins rule"
      FOO_winXP = "Broken Glass"
      FOO_mac   = "I like cat names"
-     
+
      # Pick one
      BUILD  = linux
      #BUILD = winXP
      #BUILD = mac
      FOO = ${FOO_${BUILD}}
-				
+
 The "double [set] square bracket" thing is the TCL way, nothing more.
 
 ----
@@ -290,7 +290,7 @@
 The "IF" command expects either 2 params, or 4 params.
 
  === Sidebar: About "commands" ===
-  
+
      Take a look at the internals of "jim.c"
      Look for the function: Jim_IfCoreCommand()
      And all those other "CoreCommands"
@@ -298,10 +298,10 @@
      You'll notice - they all have "argc" and "argv"
 
      Yea, the entire thing is done that way.
-     
+
      IF is a command. SO is "FOR" and "WHILE" and "DO" and the
      others. That is why I keep using the phase it is a "command"
-     
+
  === END: Sidebar: About "commands" ===
 
 Parameter 1 to the IF command is expected to be an expression.
@@ -315,7 +315,7 @@
 You give CATCH 1 or 2 parameters.
     The first 1st parameter is the "code to execute"
     The 2nd (optional) is where to put the error message.
-    
+
     CATCH returns 0 on success, 1 for failure.
     The "![catch command]" is self explaintory.
 
@@ -325,7 +325,7 @@
 be joined by exactly the words "else" or "elseif".
 
 The 4th parameter contains:
-    
+
     "error [format STRING....]"
 
 This lets me modify the previous lower level error by tacking more
@@ -346,7 +346,7 @@
 function pointer - and calling the function pointer.
 
 In this case - I execute a dynamic command. You can do some cool
-tricks with interpretors. 
+tricks with interpretors.
 
 ----------
 
@@ -380,7 +380,7 @@
 
 The "CHIP" file has defined some variables in a proper form.
 
-ie:   AT91C_BASE_US0 - for usart0, 
+ie:   AT91C_BASE_US0 - for usart0,
       AT91C_BASE_US1 - for usart1
       ... And so on ...
 
@@ -419,9 +419,9 @@
 With that little bit of code - I now have a bunch of functions like:
 
    show_US0, show_US1, show_US2, .... etc ...
-   
+
    And show_US0_MR, show_US0_IMR ... etc...
-  
+
 And - I have this for every USART... without having to create tons of
 boiler plate yucky code.
 

Modified: trunk/doc/manual/release.txt
===================================================================
--- trunk/doc/manual/release.txt	2009-09-21 18:48:22 UTC (rev 2743)
+++ trunk/doc/manual/release.txt	2009-09-21 18:52:45 UTC (rev 2744)
@@ -113,7 +113,7 @@
 
 The OpenOCD release process must be carried out on a periodic basis, so
 the project can realize the benefits presented in answer to the question,
-@ref releasewhy.  
+@ref releasewhy.
 
 Starting with the 0.2.0 release, the OpenOCD project should produce a
 new minor release every month or two, with a major release once a year.
@@ -132,7 +132,7 @@
 release.  This section presents guidelines for scheduling key points
 where the community must be informed of changing conditions.
 
-If T is the time of the next release, then the following schedule 
+If T is the time of the next release, then the following schedule
 might describe some of the key milestones of the new release cycle:
 
 - T minus one month: start of new development cycle
@@ -190,7 +190,7 @@
 The following steps should be followed to produce each release:
 
 -# Produce final patches to the trunk (or release branch):
-  -# Finalize @c NEWS file to describe the changes in the release 
+  -# Finalize @c NEWS file to describe the changes in the release
     - This file is Used to automatically post "blurbs" about the project.
     - This material should be produced during the development cycle.
     - Add a new item for each @c NEWS-worthy contribution, when committed.
@@ -208,7 +208,7 @@
 svn cp .../branches/${RELEASE_BRANCH} .../tags/${RELEASE_TAG}
 @endverbatim
   - For bug-fix releases produced in their respective branch, a tag
-    should be created in the repository: 
+    should be created in the repository:
 @verbatim
 svn cp .../branches/${RELEASE_BRANCH} .../tags/${RELEASE_TAG}
 @endverbatim

Modified: trunk/doc/manual/scripting.txt
===================================================================
--- trunk/doc/manual/scripting.txt	2009-09-21 18:48:22 UTC (rev 2743)
+++ trunk/doc/manual/scripting.txt	2009-09-21 18:52:45 UTC (rev 2744)
@@ -5,7 +5,7 @@
 The scripting support is intended for developers of OpenOCD.
 It is not the intention that normal OpenOCD users will
 use tcl scripting extensively, write lots of clever scripts,
-or contribute back to OpenOCD. 
+or contribute back to OpenOCD.
 
 Target scripts can contain new procedures that end users may
 tinker to their needs without really understanding tcl.
@@ -31,7 +31,7 @@
     file format and structure of serialnumber. Tcl allows
     an argument to consist of e.g. a list so the structure of
     the serial number is not limited to a single string.
-  - reset handling. Precise control of how srst, trst & 
+  - reset handling. Precise control of how srst, trst &
     tms is handled.
 - replace some parts of the current command line handler.
   This is only to simplify the implementation of OpenOCD
@@ -42,7 +42,7 @@
   that return machine readable output. These low level tcl
   functions constitute the tcl api. flash_banks is such
   a low level tcl proc. "flash banks" is an example of
-  a command that has human readable output. The human 
+  a command that has human readable output. The human
   readable output is expected to change inbetween versions
   of OpenOCD. The output from flash_banks may not be
   in the preferred form for the client. The client then
@@ -50,8 +50,8 @@
   or b) write a small piece of tcl to output the
   flash_banks output to a more suitable form. The latter may
   be simpler.
-  
-  
+
+
 @section scriptingexternal External scripting
 
 The embedded Jim Tcl interpreter in OpenOCD is very limited

Modified: trunk/doc/manual/server.txt
===================================================================
--- trunk/doc/manual/server.txt	2009-09-21 18:48:22 UTC (rev 2743)
+++ trunk/doc/manual/server.txt	2009-09-21 18:52:45 UTC (rev 2744)
@@ -32,14 +32,14 @@
 - the ablity to write a complex internal commands: native 'commands'
   inside of OpenOCD was complicated.
 
-Fundamentally, the basic problem with both of those would be solved 
+Fundamentally, the basic problem with both of those would be solved
 with a script language:
 
 -# <b>Internal</b>: simple, small, and self-contained.
 -# <b>Cross Language</b>: script friendly front-end
 -# <b>Cross Host</b>: GUI Host interface
 -# <b>Cross Debugger</b>: GUI-like interface
-  
+
 What follows hopefully shows how the plans to solve these problems
 materialized and help to explain the grand roadmap plan.
 
@@ -64,7 +64,7 @@
 
 The TCL Server port was added in mid-2008.  With embedded TCL, we can
 write scripts internally to help things, or we can write "C" code  that
-interfaces well with TCL. 
+interfaces well with TCL.
 
 From there, the developers wanted to create an external front-end that
 would be @a very usable and that that @a any language could utilize,
@@ -81,7 +81,7 @@
 Thus, the TCL server -- a 'machine' type socket interface -- was added
 with the hope was it would output simple "name-value" pair type
 data.  At the time, simple name/value pairs seemed reasonably easier to
-do at the time, though Maybe it should output JSON; 
+do at the time, though Maybe it should output JSON;
 
 See here:
 
@@ -101,11 +101,11 @@
 For example, Cygwin can be painful, Cygwin GUI packages want X11
 to be present, crossing the barrier between MinGW and Cygwin is
 painful, let alone getting the GUI front end to work on MacOS, and
-Linux, yuck yuck yuck. Painful. very very painful.  
+Linux, yuck yuck yuck. Painful. very very painful.
 
 What works easier and is less work is what is already present in every
 platform?  The answer: A web browser.  In other words, OpenOCD could
-serve out embedded web pages via "localhost" to your browser. 
+serve out embedded web pages via "localhost" to your browser.
 
 Long before OpenOCD had a TCL command line, Zylin AS built their ZY1000
 devince with a built-in HTTP server.  Later, they were willing to both
@@ -169,7 +169,7 @@
 
 During 2008, Duane Ellis created some TCL scripts to display peripheral
 register contents. For example, look at the sam7 TCL scripts, and the
-stm32 TCL scripts.  The hope was others would create more. 
+stm32 TCL scripts.  The hope was others would create more.
 
 
 A good example of this is display/view the peripheral registers on
@@ -215,7 +215,7 @@
 use of the feature.  In other words, one could write a Python/TK
 front-end, but it is only useable if you have Python/TK installed.
 Maybe this can be done via Ecllipse, but not all developers use Ecplise.
-Many devlopers use Emacs (possibly with GUD mode) or vim and will not 
+Many devlopers use Emacs (possibly with GUD mode) or vim and will not
 accept such an interface.  The next developer reading this might be
 using Insight (GDB-TK) - and somebody else - DDD..
 

Modified: trunk/doc/manual/style.txt
===================================================================
--- trunk/doc/manual/style.txt	2009-09-21 18:48:22 UTC (rev 2743)
+++ trunk/doc/manual/style.txt	2009-09-21 18:52:45 UTC (rev 2744)
@@ -149,7 +149,7 @@
  * in blocks such as the one in which this example appears in the Style
  * Guide.  See the Doxygen Manual for the full list of commands.
  *
- * @param foo For a function, describe the parameters (e.g. @a foo). 
+ * @param foo For a function, describe the parameters (e.g. @a foo).
  * @returns The value(s) returned, or possible error conditions.
  */
 @endverbatim
@@ -229,7 +229,7 @@
 @endverbatim
 
 For an example, the Doxygen source for this Style Guide can be found in
-@c doc/manual/style.txt, alongside other parts of The Manual.  
+@c doc/manual/style.txt, alongside other parts of The Manual.
 
  */
 /** @page styletexinfo Texinfo Style Guide
@@ -344,7 +344,7 @@
 This page provides some style guidelines for using Perl, a scripting
 language used by several small tools in the tree:
 
--# Ensure all Perl scripts use the proper suffix (@c .pl for scripts, and 
+-# Ensure all Perl scripts use the proper suffix (@c .pl for scripts, and
    @c .pm for modules)
 -# Pass files as script parameters or piped as input:
   - Do NOT code paths to files in the tree, as this breaks out-of-tree builds.

Modified: trunk/doc/manual/target/notarm.txt
===================================================================
--- trunk/doc/manual/target/notarm.txt	2009-09-21 18:48:22 UTC (rev 2743)
+++ trunk/doc/manual/target/notarm.txt	2009-09-21 18:52:45 UTC (rev 2744)
@@ -37,7 +37,7 @@
 @section targetnotarmsupport Target Support
 
 target.h is relatively CPU agnostic and
-the intention is to move in the direction of less 
+the intention is to move in the direction of less
 instruction set specific.
 
 Non-CPU targets are also supported, but there isn't
@@ -56,7 +56,7 @@
 The actual physical layer is a relatively modest part
 of the total OpenOCD system.
 
- 
+
 @section targetnotarmppc PowerPC
 
 there exists open source implementations of powerpc

Modified: trunk/doc/openocd.1
===================================================================
--- trunk/doc/openocd.1	2009-09-21 18:48:22 UTC (rev 2743)
+++ trunk/doc/openocd.1	2009-09-21 18:52:45 UTC (rev 2744)
@@ -8,19 +8,19 @@
 .B OpenOCD
 is an on\-chip debugging, in\-system programming and boundary\-scan
 testing tool for various ARM and MIPS systems.
-.PP 
+.PP
 The debugger uses an IEEE 1149\-1 compliant JTAG TAP bus master to access
 on\-chip debug functionality available on ARM based microcontrollers or
 system-on-chip solutions. For MIPS systems the EJTAG interface is supported.
-.PP 
+.PP
 User interaction is realized through a telnet command line interface,
 a gdb (the GNU debugger) remote protocol server, and a simplified RPC
 connection that can be used to interface with OpenOCD's Jim Tcl engine.
-.PP 
+.PP
 OpenOCD supports various different types of JTAG interfaces/programmers,
 please check the \fIopenocd\fR info page for the complete list.
 .SH "OPTIONS"
-.TP 
+.TP
 .B "\-f, \-\-file <filename>"
 Use configuration file
 .BR <filename> .
@@ -29,43 +29,43 @@
 arguments. If this option is omitted, the config file
 .B openocd.cfg
 in the current working directory will be used.
-.TP 
+.TP
 .B "\-s, \-\-search <dirname>"
 Search for config files and scripts in the directory
 .BR <dirname> .
 If this option is omitted, OpenOCD searches for config files and scripts
 in the current directory.
-.TP 
+.TP
 .B "\-d, \-\-debug <debuglevel>"
 Set debug level. Possible values are:
-.br 
+.br
 .RB "  * " 0 " (errors)"
-.br 
+.br
 .RB "  * " 1 " (warnings)"
-.br 
+.br
 .RB "  * " 2 " (informational messages)"
-.br 
+.br
 .RB "  * " 3 " (debug messages)"
-.br 
+.br
 The default level is
 .BR 2 .
-.TP 
+.TP
 .B "\-l, \-\-log_output <filename>"
 Redirect log output to the file
 .BR <filename> .
 Per default the log output is printed on
 .BR stderr .
-.TP 
+.TP
 .B "\-c, \-\-command <cmd>"
 Run the command
 .BR <cmd> .
-.TP 
+.TP
 .B "\-p, \-\-pipe"
 Use pipes when talking to gdb.
-.TP 
+.TP
 .B "\-h, \-\-help"
 Show a help text and exit.
-.TP 
+.TP
 .B "\-v, \-\-version"
 Show version information and exit.
 .SH "BUGS"
@@ -95,6 +95,6 @@
 .B http://openfacts.berlios.de/index-en.phtml?title=Open_On-Chip_Debugger
 .SH "AUTHORS"
 Please see the file AUTHORS.
-.PP 
+.PP
 This manual page was written by Uwe Hermann <uwe@hermann\-uwe.de>.
 It is licensed under the terms of the GNU GPL (version 2 or later).

Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-09-21 18:48:22 UTC (rev 2743)
+++ trunk/doc/openocd.texi	2009-09-21 18:52:45 UTC (rev 2744)
@@ -252,7 +252,7 @@
 
 There are several things you should keep in mind when choosing a dongle.
 
-@enumerate 
+@enumerate
 @item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
 Does your dongle support it?  You might need a level converter.
 @item @b{Pinout} What pinout does your target board use?
@@ -260,7 +260,7 @@
 wires, or an "octopus" connector, to convert pinouts.
 @item @b{Connection} Does your computer have the USB, printer, or
 Ethernet port needed?
-@item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking'' 
+@item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking''
 @end enumerate
 
 @section Stand alone Systems
@@ -344,7 +344,7 @@
 @item @b{USBprog}
 @* Link: @url{http://www.embedded-projects.net/usbprog} - which uses an Atmel MEGA32 and a UBN9604
 
-@item @b{USB - Presto} 
+@item @b{USB - Presto}
 @* Link: @url{http://tools.asix.net/prg_presto.htm}
 
 @item @b{Versaloon-Link}
@@ -2098,7 +2098,7 @@
 
 @option{srst_gates_jtag} indicates that asserting SRST gates the
 JTAG clock. This means that no communication can happen on JTAG
-while SRST is asserted. 
+while SRST is asserted.
 
 The optional @var{trst_type} and @var{srst_type} parameters allow the
 driver mode of each reset line to be specified.  These values only affect
@@ -4359,7 +4359,7 @@
 
 The target specific "dangerous" optimisation tweaking options may come and go
 as more robust and user friendly ways are found to ensure maximum throughput
-and robustness with a minimum of configuration. 
+and robustness with a minimum of configuration.
 
 Typically the "fast enable" is specified first on the command line:
 
@@ -4919,7 +4919,7 @@
 @deffn Command {armv4_5 reg}
 Display a table of all banked core registers, fetching the current value from every
 core mode if necessary. OpenOCD versions before rev. 60 didn't fetch the current
-register value. 
+register value.
 @end deffn
 
 @subsection ARM7 and ARM9 specific commands
@@ -4934,7 +4934,7 @@
 @deffn Command {arm7_9 dbgrq} (@option{enable}|@option{disable})
 Control use of the EmbeddedIce DBGRQ signal to force entry into debug mode,
 instead of breakpoints.  This should be
-safe for all but ARM7TDMI--S cores (like Philips LPC). 
+safe for all but ARM7TDMI--S cores (like Philips LPC).
 This feature is enabled by default on most ARM9 cores,
 including ARM9TDMI, ARM920T, and ARM926EJ-S.
 @end deffn
@@ -4952,7 +4952,7 @@
 Enable or disable memory writes and reads that don't check completion of
 the operation. This provides a huge speed increase, especially with USB JTAG
 cables (FT2232), but might be unsafe if used with targets running at very low
-speeds, like the 32kHz startup clock of an AT91RM9200. 
+speeds, like the 32kHz startup clock of an AT91RM9200.
 @end deffn
 
 @deffn {Debug Command} {arm7_9 write_core_reg} num mode word
@@ -5843,7 +5843,7 @@
 gdb_memory_map disable
 @end example
 For this to function correctly a valid flash configuration must also be set
-in OpenOCD. For faster performance you should also configure a valid 
+in OpenOCD. For faster performance you should also configure a valid
 working area.
 
 Informing GDB of the memory map of the target will enable GDB to protect any
@@ -5887,10 +5887,10 @@
 information as an argument to each proc.
 
 There are three main types of return values: single value, name value
-pair list and lists. 
+pair list and lists.
 
 Name value pair. The proc 'foo' below returns a name/value pair
-list. 
+list.
 
 @verbatim
 
@@ -5913,7 +5913,7 @@
                 puts "Name: $name, Value: $value"
      }
 @end verbatim
- 
+
 Lists returned must be relatively small. Otherwise a range
 should be passed in to the proc in question.
 
@@ -5949,7 +5949,7 @@
 variables. JimTCL, as implemented in OpenOCD creates $HostOS which
 holds one of the following values:
 
-@itemize @bullet 
+@itemize @bullet
 @item @b{winxx}    Built using Microsoft Visual Studio
 @item @b{linux}    Linux is the underlying operating sytem
 @item @b{darwin}   Darwin (mac-os) is the underlying operating sytem.
@@ -6088,7 +6088,7 @@
 that ``deep sleeps'' at 32kHz between every keystroke. It can be
 painful.
 
-@b{Solution #1 - A special circuit} 
+@b{Solution #1 - A special circuit}
 
 In order to make use of this, your JTAG dongle must support the RTCK
 feature. Not all dongles support this - keep reading!
@@ -6156,7 +6156,7 @@
 @item @b{Win32 Pathnames} Why don't backslashes work in Windows paths?
 
 OpenOCD uses Tcl and a backslash is an escape char. Use @{ and @}
-around Windows filenames. 
+around Windows filenames.
 
 @example
 > echo \a
@@ -6199,7 +6199,7 @@
 
 @item @b{Data Aborts} When debugging with OpenOCD and GDB (plain GDB, Insight, or Eclipse),
 I get lots of "Error: arm7_9_common.c:1771 arm7_9_read_memory():
-memory read caused data abort". 
+memory read caused data abort".
 
 The errors are non-fatal, and are the result of GDB trying to trace stack frames
 beyond the last valid frame. It might be possible to prevent this by setting up
@@ -6220,7 +6220,7 @@
 
 @b{Also note:} If you have a multi-threaded operating system, they
 often do not @b{in the intrest of saving memory} waste these few
-bytes. Painful... 
+bytes. Painful...
 
 
 @item @b{JTAG Reset Config} I get the following message in the OpenOCD console (or log file):
@@ -6342,7 +6342,7 @@
 
 @node Tcl Crash Course
 @chapter Tcl Crash Course
-@cindex Tcl 
+@cindex Tcl
 
 Not everyone knows Tcl - this is not intended to be a replacement for
 learning Tcl, the intent of this chapter is to give you some idea of
@@ -6461,7 +6461,7 @@
 
 Commands are executed like this:
 
-@enumerate 
+@enumerate
 @item Parse the next line into (argc) and (argv[]).
 @item Look up (argv[0]) in a table and call its function.
 @item Repeat until End Of File.
@@ -6609,7 +6609,7 @@
 @enumerate
 @item The SET command creates 2 variables, X and Y.
 @item The double [nested] EXPR command performs math
-@* The EXPR command produces numerical result as a string. 
+@* The EXPR command produces numerical result as a string.
 @* Refer to Rule #1
 @item The format command is executed, producing a single string
 @* Refer to Rule #1.
@@ -6632,7 +6632,7 @@
 #4 DANGER DANGER DANGER
    $_TARGETNAME configure -event foo "puts \"Time: [date]\""
 @end example
-@enumerate 
+@enumerate
 @item The $_TARGETNAME is an OpenOCD variable convention.
 @*@b{$_TARGETNAME} represents the last target created, the value changes
 each time a new target is created. Remember the parsing rules. When
@@ -6699,9 +6699,9 @@
 OpenOCD comes with a target configuration script library. These scripts can be
 used as-is or serve as a starting point.
 
-The target library is published together with the OpenOCD executable and 
+The target library is published together with the OpenOCD executable and
 the path to the target library is in the OpenOCD script search path.
-Similarly there are example scripts for configuring the JTAG interface. 
+Similarly there are example scripts for configuring the JTAG interface.
 
 The command line below uses the example parport configuration script
 that ship with OpenOCD, then configures the str710.cfg target and

[Openocd-svn] r2743 - in trunk/tcl: . board chip/atmel/at91 chip/st/stm32 target test

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-21 20:48:22 +0200 (Mon, 21 Sep 2009)
New Revision: 2743

Modified:
   trunk/tcl/bitsbytes.tcl
   trunk/tcl/board/arm_evaluator7t.cfg
   trunk/tcl/board/at91rm9200-dk.cfg
   trunk/tcl/board/at91sam9g20-ek.cfg
   trunk/tcl/board/atmel_at91sam9260-ek.cfg
   trunk/tcl/board/crossbow_tech_imote2.cfg
   trunk/tcl/board/csb732.cfg
   trunk/tcl/board/digi_connectcore_wi-9c.cfg
   trunk/tcl/board/eir.cfg
   trunk/tcl/board/hitex_str9-comstick.cfg
   trunk/tcl/board/imx27ads.cfg
   trunk/tcl/board/imx27lnst.cfg
   trunk/tcl/board/imx31pdk.cfg
   trunk/tcl/board/mini2440.cfg
   trunk/tcl/board/propox_mmnet1001.cfg
   trunk/tcl/board/pxa255_sst.cfg
   trunk/tcl/board/sheevaplug.cfg
   trunk/tcl/board/str910-eval.cfg
   trunk/tcl/board/telo.cfg
   trunk/tcl/board/unknown_at91sam9260.cfg
   trunk/tcl/board/x300t.cfg
   trunk/tcl/board/zy1000.cfg
   trunk/tcl/chip/atmel/at91/aic.tcl
   trunk/tcl/chip/atmel/at91/rtt.tcl
   trunk/tcl/chip/atmel/at91/usarts.tcl
   trunk/tcl/chip/st/stm32/stm32_rcc.tcl
   trunk/tcl/memory.tcl
   trunk/tcl/mmr_helpers.tcl
   trunk/tcl/readable.tcl
   trunk/tcl/target/aduc702x.cfg
   trunk/tcl/target/ar71xx.cfg
   trunk/tcl/target/at91eb40a.cfg
   trunk/tcl/target/at91r40008.cfg
   trunk/tcl/target/at91rm9200.cfg
   trunk/tcl/target/at91sam3uXX.cfg
   trunk/tcl/target/at91sam7sx.cfg
   trunk/tcl/target/at91sam9260.cfg
   trunk/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
   trunk/tcl/target/c100.cfg
   trunk/tcl/target/c100config.tcl
   trunk/tcl/target/c100helper.tcl
   trunk/tcl/target/c100regs.tcl
   trunk/tcl/target/cs351x.cfg
   trunk/tcl/target/epc9301.cfg
   trunk/tcl/target/feroceon.cfg
   trunk/tcl/target/imx21.cfg
   trunk/tcl/target/imx27.cfg
   trunk/tcl/target/imx31.cfg
   trunk/tcl/target/imx35.cfg
   trunk/tcl/target/is5114.cfg
   trunk/tcl/target/ixp42x.cfg
   trunk/tcl/target/lm3s1968.cfg
   trunk/tcl/target/lm3s3748.cfg
   trunk/tcl/target/lm3s6965.cfg
   trunk/tcl/target/lm3s811.cfg
   trunk/tcl/target/lm3s9b9x.cfg
   trunk/tcl/target/lpc2103.cfg
   trunk/tcl/target/lpc2129.cfg
   trunk/tcl/target/lpc2148.cfg
   trunk/tcl/target/lpc2294.cfg
   trunk/tcl/target/netx500.cfg
   trunk/tcl/target/omap3530.cfg
   trunk/tcl/target/omap5912.cfg
   trunk/tcl/target/pic32mx.cfg
   trunk/tcl/target/pxa255.cfg
   trunk/tcl/target/pxa270.cfg
   trunk/tcl/target/readme.txt
   trunk/tcl/target/sam7se512.cfg
   trunk/tcl/target/sam7x256.cfg
   trunk/tcl/target/samsung_s3c2410.cfg
   trunk/tcl/target/samsung_s3c2440.cfg
   trunk/tcl/target/samsung_s3c2450.cfg
   trunk/tcl/target/samsung_s3c4510.cfg
   trunk/tcl/target/samsung_s3c6410.cfg
   trunk/tcl/target/sharp_lh79532.cfg
   trunk/tcl/target/stm32.cfg
   trunk/tcl/target/str710.cfg
   trunk/tcl/target/str730.cfg
   trunk/tcl/target/str750.cfg
   trunk/tcl/target/str912.cfg
   trunk/tcl/target/telo.cfg
   trunk/tcl/target/test_reset_syntax_error.cfg
   trunk/tcl/target/test_syntax_error.cfg
   trunk/tcl/target/xba_revA3.cfg
   trunk/tcl/test/syntax1.cfg
Log:
Remove annoying end-of-line whitespace from tcl/* files


Modified: trunk/tcl/bitsbytes.tcl
===================================================================
--- trunk/tcl/bitsbytes.tcl	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/bitsbytes.tcl	2009-09-21 18:48:22 UTC (rev 2743)
@@ -22,7 +22,7 @@
 # Create M bytes values
 #    __1M ... to __2048K
 for { set x 1  } { $x < 2048 } { set x [expr $x * 2]} {
-    set vn [format "__%dM" $x] 
+    set vn [format "__%dM" $x]
     global $vn
     set $vn [expr (1024 * 1024 * $x)]
 }

Modified: trunk/tcl/board/arm_evaluator7t.cfg
===================================================================
--- trunk/tcl/board/arm_evaluator7t.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/arm_evaluator7t.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -2,7 +2,7 @@
 
 source [find target/samsung_s3c4510.cfg]
 
-# 
+#
 # FIXME:
 #  Add (A) sdram configuration
 #  Add (B) flash cfi programing configuration

Modified: trunk/tcl/board/at91rm9200-dk.cfg
===================================================================
--- trunk/tcl/board/at91rm9200-dk.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/at91rm9200-dk.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -16,7 +16,7 @@
     # Try to run at 1khz... Yea, that slow!
     # Chip is really running @ 32khz
     jtag_khz 8
-    
+
     mww 0xfffffc64 0xffffffff
     ##  disable all clocks but system clock
     mww 0xfffffc04 0xfffffffe
@@ -37,14 +37,14 @@
     mww 0xfffffc30 0x202
     ## Sleep some - (go read)
     sleep 100
-    
+
     #========================================
     # CPU now runs at 180mhz
     # SYS runs at 60mhz.
     jtag_khz 40000
     #========================================
-    
-    
+
+
     ##  set memc for all memories
     mww 0xffffff60 0x02
     ##  program smc controller
@@ -55,7 +55,7 @@
     mww 0xffffff80 0x02
     ##  touch sdram chip to make it work
     mww 0x20000000 0
-    ##  sdram controller mode register 
+    ##  sdram controller mode register
     mww 0xffffff90 0x04
     mww 0x20000000 0
     mww 0x20000000 0

Modified: trunk/tcl/board/at91sam9g20-ek.cfg
===================================================================
--- trunk/tcl/board/at91sam9g20-ek.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/at91sam9g20-ek.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -62,7 +62,7 @@
 }
 
 proc at91sam9g20_init { } {
-	
+
 	# At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz).  To shift over to a normal clock requires
 	# a number of steps that must be carefully performed.  The process outline below follows the
 	# recommended procedure outlined in the AT91SAM9G20 technical manual.
@@ -94,7 +94,7 @@
 
 	mww 0xfffffc30 0x00000101
 	while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
-	
+
 	# Now change PMC_MCKR register to select PLLA.
 	# Wait for MCKRDY signal from PMC_SR to assert.
 

Modified: trunk/tcl/board/atmel_at91sam9260-ek.cfg
===================================================================
--- trunk/tcl/board/atmel_at91sam9260-ek.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/atmel_at91sam9260-ek.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -26,7 +26,7 @@
         # RSTC_MR : enable user reset, MMU may be enabled... use physical address
         arm926ejs mww_phys 0xfffffd08 0xa5000501
 }
-	
+
 $_TARGETNAME configure -event reset-init {
         mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
 
@@ -48,7 +48,7 @@
 
 	mww 0xfffff870 0xffff0000         # PIO_ASR  : Select peripheral function for D15..D31
         mww 0xfffff804 0xffff0000         # PIO_PDR  : Disable PIO function for D15..D31
-        
+
         mww 0xffffef1c 0x00010002         # EBI_CSA  : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
 
 	mww 0xffffea08 0x85227259         # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)

Modified: trunk/tcl/board/crossbow_tech_imote2.cfg
===================================================================
--- trunk/tcl/board/crossbow_tech_imote2.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/crossbow_tech_imote2.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -4,7 +4,7 @@
 source [find target/pxa270.cfg]
 
 # longer-than-normal reset delay
-jtag_nsrst_delay 800 
+jtag_nsrst_delay 800
 
 reset_config trst_and_srst separate
 

Modified: trunk/tcl/board/csb732.cfg
===================================================================
--- trunk/tcl/board/csb732.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/csb732.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -11,7 +11,7 @@
 
 # Bare-bones initialization of core clocks and SDRAM
 proc csb732_init { } {
-	
+
 	# Disable fast writing only for init
 	memwrite burst disable
 
@@ -29,17 +29,17 @@
 
 	# Set ARM clock to 532 MHz, AHB to 133 MHz
 	mww 0x53F80004 0x1000
-	
+
 	# Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
 	mww 0x53F8001C 0xB2C01
-	
+
 	set ESDMISC 0xB8001010
 	set ESDCFG0 0xB8001004
 	set ESDCTL0 0xB8001000
 
 	# Enable DDR
 	mww $ESDMISC 0x4
-	
+
 	# Timing
 	mww $ESDCFG0 0x007fff3f
 
@@ -51,7 +51,7 @@
 
 	# Enable CS) auto-refresh
 	mww $ESDCTL0 0xA2120080
-	
+
 	# Refresh twice (dummy writes)
 	mww 0x80000000 0
 	mww 0x80000000 0
@@ -59,7 +59,7 @@
 	# Enable CS0 load mode register
 	mww $ESDCTL0 0xB2120080
 
-	# Dummy writes	
+	# Dummy writes
 	mwb 0x80000033 0x01
 	mwb 0x81000000 0x01
 

Modified: trunk/tcl/board/digi_connectcore_wi-9c.cfg
===================================================================
--- trunk/tcl/board/digi_connectcore_wi-9c.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/digi_connectcore_wi-9c.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -4,15 +4,15 @@
 
 reset_config trst_and_srst
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME ns9360
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
   # This config file was defaulting to big endian..
    set  _ENDIAN big
 }
@@ -46,17 +46,17 @@
 	mww 0x90600104 0x33313333
 	mww 0xA0700000 0x00000001  # Enable the memory controller.
 	mww 0xA0700024 0x00000006  # Set the refresh counter 6
-	mww 0xA0700028 0x00000001  # 
+	mww 0xA0700028 0x00000001  #
 	mww 0xA0700030 0x00000001  # Set the precharge period
 	mww 0xA0700034 0x00000004  # Active to precharge command period is 16 clock cycles
 	mww 0xA070003C 0x00000001  # tAPR
 	mww 0xA0700040 0x00000005  # tDAL
 	mww 0xA0700044 0x00000001  # tWR
-	mww 0xA0700048 0x00000006  # tRC 32 clock cycles  
+	mww 0xA0700048 0x00000006  # tRC 32 clock cycles
 	mww 0xA070004C 0x00000006  # tRFC 32 clock cycles
 	mww 0xA0700054 0x00000001  # tRRD
 	mww 0xA0700058 0x00000001  # tMRD
-	mww 0xA0700100 0x00004280  # Dynamic Config 0 (cs4) 
+	mww 0xA0700100 0x00004280  # Dynamic Config 0 (cs4)
 	mww 0xA0700120 0x00004280  # Dynamic Config 1 (cs5)
 	mww 0xA0700140 0x00004280  # Dynamic Config 2 (cs6)
 	mww 0xA0700160 0x00004280  # Dynamic Config 3 (cs7)
@@ -79,11 +79,11 @@
 	mww 0xA0900000 0x00000002
 	mww 0xA0900000 0x00000002
 	#
-	mdw 0xA0900000 
-	mdw 0xA0900000 
-	mdw 0xA0900000 
-	mdw 0xA0900000 
-	mdw 0xA0900000 
+	mdw 0xA0900000
+	mdw 0xA0900000
+	mdw 0xA0900000
+	mdw 0xA0900000
+	mdw 0xA0900000
 	#
 	mww 0xA0700024 0x00000030 # Set the refresh counter to 30
 	mww 0xA0700020 0x00000083 # Issue SDRAM MODE command

Modified: trunk/tcl/board/eir.cfg
===================================================================
--- trunk/tcl/board/eir.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/eir.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -4,7 +4,7 @@
 source [find target/sam7se512.cfg]
 
 $_TARGETNAME configure -event reset-init {
-	# WDT_MR, disable watchdog 
+	# WDT_MR, disable watchdog
 	mww 0xFFFFFD44 0x00008000
 
 	# RSTC_MR, enable user reset
@@ -51,31 +51,31 @@
 
 	# Issue 16 bit SDRAM command: NOP
 	mww 0xffffffb0 0x00000011 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 
 	# Issue 16 bit SDRAM command: Precharge all
 	mww 0xffffffb0 0x00000012 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 
 	# Issue 8 auto-refresh cycles
 	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 	mww 0xffffffb0 0x00000014 # SDRAMC_MR_OFF
-	mww 0x20000000 0x00000000 
+	mww 0x20000000 0x00000000
 
-	# Issue 16 bit SDRAM command: Set mode register  
+	# Issue 16 bit SDRAM command: Set mode register
 	mww 0xffffffb0 0x00000013 # SDRAMC_MR_OFF
 	mww 0x20000014 0xcafedede
 

Modified: trunk/tcl/board/hitex_str9-comstick.cfg
===================================================================
--- trunk/tcl/board/hitex_str9-comstick.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/hitex_str9-comstick.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -14,15 +14,15 @@
 #jtag scan chain
 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME str912
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
    set  _ENDIAN little
 }
 
@@ -56,10 +56,10 @@
 $_TARGETNAME configure -event reset-init {
 	# We can increase speed now that we know the target is halted.
 	#jtag_rclk 3000
-	
+
 	# -- Enable 96K RAM
 	# PFQBC enabled / DTCM & AHB wait-states disabled
-	mww 0x5C002034 0x0191 
+	mww 0x5C002034 0x0191
 
 	str9x flash_config 0 4 2 0 0x80000
 	flash protect 0 0 7 off

Modified: trunk/tcl/board/imx27ads.cfg
===================================================================
--- trunk/tcl/board/imx27ads.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/imx27ads.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -24,52 +24,52 @@
 	# ========================================
 	#  Configure DDR on CSD0 -- initial reset
 	# ========================================
-	mww 0xD8001010 0x00000008 
+	mww 0xD8001010 0x00000008
 
 	# ========================================
-	#  Configure PSRAM on CS5 
+	#  Configure PSRAM on CS5
 	# ========================================
 	mww 0xd8002050 0x0000dcf6
-	mww 0xd8002054 0x444a4541 
-	mww 0xd8002058 0x44443302 
+	mww 0xd8002054 0x444a4541
+	mww 0xd8002058 0x44443302
 
 	#  ========================================
 	#         Configure16 bit NorFlash on CS0
 	#  ========================================
-	mww 0xd8002000 0x0000CC03 
-	mww 0xd8002004 0xa0330D01 
-	mww 0xd8002008 0x00220800 
+	mww 0xd8002000 0x0000CC03
+	mww 0xd8002004 0xa0330D01
+	mww 0xd8002008 0x00220800
 
 	# ========================================
-	#  Configure CPLD on CS4 
+	#  Configure CPLD on CS4
 	# ========================================
-	mww 0xd8002040 0x0000DCF6 
-	mww 0xd8002044 0x444A4541 
-	mww 0xd8002048 0x44443302 
+	mww 0xd8002040 0x0000DCF6
+	mww 0xd8002044 0x444A4541
+	mww 0xd8002048 0x44443302
 
 	# ========================================
-	#  Configure DDR on CSD0 -- wait 5000 cycle 
+	#  Configure DDR on CSD0 -- wait 5000 cycle
 	# ========================================
-	mww 0x10027828 0x55555555 
-	mww 0x10027830 0x55555555 
-	mww 0x10027834 0x55555555 
-	mww 0x10027838 0x00005005 
-	mww 0x1002783C 0x15555555 
+	mww 0x10027828 0x55555555
+	mww 0x10027830 0x55555555
+	mww 0x10027834 0x55555555
+	mww 0x10027838 0x00005005
+	mww 0x1002783C 0x15555555
 
-	mww 0xD8001010 0x00000004 
+	mww 0xD8001010 0x00000004
 
-	mww 0xD8001004 0x00795729 
+	mww 0xD8001004 0x00795729
 
-	mww 0xD8001000 0x92200000 
+	mww 0xD8001000 0x92200000
 	mww 0xA0000F00 0x0
 
-	mww 0xD8001000 0xA2200000 
+	mww 0xD8001000 0xA2200000
 	mww 0xA0000F00 0x0
 	mww 0xA0000F00 0x0
 
-	mww 0xD8001000 0xB2200000 
+	mww 0xD8001000 0xB2200000
 	mwb 0xA0000033 0xFF
 	mwb 0xA1000000 0xAA
 
-	mww 0xD8001000 0x82228085 
+	mww 0xD8001000 0x82228085
 }

Modified: trunk/tcl/board/imx27lnst.cfg
===================================================================
--- trunk/tcl/board/imx27lnst.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/imx27lnst.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -22,38 +22,38 @@
 	# ========================================
 	#  Configure DDR on CSD0 -- initial reset
 	# ========================================
-	mww 0xD8001010 0x00000008 
+	mww 0xD8001010 0x00000008
 
 	sleep 100
 
 	# ========================================
-	#  Configure DDR on CSD0 -- wait 5000 cycle 
+	#  Configure DDR on CSD0 -- wait 5000 cycle
 	# ========================================
-	mww 0x10027828 0x55555555 
-	mww 0x10027830 0x55555555 
-	mww 0x10027834 0x55555555 
-	mww 0x10027838 0x00005005 
-	mww 0x1002783C 0x15555555 
+	mww 0x10027828 0x55555555
+	mww 0x10027830 0x55555555
+	mww 0x10027834 0x55555555
+	mww 0x10027838 0x00005005
+	mww 0x1002783C 0x15555555
 
-	mww 0xD8001010 0x00000004 
+	mww 0xD8001010 0x00000004
 
-	mww 0xD8001004 0x00795729 
+	mww 0xD8001004 0x00795729
 
 	#mww 0xD8001000 0x92200000
 	mww 0xD8001000 0x91120000
 	mww 0xA0000F00 0x0
 
-	#mww 0xD8001000 0xA2200000 
+	#mww 0xD8001000 0xA2200000
 	mww 0xD8001000 0xA1120000
 	mww 0xA0000F00 0x0
 	mww 0xA0000F00 0x0
 
-	#mww 0xD8001000 0xB2200000 
+	#mww 0xD8001000 0xB2200000
 	mww 0xD8001000 0xB1120000
 	mwb 0xA0000033 0xFF
 	mwb 0xA1000000 0xAA
 
-	#mww 0xD8001000 0x82228085 
+	#mww 0xD8001000 0x82228085
 	mww 0xD8001000 0x81128080
 
 }

Modified: trunk/tcl/board/imx31pdk.cfg
===================================================================
--- trunk/tcl/board/imx31pdk.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/imx31pdk.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -25,7 +25,7 @@
 	mww 0x53F80010 0x00271C1B
 
 	# ========================================
-	# Configure CPLD on CS5 
+	# Configure CPLD on CS5
 	# ========================================
 	mww 0xb8002050 0x0000DCF6
 	mww 0xb8002054 0x444A4541

Modified: trunk/tcl/board/mini2440.cfg
===================================================================
--- trunk/tcl/board/mini2440.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/mini2440.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -1,7 +1,7 @@
 #-------------------------------------------------------------------------
 # Mini2440 Samsung s3c2440A Processor with 64MB DRAM, 64MB NAND, 2 MB N0R
 # NOTE: Configured for NAND boot (switch S2 in NANDBOOT)
-# 64 MB NAND (Samsung K9D1208V0M) 
+# 64 MB NAND (Samsung K9D1208V0M)
 # B Findlay  08/09
 #
 #   ----------- Important notes to help you on your way ----------
@@ -9,9 +9,9 @@
 #     NOR/NAND Boot Switch - I have not read the vivi source, but from
 #     what I could tell from reading the registers it appears that vivi
 #     loads itself into DRAM and then flips NFCONT (0x4E000004) bits
-#     Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND 
-#     FLASH at the bottom 64MB of memory. This essentially takes the 
-#     NOR Flash out of the circuit so you can't trash it. 
+#     Mode (bit 0 = 1), and REG_nCE (bit 1 = 0) which maps the NAND
+#     FLASH at the bottom 64MB of memory. This essentially takes the
+#     NOR Flash out of the circuit so you can't trash it.
 #
 #     I adapted the samsung_s3c2440.cfg file which is why I did not
 #     include "source [find target/samsung_s3c2440.cfg]".  I believe
@@ -22,9 +22,9 @@
 #     JTAG ADAPTER SPECIFIC
 #     IMPORTANT! Any JTAG device that uses ADAPTIVE CLOCKING will likely
 #     FAIL as the pin RTCK on the mini2440 10 pin JTAG Conn doesn't exist.
-#     This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is 
+#     This is Pin 11 (RTCK) on 20 pin JTAG connector. Therefore it is
 #     necessary to FORCE setting the clock. Normally this should be configured
-#     in the openocd.cfg file, but was placed here as it can be a tough 
+#     in the openocd.cfg file, but was placed here as it can be a tough
 #     problem to figure out.  THIS MAY NOT FIX YOUR PROBLEM.. I modified
 #     the openOCD driver jlink.c and posted it here. It may eventually end
 #     up changed in openOCD, but its a hack in the driver and really should
@@ -42,21 +42,21 @@
 #     But it should get you way ahead of the game from where I started.
 #     If you find problems (and fixes) please post them to
 #     ope...@li... and join the developers and
-#     check in fixes to this and anything else you find.  I do not 
-#     provide support, but if you ask really nice and I see anything 
+#     check in fixes to this and anything else you find.  I do not
+#     provide support, but if you ask really nice and I see anything
 #     obvious I will tell you.. mostly just dig, fix, and submit to openocd.
-#     
+#
 #     best!   brf...@ya...   Nashua, NH USA
 #
 #     Recommended resources:
 #       - first two are the best Mini2440 resources anywhere
 #       - maintained by buserror... thanks guy!
 #
-#       http://bliterness.blogspot.com/    
+#       http://bliterness.blogspot.com/
 #       http://code.google.com/p/mini2440/
 #
 #       others....
-# 
+#
 #       http://forum.sparkfun.com/viewforum.php?f=18
 #       http://labs.kernelconcepts.de/Publications/Micro24401/
 #       http://www.friendlyarm.net/home
@@ -75,19 +75,19 @@
 # Target configuration for the Samsung 2440 system on chip
 # Tested on a S3C2440 Evaluation board by keesj
 # Processor : ARM920Tid(wb) rev 0 (v4l)
-# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d 
+# Info: JTAG tap: s3c2440.cpu tap/device found: 0x0032409d
 #  (Manufacturer: 0x04e, Part: 0x0324, Version: 0x0)
 #-------------------------------------------------------------------------
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME s3c2440
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
   # this defaults to a bigendian
    set  _ENDIAN little
 }
@@ -108,16 +108,16 @@
 
 #reset configuration
 jtag_nsrst_delay 100
-jtag_ntrst_delay 100 
+jtag_ntrst_delay 100
 reset_config trst_and_srst
 
 #-------------------------------------------------------------------------
 # JTAG ADAPTER SPECIFIC
-# IMPORTANT! See README at top of this file. 
+# IMPORTANT! See README at top of this file.
 #-------------------------------------------------------------------------
 
-    jtag_khz 12000  
-    jtag interface   
+    jtag_khz 12000
+    jtag interface
 
 #-------------------------------------------------------------------------
 # GDB Setup
@@ -125,23 +125,23 @@
 
     gdb_port 3333
     gdb_detach resume
-    gdb_breakpoint_override hard 
+    gdb_breakpoint_override hard
     gdb_memory_map enable
-    gdb_flash_program enable 
+    gdb_flash_program enable
 
 #------------------------------------------------
 # ARM SPECIFIC
 #------------------------------------------------
 
-    targets 
+    targets
   #  arm7_9 dcc_downloads enable
   #  arm7_9 fast_memory_access enable
-  
- 
-    nand device s3c2440 0 
 
+
+    nand device s3c2440 0
+
     jtag_nsrst_delay 100
-    jtag_ntrst_delay 100 
+    jtag_ntrst_delay 100
     reset_config trst_and_srst
     init
 
@@ -180,62 +180,62 @@
     # OM2 OM3 pulled to ground so main clock and
     # usb clock are off 12mHz xtal
     #-----------------------------------------------
-   
+
     arm920t mww_phys 0x4C000014 0x00000005 #  Clock Divider control Reg
     arm920t mww_phys 0x4C000000 0xFFFFFFFF #  LOCKTIME count register
     arm920t mww_phys 0x4C000008 0x00038022 #  UPPLCON  USB clock config Reg
     arm920t mww_phys 0x4C000004 0x0007F021 #  MPPLCON  Proc clock config Reg
-	
+
     #-----------------------------------------------
     # Configure Memory controller
     # BWSCON configures all banks, NAND, NOR, DRAM
     # DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7
     #-----------------------------------------------
-	
+
     arm920t mww_phys 0x48000000 0x22111112 #  BWSCON - Bank and Bus Width
     arm920t mww_phys 0x48000010 0x00001112 #  BANKCON4 - ?
-    arm920t mww_phys 0x4800001c 0x00018009 #  BANKCON6 - DRAM	
-    arm920t mww_phys 0x48000020 0x00018009 #  BANKCON7 - DRAM	
-    arm920t mww_phys 0x48000024 0x008E04EB #  REFRESH  - DRAM		
-    arm920t mww_phys 0x48000028 0x000000B2 #  BANKSIZE - DRAM		
-    arm920t mww_phys 0x4800002C 0x00000030 #  MRSRB6 - DRAM		
-    arm920t mww_phys 0x48000030 0x00000030 #  MRSRB7 - DRAM					
-		
+    arm920t mww_phys 0x4800001c 0x00018009 #  BANKCON6 - DRAM
+    arm920t mww_phys 0x48000020 0x00018009 #  BANKCON7 - DRAM
+    arm920t mww_phys 0x48000024 0x008E04EB #  REFRESH  - DRAM
+    arm920t mww_phys 0x48000028 0x000000B2 #  BANKSIZE - DRAM
+    arm920t mww_phys 0x4800002C 0x00000030 #  MRSRB6 - DRAM
+    arm920t mww_phys 0x48000030 0x00000030 #  MRSRB7 - DRAM
+
     #-----------------------------------------------
     # Now port configuration for enables for memory
     # and other stuff.
     #-----------------------------------------------
-    
+
     arm920t mww_phys 0x56000000	0x007FFFFF #  GPACON
-    
-    arm920t mww_phys 0x56000010	0x00295559 #  GPBCON   
+
+    arm920t mww_phys 0x56000010	0x00295559 #  GPBCON
     arm920t mww_phys 0x56000018	0x000003FF #  GPBUP (PULLUP ENABLE)
-    arm920t mww_phys 0x56000014	0x000007C2 #  GPBDAT   	    
-    
-    arm920t mww_phys 0x56000020	0xAAAAA6AA #  GPCCON   	
+    arm920t mww_phys 0x56000014	0x000007C2 #  GPBDAT
+
+    arm920t mww_phys 0x56000020	0xAAAAA6AA #  GPCCON
     arm920t mww_phys 0x56000028	0x0000FFFF #  GPCUP
-    arm920t mww_phys 0x56000024	0x00000020 #  GPCDAT   	 	   	
-    
-    arm920t mww_phys 0x56000030	0xAAAAAAAA #  GPDCON   	
-    arm920t mww_phys 0x56000038	0x0000FFFF #  GPDUP    
-    
-    arm920t mww_phys 0x56000040	0xAAAAAAAA #  GPECON   	
-    arm920t mww_phys 0x56000048	0x0000FFFF #  GPEUP    
-    
-    arm920t mww_phys 0x56000050	0x00001555 #  GPFCON   	
-    arm920t mww_phys 0x56000058	0x0000007F #  GPFUP    
-    arm920t mww_phys 0x56000054	0x00000000 #  GPFDAT       
-     
-    arm920t mww_phys 0x56000060	0x00150114 #  GPGCON   	
-    arm920t mww_phys 0x56000068	0x0000007F #  GPGUP        
- 
-    arm920t mww_phys 0x56000070	0x0015AAAA #  GPHCON  
-    arm920t mww_phys 0x56000078	0x000003FF #  GPGUP       
+    arm920t mww_phys 0x56000024	0x00000020 #  GPCDAT
 
-}	
+    arm920t mww_phys 0x56000030	0xAAAAAAAA #  GPDCON
+    arm920t mww_phys 0x56000038	0x0000FFFF #  GPDUP
 
+    arm920t mww_phys 0x56000040	0xAAAAAAAA #  GPECON
+    arm920t mww_phys 0x56000048	0x0000FFFF #  GPEUP
 
+    arm920t mww_phys 0x56000050	0x00001555 #  GPFCON
+    arm920t mww_phys 0x56000058	0x0000007F #  GPFUP
+    arm920t mww_phys 0x56000054	0x00000000 #  GPFDAT
 
+    arm920t mww_phys 0x56000060	0x00150114 #  GPGCON
+    arm920t mww_phys 0x56000068	0x0000007F #  GPGUP
+
+    arm920t mww_phys 0x56000070	0x0015AAAA #  GPHCON
+    arm920t mww_phys 0x56000078	0x000003FF #  GPGUP
+
+}
+
+
+
 proc flash_config { } {
 
     #-----------------------------------------
@@ -243,7 +243,7 @@
     #-----------------------------------------
 
     halt
-    
+
     #flash configuration (K9D1208V0M: 512Mbit, x8, 3.3V, Mode: Normal, 1st gen)
     nand probe 0
     nand list
@@ -275,8 +275,8 @@
         echo "---- http://repo.or.cz/w/u-boot-openmoko/mini2440.git  ---"
         echo "---- Also this:                                        ---"
         echo "---- http://code.google.com/p/mini2440/wiki/MiniBringup --"
-        echo "----------------------------------------------------------"      
-  
+        echo "----------------------------------------------------------"
+
 	init_2440
 	echo "Loading /tftpboot/u-boot-nand512.bin"
 	load_image /tftpboot/u-boot-nand512.bin 0x33f80000 bin

Modified: trunk/tcl/board/propox_mmnet1001.cfg
===================================================================
--- trunk/tcl/board/propox_mmnet1001.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/propox_mmnet1001.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -9,7 +9,7 @@
 
 
 proc at91sam_init { } {
-	
+
 	# at reset chip runs at 32 kHz => 1/8 * 32 kHz = 4 kHz
 	jtag_rclk 4
 

Modified: trunk/tcl/board/pxa255_sst.cfg
===================================================================
--- trunk/tcl/board/pxa255_sst.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/pxa255_sst.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -1,7 +1,7 @@
 # A PXA255 test board with SST 39LF400A flash
 #
 # At reset the memory map is as follows. Note that
-# the memory map changes later on as the application 
+# the memory map changes later on as the application
 # starts...
 #
 # RAM at 0x4000000

Modified: trunk/tcl/board/sheevaplug.cfg
===================================================================
--- trunk/tcl/board/sheevaplug.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/sheevaplug.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -1,4 +1,4 @@
-# Marvell SheevaPlug 
+# Marvell SheevaPlug
 
 source [find interface/sheevaplug.cfg]
 source [find target/feroceon.cfg]

Modified: trunk/tcl/board/str910-eval.cfg
===================================================================
--- trunk/tcl/board/str910-eval.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/str910-eval.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -1,17 +1,17 @@
 # str910-eval eval board
-# 
-# Need reset scripts 
+#
+# Need reset scripts
 reset_config trst_and_srst
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME str912
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
    set  _ENDIAN little
 }
 
@@ -44,10 +44,10 @@
 $_TARGETNAME configure -event reset-init {
 	# We can increase speed now that we know the target is halted.
 	#jtag_rclk 3000
-	
+
 	# -- Enable 96K RAM
 	# PFQBC enabled / DTCM & AHB wait-states disabled
-	mww 0x5C002034 0x0191 
+	mww 0x5C002034 0x0191
 
 	str9x flash_config 0 4 2 0 0x80000
 	flash protect 0 0 7 off

Modified: trunk/tcl/board/telo.cfg
===================================================================
--- trunk/tcl/board/telo.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/telo.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -8,7 +8,7 @@
 
 
 # Telo board & C100 support trst and srst
-# however openocd does not support 
+# however openocd does not support
 # 1. setting srst reset pulse width
 # 2. setting delay between srst pulse and JTAG access
 # This really makes the srst useless for now.
@@ -23,7 +23,7 @@
 	# setup GPIO used as control signals for C100
 	setupGPIO
 	# This will allow acces to lower 8MB or NOR
-	lowGPIO5 
+	lowGPIO5
 	# setup NOR size,timing,etc.
 	setupNOR
 	# setup internals + PLL + DDR2
@@ -38,10 +38,10 @@
 	# Force target into ARM state.
 #	soft_reset_halt # not implemented on ARM11
 	puts "Detected SRSRT asserted on C100.CPU"
-	
+
 }
 
-proc power_restore {} { puts "Sensed power restore. No action." } 
+proc power_restore {} { puts "Sensed power restore. No action." }
 proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
 
 

Modified: trunk/tcl/board/unknown_at91sam9260.cfg
===================================================================
--- trunk/tcl/board/unknown_at91sam9260.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/unknown_at91sam9260.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -1,4 +1,4 @@
-# Thanks to Pieter Conradie for this script! 
+# Thanks to Pieter Conradie for this script!
 #
 # Unknown vendor board contains:
 #
@@ -15,13 +15,13 @@
 $_TARGETNAME configure -event reset-start {
         # At reset CPU runs at 22 to 42 kHz.
         # JTAG Frequency must be 6 times slower.
-        jtag_rclk 3                        
+        jtag_rclk 3
         halt
 	# RSTC_MR : enable user reset, MMU may be enabled... use physical address
         arm926ejs mww_phys 0xfffffd08 0xa5000501
 }
-	
 
+
 $_TARGETNAME configure -event reset-init {
         mww 0xfffffd44 0x00008000         # WDT_MR : disable watchdog
 
@@ -37,7 +37,7 @@
         sleep 10                          # wait 10 ms
 
 	# Increase JTAG Speed to 6 MHz if RCLK is not supported
-        jtag_rclk 6000                    
+        jtag_rclk 6000
 
 	arm7_9 dcc_downloads enable       # Enable faster DCC downloads
 
@@ -51,7 +51,7 @@
 	mww 0xfffff870 0xffff0000         # PIO_ASR  : Select peripheral function for D15..D31
         mww 0xfffff804 0xffff0000         # PIO_PDR  : Disable PIO function for D15..D31
         mww 0xfffff860 0xffff0000         # PIO_PUDR : Disable D15..D31 pull-ups
-        
+
         mww 0xffffef1c 0x00010102         # EBI_CSA  : Assign EBI Chip Select 1 to SDRAM
                                           #            VDDIOMSEL set for +3V3 memory
                                           #            Disable D0..D15 pull-ups

Modified: trunk/tcl/board/x300t.cfg
===================================================================
--- trunk/tcl/board/x300t.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/x300t.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -18,13 +18,13 @@
 	mww 0xa0030000 0xE34111BA
 	mww 0xa003fffc 0xa4444
 	mww 0xa003fffc 0
-	
+
 	# remap boot vector in CPU local RAM
 	mww 0xa006f000 0x60000
-	
+
 	# map flash to CPU address space REG_BASE_cpu_block+CPU_remap4
 	mww 0x0006f010 0x48000000
-	
+
 	# map flash addr to REG_BASE_cpu_block + LR_XENV_LOCATION (normally done by XOS)
 	mww 0x00061ff0 0x48000000
 }

Modified: trunk/tcl/board/zy1000.cfg
===================================================================
--- trunk/tcl/board/zy1000.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/board/zy1000.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -10,19 +10,19 @@
 reset_config srst_only srst_pulls_trst
 
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME zy1000
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
    set  _ENDIAN little
 }
 
- 
+
 #jtag scan chain
 if { [info exists CPUTAPID ] } {
    set _CPUTAPID $CPUTAPID
@@ -39,7 +39,7 @@
 arm7_9 dcc_downloads enable
 
 flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
-$_TARGETNAME configure -event reset-init { 
+$_TARGETNAME configure -event reset-init {
 	# Set up chip selects & timings
 	mww 0xFFE00000 0x0100273D
 	mww 0xFFE00004 0x08002125
@@ -51,12 +51,12 @@
 	mww 0xFFE0001c 0x70000000
 	mww 0xFFE00020 0x00000001
 	mww 0xFFE00024 0x00000000
-	
-	# remap  
-	mww 0xFFFFF124 0xFFFFFFFF  
+
+	# remap
+	mww 0xFFFFF124 0xFFFFFFFF
 	mww 0xffff0010 0x100
 	mww 0xffff0034 0x100
-	
+
 	#disable 16x5x UART interrupts
 	mww 0x08020004 0
 }
@@ -75,7 +75,7 @@
 # There is no return value from this procedure. If it is
 # successful it does not throw an exception
 #
-# Progress messages are output via puts 
+# Progress messages are output via puts
 proc production {firmwarefile serialnumber} {
 	if {[string length $serialnumber]!=12} {
 		puts "Invalid serial number"
@@ -92,11 +92,11 @@
 	verify_image $firmwarefile 0x1000000 bin
 
 	# Big endian... weee!!!!
-	puts "Setting MAC number to $serialnumber"	
+	puts "Setting MAC number to $serialnumber"
 	flash fillw [expr 0x1030000-0x8] "0x[string range $serialnumber 2 3][string range $serialnumber 0 1]0000" 1
 	flash fillw [expr 0x1030000-0x4] "0x[string range $serialnumber 10 11][string range $serialnumber 8 9][string range $serialnumber 6 7][string range $serialnumber 4 5]" 1
 	puts "Production successful"
-} 
+}
 
 
 proc production_test {} {

Modified: trunk/tcl/chip/atmel/at91/aic.tcl
===================================================================
--- trunk/tcl/chip/atmel/at91/aic.tcl	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/chip/atmel/at91/aic.tcl	2009-09-21 18:48:22 UTC (rev 2743)
@@ -85,12 +85,12 @@
 	incr x
 	puts [format "%2d: %5s 0x%08x" $x $AT91C_ID($x) $aaa($x)]
 	incr x
-    } 
+    }
 
     foreach REG {
-	AIC_IVR   AIC_FVR  AIC_ISR 
+	AIC_IVR   AIC_FVR  AIC_ISR
 	AIC_IPR  AIC_IMR  AIC_CISR  AIC_IECR AIC_IDCR
-	AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU  AIC_DCR     
+	AIC_ICCR AIC_ISCR AIC_EOICR AIC_SPU  AIC_DCR
 	AIC_FFER AIC_FFDR AIC_FFSR } {
 	if [catch { show_mmr32_reg $REG } msg ] {
 	    error $msg

Modified: trunk/tcl/chip/atmel/at91/rtt.tcl
===================================================================
--- trunk/tcl/chip/atmel/at91/rtt.tcl	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/chip/atmel/at91/rtt.tcl	2009-09-21 18:48:22 UTC (rev 2743)
@@ -13,7 +13,7 @@
     global BIT16 BIT17
     if { $rtpres == 0 } {
 	set rtpres 65536;
-    } 
+    }
     global AT91C_SLOWOSC_FREQ
     # Nasty hack, make this a float by tacking a .0 on the end
     # otherwise, jim makes the value an integer
@@ -47,7 +47,7 @@
 }
 
 proc show_RTTC { } {
-    
+
     show_mmr32_reg RTTC_RTMR
     show_mmr32_reg RTTC_RTAR
     show_mmr32_reg RTTC_RTVR

Modified: trunk/tcl/chip/atmel/at91/usarts.tcl
===================================================================
--- trunk/tcl/chip/atmel/at91/usarts.tcl	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/chip/atmel/at91/usarts.tcl	2009-09-21 18:48:22 UTC (rev 2743)
@@ -48,7 +48,7 @@
 
     set x [show_normalize_bitfield $VAL 11 9]
     set s "unknown"
-    switch -exact $x { 
+    switch -exact $x {
 	0 { set s "Even" }
 	1 { set s "Odd" }
 	2 { set s "Force=0" }
@@ -62,7 +62,7 @@
 	}
     }
     puts [format "\tParity: %s " $s]
-    
+
     set x [expr 5 + [show_normalize_bitfield $VAL 7 6]]
     puts [format "\tDatabits: %d" $x]
 
@@ -80,7 +80,7 @@
     set n AT91C_BASE_[set WHO]
     set str ""
 
-    # Only if it exists on the chip 
+    # Only if it exists on the chip
     if [ info exists $n ] {
 	# Hence: $n - is like AT91C_BASE_USx
 	# For every sub-register
@@ -114,12 +114,12 @@
 
 
 # For every sub-register
-foreach REG {DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR 
+foreach REG {DBGU_CR DBGU_MR DBGU_IER DBGU_IDR DBGU_IMR
     DBGU_CSR DBGU_RHR DBGU_THR DBGU_BRGR DBGU_CIDR DBGU_EXID DBGU_FNTR} {
 
     # Create a command for this specific register.
     proc show_$REG { } "show_mmr32_reg $REG"
-    
+
     # Add this command to the Device(as a whole) command
     set str "$str\nshow_$REG"
 }

Modified: trunk/tcl/chip/st/stm32/stm32_rcc.tcl
===================================================================
--- trunk/tcl/chip/st/stm32/stm32_rcc.tcl	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/chip/st/stm32/stm32_rcc.tcl	2009-09-21 18:48:22 UTC (rev 2743)
@@ -16,7 +16,7 @@
 	error $msg
     }
 
-    show_mmr_bitfield  0  0 $val HSI      { OFF ON } 
+    show_mmr_bitfield  0  0 $val HSI      { OFF ON }
     show_mmr_bitfield  1  1 $val HSIRDY   { NOTRDY RDY  }
     show_mmr_bitfield  7  3 $val HSITRIM  { _NUMBER_ }
     show_mmr_bitfield 15  8 $val HSICAL   { _NUMBER_ }
@@ -26,8 +26,8 @@
     show_mmr_bitfield 19 19 $val CSSON    { OFF ON }
     show_mmr_bitfield 24 24 $val PLLON    { OFF ON }
     show_mmr_bitfield 25 25 $val PLLRDY   { NOTRDY RDY }
-}    
-	
+}
+
 proc show_RCC_CFGR { } {
     if [ catch { set val [show_mmr32_reg RCC_CFGR] } msg ] {
 	error $msg
@@ -47,12 +47,12 @@
     show_mmr_bitfield 26 24 $val  MCO    { none none none none SysClk HSI HSE PLL_div2 }
 }
 
-    
+
 proc show_RCC_CIR { } {
     if [ catch { set val [show_mmr32_reg RCC_CIR] } msg ] {
 	error $msg
     }
- 
+
 }
 
 proc show_RCC_APB2RSTR { } {
@@ -106,7 +106,7 @@
     set bits(13) xxx
     set bits(12) xxx
     set bits(11) wwdg
-    set bits(10) xxx 
+    set bits(10) xxx
     set bits(9) xxx
     set bits(8) xxx
     set bits(7) xxx
@@ -118,7 +118,7 @@
     set bits(1) tim3
     set bits(0) tim2
     show_mmr32_bits bits $val
-    
+
 }
 
 proc show_RCC_AHBENR   { } {
@@ -141,7 +141,7 @@
     set bits(18) xxx
     set bits(17) xxx
     set bits(16) xxx
-    set bits(15) xxx  
+    set bits(15) xxx
     set bits(14) xxx
     set bits(13) xxx
     set bits(12) xxx
@@ -180,7 +180,7 @@
     set bits(18) xxx
     set bits(17) xxx
     set bits(16) xxx
-    set bits(15) adc3  
+    set bits(15) adc3
     set bits(14) usart1
     set bits(13) tim8
     set bits(12) spi1

Modified: trunk/tcl/memory.tcl
===================================================================
--- trunk/tcl/memory.tcl	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/memory.tcl	2009-09-21 18:48:22 UTC (rev 2743)
@@ -1,4 +1,4 @@
-# MEMORY 
+# MEMORY
 #
 # All Memory regions have two components.
 #    (1) A count of regions, in the form N_NAME
@@ -62,7 +62,7 @@
 }
 
 proc address_info { ADDRESS } {
-    
+
     foreach WHERE { FLASH RAM MMREGS XMEM UNKNOWN } {
 	if { info exists $WHERE } {
 	    set lmt [set N_[set WHERE]]
@@ -85,7 +85,7 @@
     } else {
 	error "memread32: $msg"
     }
-}    
+}
 
 proc memread16 {ADDR} {
     set foo(0) 0
@@ -94,7 +94,7 @@
     } else {
 	error "memread16: $msg"
     }
-}    
+}
 
 proc memread8 {ADDR} {
     set foo(0) 0
@@ -103,7 +103,7 @@
     } else {
 	error "memread8: $msg"
     }
-}    
+}
 
 proc memwrite32 {ADDR DATA} {
     set foo(0) $DATA
@@ -112,7 +112,7 @@
     } else {
 	error "memwrite32: $msg"
     }
-}    
+}
 
 proc memwrite16 {ADDR DATA} {
     set foo(0) $DATA
@@ -121,7 +121,7 @@
     } else {
 	error "memwrite16: $msg"
     }
-}    
+}
 
 proc memwrite8 {ADDR DATA} {
     set foo(0) $DATA
@@ -130,4 +130,4 @@
     } else {
 	error "memwrite8: $msg"
     }
-}    
+}

Modified: trunk/tcl/mmr_helpers.tcl
===================================================================
--- trunk/tcl/mmr_helpers.tcl	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/mmr_helpers.tcl	2009-09-21 18:48:22 UTC (rev 2743)
@@ -7,7 +7,7 @@
 
 # Give: REGISTER name - must be a global variable.
 proc show_mmr32_reg { NAME } {
-    
+
     global $NAME
     # we want $($NAME)
     set a [set [set NAME]]
@@ -41,7 +41,7 @@
 	set l [string length $N]
 	if { $l > $w } { set w $l }
     }
-    
+
     for { set x 24 } { $x >= 0 } { incr x -8 } {
 	puts -nonewline "  "
 	for { set y 7 } { $y >= 0 } { incr y -1 } {

Modified: trunk/tcl/readable.tcl
===================================================================
--- trunk/tcl/readable.tcl	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/readable.tcl	2009-09-21 18:48:22 UTC (rev 2743)
@@ -22,4 +22,3 @@
 }
 
 proc isreadable32 { ADDRESS } {
-    
\ No newline at end of file

Modified: trunk/tcl/target/aduc702x.cfg
===================================================================
--- trunk/tcl/target/aduc702x.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/target/aduc702x.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -2,22 +2,22 @@
 ##
 
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME aduc702x
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
   # This config file was defaulting to big endian..
    set  _ENDIAN little
 }
 
-if { [info exists CPUTAPID] } {	
-   set  _CPUTAPID $CPUTAPID    
-} else {	 
+if { [info exists CPUTAPID] } {
+   set  _CPUTAPID $CPUTAPID
+} else {
    set  _CPUTAPID 0x3f0f0f0f
 }
 
@@ -26,7 +26,7 @@
 jtag_ntrst_delay 200
 
 # This is for the case that TRST/SRST is not wired on your JTAG adaptor.
-# Don't really need them anyways.  
+# Don't really need them anyways.
 reset_config none
 
 ## JTAG scan chain

Modified: trunk/tcl/target/ar71xx.cfg
===================================================================
--- trunk/tcl/target/ar71xx.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/target/ar71xx.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -29,11 +29,11 @@
 	mww 0xb8050000 0x800f00e8       # clr pwrdwn & bypass
 	mww 0xb8050008 1		# set clock_switch bit
 	sleep 1                         # wait for lock
-	
+
 	# Setup DDR config and flash mapping
 	mww 0xb8000000 0xefbc8cd0       # DDR cfg cdl val (rst: 0x5bfc8d0)
 	mww 0xb8000004 0x8e7156a2       # DDR cfg2 cdl val (rst: 0x80d106a8)
-	
+
 	mww 0xb8000010 8		# force precharge all banks
 	mww 0xb8000010 1 		# force EMRS update cycle
 	mww 0xb800000c 0                # clr ext. mode register
@@ -47,7 +47,7 @@
 	mww 0xb8000020 0
 	mww 0xb8000024 0
 	mww 0xb8000028 0
-}	
+}
 
 # setup working area somewhere in RAM
 $TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000

Modified: trunk/tcl/target/at91eb40a.cfg
===================================================================
--- trunk/tcl/target/at91eb40a.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/target/at91eb40a.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -1,14 +1,14 @@
 #Script for AT91EB40a
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME at91eb40a
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
    set  _ENDIAN little
 }
 
@@ -28,7 +28,7 @@
 #SRST reset, which means that the CPU will run a number
 #of cycles before it can be halted(as much as milliseconds).
 reset_config srst_only srst_pulls_trst
- 
+
 #jtag scan chain
 #format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
@@ -53,9 +53,9 @@
 	# Reset script for AT91EB40a
 	reg cpsr 0x000000D3
 	mww 0xFFE00020 0x1
-	mww 0xFFE00024 0x00000000  
-	mww 0xFFE00000 0x01002539 
-	mww 0xFFFFF124 0xFFFFFFFF  
+	mww 0xFFE00024 0x00000000
+	mww 0xFFE00000 0x01002539
+	mww 0xFFFFF124 0xFFFFFFFF
 	mww 0xffff0010 0x100
 	mww 0xffff0034 0x100
 }

Modified: trunk/tcl/target/at91r40008.cfg
===================================================================
--- trunk/tcl/target/at91r40008.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/target/at91r40008.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -1,14 +1,14 @@
 
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME at9r40008
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
    set  _ENDIAN little
 }
 

Modified: trunk/tcl/target/at91rm9200.cfg
===================================================================
--- trunk/tcl/target/at91rm9200.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/target/at91rm9200.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -3,15 +3,15 @@
 
 reset_config trst_and_srst
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME at91rm9200
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
    set  _ENDIAN little
 }
 
@@ -39,7 +39,7 @@
 
 # Create the GDB Target.
 set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME 
+target create $_TARGETNAME arm920t -endian $_ENDIAN -chain-position $_TARGETNAME
 
 # AT91RM9200 has a 16K block of sram @ 0x0020.0000
 $_TARGETNAME configure -work-area-virt 0x00200000 -work-area-phys 0x00200000 \

Modified: trunk/tcl/target/at91sam3uXX.cfg
===================================================================
--- trunk/tcl/target/at91sam3uXX.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/target/at91sam3uXX.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -7,15 +7,15 @@
 #  at91sam3u2c
 #  at91sam3u1c
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME sam3
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
    set  _ENDIAN little
 }
 

Modified: trunk/tcl/target/at91sam7sx.cfg
===================================================================
--- trunk/tcl/target/at91sam7sx.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/target/at91sam7sx.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -1,15 +1,15 @@
 #use combined on interfaces or targets that can't set TRST/SRST separately
 reset_config srst_only srst_pulls_trst
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME at91sam7s
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
    set  _ENDIAN little
 }
 
@@ -24,26 +24,26 @@
 set _TARGETNAME $_CHIPNAME.cpu
 
 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
-$_TARGETNAME configure -event reset-init { 
+$_TARGETNAME configure -event reset-init {
         soft_reset_halt
         # RSTC_CR : Reset peripherals
         mww 0xfffffd00 0xa5000004
         # disable watchdog
-	mww 0xfffffd44 0x00008000	
+	mww 0xfffffd44 0x00008000
 	# enable user reset
-	mww 0xfffffd08 0xa5000001	
+	mww 0xfffffd08 0xa5000001
 	# CKGR_MOR : enable the main oscillator
-	mww 0xfffffc20 0x00000601	
+	mww 0xfffffc20 0x00000601
 	sleep 10
 	# CKGR_PLLR: 96.1097 MHz
-	mww 0xfffffc2c 0x00481c0e 	
+	mww 0xfffffc2c 0x00481c0e
 	sleep 10
 	# PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
-	mww 0xfffffc30 0x00000007	
+	mww 0xfffffc30 0x00000007
 	sleep 10
 	# MC_FMR: flash mode (FWS=1,FMCN=73)
-	mww 0xffffff60 0x00490100	
-	sleep 100        
+	mww 0xffffff60 0x00490100
+	sleep 100
 }
 
 $_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup 0

Modified: trunk/tcl/target/at91sam9260.cfg
===================================================================
--- trunk/tcl/target/at91sam9260.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/target/at91sam9260.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -2,15 +2,15 @@
 # Target:    Atmel AT91SAM9260
 ######################################
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME at91sam9260
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
    set  _ENDIAN little
 }
 

Modified: trunk/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg
===================================================================
--- trunk/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/target/at91sam9260_ext_RAM_ext_flash.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -8,15 +8,15 @@
 # Target:    Atmel AT91SAM9260
 ######################################
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME at91sam9260
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
    set  _ENDIAN little
 }
 
@@ -59,7 +59,7 @@
 
 
 proc at91sam_init { } {
-	
+
 	# at reset chip runs at 32khz
 	jtag_khz 8
 	halt

Modified: trunk/tcl/target/c100.cfg
===================================================================
--- trunk/tcl/target/c100.cfg	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/target/c100.cfg	2009-09-21 18:48:22 UTC (rev 2743)
@@ -5,15 +5,15 @@
 # assume no PLL lock, start slowly
 jtag_khz 100
 
-if { [info exists CHIPNAME] } {	
-   set  _CHIPNAME $CHIPNAME    
-} else {	 
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
    set  _CHIPNAME c100
 }
 
-if { [info exists ENDIAN] } {	
-   set  _ENDIAN $ENDIAN    
-} else {	 
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
    set  _ENDIAN little
 }
 

Modified: trunk/tcl/target/c100config.tcl
===================================================================
--- trunk/tcl/target/c100config.tcl	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/target/c100config.tcl	2009-09-21 18:48:22 UTC (rev 2743)
@@ -3,7 +3,7 @@
 
 # set CFG_REFCLKFREQ [configC100 CFG_REFCLKFREQ]
 proc config {label} {
-    return [dict get [configC100] $label ]	
+    return [dict get [configC100] $label ]
 }
 
 # show the value for the param. with label
@@ -15,7 +15,7 @@
 # when there are more then one board config
 # use soft links to c100board-config.tcl
 # so that only the right board-config gets
-# included (just like include/configs/board-configs.h 
+# included (just like include/configs/board-configs.h
 # in u-boot.
 proc configC100 {} {
     # xtal freq. 24MHz
@@ -28,7 +28,7 @@
     # y = amba_clk * (w+1)*(x+1)*2/xtal_clk
     dict set configC100 y_amba [expr ([dict get $configC100 CONFIG_SYS_HZ_CLOCK] * ( ([dict get $configC100 w_amba]+1 ) * ([dict get $configC100 x_amba]+1 ) *2 ) / [dict get $configC100 CFG_REFCLKFREQ]) ]
 
-    # Arm Clk 450MHz, must be a multiple of 25 MHz 
+    # Arm Clk 450MHz, must be a multiple of 25 MHz
     dict set configC100 CFG_ARM_CLOCK      450000000
     dict set configC100 w_arm 0
     dict set configC100 x_arm 1
@@ -41,17 +41,17 @@
 proc setupNOR {} {
     puts "Setting up NOR: 16MB, 16-bit wide bus, CS0"
     # this is taken from u-boot/boards/mindspeed/ooma-darwin/board.c:nor_hw_init()
-    set EX_CSEN_REG	    [regs EX_CSEN_REG ]	
-    set EX_CS0_SEG_REG	    [regs EX_CS0_SEG_REG ]	
-    set EX_CS0_CFG_REG	    [regs EX_CS0_CFG_REG ]	
-    set EX_CS0_TMG1_REG	    [regs EX_CS0_TMG1_REG ]	
-    set EX_CS0_TMG2_REG	    [regs EX_CS0_TMG2_REG ]	
-    set EX_CS0_TMG3_REG	    [regs EX_CS0_TMG3_REG ]	
+    set EX_CSEN_REG	    [regs EX_CSEN_REG ]
+    set EX_CS0_SEG_REG	    [regs EX_CS0_SEG_REG ]
+    set EX_CS0_CFG_REG	    [regs EX_CS0_CFG_REG ]
+    set EX_CS0_TMG1_REG	    [regs EX_CS0_TMG1_REG ]
+    set EX_CS0_TMG2_REG	    [regs EX_CS0_TMG2_REG ]
+    set EX_CS0_TMG3_REG	    [regs EX_CS0_TMG3_REG ]
     set EX_CLOCK_DIV_REG    [regs EX_CLOCK_DIV_REG ]
-    set EX_MFSM_REG	    [regs EX_MFSM_REG ]	
-    set EX_CSFSM_REG	    [regs EX_CSFSM_REG ]	
-    set EX_WRFSM_REG	    [regs EX_WRFSM_REG ]	
-    set EX_RDFSM_REG	    [regs EX_RDFSM_REG ]	
+    set EX_MFSM_REG	    [regs EX_MFSM_REG ]
+    set EX_CSFSM_REG	    [regs EX_CSFSM_REG ]
+    set EX_WRFSM_REG	    [regs EX_WRFSM_REG ]
+    set EX_RDFSM_REG	    [regs EX_RDFSM_REG ]
 
     # enable Expansion Bus Clock + CS0 (NOR)
     mww $EX_CSEN_REG 0x3
@@ -62,7 +62,7 @@
     # set timings to NOR
     mww $EX_CS0_TMG1_REG 0x03034006
     mww $EX_CS0_TMG2_REG 0x04040002
-    #mww $EX_CS0_TMG3_REG 
+    #mww $EX_CS0_TMG3_REG
     # set EBUS clock 165/5=33MHz
     mww $EX_CLOCK_DIV_REG 0x5
     # everthing else is OK with default
@@ -72,7 +72,7 @@
     set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]
     set BLOCK_RESET_REG	       [regs BLOCK_RESET_REG]
     set DDR_RST		       [regs DDR_RST]
- 
+
     # put DDR controller in reset (so that it comes reset in u-boot)
     mmw $BLOCK_RESET_REG 0x0 $DDR_RST
     # setup CS0 controller for NOR
@@ -93,8 +93,8 @@
     #GPIO17 reset for DECT module.
     #GPIO29 CS_n for NAND
 
-    set GPIO_OUTPUT_REG		    [regs GPIO_OUTPUT_REG]	
-    set GPIO_OE_REG		    [regs GPIO_OE_REG]	
+    set GPIO_OUTPUT_REG		    [regs GPIO_OUTPUT_REG]
+    set GPIO_OE_REG		    [regs GPIO_OE_REG]
 
     # set GPIO29=GPIO17=1, GPIO5=0
     mww $GPIO_OUTPUT_REG [expr 1<<29 | 1<<17]
@@ -104,14 +104,14 @@
 
 proc highGPIO5 {} {
     puts "GPIO5 high"
-    set GPIO_OUTPUT_REG		    [regs GPIO_OUTPUT_REG]	
+    set GPIO_OUTPUT_REG		    [regs GPIO_OUTPUT_REG]
     # set GPIO5=1
     mmw $GPIO_OUTPUT_REG [expr 1 << 5] 0x0
 }
 
 proc lowGPIO5 {} {
     puts "GPIO5 low"
-    set GPIO_OUTPUT_REG		    [regs GPIO_OUTPUT_REG]	
+    set GPIO_OUTPUT_REG		    [regs GPIO_OUTPUT_REG]
     # set GPIO5=0
     mmw $GPIO_OUTPUT_REG 0x0 [expr 1 << 5]
 }
@@ -119,31 +119,31 @@
 proc boardID {id} {
     # so far built:
     # 4'b1111
-    dict set boardID 15 name "EVT1"		
+    dict set boardID 15 name "EVT1"
     dict set boardID 15 ddr2size 128M
     # dict set boardID 15 nandsize 1G
     # dict set boardID 15 norsize 16M
     # 4'b0000
-    dict set boardID 0 name "EVT2"		
+    dict set boardID 0 name "EVT2"
     dict set boardID 0 ddr2size 128M
     # 4'b0001
-    dict set boardID 1 name "EVT3"		
+    dict set boardID 1 name "EVT3"
     dict set boardID 1 ddr2size 256M
     # 4'b1110
     dict set boardID 14 name "EVT3_old"
     dict set boardID 14 ddr2size 128M
     # 4'b0010
-    dict set boardID 2 name "EVT4"		
+    dict set boardID 2 name "EVT4"
     dict set boardID 2 ddr2size 256M
 
     return $boardID
 }
 
 # converted from u-boot/boards/mindspeed/ooma-darwin/board.c:ooma_board_detect()
-# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors 
+# figure out what board revision this is, uses BOOTSTRAP register to read stuffed resistors
 proc ooma_board_detect {} {
     set GPIO_BOOTSTRAP_REG	[regs GPIO_BOOTSTRAP_REG]
-    
+
     # read the current value of the BOOTSRAP pins
     set tmp [mrw $GPIO_BOOTSTRAP_REG]
     puts [format "GPIO_BOOTSTRAP_REG  (0x%x): 0x%x" $GPIO_BOOTSTRAP_REG $tmp]
@@ -187,9 +187,9 @@
     set DENALI_CTL_20_DATA    [regs DENALI_CTL_20_DATA]
 
 
-    set DENALI_CTL_02_VAL 0x0100010000010100 
+    set DENALI_CTL_02_VAL 0x0100010000010100
     set DENALI_CTL_11_VAL 0x433A42124A650A37
-    # set some default values     
+    # set some default values
     mw64bit $DENALI_CTL_00_DATA  0x0100000101010101
     mw64bit $DENALI_CTL_01_DATA  0x0100000100000101
     mw64bit $DENALI_CTL_02_DATA  $DENALI_CTL_02_VAL
@@ -218,7 +218,7 @@
     # wait int_status[2] (DRAM init complete)
     puts -nonewline "Waiting for DDR2 controller to init..."
     set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
-    while { [expr $tmp & 0x040000] == 0 } { 
+    while { [expr $tmp & 0x040000] == 0 } {
 	sleep 1
 	set tmp [mrw [expr $DENALI_CTL_08_DATA + 4]]
     }
@@ -237,18 +237,18 @@
     set GPIO_IOCTRL_REG    [regs GPIO_IOCTRL_REG]
     set GPIO_IOCTRL_VAL    [regs GPIO_IOCTRL_VAL]
     set GPIO_IOCTRL_UART0  [regs GPIO_IOCTRL_UART0]
-    set UART0_LCR	            [regs UART0_LCR]	
-    set LCR_DLAB		    [regs LCR_DLAB]	
-    set UART0_DLL		    [regs UART0_DLL]		
-    set UART0_DLH		    [regs UART0_DLH]	
-    set UART0_IIR		    [regs UART0_IIR]	
-    set UART0_IER		    [regs UART0_IER]	
-    set LCR_ONE_STOP		    [regs LCR_ONE_STOP]		
-    set LCR_CHAR_LEN_8		    [regs LCR_CHAR_LEN_8]		
+    set UART0_LCR	            [regs UART0_LCR]
+    set LCR_DLAB		    [regs LCR_DLAB]
+    set UART0_DLL		    [regs UART0_DLL]
+    set UART0_DLH		    [regs UART0_DLH]
+    set UART0_IIR		    [regs UART0_IIR]
+    set UART0_IER		    [regs UART0_IER]
+    set LCR_ONE_STOP		    [regs LCR_ONE_STOP]
+    set LCR_CHAR_LEN_8		    [regs LCR_CHAR_LEN_8]
     set FCR_XMITRES		    [regs FCR_XMITRES]
-    set FCR_RCVRRES		    [regs FCR_RCVRRES]	
-    set FCR_FIFOEN		    [regs FCR_FIFOEN]	
-    set IER_UUE			    [regs IER_UUE]		
+    set FCR_RCVRRES		    [regs FCR_RCVRRES]
+    set FCR_FIFOEN		    [regs FCR_FIFOEN]
+    set IER_UUE			    [regs IER_UUE]
 
     # unlock writing to IOCTRL register
     mww $GPIO_LOCK_REG $GPIO_IOCTRL_VAL
@@ -274,7 +274,7 @@
 
 proc putcUART0 {char} {
 
-    set UART0_LSR	    [regs UART0_LSR]	
+    set UART0_LSR	    [regs UART0_LSR]
     set UART0_THR	    [regs UART0_THR]
     set LSR_TEMT	    [regs LSR_TEMT]
 
@@ -311,7 +311,7 @@
 proc flashUBOOT {} {
     # this will update uboot on NOR partition
     set EXP_CS0_BASEADDR       [regs EXP_CS0_BASEADDR]
-    
+
     # setup CS0 controller for NOR
     setupNOR
     # make sure we are accessing the lower part of NOR

Modified: trunk/tcl/target/c100helper.tcl
===================================================================
--- trunk/tcl/target/c100helper.tcl	2009-09-21 18:40:55 UTC (rev 2742)
+++ trunk/tcl/target/c100helper.tcl	2009-09-21 18:48:22 UTC (rev 2743)
@@ -61,17 +61,17 @@
 
 proc showNOR {} {
     puts "This is the current NOR setup"
-    set EX_CSEN_REG	    [regs EX_CSEN_REG ]	
-    set EX_CS0_SEG_REG	    [regs EX_CS0_SEG_REG ]	
-    set EX_CS0_CFG_REG	    [regs EX_CS0_CFG_REG ]	
-    set EX_CS0_TMG1_REG	    [regs EX_CS0_TMG1_REG ]	
-    set EX_CS0_TMG2_REG	    [regs EX_CS0_TMG2_REG ]	
-    set EX_CS0_TMG3_REG	    [regs EX_CS0_TMG3_REG ]	
+    set EX_CSEN_REG	    [regs EX_CSEN_REG ]
+    set EX_CS0_SEG_REG	    [regs EX_CS0_SEG_REG ]
+    set EX_CS0_CFG_REG	    [regs EX_CS0_CFG_REG ]
+    set EX_CS0_TMG1_REG	    [regs EX_CS0_TMG1_REG ]
+    set EX_CS0_TMG2_...
 
[truncated message content]

[Openocd-svn] r2742 - in trunk/src: . flash/ocl/at91sam7x helper jtag jtag/rlink server target target/xscale

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-21 20:40:55 +0200 (Mon, 21 Sep 2009)
New Revision: 2742

Modified:
   trunk/src/Makefile.am
   trunk/src/flash/ocl/at91sam7x/at91sam7x_ram.ld
   trunk/src/flash/ocl/at91sam7x/crt.s
   trunk/src/flash/ocl/at91sam7x/makefile
   trunk/src/helper/Makefile.am
   trunk/src/helper/startup.tcl
   trunk/src/jtag/jlink.c
   trunk/src/jtag/rlink/call.m4
   trunk/src/server/gdb_server.c
   trunk/src/target/Makefile.am
   trunk/src/target/arm11.c
   trunk/src/target/arm7_9_common.c
   trunk/src/target/arm926ejs.c
   trunk/src/target/breakpoints.c
   trunk/src/target/cortex_a8.c
   trunk/src/target/mips_m4k.c
   trunk/src/target/target.c
   trunk/src/target/target.h
   trunk/src/target/xscale/debug_handler.S
   trunk/src/target/xscale/debug_handler.cmd
Log:
Remove annoying end-of-line whitespace from most src/*
files; omitted src/httpd


Modified: trunk/src/Makefile.am
===================================================================
--- trunk/src/Makefile.am	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/Makefile.am	2009-09-21 18:40:55 UTC (rev 2742)
@@ -9,7 +9,7 @@
 MAINFILE = main.c
 endif
 
-openocd_SOURCES = $(MAINFILE) 
+openocd_SOURCES = $(MAINFILE)
 openocd_LDADD = libopenocd.la
 
 libopenocd_la_SOURCES = openocd.c
@@ -38,7 +38,7 @@
 libopenocd_la_CPPFLAGS += $(AM_CPPFLAGS) $(CPPFLAGS)
 
 # the library search path.
-libopenocd_la_LDFLAGS = $(all_libraries) 
+libopenocd_la_LDFLAGS = $(all_libraries)
 
 if IS_MINGW
 MINGWLDADD = -lwsock32
@@ -97,6 +97,6 @@
 # assumption is: You are only rebuilding the EXE.... and everything
 # else is/was previously installed.
 #
-# use at your own risk 
+# use at your own risk
 quick: all install-binPROGRAMS
 

Modified: trunk/src/flash/ocl/at91sam7x/at91sam7x_ram.ld
===================================================================
--- trunk/src/flash/ocl/at91sam7x/at91sam7x_ram.ld	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/flash/ocl/at91sam7x/at91sam7x_ram.ld	2009-09-21 18:40:55 UTC (rev 2742)
@@ -1,30 +1,30 @@
 /****************************************************************************
 *  Copyright (c) 2006 by Michael Fischer. All rights reserved.
 *
-*  Redistribution and use in source and binary forms, with or without 
-*  modification, are permitted provided that the following conditions 
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
 *  are met:
-*  
-*  1. Redistributions of source code must retain the above copyright 
+*
+*  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in the 
+*     notice, this list of conditions and the following disclaimer in the
 *     documentation and/or other materials provided with the distribution.
-*  3. Neither the name of the author nor the names of its contributors may 
-*     be used to endorse or promote products derived from this software 
+*  3. Neither the name of the author nor the names of its contributors may
+*     be used to endorse or promote products derived from this software
 *     without specific prior written permission.
 *
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
-*  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 
-*  THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
-*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
-*  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 
-*  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 
-*  AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 
-*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-*  THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+*  THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+*  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+*  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+*  AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+*  THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 ****************************************************************************
@@ -94,11 +94,11 @@
     *(COMMON)
     . = ALIGN(4);
     PROVIDE (__bss_end = .);
-    
+
     . = ALIGN(256);
-    
+
     PROVIDE (__stack_start = .);
-    
+
     PROVIDE (__stack_fiq_start = .);
     . += FIQ_STACK_SIZE;
     . = ALIGN(4);
@@ -124,9 +124,9 @@
     . = ALIGN(4);
     PROVIDE (__stack_svc_end = .);
     PROVIDE (__stack_end = .);
-    PROVIDE (__heap_start = .);   
+    PROVIDE (__heap_start = .);
   } > ram
-    
+
 }
 /*** EOF ***/
 

Modified: trunk/src/flash/ocl/at91sam7x/crt.s
===================================================================
--- trunk/src/flash/ocl/at91sam7x/crt.s	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/flash/ocl/at91sam7x/crt.s	2009-09-21 18:40:55 UTC (rev 2742)
@@ -1,30 +1,30 @@
 /****************************************************************************
 *  Copyright (c) 2006 by Michael Fischer. All rights reserved.
 *
-*  Redistribution and use in source and binary forms, with or without 
-*  modification, are permitted provided that the following conditions 
+*  Redistribution and use in source and binary forms, with or without
+*  modification, are permitted provided that the following conditions
 *  are met:
-*  
-*  1. Redistributions of source code must retain the above copyright 
+*
+*  1. Redistributions of source code must retain the above copyright
 *     notice, this list of conditions and the following disclaimer.
 *  2. Redistributions in binary form must reproduce the above copyright
-*     notice, this list of conditions and the following disclaimer in the 
+*     notice, this list of conditions and the following disclaimer in the
 *     documentation and/or other materials provided with the distribution.
-*  3. Neither the name of the author nor the names of its contributors may 
-*     be used to endorse or promote products derived from this software 
+*  3. Neither the name of the author nor the names of its contributors may
+*     be used to endorse or promote products derived from this software
 *     without specific prior written permission.
 *
-*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
-*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
-*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
-*  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 
-*  THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
-*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
-*  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS 
-*  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 
-*  AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 
-*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF 
-*  THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 
+*  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+*  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+*  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+*  FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+*  THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+*  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+*  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+*  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+*  AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+*  OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+*  THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
 *  SUCH DAMAGE.
 *
 ****************************************************************************
@@ -33,14 +33,14 @@
 *
 *  18.12.06  mifi   First Version
 *                   The hardware initialization is based on the startup file
-*                   crtat91sam7x256_rom.S from NutOS 4.2.1. 
+*                   crtat91sam7x256_rom.S from NutOS 4.2.1.
 *                   Therefore partial copyright by egnite Software GmbH.
 ****************************************************************************/
 
 /*
  * Some defines for the program status registers
  */
-   ARM_MODE_USER  = 0x10      /* Normal User Mode                             */ 
+   ARM_MODE_USER  = 0x10      /* Normal User Mode                             */
    ARM_MODE_FIQ   = 0x11      /* FIQ Fast Interrupts Mode                     */
    ARM_MODE_IRQ   = 0x12      /* IRQ Standard Interrupts Mode                 */
    ARM_MODE_SVC   = 0x13      /* Supervisor Interrupts Mode                   */
@@ -48,10 +48,10 @@
    ARM_MODE_UNDEF = 0x1B      /* Undefined Instructions Mode                  */
    ARM_MODE_SYS   = 0x1F      /* System Running in Priviledged Operating Mode */
    ARM_MODE_MASK  = 0x1F
-   
+
    I_BIT          = 0x80      /* disable IRQ when I bit is set */
    F_BIT          = 0x40      /* disable IRQ when I bit is set */
-   
+
 /*
  * Register Base Address
  */
@@ -70,10 +70,10 @@
    MC_BASE          = 0xFFFFFF00
    MC_FMR_OFF       = 0x00000060
    MC_FWS_1FWS      = 0x00480100
-      
+
    .section .vectors,"ax"
    .code 32
-        
+
 /****************************************************************************/
 /*               Vector table and reset entry                               */
 /****************************************************************************/
@@ -101,7 +101,7 @@
 
    .section .init, "ax"
    .code 32
-   
+
    .global ResetHandler
    .global ExitFunction
    .extern main
@@ -116,7 +116,7 @@
    ldr   r0, =WDT_WDDIS
    str   r0, [r1, #WDT_MR_OFF]
 
-   
+
    /*
     * Enable user reset: assertion length programmed to 1ms
     */
@@ -124,7 +124,7 @@
    ldr   r1, =RSTC_MR
    str   r0, [r1, #0]
 
-   
+
    /*
     * Use 2 cycles for flash access.
     */
@@ -141,22 +141,22 @@
    str   r0, [r1, #AIC_EOICR_OFF]
    str   r0, [r1, #AIC_IDCR_OFF]
 
-    
+
    /*
     * Setup a stack for each mode
-    */    
-   msr   CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT   /* Undefined Instruction Mode */     
+    */
+   msr   CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT   /* Undefined Instruction Mode */
    ldr   sp, =__stack_und_end
-   
+
    msr   CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT   /* Abort Mode */
    ldr   sp, =__stack_abt_end
-   
-   msr   CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT     /* FIQ Mode */   
+
+   msr   CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT     /* FIQ Mode */
    ldr   sp, =__stack_fiq_end
-   
-   msr   CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT     /* IRQ Mode */   
+
+   msr   CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT     /* IRQ Mode */
    ldr   sp, =__stack_irq_end
-   
+
    msr   CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT     /* Supervisor Mode */
    ldr   sp, =__stack_svc_end
 
@@ -171,35 +171,35 @@
    cmp   r1, r2
    strne r3, [r1], #+4
    bne   bss_clear_loop
-   
-   
+
+
    /*
     * Jump to main
     */
    mrs   r0, cpsr
    bic   r0, r0, #I_BIT | F_BIT     /* Enable FIQ and IRQ interrupt */
    msr   cpsr, r0
-   
+
    mov   r0, #0 /* No arguments */
    mov   r1, #0 /* No arguments */
    ldr   r2, =main
    mov   lr, pc
    bx    r2     /* And jump... */
-                       
+
 ExitFunction:
    nop
    nop
    nop
-   b ExitFunction   
-   
+   b ExitFunction
 
+
 /****************************************************************************/
 /*                         Default interrupt handler                        */
 /****************************************************************************/
 
 UndefHandler:
    b UndefHandler
-   
+
 SWIHandler:
    b SWIHandler
 
@@ -208,13 +208,13 @@
 
 DAbortHandler:
    b DAbortHandler
-   
+
 IRQHandler:
    b IRQHandler
-   
+
 FIQHandler:
    b FIQHandler
-   
+
    .weak ExitFunction
    .weak UndefHandler, PAbortHandler, DAbortHandler
    .weak IRQHandler, FIQHandler

Modified: trunk/src/flash/ocl/at91sam7x/makefile
===================================================================
--- trunk/src/flash/ocl/at91sam7x/makefile	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/flash/ocl/at91sam7x/makefile	2009-09-21 18:40:55 UTC (rev 2742)
@@ -13,19 +13,19 @@
 MCU  = arm7tdmi
 
 # List all default C defines here, like -D_DEBUG=1
-DDEFS = 
+DDEFS =
 
 # List all default ASM defines here, like -D_DEBUG=1
-DADEFS = 
+DADEFS =
 
 # List all default directories to look for include files here
-DINCDIR = 
+DINCDIR =
 
 # List the default directory to look for the libraries here
 DLIBDIR =
 
 # List all default libraries here
-DLIBS = 
+DLIBS =
 
 #
 # End of default section
@@ -42,10 +42,10 @@
 LDSCRIPT= at91sam7x_ram.ld
 
 # List all user C define here, like -D_DEBUG=1
-UDEFS = 
+UDEFS =
 
 # Define ASM defines here
-UADEFS = 
+UADEFS =
 
 # List C source files here
 SRC  = main.c dcc.c samflash.c
@@ -60,7 +60,7 @@
 ULIBDIR =
 
 # List all user libraries here
-ULIBS = 
+ULIBS =
 
 # Define optimisation level here
 OPT = -O2
@@ -122,7 +122,7 @@
 	-rm -f $(ASRC:.s=.lst)
 	-rm -fR .dep
 
-# 
+#
 # Include the dependency files, should be the last of the makefile
 #
 #-include $(shell mkdir .dep 2>/dev/null) $(wildcard .dep/*)

Modified: trunk/src/helper/Makefile.am
===================================================================
--- trunk/src/helper/Makefile.am	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/helper/Makefile.am	2009-09-21 18:40:55 UTC (rev 2742)
@@ -7,9 +7,9 @@
 noinst_LTLIBRARIES = libhelper.la
 
 if ECOSBOARD
-CONFIGFILES = 
+CONFIGFILES =
 else
-CONFIGFILES = options.c jim.c jim-eventloop.c 
+CONFIGFILES = options.c jim.c jim-eventloop.c
 endif
 
 

Modified: trunk/src/helper/startup.tcl
===================================================================
--- trunk/src/helper/startup.tcl	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/helper/startup.tcl	2009-09-21 18:40:55 UTC (rev 2742)
@@ -24,16 +24,16 @@
 
 # Show flash in human readable form
 # This is an example of a human readable form of a low level fn
-proc flash_banks {} { 
-	set i 0 	
+proc flash_banks {} {
+	set i 0
 	set result ""
 	foreach {a} [ocd_flash_banks] {
 		if {$i > 0} {
 			set result "$result\n"
 		}
 		set result [format "$result#%d: %s at 0x%08x, size 0x%08x, buswidth %d, chipwidth %d" $i $a(name) $a(base) $a(size) $a(bus_width) $a(chip_width)]
-		set i [expr $i+1]	
-	}	
+		set i [expr $i+1]
+	}
 	return $result
 }
 
@@ -56,7 +56,7 @@
 			set n 0
 			while 1 {
 				if {$n > [string length $h]} {break}
-				
+
 				set next_a [expr $n+$w]
 				if {[string length $h]>$n+$w} {
 					set xxxx [string range $h $n [expr $n+$w]]
@@ -67,8 +67,8 @@
 						set next_a [expr $lastpos+$n+1]
 					}
 				}
-				
-				
+
+
 				puts [format "%-25s %s" $cmdname [string range $h $n [expr $next_a-1]] ]
 				set cmdname ""
 				set n [expr $next_a]
@@ -144,11 +144,11 @@
 		set in_process_reset 0
 		return -code error "'reset' can not be invoked recursively"
 	}
-	
+
 	set in_process_reset 1
-	set success [expr [catch {ocd_process_reset_inner $MODE} result]==0] 
+	set success [expr [catch {ocd_process_reset_inner $MODE} result]==0]
 	set in_process_reset 0
-	
+
 	if {$success} {
 		return $result
 	} else {
@@ -239,13 +239,13 @@
 			# the JTAG tap reset signal might be hooked to a slow
 			# resistor/capacitor circuit - and it might take a while
 			# to charge
-			
+
 			# Catch, but ignore any errors.
 			catch { $t arp_waitstate halted 1000 }
-			
+
 			# Did we succeed?
 			set s [$t curstate]
-			
+
 			if { 0 != [string compare $s "halted" ] } {
 				return -error [format "TARGET: %s - Not halted" $t]
 			}
@@ -262,7 +262,7 @@
 			set err [catch "$t arp_waitstate halted 5000"]
 			# Did it halt?
 			if { $err == 0 } {
-				$t invoke-event reset-init		
+				$t invoke-event reset-init
 			}
 		}
 	}
@@ -294,13 +294,13 @@
 # A list of names of CPU and options required
 set ocd_cpu_list {
 	{
-		name IXP42x 
-		options {xscale -variant IXP42x} 
+		name IXP42x
+		options {xscale -variant IXP42x}
 		comment {IXP42x cpu}
 	}
 	{
-		name arm7 
-		options {arm7tdmi -variant arm7tdmi} 
+		name arm7
+		options {arm7tdmi -variant arm7tdmi}
 		comment {vanilla ARM7}
 	}
 }
@@ -312,7 +312,7 @@
 	global ocd_cpu_list
 	foreach a [lsort $ocd_cpu_list] {
 		if {[string length $args]==0||[string first [string toupper $name] [string toupper "$a(name)$a(options)$a(comment)"]]!=-1} {
-			lappend result $a 
+			lappend result $a
 		}
 	}
 	return $result
@@ -352,5 +352,5 @@
 	catch {
 		capture {uplevel $a}
 	} result
-	return $result 
+	return $result
 }

Modified: trunk/src/jtag/jlink.c
===================================================================
--- trunk/src/jtag/jlink.c	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/jtag/jlink.c	2009-09-21 18:40:55 UTC (rev 2742)
@@ -314,7 +314,7 @@
 		LOG_ERROR("Cannot find jlink Interface! Please check connection and permissions.");
 		return ERROR_JTAG_INIT_FAILED;
 	}
-	
+
 	/*
 	 *  The next three instructions were added after discovering a problem while using an oscilloscope.  For the V8
 	 *	SAM-ICE dongle (and likely other j-link device variants), the reset line to the target microprocessor was found to
@@ -324,7 +324,7 @@
 	 *	following a new USB session.  Keeping the processor in reset during the first read collecting version information
 	 *	seems to prevent errant "J-Link command EMU_CMD_VERSION failed" issues.
 	 */
-	
+
 	LOG_INFO("J-Link initialization started / target CPU reset initiated");
 	jlink_simple_command(EMU_CMD_HW_TRST0);
 	jlink_simple_command(EMU_CMD_HW_RESET0);
@@ -881,7 +881,7 @@
 
 	if (result->usb_handle)
 	{
-	
+
 		/* BE ***VERY CAREFUL*** ABOUT MAKING CHANGES IN THIS AREA!!!!!!!!!!!
 		 * The behavior of libusb is not completely consistent across Windows, Linux, and Mac OS X platforms.  The actions taken
 		 * in the following compiler conditionals may not agree with published documentation for libusb, but were found

Modified: trunk/src/jtag/rlink/call.m4
===================================================================
--- trunk/src/jtag/rlink/call.m4	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/jtag/rlink/call.m4	2009-09-21 18:40:55 UTC (rev 2742)
@@ -67,7 +67,7 @@
 	A.L = m4_low_nybble(`('$1`) / 2')
 	Y = A
 )')
-	
+
 m4_define(`m4_delay_loop',
 `; delay loop (m4_eval($1) cycles)'
 `m4_ifelse(m4_eval(`('$1`) < 6'), 1,
@@ -79,7 +79,7 @@
 )')
 
 m4_dnl These are utility macros for use with delays.  Specifically, there is code below which needs some predictability in code size for relative jumps to reach.  The m4_delay macro generates an extra NOP when an even delay is needed, and the m4_delay_loop macro generates an extra NOP when an odd delay is needed.  Using this for the argument to the respective macro rounds up the argument so that the extra NOP will not be generated.  There is also logic built in to cancel the rounding when the result is small enough that a loop would not be generated.
-	
+
 m4_define(`m4_delay_loop_round_up', `m4_ifelse(m4_eval($1` < 6'), 1, $1, m4_eval(`(('$1`) + 1) / 2 * 2'))')
 m4_define(`m4_delay_round_up', `m4_ifelse(m4_eval($1` < 6'), 1, $1, m4_eval(`(('$1`) / 2 * 2) + 1'))')
 
@@ -106,7 +106,7 @@
 	A.H = 0xc	; lookup table at 0x1550 + 0xc0 = 0x1610
 
 	; branch to address in lookup table
-	Y = A 
+	Y = A
 	A = <Y>
 	BRANCH
 
@@ -203,7 +203,7 @@
 ;	; Ack buffer 0 in download mode
 ;	A.L = 0x1
 ;	BUFFER_MNGT = A
-;	
+;
 ;	STATUS STOP
 
 
@@ -213,7 +213,7 @@
 
 	A = CMP01	; bits 3..0 contain the number of bytes to shift - 1
 	A.H = 0
-	Y = A		; loop counter 
+	Y = A		; loop counter
 
 	A = CMP01
 	EXCHANGE
@@ -262,7 +262,7 @@
 
 	A = CMP01	; bits 3..0 contain the number of bytes to shift - 1
 	A.H = 0
-	Y = A		; loop counter 
+	Y = A		; loop counter
 
 opcode_shift_tdo_bytes__loop:
 	SHIFT MPEG PIN0=>IN
@@ -303,7 +303,7 @@
 
 	JP sub_shift_tdio_bits
 opcode_shift_tdio_bytes__sub_return:
-	
+
 	A = CMP10	; byte loop counter
 	CP A=>X
 	CLC
@@ -323,7 +323,7 @@
 	A = CMP01	; bits 2..0 contain the number of bits to shift - 1
 	A.H = 0
 	BCLR 3		; set TMS=1 if bit 3 was set
-	CMP11 = A	; bit loop counter 
+	CMP11 = A	; bit loop counter
 
 	A.H = opcode_shift_tdio_bits__sub_return
 	A.L = opcode_shift_tdio_bits__sub_return
@@ -334,7 +334,7 @@
 	DR_CARD = A
 	JP sub_shift_tdio_bits
 opcode_shift_tdio_bits__sub_return:
-	
+
 	A = X
 ;DR_MPEG = A ; return TCK low, as str912 reset halt seems to require it
 	BRANCH
@@ -365,9 +365,9 @@
 m4_delay_loop(m4_delay_loop_round_up(SETUP_DELAY_CYCLES - 1))
 
 	BSET 2		; TCK high
-	DR_MPEG = A 
+	DR_MPEG = A
 
-	A = DR_MPEG	; set carry bit to TDO 
+	A = DR_MPEG	; set carry bit to TDO
 	CLC
 	BCLR 0
 	JP +2
@@ -431,7 +431,7 @@
 	BSET 3		; bit says whether to return TDO
 	JP +2
 	ADR_BUFFER1 -= X	; subroutine returns it, so undo that
-	
+
 	A = X
 	DR_MPEG = A ; return TCK low, as str912 reset halt seems to require it
 	BRANCH
@@ -443,7 +443,7 @@
 
 	A = CMP01	; bits 3..0 contain the number of bits to shift - 1 (only 1-8 bits is valid... no checking, just improper operation)
 	A.H = 0
-	CMP11 = A	; bit loop counter 
+	CMP11 = A	; bit loop counter
 
 	A = DATA_BUFFER0	; get byte from input buffer
 	ADR_BUFFER0 += X
@@ -467,7 +467,7 @@
 m4_delay_loop(SETUP_DELAY_CYCLES - 1)
 
 	BSET 2		; TCK high
-	DR_MPEG = A 
+	DR_MPEG = A
 
 m4_delay(HOLD_DELAY_CYCLES - 10)
 

Modified: trunk/src/server/gdb_server.c
===================================================================
--- trunk/src/server/gdb_server.c	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/server/gdb_server.c	2009-09-21 18:40:55 UTC (rev 2742)
@@ -822,7 +822,7 @@
 	log_remove_callback(gdb_log_callback, connection);
 
 	gdb_actual_connections--;
-	LOG_DEBUG("GDB Close, Target: %s, state: %s, gdb_actual_connections=%d", 
+	LOG_DEBUG("GDB Close, Target: %s, state: %s, gdb_actual_connections=%d",
 		  gdb_service->target->cmd_name,
 		  target_state_name(gdb_service->target),
 		  gdb_actual_connections);

Modified: trunk/src/target/Makefile.am
===================================================================
--- trunk/src/target/Makefile.am	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/target/Makefile.am	2009-09-21 18:40:55 UTC (rev 2742)
@@ -98,7 +98,7 @@
 	avrt.h
 
 nobase_dist_pkglib_DATA =
-nobase_dist_pkglib_DATA += xscale/debug_handler.bin 
+nobase_dist_pkglib_DATA += xscale/debug_handler.bin
 nobase_dist_pkglib_DATA += ecos/at91eb40a.elf
 
 MAINTAINERCLEANFILES = $(srcdir)/Makefile.in

Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/target/arm11.c	2009-09-21 18:40:55 UTC (rev 2742)
@@ -1066,7 +1066,7 @@
 			retval = arm11_simulate_step(target, &next_pc);
 			if (retval != ERROR_OK)
 				return retval;
-				
+
 			brp[0].value	= next_pc;
 			brp[1].value	= 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (0 << 21);
 		}

Modified: trunk/src/target/arm7_9_common.c
===================================================================
--- trunk/src/target/arm7_9_common.c	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/target/arm7_9_common.c	2009-09-21 18:40:55 UTC (rev 2742)
@@ -95,7 +95,7 @@
 	{
 		LOG_ERROR("BUG: no hardware comparator available");
 	}
-	LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d", 
+	LOG_DEBUG("BPID: %d (0x%08" PRIx32 ") using hw wp: %d",
 			  breakpoint->unique_id,
 			  breakpoint->address,
 			  breakpoint->set );
@@ -158,7 +158,7 @@
 		LOG_ERROR("BUG: both watchpoints used, but wp_available >= 1");
 		return ERROR_FAIL;
 	}
-	LOG_DEBUG("SW BP using hw wp: %d", 
+	LOG_DEBUG("SW BP using hw wp: %d",
 			  arm7_9->sw_breakpoints_added );
 
 	return jtag_execute_queue();
@@ -371,7 +371,7 @@
 
 	if (breakpoint->type == BKPT_HARD)
 	{
-		LOG_DEBUG("BPID: %d Releasing hw wp: %d", 
+		LOG_DEBUG("BPID: %d Releasing hw wp: %d",
 				  breakpoint->unique_id,
 				  breakpoint->set );
 		if (breakpoint->set == 1)

Modified: trunk/src/target/arm926ejs.c
===================================================================
--- trunk/src/target/arm926ejs.c	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/target/arm926ejs.c	2009-09-21 18:40:55 UTC (rev 2742)
@@ -174,12 +174,12 @@
 		{
 			return retval;
 		}
-		
+
 		if (buf_get_u32(&access, 0, 1) == 1)
 		{
 			break;
 		}
-		
+
 		/* 10ms timeout */
 		if ((timeval_ms()-then)>10)
 		{

Modified: trunk/src/target/breakpoints.c
===================================================================
--- trunk/src/target/breakpoints.c	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/target/breakpoints.c	2009-09-21 18:40:55 UTC (rev 2742)
@@ -54,7 +54,7 @@
 	{
 		n++;
 		if (breakpoint->address == address){
-			LOG_DEBUG("Duplicate Breakpoint address: 0x%08" PRIx32 " (BP %d)", 
+			LOG_DEBUG("Duplicate Breakpoint address: 0x%08" PRIx32 " (BP %d)",
 				  address, breakpoint->unique_id );
 			return ERROR_OK;
 		}
@@ -76,10 +76,10 @@
 		switch (retval)
 		{
 			case ERROR_TARGET_RESOURCE_NOT_AVAILABLE:
-				LOG_INFO("can't add %s breakpoint, resource not available (BPID=%d)", 
+				LOG_INFO("can't add %s breakpoint, resource not available (BPID=%d)",
 					 breakpoint_type_strings[(*breakpoint_p)->type],
 					 (*breakpoint_p)->unique_id );
-				
+
 				free((*breakpoint_p)->orig_instr);
 				free(*breakpoint_p);
 				*breakpoint_p = NULL;
@@ -87,7 +87,7 @@
 				break;
 			case ERROR_TARGET_NOT_HALTED:
 				LOG_INFO("can't add breakpoint while target is running (BPID: %d)",
-						 (*breakpoint_p)->unique_id );						 
+						 (*breakpoint_p)->unique_id );
 				free((*breakpoint_p)->orig_instr);
 				free(*breakpoint_p);
 				*breakpoint_p = NULL;
@@ -207,7 +207,7 @@
 		switch (retval)
 		{
 			case ERROR_TARGET_RESOURCE_NOT_AVAILABLE:
-				LOG_INFO("can't add %s watchpoint, resource not available (WPID: %d)", 
+				LOG_INFO("can't add %s watchpoint, resource not available (WPID: %d)",
 					 watchpoint_rw_strings[(*watchpoint_p)->rw],
 					 (*watchpoint_p)->unique_id );
 				free (*watchpoint_p);
@@ -230,7 +230,7 @@
 
 	LOG_DEBUG("added %s watchpoint at 0x%8.8" PRIx32 " of length 0x%8.8x (WPID: %d)",
 			  watchpoint_rw_strings[(*watchpoint_p)->rw],
-			  (*watchpoint_p)->address, 
+			  (*watchpoint_p)->address,
 			  (*watchpoint_p)->length,
 			  (*watchpoint_p)->unique_id );
 

Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/target/cortex_a8.c	2009-09-21 18:40:55 UTC (rev 2742)
@@ -138,8 +138,8 @@
 	/* Clear Sticky Power Down status Bit in PRSR to enable access to
 	   the registers in the Core Power Domain */
 	retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
-	/* Enabling of instruction execution in debug mode is done in debug_entry code */ 
-	
+	/* Enabling of instruction execution in debug mode is done in debug_entry code */
+
 	return retval;
 }
 
@@ -1374,7 +1374,7 @@
 	uint32_t didr, ctypr, ttypr, cpuid;
 
 	LOG_DEBUG("TODO");
-	
+
 	/* Here we shall insert a proper ROM Table scan */
 	armv7a->debug_base = OMAP3530_DEBUG_BASE;
 
@@ -1451,7 +1451,7 @@
 
 	/* Configure core debug access */
 	cortex_a8_init_debug_access(target);
-	
+
 	target->type->examined = 1;
 
 	return retval;

Modified: trunk/src/target/mips_m4k.c
===================================================================
--- trunk/src/target/mips_m4k.c	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/target/mips_m4k.c	2009-09-21 18:40:55 UTC (rev 2742)
@@ -524,7 +524,7 @@
 		target_write_u32(target, comparator_list[bp_num].reg_address, comparator_list[bp_num].bp_value);
 		target_write_u32(target, comparator_list[bp_num].reg_address + 0x08, 0x00000000);
 		target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 1);
-		LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "", 
+		LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx32 "",
 				  breakpoint->unique_id,
 				  bp_num, comparator_list[bp_num].bp_value);
 	}
@@ -612,7 +612,7 @@
 		comparator_list[bp_num].used = 0;
 		comparator_list[bp_num].bp_value = 0;
 		target_write_u32(target, comparator_list[bp_num].reg_address + 0x18, 0);
-		
+
 	}
 	else
 	{
@@ -711,9 +711,9 @@
 	 * and exclude both load and store accesses from  watchpoint
 	 * condition evaluation
 	*/
-	int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE | 
+	int enable = EJTAG_DBCn_NOSB | EJTAG_DBCn_NOLB | EJTAG_DBCn_BE |
                 (0xff << EJTAG_DBCn_BLM_SHIFT);
-	
+
 	if (watchpoint->set)
 	{
 		LOG_WARNING("watchpoint already set");
@@ -765,7 +765,7 @@
 	target_write_u32(target, comparator_list[wp_num].reg_address + 0x18, enable);
 	target_write_u32(target, comparator_list[wp_num].reg_address + 0x20, 0);
 	LOG_DEBUG("wp_num %i bp_value 0x%" PRIx32 "", wp_num, comparator_list[wp_num].bp_value);
-	
+
 	return ERROR_OK;
 }
 
@@ -774,7 +774,7 @@
 	/* get pointers to arch-specific information */
 	mips32_common_t *mips32 = target->arch_info;
 	mips32_comparator_t * comparator_list = mips32->data_break_list;
-	
+
 	if (!watchpoint->set)
 	{
 		LOG_WARNING("watchpoint not set");
@@ -804,7 +804,7 @@
 		LOG_INFO("no hardware watchpoints available");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
-		
+
 	mips32->num_data_bpoints_avail--;
 
 	mips_m4k_set_watchpoint(target, watchpoint);

Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/target/target.c	2009-09-21 18:40:55 UTC (rev 2742)
@@ -1241,7 +1241,7 @@
 		address += aligned;
 		size -= aligned;
 	}
-	
+
 	/*prevent byte access when possible (avoid AHB access limitations in some cases)*/
 	if(size	>=2)
 	{

Modified: trunk/src/target/target.h
===================================================================
--- trunk/src/target/target.h	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/target/target.h	2009-09-21 18:40:55 UTC (rev 2742)
@@ -42,7 +42,7 @@
  * TARGET_RESET   = 3: the target is being held in reset (only a temporary state,
  * not sure how this is used with all the recent changes)
  * TARGET_DEBUG_RUNNING = 4: the target is running, but it is executing code on
- * behalf of the debugger (e.g. algorithm for flashing) 
+ * behalf of the debugger (e.g. algorithm for flashing)
  *
  * also see: target_state_name();
  */

Modified: trunk/src/target/xscale/debug_handler.S
===================================================================
--- trunk/src/target/xscale/debug_handler.S	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/target/xscale/debug_handler.S	2009-09-21 18:40:55 UTC (rev 2742)
@@ -30,7 +30,7 @@
 1:
 	mrc p14, 0, r15, c14, c0, 0
 	bvs 1b
-	mcr p14, 0, \reg, c8, c0, 0	
+	mcr p14, 0, \reg, c8, c0, 0
 .endm
 
 @ receive word from debugger
@@ -38,7 +38,7 @@
 1:
 	mrc p14, 0, r15, c14, c0, 0
 	bpl 1b
-	mrc p14, 0, \reg, c9, c0, 0	
+	mrc p14, 0, \reg, c9, c0, 0
 .endm
 
 @ save register on debugger, small
@@ -75,7 +75,7 @@
 	mrc p14, 0, r13, c10, c0
 	@ check if global enable bit (GE) is set
 	ands r13, r13, #0x80000000
-	
+
 	bne debug_handler
 
 	@ set global enable bit (GE)
@@ -111,7 +111,7 @@
 	cmp r1, #MODE_USR
 
 	bne not_user_mode
-	
+
 	@ replace USR mode with SYS
 	bic r0, r0, #MODE_MASK
 	orr r0, r0, #MODE_SYS
@@ -124,7 +124,7 @@
 @ wait for command from debugger, than execute desired function
 get_command:
 	bl receive_from_debugger
-	
+
 	@ 0x0n - register access
 	cmp r0, #0x0
 	beq get_banked_registers
@@ -145,10 +145,10 @@
 	@ 0x2n - write memory
 	cmp r0, #0x21
 	beq write_byte
-	
+
 	cmp r0, #0x22
 	beq write_half_word
-	
+
 	cmp r0, #0x24
 	beq write_word
 
@@ -172,7 +172,7 @@
 
 	cmp r0, #0x51
 	beq invalidate_d_cache
-	
+
 	cmp r0, #0x52
 	beq invalidate_i_cache
 
@@ -185,10 +185,10 @@
 
 	cmp r0, #0x61
 	beq read_trace_buffer
-	
+
 	cmp r0, #0x62
 	beq clean_trace_buffer
-	
+
 	@ return (back to get_command)
 	b get_command
 
@@ -221,11 +221,11 @@
 	m_receive_from_debugger lr
 
 	@ branch back to application code, restoring CPSR
-	subs pc, lr, #0	
+	subs pc, lr, #0
 
 @ get banked registers
-@ receive mode bits from host, then run into save_banked_registers to 
-	
+@ receive mode bits from host, then run into save_banked_registers to
+
 get_banked_registers:
 	bl receive_from_debugger
 
@@ -239,7 +239,7 @@
 
 	@ keep current mode bits in r1 for later use
 	and r1, r0, #MODE_MASK
-	
+
 	@ backup banked registers
 	m_send_to_debugger r8
 	m_send_to_debugger r9
@@ -251,7 +251,7 @@
 
 	@ if not in SYS mode (or USR, which we replaced with SYS before)
 	cmp r1, #MODE_SYS
-	
+
 	beq no_spsr_to_save
 
 	@ backup SPSR
@@ -271,8 +271,8 @@
 
 
 @ set banked registers
-@ receive mode bits from host, then run into save_banked_registers to 
-	
+@ receive mode bits from host, then run into save_banked_registers to
+
 set_banked_registers:
 	bl receive_from_debugger
 
@@ -286,7 +286,7 @@
 
 	@ keep current mode bits in r1 for later use
 	and r1, r0, #MODE_MASK
-	
+
 	@ set banked registers
 	m_receive_from_debugger r8
 	m_receive_from_debugger r9
@@ -298,7 +298,7 @@
 
 	@ if not in SYS mode (or USR, which we replaced with SYS before)
 	cmp r1, #MODE_SYS
-	
+
 	beq no_spsr_to_restore
 
 	@ set SPSR
@@ -327,7 +327,7 @@
 
 rb_loop:
 	ldrb r0, [r2], #1
-	
+
 	@ drain write- (and fill-) buffer to work around XScale errata
 	mcr p15, 0, r8, c7, c10, 4
 
@@ -335,7 +335,7 @@
 
 	subs r1, r1, #1
 	bne rb_loop
-	
+
 	@ return
 	b get_command
 
@@ -352,7 +352,7 @@
 
 rh_loop:
 	ldrh r0, [r2], #2
-	
+
 	@ drain write- (and fill-) buffer to work around XScale errata
 	mcr p15, 0, r8, c7, c10, 4
 
@@ -360,7 +360,7 @@
 
 	subs r1, r1, #1
 	bne rh_loop
-	
+
 	@ return
 	b get_command
 
@@ -377,7 +377,7 @@
 
 rw_loop:
 	ldr r0, [r2], #4
-	
+
 	@ drain write- (and fill-) buffer to work around XScale errata
 	mcr p15, 0, r8, c7, c10, 4
 
@@ -385,7 +385,7 @@
 
 	subs r1, r1, #1
 	bne rw_loop
-	
+
 	@ return
 	b get_command
 
@@ -409,7 +409,7 @@
 
 	subs r1, r1, #1
 	bne wb_loop
-	
+
 	@ return
 	b get_command
 
@@ -433,7 +433,7 @@
 
 	subs r1, r1, #1
 	bne wh_loop
-	
+
 	@ return
 	b get_command
 
@@ -457,7 +457,7 @@
 
 	subs r1, r1, #1
 	bne ww_loop
-	
+
 	@ return
 	b get_command
 
@@ -466,7 +466,7 @@
 clear_sa:
 	@ read DCSR
 	mrc p14, 0, r0, c10, c0
-	
+
 	@ clear SA bit
 	bic r0, r0, #0x20
 
@@ -481,7 +481,7 @@
 clean_d_cache:
 	@ r0: cache clean area
 	bl receive_from_debugger
-	
+
 	mov r1, #1024
 clean_loop:
 	mcr p15, 0, r0, c7, c2, 5
@@ -568,7 +568,7 @@
 	b read_cp_reg_reply
 
 read_cp_reg_reply:
-	bl send_to_debugger	
+	bl send_to_debugger
 
 	@ return
 	b get_command
@@ -641,14 +641,14 @@
 	@ dump checkpoint register 0
 	mrc p14, 0, r0, c12, c0, 0 @ XSCALE_CHKPT0 (0x10)
 	bl send_to_debugger
-	
+
 	@ dump checkpoint register 1
 	mrc p14, 0, r0, c13, c0, 0 @ XSCALE_CHKPT1 (0x11)
 	bl send_to_debugger
 
 	@ return
 	b get_command
-	
+
 @ ----
 
 clean_trace_buffer:
@@ -662,7 +662,7 @@
 
 	@ return
 	b get_command
-	
+
 @ ----
 
 
@@ -697,7 +697,7 @@
 	mcr p14, 0, r13, c10, c0, 0 @ XSCALE_DCSR
 
 	@ branch back to application code, restoring CPSR
-	subs pc, lr, #0	
+	subs pc, lr, #0
 
 undef_handler:
 swi_handler:

Modified: trunk/src/target/xscale/debug_handler.cmd
===================================================================
--- trunk/src/target/xscale/debug_handler.cmd	2009-09-21 09:25:52 UTC (rev 2741)
+++ trunk/src/target/xscale/debug_handler.cmd	2009-09-21 18:40:55 UTC (rev 2742)
@@ -2,14 +2,14 @@
 ENTRY(reset_handler)
 
 /* specify the mini-ICache memory areas  */
-MEMORY 
+MEMORY
 {
 	mini_icache_0 (x)  				: ORIGIN = 0x0, LENGTH = 1024	/* first part of mini icache (sets 0-31) */
 	mini_icache_1 (x)  				: ORIGIN = 0x400, LENGTH = 1024	/* second part of mini icache (sets 0-31) */
 }
 
 /* now define the output sections  */
-SECTIONS 
+SECTIONS
 {
 	.part1 :
 	{

[Openocd-svn] r2741 - trunk/tcl/board

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-21 11:25:52 +0200 (Mon, 21 Sep 2009)
New Revision: 2741

Added:
   trunk/tcl/board/csb732.cfg
Log:
Ethan Eade <et...@ev...> board config script for Cogent CSB732 i.MX35 (arm1136)

Added: trunk/tcl/board/csb732.cfg
===================================================================
--- trunk/tcl/board/csb732.cfg	2009-09-21 00:37:58 UTC (rev 2740)
+++ trunk/tcl/board/csb732.cfg	2009-09-21 09:25:52 UTC (rev 2741)
@@ -0,0 +1,71 @@
+# The Cogent CSB732 board has a single i.MX35 chip
+source [find target/imx35.cfg]
+
+# Determined by trial and error
+reset_config trst_and_srst combined
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+$_TARGETNAME configure -event reset-init { csb732_init }
+
+# Bare-bones initialization of core clocks and SDRAM
+proc csb732_init { } {
+	
+	# Disable fast writing only for init
+	memwrite burst disable
+
+	# All delay loops are omitted.
+	# We assume the interpreter latency is enough.
+
+	# Allow access to all coprocessors
+	arm11 mcr imx35.cpu 15 0 15 1 0 0x2001
+
+	# Disable MMU, caches, write buffer
+	arm11 mcr imx35.cpu 15 0 1 0 0 0x78
+
+	# Grant manager access to all domains
+	arm11 mcr imx35.cpu 15 0 3 0 0 0xFFFFFFFF
+
+	# Set ARM clock to 532 MHz, AHB to 133 MHz
+	mww 0x53F80004 0x1000
+	
+	# Set core clock to 2 * 24 MHz * (11 + 1/12) = 532 MHz
+	mww 0x53F8001C 0xB2C01
+	
+	set ESDMISC 0xB8001010
+	set ESDCFG0 0xB8001004
+	set ESDCTL0 0xB8001000
+
+	# Enable DDR
+	mww $ESDMISC 0x4
+	
+	# Timing
+	mww $ESDCFG0 0x007fff3f
+
+	# CS0
+	mww $ESDCTL0 0x92120080
+
+	# Precharge all dummy write
+	mww 0x80000400 0
+
+	# Enable CS) auto-refresh
+	mww $ESDCTL0 0xA2120080
+	
+	# Refresh twice (dummy writes)
+	mww 0x80000000 0
+	mww 0x80000000 0
+
+	# Enable CS0 load mode register
+	mww $ESDCTL0 0xB2120080
+
+	# Dummy writes	
+	mwb 0x80000033 0x01
+	mwb 0x81000000 0x01
+
+	mww $ESDCTL0 0x82226080
+	mww 0x80000000 0
+
+	# Re-enable fast writing
+	memwrite burst enable
+}


Property changes on: trunk/tcl/board/csb732.cfg
___________________________________________________________________
Name: svn:eol-style
   + native

[Openocd-svn] r2740 - trunk/tcl/target

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-21 02:37:58 +0200 (Mon, 21 Sep 2009)
New Revision: 2740

Modified:
   trunk/tcl/target/ti_dm355.cfg
   trunk/tcl/target/ti_dm365.cfg
   trunk/tcl/target/ti_dm6446.cfg
Log:
Ensure that DaVinci chips can't start with a too-fast JTAG clock.
It can be sped up later, once it's known the PLLs are active.

Note that modern tools from TI all use adaptive clocking; and
that if that's done with OpenOCD, "too fast" is also a non-issue.


Modified: trunk/tcl/target/ti_dm355.cfg
===================================================================
--- trunk/tcl/target/ti_dm355.cfg	2009-09-21 00:04:35 UTC (rev 2739)
+++ trunk/tcl/target/ti_dm355.cfg	2009-09-21 00:37:58 UTC (rev 2740)
@@ -86,6 +86,12 @@
 	-work-area-size 0x4000 \
 	-work-area-backup 0
 
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 24 MHz (best case: 36 MHz) even when no bootloader turns
+# on the PLL and starts using it.  OK to speed up after clock setup.
+jtag_rclk 1500
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
 

Modified: trunk/tcl/target/ti_dm365.cfg
===================================================================
--- trunk/tcl/target/ti_dm365.cfg	2009-09-21 00:04:35 UTC (rev 2739)
+++ trunk/tcl/target/ti_dm365.cfg	2009-09-21 00:37:58 UTC (rev 2740)
@@ -88,6 +88,12 @@
 	-work-area-size 0x4000 \
 	-work-area-backup 0
 
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 19.2 MHz (best case: 36 MHz) even when no bootloader turns
+# on the PLL and starts using it.  OK to speed up after clock setup.
+jtag_rclk 1500
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
 

Modified: trunk/tcl/target/ti_dm6446.cfg
===================================================================
--- trunk/tcl/target/ti_dm6446.cfg	2009-09-21 00:04:35 UTC (rev 2739)
+++ trunk/tcl/target/ti_dm6446.cfg	2009-09-21 00:37:58 UTC (rev 2740)
@@ -68,6 +68,12 @@
 target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
 $_TARGETNAME configure -work-area-phys 0x0000a000 -work-area-size 0x2000
 
+# be absolutely certain the JTAG clock will work with the worst-case
+# CLKIN = 20 MHz (best case: 30 MHz) even when no bootloader turns
+# on the PLL and starts using it.  OK to speed up after clock setup.
+jtag_rclk 1500
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1500 }
+
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable