openocd-commit — OpenOCD commit maling list - read only

[Openocd-svn] r2814 - trunk/src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-10-07 14:05:37 +0200 (Wed, 07 Oct 2009)
New Revision: 2814

Modified:
   trunk/src/target/arm11.c
Log:
add timeouts and fix syntax error handling of mrc/mcr commands.

Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c	2009-10-07 11:03:56 UTC (rev 2813)
+++ trunk/src/target/arm11.c	2009-10-07 12:05:37 UTC (rev 2814)
@@ -768,12 +768,29 @@
 
 	uint32_t dscr;
 
+	int i = 0;
 	while (1)
 	{
 		CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 
 		if (dscr & ARM11_DSCR_CORE_HALTED)
 			break;
+
+
+		long long then = 0;
+		if (i == 1000)
+		{
+			then = timeval_ms();
+		}
+		if (i >= 1000)
+		{
+			if ((timeval_ms()-then) > 1000)
+			{
+				LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+				return ERROR_FAIL;
+			}
+		}
+		i++;
 	}
 
 	arm11_on_enter_debug_state(arm11);
@@ -865,6 +882,7 @@
 
 	CHECK_RETVAL(jtag_execute_queue());
 
+	int i = 0;
 	while (1)
 	{
 		uint32_t dscr;
@@ -875,6 +893,22 @@
 
 		if (dscr & ARM11_DSCR_CORE_RESTARTED)
 			break;
+
+
+		long long then = 0;
+		if (i == 1000)
+		{
+			then = timeval_ms();
+		}
+		if (i >= 1000)
+		{
+			if ((timeval_ms()-then) > 1000)
+			{
+				LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+				return ERROR_FAIL;
+			}
+		}
+		i++;
 	}
 
 	if (!debug_execution)
@@ -1088,10 +1122,8 @@
 
 		CHECK_RETVAL(jtag_execute_queue());
 
-		/** \todo TODO: add a timeout */
-
 		/* wait for halt */
-
+		int i = 0;
 		while (1)
 		{
 			uint32_t dscr;
@@ -1103,6 +1135,21 @@
 			if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
 				(ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
 				break;
+
+			long long then = 0;
+			if (i == 1000)
+			{
+				then = timeval_ms();
+			}
+			if (i >= 1000)
+			{
+				if ((timeval_ms()-then) > 1000)
+				{
+					LOG_WARNING("Timeout (1000ms) waiting for instructions to complete");
+					return ERROR_FAIL;
+				}
+			}
+			i++;
 		}
 
 		/* clear breakpoint */
@@ -1936,9 +1983,6 @@
 	0xFFFFFFFF,		/* value */
 };
 
-const char arm11_mrc_syntax[] = "Syntax: mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.";
-const char arm11_mcr_syntax[] = "Syntax: mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.";
-
 arm11_common_t * arm11_find_target(const char * arg)
 {
 	jtag_tap_t *	tap;
@@ -1966,18 +2010,16 @@
 {
 	if (argc != (read ? 6 : 7))
 	{
-		LOG_ERROR("Invalid number of arguments. %s", read ? arm11_mrc_syntax : arm11_mcr_syntax);
-		return -1;
+		LOG_ERROR("Invalid number of arguments.");
+		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
 	arm11_common_t * arm11 = arm11_find_target(args[0]);
 
 	if (!arm11)
 	{
-		LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device. %s",
-			read ? arm11_mrc_syntax : arm11_mcr_syntax);
-
-		return -1;
+		LOG_ERROR("Parameter 1 is not a the JTAG chain position of an ARM11 device.");
+		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
 	if (arm11->target->state != TARGET_HALTED)
@@ -1994,11 +2036,10 @@
 
 		if (values[i] > arm11_coproc_instruction_limits[i])
 		{
-			LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max). %s",
+			LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max).",
 				  (long)(i + 2),
-				  arm11_coproc_instruction_limits[i],
-				read ? arm11_mrc_syntax : arm11_mcr_syntax);
-			return -1;
+				  arm11_coproc_instruction_limits[i]);
+			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 	}
 
@@ -2072,7 +2113,7 @@
 
 	register_command(cmd_ctx, top_cmd, "mcr",
 			arm11_handle_mcr, COMMAND_ANY,
-			"Write Coprocessor register");
+			"Write Coprocessor register. mcr <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2> <32bit value to write>. All parameters are numbers only.");
 
 	mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
 			NULL, COMMAND_ANY, NULL);
@@ -2087,7 +2128,7 @@
 
 	register_command(cmd_ctx, top_cmd, "mrc",
 			arm11_handle_mrc, COMMAND_ANY,
-			"Read Coprocessor register");
+			"Read Coprocessor register. mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.");
 	register_command(cmd_ctx, top_cmd, "no_increment",
 			arm11_handle_bool_memrw_no_increment, COMMAND_ANY,
 			"Don't increment address on multi-read/-write"

[Openocd-svn] r2813 - trunk/src

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-10-07 13:03:56 +0200 (Wed, 07 Oct 2009)
New Revision: 2813

Modified:
   trunk/src/ecosboard.c
Log:
increase pause before reboot so web interface remains responsive when issuing a reboot of zy1000

Modified: trunk/src/ecosboard.c
===================================================================
--- trunk/src/ecosboard.c	2009-10-07 11:03:01 UTC (rev 2812)
+++ trunk/src/ecosboard.c	2009-10-07 11:03:56 UTC (rev 2813)
@@ -155,8 +155,8 @@
 static void zylinjtag_reboot(cyg_addrword_t data)
 {
 	serialLog = true;
-	diag_printf("Rebooting in 100 ticks..\n");
-	cyg_thread_delay(100);
+	diag_printf("Rebooting in 500 ticks..\n");
+	cyg_thread_delay(500);
 	diag_printf("Unmounting /config..\n");
 	umount("/config");
 	diag_printf("Rebooting..\n");

[Openocd-svn] r2812 - trunk/src/jtag

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-10-07 13:03:01 +0200 (Wed, 07 Oct 2009)
New Revision: 2812

Modified:
   trunk/src/jtag/core.c
Log:
Do not check ir capture if there is no IDCODE

Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-10-07 06:56:45 UTC (rev 2811)
+++ trunk/src/jtag/core.c	2009-10-07 11:03:01 UTC (rev 2812)
@@ -1108,19 +1108,22 @@
 			break;
 		}
 
-		/* Validate the two LSBs, which must be 01 per JTAG spec.
-		 * REVISIT we might be able to verify some MSBs too, using
-		 * ircapture/irmask attributes.
-		 */
-		val = buf_get_u32(ir_test, chain_pos, tap->ir_length);
-		if ((val & 0x3) != 1) {
-			LOG_ERROR("%s: IR capture error; saw 0x%0*x not 0x..1",
-					jtag_tap_name(tap),
-					(tap->ir_length + 7) / tap->ir_length,
-					val);
+		if (tap->hasidcode)
+		{
+			/* Validate the two LSBs, which must be 01 per JTAG spec.
+			 * REVISIT we might be able to verify some MSBs too, using
+			 * ircapture/irmask attributes.
+			 */
+			val = buf_get_u32(ir_test, chain_pos, tap->ir_length);
+			if ((val & 0x3) != 1) {
+				LOG_ERROR("%s: IR capture error; saw 0x%0*x not 0x..1",
+						jtag_tap_name(tap),
+						(tap->ir_length + 7) / tap->ir_length,
+						val);
 
-			retval = ERROR_JTAG_INIT_FAILED;
-			goto done;
+				retval = ERROR_JTAG_INIT_FAILED;
+				goto done;
+			}
 		}
 		LOG_DEBUG("%s: IR capture 0x%0*x", jtag_tap_name(tap),
 				(tap->ir_length + 7) / tap->ir_length, val);

[Openocd-svn] r2811 - in zy1000/trunk: build/tcl snapshots

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-10-07 08:56:45 +0200 (Wed, 07 Oct 2009)
New Revision: 2811

Modified:
   zy1000/trunk/build/tcl/index.tcl
   zy1000/trunk/build/tcl/preconfig.tcl
   zy1000/trunk/build/tcl/reload.tcl
   zy1000/trunk/build/tcl/upgrade.tcl
   zy1000/trunk/build/tcl/zy1000.tcl
   zy1000/trunk/snapshots/discover.zip
   zy1000/trunk/snapshots/jimtcl.zip
Log:
zy1000 1.55 snapshot

Modified: zy1000/trunk/build/tcl/index.tcl
===================================================================
--- zy1000/trunk/build/tcl/index.tcl	2009-10-07 06:53:44 UTC (rev 2810)
+++ zy1000/trunk/build/tcl/index.tcl	2009-10-07 06:56:45 UTC (rev 2811)
@@ -246,7 +246,7 @@
 			<tcl>
 				if {[string compare $form_action "Reboot ZY1000"]==0} {
 					append buffer "Rebooting ZY1000..."
-					reboot
+					zy1000_reboot
 				}
 			</tcl>
 

Modified: zy1000/trunk/build/tcl/preconfig.tcl
===================================================================
--- zy1000/trunk/build/tcl/preconfig.tcl	2009-10-07 06:53:44 UTC (rev 2810)
+++ zy1000/trunk/build/tcl/preconfig.tcl	2009-10-07 06:56:45 UTC (rev 2811)
@@ -145,7 +145,7 @@
 			if {[string compare $form_action "Select and reload"]==0} {
 				capture "trunc /config/settings/openocd.cfg"
 				capture "append_file /config/settings/openocd.cfg script $form_target"
-				reboot 
+				zy1000_reboot 
 			}
 			
 			set form_target [load_target] 

Modified: zy1000/trunk/build/tcl/reload.tcl
===================================================================
--- zy1000/trunk/build/tcl/reload.tcl	2009-10-07 06:53:44 UTC (rev 2810)
+++ zy1000/trunk/build/tcl/reload.tcl	2009-10-07 06:56:45 UTC (rev 2811)
@@ -151,7 +151,7 @@
 	
 				if {[string compare $form_action "Reload"]==0} {
 					append buffer "Reloading Config Scripts...<p>"
-					reboot
+					zy1000_reboot
 				}
 			</tcl>
 			<form enctype="multipart/form-data" action="reload.tcl" method="post">

Modified: zy1000/trunk/build/tcl/upgrade.tcl
===================================================================
--- zy1000/trunk/build/tcl/upgrade.tcl	2009-10-07 06:53:44 UTC (rev 2810)
+++ zy1000/trunk/build/tcl/upgrade.tcl	2009-10-07 06:56:45 UTC (rev 2811)
@@ -194,7 +194,7 @@
 					if {[check_firmware $form_filecontent]} {
 						write_firmware $form_filecontent
 						append buffer "<br><div style='font-size:14px;'>Upgraded Zylin JTAG, rebooting (wait ca. 30 seconds)...</div><br>"
-						reboot
+						zy1000_reboot
 					} else {
 						append buffer "<br>Not a valid Zylin JTAG firmware file.<br>"
 					}
@@ -208,7 +208,7 @@
 						}
 					}				
 					rmdir /config/settings
-					reboot
+					zy1000_reboot
 					append buffer "Restoring factory settings (wait ca. 30 seconds)...<br>"
 				} else {
 					append buffer {<div style="font-size:14px;">Upgrade Zylin JTAG firmware + reboot. </div><p>}

Modified: zy1000/trunk/build/tcl/zy1000.tcl
===================================================================
--- zy1000/trunk/build/tcl/zy1000.tcl	2009-10-07 06:53:44 UTC (rev 2810)
+++ zy1000/trunk/build/tcl/zy1000.tcl	2009-10-07 06:56:45 UTC (rev 2811)
@@ -228,13 +228,13 @@
 					$fp puts -nonewline "$form_ip,$form_mask,$form_gateway"
 					$fp close
 					append buffer "Set $form_ip,$form_mask,$form_gateway to $form_filename. Reloading settings..."
-					reboot
+					zy1000_reboot
 				} elseif {[string compare $form_action "Use DHCP"]==0} {
 					set fp [aio.open $form_filename w];
 					$fp puts -nonewline ""
 					$fp close
 					append buffer "Using DHCP. Reloading settings..."
-					reboot
+					zy1000_reboot
 				} else {
 				</tcl>
 					<form action="zy1000.tcl" method="post"> 

Modified: zy1000/trunk/snapshots/discover.zip
===================================================================
(Binary files differ)

Modified: zy1000/trunk/snapshots/jimtcl.zip
===================================================================
(Binary files differ)

[Openocd-svn] r2810 - trunk/src/jtag/zy1000

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-10-07 08:53:44 +0200 (Wed, 07 Oct 2009)
New Revision: 2810

Modified:
   trunk/src/jtag/zy1000/zy1000.c
Log:
1.55 snapshot

Modified: trunk/src/jtag/zy1000/zy1000.c
===================================================================
--- trunk/src/jtag/zy1000/zy1000.c	2009-10-07 05:43:05 UTC (rev 2809)
+++ trunk/src/jtag/zy1000/zy1000.c	2009-10-07 06:53:44 UTC (rev 2810)
@@ -28,7 +28,7 @@
 #include <cyg/hal/hal_diag.h>
 
 
-#define ZYLIN_VERSION "1.54"
+#define ZYLIN_VERSION "1.55"
 #define ZYLIN_DATE __DATE__
 #define ZYLIN_TIME __TIME__
 #define ZYLIN_OPENOCD "$Revision$"

[Openocd-svn] r2809 - in trunk: . doc/manual src tools

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-10-07 07:43:05 +0200 (Wed, 07 Oct 2009)
New Revision: 2809

Modified:
   trunk/configure.in
   trunk/doc/manual/release.txt
   trunk/guess-rev.sh
   trunk/src/Makefile.am
   trunk/src/openocd.c
   trunk/tools/release.sh
Log:
Change version labels to work better with GIT

 - The guess-rev.sh script is now a tweaked version of "setlocalversion" as
   seen in Linux, U-Boot, and various other projects.  When it finds source
   control support (git, hg, svn) it uses IDs from there.  Else (specific
   to this project) it reports itself as "-snapshot", e.g. from gitweb.

   I verified this new "guess-rev.sh" script runs under Cygwin.

 - Also update the generic version strings to be like "0.3.0-dev" (during
   development) instead of the very long "0.3.0-in-development".  These also
   show up in the PDF docs.  For better tracking, we might eventually change
   these strings to include the version IDs too.

 - Change the startup banner version strings so they include the guess-rev
   output.  Development and release versions with GIT will be like

    Open On-Chip Debugger 0.3.0-dev-00282-g7191a4f-dirty (2009-10-05-20:57) 
    Open On-Chip Debugger 0.3.0 (2009-10-05-20:57) 

   instead of the previous SVN-specific (even when using git-svn!)

    Open On-Chip Debugger 0.3.0-in-development (2009-10-05-01:39) svn:exported
    Open On-Chip Debugger 0.3.0 (2009-10-05-01:39) Release



Modified: trunk/configure.in
===================================================================
--- trunk/configure.in	2009-10-06 22:56:52 UTC (rev 2808)
+++ trunk/configure.in	2009-10-07 05:43:05 UTC (rev 2809)
@@ -1,5 +1,5 @@
 AC_PREREQ(2.60)
-AC_INIT([openocd], [0.3.0-in-development],
+AC_INIT([openocd], [0.3.0-dev],
   [OpenOCD Mailing List <ope...@li...>])
 AC_CONFIG_SRCDIR([src/openocd.c])
 

Modified: trunk/doc/manual/release.txt
===================================================================
--- trunk/doc/manual/release.txt	2009-10-06 22:56:52 UTC (rev 2808)
+++ trunk/doc/manual/release.txt	2009-10-07 05:43:05 UTC (rev 2809)
@@ -62,9 +62,9 @@
 @subsection releaseversiontags Version Tags
 
 After these required numeric components, the version string may contain
-one or more <i>version tags</i>, such as '-rc1' or '-in-development'.
+one or more <i>version tags</i>, such as '-rc1' or '-dev'.
 
-The trunk and all branches should have the tag '-in-development' in
+The trunk and all branches should have the tag '-dev' in
 their version number.  This tag helps developers identify reports
 created from the Subversion repository, and it can be detected and
 manipulated by the release script.  Specifically, this tag will be
@@ -218,7 +218,7 @@
     - This material should be produced during the development cycle.
     - Add a new item for each @c NEWS-worthy contribution, when committed.
   -# bump library version if our API changed (not yet required)
-  -# Remove -in-development tag from package version:
+  -# Remove -dev tag from package version in configure.in:
     - For major/minor releases, remove version tag from trunk, @a or
     - For bug-fix releases, remove version tag from release branch.
 -# Branch or tag the required tree in the Subversion repository:

Modified: trunk/guess-rev.sh
===================================================================
--- trunk/guess-rev.sh	2009-10-06 22:56:52 UTC (rev 2808)
+++ trunk/guess-rev.sh	2009-10-07 05:43:05 UTC (rev 2809)
@@ -1,8 +1,83 @@
-#!/bin/bash
+#!/bin/sh
 #
+# This scripts adds local version information from the version
+# control systems git, mercurial (hg) and subversion (svn).
+#
+# Copied from Linux 2.6.32 scripts/setlocalversion and modified
+# slightly to work better for OpenOCD.
+#
 
-REV=unknown
+usage() {
+	echo "Usage: $0 [srctree]" >&2
+	exit 1
+}
 
-which svnversion > /dev/null 2>&1 && REV=`svnversion -n "$1"`
+cd "${1:-.}" || usage
 
-echo -n $REV
+# Check for git and a git repo.
+if head=`git rev-parse --verify --short HEAD 2>/dev/null`; then
+
+	# If we are at a tagged commit (like "v2.6.30-rc6"), we ignore it,
+	# because this version is defined in the top level Makefile.
+	if [ -z "`git describe --exact-match 2>/dev/null`" ]; then
+
+		# If we are past a tagged commit (like "v2.6.30-rc5-302-g72357d5"),
+		# we pretty print it.
+		if atag="`git describe 2>/dev/null`"; then
+			echo "$atag" | awk -F- '{printf("-%05d-%s", $(NF-1),$(NF))}'
+
+		# If we don't have a tag at all we print -g{commitish}.
+		else
+			printf '%s%s' -g $head
+		fi
+	fi
+
+	# Is this git on svn?
+	if git config --get svn-remote.svn.url >/dev/null; then
+	        printf -- '-svn%s' "`git svn find-rev $head`"
+	fi
+
+	# Update index only on r/w media
+	[ -w . ] && git update-index --refresh --unmerged > /dev/null
+
+	# Check for uncommitted changes
+	if git diff-index --name-only HEAD | grep -v "^scripts/package" \
+	    | read dummy; then
+		printf '%s' -dirty
+	fi
+
+	# All done with git
+	exit
+fi
+
+# Check for mercurial and a mercurial repo.
+if hgid=`hg id 2>/dev/null`; then
+	tag=`printf '%s' "$hgid" | cut -d' ' -f2`
+
+	# Do we have an untagged version?
+	if [ -z "$tag" -o "$tag" = tip ]; then
+		id=`printf '%s' "$hgid" | sed 's/[+ ].*//'`
+		printf '%s%s' -hg "$id"
+	fi
+
+	# Are there uncommitted changes?
+	# These are represented by + after the changeset id.
+	case "$hgid" in
+		*+|*+\ *) printf '%s' -dirty ;;
+	esac
+
+	# All done with mercurial
+	exit
+fi
+
+# Check for svn and a svn repo.
+if rev=`svn info 2>/dev/null | grep '^Last Changed Rev'`; then
+	rev=`echo $rev | awk '{print $NF}'`
+	printf -- '-svn%s' "$rev"
+
+	# All done with svn
+	exit
+fi
+
+# There's no reecognized repository; we must be a snapshot.
+printf -- '-snapshot'

Modified: trunk/src/Makefile.am
===================================================================
--- trunk/src/Makefile.am	2009-10-06 22:56:52 UTC (rev 2808)
+++ trunk/src/Makefile.am	2009-10-07 05:43:05 UTC (rev 2809)
@@ -28,10 +28,12 @@
 
 libopenocd_la_CPPFLAGS = -DPKGBLDDATE=\"`date +%F-%R`\"
 
+# banner output includes RELSTR appended to $VERSION from the configure script
+# guess-rev.sh returns either a repository version ID or "-snapshot"
 if RELEASE
-libopenocd_la_CPPFLAGS += -DRELSTR=\"Release\" -DPKGBLDREV=\"\"
+libopenocd_la_CPPFLAGS += -DRELSTR=\"\"
 else
-libopenocd_la_CPPFLAGS += -DRELSTR=\"svn:\" -DPKGBLDREV=\"`$(top_srcdir)/guess-rev.sh $(top_srcdir)`\"
+libopenocd_la_CPPFLAGS += -DRELSTR=\"`$(top_srcdir)/guess-rev.sh $(top_srcdir)`\"
 endif
 
 # add default CPPFLAGS

Modified: trunk/src/openocd.c
===================================================================
--- trunk/src/openocd.c	2009-10-06 22:56:52 UTC (rev 2808)
+++ trunk/src/openocd.c	2009-10-07 05:43:05 UTC (rev 2809)
@@ -49,7 +49,7 @@
 
 
 #define OPENOCD_VERSION \
-		"Open On-Chip Debugger " VERSION " (" PKGBLDDATE ") " RELSTR PKGBLDREV
+		"Open On-Chip Debugger " VERSION RELSTR " (" PKGBLDDATE ")"
 
 static void print_version(void)
 {

Modified: trunk/tools/release.sh
===================================================================
--- trunk/tools/release.sh	2009-10-06 22:56:52 UTC (rev 2808)
+++ trunk/tools/release.sh	2009-10-07 05:43:05 UTC (rev 2809)
@@ -97,7 +97,7 @@
 
 	PACKAGE_VERSION="$(package_info_load_version)"
 	[ "${RELEASE_VERSION}" ] || \
-		RELEASE_VERSION=${PACKAGE_VERSION/-in-development/}
+		RELEASE_VERSION=${PACKAGE_VERSION/-dev/}
 
 	[ "${PACKAGE_NAME}" -a "${PACKAGE_VERSION}" ] || \
 		die "package information is missing from configure script"
@@ -427,7 +427,7 @@
 	package_info_load
 	svn_setup_load
 
-	[ "${PACKAGE_VERSION/in-development/}" = "${PACKAGE_VERSION}" ] || \
+	[ "${PACKAGE_VERSION/dev/}" = "${PACKAGE_VERSION}" ] || \
 		die "'${PACKAGE_NAME}-${PACKAGE_VERSION}' cannot be released"
 
 	[ "${PACKAGE_VERSION%.0}" = "${PACKAGE_VERSION}" ] || \
@@ -437,7 +437,7 @@
 
 
 do_release_step_prep() {
-	do_version tag remove in-development
+	do_version tag remove dev
 	# reset RELEASE_VERSION now to allow release version to be detected
 	export RELEASE_VERSION=
 }
@@ -447,7 +447,7 @@
 	local TYPE="$1"
 	echo "Bump ${TYPE} version and add tag:"
 	do_version_bump ${TYPE}
-	do_version_tag_add in-development
+	do_version_tag_add dev
 }
 do_release_step_branch() {
 	do_svn_switch "${PACKAGE_BRANCH}"

[Openocd-svn] r2808 - trunk/tcl/board

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-10-07 00:56:52 +0200 (Wed, 07 Oct 2009)
New Revision: 2808

Added:
   trunk/tcl/board/dm6446evm.cfg
Log:
Add basic support for DM6446 EVM board.


Added: trunk/tcl/board/dm6446evm.cfg
===================================================================
--- trunk/tcl/board/dm6446evm.cfg	2009-10-06 22:55:46 UTC (rev 2807)
+++ trunk/tcl/board/dm6446evm.cfg	2009-10-06 22:56:52 UTC (rev 2808)
@@ -0,0 +1,74 @@
+# DM6446 EVM board
+#   http://focus.ti.com/docs/toolsw/folders/print/tmdsevm6446.html
+#   http://c6000.spectrumdigital.com/davincievm/
+# EVM is just the board; buy that at Spectrum.
+# The "kit" from TI also has: video camera, LCD video monitor, more.
+
+source [find target/ti_dm6446.cfg]
+
+# J4 controls what CS2 hooks up to, usually NOR or NAND flash.
+# S3.1/S3.2 controls boot mode, which may force J4 and S3.3 settings.
+# S3.3 controls AEMIF bus width.
+
+if { [info exists J4_OPTION] } {
+	# NOR, NAND, SRAM, ...
+	set CS2_MODE $J4_OPTION
+} else {
+	set CS2_MODE ""
+}
+
+# ARM boot:
+#  S3.1 = 0, S3.2 = 0	==> ROM/UBL boot via NAND (J4 == NAND)
+#  S3.1 = 1, S3.2 = 0	==> AEMIF boot (J4 == NOR or SRAM)
+#  S3.1 = 0, S3.2 = 1	==> ROM/UBL boot via HPI
+#  S3.1 = 1, S3.2 = 1	==> ROM/UBL boot via UART (J4 == don't care)
+# AEMIF bus width:
+#  S3.3 = 0		==> 8 bit bus width
+#  S3.3 = 1		==> 16 bit bus width
+# DSP boot:
+#  S3.4 = 0		==> controlled by ARM
+
+if { $CS2_MODE == "NOR" } {
+	# 16 Mbytes address space; 16 bit bus width
+	# (older boards used 32MB parts, with upper 16 MB unusable)
+	flash bank cfi 0x02000000 0x01000000 2 2 $_TARGETNAME
+	proc flashprobe {} { flash probe 0 }
+} elseif { $CS2_MODE == "NAND" } {
+	# 64 Mbyte small page; 8 bit bus width
+	nand device davinci $_TARGETNAME 0x02000000 hwecc1 0x01e00000
+	proc flashprobe {} { nand probe 0 }
+} elseif { $CS2_MODE == "SRAM" } {
+	# 4 Mbyte address space; 16 bit bus width
+	# loaded via JTAG or HPI
+	proc flashprobe {} {}
+} else {
+	# maybe it's HPI boot?  can't tell...
+	echo "WARNING:  CS2/flash configuration not recognized"
+	proc flashprobe {} {}
+}
+
+# NOTE:  disable or replace this call to dm6446evm_init if you're
+# debugging new UBL code from SRAM (for NAND boot).
+$_TARGETNAME configure -event reset-init { dm6446evm_init }
+
+#
+# This post-reset init is called when the MMU isn't active, all IRQs
+# are disabled, etc.  It should do most of what a UBL does, except for
+# loading code (like U-Boot) into DRAM and running it.
+#
+proc dm6446evm_init {} {
+
+	puts "Initialize DM6446 EVM board"
+
+	# FIXME initialize everything:
+	#  - PLL1
+	#  - PLL2
+	#  - PINMUX
+	#  - PSC
+	#  - DDR
+	#  - AEMIF
+	#  - UART0
+	#  - icache
+
+	flashprobe
+}

[Openocd-svn] r2807 - trunk/src/target

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-10-07 00:55:46 +0200 (Wed, 07 Oct 2009)
New Revision: 2807

Modified:
   trunk/src/target/embeddedice.c
Log:
Dragonite has the same EICE affliction as feroceon.

From: Nicolas Pitre <ni...@fl...>


Modified: trunk/src/target/embeddedice.c
===================================================================
--- trunk/src/target/embeddedice.c	2009-10-06 22:55:04 UTC (rev 2806)
+++ trunk/src/target/embeddedice.c	2009-10-06 22:55:46 UTC (rev 2807)
@@ -264,7 +264,8 @@
 			 * in some unusual bits.  Let feroceon.c validate it
 			 * and do the appropriate setup itself.
 			 */
-			if (strcmp(target_get_name(target), "feroceon") == 0)
+			if (strcmp(target_get_name(target), "feroceon") == 0 ||
+			    strcmp(target_get_name(target), "dragonite") == 0)
 				break;
 			LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8" PRIx32 ")", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 	}

[Openocd-svn] r2806 - trunk/tcl/target

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-10-07 00:55:04 +0200 (Wed, 07 Oct 2009)
New Revision: 2806

Added:
   trunk/tcl/target/dragonite.cfg
Log:
Dragonite target script

From: Nicolas Pitre <ni...@fl...>


Added: trunk/tcl/target/dragonite.cfg
===================================================================
--- trunk/tcl/target/dragonite.cfg	2009-10-06 08:10:57 UTC (rev 2805)
+++ trunk/tcl/target/dragonite.cfg	2009-10-06 22:55:04 UTC (rev 2806)
@@ -0,0 +1,31 @@
+######################################
+# Target:    Marvell Dragonite CPU core
+######################################
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME dragonite
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x121003d3
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME dragonite -endian $_ENDIAN -chain-position $_TARGETNAME
+
+reset_config trst_and_srst
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+

[Openocd-svn] r2805 - in trunk/src: helper jtag

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-10-06 10:10:57 +0200 (Tue, 06 Oct 2009)
New Revision: 2805

Modified:
   trunk/src/helper/startup.tcl
   trunk/src/jtag/core.c
   trunk/src/jtag/jtag.h
   trunk/src/jtag/tcl.c
Log:
Introduced jtag_init and "jtag arp_init" to allow target scripts more control over how OpenOCD starts up and initializes the target.

Modified: trunk/src/helper/startup.tcl
===================================================================
--- trunk/src/helper/startup.tcl	2009-10-06 08:10:05 UTC (rev 2804)
+++ trunk/src/helper/startup.tcl	2009-10-06 08:10:57 UTC (rev 2805)
@@ -359,3 +359,13 @@
 	} result
 	return $result
 }
+
+
+# Executed during "init". Can be implemented by target script 
+# tar
+proc jtag_init {} {
+	if {[catch {jtag arp_init} err]!=0} {
+		# try resetting additionally
+		jtag arp_init-reset
+	}
+}
\ No newline at end of file

Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-10-06 08:10:05 UTC (rev 2804)
+++ trunk/src/jtag/core.c	2009-10-06 08:10:57 UTC (rev 2805)
@@ -1,16 +1,16 @@
 /***************************************************************************
- *   Copyright (C) 2005 by Dominic Rath                                    *
- *   Dom...@gm...                                                   *
+ *   Copyright (C) 2009 Zachary T Welch                                    *
+ *   zw...@su...                                                  *
  *                                                                         *
- *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
+ *   Copyright (C) 2007,2008,2009 Øyvind Harboe                            *
  *   oyv...@zy...                                               *
  *                                                                         *
  *   Copyright (C) 2009 SoftPLC Corporation                                *
  *       http://softplc.com                                                *
  *   di...@so...                                                      *
  *                                                                         *
- *   Copyright (C) 2009 Zachary T Welch                                    *
- *   zw...@su...                                                  *
+ *   Copyright (C) 2005 by Dominic Rath                                    *
+ *   Dom...@gm...                                                   *
  *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
@@ -1230,7 +1230,7 @@
 	return ERROR_OK;
 }
 
-static int jtag_init_inner(struct command_context_s *cmd_ctx)
+int jtag_init_inner(struct command_context_s *cmd_ctx)
 {
 	jtag_tap_t *tap;
 	int retval;
@@ -1334,11 +1334,11 @@
 	int retval;
 	if ((retval = jtag_interface_init(cmd_ctx)) != ERROR_OK)
 		return retval;
-	if (jtag_init_inner(cmd_ctx) == ERROR_OK)
-	{
-		return ERROR_OK;
-	}
-	return jtag_init_reset(cmd_ctx);
+
+	if (Jim_Eval_Named(interp, "jtag_init", __FILE__, __LINE__) != JIM_OK)
+		return ERROR_FAIL;
+
+	return ERROR_OK;
 }
 
 unsigned jtag_get_speed_khz(void)

Modified: trunk/src/jtag/jtag.h
===================================================================
--- trunk/src/jtag/jtag.h	2009-10-06 08:10:05 UTC (rev 2804)
+++ trunk/src/jtag/jtag.h	2009-10-06 08:10:57 UTC (rev 2805)
@@ -335,8 +335,9 @@
 extern int  jtag_init(struct command_context_s* cmd_ctx);
 
 /// reset, then initialize JTAG chain
-extern int  jtag_init_reset(struct command_context_s* cmd_ctx);
-extern int  jtag_register_commands(struct command_context_s* cmd_ctx);
+extern int jtag_init_reset(struct command_context_s* cmd_ctx);
+extern int jtag_register_commands(struct command_context_s* cmd_ctx);
+extern int jtag_init_inner(struct command_context_s *cmd_ctx);
 
 /**
  * @file

Modified: trunk/src/jtag/tcl.c
===================================================================
--- trunk/src/jtag/tcl.c	2009-10-06 08:10:05 UTC (rev 2804)
+++ trunk/src/jtag/tcl.c	2009-10-06 08:10:57 UTC (rev 2805)
@@ -410,6 +410,7 @@
 
 	enum {
 		JTAG_CMD_INTERFACE,
+		JTAG_CMD_INIT,
 		JTAG_CMD_INIT_RESET,
 		JTAG_CMD_NEWTAP,
 		JTAG_CMD_TAPENABLE,
@@ -422,6 +423,7 @@
 
 	const Jim_Nvp jtag_cmds[] = {
 		{ .name = "interface"     , .value = JTAG_CMD_INTERFACE },
+		{ .name = "arp_init"      , .value = JTAG_CMD_INIT },
 		{ .name = "arp_init-reset", .value = JTAG_CMD_INIT_RESET },
 		{ .name = "newtap"        , .value = JTAG_CMD_NEWTAP },
 		{ .name = "tapisenabled"     , .value = JTAG_CMD_TAPISENABLED },
@@ -455,6 +457,17 @@
 		}
 		Jim_SetResultString(goi.interp, jtag_interface->name, -1);
 		return JIM_OK;
+	case JTAG_CMD_INIT:
+		if (goi.argc != 0) {
+			Jim_WrongNumArgs(goi.interp, 1, goi.argv-1, "(no params)");
+			return JIM_ERR;
+		}
+		e = jtag_init_inner(context);
+		if (e != ERROR_OK) {
+			Jim_SetResult_sprintf(goi.interp, "error: %d", e);
+			return JIM_ERR;
+		}
+		return JIM_OK;
 	case JTAG_CMD_INIT_RESET:
 		if (goi.argc != 0) {
 			Jim_WrongNumArgs(goi.interp, 1, goi.argv-1, "(no params)");

[Openocd-svn] r2804 - trunk/tcl/board

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-10-06 10:10:05 +0200 (Tue, 06 Oct 2009)
New Revision: 2804

Modified:
   trunk/tcl/board/zy1000.cfg
Log:
stop using targetnum

Modified: trunk/tcl/board/zy1000.cfg
===================================================================
--- trunk/tcl/board/zy1000.cfg	2009-10-06 05:28:30 UTC (rev 2803)
+++ trunk/tcl/board/zy1000.cfg	2009-10-06 08:10:05 UTC (rev 2804)
@@ -38,7 +38,7 @@
 arm7_9 fast_memory_access enable
 arm7_9 dcc_downloads enable
 
-flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
+flash bank ecosflash 0x01000000 0x200000 2 2 $_TARGETNAME ecos/at91eb40a.elf
 $_TARGETNAME configure -event reset-init {
 	# Set up chip selects & timings
 	mww 0xFFE00000 0x0100273D

[Openocd-svn] r2803 - trunk

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-10-06 07:28:30 +0200 (Tue, 06 Oct 2009)
New Revision: 2803

Modified:
   trunk/.gitignore
Log:
Take "patches" out of .gitignore ... Win32 is case-crazy


Modified: trunk/.gitignore
===================================================================
--- trunk/.gitignore	2009-10-05 23:45:14 UTC (rev 2802)
+++ trunk/.gitignore	2009-10-06 05:28:30 UTC (rev 2803)
@@ -47,6 +47,3 @@
 stamp-vti
 INSTALL
 NOTES
-
-# quilt support
-patches

[Openocd-svn] r2802 - trunk

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-10-06 01:45:14 +0200 (Tue, 06 Oct 2009)
New Revision: 2802

Added:
   trunk/.gitignore
Log:
Add initial ".gitignore".


Added: trunk/.gitignore
===================================================================
--- trunk/.gitignore	2009-10-05 08:23:33 UTC (rev 2801)
+++ trunk/.gitignore	2009-10-05 23:45:14 UTC (rev 2802)
@@ -0,0 +1,52 @@
+# stuff "git status" should ignore
+
+# build output
+.*
+*.o
+*.a
+*.lo
+*.la
+*.in
+startup_tcl.c
+bin2char
+doc/openocd.aux
+doc/openocd.cp
+doc/openocd.cps
+doc/openocd.fn
+doc/openocd.fns
+doc/openocd.html
+doc/openocd.info
+doc/openocd.ky
+doc/openocd.log
+doc/openocd.pdf
+doc/openocd.pg
+doc/openocd.toc
+doc/openocd.tp
+doc/openocd.vr
+doc/texinfo.tex
+doc/version.texi
+src/openocd
+
+# configure/autotools output
+aclocal.m4
+autom4te.cache
+compile
+config.*
+configure
+depcomp
+doxygen
+doxygen.log
+Doxyfile
+install-sh
+libtool
+ltmain.sh
+Makefile
+mdate-sh
+missing
+stamp-h1
+stamp-vti
+INSTALL
+NOTES
+
+# quilt support
+patches

[Openocd-svn] r2800 - in trunk: doc src/jtag tcl/target

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-10-05 10:20:28 +0200 (Mon, 05 Oct 2009)
New Revision: 2800

Modified:
   trunk/doc/openocd.texi
   trunk/src/jtag/core.c
   trunk/src/jtag/jtag.h
   trunk/src/jtag/tcl.c
   trunk/tcl/target/ti_dm355.cfg
   trunk/tcl/target/ti_dm365.cfg
   trunk/tcl/target/ti_dm6446.cfg
Log:
Add a new JTAG "setup" event; use for better DaVinci ICEpick support.

The model is that this fires after scanchain verification, when it's
safe to call "jtag tapenable $TAPNAME".  So it will fire as part of
non-error paths of "init" and "reset" command processing.  However it
will *NOT* trigger during "jtag_reset" processing, which skips all
scan chain verification, or after verification errors.

ALSO:
 - switch DaVinci chips to use this new mechanism
 - log TAP activation/deactivation, since their IDCODEs aren't verified
 - unify "enum jtag_event" scripted event notifications
 - remove duplicative JTAG_TAP_EVENT_POST_RESET


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-10-05 08:18:17 UTC (rev 2799)
+++ trunk/doc/openocd.texi	2009-10-05 08:20:28 UTC (rev 2800)
@@ -2428,12 +2428,18 @@
 @itemize @bullet
 @item @b{post-reset}
 @* The TAP has just completed a JTAG reset.
-For the first such handler called, the tap is still
-in the JTAG @sc{reset} state.
+The tap may still be in the JTAG @sc{reset} state.
+Handlers for these events might perform initialization sequences
+such as issuing TCK cycles, TMS sequences to ensure
+exit from the ARM SWD mode, and more.
+
 Because the scan chain has not yet been verified, handlers for these events
 @emph{should not issue commands which scan the JTAG IR or DR registers}
 of any particular target.
 @b{NOTE:} As this is written (September 2009), nothing prevents such access.
+@item @b{setup}
+@* The scan chain has been reset and verified.
+This handler may enable TAPs as needed.
 @item @b{tap-disable}
 @* The TAP needs to be disabled.  This handler should
 implement @command{jtag tapdisable}
@@ -2450,7 +2456,7 @@
 
 @example
 jtag configure CHIP.jrc -event post-reset @{
-  echo "Reset done"
+  echo "JTAG Reset done"
   ... non-scan jtag operations to be done after reset
 @}
 @end example
@@ -2493,20 +2499,30 @@
 In OpenOCD, tap enabling/disabling is invoked by the Tcl commands
 shown below, and is implemented using TAP event handlers.
 So for example, when defining a TAP for a CPU connected to
-a JTAG router, you should define TAP event handlers using
+a JTAG router, your @file{target.cfg} file
+should define TAP event handlers using
 code that looks something like this:
 
 @example
 jtag configure CHIP.cpu -event tap-enable @{
-  echo "Enabling CPU TAP"
   ... jtag operations using CHIP.jrc
 @}
 jtag configure CHIP.cpu -event tap-disable @{
-  echo "Disabling CPU TAP"
   ... jtag operations using CHIP.jrc
 @}
 @end example
 
+Then you might want that CPU's TAP enabled almost all the time:
+
+@example
+jtag configure $CHIP.jrc -event setup "jtag tapenable $CHIP.cpu"
+@end example
+
+Note how that particular setup event handler declaration
+uses quotes to evaluate @code{$CHIP} when the event is configured.
+Using brackets @{ @} would cause it to be evaluated later,
+at runtime, when it might have a different value.
+
 @deffn Command {jtag tapdisable} dotted.name
 If necessary, disables the tap
 by sending it a @option{tap-disable} event.

Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-10-05 08:18:17 UTC (rev 2799)
+++ trunk/src/jtag/core.c	2009-10-05 08:20:28 UTC (rev 2800)
@@ -61,8 +61,8 @@
 static const char *jtag_event_strings[] =
 {
 	[JTAG_TRST_ASSERTED] = "TAP reset",
+	[JTAG_TAP_EVENT_SETUP] = "TAP setup",
 	[JTAG_TAP_EVENT_ENABLE] = "TAP enabled",
-	[JTAG_TAP_EVENT_POST_RESET] = "TAP post reset",
 	[JTAG_TAP_EVENT_DISABLE] = "TAP disabled",
 };
 
@@ -489,7 +489,7 @@
 
 	/* NOTE: order here matches TRST path in jtag_add_reset() */
 	jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
-	jtag_notify_reset();
+	jtag_notify_event(JTAG_TRST_ASSERTED);
 }
 
 void jtag_add_pathmove(int num_states, const tap_state_t *path)
@@ -704,7 +704,7 @@
 			 * sequence must match jtag_add_tlr().
 			 */
 			jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
-			jtag_notify_reset();
+			jtag_notify_event(JTAG_TRST_ASSERTED);
 		}
 	}
 }
@@ -1232,6 +1232,7 @@
 {
 	jtag_tap_t *tap;
 	int retval;
+	bool issue_setup = true;
 
 	LOG_DEBUG("Init JTAG chain");
 
@@ -1249,13 +1250,21 @@
 	if (jtag_examine_chain() != ERROR_OK)
 	{
 		LOG_ERROR("Trying to use configured scan chain anyway...");
+		issue_setup = false;
 	}
 
 	if (jtag_validate_ircapture() != ERROR_OK)
 	{
 		LOG_WARNING("Errors during IR capture, continuing anyway...");
+		issue_setup = false;
 	}
 
+	if (issue_setup)
+		jtag_notify_event(JTAG_TAP_EVENT_SETUP);
+	else
+		LOG_WARNING("Bypassing JTAG setup events due to errors");
+
+
 	return ERROR_OK;
 }
 

Modified: trunk/src/jtag/jtag.h
===================================================================
--- trunk/src/jtag/jtag.h	2009-10-05 08:18:17 UTC (rev 2799)
+++ trunk/src/jtag/jtag.h	2009-10-05 08:20:28 UTC (rev 2800)
@@ -192,23 +192,32 @@
 
 
 /*
- * There are three cases when JTAG_TRST_ASSERTED callback is invoked. The
- * event is invoked *after* TRST is asserted(or queued rather). It is illegal
- * to communicate with the JTAG interface during the callback(as there is
- * currently a queue being built).
+ * - TRST_ASSERTED triggers two sets of callbacks, after operations to
+ *   reset the scan chain -- via TMS+TCK signaling, or deasserting the
+ *   nTRST signal -- are queued:
  *
- * - TMS reset
- * - SRST pulls TRST
- * - TRST asserted
+ *    + Callbacks in C code fire first, patching internal state
+ *    + Then post-reset event scripts fire ... activating JTAG circuits
+ *      via TCK cycles, exiting SWD mode via TMS sequences, etc
  *
- * TAP activation/deactivation is currently implemented outside the core
- * using scripted code that understands the specific router type.
+ *   During those callbacks, scan chain contents have not been validated.
+ *   JTAG operations that address a specific TAP (primarily DR/IR scans)
+ *   must *not* be queued.
+ *
+ * - TAP_EVENT_SETUP is reported after TRST_ASSERTED, and after the scan
+ *   chain has been validated.  JTAG operations including scans that
+ *   target specific TAPs may be performed.
+ *
+ * - TAP_EVENT_ENABLE and TAP_EVENT_DISABLE implement TAP activation and
+ *   deactivation outside the core using scripted code that understands
+ *   the specific JTAG router type.  They might be triggered indirectly
+ *   from EVENT_SETUP operations.
  */
 enum jtag_event {
 	JTAG_TRST_ASSERTED,
+	JTAG_TAP_EVENT_SETUP,
 	JTAG_TAP_EVENT_ENABLE,
 	JTAG_TAP_EVENT_DISABLE,
-	JTAG_TAP_EVENT_POST_RESET,
 };
 
 struct jtag_tap_event_action_s
@@ -643,8 +652,8 @@
 /// @returns the number of times the scan queue has been flushed
 int jtag_get_flush_queue_count(void);
 
-/// Notify all TAP's about a TLR reset
-void jtag_notify_reset(void);
+/// Report Tcl event to all TAPs
+void jtag_notify_event(enum jtag_event);
 
 
 /* can be implemented by hw + sw */

Modified: trunk/src/jtag/tcl.c
===================================================================
--- trunk/src/jtag/tcl.c	2009-10-05 08:18:17 UTC (rev 2799)
+++ trunk/src/jtag/tcl.c	2009-10-05 08:20:28 UTC (rev 2800)
@@ -41,7 +41,8 @@
 #endif
 
 static const Jim_Nvp nvp_jtag_tap_event[] = {
-	{ .value = JTAG_TAP_EVENT_POST_RESET,   .name = "post-reset" },
+	{ .value = JTAG_TRST_ASSERTED,		.name = "post-reset" },
+	{ .value = JTAG_TAP_EVENT_SETUP,	.name = "setup" },
 	{ .value = JTAG_TAP_EVENT_ENABLE,       .name = "tap-enable" },
 	{ .value = JTAG_TAP_EVENT_DISABLE,      .name = "tap-disable" },
 
@@ -373,7 +374,7 @@
 
 	for (jteap = tap->event_action; jteap != NULL; jteap = jteap->next) {
 		if (jteap->event == e) {
-			LOG_DEBUG("JTAG tap: %s event: %d (%s) action: %s\n",
+			LOG_DEBUG("JTAG tap: %s event: %d (%s)\n\taction: %s",
 					tap->dotted_name,
 					e,
 					Jim_Nvp_value2name_simple(nvp_jtag_tap_event, e)->name,
@@ -384,10 +385,12 @@
 			case JTAG_TAP_EVENT_ENABLE:
 			case JTAG_TAP_EVENT_DISABLE:
 				/* NOTE:  we currently assume the handlers
-				 * can't fail.  That presumes later code
-				 * will be verifying the scan chains ...
+				 * can't fail.  Right here is where we should
+				 * really be verifying the scan chains ...
 				 */
 				tap->enabled = (e == JTAG_TAP_EVENT_ENABLE);
+				LOG_INFO("JTAG tap: %s %s", tap->dotted_name,
+					tap->enabled ? "enabled" : "disabled");
 				break;
 			default:
 				break;
@@ -586,13 +589,12 @@
 }
 
 
-void jtag_notify_reset(void)
+void jtag_notify_event(enum jtag_event event)
 {
 	jtag_tap_t *tap;
+
 	for (tap = jtag_all_taps(); tap; tap = tap->next_tap)
-	{
-		jtag_tap_handle_event(tap, JTAG_TAP_EVENT_POST_RESET);
-	}
+		jtag_tap_handle_event(tap, event);
 }
 
 

Modified: trunk/tcl/target/ti_dm355.cfg
===================================================================
--- trunk/tcl/target/ti_dm355.cfg	2009-10-05 08:18:17 UTC (rev 2799)
+++ trunk/tcl/target/ti_dm355.cfg	2009-10-05 08:20:28 UTC (rev 2800)
@@ -9,11 +9,11 @@
 
 # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
 # after JTAG reset until ICEpick is used to route them in.
-#set EMU01 "-disable"
+set EMU01 "-disable"
 
 # With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
 # needing any ICEpick interaction.
-set EMU01 "-enable"
+#set EMU01 "-enable"
 
 source [find target/icepick.cfg]
 
@@ -50,6 +50,9 @@
 }
 jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
 
+jtag configure $_CHIPNAME.jrc -event setup \
+	"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
+
 ################
 
 # various symbol definitions, to avoid hard-wiring addresses

Modified: trunk/tcl/target/ti_dm365.cfg
===================================================================
--- trunk/tcl/target/ti_dm365.cfg	2009-10-05 08:18:17 UTC (rev 2799)
+++ trunk/tcl/target/ti_dm365.cfg	2009-10-05 08:20:28 UTC (rev 2800)
@@ -7,16 +7,15 @@
    set  _CHIPNAME dm365
 }
 
-#
-# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
-# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
-#
-# Also note:  when running without RTCK before the PLLs are set up, you
-# may need to slow the JTAG clock down quite a lot (under 2 MHz).
-#
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+#set EMU01 "-enable"
+
 source [find target/icepick.cfg]
-set EMU01 "-enable"
-#set EMU01 "-disable"
 
 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
 if { [info exists ETB_TAPID ] } {
@@ -46,6 +45,9 @@
 }
 jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
 
+jtag configure $_CHIPNAME.jrc -event setup \
+	"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
+
 ################
 
 # various symbol definitions, to avoid hard-wiring addresses

Modified: trunk/tcl/target/ti_dm6446.cfg
===================================================================
--- trunk/tcl/target/ti_dm6446.cfg	2009-10-05 08:18:17 UTC (rev 2799)
+++ trunk/tcl/target/ti_dm6446.cfg	2009-10-05 08:20:28 UTC (rev 2800)
@@ -7,17 +7,15 @@
    set  _CHIPNAME dm6446
 }
 
-#
-# For now, expect EMU0/EMU1 jumpered LOW (not TI's default) so ARM and ETB
-# are enabled without making ICEpick route ARM and ETB into the JTAG chain.
-# Override by setting EMU01 to "-disable".
-#
-# Also note:  when running without RTCK before the PLLs are set up, you
-# may need to slow the JTAG clock down quite a lot (under 2 MHz).
-#
+# TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
+# after JTAG reset until ICEpick is used to route them in.
+set EMU01 "-disable"
+
+# With EMU0/EMU1 jumpered *low* ARM and ETB are *enabled* without
+# needing any ICEpick interaction.
+#set EMU01 "-enable"
+
 source [find target/icepick.cfg]
-set EMU01 "-enable"
-#set EMU01 "-disable"
 
 # Subsidiary TAP: unknown ... must enable via ICEpick
 jtag newtap $_CHIPNAME unknown -irlen 8 -disable
@@ -57,6 +55,10 @@
 }
 jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
 
+jtag configure $_CHIPNAME.jrc -event setup \
+	"jtag tapenable $_CHIPNAME.etb; jtag tapenable $_CHIPNAME.arm"
+
+################
 # GDB target:  the ARM, using SRAM1 for scratch.  SRAM0 (also 8K)
 # and the ETB memory (4K) are other options, while trace is unused.
 # Little-endian; use the OpenOCD default.

[Openocd-svn] r2797 - trunk/tcl/target

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-10-05 10:13:00 +0200 (Mon, 05 Oct 2009)
New Revision: 2797

Modified:
   trunk/tcl/target/omap2420.cfg
   trunk/tcl/target/omap5912.cfg
   trunk/tcl/target/ti_dm355.cfg
   trunk/tcl/target/ti_dm365.cfg
   trunk/tcl/target/ti_dm6446.cfg
Log:
Get rid of needless OMAP and Davinci target config options
so they provide better examples and are easier to maintain.


Modified: trunk/tcl/target/omap2420.cfg
===================================================================
--- trunk/tcl/target/omap2420.cfg	2009-10-02 16:52:02 UTC (rev 2796)
+++ trunk/tcl/target/omap2420.cfg	2009-10-05 08:13:00 UTC (rev 2797)
@@ -6,11 +6,6 @@
 } else {
    set  _CHIPNAME omap2420
 }
-if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
-} else {
-   set  _ENDIAN little
-}
 
 # NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK
 
@@ -46,7 +41,7 @@
 
 # GDB target:  the ARM.
 set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm11 -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm11 -chain-position $_TARGETNAME
 
 # scratch:  framebuffer, may be initially unavailable in some chips
 $_TARGETNAME configure -work-area-phys 0x40210000

Modified: trunk/tcl/target/omap5912.cfg
===================================================================
--- trunk/tcl/target/omap5912.cfg	2009-10-02 16:52:02 UTC (rev 2796)
+++ trunk/tcl/target/omap5912.cfg	2009-10-05 08:13:00 UTC (rev 2797)
@@ -7,13 +7,6 @@
    set  _CHIPNAME omap5912
 }
 
-if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
-} else {
-  # this defaults to a bigendian
-   set  _ENDIAN little
-}
-
 if { [info exists CPUTAPID ] } {
    set _CPUTAPID $CPUTAPID
 } else {
@@ -30,7 +23,7 @@
 jtag newtap $_CHIPNAME unknown -irlen 8
 
 set _TARGETNAME $_CHIPNAME.arm
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
 
 proc omap5912_reset {} {
 	#

Modified: trunk/tcl/target/ti_dm355.cfg
===================================================================
--- trunk/tcl/target/ti_dm355.cfg	2009-10-02 16:52:02 UTC (rev 2796)
+++ trunk/tcl/target/ti_dm355.cfg	2009-10-05 08:13:00 UTC (rev 2797)
@@ -6,11 +6,6 @@
 } else {
    set  _CHIPNAME dm355
 }
-if { [info exists ENDIAN] } {
-   set  _ENDIAN $ENDIAN
-} else {
-   set  _ENDIAN little
-}
 
 # TI boards default to EMU0/EMU1 *high* -- ARM and ETB are *disabled*
 # after JTAG reset until ICEpick is used to route them in.
@@ -33,8 +28,7 @@
 } else {
    set _ETB_TAPID 0x2b900f0f
 }
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
-	-expected-id $_ETB_TAPID $EMU01
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
 jtag configure $_CHIPNAME.etb -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 1"
 
@@ -44,8 +38,7 @@
 } else {
    set _CPU_TAPID 0x07926001
 }
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
-	-expected-id $_CPU_TAPID $EMU01
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
 jtag configure $_CHIPNAME.arm -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 0"
 
@@ -55,7 +48,7 @@
 } else {
    set _JRC_TAPID 0x0b73b02f
 }
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
 
 ################
 
@@ -89,7 +82,7 @@
 # and the ETB memory (4K) are other options, while trace is unused.
 set _TARGETNAME $_CHIPNAME.arm
 
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME
+target create $_TARGETNAME arm926ejs -chain-position $_TARGETNAME
 
 # NOTE that work-area-virt presumes a Linux 2.6.30-rc2+ kernel,
 # and that the work area is used only with a kernel mmu context ...

Modified: trunk/tcl/target/ti_dm365.cfg
===================================================================
--- trunk/tcl/target/ti_dm365.cfg	2009-10-02 16:52:02 UTC (rev 2796)
+++ trunk/tcl/target/ti_dm365.cfg	2009-10-05 08:13:00 UTC (rev 2797)
@@ -24,8 +24,7 @@
 } else {
    set _ETB_TAPID 0x2b900f0f
 }
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
-	-expected-id $_ETB_TAPID $EMU01
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
 jtag configure $_CHIPNAME.etb -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 1"
 
@@ -35,8 +34,7 @@
 } else {
    set _CPU_TAPID 0x0792602f
 }
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
-	-expected-id $_CPU_TAPID $EMU01
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
 jtag configure $_CHIPNAME.arm -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 0"
 
@@ -46,8 +44,7 @@
 } else {
    set _JRC_TAPID 0x0b83e02f
 }
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-	-expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
 
 ################
 

Modified: trunk/tcl/target/ti_dm6446.cfg
===================================================================
--- trunk/tcl/target/ti_dm6446.cfg	2009-10-02 16:52:02 UTC (rev 2796)
+++ trunk/tcl/target/ti_dm6446.cfg	2009-10-05 08:13:00 UTC (rev 2797)
@@ -20,7 +20,7 @@
 #set EMU01 "-disable"
 
 # Subsidiary TAP: unknown ... must enable via ICEpick
-jtag newtap $_CHIPNAME unknown -irlen 8 -ircapture 0xff -irmask 0xff -disable
+jtag newtap $_CHIPNAME unknown -irlen 8 -disable
 jtag configure $_CHIPNAME.unknown -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 3"
 
@@ -35,8 +35,7 @@
 } else {
    set _ETB_TAPID 0x2b900f0f
 }
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf \
-	-expected-id $_ETB_TAPID $EMU01
+jtag newtap $_CHIPNAME etb -irlen 4 -irmask 0xf -expected-id $_ETB_TAPID $EMU01
 jtag configure $_CHIPNAME.etb -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 1"
 
@@ -46,8 +45,7 @@
 } else {
    set _CPU_TAPID 0x07926001
 }
-jtag newtap $_CHIPNAME arm -irlen 4 -ircapture 0x1 -irmask 0xf \
-	-expected-id $_CPU_TAPID $EMU01
+jtag newtap $_CHIPNAME arm -irlen 4 -irmask 0xf -expected-id $_CPU_TAPID $EMU01
 jtag configure $_CHIPNAME.arm -event tap-enable \
 	"icepick_c_tapenable $_CHIPNAME.jrc 0"
 
@@ -57,8 +55,7 @@
 } else {
    set _JRC_TAPID 0x0b70002f
 }
-jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-	-expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 6 -irmask 0x3f -expected-id $_JRC_TAPID
 
 # GDB target:  the ARM, using SRAM1 for scratch.  SRAM0 (also 8K)
 # and the ETB memory (4K) are other options, while trace is unused.

[Openocd-svn] r2798 - trunk

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-10-05 10:14:57 +0200 (Mon, 05 Oct 2009)
New Revision: 2798

Modified:
   trunk/NEWS
Log:
Update the NEWS file to cover more of the user-visible changes.


Modified: trunk/NEWS
===================================================================
--- trunk/NEWS	2009-10-05 08:13:00 UTC (rev 2797)
+++ trunk/NEWS	2009-10-05 08:14:57 UTC (rev 2798)
@@ -5,27 +5,43 @@
 
 JTAG Layer:
     FT2232H (high speed USB) support doesn't need separate configuration
+    New reset_config options for SRST gating the JTAG clock (or not)
+    TAP declaration no longer requires ircapture and mask attributes
+    New "post-reset" event handler for TAP-invariant setup code
 
 Target Layer:
     New commands for use with Cortex-M3 processors:
 	"cortex_m3 disassemble" ... Thumb2 disassembly (UAL format)
 	"cortex_m3 vector_catch" ... traps certain hardware faults
 		without tying up breakpoint resources
-    If you're willing to help debug it:  VERY EARLY Cortex-A8 support
+    If you're willing to help debug it
+	VERY EARLY Cortex-A8 and ARMv7A support
+	Updated BeagleBoard.org hardware support
     New commands for use with XScale processors: "xscale vector_table"
-    ARM11 single stepping support for i.MX31 
+    ARM11
+	single stepping support for i.MX31
+	bugfix for missing "arm11" prefix on "arm11 memwrite ..."
+    ETM support
+	Unavailable registers are not listed
 
 Flash Layer:
     The lpc2000 driver handles the new NXP LPC1700 (Cortex-M3) chips
+    New lpc2900 driver for NXP LPC2900 chips (ARM968 based)
+    New "last" flag for NOR "flash erase_sector" and "flash protect"
+    The "nand erase N" command now erases all of bank N
 
 Board, Target, and Interface Configuration Scripts:
+    Amontec JTAGkey2 support
     Cleanup and additions for the TI/Luminary Stellaris scripts
     LPC1768 target (and flash) support
 	Keil MCB1700 eval board
     Samsung s3c2450
 	Mini2440 board
+    Numeric TAP and Target identifiers now trigger warnings
 
 Documentation:
+    Capture more debugging and setup advice
+    Notes on target source code changes that may help debugging
 
 Build and Release:
 

[Openocd-svn] r2801 - trunk/src/jtag

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-10-05 10:23:33 +0200 (Mon, 05 Oct 2009)
New Revision: 2801

Modified:
   trunk/src/jtag/core.c
Log:
Improve jtag_validate_ircapture() diagnostics.

Bugfix the error message so it shows the disliked value, and add
a debug message showing each TAP's IR capture value, all N bits.

This just changes diagnostics ... it still ignores the parameters
given to us at TAP declaration time.


Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-10-05 08:20:28 UTC (rev 2800)
+++ trunk/src/jtag/core.c	2009-10-05 08:23:33 UTC (rev 2801)
@@ -1068,6 +1068,7 @@
 	int total_ir_length = 0;
 	uint8_t *ir_test = NULL;
 	scan_field_t field;
+	int val;
 	int chain_pos = 0;
 	int retval;
 
@@ -1100,7 +1101,7 @@
 
 	tap = NULL;
 	chain_pos = 0;
-	int val;
+
 	for (;;) {
 		tap = jtag_tap_next_enabled(tap);
 		if (tap == NULL) {
@@ -1111,17 +1112,18 @@
 		 * REVISIT we might be able to verify some MSBs too, using
 		 * ircapture/irmask attributes.
 		 */
-		val = buf_get_u32(ir_test, chain_pos, 2);
-		if (val != 1) {
-			char *cbuf = buf_to_str(ir_test, total_ir_length, 16);
+		val = buf_get_u32(ir_test, chain_pos, tap->ir_length);
+		if ((val & 0x3) != 1) {
+			LOG_ERROR("%s: IR capture error; saw 0x%0*x not 0x..1",
+					jtag_tap_name(tap),
+					(tap->ir_length + 7) / tap->ir_length,
+					val);
 
-			LOG_ERROR("%s: IR capture error; saw 0x%s not 0x..1",
-					jtag_tap_name(tap), cbuf);
-
-			free(cbuf);
 			retval = ERROR_JTAG_INIT_FAILED;
 			goto done;
 		}
+		LOG_DEBUG("%s: IR capture 0x%0*x", jtag_tap_name(tap),
+				(tap->ir_length + 7) / tap->ir_length, val);
 		chain_pos += tap->ir_length;
 	}
 

[Openocd-svn] r2799 - trunk/src/target

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-10-05 10:18:17 +0200 (Mon, 05 Oct 2009)
New Revision: 2799

Modified:
   trunk/src/target/arm926ejs.c
Log:
Minor cleanup to ARM926 debug entry:

 - don't needlessly export this function
 - handle "case 0" debug method-of-entry better (silent by default)

The "case 0" is a valid debug entry mode so it doesn't deserve the
warning int now gets.  But it probably means that OpenOCD confused
itself somehow; or that it confused the ARM9EJS target.


Modified: trunk/src/target/arm926ejs.c
===================================================================
--- trunk/src/target/arm926ejs.c	2009-10-05 08:14:57 UTC (rev 2798)
+++ trunk/src/target/arm926ejs.c	2009-10-05 08:18:17 UTC (rev 2799)
@@ -277,7 +277,7 @@
 	return ERROR_OK;
 }
 
-int arm926ejs_examine_debug_reason(target_t *target)
+static int arm926ejs_examine_debug_reason(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
@@ -294,7 +294,11 @@
 
 	switch (debug_reason)
 	{
-		/* case 0:  no debug entry */
+		case 0:
+			LOG_DEBUG("no *NEW* debug entry (?missed one?)");
+			/* ... since last restart or debug reset ... */
+			target->debug_reason = DBG_REASON_DBGRQ;
+			break;
 		case 1:
 			LOG_DEBUG("breakpoint from EICE unit 0");
 			target->debug_reason = DBG_REASON_BREAKPOINT;

[Openocd-svn] r2796 - trunk/tcl/target

[<ml...@ma...>]

Author: mlu
Date: 2009-10-02 18:52:02 +0200 (Fri, 02 Oct 2009)
New Revision: 2796

Modified:
   trunk/tcl/target/omap3530.cfg
Log:
Updated reset event handling in omap3530 cfg

Modified: trunk/tcl/target/omap3530.cfg
===================================================================
--- trunk/tcl/target/omap3530.cfg	2009-10-02 16:50:42 UTC (rev 2795)
+++ trunk/tcl/target/omap3530.cfg	2009-10-02 16:52:02 UTC (rev 2796)
@@ -42,15 +42,20 @@
 # FIXME much of this should be in reset event handlers
 proc omap3_dbginit { } {
      poll off
-     reset
      sleep 100
 
      jtag tapenable omap3530.dap
      targets
      # General Cortex A8 debug initialisation
      cortex_a8 dbginit
-     # Enable DBGU singal for OMAP353x
+     # Enable DBGU signal for OMAP353x
      omap3.cpu mww 0x5401d030 0x00002000
      poll on
 }
 
+set PRM_RSTCTRL 0x48307250
+
+omap3.cpu configure -event reset-start "omap3.cpu mww $PRM_RSTCTRL 2"
+omap3.cpu configure -event reset-assert-pre "omap3_dbginit"
+
+

[Openocd-svn] r2795 - trunk/src/target

[<ml...@ma...>]

Author: mlu
Date: 2009-10-02 18:50:42 +0200 (Fri, 02 Oct 2009)
New Revision: 2795

Modified:
   trunk/src/target/cortex_a8.c
Log:
It is not possible to invalidate I-Cache on memory writes while the target is running

Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-10-02 16:44:16 UTC (rev 2794)
+++ trunk/src/target/cortex_a8.c	2009-10-02 16:50:42 UTC (rev 2795)
@@ -1332,6 +1332,8 @@
 			exit(-1);
 	}
 
+	if (target->state == TARGET_HALTED)
+	{
 		/* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
 		/* invalidate I-Cache */
 		if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
@@ -1349,6 +1351,7 @@
 			for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
 				armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */
 		}
+	}
 
 	return retval;
 }

[Openocd-svn] r2794 - trunk/src/target

[<ml...@ma...>]

Author: mlu
Date: 2009-10-02 18:44:16 +0200 (Fri, 02 Oct 2009)
New Revision: 2794

Modified:
   trunk/src/target/cortex_a8.c
Log:
Make sure that DSCR_DTR_RX is not full before writing

Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-10-02 16:39:50 UTC (rev 2793)
+++ trunk/src/target/cortex_a8.c	2009-10-02 16:44:16 UTC (rev 2794)
@@ -236,11 +236,25 @@
 	uint8_t CP, uint8_t op1, uint8_t CRn, uint8_t CRm, uint8_t op2)
 {
 	int retval;
+	uint32_t dscr;
+
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	armv7a_common_t *armv7a = armv4_5->arch_info;
 	swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
+	LOG_DEBUG("CP%i, CRn %i, value 0x%08" PRIx32, CP, CRn, value);
+
+	/* Check that DCCRX is not full */
+	retval = mem_ap_read_atomic_u32(swjdp,
+				armv7a->debug_base + CPUDBG_DSCR, &dscr);
+	if (dscr & (1 << DSCR_DTR_RX_FULL))
+	{
+		LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
+		/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode  0xEE000E15 */
+		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+	}
+	
 	retval = mem_ap_write_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DTRRX, value);
 	/* Move DTRRX to r0 */
@@ -311,12 +325,25 @@
 {
 	int retval = ERROR_OK;
 	uint8_t Rd = regnum&0xFF;
+	uint32_t dscr;
 
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	armv7a_common_t *armv7a = armv4_5->arch_info;
 	swjdp_common_t *swjdp = &armv7a->swjdp_info;
 	
+	LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
+
+	/* Check that DCCRX is not full */
+	retval = mem_ap_read_atomic_u32(swjdp,
+				armv7a->debug_base + CPUDBG_DSCR, &dscr);
+	if (dscr & (1 << DSCR_DTR_RX_FULL))
+	{
+		LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
+		/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode  0xEE000E15 */
+		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
+	}
+	
 	if (Rd > 16)
 		return retval;
 

[Openocd-svn] r2793 - trunk/src/target

[<ml...@ma...>]

Author: mlu
Date: 2009-10-02 18:39:50 +0200 (Fri, 02 Oct 2009)
New Revision: 2793

Modified:
   trunk/src/target/cortex_a8.c
Log:
More error reporting in Cortex_a8 execute_opcode

Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-10-02 16:37:22 UTC (rev 2792)
+++ trunk/src/target/cortex_a8.c	2009-10-02 16:39:50 UTC (rev 2793)
@@ -165,8 +165,11 @@
 		retval = mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
 		if (retval != ERROR_OK)
+		{
+			LOG_ERROR("Could not read DSCR register, opcode = 0x%08" PRIx32, opcode);
 			return retval;
 		}
+	}
 	while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
 	mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
@@ -176,8 +179,11 @@
 		retval = mem_ap_read_atomic_u32(swjdp,
 				armv7a->debug_base + CPUDBG_DSCR, &dscr);
 		if (retval != ERROR_OK)
+		{
+			LOG_ERROR("Could not read DSCR register");
 			return retval;
 		}
+	}
 	while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
 	return retval;

[Openocd-svn] r2792 - trunk/src/target

[<ml...@ma...>]

Author: mlu
Date: 2009-10-02 18:37:22 +0200 (Fri, 02 Oct 2009)
New Revision: 2792

Modified:
   trunk/src/target/cortex_a8.c
Log:
Added asser_reset and deassert_reset for cortex_a8

Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-10-02 16:36:03 UTC (rev 2791)
+++ trunk/src/target/cortex_a8.c	2009-10-02 16:37:22 UTC (rev 2792)
@@ -83,8 +83,8 @@
 	.resume = cortex_a8_resume,
 	.step = cortex_a8_step,
 
-	.assert_reset = NULL,
-	.deassert_reset = NULL,
+	.assert_reset = cortex_a8_assert_reset,
+	.deassert_reset = cortex_a8_deassert_reset,
 	.soft_reset_halt = NULL,
 
 	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,

[Openocd-svn] r2791 - trunk/src/target

[<ml...@ma...>]

Author: mlu
Date: 2009-10-02 18:36:03 +0200 (Fri, 02 Oct 2009)
New Revision: 2791

Modified:
   trunk/src/target/cortex_a8.c
Log:
Added asser_reset and deassert_reset for cortex_a8

Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-10-02 09:19:03 UTC (rev 2790)
+++ trunk/src/target/cortex_a8.c	2009-10-02 16:36:03 UTC (rev 2791)
@@ -67,6 +67,8 @@
 		uint32_t *value, int regnum);
 int cortex_a8_dap_write_coreregister_u32(target_t *target,
 		uint32_t value, int regnum);
+int cortex_a8_assert_reset(target_t *target);
+int cortex_a8_deassert_reset(target_t *target);
 
 target_type_t cortexa8_target =
 {
@@ -138,8 +140,13 @@
 	/* Clear Sticky Power Down status Bit in PRSR to enable access to
 	   the registers in the Core Power Domain */
 	retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
-	/* Enabling of instruction execution in debug mode is done in debug_entry code */
-
+	/* Enabling of instruction execution in debug mode is done in debug_entry code */ 
+	
+	/* Resync breakpoint registers */
+	
+	/* Since this is likley called from init or reset, update targtet state information*/
+	cortex_a8_poll(target);
+	
 	return retval;
 }
 
@@ -303,7 +310,7 @@
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	armv7a_common_t *armv7a = armv4_5->arch_info;
 	swjdp_common_t *swjdp = &armv7a->swjdp_info;
-
+	
 	if (Rd > 16)
 		return retval;
 
@@ -1188,7 +1195,34 @@
  * Cortex-A8 Reset fuctions
  */
 
+int cortex_a8_assert_reset(target_t *target)
+{
 
+	LOG_DEBUG(" ");
+
+	/* registers are now invalid */
+	armv4_5_invalidate_core_regs(target);
+
+	target->state = TARGET_RESET;
+	
+	return ERROR_OK;
+}
+
+int cortex_a8_deassert_reset(target_t *target)
+{
+
+	LOG_DEBUG(" ");
+
+	if (target->reset_halt)
+	{
+		int retval;
+		if ((retval = target_halt(target)) != ERROR_OK)
+			return retval;
+	}
+
+	return ERROR_OK;
+}
+
 /*
  * Cortex-A8 Memory access
  *
@@ -1265,23 +1299,23 @@
 			exit(-1);
 	}
 
-	/* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
-	/* invalidate I-Cache */
-	if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
-	{
-		/* Invalidate ICache single entry with MVA, repeat this for all cache
-		   lines in the address range, Cortex-A8 has fixed 64 byte line length */
-		/* Invalidate Cache single entry with MVA to PoU */
-		for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
-			armv7a->write_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */
-	}
-	/* invalidate D-Cache */
-	if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
-	{
-		/* Invalidate Cache single entry with MVA to PoC */
-		for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
-			armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */
-	}
+		/* The Cache handling will NOT work with MMU active, the wrong addresses will be invalidated */
+		/* invalidate I-Cache */
+		if (armv7a->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
+		{
+			/* Invalidate ICache single entry with MVA, repeat this for all cache
+			   lines in the address range, Cortex-A8 has fixed 64 byte line length */
+			/* Invalidate Cache single entry with MVA to PoU */
+			for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
+				armv7a->write_cp15(target, 0, 1, 7, 5, cacheline); /* I-Cache to PoU */
+		}
+		/* invalidate D-Cache */
+		if (armv7a->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled)
+		{
+			/* Invalidate Cache single entry with MVA to PoC */
+			for (uint32_t cacheline=address; cacheline<address+size*count; cacheline+=64)
+				armv7a->write_cp15(target, 0, 1, 7, 6, cacheline); /* U/D cache to PoC */
+		}
 
 	return retval;
 }
@@ -1374,7 +1408,7 @@
 	uint32_t didr, ctypr, ttypr, cpuid;
 
 	LOG_DEBUG("TODO");
-
+	
 	/* Here we shall insert a proper ROM Table scan */
 	armv7a->debug_base = OMAP3530_DEBUG_BASE;
 
@@ -1451,7 +1485,7 @@
 
 	/* Configure core debug access */
 	cortex_a8_init_debug_access(target);
-
+	
 	target->type->examined = 1;
 
 	return retval;

[Openocd-svn] r2790 - in trunk: doc src/target

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-10-02 11:19:03 +0200 (Fri, 02 Oct 2009)
New Revision: 2790

Modified:
   trunk/doc/openocd.texi
   trunk/src/target/etb.c
   trunk/src/target/etm.c
Log:
Minor ETB and ETM bugfixes and doc updates

 - ETB
    * report _actual_ hardware status, not just expected status
    * add a missing diagnostic on a potential ETB setup error
    * prefix any diagnostics with "ETB"
 - ETM
    * make "etm status" show ETM hardware status too, instead of
      just traceport status (which previously was fake, sigh)
 - Docs
    * flesh out "etm tracemode" docs a bit
    * clarify "etm status" ... previously it was traceport status
    * explain "etm trigger_percent" as a *traceport* option

ETM+ETB tracing still isn't behaving, but now I can see that part of 
the reason is that the ETB turns itself off almost immediately after
being enabled, and before collecting any data.


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-10-01 17:39:13 UTC (rev 2789)
+++ trunk/doc/openocd.texi	2009-10-02 09:19:03 UTC (rev 2790)
@@ -4891,7 +4891,7 @@
 @end deffn
 
 @deffn Command {etm status}
-Displays status of the current target's ETM:
+Displays status of the current target's ETM and trace port driver:
 is the ETM idle, or is it collecting data?
 Did trace data overflow?
 Was it triggered?
@@ -4904,19 +4904,43 @@
 and any buffered trace data is invalidated.
 
 @itemize
-@item @var{type} ... one of
+@item @var{type} ... describing how data accesses are traced,
+when they pass any ViewData filtering that that was set up.
+The value is one of
 @option{none} (save nothing),
 @option{data} (save data),
 @option{address} (save addresses),
 @option{all} (save data and addresses)
 @item @var{context_id_bits} ... 0, 8, 16, or 32
 @item @var{cycle_accurate} ...  @option{enable} or @option{disable}
-@item @var{branch_output} ...  @option{enable} or @option{disable}
+cycle-accurate instruction tracing.
+Before ETMv3, enabling this causes much extra data to be recorded.
+@item @var{branch_output} ...  @option{enable} or @option{disable}.
+Disable this unless you need to try reconstructing the instruction
+trace stream without an image of the code.
 @end itemize
 @end deffn
 
-@deffn Command {etm trigger_percent} percent
-@emph{Buggy and effectively a NOP ... @var{percent} from 2..100}
+@deffn Command {etm trigger_percent} [percent]
+This displays, or optionally changes, the trace port driver's
+behavior after the ETM's configured @emph{trigger} event fires.
+It controls how much more trace data is saved after the (single)
+trace trigger becomes active.
+
+@itemize
+@item The default corresponds to @emph{trace around} usage,
+recording 50 percent data before the event and the rest
+afterwards.
+@item The minimum value of @var{percent} is 2 percent,
+recording almost exclusively data before the trigger.
+Such extreme @emph{trace before} usage can help figure out
+what caused that event to happen.
+@item The maximum value of @var{percent} is 100 percent,
+recording data almost exclusively after the event.
+This extreme @emph{trace after} usage might help sort out
+how the event caused trouble.
+@end itemize
+@c REVISIT allow "break" too -- enter debug mode.
 @end deffn
 
 @subsection ETM Trace Operation

Modified: trunk/src/target/etb.c
===================================================================
--- trunk/src/target/etb.c	2009-10-01 17:39:13 UTC (rev 2789)
+++ trunk/src/target/etb.c	2009-10-02 09:19:03 UTC (rev 2790)
@@ -110,13 +110,13 @@
 
 	if ((retval = etb_read_reg(reg)) != ERROR_OK)
 	{
-		LOG_ERROR("BUG: error scheduling etm register read");
+		LOG_ERROR("BUG: error scheduling ETB register read");
 		return retval;
 	}
 
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
-		LOG_ERROR("register read failed");
+		LOG_ERROR("ETB register read failed");
 		return retval;
 	}
 
@@ -288,7 +288,7 @@
 
 	if ((retval = etb_write_reg(reg, value)) != ERROR_OK)
 	{
-		LOG_ERROR("BUG: error scheduling etm register write");
+		LOG_ERROR("BUG: error scheduling ETB register write");
 		return retval;
 	}
 
@@ -307,7 +307,7 @@
 
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
-		LOG_ERROR("register write failed");
+		LOG_ERROR("ETB: register write failed");
 		return retval;
 	}
 	return ERROR_OK;
@@ -378,20 +378,20 @@
 
 	if (!target)
 	{
-		LOG_ERROR("target '%s' not defined", args[0]);
+		LOG_ERROR("ETB: target '%s' not defined", args[0]);
 		return ERROR_FAIL;
 	}
 
 	if (arm7_9_get_arch_pointers(target, &armv4_5, &arm7_9) != ERROR_OK)
 	{
-		command_print(cmd_ctx, "current target isn't an ARM7/ARM9 target");
+		command_print(cmd_ctx, "ETB: current target isn't an ARM7/ARM9 target");
 		return ERROR_FAIL;
 	}
 
 	tap = jtag_tap_by_string(args[1]);
 	if (tap == NULL)
 	{
-		command_print(cmd_ctx, "Tap: %s does not exist", args[1]);
+		command_print(cmd_ctx, "ETB: TAP %s does not exist", args[1]);
 		return ERROR_FAIL;
 	}
 
@@ -409,7 +409,7 @@
 	}
 	else
 	{
-		LOG_ERROR("target has no ETM defined, ETB left unconfigured");
+		LOG_ERROR("ETM: target has no ETM defined, ETB left unconfigured");
 		return ERROR_FAIL;
 	}
 
@@ -436,56 +436,53 @@
 static trace_status_t etb_status(etm_context_t *etm_ctx)
 {
 	etb_t *etb = etm_ctx->capture_driver_priv;
+	reg_t *control = &etb->reg_cache->reg_list[ETB_CTRL];
+	reg_t *status = &etb->reg_cache->reg_list[ETB_STATUS];
+	trace_status_t retval = 0;
+	int etb_timeout = 100;
 
 	etb->etm_ctx = etm_ctx;
 
-	/* if tracing is currently idle, return this information */
-	if (etm_ctx->capture_status == TRACE_IDLE)
-	{
-		return etm_ctx->capture_status;
-	}
-	else if (etm_ctx->capture_status & TRACE_RUNNING)
-	{
-		reg_t *etb_status_reg = &etb->reg_cache->reg_list[ETB_STATUS];
-		int etb_timeout = 100;
+	/* read control and status registers */
+	etb_read_reg(control);
+	etb_read_reg(status);
+	jtag_execute_queue();
 
-		/* trace is running, check the ETB status flags */
-		etb_get_reg(etb_status_reg);
+	/* See if it's (still) active */
+	retval = buf_get_u32(control->value, 0, 1) ? TRACE_RUNNING : TRACE_IDLE;
 
-		/* check Full bit to identify an overflow */
-		if (buf_get_u32(etb_status_reg->value, 0, 1) == 1)
-			etm_ctx->capture_status |= TRACE_OVERFLOWED;
+	/* check Full bit to identify wraparound/overflow */
+	if (buf_get_u32(status->value, 0, 1) == 1)
+		retval |= TRACE_OVERFLOWED;
 
-		/* check Triggered bit to identify trigger condition */
-		if (buf_get_u32(etb_status_reg->value, 1, 1) == 1)
-			etm_ctx->capture_status |= TRACE_TRIGGERED;
+	/* check Triggered bit to identify trigger condition */
+	if (buf_get_u32(status->value, 1, 1) == 1)
+		retval |= TRACE_TRIGGERED;
 
-		/* check AcqComp to identify trace completion */
-		if (buf_get_u32(etb_status_reg->value, 2, 1) == 1)
-		{
-			while (etb_timeout-- && (buf_get_u32(etb_status_reg->value, 3, 1) == 0))
-			{
-				/* wait for data formatter idle */
-				etb_get_reg(etb_status_reg);
-			}
+	/* check AcqComp to see if trigger counter dropped to zero */
+	if (buf_get_u32(status->value, 2, 1) == 1) {
+		/* wait for DFEmpty */
+		while (etb_timeout-- && buf_get_u32(status->value, 3, 1) == 0)
+			etb_get_reg(status);
 
-			if (etb_timeout == 0)
-			{
-				LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%" PRIx32 "",
-					buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
-			}
+		if (etb_timeout == 0)
+			LOG_ERROR("ETB:  DFEmpty won't go high, status 0x%02x",
+				(unsigned) buf_get_u32(status->value, 0, 4));
 
-			if (!(etm_ctx->capture_status && TRACE_TRIGGERED))
-			{
-				LOG_ERROR("trace completed, but no trigger condition detected");
-			}
+		if (!(etm_ctx->capture_status & TRACE_TRIGGERED))
+			LOG_WARNING("ETB: trace complete without triggering?");
 
-			etm_ctx->capture_status &= ~TRACE_RUNNING;
-			etm_ctx->capture_status |= TRACE_COMPLETED;
-		}
+		retval |= TRACE_COMPLETED;
 	}
 
-	return etm_ctx->capture_status;
+	/* NOTE: using a trigger is optional; and at least ETB11 has a mode
+	 * where it can ignore the trigger counter.
+	 */
+
+	/* update recorded state */
+	etm_ctx->capture_status = retval;
+
+	return retval;
 }
 
 static int etb_read_trace(etm_context_t *etm_ctx)
@@ -654,8 +651,10 @@
 		etb_ctrl_value |= 0x2;
 	}
 
-	if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED)
+	if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) {
+		LOG_ERROR("ETB: can't run in multiplexed mode");
 		return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
+	}
 
 	trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
 

Modified: trunk/src/target/etm.c
===================================================================
--- trunk/src/target/etm.c	2009-10-01 17:39:13 UTC (rev 2789)
+++ trunk/src/target/etm.c	2009-10-02 09:19:03 UTC (rev 2790)
@@ -1567,6 +1567,7 @@
 	target_t *target;
 	armv4_5_common_t *armv4_5;
 	arm7_9_common_t *arm7_9;
+	etm_context_t *etm;
 	trace_status_t trace_status;
 
 	target = get_current_target(cmd_ctx);
@@ -1582,28 +1583,56 @@
 		command_print(cmd_ctx, "current target doesn't have an ETM configured");
 		return ERROR_OK;
 	}
+	etm = arm7_9->etm_ctx;
 
-	trace_status = arm7_9->etm_ctx->capture_driver->status(arm7_9->etm_ctx);
+	/* ETM status */
+	if (etm->bcd_vers >= 0x11) {
+		reg_t *reg;
 
+		reg = etm_reg_lookup(etm, ETM_STATUS);
+		if (!reg)
+			return ERROR_OK;
+		if (etm_get_reg(reg) == ERROR_OK) {
+			unsigned s = buf_get_u32(reg->value, 0, reg->size);
+
+			command_print(cmd_ctx, "etm: %s%s%s%s",
+				/* bit(1) == progbit */
+				(etm->bcd_vers >= 0x12)
+					? ((s & (1 << 1))
+						? "disabled" : "enabled")
+					: "?",
+				((s & (1 << 3)) && etm->bcd_vers >= 0x31)
+					? " triggered" : "",
+				((s & (1 << 2)) && etm->bcd_vers >= 0x12)
+					? " start/stop" : "",
+				((s & (1 << 0)) && etm->bcd_vers >= 0x11)
+					? " untraced-overflow" : "");
+		} /* else ignore and try showing trace port status */
+	}
+
+	/* Trace Port Driver status */
+	trace_status = etm->capture_driver->status(etm);
 	if (trace_status == TRACE_IDLE)
 	{
-		command_print(cmd_ctx, "tracing is idle");
+		command_print(cmd_ctx, "%s: idle", etm->capture_driver->name);
 	}
 	else
 	{
 		static char *completed = " completed";
 		static char *running = " is running";
-		static char *overflowed = ", trace overflowed";
-		static char *triggered = ", trace triggered";
+		static char *overflowed = ", overflowed";
+		static char *triggered = ", triggered";
 
-		command_print(cmd_ctx, "trace collection%s%s%s",
+		command_print(cmd_ctx, "%s: trace collection%s%s%s",
+			etm->capture_driver->name,
 			(trace_status & TRACE_RUNNING) ? running : completed,
 			(trace_status & TRACE_OVERFLOWED) ? overflowed : "",
 			(trace_status & TRACE_TRIGGERED) ? triggered : "");
 
-		if (arm7_9->etm_ctx->trace_depth > 0)
+		if (etm->trace_depth > 0)
 		{
-			command_print(cmd_ctx, "%i frames of trace data read", (int)(arm7_9->etm_ctx->trace_depth));
+			command_print(cmd_ctx, "%i frames of trace data read",
+					(int)(etm->trace_depth));
 		}
 	}