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[openocd-svn] Main OpenOCD repository branch, master, updated. 0.2.0-373-g251b5ef

[Øyvind H. <go...@us...>]

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- Log -----------------------------------------------------------------
commit 251b5efa04fd3a34f174c2ce91544c39391b4fbd
Author: Wookey <wo...@wo...>
Date:   Wed Oct 14 14:27:41 2009 +0100

    Fw: [PATCH] OpenRD board configuration
    
    Ofrwarded from Ron, who's not subscribed.
    
    ----- Forwarded message from Ron <ro...@de...> -----
    
    From: Ron <ro...@de...>
    Date: Wed, 14 Oct 2009 04:50:17 +1030
    To: wo...@de...
    Subject: [PATCH] OpenRD board configuration
    X-Spam-Status: No, score=-3.6 required=4.5 tests=BAYES_00,RCVD_IN_DNSWL_LOW
    	autolearn=ham version=3.2.5
    
    This piggybacks on the 'sheevaplug' layout which uses the same Kirkwood SoC.
    
    Signed-off-by: Ron Lee <ro...@de...>

diff --git a/tcl/board/openrd.cfg b/tcl/board/openrd.cfg
new file mode 100644
index 0000000..a77dcdb
--- /dev/null
+++ b/tcl/board/openrd.cfg
@@ -0,0 +1,122 @@
+# Marvell OpenRD
+
+source [find interface/openrd.cfg]
+source [find target/feroceon.cfg]
+
+$_TARGETNAME configure \
+	-work-area-phys 0x10000000 \
+	-work-area-size 65536 \
+	-work-area-backup 0
+
+arm7_9 dcc_downloads enable
+
+# this assumes the hardware default peripherals location before u-Boot moves it
+nand device orion 0 0xd8000000
+
+proc openrd_init { } {
+
+	# We need to assert DBGRQ while holding nSRST down.
+	# However DBGACK will be set only when nSRST is released.
+	# Furthermore, the JTAG interface doesn't respond at all when
+	# the CPU is in the WFI (wait for interrupts) state, so it is
+	# possible that initial tap examination failed.  So let's
+	# re-examine the target again here when nSRST is asserted which
+	# should then succeed.
+	jtag_reset 0 1
+	feroceon.cpu arp_examine
+	halt 0
+	jtag_reset 0 0
+	wait_halt
+
+	arm926ejs cp15 0 0 1 0 0x00052078
+
+	mww 0xD0001400 0x43000C30 #  DDR SDRAM Configuration Register
+	mww 0xD0001404 0x37543000 #  Dunit Control Low Register
+	mww 0xD0001408 0x22125451 #  DDR SDRAM Timing (Low) Register
+	mww 0xD000140C 0x00000A33 #  DDR SDRAM Timing (High) Register
+	mww 0xD0001410 0x000000CC #  DDR SDRAM Address Control Register
+	mww 0xD0001414 0x00000000 #  DDR SDRAM Open Pages Control Register
+	mww 0xD0001418 0x00000000 #  DDR SDRAM Operation Register
+	mww 0xD000141C 0x00000C52 #  DDR SDRAM Mode Register
+	mww 0xD0001420 0x00000004 #  DDR SDRAM Extended Mode Register
+	mww 0xD0001424 0x0000F17F #  Dunit Control High Register
+	mww 0xD0001428 0x00085520 #  Dunit Control High Register
+	mww 0xD000147c 0x00008552 #  Dunit Control High Register
+	mww 0xD0001504 0x0FFFFFF1 #  CS0n Size Register
+	mww 0xD0001508 0x10000000 #  CS1n Base Register
+	mww 0xD000150C 0x0FFFFFF5 #  CS1n Size Register
+	mww 0xD0001514 0x00000000 #  CS2n Size Register
+	mww 0xD000151C 0x00000000 #  CS3n Size Register
+	mww 0xD0001494 0x00120012 #  DDR2 SDRAM ODT Control (Low) Register
+	mww 0xD0001498 0x00000000 #  DDR2 SDRAM ODT Control (High) REgister
+	mww 0xD000149C 0x0000E40F #  DDR2 Dunit ODT Control Register
+	mww 0xD0001480 0x00000001 #  DDR SDRAM Initialization Control Register
+	mww 0xD0020204 0x00000000 #  Main IRQ Interrupt Mask Register
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+	mww 0xD0020204 0x00000000 #              "
+
+	mww 0xD0010000 0x01111111 #  MPP  0 to 7
+	mww 0xD0010004 0x11113322 #  MPP  8 to 15
+	mww 0xD0010008 0x00001111 #  MPP 16 to 23
+
+	mww 0xD0010418 0x003E07CF #  NAND Read Parameters REgister
+	mww 0xD001041C 0x000F0F0F #  NAND Write Parameters Register
+	mww 0xD0010470 0x01C7D943 #  NAND Flash Control Register
+
+}
+
+proc openrd_reflash_uboot { } {
+
+	# reflash the u-Boot binary and reboot into it
+	openrd_init
+	nand probe 0
+	nand erase 0 0x0 0xa0000
+	nand write 0 uboot.bin 0 oob_softecc_kw
+	resume
+
+}
+
+proc openrd_load_uboot { } {
+
+	# load u-Boot into RAM and execute it
+	openrd_init
+	load_image uboot.elf
+	verify_image uboot.elf
+	resume 0x00600000
+
+}
+
diff --git a/tcl/interface/openrd.cfg b/tcl/interface/openrd.cfg
new file mode 100644
index 0000000..b01205b
--- /dev/null
+++ b/tcl/interface/openrd.cfg
@@ -0,0 +1,12 @@
+#
+# Marvell OpenRD
+#
+# http://www.marvell.com/products/embedded_processors/developer/kirkwood/openrd.jsp
+#
+
+interface ft2232
+ft2232_layout sheevaplug
+ft2232_vid_pid 0x0403 0x9e90
+ft2232_device_desc "OpenRD JTAGKey FT2232D B"
+jtag_khz 3000
+

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/{sheevaplug.cfg => openrd.cfg} |   35 ++++++++++-------------------
 tcl/interface/openrd.cfg                 |   12 ++++++++++
 2 files changed, 24 insertions(+), 23 deletions(-)
 copy tcl/board/{sheevaplug.cfg => openrd.cfg} (84%)
 create mode 100644 tcl/interface/openrd.cfg


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Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. 0.2.0-372-ga3697c3

[Øyvind H. <go...@us...>]

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- Log -----------------------------------------------------------------
commit a3697c35b2ef510f519757349884bc924c03c9e9
Author: Øyvind Harboe <oyv...@zy...>
Date:   Wed Oct 14 12:01:52 2009 +0200

    S29WS-N CFI query fix is to try 0x555 if 0x55 fails.

diff --git a/src/flash/cfi.c b/src/flash/cfi.c
index ffc9d27..2d75ff4 100644
--- a/src/flash/cfi.c
+++ b/src/flash/cfi.c
@@ -2143,6 +2143,45 @@ static void cfi_fixup_0002_unlock_addresses(flash_bank_t *bank, void *param)
 	pri_ext->_unlock2 = unlock_addresses->unlock2;
 }
 
+
+static int cfi_query_string(struct flash_bank_s *bank, int address)
+{
+	cfi_flash_bank_t *cfi_info = bank->driver_priv;
+	target_t *target = bank->target;
+	int retval;
+	uint8_t command[8];
+
+	cfi_command(bank, 0x98, command);
+	if ((retval = target_write_memory(target, flash_address(bank, 0, address), bank->bus_width, 1, command)) != ERROR_OK)
+	{
+		return retval;
+	}
+
+	cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
+	cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
+	cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
+
+	LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
+
+	if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
+	{
+		cfi_command(bank, 0xf0, command);
+		if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+		{
+			return retval;
+		}
+		cfi_command(bank, 0xff, command);
+		if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
+		{
+			return retval;
+		}
+		LOG_ERROR("Could not probe bank: no QRY");
+		return ERROR_FLASH_BANK_INVALID;
+	}
+
+	return ERROR_OK;
+}
+
 static int cfi_probe(struct flash_bank_s *bank)
 {
 	cfi_flash_bank_t *cfi_info = bank->driver_priv;
@@ -2236,6 +2275,8 @@ static int cfi_probe(struct flash_bank_s *bank)
 	 */
 	if (cfi_info->not_cfi == 0)
 	{
+		int retval;
+
 		/* enter CFI query mode
 		 * according to JEDEC Standard No. 68.01,
 		 * a single bus sequence with address = 0x55, data = 0x98 should put
@@ -2243,33 +2284,21 @@ static int cfi_probe(struct flash_bank_s *bank)
 		 *
 		 * SST flashes clearly violate this, and we will consider them incompatbile for now
 		 */
-		cfi_command(bank, 0x98, command);
-		if ((retval = target_write_memory(target, flash_address(bank, 0, 0x55), bank->bus_width, 1, command)) != ERROR_OK)
-		{
-			return retval;
-		}
 
-		cfi_info->qry[0] = cfi_query_u8(bank, 0, 0x10);
-		cfi_info->qry[1] = cfi_query_u8(bank, 0, 0x11);
-		cfi_info->qry[2] = cfi_query_u8(bank, 0, 0x12);
-
-		LOG_DEBUG("CFI qry returned: 0x%2.2x 0x%2.2x 0x%2.2x", cfi_info->qry[0], cfi_info->qry[1], cfi_info->qry[2]);
-
-		if ((cfi_info->qry[0] != 'Q') || (cfi_info->qry[1] != 'R') || (cfi_info->qry[2] != 'Y'))
+		retval = cfi_query_string(bank, 0x55);
+		if (retval != ERROR_OK)
 		{
-			cfi_command(bank, 0xf0, command);
-			if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
-			{
-				return retval;
-			}
-			cfi_command(bank, 0xff, command);
-			if ((retval = target_write_memory(target, flash_address(bank, 0, 0x0), bank->bus_width, 1, command)) != ERROR_OK)
-			{
-				return retval;
-			}
-			LOG_ERROR("Could not probe bank: no QRY");
-			return ERROR_FLASH_BANK_INVALID;
+			/*
+			 * Spansion S29WS-N CFI query fix is to try 0x555 if 0x55 fails. Should
+			 * be harmless enough:
+			 *
+			 * http://www.infradead.org/pipermail/linux-mtd/2005-September/013618.html
+			 */
+			LOG_USER("Try workaround w/0x555 instead of 0x55 to get QRY.");
+			retval = cfi_query_string(bank, 0x555);
 		}
+		if (retval != ERROR_OK)
+			return retval;
 
 		cfi_info->pri_id = cfi_query_u16(bank, 0, 0x13);
 		cfi_info->pri_addr = cfi_query_u16(bank, 0, 0x15);

-----------------------------------------------------------------------

Summary of changes:
 src/flash/cfi.c |   77 +++++++++++++++++++++++++++++++++++++-----------------
 1 files changed, 53 insertions(+), 24 deletions(-)


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Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. 0.2.0-371-g36564d7

[Øyvind H. <go...@us...>]

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- Log -----------------------------------------------------------------
commit 36564d74505598c328fab91d0cfe415b0fc61676
Author: Øyvind Harboe <oyv...@zy...>
Date:   Wed Oct 14 11:14:04 2009 +0200

    Work in progress on arm11 reset. Assert srst.

diff --git a/src/target/arm11.c b/src/target/arm11.c
index f46e424..94d5fb1 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1200,18 +1200,62 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl
 int arm11_assert_reset(target_t *target)
 {
 	FNC_INFO;
+	int retval;
 
-	/* FIX! we really should assert srst here, but
-	 * how do we reset the target into the halted state?
-	 *
-	 * Also arm11 behaves "funny" when srst is asserted
-	 * (as of writing the rules are not understood).
-	 */
+	arm11_common_t * arm11 = target->arch_info;
+	retval = arm11_check_init(arm11, NULL);
+	if (retval != ERROR_OK)
+		return retval;
+
+	target->state = TARGET_UNKNOWN;
+
+	/* we would very much like to reset into the halted, state,
+	 * but resetting and halting is second best... */
 	if (target->reset_halt)
 	{
 		CHECK_RETVAL(target_halt(target));
 	}
 
+
+	/* srst is funny. We can not do *anything* else while it's asserted
+	 * and it has unkonwn side effects. Make sure no other code runs
+	 * meanwhile.
+	 *
+	 * Code below assumes srst:
+	 *
+	 * - Causes power-on-reset (but of what parts of the system?). Bug
+	 * in arm11?
+	 *
+	 * - Messes us TAP state without asserting trst.
+	 *
+	 * - There is another bug in the arm11 core. When you generate an access to
+	 * external logic (for example ddr controller via AHB bus) and that block
+	 * is not configured (perhaps it is still held in reset), that transaction
+	 * will never complete. This will hang arm11 core but it will also hang
+	 * JTAG controller. Nothing, short of srst assertion will bring it out of
+	 * this.
+	 *
+	 * Mysteries:
+	 *
+	 * - What should the PC be after an srst reset when starting in the halted
+	 * state?
+	 */
+
+	jtag_add_reset(0, 1);
+	jtag_add_reset(0, 0);
+
+	/* How long do we have to wait? */
+	jtag_add_sleep(5000);
+
+	/* un-mess up TAP state */
+	jtag_add_tlr();
+
+	retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+	{
+		return retval;
+	}
+
 	return ERROR_OK;
 }
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm11.c |   56 ++++++++++++++++++++++++++++++++++++++++++++++-----
 1 files changed, 50 insertions(+), 6 deletions(-)


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[Øyvind H. <go...@us...>]

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- Log -----------------------------------------------------------------
commit 77ca2f3a702c7a9cfceba14166042a0ed09947fe
Author: Øyvind Harboe <oyv...@zy...>
Date:   Wed Oct 14 10:34:41 2009 +0200

    iMX target config script's ported from Freescale BSP.

diff --git a/tcl/board/imx31pdk.cfg b/tcl/board/imx31pdk.cfg
index e000e3c..4dfa4db 100644
--- a/tcl/board/imx31pdk.cfg
+++ b/tcl/board/imx31pdk.cfg
@@ -1,59 +1,47 @@
 # The IMX31PDK eval board has a single IMX31 chip
 source [find target/imx31.cfg]
+source [find target/imx.cfg]
 $_TARGETNAME configure -event reset-init { imx31pdk_init }
 
 proc imx31pdk_init { } {
+
+	imx3x_reset
+
 	# This setup puts RAM at 0x80000000
 
-	# ========================================
-	# Init CCM
-	# ========================================
 	mww 0x53FC0000 0x040
 	mww 0x53F80000 0x074B0B7D
-
-	sleep 100
-
-	# ========================================
+	
 	# 399MHz - 26MHz input, PD=1,MFI=7, MFN=27, MFD=40
-	# ========================================
-	mww 0x53F80004 0xFF871D50
-	mww 0x53F80010 0x00271C1B
-
-	# ========================================
-	# Configure CPLD on CS5
-	# ========================================
-	mww 0xb8002050 0x0000DCF6
-	mww 0xb8002054 0x444A4541
-	mww 0xb8002058 0x44443302
-
-	# ========================================
+	#mww 0x53F80004 0xFF871D50
+	#mww 0x53F80010 0x00271C1B
+	
+	# Start 16 bit NorFlash Initialization on CS0
+	mww 0xb8002000 0x0000CC03
+	mww 0xb8002004 0xa0330D01
+	mww 0xb8002008 0x00220800
+	
+	# Configure CPLD on CS4
+	mww 0xb8002040 0x0000DCF6
+	mww 0xb8002044 0x444A4541
+	mww 0xb8002048 0x44443302
+	
 	# SDCLK
-	# ========================================
 	mww 0x43FAC26C 0
-
-	# ========================================
+	
 	# CAS
-	# ========================================
 	mww 0x43FAC270 0
-
-	# ========================================
+	
 	# RAS
-	# ========================================
 	mww 0x43FAC274 0
-
-	# ========================================
+	
 	# CS2 (CSD0)
-	# ========================================
 	mww 0x43FAC27C 0x1000
-
-	# ========================================
+	
 	# DQM3
-	# ========================================
 	mww 0x43FAC284 0
-
-	# ========================================
+	
 	# DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC)
-	# ========================================
 	mww 0x43FAC288 0
 	mww 0x43FAC28C 0
 	mww 0x43FAC290 0
@@ -76,10 +64,8 @@ proc imx31pdk_init { } {
 	mww 0x43FAC2D4 0
 	mww 0x43FAC2D8 0
 	mww 0x43FAC2DC 0
-
-	# ========================================
-	# Initialization script for 32 bit DDR on MX31 PDK
-	# ========================================
+	
+	# Initialization script for 32 bit DDR on MX31 ADS
 	mww 0xB8001010 0x00000004
 	mww 0xB8001004 0x006ac73a
 	mww 0xB8001000 0x92100000
diff --git a/tcl/board/imx35pdk.cfg b/tcl/board/imx35pdk.cfg
index 7724bac..e5891c8 100644
--- a/tcl/board/imx35pdk.cfg
+++ b/tcl/board/imx35pdk.cfg
@@ -1,35 +1,11 @@
 # The IMX35PDK eval board has a single IMX35 chip
 source [find target/imx35.cfg]
+source [find target/imx.cfg]
 $_TARGETNAME configure -event reset-init { imx35pdk_init }
 
-
-global TARGETNAME 
-set TARGETNAME $_TARGETNAME
-
-# rewrite commands of the form below to arm11 mcr...
-#	Data.Set c15:0x042f %long 0x40000015
-proc setc15 {regs value} {
-	global TARGETNAME 
-
-	echo [format "set p15 0x%04x, 0x%08x" $regs $value] 
-
-	arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value 
-}
-
 proc imx35pdk_init { } {
 	
-	# this reset script comes from the Freescale PDK
-	#
-	# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX35PDK
-	
-	echo "Target Setup: initialize DRAM controller and peripherals"
-	
-#	Data.Set c15:0x01 %long 0x00050078
-	setc15 0x01 0x00050078
-	
-	echo "configuring CP15 for enabling the peripheral bus"
-#	Data.Set c15:0x042f %long 0x40000015
-	setc15 0x042f 0x40000015
+	imx3x_reset
 	
 	mww 0x43f00040 0x00000000
 	mww 0x43f00044 0x00000000
diff --git a/tcl/target/imx.cfg b/tcl/target/imx.cfg
new file mode 100644
index 0000000..16773fa
--- /dev/null
+++ b/tcl/target/imx.cfg
@@ -0,0 +1,30 @@
+# utility fn's for Freescale i.MX series
+
+global TARGETNAME 
+set TARGETNAME $_TARGETNAME
+
+# rewrite commands of the form below to arm11 mcr...
+#	Data.Set c15:0x042f %long 0x40000015
+proc setc15 {regs value} {
+	global TARGETNAME 
+
+	echo [format "set p15 0x%04x, 0x%08x" $regs $value] 
+
+	arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value 
+}
+
+
+proc imx3x_reset {} {
+	# this reset script comes from the Freescale PDK
+	#
+	# http://www.freescale.com/webapp/sps/site/prod_summary.jsp?code=IMX35PDK
+	
+	echo "Target Setup: initialize DRAM controller and peripherals"
+	
+#	Data.Set c15:0x01 %long 0x00050078
+	setc15 0x01 0x00050078
+	
+	echo "configuring CP15 for enabling the peripheral bus"
+#	Data.Set c15:0x042f %long 0x40000015
+	setc15 0x042f 0x40000015
+}

commit bc5eae23c5b7e14edc273da30bf4bce06a269a9b
Author: David Brownell <da...@pa...>
Date:   Wed Oct 14 09:32:42 2009 +0200

    Fix problems building xscale_debug.S

diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 86716dc..a2c34f0 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -10,6 +10,12 @@ AM_CPPFLAGS = \
 	-I$(top_srcdir)/src/jtag \
 	-I$(top_srcdir)/src/xsvf
 
+# ideally this would be specific to xscale_debug.S ...
+libtarget_la_CCASFLAGS = \
+       -Wa,-I$(top_srcdir)/src/target \
+       $(AM_CCASFLAGS)
+
+
 METASOURCES = AUTO
 noinst_LTLIBRARIES = libtarget.la
 libtarget_la_SOURCES = \

-----------------------------------------------------------------------

Summary of changes:
 src/target/Makefile.am |    6 ++++
 tcl/board/imx31pdk.cfg |   64 ++++++++++++++++++-----------------------------
 tcl/board/imx35pdk.cfg |   28 +-------------------
 tcl/target/imx.cfg     |   30 ++++++++++++++++++++++
 4 files changed, 63 insertions(+), 65 deletions(-)
 create mode 100644 tcl/target/imx.cfg


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commit 5ae48dba487b76162c2d108193241e34330abe5b
Author: David Brownell <dbr...@us...>
Date:   Wed Oct 14 02:00:34 2009 -0700

    omap2420.cfg updates
    
    Remove ircapture/mask attributes.  Add "srst_nogate".
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/tcl/target/omap2420.cfg b/tcl/target/omap2420.cfg
index 866b4a3..a579866 100644
--- a/tcl/target/omap2420.cfg
+++ b/tcl/target/omap2420.cfg
@@ -8,12 +8,13 @@ if { [info exists CHIPNAME] } {
 }
 
 # NOTE: likes slowish clock on reset (1.5 MBit/s or less) or use RCLK
+reset_config srst_nogate
 
 # Subsidiary TAP:  ARM7TDMIr4 plus imaging ... must add via ICEpick (addr 6).
-jtag newtap $_CHIPNAME iva -irlen 4 -ircapture 0x1 -irmask 0x3f -disable
+jtag newtap $_CHIPNAME iva -irlen 4 -disable
 
 # Subsidiary TAP: C55x DSP ... must add via ICEpick (addr 2).
-jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x1 -irmask 0x3f -disable
+jtag newtap $_CHIPNAME dsp -irlen 38 -disable
 
 # Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
 if { [info exists ETB_TAPID ] } {
@@ -21,7 +22,7 @@ if { [info exists ETB_TAPID ] } {
 } else {
    set _ETB_TAPID 0x2b900f0f
 }
-jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETB_TAPID
+jtag newtap $_CHIPNAME etb -irlen 4 -expected-id $_ETB_TAPID
 
 # Subsidiary TAP: ARM1136jf-s with scan chains for ARM Debug, EmbeddedICE-RT, ETM.
 if { [info exists CPU_TAPID ] } {
@@ -29,7 +30,7 @@ if { [info exists CPU_TAPID ] } {
 } else {
    set _CPU_TAPID 0x07b3602f
 }
-jtag newtap $_CHIPNAME arm -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPU_TAPID
+jtag newtap $_CHIPNAME arm -irlen 5 -expected-id $_CPU_TAPID
 
 # Primary TAP: ICEpick-B (JTAG route controller) and boundary scan
 if { [info exists JRC_TAPID ] } {
@@ -37,7 +38,7 @@ if { [info exists JRC_TAPID ] } {
 } else {
    set _JRC_TAPID 0x01ce4801
 }
-jtag newtap $_CHIPNAME jrc -irlen 2 -ircapture 0x1 -irmask 0x3 -expected-id $_JRC_TAPID
+jtag newtap $_CHIPNAME jrc -irlen 2 -expected-id $_JRC_TAPID
 
 # GDB target:  the ARM.
 set _TARGETNAME $_CHIPNAME.arm

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/omap2420.cfg |   11 ++++++-----
 1 files changed, 6 insertions(+), 5 deletions(-)


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commit 4bc3132a1e8229e6475fa64ce095330a71cb10ae
Author: Lennert Buytenhek <bu...@wa...>
Date:   Tue Oct 13 22:48:18 2009 +0200

    fix detection of PLD instructions
    
    Signed-off-by: Lennert Buytenhek <bu...@ma...>
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 2755cc2..5b0046b 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -110,7 +110,7 @@ static int evaluate_pld(uint32_t opcode,
 		uint32_t address, arm_instruction_t *instruction)
 {
 	/* PLD */
-	if ((opcode & 0x0d70f0000) == 0x0550f000)
+	if ((opcode & 0x0d70f000) == 0x0550f000)
 	{
 		instruction->type = ARM_PLD;
 

commit 0e1d222328e4990d6aea488bbff618622d53b624
Author: Lennert Buytenhek <bu...@wa...>
Date:   Tue Oct 13 20:27:03 2009 +0200

    fix pass_condition() LE condition code check
    
    The LE check is obviously buggy (as easily triggered during some
    testing), but I didn't audit the rest of the cases.
    
    Signed-off-by: Lennert Buytenhek <bu...@ma...>
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_simulator.c b/src/target/arm_simulator.c
index 7c610a5..93fb3dd 100644
--- a/src/target/arm_simulator.c
+++ b/src/target/arm_simulator.c
@@ -243,9 +243,9 @@ int pass_condition(uint32_t cpsr, uint32_t opcode)
 			else
 				return 0;
 		case 0xd:	/* LE */
-			if ((cpsr & 0x40000000) &&
-				(((cpsr & 0x80000000) && !(cpsr & 0x10000000))
-				|| (!(cpsr & 0x80000000) && (cpsr & 0x10000000))))
+			if ((cpsr & 0x40000000) ||
+				((cpsr & 0x80000000) && !(cpsr & 0x10000000))
+				|| (!(cpsr & 0x80000000) && (cpsr & 0x10000000)))
 				return 1;
 			else
 				return 0;

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_disassembler.c |    2 +-
 src/target/arm_simulator.c    |    6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)


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- Log -----------------------------------------------------------------
commit ab8712e5447ddd5fcdde20e1a6d98b001740d48d
Author: David Brownell <dbr...@us...>
Date:   Tue Oct 13 10:55:24 2009 -0700

    cosmetic cleanup in TMS tables
    
    Cleanup comments and layout/whitespace in the TMS tables.
    Table contents stayed the same (ignoring whitespace).
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/jtag/interface.c b/src/jtag/interface.c
index fee1255..e83a772 100644
--- a/src/jtag/interface.c
+++ b/src/jtag/interface.c
@@ -133,13 +133,10 @@ static const struct tms_sequences old_tms_seqs[6][6] =		/*  [from_state_ndx][to_
 {
 	/* value clocked to TMS to move from one of six stable states to another.
 	 * N.B. OOCD clocks TMS from LSB first, so read these right-to-left.
-	 * N.B. These values are tightly bound to the table in tap_get_tms_path_len().
 	 * N.B. Reset only needs to be 0b11111, but in JLink an even byte of 1's is more stable.
 	 * These extra ones cause no TAP state problem, because we go into reset and stay in reset.
 	 */
 
-
-
 	/* to state: */
 	/*	RESET			IDLE			DRSHIFT			DRPAUSE			IRSHIFT			IRPAUSE 	*/		/* from state: */
 	{	B8(1111111,7),	B8(0000000,7),	B8(0010111,7),	B8(0001010,7),	B8(0011011,7),	B8(0010110,7) },	/* RESET */
@@ -168,24 +165,33 @@ static const struct tms_sequences short_tms_seqs[6][6] =		/*  [from_state_ndx][t
 
 		state specific comments:
 		------------------------
-		*->RESET		   tried the 5 bit reset and it gave me problems, 7 bits seems to
+		*->RESET	   tried the 5 bit reset and it gave me problems, 7 bits seems to
 					   work better on ARM9 with ft2232 driver.  (Dick)
 
 		RESET->DRSHIFT add 1 extra clock cycles in the RESET state before advancing.
 						needed on ARM9 with ft2232 driver.  (Dick)
+						(For a total of *THREE* extra clocks in RESET; NOP.)
 
 		RESET->IRSHIFT add 1 extra clock cycles in the RESET state before advancing.
 						needed on ARM9 with ft2232 driver.  (Dick)
+						(For a total of *TWO* extra clocks in RESET; NOP.)
+
+		RESET->*		always adds one or more clocks in the target state,
+						which should be NOPS; except shift states which (as
+						noted above) add those clocks in RESET.
+
+		The X-to-X transitions always add clocks; from *SHIFT, they go
+		via IDLE and thus *DO HAVE SIDE EFFECTS* (capture and update).
 	*/
 
 	/* to state: */
-	/*	RESET			IDLE				DRSHIFT			DRPAUSE			IRSHIFT	  		IRPAUSE */			/* from state: */
-	{	B8(1111111,7),	B8(0000000,7),	B8(0010111,7),		B8(0001010,7),	B8(0011011,7),	B8(0010110,7) },	/* RESET */
-	{	B8(1111111,7),	B8(0000000,7),	B8(001,3),			B8(0101,4),		B8(0011,4),  	B8(01011,5) },		/* IDLE */
-	{	B8(1111111,7),	B8(011,3),		B8(00111,5),		B8(01,2),		B8(001111,6),	B8(0101111,7) },	/* DRSHIFT */
-	{	B8(1111111,7),	B8(011,3),		B8(01,2),   		B8(0,1),		B8(001111,6),	B8(0101111,7) },	/* DRPAUSE */
-	{	B8(1111111,7),	B8(011,3),		B8(00111,5),		B8(010111,6), 	B8(001111,6),	B8(01,2) },			/* IRSHIFT */
-	{	B8(1111111,7),	B8(011,3),		B8(00111,5),		B8(010111,6),	B8(01,2),		B8(0,1) } 			/* IRPAUSE */
+	/*	RESET			IDLE			DRSHIFT			DRPAUSE			IRSHIFT			IRPAUSE */			/* from state: */
+	{	B8(1111111,7),	B8(0000000,7),	B8(0010111,7),	B8(0001010,7),	B8(0011011,7),	B8(0010110,7) },	/* RESET */
+	{	B8(1111111,7),	B8(0000000,7),	B8(001,3),		B8(0101,4),		B8(0011,4),		B8(01011,5) },		/* IDLE */
+	{	B8(1111111,7),	B8(011,3),		B8(00111,5),	B8(01,2),		B8(001111,6),	B8(0101111,7) },	/* DRSHIFT */
+	{	B8(1111111,7),	B8(011,3),		B8(01,2),		B8(0,1),		B8(001111,6),	B8(0101111,7) },	/* DRPAUSE */
+	{	B8(1111111,7),	B8(011,3),		B8(00111,5),	B8(010111,6),	B8(001111,6),	B8(01,2) },			/* IRSHIFT */
+	{	B8(1111111,7),	B8(011,3),		B8(00111,5),	B8(010111,6),	B8(01,2),		B8(0,1)}			/* IRPAUSE */
 
 };
 

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/interface.c |   28 +++++++++++++++++-----------
 1 files changed, 17 insertions(+), 11 deletions(-)


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- Log -----------------------------------------------------------------
commit 497970237790fc3341854556cfc59942ad80d066
Author: Yauheni Kaliuta <y.k...@gm...>
Date:   Tue Oct 13 20:00:46 2009 +0300

    Cleanup: nuke trailling whitespaces
    
    Signed-off-by: Yauheni Kaliuta <y.k...@gm...>

diff --git a/contrib/libdcc/dcc_stdio.c b/contrib/libdcc/dcc_stdio.c
index a25e7dd..08a49ab 100644
--- a/contrib/libdcc/dcc_stdio.c
+++ b/contrib/libdcc/dcc_stdio.c
@@ -99,7 +99,7 @@ void dbg_write_u16(const unsigned short *val, long len)
 
 	while (len > 0)
 	{
-		dcc_data = val[0] 
+		dcc_data = val[0]
 			| ((len > 1) ? val[1] << 16: 0x0000);
 
 		dbg_write(dcc_data);
@@ -145,7 +145,7 @@ void dbg_write_str(const char *msg)
 			| ((len > 2) ? msg[2] << 16 : 0x00)
 			| ((len > 3) ? msg[3] << 24 : 0x00);
 		dbg_write(dcc_data);
-		
+
 		msg += 4;
 		len -= 4;
 	}
diff --git a/contrib/libdcc/example.c b/contrib/libdcc/example.c
index d456f39..0814c9c 100644
--- a/contrib/libdcc/example.c
+++ b/contrib/libdcc/example.c
@@ -23,11 +23,11 @@
 #include "dcc_stdio.h"
 
 /* enable openocd debugmsg at the gdb prompt:
- * monitor target_request debugmsgs enable 
- * 
+ * monitor target_request debugmsgs enable
+ *
  * create a trace point:
  * monitor trace point 1
- * 
+ *
  * to show how often the trace point was hit:
  * monitor trace point
 */
diff --git a/ecosflash/flash.c b/ecosflash/flash.c
index 81f7d07..c8ac353 100644
--- a/ecosflash/flash.c
+++ b/ecosflash/flash.c
@@ -53,7 +53,7 @@ int init()
 		*t=0;
 	}
 	return flash_init((_printf *)&myprintf);
-	
+
 }
 
 
@@ -68,15 +68,15 @@ int checkFlash(void *addr, int len)
 }
 
 
-int erase(void *address, int len)	
+int erase(void *address, int len)
 {
 	int retval;
 	void *failAddress;
-	
+
 	retval=checkFlash(address, len);
 	if (retval!=0)
 		return retval;
-	
+
 	retval=init();
 	if (retval!=0)
 		return retval;
@@ -88,14 +88,14 @@ int erase(void *address, int len)
 extern char _end;
 
 // Data follows immediately after program, long word aligned.
-int program(void *buffer, void *address, int len)	
+int program(void *buffer, void *address, int len)
 {
 	int retval;
 	void *failAddress;
 	retval=checkFlash(address, len);
 	if (retval!=0)
 		return retval;
-	
+
 	retval=init();
 	if (retval!=0)
 		return retval;
diff --git a/src/flash/lpc2900.c b/src/flash/lpc2900.c
index e39c531..902180c 100644
--- a/src/flash/lpc2900.c
+++ b/src/flash/lpc2900.c
@@ -528,7 +528,7 @@ static uint32_t lpc2900_calc_tr( uint32_t clock, uint32_t time )
 	 * FPTR.TR = -------------------------------
 	 *                         512
 	 *
-	 * The result is the 
+	 * The result is the
 	 */
 
 	uint32_t tr_val = (uint32_t)((((time / 1e6) * clock) + 511.0) / 512.0);
diff --git a/src/target/arm11.c b/src/target/arm11.c
index c41adfa..f46e424 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1203,7 +1203,7 @@ int arm11_assert_reset(target_t *target)
 
 	/* FIX! we really should assert srst here, but
 	 * how do we reset the target into the halted state?
-	 * 
+	 *
 	 * Also arm11 behaves "funny" when srst is asserted
 	 * (as of writing the rules are not understood).
 	 */
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 499d592..1e0e02f 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -176,7 +176,7 @@ reg_t armv7a_gdb_dummy_fp_reg =
 void armv7a_show_fault_registers(target_t *target)
 {
 	uint32_t dfsr, ifsr, dfar, ifar;
-	
+
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	armv7a_common_t *armv7a = armv4_5->arch_info;
@@ -186,9 +186,9 @@ void armv7a_show_fault_registers(target_t *target)
 	armv7a->read_cp15(target, 0, 0, 6, 0, &dfar);
 	armv7a->read_cp15(target, 0, 2, 6, 0, &ifar);
 
-	LOG_USER("Data fault registers        DFSR: %8.8" PRIx32 
+	LOG_USER("Data fault registers        DFSR: %8.8" PRIx32
 			", DFAR: %8.8" PRIx32, dfsr, dfar);
-	LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32 
+	LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
 			", IFAR: %8.8" PRIx32, ifsr, ifar);
 
 }
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 846d90c..025a468 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -140,13 +140,13 @@ int cortex_a8_init_debug_access(target_t *target)
 	/* Clear Sticky Power Down status Bit in PRSR to enable access to
 	   the registers in the Core Power Domain */
 	retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
-	/* Enabling of instruction execution in debug mode is done in debug_entry code */ 
-	
+	/* Enabling of instruction execution in debug mode is done in debug_entry code */
+
 	/* Resync breakpoint registers */
-	
+
 	/* Since this is likley called from init or reset, update targtet state information*/
 	cortex_a8_poll(target);
-	
+
 	return retval;
 }
 
@@ -254,7 +254,7 @@ int cortex_a8_write_cp(target_t *target, uint32_t value,
 		/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode  0xEE000E15 */
 		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
 	}
-	
+
 	retval = mem_ap_write_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DTRRX, value);
 	/* Move DTRRX to r0 */
@@ -331,7 +331,7 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	armv7a_common_t *armv7a = armv4_5->arch_info;
 	swjdp_common_t *swjdp = &armv7a->swjdp_info;
-	
+
 	LOG_DEBUG("register %i, value 0x%08" PRIx32, regnum, value);
 
 	/* Check that DCCRX is not full */
@@ -343,7 +343,7 @@ int cortex_a8_dap_write_coreregister_u32(target_t *target, uint32_t value, int r
 		/* Clear DCCRX with MCR(p14, 0, Rd, c0, c5, 0), opcode  0xEE000E15 */
 		cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
 	}
-	
+
 	if (Rd > 16)
 		return retval;
 
@@ -1237,7 +1237,7 @@ int cortex_a8_assert_reset(target_t *target)
 	armv4_5_invalidate_core_regs(target);
 
 	target->state = TARGET_RESET;
-	
+
 	return ERROR_OK;
 }
 
@@ -1444,7 +1444,7 @@ int cortex_a8_examine(struct target_s *target)
 	uint32_t didr, ctypr, ttypr, cpuid;
 
 	LOG_DEBUG("TODO");
-	
+
 	/* Here we shall insert a proper ROM Table scan */
 	armv7a->debug_base = OMAP3530_DEBUG_BASE;
 
@@ -1521,7 +1521,7 @@ int cortex_a8_examine(struct target_s *target)
 
 	/* Configure core debug access */
 	cortex_a8_init_debug_access(target);
-	
+
 	target->type->examined = 1;
 
 	return retval;

-----------------------------------------------------------------------

Summary of changes:
 contrib/libdcc/dcc_stdio.c |    4 ++--
 contrib/libdcc/example.c   |    6 +++---
 ecosflash/flash.c          |   12 ++++++------
 src/flash/lpc2900.c        |    2 +-
 src/target/arm11.c         |    2 +-
 src/target/armv7a.c        |    6 +++---
 src/target/cortex_a8.c     |   20 ++++++++++----------
 7 files changed, 26 insertions(+), 26 deletions(-)


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- Log -----------------------------------------------------------------
commit a2fd31eb66f9d56b00ab8b7e15e8875ae5125089
Author: Yauheni Kaliuta <y.k...@gm...>
Date:   Sun Oct 11 18:27:27 2009 +0300

    Do not replace virt2phys with the default one if it was assigned
    
    Signed-off-by: Yauheni Kaliuta <y.k...@gm...>

diff --git a/src/target/target.c b/src/target/target.c
index 2b7d7e2..7763b95 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -698,7 +698,6 @@ int target_init(struct command_context_s *cmd_ctx)
 		{
 			target->type->virt2phys = default_virt2phys;
 		}
-		target->type->virt2phys = default_virt2phys;
 		/* a non-invasive way(in terms of patches) to add some code that
 		 * runs before the type->write/read_memory implementation
 		 */

-----------------------------------------------------------------------

Summary of changes:
 src/target/target.c |    1 -
 1 files changed, 0 insertions(+), 1 deletions(-)


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commit 530281c469e58e6f37eb500a5562f49fb7d9857e
Author: Øyvind Harboe <oyv...@zy...>
Date:   Tue Oct 13 13:44:15 2009 +0200

    Retired gdb_attach. gdb-detach event covers this functionality.

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 479aa17..fd4f9f7 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1638,11 +1638,6 @@ GDB behaviour is not sufficient.  GDB normally uses hardware
 breakpoints if the memory map has been set up for flash regions.
 @end deffn
 
-@deffn {Config Command} gdb_detach (@option{resume}|@option{reset}|@option{halt}|@option{nothing})
-Configures what OpenOCD will do when GDB detaches from the daemon.
-Default behaviour is @option{resume}.
-@end deffn
-
 @anchor{gdb_flash_program}
 @deffn {Config Command} gdb_flash_program (@option{enable}|@option{disable})
 Set to @option{enable} to cause OpenOCD to program the flash memory when a
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index ad09a0e..adf5c68 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -52,17 +52,6 @@ static const char *DIGITS = "0123456789abcdef";
 static void gdb_log_callback(void *priv, const char *file, int line,
 		const char *function, const char *string);
 
-enum gdb_detach_mode
-{
-	GDB_DETACH_RESUME,
-	GDB_DETACH_RESET,
-	GDB_DETACH_HALT,
-	GDB_DETACH_NOTHING
-};
-
-/* target behaviour on gdb detach */
-enum gdb_detach_mode detach_mode = GDB_DETACH_RESUME;
-
 /* number of gdb connections, mainly to supress gdb related debugging spam
  * in helper/log.c when no gdb connections are actually active */
 int gdb_actual_connections;
@@ -1960,29 +1949,11 @@ int gdb_v_packet(connection_t *connection, target_t *target, char *packet, int p
 
 int gdb_detach(connection_t *connection, target_t *target)
 {
+	gdb_service_t *gdb_service = connection->service->priv;
 
-	switch (detach_mode)
-	{
-		case GDB_DETACH_RESUME:
-			target_handle_event(target, TARGET_EVENT_OLD_pre_resume);
-			target_resume(target, 1, 0, 1, 0);
-			break;
-
-		case GDB_DETACH_RESET:
-			/* FIX?? make this configurable?? */
-			target_process_reset(connection->cmd_ctx, RESET_HALT);
-			break;
-
-		case GDB_DETACH_HALT:
-			target_halt(target);
-			break;
-
-		case GDB_DETACH_NOTHING:
-			break;
-	}
+	target_call_event_callbacks(gdb_service->target, TARGET_EVENT_GDB_DETACH);
 
-	gdb_put_packet(connection, "OK", 2);
-	return ERROR_OK;
+	return gdb_put_packet(connection, "OK", 2);
 }
 
 static void gdb_log_callback(void *priv, const char *file, int line,
@@ -2311,37 +2282,6 @@ int handle_gdb_port_command(struct command_context_s *cmd_ctx, char *cmd, char *
 	return ERROR_OK;
 }
 
-int handle_gdb_detach_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
-{
-	if (argc == 1)
-	{
-		if (strcmp(args[0], "resume") == 0)
-		{
-			detach_mode = GDB_DETACH_RESUME;
-			return ERROR_OK;
-		}
-		else if (strcmp(args[0], "reset") == 0)
-		{
-			detach_mode = GDB_DETACH_RESET;
-			return ERROR_OK;
-		}
-		else if (strcmp(args[0], "halt") == 0)
-		{
-			detach_mode = GDB_DETACH_HALT;
-			return ERROR_OK;
-		}
-		else if (strcmp(args[0], "nothing") == 0)
-		{
-			detach_mode = GDB_DETACH_NOTHING;
-			return ERROR_OK;
-		}
-		else
-			LOG_WARNING("invalid gdb_detach configuration directive: %s", args[0]);
-	}
-
-	return ERROR_COMMAND_SYNTAX_ERROR;
-}
-
 int handle_gdb_memory_map_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
 {
 	if (argc == 1)
@@ -2445,9 +2385,6 @@ int gdb_register_commands(command_context_t *command_context)
 			COMMAND_ANY, "next stepi will return immediately allowing GDB fetch register state without affecting target state");
 	register_command(command_context, NULL, "gdb_port", handle_gdb_port_command,
 			COMMAND_ANY, "daemon configuration command gdb_port");
-	register_command(command_context, NULL, "gdb_detach", handle_gdb_detach_command,
-			COMMAND_CONFIG, "resume/reset/halt/nothing - "
-			"specify behavior when GDB detaches from the target");
 	register_command(command_context, NULL, "gdb_memory_map", handle_gdb_memory_map_command,
 			COMMAND_CONFIG, "enable or disable memory map");
 	register_command(command_context, NULL, "gdb_flash_program", handle_gdb_flash_program_command,

commit 77ca1a4c835a0f6ea0b45ff67c362734ce5331f4
Author: Øyvind Harboe <oyv...@zy...>
Date:   Tue Oct 13 13:13:29 2009 +0200

    Missing type for eCos.

diff --git a/src/helper/types.h b/src/helper/types.h
index 21a6a33..86b62c2 100644
--- a/src/helper/types.h
+++ b/src/helper/types.h
@@ -152,6 +152,7 @@ typedef uint64_t uintmax_t;
 #define INT64_MIN (-INT64_MAX - 1LL)
 #define UINT64_MAX (__CONCAT(INT64_MAX, U) * 2ULL + 1ULL)
 
+#define ULLONG_MAX 18446744073709551615
 
 /* C99, eCos is C90 compliant (with bits of C99) */
 #define isblank(c) ((c) == ' ' || (c) == '\t')

commit 7e424445c1a0caf979e4c0288be111592dd47e57
Author: Øyvind Harboe <oyv...@zy...>
Date:   Tue Oct 13 12:22:23 2009 +0200

    Fix warning.

diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index 57685cf..c9812a1 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -590,7 +590,7 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, uint32_t opcode,
 	Readies = (uint8_t *) malloc(bytes);
 	if (Readies == NULL)
 	{
-		LOG_ERROR("Out of memory allocating %d bytes", bytes);
+		LOG_ERROR("Out of memory allocating " ZU " bytes", bytes);
 		return ERROR_FAIL;
 	}
 

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi          |    5 ---
 src/helper/types.h        |    1 +
 src/server/gdb_server.c   |   69 ++-------------------------------------------
 src/target/arm11_dbgtap.c |    2 +-
 4 files changed, 5 insertions(+), 72 deletions(-)


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- Log -----------------------------------------------------------------
commit 6bff28fbdb8ae97d29608e15deee8bcf9f9c2316
Author: Øyvind Harboe <oyv...@zy...>
Date:   Tue Oct 13 12:06:55 2009 +0200

    Delete commented out code. Add a bit of error checking.

diff --git a/TODO b/TODO
index 6521c60..a57ed24 100644
--- a/TODO
+++ b/TODO
@@ -138,11 +138,9 @@ https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
 - ARM923EJS:
   - reset run/halt/step is not robust; needs testing to map out problems.
 - ARM11 improvements (MB?)
+  - add support for asserting srst to reset the core.
   - Single stepping works, but should automatically
   use hardware stepping if available.
-  - hunt down and add timeouts to all infinite loops, e.g. arm11_run_instr_no_data would
-    lock up in infinite loop if e.g. an "mdh" command tries to read memory from invalid memory location.
-    Try mdh 0x40000000 on i.MX31 PDK
   - mdb can return garbage data if read byte operation fails for
   a memory region(16 & 32 byte access modes may be supported). Is this
   a bug in the .MX31 PDK init script? Try on i.MX31 PDK: 
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 36ed6b8..c41adfa 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -608,6 +608,13 @@ int arm11_leave_debug_state(arm11_common_t * arm11)
 
 		if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
 		{
+			/*
+			The wDTR/rDTR two registers that are used to send/receive data to/from
+			the core in tandem with corresponding instruction codes that are
+			written into the core. The RDTR FULL/WDTR FULL flag indicates that the
+			registers hold data that was written by one side (CPU or JTAG) and not
+			read out by the other side.
+			*/
 			LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
 			return ERROR_FAIL;
 		}
@@ -702,9 +709,6 @@ int arm11_poll(struct target_s *target)
 
 	arm11_common_t * arm11 = target->arch_info;
 
-	if (arm11->trst_active)
-		return ERROR_OK;
-
 	uint32_t	dscr;
 
 	CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
@@ -784,12 +788,6 @@ int arm11_halt(struct target_s *target)
 		return ERROR_OK;
 	}
 
-	if (arm11->trst_active)
-	{
-		arm11->halt_requested = true;
-		return ERROR_OK;
-	}
-
 	arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
 
 	CHECK_RETVAL(jtag_execute_queue());
@@ -1199,22 +1197,16 @@ int arm11_step(struct target_s *target, int current, uint32_t address, int handl
 	return ERROR_OK;
 }
 
-/* target reset control */
-int arm11_assert_reset(struct target_s *target)
+int arm11_assert_reset(target_t *target)
 {
 	FNC_INFO;
 
-#if 0
-	/* assert reset lines */
-	/* resets only the DBGTAP, not the ARM */
-
-	jtag_add_reset(1, 0);
-	jtag_add_sleep(5000);
-
-	arm11_common_t * arm11 = target->arch_info;
-	arm11->trst_active = true;
-#endif
-
+	/* FIX! we really should assert srst here, but
+	 * how do we reset the target into the halted state?
+	 * 
+	 * Also arm11 behaves "funny" when srst is asserted
+	 * (as of writing the rules are not understood).
+	 */
 	if (target->reset_halt)
 	{
 		CHECK_RETVAL(target_halt(target));
@@ -1223,25 +1215,8 @@ int arm11_assert_reset(struct target_s *target)
 	return ERROR_OK;
 }
 
-int arm11_deassert_reset(struct target_s *target)
+int arm11_deassert_reset(target_t *target)
 {
-	FNC_INFO;
-
-#if 0
-	LOG_DEBUG("target->state: %s",
-		target_state_name(target));
-
-
-	/* deassert reset lines */
-	jtag_add_reset(0, 0);
-
-	arm11_common_t * arm11 = target->arch_info;
-	arm11->trst_active = false;
-
-	if (arm11->halt_requested)
-		return arm11_halt(target);
-#endif
-
 	return ERROR_OK;
 }
 
@@ -1807,6 +1782,8 @@ int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target
 /* talk to the target and set things up */
 int arm11_examine(struct target_s *target)
 {
+	int retval;
+
 	FNC_INFO;
 
 	arm11_common_t * arm11 = target->arch_info;
@@ -1874,7 +1851,9 @@ int arm11_examine(struct target_s *target)
 	 * as suggested by the spec.
 	 */
 
-	arm11_check_init(arm11, NULL);
+	retval = arm11_check_init(arm11, NULL);
+	if (retval != ERROR_OK)
+		return retval;
 
 	target_set_examined(target);
 
diff --git a/src/target/arm11.h b/src/target/arm11.h
index c93e5ab..61c5f7f 100644
--- a/src/target/arm11.h
+++ b/src/target/arm11.h
@@ -98,10 +98,6 @@ typedef struct arm11_common_s
 	uint32_t		last_dscr;		/**< Last retrieved DSCR value;
 							     Use only for debug message generation		*/
 
-	bool	trst_active;
-	bool	halt_requested;					/**< Keep track if arm11_halt() calls occured
-												 during reset. Otherwise do it ASAP. */
-
 	bool	simulate_reset_on_next_halt;	/**< Perform cleanups of the ARM state on next halt */
 
 	/** \name Shadow registers to save processor state */

commit adefaa944eac21156150a809b739cca692901db7
Author: Øyvind Harboe <oyv...@zy...>
Date:   Tue Oct 13 12:02:09 2009 +0200

    arm11 seems to gate JTAG when srst is asserted

diff --git a/tcl/target/imx31.cfg b/tcl/target/imx31.cfg
index f579d6e..61a2925 100644
--- a/tcl/target/imx31.cfg
+++ b/tcl/target/imx31.cfg
@@ -1,7 +1,7 @@
 # imx31 config
 #
 
-reset_config trst_and_srst srst_nogate
+reset_config trst_and_srst srst_gates_jtag
 
 if { [info exists CHIPNAME] } {
    set  _CHIPNAME $CHIPNAME
diff --git a/tcl/target/imx35.cfg b/tcl/target/imx35.cfg
index 800e142..32748c5 100644
--- a/tcl/target/imx35.cfg
+++ b/tcl/target/imx35.cfg
@@ -1,8 +1,7 @@
 # imx35 config
 #
 
-reset_config trst_and_srst srst_nogate
-
+reset_config trst_and_srst srst_gates_jtag
 
 if { [info exists CHIPNAME] } {
    set  _CHIPNAME $CHIPNAME

commit 40fe5b1428e054bae7a351fbdac9cc8c87fd6dc1
Author: Øyvind Harboe <oyv...@zy...>
Date:   Tue Oct 13 11:29:05 2009 +0200

    Propagate error from assert, deassert and halt on tcl target object.

diff --git a/src/target/target.c b/src/target/target.c
index 8bb9371..2b7d7e2 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -3452,6 +3452,10 @@ void target_all_handle_event(enum target_event e)
 	}
 }
 
+
+/* FIX? should we propagate errors here rather than printing them
+ * and continuing?
+ */
 void target_handle_event(target_t *target, enum target_event e)
 {
 	target_event_action_t *teap;
@@ -4093,11 +4097,11 @@ static int tcl_target_func(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 
 		/* do the assert */
 		if (n->value == NVP_ASSERT) {
-			target->type->assert_reset(target);
+			e = target->type->assert_reset(target);
 		} else {
-			target->type->deassert_reset(target);
+			e = target->type->deassert_reset(target);
 		}
-		return JIM_OK;
+		return (e == ERROR_OK) ? JIM_OK : JIM_ERR;
 	case TS_CMD_HALT:
 		if (goi.argc) {
 			Jim_WrongNumArgs(goi.interp, 0, argv, "halt [no parameters]");
@@ -4105,8 +4109,8 @@ static int tcl_target_func(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 		}
 		if (!target->tap->enabled)
 			goto err_tap_disabled;
-		target->type->halt(target);
-		return JIM_OK;
+		e = target->type->halt(target);
+		return (e == ERROR_OK) ? JIM_OK : JIM_ERR;
 	case TS_CMD_WAITSTATE:
 		/* params:  <name>  statename timeoutmsecs */
 		if (goi.argc != 2) {

-----------------------------------------------------------------------

Summary of changes:
 TODO                 |    4 +--
 src/target/arm11.c   |   61 ++++++++++++++++---------------------------------
 src/target/arm11.h   |    4 ---
 src/target/target.c  |   14 +++++++----
 tcl/target/imx31.cfg |    2 +-
 tcl/target/imx35.cfg |    3 +-
 6 files changed, 32 insertions(+), 56 deletions(-)


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Re: [openocd-svn] Main OpenOCD repository branch, master, updated. 0.2.0-356-g1c2e48b

[David B. <da...@pa...>]

On Tuesday 13 October 2009, Øyvind Harboe wrote:
> I'm not crazy about the memset() w.r.t. performance of inner loops.

I wouldn't call those "inner loops"; or consider *knowing* the code
is correct to ever be an issue.

And in any case, GCC tends to use a builtin, which gives *VERY* tight
code.  Loop runs inside of one cacheline, etc.  


p.s.


 gcc -std=gnu99 -DHAVE_CONFIG_H -I. -I../.. -I../../src/helper -I../../src/jtag -I../../src/xsvf -I/usr/local/include -Wall -Wstrict-prototypes -Wformat-security -Wextra -Wno-unused-parameter -Wbad-function-cast -Wcast-align -Wredundant-decls -Werror -MT arm11.lo -MD -MP -MF .deps/arm11.Tpo -c arm11.c -o arm11.o
cc1: warnings being treated as errors
arm11_dbgtap.c: In function ‘arm11_run_instr_data_to_core_noack’:
arm11_dbgtap.c:593: warning: format ‘%d’ expects type ‘int’, but argument 6 has type ‘size_t’
make[3]: *** [arm11_dbgtap.lo] Error 1
make[3]: *** Waiting for unfinished jobs....

Re: [openocd-svn] Main OpenOCD repository branch, master, updated. 0.2.0-356-g1c2e48b

[Øyvind H. <oyv...@zy...>]

I'm not crazy about the memset() w.r.t. performance of inner loops.

If it turns up in profiling, I'll see about removing memset()'s, otherwise
their fine by me.



-- 
Øyvind Harboe
http://www.zylin.com/zy1000.html
ARM7 ARM9 ARM11 XScale Cortex
JTAG debugger and flash programmer

[openocd-svn] Main OpenOCD repository branch, master, updated. 0.2.0-356-g1c2e48b

[David B. <dbr...@us...>]

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- Log -----------------------------------------------------------------
commit 1c2e48b000503f15abba9092e8a159e0914c587b
Author: David Brownell <dbr...@us...>
Date:   Tue Oct 13 01:21:24 2009 -0700

    xscale: stackframe corruption bugfix
    
    Resolve a "FIX" comment; yes that was superfluous given that the
    JTAG core does that check by default.  It was also buggy since it
    wrote to a stack frame that went away before the write happened!!
    
    Other fixes:  remove pointless malloc(); zero-init scan_field_t
    values wherever they appear; whitespace scrub; spelling fix.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/xscale.c b/src/target/xscale.c
index 82a2c57..dd16b35 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -42,7 +42,7 @@
  *  Intel XScale® Core Developer’s Manual, January 2004
  *		Order Number: 273473-002
  *	This has a chapter detailing debug facilities, and punts some
- *	details to chip-specific microarchitecture documentats.
+ *	details to chip-specific microarchitecture documents.
  *
  *  Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
  *		Document Number: 273539-005
@@ -166,21 +166,15 @@ static int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr)
 	if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
 	{
 		scan_field_t field;
+		uint8_t scratch[4];
 
+		memset(&field, 0, sizeof field);
 		field.tap = tap;
 		field.num_bits = tap->ir_length;
-		field.out_value = calloc(CEIL(field.num_bits, 8), 1);
+		field.out_value = scratch;
 		buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
 
-		uint8_t tmp[4];
-		field.in_value = tmp;
-
 		jtag_add_ir_scan(1, &field, jtag_get_end_state());
-
-		/* FIX!!!! isn't this check superfluous? verify_ircapture handles this? */
-		jtag_check_value_mask(&field, tap->expected, tap->expected_mask);
-
-		free(field.out_value);
 	}
 
 	return ERROR_OK;
@@ -190,9 +184,7 @@ static int xscale_read_dcsr(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
-
 	int retval;
-
 	scan_field_t fields[3];
 	uint8_t field0 = 0x0;
 	uint8_t field0_check_value = 0x2;
@@ -207,6 +199,8 @@ static int xscale_read_dcsr(target_t *target)
 	buf_set_u32(&field0, 1, 1, xscale->hold_rst);
 	buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
 
+	memset(&fields, 0, sizeof fields);
+
 	fields[0].tap = target->tap;
 	fields[0].num_bits = 3;
 	fields[0].out_value = &field0;
@@ -215,7 +209,6 @@ static int xscale_read_dcsr(target_t *target)
 
 	fields[1].tap = target->tap;
 	fields[1].num_bits = 32;
-	fields[1].out_value = NULL;
 	fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 
 	fields[2].tap = target->tap;
@@ -277,30 +270,24 @@ static int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
 	uint8_t field2_check_mask = 0x1;
 	int words_done = 0;
 	int words_scheduled = 0;
-
 	int i;
 
 	path[0] = TAP_DRSELECT;
 	path[1] = TAP_DRCAPTURE;
 	path[2] = TAP_DRSHIFT;
 
+	memset(&fields, 0, sizeof fields);
+
 	fields[0].tap = target->tap;
 	fields[0].num_bits = 3;
-	fields[0].out_value = NULL;
-	fields[0].in_value = NULL;
 	fields[0].check_value = &field0_check_value;
 	fields[0].check_mask = &field0_check_mask;
 
 	fields[1].tap = target->tap;
 	fields[1].num_bits = 32;
-	fields[1].out_value = NULL;
-	fields[1].check_value = NULL;
-	fields[1].check_mask = NULL;
 
 	fields[2].tap = target->tap;
 	fields[2].num_bits = 1;
-	fields[2].out_value = NULL;
-	fields[2].in_value = NULL;
 	fields[2].check_value = &field2_check_value;
 	fields[2].check_mask = &field2_check_mask;
 
@@ -377,10 +364,8 @@ static int xscale_read_tx(target_t *target, int consume)
 	xscale_common_t *xscale = armv4_5->arch_info;
 	tap_state_t path[3];
 	tap_state_t noconsume_path[6];
-
 	int retval;
 	struct timeval timeout, now;
-
 	scan_field_t fields[3];
 	uint8_t field0_in = 0x0;
 	uint8_t field0_check_value = 0x2;
@@ -403,19 +388,18 @@ static int xscale_read_tx(target_t *target, int consume)
 	noconsume_path[4] = TAP_DREXIT2;
 	noconsume_path[5] = TAP_DRSHIFT;
 
+	memset(&fields, 0, sizeof fields);
+
 	fields[0].tap = target->tap;
 	fields[0].num_bits = 3;
-	fields[0].out_value = NULL;
 	fields[0].in_value = &field0_in;
 
 	fields[1].tap = target->tap;
 	fields[1].num_bits = 32;
-	fields[1].out_value = NULL;
 	fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
 
 	fields[2].tap = target->tap;
 	fields[2].num_bits = 1;
-	fields[2].out_value = NULL;
 	uint8_t tmp;
 	fields[2].in_value = &tmp;
 
@@ -477,10 +461,8 @@ static int xscale_write_rx(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
-
 	int retval;
 	struct timeval timeout, now;
-
 	scan_field_t fields[3];
 	uint8_t field0_out = 0x0;
 	uint8_t field0_in = 0x0;
@@ -494,6 +476,8 @@ static int xscale_write_rx(target_t *target)
 
 	xscale_jtag_set_instr(target->tap, XSCALE_DBGRX);
 
+	memset(&fields, 0, sizeof fields);
+
 	fields[0].tap = target->tap;
 	fields[0].num_bits = 3;
 	fields[0].out_value = &field0_out;
@@ -502,7 +486,6 @@ static int xscale_write_rx(target_t *target)
 	fields[1].tap = target->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
-	fields[1].in_value = NULL;
 
 	fields[2].tap = target->tap;
 	fields[2].num_bits = 1;
@@ -637,9 +620,7 @@ static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
-
 	int retval;
-
 	scan_field_t fields[3];
 	uint8_t field0 = 0x0;
 	uint8_t field0_check_value = 0x2;
@@ -660,6 +641,8 @@ static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
 	buf_set_u32(&field0, 1, 1, xscale->hold_rst);
 	buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
 
+	memset(&fields, 0, sizeof fields);
+
 	fields[0].tap = target->tap;
 	fields[0].num_bits = 3;
 	fields[0].out_value = &field0;
@@ -669,7 +652,6 @@ static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
 	fields[1].tap = target->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
-	fields[1].in_value = NULL;
 
 	fields[2].tap = target->tap;
 	fields[2].num_bits = 1;
@@ -728,15 +710,15 @@ static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8])
 	/* virtual address of desired cache line */
 	buf_set_u32(packet, 0, 27, va >> 5);
 
+	memset(&fields, 0, sizeof fields);
+
 	fields[0].tap = target->tap;
 	fields[0].num_bits = 6;
 	fields[0].out_value = &cmd;
-	fields[0].in_value = NULL;
 
 	fields[1].tap = target->tap;
 	fields[1].num_bits = 27;
 	fields[1].out_value = packet;
-	fields[1].in_value = NULL;
 
 	jtag_add_dr_scan(2, fields, jtag_get_end_state());
 
@@ -776,15 +758,15 @@ static int xscale_invalidate_ic_line(target_t *target, uint32_t va)
 	/* virtual address of desired cache line */
 	buf_set_u32(packet, 0, 27, va >> 5);
 
+	memset(&fields, 0, sizeof fields);
+
 	fields[0].tap = target->tap;
 	fields[0].num_bits = 6;
 	fields[0].out_value = &cmd;
-	fields[0].in_value = NULL;
 
 	fields[1].tap = target->tap;
 	fields[1].num_bits = 27;
 	fields[1].out_value = packet;
-	fields[1].in_value = NULL;
 
 	jtag_add_dr_scan(2, fields, jtag_get_end_state());
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/xscale.c |   54 +++++++++++++++++----------------------------------
 1 files changed, 18 insertions(+), 36 deletions(-)


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commit 9aab763fa555f049f03a242114ade0d1978f4291
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Oct 12 15:25:00 2009 +0200

    More error propagation fixes.

diff --git a/src/target/arm11.c b/src/target/arm11.c
index f7265da..36ed6b8 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1401,7 +1401,9 @@ int arm11_write_memory_inner(struct target_s *target, uint32_t address, uint32_t
 
 	arm11_common_t * arm11 = target->arch_info;
 
-	arm11_run_instr_data_prepare(arm11);
+	retval = arm11_run_instr_data_prepare(arm11);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* MRC p14,0,r0,c0,c5,0 */
 	retval = arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index 1ab6c52..57685cf 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -925,7 +925,10 @@ void arm11_sc7_set_vcr(arm11_common_t * arm11, uint32_t value)
  */
 int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t * result)
 {
-	arm11_run_instr_data_prepare(arm11);
+	int retval;
+	retval = arm11_run_instr_data_prepare(arm11);
+	if (retval != ERROR_OK)
+		return retval;
 
 	/* MRC p14,0,r0,c0,c5,0 (r0 = address) */
 	CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address));
@@ -933,9 +936,7 @@ int arm11_read_memory_word(arm11_common_t * arm11, uint32_t address, uint32_t *
 	/* LDC p14,c5,[R0],#4 (DTR = [r0]) */
 	CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1));
 
-	arm11_run_instr_data_finish(arm11);
-
-	return ERROR_OK;
+	return arm11_run_instr_data_finish(arm11);
 }
 
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm11.c        |    4 +++-
 src/target/arm11_dbgtap.c |    9 +++++----
 2 files changed, 8 insertions(+), 5 deletions(-)


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- Log -----------------------------------------------------------------
commit 59d09ff393daaf3cb2a5a27c808c40384bc3f74a
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Oct 12 15:13:44 2009 +0200

    arm11 burst writes are now only enabled for writes larger than 1 word. Single word writes are frequently used from reset init scripts to non-memory peripherals.

diff --git a/doc/openocd.texi b/doc/openocd.texi
index ddc0cfd..479aa17 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5737,7 +5737,11 @@ one bit in the encoding, effecively a fifth parameter.)
 
 @deffn Command {arm11 memwrite burst} [value]
 Displays the value of the memwrite burst-enable flag,
-which is enabled by default.
+which is enabled by default. Burst writes are only used
+for memory writes larger than 1 word. Single word writes
+are likely to be from reset init scripts and those writes
+are often to non-memory locations which could easily have
+many wait states, which could easily break burst writes.
 If @var{value} is defined, first assigns that.
 @end deffn
 
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 16c8dd3..f7265da 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1408,6 +1408,15 @@ int arm11_write_memory_inner(struct target_s *target, uint32_t address, uint32_t
 	if (retval != ERROR_OK)
 		return retval;
 
+	/* burst writes are not used for single words as those may well be
+	 * reset init script writes.
+	 *
+	 * The other advantage is that as burst writes are default, we'll
+	 * now exercise both burst and non-burst code paths with the
+	 * default settings, increasing code coverage.
+	 */
+	bool burst = arm11_config_memwrite_burst && (count > 1);
+
 	switch (size)
 	{
 	case 1:
@@ -1463,7 +1472,7 @@ int arm11_write_memory_inner(struct target_s *target, uint32_t address, uint32_t
 		/** \todo TODO: buffer cast to uint32_t* causes alignment warnings */
 		uint32_t *words = (uint32_t*)buffer;
 
-		if (!arm11_config_memwrite_burst)
+		if (!burst)
 		{
 			/* STC p14,c5,[R0],#4 */
 			/* STC p14,c5,[R0]*/
@@ -1501,7 +1510,7 @@ int arm11_write_memory_inner(struct target_s *target, uint32_t address, uint32_t
 					(unsigned) (address + size * count),
 					(unsigned) r0);
 
-			if (arm11_config_memwrite_burst)
+			if (burst)
 				LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
 
 			if (arm11_config_memwrite_error_fatal)

commit d38c75421b937026091927e4a8577f51a3d5dc16
Author: Wookey <wo...@wo...>
Date:   Mon Oct 12 15:12:35 2009 +0200

    Xilinx xcr3256.cfg basic config script

diff --git a/tcl/cpld/xilinx-xcr3256.cfg b/tcl/cpld/xilinx-xcr3256.cfg
new file mode 100644
index 0000000..e5611f1
--- /dev/null
+++ b/tcl/cpld/xilinx-xcr3256.cfg
@@ -0,0 +1,3 @@
+#xilinx coolrunner xcr3256
+#simple device - just configure a tap
+jtag newtap xcr tap -irlen 5 -ircapture 0x01 -irmask 0x1f -expected-id  0x0494c093

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi            |    6 +++++-
 src/target/arm11.c          |   13 +++++++++++--
 tcl/cpld/xilinx-xcr3256.cfg |    3 +++
 3 files changed, 19 insertions(+), 3 deletions(-)
 create mode 100644 tcl/cpld/xilinx-xcr3256.cfg


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- Log -----------------------------------------------------------------
commit 6d694d405d767a537ca1eded70003887433d47bd
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Oct 12 14:21:38 2009 +0200

    Retire arm11 no_increment. Intended for future expansion to read/write to ports. New arm11 commands would have to be added to exploit it.

diff --git a/doc/openocd.texi b/doc/openocd.texi
index d41f422..ddc0cfd 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5756,13 +5756,6 @@ one bit in the encoding, effecively a fifth parameter.)
 Displays the result.
 @end deffn
 
-@deffn Command {arm11 no_increment}  [value]
-Displays the value of the flag controlling whether
-some read or write operations increment the pointer
-(the default behavior) or not (acting like a FIFO).
-If @var{value} is defined, first assigns that.
-@end deffn
-
 @deffn Command {arm11 step_irq_enable}  [value]
 Displays the value of the flag controlling whether
 IRQs are enabled during single stepping;
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 915bee6..16c8dd3 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -54,7 +54,6 @@ static int arm11_on_enter_debug_state(arm11_common_t * arm11);
 bool	arm11_config_memwrite_burst				= true;
 bool	arm11_config_memwrite_error_fatal		= true;
 uint32_t		arm11_vcr								= 0;
-bool	arm11_config_memrw_no_increment			= false;
 bool	arm11_config_step_irq_enable			= false;
 bool	arm11_config_hardware_step				= false;
 
@@ -1284,8 +1283,13 @@ int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], i
 /* target memory access
  * size: 1 = byte (8bit), 2 = half-word (16bit), 4 = word (32bit)
  * count: number of items of <size>
+ *
+ * arm11_config_memrw_no_increment - in the future we may want to be able
+ * to read/write a range of data to a "port". a "port" is an action on
+ * read memory address for some peripheral.
  */
-int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int arm11_read_memory_inner(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
+		bool arm11_config_memrw_no_increment)
 {
 	/** \todo TODO: check if buffer cast to uint32_t* and uint16_t* might cause alignment problems */
 	int retval;
@@ -1371,7 +1375,18 @@ int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size,
 	return arm11_run_instr_data_finish(arm11);
 }
 
-int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+int arm11_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+{
+	return arm11_read_memory_inner(target, address, size, count, buffer, false);
+}
+
+/*
+* arm11_config_memrw_no_increment - in the future we may want to be able
+* to read/write a range of data to a "port". a "port" is an action on
+* read memory address for some peripheral.
+*/
+int arm11_write_memory_inner(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer,
+		bool arm11_config_memrw_no_increment)
 {
 	int retval;
 	FNC_INFO;
@@ -1497,6 +1512,10 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size,
 	return arm11_run_instr_data_finish(arm11);
 }
 
+int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+{
+	return arm11_write_memory_inner(target, address, size, count, buffer, false);
+}
 
 /* write target memory in multiples of 4 byte, optimized for writing large quantities of data */
 int arm11_bulk_write_memory(struct target_s *target, uint32_t address, uint32_t count, uint8_t *buffer)
@@ -2002,7 +2021,6 @@ int arm11_handle_bool_##name(struct command_context_s *cmd_ctx, char *cmd, char
 
 BOOL_WRAPPER(memwrite_burst,			"memory write burst mode")
 BOOL_WRAPPER(memwrite_error_fatal,		"fatal error mode for memory writes")
-BOOL_WRAPPER(memrw_no_increment,		"\"no increment\" mode for memory transfers")
 BOOL_WRAPPER(step_irq_enable,			"IRQs while stepping")
 BOOL_WRAPPER(hardware_step,			"hardware single step")
 
@@ -2182,10 +2200,6 @@ int arm11_register_commands(struct command_context_s *cmd_ctx)
 	register_command(cmd_ctx, top_cmd, "mrc",
 			arm11_handle_mrc, COMMAND_ANY,
 			"Read Coprocessor register. mrc <jtag_target> <coprocessor> <opcode 1> <CRn> <CRm> <opcode 2>. All parameters are numbers only.");
-	register_command(cmd_ctx, top_cmd, "no_increment",
-			arm11_handle_bool_memrw_no_increment, COMMAND_ANY,
-			"Don't increment address on multi-read/-write"
-				" (default: disabled)");
 	register_command(cmd_ctx, top_cmd, "step_irq_enable",
 			arm11_handle_bool_step_irq_enable, COMMAND_ANY,
 			"Enable interrupts while stepping"

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi   |    7 -------
 src/target/arm11.c |   30 ++++++++++++++++++++++--------
 2 files changed, 22 insertions(+), 15 deletions(-)


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- Log -----------------------------------------------------------------
commit 4f4f4ab35a2ee485ee19e3c7b6e7d35faac6daa8
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Oct 12 14:10:49 2009 +0200

    Propagate wDTR/rDTR failure immediately, otherwise it's followed up by timeout errors.

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 588ea3c..915bee6 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -610,6 +610,7 @@ int arm11_leave_debug_state(arm11_common_t * arm11)
 		if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
 		{
 			LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
+			return ERROR_FAIL;
 		}
 	}
 

commit 94add4688d2fbe7003b1e118bbcd68cc0ee82a30
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Oct 12 14:09:10 2009 +0200

    Fix warning and improve error message upon burst transfer failure

diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index 9aa7a30..1ab6c52 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -585,8 +585,8 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, uint32_t opcode,
 	arm11_setup_field(arm11,  1,    NULL,			NULL,				chain5_fields + 2);
 
 	uint8_t			*Readies;
-	int readiesNum = (count + 1);
-	int bytes = sizeof(*Readies)*readiesNum;
+	size_t readiesNum = (count + 1);
+	size_t bytes = sizeof(*Readies)*readiesNum;
 	Readies = (uint8_t *) malloc(bytes);
 	if (Readies == NULL)
 	{
@@ -634,7 +634,7 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, uint32_t opcode,
 		}
 
 		if (error_count > 0 )
-			LOG_ERROR(ZU " words not transferred", error_count);
+			LOG_ERROR(ZU " words out of " ZU " not transferred", error_count, readiesNum);
 
 	}
 

commit 7a83ea411468d00b68e358b87a0845d1ad3c35a9
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Oct 12 14:08:29 2009 +0200

    burst writes work fine. clean up junk.

diff --git a/tcl/board/imx35pdk.cfg b/tcl/board/imx35pdk.cfg
index 05d83ee..7724bac 100644
--- a/tcl/board/imx35pdk.cfg
+++ b/tcl/board/imx35pdk.cfg
@@ -2,9 +2,6 @@
 source [find target/imx35.cfg]
 $_TARGETNAME configure -event reset-init { imx35pdk_init }
 
-memwrite burst disable
-#arm11 no_increment enable
-
 
 global TARGETNAME 
 set TARGETNAME $_TARGETNAME

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm11.c        |    1 +
 src/target/arm11_dbgtap.c |    6 +++---
 tcl/board/imx35pdk.cfg    |    3 ---
 3 files changed, 4 insertions(+), 6 deletions(-)


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- Log -----------------------------------------------------------------
commit 3fef24258ab803e92fefd8191944299da54ba286
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Oct 12 11:57:59 2009 +0200

    Fix bogus 'transfer errors' with arm11 'memwrite burst enable'. A regression introduced in b8103660fa36a77158bd77379572c09913d85c00

diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index b08d300..9aa7a30 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -585,7 +585,8 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, uint32_t opcode,
 	arm11_setup_field(arm11,  1,    NULL,			NULL,				chain5_fields + 2);
 
 	uint8_t			*Readies;
-	int bytes = sizeof(*Readies)*(count + 1);
+	int readiesNum = (count + 1);
+	int bytes = sizeof(*Readies)*readiesNum;
 	Readies = (uint8_t *) malloc(bytes);
 	if (Readies == NULL)
 	{
@@ -622,10 +623,9 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, uint32_t opcode,
 	int retval = jtag_execute_queue();
 	if (retval == ERROR_OK)
 	{
-
 		size_t error_count = 0;
 
-		for (size_t i = 0; i < asizeof(Readies); i++)
+		for (size_t i = 0; i < readiesNum; i++)
 		{
 			if (Readies[i] != 1)
 			{
@@ -633,8 +633,8 @@ int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, uint32_t opcode,
 			}
 		}
 
-		if (error_count)
-			LOG_ERROR("Transfer errors " ZU, error_count);
+		if (error_count > 0 )
+			LOG_ERROR(ZU " words not transferred", error_count);
 
 	}
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm11_dbgtap.c |   10 +++++-----
 1 files changed, 5 insertions(+), 5 deletions(-)


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- Log -----------------------------------------------------------------
commit a51e23c39f9d61dc4d999a4d4b23d1bbb364cd46
Author: David Brownell <dbr...@us...>
Date:   Mon Oct 12 02:39:18 2009 -0700

    simplify XScale debug handler installation
    
    Load the XScale debug handler from the read-only data section
    instead of from a separate file that can get lost or garbaged.
    This eliminates installation and versioning issues, and also
    speeds up reset handling a bit.
    
    Plus some minor bits of cleanup related to loading that handler:
    comments about just what this handler does, and check fault codes
    while writing it into the mini-icache.
    
    The only behavioral changes should be cleaner failure modes after
    errors during handler loading, and being a bit faster.
    
    NOTE:  presumes GNU assembly syntax, with ".incbin"; and ELF,
    because of the syntax of the ".size" directive.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/TODO b/TODO
index cf7778b..6521c60 100644
--- a/TODO
+++ b/TODO
@@ -125,9 +125,6 @@ Once the above are completed:
 
 - general layer cleanup: @par
   https://lists.berlios.de/pipermail/openocd-development/2009-May/006590.html
-- regression: xscale does not place debug_handler.bin into the right spot. workaround:
-  use -s option on command line to place xscale/debug_handler.bin in search path @par
-  https://lists.berlios.de/pipermail/openocd-development/2009-July/009338.html
 - bug: either USBprog is broken with new tms sequence or there is a general
   problem with XScale and the new tms sequence. Workaround: use "tms_sequence long"
   @par
diff --git a/configure.in b/configure.in
index 8e2881c..84574be 100644
--- a/configure.in
+++ b/configure.in
@@ -16,6 +16,7 @@ AC_LANG_C
 AC_PROG_CC
 AC_PROG_CC_C99
 AM_PROG_CC_C_O
+AM_PROG_AS
 AC_PROG_RANLIB
 
 dnl disable checks for C++, Fortran and GNU Java Compiler
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 9eee2f9..86716dc 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -35,6 +35,7 @@ libtarget_la_SOURCES = \
 	feroceon.c \
 	etb.c \
 	xscale.c \
+	xscale_debug.S \
 	arm_simulator.c \
 	image.c \
 	armv7m.c \
@@ -98,7 +99,6 @@ noinst_HEADERS = \
 	avrt.h
 
 nobase_dist_pkglib_DATA =
-nobase_dist_pkglib_DATA += xscale/debug_handler.bin
 nobase_dist_pkglib_DATA += ecos/at91eb40a.elf
 
 MAINTAINERCLEANFILES = $(srcdir)/Makefile.in
diff --git a/src/target/xscale.c b/src/target/xscale.c
index fca578d..82a2c57 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -1559,15 +1559,6 @@ static int xscale_deassert_reset(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
-
-	fileio_t debug_handler;
-	uint32_t address;
-	uint32_t binary_size;
-
-	uint32_t buf_cnt;
-	uint32_t i;
-	int retval;
-
 	breakpoint_t *breakpoint = target->breakpoints;
 
 	LOG_DEBUG("-");
@@ -1592,6 +1583,11 @@ static int xscale_deassert_reset(target_t *target)
 
 	if (!xscale->handler_installed)
 	{
+		uint32_t address;
+		unsigned buf_cnt;
+		const uint8_t *buffer = xscale_debug_handler;
+		int retval;
+
 		/* release SRST */
 		jtag_add_reset(0, 0);
 
@@ -1606,36 +1602,26 @@ static int xscale_deassert_reset(target_t *target)
 		buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 16, 1, 0x1);
 		xscale_write_dcsr(target, 1, 0);
 
-		/* Load debug handler */
-		if (fileio_open(&debug_handler, "xscale/debug_handler.bin", FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
-		{
-			return ERROR_OK;
-		}
-
-		if ((binary_size = debug_handler.size) % 4)
-		{
-			LOG_ERROR("debug_handler.bin: size not a multiple of 4");
-			exit(-1);
-		}
-
-		if (binary_size > 0x800)
-		{
-			LOG_ERROR("debug_handler.bin: larger than 2kb");
-			exit(-1);
-		}
-
-		binary_size = CEIL(binary_size, 32) * 32;
-
+		/* Load the debug handler into the mini-icache.  Since
+		 * it's using halt mode (not monitor mode), it runs in
+		 * "Special Debug State" for access to registers, memory,
+		 * coprocessors, trace data, etc.
+		 *
+		 * REVISIT:  *assumes* we've had a SRST+TRST reset so the
+		 * mini-icache contents have been invalidated.  Safest to
+		 * force that, so writing new contents is reliable...
+		 */
 		address = xscale->handler_address;
-		while (binary_size > 0)
+		for (unsigned binary_size = xscale_debug_handler_size;
+				binary_size > 0;
+				binary_size -= buf_cnt, buffer += buf_cnt)
 		{
 			uint32_t cache_line[8];
-			uint8_t buffer[32];
-
-			if ((retval = fileio_read(&debug_handler, 32, buffer, &buf_cnt)) != ERROR_OK)
-			{
+			unsigned i;
 
-			}
+			buf_cnt = binary_size;
+			if (buf_cnt > 32)
+				buf_cnt = 32;
 
 			for (i = 0; i < buf_cnt; i += 4)
 			{
@@ -1651,15 +1637,23 @@ static int xscale_deassert_reset(target_t *target)
 			/* only load addresses other than the reset vectors */
 			if ((address % 0x400) != 0x0)
 			{
-				xscale_load_ic(target, address, cache_line);
+				retval = xscale_load_ic(target, address,
+						cache_line);
+				if (retval != ERROR_OK)
+					return retval;
 			}
 
 			address += buf_cnt;
-			binary_size -= buf_cnt;
 		};
 
-		xscale_load_ic(target, 0x0, xscale->low_vectors);
-		xscale_load_ic(target, 0xffff0000, xscale->high_vectors);
+		retval = xscale_load_ic(target, 0x0,
+					xscale->low_vectors);
+		if (retval != ERROR_OK)
+			return retval;
+		retval = xscale_load_ic(target, 0xffff0000,
+					xscale->high_vectors);
+		if (retval != ERROR_OK)
+			return retval;
 
 		jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE));
 
@@ -1685,8 +1679,6 @@ static int xscale_deassert_reset(target_t *target)
 			/* resume the target */
 			xscale_resume(target, 1, 0x0, 1, 0);
 		}
-
-		fileio_close(&debug_handler);
 	}
 	else
 	{
@@ -3056,6 +3048,11 @@ static int xscale_target_create(struct target_s *target, Jim_Interp *interp)
 {
 	xscale_common_t *xscale;
 
+	if (xscale_debug_handler_size > 0x800) {
+		LOG_ERROR("debug_handler.bin: larger than 2kb");
+		return ERROR_FAIL;
+	}
+
 	xscale = calloc(1, sizeof(*xscale));
 	if (!xscale)
 		return ERROR_FAIL;
diff --git a/src/target/xscale.h b/src/target/xscale.h
index a5d83ee..9d92550 100644
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -170,4 +170,10 @@ enum
 
 #define ERROR_XSCALE_NO_TRACE_DATA	(-1500)
 
+/* This XScale "debug handler" is loaded into the processor's
+ * mini-ICache, which is 2K of code writable only via JTAG.
+ */
+extern const uint8_t xscale_debug_handler[];
+extern const uint32_t xscale_debug_handler_size;
+
 #endif /* XSCALE_H */
diff --git a/src/target/xscale_debug.S b/src/target/xscale_debug.S
new file mode 100644
index 0000000..0a7b87d
--- /dev/null
+++ b/src/target/xscale_debug.S
@@ -0,0 +1,13 @@
+	.section	.rodata
+
+	.align		4
+	.global		 xscale_debug_handler
+xscale_debug_handler:
+	.incbin		"xscale/debug_handler.bin"
+	.size		xscale_debug_handler, . - xscale_debug_handler
+
+	.align		4
+	.global		 xscale_debug_handler_size
+xscale_debug_handler_size:
+	.word		. - xscale_debug_handler
+	.size		xscale_debug_handler_size, 4

commit 43a241afe2c342437afe7cdbe9a20501dc4f1499
Author: David Brownell <dbr...@us...>
Date:   Mon Oct 12 02:39:01 2009 -0700

    more xscale cleanup (mostly removing JTAG hooks)
    
    Streamline/shrink some needless JTAG stuff:
    
     - Use #defines for the JTAG instructions; they can't ever change
     - Remove an unused (!) shadow of tap->ir_length
     - Stop using a copy of target->tap
     - Don't bother saving the variant after sanity checking ir_length
    
    Also, make target_create() work as on other targets:  build the
    register cache later, making init_target() no longer be a NOP.
    Handle malloc failure; remove a comment that was obsoleted by the
    not-so-new target syntax.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/xscale.c b/src/target/xscale.c
index f245a20..fca578d 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -202,23 +202,23 @@ static int xscale_read_dcsr(target_t *target)
 	uint8_t field2_check_mask = 0x1;
 
 	jtag_set_end_state(TAP_DRPAUSE);
-	xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
+	xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
 
 	buf_set_u32(&field0, 1, 1, xscale->hold_rst);
 	buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
 
-	fields[0].tap = xscale->jtag_info.tap;
+	fields[0].tap = target->tap;
 	fields[0].num_bits = 3;
 	fields[0].out_value = &field0;
 	uint8_t tmp;
 	fields[0].in_value = &tmp;
 
-	fields[1].tap = xscale->jtag_info.tap;
+	fields[1].tap = target->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = NULL;
 	fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 
-	fields[2].tap = xscale->jtag_info.tap;
+	fields[2].tap = target->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = &field2;
 	uint8_t tmp2;
@@ -267,12 +267,8 @@ static int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
 		return ERROR_INVALID_ARGUMENTS;
 
 	int retval = ERROR_OK;
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	xscale_common_t *xscale = armv4_5->arch_info;
-
 	tap_state_t path[3];
 	scan_field_t fields[3];
-
 	uint8_t *field0 = malloc(num_words * 1);
 	uint8_t field0_check_value = 0x2;
 	uint8_t field0_check_mask = 0x6;
@@ -288,20 +284,20 @@ static int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
 	path[1] = TAP_DRCAPTURE;
 	path[2] = TAP_DRSHIFT;
 
-	fields[0].tap = xscale->jtag_info.tap;
+	fields[0].tap = target->tap;
 	fields[0].num_bits = 3;
 	fields[0].out_value = NULL;
 	fields[0].in_value = NULL;
 	fields[0].check_value = &field0_check_value;
 	fields[0].check_mask = &field0_check_mask;
 
-	fields[1].tap = xscale->jtag_info.tap;
+	fields[1].tap = target->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = NULL;
 	fields[1].check_value = NULL;
 	fields[1].check_mask = NULL;
 
-	fields[2].tap = xscale->jtag_info.tap;
+	fields[2].tap = target->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = NULL;
 	fields[2].in_value = NULL;
@@ -309,7 +305,7 @@ static int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
 	fields[2].check_mask = &field2_check_mask;
 
 	jtag_set_end_state(TAP_IDLE);
-	xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
+	xscale_jtag_set_instr(target->tap, XSCALE_DBGTX);
 	jtag_add_runtest(1, jtag_get_end_state()); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
 
 	/* repeat until all words have been collected */
@@ -394,7 +390,7 @@ static int xscale_read_tx(target_t *target, int consume)
 
 	jtag_set_end_state(TAP_IDLE);
 
-	xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgtx);
+	xscale_jtag_set_instr(target->tap, XSCALE_DBGTX);
 
 	path[0] = TAP_DRSELECT;
 	path[1] = TAP_DRCAPTURE;
@@ -407,17 +403,17 @@ static int xscale_read_tx(target_t *target, int consume)
 	noconsume_path[4] = TAP_DREXIT2;
 	noconsume_path[5] = TAP_DRSHIFT;
 
-	fields[0].tap = xscale->jtag_info.tap;
+	fields[0].tap = target->tap;
 	fields[0].num_bits = 3;
 	fields[0].out_value = NULL;
 	fields[0].in_value = &field0_in;
 
-	fields[1].tap = xscale->jtag_info.tap;
+	fields[1].tap = target->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = NULL;
 	fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
 
-	fields[2].tap = xscale->jtag_info.tap;
+	fields[2].tap = target->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = NULL;
 	uint8_t tmp;
@@ -496,19 +492,19 @@ static int xscale_write_rx(target_t *target)
 
 	jtag_set_end_state(TAP_IDLE);
 
-	xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
+	xscale_jtag_set_instr(target->tap, XSCALE_DBGRX);
 
-	fields[0].tap = xscale->jtag_info.tap;
+	fields[0].tap = target->tap;
 	fields[0].num_bits = 3;
 	fields[0].out_value = &field0_out;
 	fields[0].in_value = &field0_in;
 
-	fields[1].tap = xscale->jtag_info.tap;
+	fields[1].tap = target->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
 	fields[1].in_value = NULL;
 
-	fields[2].tap = xscale->jtag_info.tap;
+	fields[2].tap = target->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = &field2;
 	uint8_t tmp;
@@ -567,18 +563,14 @@ static int xscale_write_rx(target_t *target)
 /* send count elements of size byte to the debug handler */
 static int xscale_send(target_t *target, uint8_t *buffer, int count, int size)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	xscale_common_t *xscale = armv4_5->arch_info;
 	uint32_t t[3];
 	int bits[3];
-
 	int retval;
-
 	int done_count = 0;
 
 	jtag_set_end_state(TAP_IDLE);
 
-	xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dbgrx);
+	xscale_jtag_set_instr(target->tap, XSCALE_DBGRX);
 
 	bits[0]=3;
 	t[0]=0;
@@ -615,7 +607,7 @@ static int xscale_send(target_t *target, uint8_t *buffer, int count, int size)
 			LOG_ERROR("BUG: size neither 4, 2 nor 1");
 			exit(-1);
 		}
-		jtag_add_dr_out(xscale->jtag_info.tap,
+		jtag_add_dr_out(target->tap,
 				3,
 				bits,
 				t,
@@ -663,23 +655,23 @@ static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
 		xscale->external_debug_break = ext_dbg_brk;
 
 	jtag_set_end_state(TAP_IDLE);
-	xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
+	xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
 
 	buf_set_u32(&field0, 1, 1, xscale->hold_rst);
 	buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
 
-	fields[0].tap = xscale->jtag_info.tap;
+	fields[0].tap = target->tap;
 	fields[0].num_bits = 3;
 	fields[0].out_value = &field0;
 	uint8_t tmp;
 	fields[0].in_value = &tmp;
 
-	fields[1].tap = xscale->jtag_info.tap;
+	fields[1].tap = target->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 	fields[1].in_value = NULL;
 
-	fields[2].tap = xscale->jtag_info.tap;
+	fields[2].tap = target->tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = &field2;
 	uint8_t tmp2;
@@ -716,19 +708,16 @@ static unsigned int parity (unsigned int v)
 
 static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8])
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	xscale_common_t *xscale = armv4_5->arch_info;
 	uint8_t packet[4];
 	uint8_t cmd;
 	int word;
-
 	scan_field_t fields[2];
 
 	LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
 
 	/* LDIC into IR */
 	jtag_set_end_state(TAP_IDLE);
-	xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic);
+	xscale_jtag_set_instr(target->tap, XSCALE_LDIC);
 
 	/* CMD is b011 to load a cacheline into the Mini ICache.
 	 * Loading into the main ICache is deprecated, and unused.
@@ -739,12 +728,12 @@ static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8])
 	/* virtual address of desired cache line */
 	buf_set_u32(packet, 0, 27, va >> 5);
 
-	fields[0].tap = xscale->jtag_info.tap;
+	fields[0].tap = target->tap;
 	fields[0].num_bits = 6;
 	fields[0].out_value = &cmd;
 	fields[0].in_value = NULL;
 
-	fields[1].tap = xscale->jtag_info.tap;
+	fields[1].tap = target->tap;
 	fields[1].num_bits = 27;
 	fields[1].out_value = packet;
 	fields[1].in_value = NULL;
@@ -774,15 +763,12 @@ static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8])
 
 static int xscale_invalidate_ic_line(target_t *target, uint32_t va)
 {
-	armv4_5_common_t *armv4_5 = target->arch_info;
-	xscale_common_t *xscale = armv4_5->arch_info;
 	uint8_t packet[4];
 	uint8_t cmd;
-
 	scan_field_t fields[2];
 
 	jtag_set_end_state(TAP_IDLE);
-	xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
+	xscale_jtag_set_instr(target->tap, XSCALE_LDIC);
 
 	/* CMD for invalidate IC line b000, bits [6:4] b000 */
 	buf_set_u32(&cmd, 0, 6, 0x0);
@@ -790,12 +776,12 @@ static int xscale_invalidate_ic_line(target_t *target, uint32_t va)
 	/* virtual address of desired cache line */
 	buf_set_u32(packet, 0, 27, va >> 5);
 
-	fields[0].tap = xscale->jtag_info.tap;
+	fields[0].tap = target->tap;
 	fields[0].num_bits = 6;
 	fields[0].out_value = &cmd;
 	fields[0].in_value = NULL;
 
-	fields[1].tap = xscale->jtag_info.tap;
+	fields[1].tap = target->tap;
 	fields[1].num_bits = 27;
 	fields[1].out_value = packet;
 	fields[1].in_value = NULL;
@@ -1539,7 +1525,7 @@ static int xscale_assert_reset(target_t *target)
 	 * end up in T-L-R, which would reset JTAG
 	 */
 	jtag_set_end_state(TAP_IDLE);
-	xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
+	xscale_jtag_set_instr(target->tap, XSCALE_SELDCSR);
 
 	/* set Hold reset, Halt mode and Trap Reset */
 	buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
@@ -1547,7 +1533,7 @@ static int xscale_assert_reset(target_t *target)
 	xscale_write_dcsr(target, 1, 0);
 
 	/* select BYPASS, because having DCSR selected caused problems on the PXA27x */
-	xscale_jtag_set_instr(xscale->jtag_info.tap, 0x7f);
+	xscale_jtag_set_instr(target->tap, 0x7f);
 	jtag_execute_queue();
 
 	/* assert reset */
@@ -2948,6 +2934,7 @@ static void xscale_build_reg_cache(target_t *target)
 static int xscale_init_target(struct command_context_s *cmd_ctx,
 		struct target_s *target)
 {
+	xscale_build_reg_cache(target);
 	return ERROR_OK;
 }
 
@@ -2970,29 +2957,28 @@ static int xscale_init_arch_info(target_t *target,
 	xscale->arch_info = NULL;
 	xscale->common_magic = XSCALE_COMMON_MAGIC;
 
-	/* remember the variant (PXA25x, PXA27x, IXP42x, ...) */
-	xscale->variant = strdup(variant);
-
-	/* prepare JTAG information for the new target */
-	xscale->jtag_info.tap = tap;
-
-	xscale->jtag_info.dbgrx = 0x02;
-	xscale->jtag_info.dbgtx = 0x10;
-	xscale->jtag_info.dcsr = 0x09;
-	xscale->jtag_info.ldic = 0x07;
+	/* we don't really *need* variant info ... */
+	if (variant) {
+		int ir_length = 0;
+
+		if (strcmp(variant, "pxa250") == 0
+				|| strcmp(variant, "pxa255") == 0
+				|| strcmp(variant, "pxa26x") == 0)
+			ir_length = 5;
+		else if (strcmp(variant, "pxa27x") == 0
+				|| strcmp(variant, "ixp42x") == 0
+				|| strcmp(variant, "ixp45x") == 0
+				|| strcmp(variant, "ixp46x") == 0)
+			ir_length = 7;
+		else
+			LOG_WARNING("%s: unrecognized variant %s",
+				tap->dotted_name, variant);
 
-	if ((strcmp(xscale->variant, "pxa250") == 0) ||
-		(strcmp(xscale->variant, "pxa255") == 0) ||
-		(strcmp(xscale->variant, "pxa26x") == 0))
-	{
-		xscale->jtag_info.ir_length = 5;
-	}
-	else if ((strcmp(xscale->variant, "pxa27x") == 0) ||
-		(strcmp(xscale->variant, "ixp42x") == 0) ||
-		(strcmp(xscale->variant, "ixp45x") == 0) ||
-		(strcmp(xscale->variant, "ixp46x") == 0))
-	{
-		xscale->jtag_info.ir_length = 7;
+		if (ir_length && ir_length != tap->ir_length) {
+			LOG_WARNING("%s: IR length for %s is %d; fixing",
+				tap->dotted_name, variant, ir_length);
+			tap->ir_length = ir_length;
+		}
 	}
 
 	/* the debug handler isn't installed (and thus not running) at this time */
@@ -3066,15 +3052,16 @@ static int xscale_init_arch_info(target_t *target,
 	return ERROR_OK;
 }
 
-/* target xscale <endianess> <startup_mode> <chain_pos> <variant> */
 static int xscale_target_create(struct target_s *target, Jim_Interp *interp)
 {
-	xscale_common_t *xscale = calloc(1,sizeof(xscale_common_t));
+	xscale_common_t *xscale;
 
-	xscale_init_arch_info(target, xscale, target->tap, target->variant);
-	xscale_build_reg_cache(target);
+	xscale = calloc(1, sizeof(*xscale));
+	if (!xscale)
+		return ERROR_FAIL;
 
-	return ERROR_OK;
+	return xscale_init_arch_info(target, xscale, target->tap,
+			target->variant);
 }
 
 static int
diff --git a/src/target/xscale.h b/src/target/xscale.h
index 6cfe76e..a5d83ee 100644
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -29,18 +29,13 @@
 
 #define	XSCALE_COMMON_MAGIC 0x58534341
 
-typedef struct xscale_jtag_s
-{
-	/* position in JTAG scan chain */
-	jtag_tap_t *tap;
-
-	/* IR length and instructions */
-	int ir_length;
-	uint32_t dbgrx;
-	uint32_t dbgtx;
-	uint32_t ldic;
-	uint32_t dcsr;
-} xscale_jtag_t;
+/* These four JTAG instructions are architecturally defined.
+ * Lengths are core-specific; originally 5 bits, later 7.
+ */
+#define XSCALE_DBGRX	0x02
+#define XSCALE_DBGTX	0x10
+#define XSCALE_LDIC	0x07
+#define XSCALE_SELDCSR	0x09
 
 enum xscale_debug_reason
 {
@@ -90,11 +85,6 @@ typedef struct xscale_common_s
 	/* XScale registers (CP15, DBG) */
 	reg_cache_t *reg_cache;
 
-	/* pxa250, pxa255, pxa27x, ixp42x, ... */
-	char *variant;
-
-	xscale_jtag_t jtag_info;
-
 	/* current state of the debug handler */
 	int handler_installed;
 	int handler_running;

-----------------------------------------------------------------------

Summary of changes:
 TODO                      |    3 -
 configure.in              |    1 +
 src/target/Makefile.am    |    2 +-
 src/target/xscale.c       |  208 +++++++++++++++++++++------------------------
 src/target/xscale.h       |   30 +++----
 src/target/xscale_debug.S |   13 +++
 6 files changed, 124 insertions(+), 133 deletions(-)
 create mode 100644 src/target/xscale_debug.S


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Main OpenOCD repository

[openocd-svn] branch, master, updated. 0.2.0-345-g3e6512f

[Øyvind H. <go...@us...>]

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The branch, master has been updated
       via  3e6512fe5708d2b38e01dcab7246ac01b994d5a3 (commit)
       via  9ccdc02b8d6d5aebd948626a95e942504b6a21fc (commit)
       via  6b72f2486be59dbfea53e511aaf1adfb5fa68f05 (commit)
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- Log -----------------------------------------------------------------
commit 3e6512fe5708d2b38e01dcab7246ac01b994d5a3
Merge: 9ccdc02 6451563
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Oct 12 09:28:56 2009 +0200

    Merge commit 'origin/master'


commit 9ccdc02b8d6d5aebd948626a95e942504b6a21fc
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Oct 12 09:27:27 2009 +0200

    If halt times out, stop GDB. Allows e.g. manual reset via monitor commands.

diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 00de5fc..ad09a0e 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -2194,10 +2194,13 @@ int gdb_input_inner(connection_t *connection)
 				retval = target_halt(target);
 				if (retval != ERROR_OK)
 				{
-					/* stop this debug session */
 					target_call_event_callbacks(target, TARGET_EVENT_GDB_HALT);
 				}
 				gdb_con->ctrl_c = 0;
+			} else
+			{
+				LOG_INFO("The target is not running when halt was requested, stopping GDB.");
+				target_call_event_callbacks(target, TARGET_EVENT_GDB_HALT);
 			}
 		}
 
diff --git a/src/target/target.c b/src/target/target.c
index ced09e9..8bb9371 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -378,24 +378,57 @@ target_t* get_current_target(command_context_t *cmd_ctx)
 
 int target_poll(struct target_s *target)
 {
+	int retval;
+
 	/* We can't poll until after examine */
 	if (!target_was_examined(target))
 	{
 		/* Fail silently lest we pollute the log */
 		return ERROR_FAIL;
 	}
-	return target->type->poll(target);
+
+	retval = target->type->poll(target);
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (target->halt_issued)
+	{
+		if (target->state == TARGET_HALTED)
+		{
+			target->halt_issued = false;
+		} else
+		{
+			long long t = timeval_ms() - target->halt_issued_time;
+			if (t>1000)
+			{
+				target->halt_issued = false;
+				LOG_INFO("Halt timed out, wake up GDB.");
+				target_call_event_callbacks(target, TARGET_EVENT_GDB_HALT);
+			}
+		}
+	}
+
+	return ERROR_OK;
 }
 
 int target_halt(struct target_s *target)
 {
+	int retval;
 	/* We can't poll until after examine */
 	if (!target_was_examined(target))
 	{
 		LOG_ERROR("Target not examined yet");
 		return ERROR_FAIL;
 	}
-	return target->type->halt(target);
+
+	retval = target->type->halt(target);
+	if (retval != ERROR_OK)
+		return retval;
+
+	target->halt_issued = true;
+	target->halt_issued_time = timeval_ms();
+
+	return ERROR_OK;
 }
 
 int target_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
@@ -4236,6 +4269,8 @@ static int target_create(Jim_GetOptInfo *goi)
 
 	target->display             = 1;
 
+	target->halt_issued			= false;
+
 	/* initialize trace information */
 	target->trace_info = malloc(sizeof(trace_t));
 	target->trace_info->num_trace_points         = 0;
diff --git a/src/target/target.h b/src/target/target.h
index 6547d4d..0f8be6f 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -148,6 +148,8 @@ typedef struct target_s
 
 	int display;						/* display async info in telnet session. Do not display
 										 * lots of halted/resumed info when stepping in debugger. */
+	bool halt_issued;					/* did we transition to halted state? */
+	long long halt_issued_time;			/* Note time when halt was issued */
 } target_t;
 
 enum target_event

commit 6b72f2486be59dbfea53e511aaf1adfb5fa68f05
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Oct 12 09:25:08 2009 +0200

    Supply default reset_config statement to make target scripts useful standalone and provide sensible default

diff --git a/tcl/target/imx31.cfg b/tcl/target/imx31.cfg
index ad99975..f579d6e 100644
--- a/tcl/target/imx31.cfg
+++ b/tcl/target/imx31.cfg
@@ -1,7 +1,7 @@
 # imx31 config
 #
 
-reset_config trst_and_srst
+reset_config trst_and_srst srst_nogate
 
 if { [info exists CHIPNAME] } {
    set  _CHIPNAME $CHIPNAME
diff --git a/tcl/target/imx35.cfg b/tcl/target/imx35.cfg
index 446eef6..800e142 100644
--- a/tcl/target/imx35.cfg
+++ b/tcl/target/imx35.cfg
@@ -1,6 +1,9 @@
 # imx35 config
 #
 
+reset_config trst_and_srst srst_nogate
+
+
 if { [info exists CHIPNAME] } {
    set  _CHIPNAME $CHIPNAME
 } else {

-----------------------------------------------------------------------

Summary of changes:
 src/server/gdb_server.c |    5 ++++-
 src/target/target.c     |   39 +++++++++++++++++++++++++++++++++++++--
 src/target/target.h     |    2 ++
 tcl/target/imx31.cfg    |    2 +-
 tcl/target/imx35.cfg    |    3 +++
 5 files changed, 47 insertions(+), 4 deletions(-)


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- Log -----------------------------------------------------------------
commit 6451563ce849929e43de1c3d72359846c8141375
Author: David Brownell <dbr...@us...>
Date:   Sun Oct 11 10:35:52 2009 -0700

    xscale_load_ic cleanup
    
    Remove unused and deprecated (in the arch spec) mode for loading
    code into the *main* icache (vs the "mini" icache).  Disable some
    extremely noisy (and rarely useful) low-level debug messages
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/xscale.c b/src/target/xscale.c
index 705c2f0..f245a20 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -705,16 +705,16 @@ static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
 static unsigned int parity (unsigned int v)
 {
-	unsigned int ov = v;
+	// unsigned int ov = v;
 	v ^= v >> 16;
 	v ^= v >> 8;
 	v ^= v >> 4;
 	v &= 0xf;
-	LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
+	// LOG_DEBUG("parity of 0x%x is %i", ov, (0x6996 >> v) & 1);
 	return (0x6996 >> v) & 1;
 }
 
-static int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8])
+static int xscale_load_ic(target_t *target, uint32_t va, uint32_t buffer[8])
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -726,16 +726,15 @@ static int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buff
 
 	LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
 
+	/* LDIC into IR */
 	jtag_set_end_state(TAP_IDLE);
-	xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
-
-	/* CMD is b010 for Main IC and b011 for Mini IC */
-	if (mini)
-		buf_set_u32(&cmd, 0, 3, 0x3);
-	else
-		buf_set_u32(&cmd, 0, 3, 0x2);
+	xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic);
 
-	buf_set_u32(&cmd, 3, 3, 0x0);
+	/* CMD is b011 to load a cacheline into the Mini ICache.
+	 * Loading into the main ICache is deprecated, and unused.
+	 * It's followed by three zero bits, and 27 address bits.
+	 */
+	buf_set_u32(&cmd, 0, 6, 0x3);
 
 	/* virtual address of desired cache line */
 	buf_set_u32(packet, 0, 27, va >> 5);
@@ -752,6 +751,7 @@ static int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buff
 
 	jtag_add_dr_scan(2, fields, jtag_get_end_state());
 
+	/* rest of packet is a cacheline: 8 instructions, with parity */
 	fields[0].num_bits = 32;
 	fields[0].out_value = packet;
 
@@ -864,8 +864,8 @@ static int xscale_update_vectors(target_t *target)
 	xscale_invalidate_ic_line(target, 0x0);
 	xscale_invalidate_ic_line(target, 0xffff0000);
 
-	xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
-	xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
+	xscale_load_ic(target, 0x0, xscale->low_vectors);
+	xscale_load_ic(target, 0xffff0000, xscale->high_vectors);
 
 	return ERROR_OK;
 }
@@ -1665,15 +1665,15 @@ static int xscale_deassert_reset(target_t *target)
 			/* only load addresses other than the reset vectors */
 			if ((address % 0x400) != 0x0)
 			{
-				xscale_load_ic(target, 1, address, cache_line);
+				xscale_load_ic(target, address, cache_line);
 			}
 
 			address += buf_cnt;
 			binary_size -= buf_cnt;
 		};
 
-		xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
-		xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
+		xscale_load_ic(target, 0x0, xscale->low_vectors);
+		xscale_load_ic(target, 0xffff0000, xscale->high_vectors);
 
 		jtag_add_runtest(30, jtag_set_end_state(TAP_IDLE));
 

commit 2d035d8640ad6c0946edaf423abd17e6b2e1af6e
Author: David Brownell <dbr...@us...>
Date:   Sun Oct 11 10:35:28 2009 -0700

    xscale.c cleanup
    
    Declare almost everything as static.
    Move stuff to remove most forward references.
    Remove most forward declarations.
    Warn if the unimplemented register functions get called.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/xscale.c b/src/target/xscale.c
index 38ed167..705c2f0 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -55,87 +55,19 @@
  * Chip-specific microarchitecture documents may also be useful.
  */
 
-/* cli handling */
-int xscale_register_commands(struct command_context_s *cmd_ctx);
 
 /* forward declarations */
-int xscale_target_create(struct target_s *target, Jim_Interp *interp);
-int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
-int xscale_quit(void);
-
-int xscale_arch_state(struct target_s *target);
-int xscale_poll(target_t *target);
-int xscale_halt(target_t *target);
-int xscale_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution);
-int xscale_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints);
-int xscale_debug_entry(target_t *target);
-int xscale_restore_context(target_t *target);
-
-int xscale_assert_reset(target_t *target);
-int xscale_deassert_reset(target_t *target);
-
-int xscale_set_reg_u32(reg_t *reg, uint32_t value);
-
-int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode);
-int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value);
-
-int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-int xscale_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer);
-
-int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint);
-int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
-int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
-void xscale_enable_watchpoints(struct target_s *target);
-void xscale_enable_breakpoints(struct target_s *target);
-static int xscale_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical);
-static int xscale_mmu(struct target_s *target, int *enabled);
-
-int xscale_read_trace(target_t *target);
+static int xscale_resume(struct target_s *, int current,
+	uint32_t address, int handle_breakpoints, int debug_execution);
+static int xscale_debug_entry(target_t *);
+static int xscale_restore_context(target_t *);
+static int xscale_get_reg(reg_t *reg);
+static int xscale_set_reg(reg_t *reg, uint8_t *buf);
+static int xscale_set_breakpoint(struct target_s *, breakpoint_t *);
+static int xscale_set_watchpoint(struct target_s *, watchpoint_t *);
+static int xscale_unset_breakpoint(struct target_s *, breakpoint_t *);
+static int xscale_read_trace(target_t *);
 
-target_type_t xscale_target =
-{
-	.name = "xscale",
-
-	.poll = xscale_poll,
-	.arch_state = xscale_arch_state,
-
-	.target_request_data = NULL,
-
-	.halt = xscale_halt,
-	.resume = xscale_resume,
-	.step = xscale_step,
-
-	.assert_reset = xscale_assert_reset,
-	.deassert_reset = xscale_deassert_reset,
-	.soft_reset_halt = NULL,
-
-	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
-
-	.read_memory = xscale_read_memory,
-	.write_memory = xscale_write_memory,
-	.bulk_write_memory = xscale_bulk_write_memory,
-	.checksum_memory = arm7_9_checksum_memory,
-	.blank_check_memory = arm7_9_blank_check_memory,
-
-	.run_algorithm = armv4_5_run_algorithm,
-
-	.add_breakpoint = xscale_add_breakpoint,
-	.remove_breakpoint = xscale_remove_breakpoint,
-	.add_watchpoint = xscale_add_watchpoint,
-	.remove_watchpoint = xscale_remove_watchpoint,
-
-	.register_commands = xscale_register_commands,
-	.target_create = xscale_target_create,
-	.init_target = xscale_init_target,
-	.quit = xscale_quit,
-
-	.virt2phys = xscale_virt2phys,
-	.mmu = xscale_mmu
-};
 
 static char *const xscale_reg_list[] =
 {
@@ -191,10 +123,19 @@ static const xscale_reg_t xscale_reg_arch_info[] =
 
 static int xscale_reg_arch_type = -1;
 
-int xscale_get_reg(reg_t *reg);
-int xscale_set_reg(reg_t *reg, uint8_t *buf);
+/* convenience wrapper to access XScale specific registers */
+static int xscale_set_reg_u32(reg_t *reg, uint32_t value)
+{
+	uint8_t buf[4];
+
+	buf_set_u32(buf, 0, 32, value);
 
-int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xscale_common_t **xscale_p)
+	return xscale_set_reg(reg, buf);
+}
+
+
+static int xscale_get_arch_pointers(target_t *target,
+		armv4_5_common_t **armv4_5_p, xscale_common_t **xscale_p)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -217,7 +158,7 @@ int xscale_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, xsc
 	return ERROR_OK;
 }
 
-int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr)
+static int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr)
 {
 	if (tap == NULL)
 		return ERROR_FAIL;
@@ -245,7 +186,7 @@ int xscale_jtag_set_instr(jtag_tap_t *tap, uint32_t new_instr)
 	return ERROR_OK;
 }
 
-int xscale_read_dcsr(target_t *target)
+static int xscale_read_dcsr(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -320,7 +261,7 @@ static void xscale_getbuf(jtag_callback_data_t arg)
 	*((uint32_t *)in) = buf_get_u32(in, 0, 32);
 }
 
-int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
+static int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
 {
 	if (num_words == 0)
 		return ERROR_INVALID_ARGUMENTS;
@@ -434,7 +375,7 @@ int xscale_receive(target_t *target, uint32_t *buffer, int num_words)
 	return retval;
 }
 
-int xscale_read_tx(target_t *target, int consume)
+static int xscale_read_tx(target_t *target, int consume)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -536,7 +477,7 @@ int xscale_read_tx(target_t *target, int consume)
 	return ERROR_OK;
 }
 
-int xscale_write_rx(target_t *target)
+static int xscale_write_rx(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -624,7 +565,7 @@ int xscale_write_rx(target_t *target)
 }
 
 /* send count elements of size byte to the debug handler */
-int xscale_send(target_t *target, uint8_t *buffer, int count, int size)
+static int xscale_send(target_t *target, uint8_t *buffer, int count, int size)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -691,7 +632,7 @@ int xscale_send(target_t *target, uint8_t *buffer, int count, int size)
 	return ERROR_OK;
 }
 
-int xscale_send_u32(target_t *target, uint32_t value)
+static int xscale_send_u32(target_t *target, uint32_t value)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -700,7 +641,7 @@ int xscale_send_u32(target_t *target, uint32_t value)
 	return xscale_write_rx(target);
 }
 
-int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
+static int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -762,7 +703,7 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
 }
 
 /* parity of the number of bits 0 if even; 1 if odd. for 32 bit words */
-unsigned int parity (unsigned int v)
+static unsigned int parity (unsigned int v)
 {
 	unsigned int ov = v;
 	v ^= v >> 16;
@@ -773,7 +714,7 @@ unsigned int parity (unsigned int v)
 	return (0x6996 >> v) & 1;
 }
 
-int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8])
+static int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8])
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -831,7 +772,7 @@ int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8])
 	return jtag_execute_queue();
 }
 
-int xscale_invalidate_ic_line(target_t *target, uint32_t va)
+static int xscale_invalidate_ic_line(target_t *target, uint32_t va)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -864,7 +805,7 @@ int xscale_invalidate_ic_line(target_t *target, uint32_t va)
 	return ERROR_OK;
 }
 
-int xscale_update_vectors(target_t *target)
+static int xscale_update_vectors(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -929,7 +870,7 @@ int xscale_update_vectors(target_t *target)
 	return ERROR_OK;
 }
 
-int xscale_arch_state(struct target_s *target)
+static int xscale_arch_state(struct target_s *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -967,7 +908,7 @@ int xscale_arch_state(struct target_s *target)
 	return ERROR_OK;
 }
 
-int xscale_poll(target_t *target)
+static int xscale_poll(target_t *target)
 {
 	int retval = ERROR_OK;
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -1011,7 +952,7 @@ int xscale_poll(target_t *target)
 	return retval;
 }
 
-int xscale_debug_entry(target_t *target)
+static int xscale_debug_entry(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -1192,7 +1133,7 @@ int xscale_debug_entry(target_t *target)
 	return ERROR_OK;
 }
 
-int xscale_halt(target_t *target)
+static int xscale_halt(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -1227,7 +1168,7 @@ int xscale_halt(target_t *target)
 	return ERROR_OK;
 }
 
-int xscale_enable_single_step(struct target_s *target, uint32_t next_pc)
+static int xscale_enable_single_step(struct target_s *target, uint32_t next_pc)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale= armv4_5->arch_info;
@@ -1255,7 +1196,7 @@ int xscale_enable_single_step(struct target_s *target, uint32_t next_pc)
 	return ERROR_OK;
 }
 
-int xscale_disable_single_step(struct target_s *target)
+static int xscale_disable_single_step(struct target_s *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale= armv4_5->arch_info;
@@ -1268,7 +1209,33 @@ int xscale_disable_single_step(struct target_s *target)
 	return ERROR_OK;
 }
 
-int xscale_resume(struct target_s *target, int current, uint32_t address, int handle_breakpoints, int debug_execution)
+static void xscale_enable_watchpoints(struct target_s *target)
+{
+	watchpoint_t *watchpoint = target->watchpoints;
+
+	while (watchpoint)
+	{
+		if (watchpoint->set == 0)
+			xscale_set_watchpoint(target, watchpoint);
+		watchpoint = watchpoint->next;
+	}
+}
+
+static void xscale_enable_breakpoints(struct target_s *target)
+{
+	breakpoint_t *breakpoint = target->breakpoints;
+
+	/* set any pending breakpoints */
+	while (breakpoint)
+	{
+		if (breakpoint->set == 0)
+			xscale_set_breakpoint(target, breakpoint);
+		breakpoint = breakpoint->next;
+	}
+}
+
+static int xscale_resume(struct target_s *target, int current,
+		uint32_t address, int handle_breakpoints, int debug_execution)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale= armv4_5->arch_info;
@@ -1424,7 +1391,8 @@ int xscale_resume(struct target_s *target, int current, uint32_t address, int ha
 	return ERROR_OK;
 }
 
-static int xscale_step_inner(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
+static int xscale_step_inner(struct target_s *target, int current,
+		uint32_t address, int handle_breakpoints)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -1504,7 +1472,8 @@ static int xscale_step_inner(struct target_s *target, int current, uint32_t addr
 	return ERROR_OK;
 }
 
-int xscale_step(struct target_s *target, int current, uint32_t address, int handle_breakpoints)
+static int xscale_step(struct target_s *target, int current,
+		uint32_t address, int handle_breakpoints)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	breakpoint_t *breakpoint = target->breakpoints;
@@ -1558,7 +1527,7 @@ int xscale_step(struct target_s *target, int current, uint32_t address, int hand
 
 }
 
-int xscale_assert_reset(target_t *target)
+static int xscale_assert_reset(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -1600,7 +1569,7 @@ int xscale_assert_reset(target_t *target)
 	return ERROR_OK;
 }
 
-int xscale_deassert_reset(target_t *target)
+static int xscale_deassert_reset(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -1741,18 +1710,21 @@ int xscale_deassert_reset(target_t *target)
 	return ERROR_OK;
 }
 
-int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
+static int xscale_read_core_reg(struct target_s *target, int num,
+		enum armv4_5_mode mode)
 {
+	LOG_ERROR("not implemented");
 	return ERROR_OK;
 }
 
-int xscale_write_core_reg(struct target_s *target, int num, enum armv4_5_mode mode, uint32_t value)
+static int xscale_write_core_reg(struct target_s *target, int num,
+		enum armv4_5_mode mode, uint32_t value)
 {
-
+	LOG_ERROR("not implemented");
 	return ERROR_OK;
 }
 
-int xscale_full_context(target_t *target)
+static int xscale_full_context(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 
@@ -1828,14 +1800,12 @@ int xscale_full_context(target_t *target)
 	return ERROR_OK;
 }
 
-int xscale_restore_context(target_t *target)
+static int xscale_restore_context(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 
 	int i, j;
 
-	LOG_DEBUG("-");
-
 	if (target->state != TARGET_HALTED)
 	{
 		LOG_WARNING("target not halted");
@@ -1897,7 +1867,8 @@ int xscale_restore_context(target_t *target)
 	return ERROR_OK;
 }
 
-int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+static int xscale_read_memory(struct target_s *target, uint32_t address,
+		uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -1976,7 +1947,8 @@ int xscale_read_memory(struct target_s *target, uint32_t address, uint32_t size,
 	return ERROR_OK;
 }
 
-int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+static int xscale_write_memory(struct target_s *target, uint32_t address,
+		uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -2054,12 +2026,13 @@ int xscale_write_memory(struct target_s *target, uint32_t address, uint32_t size
 	return ERROR_OK;
 }
 
-int xscale_bulk_write_memory(target_t *target, uint32_t address, uint32_t count, uint8_t *buffer)
+static int xscale_bulk_write_memory(target_t *target, uint32_t address,
+		uint32_t count, uint8_t *buffer)
 {
 	return xscale_write_memory(target, address, 4, count, buffer);
 }
 
-uint32_t xscale_get_ttb(target_t *target)
+static uint32_t xscale_get_ttb(target_t *target)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -2071,7 +2044,8 @@ uint32_t xscale_get_ttb(target_t *target)
 	return ttb;
 }
 
-void xscale_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
+static void xscale_disable_mmu_caches(target_t *target, int mmu,
+		int d_u_cache, int i_cache)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -2110,7 +2084,8 @@ void xscale_disable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_c
 	xscale_send_u32(target, 0x53);
 }
 
-void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_cache)
+static void xscale_enable_mmu_caches(target_t *target, int mmu,
+		int d_u_cache, int i_cache)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -2136,7 +2111,8 @@ void xscale_enable_mmu_caches(target_t *target, int mmu, int d_u_cache, int i_ca
 	xscale_send_u32(target, 0x53);
 }
 
-int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+static int xscale_set_breakpoint(struct target_s *target,
+		breakpoint_t *breakpoint)
 {
 	int retval;
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2209,7 +2185,8 @@ int xscale_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 	return ERROR_OK;
 }
 
-int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+static int xscale_add_breakpoint(struct target_s *target,
+		breakpoint_t *breakpoint)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -2240,7 +2217,8 @@ int xscale_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 	return ERROR_OK;
 }
 
-int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+static int xscale_unset_breakpoint(struct target_s *target,
+		breakpoint_t *breakpoint)
 {
 	int retval;
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2295,7 +2273,7 @@ int xscale_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 	return ERROR_OK;
 }
 
-int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
+static int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -2317,7 +2295,8 @@ int xscale_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
 	return ERROR_OK;
 }
 
-int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+static int xscale_set_watchpoint(struct target_s *target,
+		watchpoint_t *watchpoint)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -2373,7 +2352,8 @@ int xscale_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 	return ERROR_OK;
 }
 
-int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+static int xscale_add_watchpoint(struct target_s *target,
+		watchpoint_t *watchpoint)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -2399,7 +2379,8 @@ int xscale_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 	return ERROR_OK;
 }
 
-int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+static int xscale_unset_watchpoint(struct target_s *target,
+		watchpoint_t *watchpoint)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -2435,7 +2416,7 @@ int xscale_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 	return ERROR_OK;
 }
 
-int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
+static int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 {
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
@@ -2456,32 +2437,7 @@ int xscale_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
 	return ERROR_OK;
 }
 
-void xscale_enable_watchpoints(struct target_s *target)
-{
-	watchpoint_t *watchpoint = target->watchpoints;
-
-	while (watchpoint)
-	{
-		if (watchpoint->set == 0)
-			xscale_set_watchpoint(target, watchpoint);
-		watchpoint = watchpoint->next;
-	}
-}
-
-void xscale_enable_breakpoints(struct target_s *target)
-{
-	breakpoint_t *breakpoint = target->breakpoints;
-
-	/* set any pending breakpoints */
-	while (breakpoint)
-	{
-		if (breakpoint->set == 0)
-			xscale_set_breakpoint(target, breakpoint);
-		breakpoint = breakpoint->next;
-	}
-}
-
-int xscale_get_reg(reg_t *reg)
+static int xscale_get_reg(reg_t *reg)
 {
 	xscale_reg_t *arch_info = reg->arch_info;
 	target_t *target = arch_info->target;
@@ -2527,7 +2483,7 @@ int xscale_get_reg(reg_t *reg)
 	return ERROR_OK;
 }
 
-int xscale_set_reg(reg_t *reg, uint8_t* buf)
+static int xscale_set_reg(reg_t *reg, uint8_t* buf)
 {
 	xscale_reg_t *arch_info = reg->arch_info;
 	target_t *target = arch_info->target;
@@ -2572,17 +2528,7 @@ int xscale_set_reg(reg_t *reg, uint8_t* buf)
 	return ERROR_OK;
 }
 
-/* convenience wrapper to access XScale specific registers */
-int xscale_set_reg_u32(reg_t *reg, uint32_t value)
-{
-	uint8_t buf[4];
-
-	buf_set_u32(buf, 0, 32, value);
-
-	return xscale_set_reg(reg, buf);
-}
-
-int xscale_write_dcsr_sw(target_t *target, uint32_t value)
+static int xscale_write_dcsr_sw(target_t *target, uint32_t value)
 {
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2603,7 +2549,7 @@ int xscale_write_dcsr_sw(target_t *target, uint32_t value)
 	return ERROR_OK;
 }
 
-int xscale_read_trace(target_t *target)
+static int xscale_read_trace(target_t *target)
 {
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2682,7 +2628,8 @@ int xscale_read_trace(target_t *target)
 	return ERROR_OK;
 }
 
-int xscale_read_instruction(target_t *target, arm_instruction_t *instruction)
+static int xscale_read_instruction(target_t *target,
+		arm_instruction_t *instruction)
 {
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2748,7 +2695,8 @@ int xscale_read_instruction(target_t *target, arm_instruction_t *instruction)
 	return ERROR_OK;
 }
 
-int xscale_branch_address(xscale_trace_data_t *trace_data, int i, uint32_t *target)
+static int xscale_branch_address(xscale_trace_data_t *trace_data,
+		int i, uint32_t *target)
 {
 	/* if there are less than four entries prior to the indirect branch message
 	 * we can't extract the address */
@@ -2763,7 +2711,7 @@ int xscale_branch_address(xscale_trace_data_t *trace_data, int i, uint32_t *targ
 	return 0;
 }
 
-int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
+static int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
 {
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2952,7 +2900,7 @@ int xscale_analyze_trace(target_t *target, command_context_t *cmd_ctx)
 	return ERROR_OK;
 }
 
-void xscale_build_reg_cache(target_t *target)
+static void xscale_build_reg_cache(target_t *target)
 {
 	/* get pointers to arch-specific information */
 	armv4_5_common_t *armv4_5 = target->arch_info;
@@ -2997,17 +2945,20 @@ void xscale_build_reg_cache(target_t *target)
 	xscale->reg_cache = (*cache_p);
 }
 
-int xscale_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
+static int xscale_init_target(struct command_context_s *cmd_ctx,
+		struct target_s *target)
 {
 	return ERROR_OK;
 }
 
-int xscale_quit(void)
+static int xscale_quit(void)
 {
+	jtag_add_runtest(100, TAP_RESET);
 	return ERROR_OK;
 }
 
-int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, jtag_tap_t *tap, const char *variant)
+static int xscale_init_arch_info(target_t *target,
+		xscale_common_t *xscale, jtag_tap_t *tap, const char *variant)
 {
 	armv4_5_common_t *armv4_5;
 	uint32_t high_reset_branch, low_reset_branch;
@@ -3116,7 +3067,7 @@ int xscale_init_arch_info(target_t *target, xscale_common_t *xscale, jtag_tap_t
 }
 
 /* target xscale <endianess> <startup_mode> <chain_pos> <variant> */
-int xscale_target_create(struct target_s *target, Jim_Interp *interp)
+static int xscale_target_create(struct target_s *target, Jim_Interp *interp)
 {
 	xscale_common_t *xscale = calloc(1,sizeof(xscale_common_t));
 
@@ -3126,7 +3077,9 @@ int xscale_target_create(struct target_s *target, Jim_Interp *interp)
 	return ERROR_OK;
 }
 
-int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int
+xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target = NULL;
 	armv4_5_common_t *armv4_5;
@@ -3167,7 +3120,9 @@ int xscale_handle_debug_handler_command(struct command_context_s *cmd_ctx, char
 	return ERROR_OK;
 }
 
-int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int
+xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target = NULL;
 	armv4_5_common_t *armv4_5;
@@ -3206,7 +3161,9 @@ int xscale_handle_cache_clean_address_command(struct command_context_s *cmd_ctx,
 	return ERROR_OK;
 }
 
-int xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int
+xscale_handle_cache_info_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5;
@@ -3220,7 +3177,8 @@ int xscale_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cm
 	return armv4_5_handle_cache_info_command(cmd_ctx, &xscale->armv4_5_mmu.armv4_5_cache);
 }
 
-static int xscale_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical)
+static int xscale_virt2phys(struct target_s *target,
+		uint32_t virtual, uint32_t *physical)
 {
 	armv4_5_common_t *armv4_5;
 	xscale_common_t *xscale;
@@ -3257,7 +3215,8 @@ static int xscale_mmu(struct target_s *target, int *enabled)
 	return ERROR_OK;
 }
 
-int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
+static int xscale_handle_mmu_command(command_context_t *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5;
@@ -3293,7 +3252,8 @@ int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args
 	return ERROR_OK;
 }
 
-int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
+static int xscale_handle_idcache_command(command_context_t *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5;
@@ -3347,7 +3307,8 @@ int xscale_handle_idcache_command(command_context_t *cmd_ctx, char *cmd, char **
 	return ERROR_OK;
 }
 
-int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
+static int xscale_handle_vector_catch_command(command_context_t *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5;
@@ -3375,7 +3336,8 @@ int xscale_handle_vector_catch_command(command_context_t *cmd_ctx, char *cmd, ch
 }
 
 
-int xscale_handle_vector_table_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
+static int xscale_handle_vector_table_command(command_context_t *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5;
@@ -3434,7 +3396,9 @@ int xscale_handle_vector_table_command(command_context_t *cmd_ctx, char *cmd, ch
 }
 
 
-int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int
+xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5;
@@ -3513,7 +3477,9 @@ int xscale_handle_trace_buffer_command(struct command_context_s *cmd_ctx, char *
 	return ERROR_OK;
 }
 
-int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int
+xscale_handle_trace_image_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target;
 	armv4_5_common_t *armv4_5;
@@ -3564,7 +3530,8 @@ int xscale_handle_trace_image_command(struct command_context_s *cmd_ctx, char *c
 	return ERROR_OK;
 }
 
-int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5;
@@ -3622,7 +3589,9 @@ int xscale_handle_dump_trace_command(struct command_context_s *cmd_ctx, char *cm
 	return ERROR_OK;
 }
 
-int xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+static int
+xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5;
@@ -3638,7 +3607,8 @@ int xscale_handle_analyze_trace_buffer_command(struct command_context_s *cmd_ctx
 	return ERROR_OK;
 }
 
-int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
+static int xscale_handle_cp15(command_context_t *cmd_ctx,
+		char *cmd, char **args, int argc)
 {
 	target_t *target = get_current_target(cmd_ctx);
 	armv4_5_common_t *armv4_5;
@@ -3727,7 +3697,7 @@ int xscale_handle_cp15(command_context_t *cmd_ctx, char *cmd, char **args, int a
 	return ERROR_OK;
 }
 
-int xscale_register_commands(struct command_context_s *cmd_ctx)
+static int xscale_register_commands(struct command_context_s *cmd_ctx)
 {
 	command_t *xscale_cmd;
 
@@ -3757,3 +3727,44 @@ int xscale_register_commands(struct command_context_s *cmd_ctx)
 
 	return ERROR_OK;
 }
+
+target_type_t xscale_target =
+{
+	.name = "xscale",
+
+	.poll = xscale_poll,
+	.arch_state = xscale_arch_state,
+
+	.target_request_data = NULL,
+
+	.halt = xscale_halt,
+	.resume = xscale_resume,
+	.step = xscale_step,
+
+	.assert_reset = xscale_assert_reset,
+	.deassert_reset = xscale_deassert_reset,
+	.soft_reset_halt = NULL,
+
+	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+
+	.read_memory = xscale_read_memory,
+	.write_memory = xscale_write_memory,
+	.bulk_write_memory = xscale_bulk_write_memory,
+	.checksum_memory = arm7_9_checksum_memory,
+	.blank_check_memory = arm7_9_blank_check_memory,
+
+	.run_algorithm = armv4_5_run_algorithm,
+
+	.add_breakpoint = xscale_add_breakpoint,
+	.remove_breakpoint = xscale_remove_breakpoint,
+	.add_watchpoint = xscale_add_watchpoint,
+	.remove_watchpoint = xscale_remove_watchpoint,
+
+	.register_commands = xscale_register_commands,
+	.target_create = xscale_target_create,
+	.init_target = xscale_init_target,
+	.quit = xscale_quit,
+
+	.virt2phys = xscale_virt2phys,
+	.mmu = xscale_mmu
+};

commit 3c75764434ae46710de17020dac3c6fd0f5e0663
Author: David Brownell <dbr...@us...>
Date:   Sun Oct 11 10:06:08 2009 -0700

    xscale bugfix to handler loading
    
    Just fill out the rest of the cache line with NOPs; don't change
    the record of how much data we consumed.  Otherwise the count of
    how much data is left can roll over from positive to negative
    ("VERY positive") and skip the loop termination of zero.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/xscale.c b/src/target/xscale.c
index b46b621..38ed167 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -1688,9 +1688,9 @@ int xscale_deassert_reset(target_t *target)
 				cache_line[i / 4] = le_to_h_u32(&buffer[i]);
 			}
 
-			for (; buf_cnt < 32; buf_cnt += 4)
+			for (; i < 32; i += 4)
 			{
-				cache_line[buf_cnt / 4] = 0xe1a08008;
+				cache_line[i / 4] = 0xe1a08008;
 			}
 
 			/* only load addresses other than the reset vectors */

commit d62e80769a23c8855d22e132318fd2b2f8c0ea97
Author: David Brownell <dbr...@us...>
Date:   Sun Oct 11 02:52:00 2009 -0700

    xscale minor cleanup
    
    Add a header comment referencing useful XScale specs.
    Make most data static, and the tables readonly.
    Scrub extra blank lines.
    Return fault codes from one routine.
    Remove a needless NOP methood.
    
    (BUGFIX) When we update R0, mark R0 as dirty/valid ... not R15/PC!
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/xscale.c b/src/target/xscale.c
index 40126c9..b46b621 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -35,6 +35,26 @@
 #include "time_support.h"
 #include "image.h"
 
+
+/*
+ * Important XScale documents available as of October 2009 include:
+ *
+ *  Intel XScale® Core Developer’s Manual, January 2004
+ *		Order Number: 273473-002
+ *	This has a chapter detailing debug facilities, and punts some
+ *	details to chip-specific microarchitecture documentats.
+ *
+ *  Hot-Debug for Intel XScale® Core Debug White Paper, May 2005
+ *		Document Number: 273539-005
+ *	Less detailed than the developer's manual, but summarizes those
+ *	missing details (for most XScales) and gives LOTS of notes about
+ *	debugger/handler interaction issues.  Presents a simpler reset
+ *	and load-handler sequence than the arch doc.  (Note, OpenOCD
+ *	doesn't currently support "Hot-Debug" as defined there.)
+ *
+ * Chip-specific microarchitecture documents may also be useful.
+ */
+
 /* cli handling */
 int xscale_register_commands(struct command_context_s *cmd_ctx);
 
@@ -53,7 +73,6 @@ int xscale_restore_context(target_t *target);
 
 int xscale_assert_reset(target_t *target);
 int xscale_deassert_reset(target_t *target);
-int xscale_soft_reset_halt(struct target_s *target);
 
 int xscale_set_reg_u32(reg_t *reg, uint32_t value);
 
@@ -92,7 +111,7 @@ target_type_t xscale_target =
 
 	.assert_reset = xscale_assert_reset,
 	.deassert_reset = xscale_deassert_reset,
-	.soft_reset_halt = xscale_soft_reset_halt,
+	.soft_reset_halt = NULL,
 
 	.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
 
@@ -118,7 +137,7 @@ target_type_t xscale_target =
 	.mmu = xscale_mmu
 };
 
-char* xscale_reg_list[] =
+static char *const xscale_reg_list[] =
 {
 	"XSCALE_MAINID",		/* 0 */
 	"XSCALE_CACHETYPE",
@@ -144,7 +163,7 @@ char* xscale_reg_list[] =
 	"XSCALE_TXRXCTRL",
 };
 
-xscale_reg_t xscale_reg_arch_info[] =
+static const xscale_reg_t xscale_reg_arch_info[] =
 {
 	{XSCALE_MAINID, NULL},
 	{XSCALE_CACHETYPE, NULL},
@@ -170,7 +189,7 @@ xscale_reg_t xscale_reg_arch_info[] =
 	{-1, NULL}, /* TXRXCTRL implicit access via JTAG */
 };
 
-int xscale_reg_arch_type = -1;
+static int xscale_reg_arch_type = -1;
 
 int xscale_get_reg(reg_t *reg);
 int xscale_set_reg(reg_t *reg, uint8_t *buf);
@@ -258,7 +277,6 @@ int xscale_read_dcsr(target_t *target)
 	fields[1].out_value = NULL;
 	fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 
-
 	fields[2].tap = xscale->jtag_info.tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = &field2;
@@ -298,7 +316,7 @@ int xscale_read_dcsr(target_t *target)
 
 static void xscale_getbuf(jtag_callback_data_t arg)
 {
-  uint8_t *in = (uint8_t *)arg;
+	uint8_t *in = (uint8_t *)arg;
 	*((uint32_t *)in) = buf_get_u32(in, 0, 32);
 }
 
@@ -458,7 +476,6 @@ int xscale_read_tx(target_t *target, int consume)
 	fields[1].out_value = NULL;
 	fields[1].in_value = xscale->reg_cache->reg_list[XSCALE_TX].value;
 
-
 	fields[2].tap = xscale->jtag_info.tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = NULL;
@@ -550,7 +567,6 @@ int xscale_write_rx(target_t *target)
 	fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_RX].value;
 	fields[1].in_value = NULL;
 
-
 	fields[2].tap = xscale->jtag_info.tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = &field2;
@@ -722,7 +738,6 @@ int xscale_write_dcsr(target_t *target, int hold_rst, int ext_dbg_brk)
 	fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 	fields[1].in_value = NULL;
 
-
 	fields[2].tap = xscale->jtag_info.tap;
 	fields[2].num_bits = 1;
 	fields[2].out_value = &field2;
@@ -787,23 +802,13 @@ int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8])
 	fields[0].tap = xscale->jtag_info.tap;
 	fields[0].num_bits = 6;
 	fields[0].out_value = &cmd;
-
 	fields[0].in_value = NULL;
 
-
-
-
-
 	fields[1].tap = xscale->jtag_info.tap;
 	fields[1].num_bits = 27;
 	fields[1].out_value = packet;
-
 	fields[1].in_value = NULL;
 
-
-
-
-
 	jtag_add_dr_scan(2, fields, jtag_get_end_state());
 
 	fields[0].num_bits = 32;
@@ -823,9 +828,7 @@ int xscale_load_ic(target_t *target, int mini, uint32_t va, uint32_t buffer[8])
 		jtag_add_dr_scan(2, fields, jtag_get_end_state());
 	}
 
-	jtag_execute_queue();
-
-	return ERROR_OK;
+	return jtag_execute_queue();
 }
 
 int xscale_invalidate_ic_line(target_t *target, uint32_t va)
@@ -849,23 +852,13 @@ int xscale_invalidate_ic_line(target_t *target, uint32_t va)
 	fields[0].tap = xscale->jtag_info.tap;
 	fields[0].num_bits = 6;
 	fields[0].out_value = &cmd;
-
 	fields[0].in_value = NULL;
 
-
-
-
-
 	fields[1].tap = xscale->jtag_info.tap;
 	fields[1].num_bits = 27;
 	fields[1].out_value = packet;
-
 	fields[1].in_value = NULL;
 
-
-
-
-
 	jtag_add_dr_scan(2, fields, jtag_get_end_state());
 
 	return ERROR_OK;
@@ -941,12 +934,12 @@ int xscale_arch_state(struct target_s *target)
 	armv4_5_common_t *armv4_5 = target->arch_info;
 	xscale_common_t *xscale = armv4_5->arch_info;
 
-	char *state[] =
+	static const char *state[] =
 	{
 		"disabled", "enabled"
 	};
 
-	char *arch_dbg_reason[] =
+	static const char *arch_dbg_reason[] =
 	{
 		"", "\n(processor reset)", "\n(trace buffer full)"
 	};
@@ -1040,8 +1033,8 @@ int xscale_debug_entry(target_t *target)
 
 	/* move r0 from buffer to register cache */
 	buf_set_u32(armv4_5->core_cache->reg_list[0].value, 0, 32, buffer[0]);
-	armv4_5->core_cache->reg_list[15].dirty = 1;
-	armv4_5->core_cache->reg_list[15].valid = 1;
+	armv4_5->core_cache->reg_list[0].dirty = 1;
+	armv4_5->core_cache->reg_list[0].valid = 1;
 	LOG_DEBUG("r0: 0x%8.8" PRIx32 "", buffer[0]);
 
 	/* move pc from buffer to register cache */
@@ -1148,7 +1141,7 @@ int xscale_debug_entry(target_t *target)
 			xscale->arch_debug_reason = XSCALE_DBG_REASON_TB_FULL;
 			pc -= 4;
 			break;
-		case 0x7: /* Reserved */
+		case 0x7: /* Reserved (may flag Hot-Debug support) */
 		default:
 			LOG_ERROR("Method of Entry is 'Reserved'");
 			exit(-1);
@@ -1748,11 +1741,6 @@ int xscale_deassert_reset(target_t *target)
 	return ERROR_OK;
 }
 
-int xscale_soft_reset_halt(struct target_s *target)
-{
-	return ERROR_OK;
-}
-
 int xscale_read_core_reg(struct target_s *target, int num, enum armv4_5_mode mode)
 {
 	return ERROR_OK;

-----------------------------------------------------------------------

Summary of changes:
 src/target/xscale.c |  487 +++++++++++++++++++++++++--------------------------
 1 files changed, 243 insertions(+), 244 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. 0.2.0-338-ga6ad76b

[David B. <dbr...@us...>]

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The branch, master has been updated
       via  a6ad76bba9cc7b73e836a04b48d3f3e9fa56de12 (commit)
      from  2ff66fee7b5b24eee162ee25d22726a04739e2c7 (commit)

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not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit a6ad76bba9cc7b73e836a04b48d3f3e9fa56de12
Author: David Brownell <dbr...@us...>
Date:   Sat Oct 10 11:32:39 2009 -0700

    printf format warning fixes
    
    Observed on a Cygwin build.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/flash/flash.c b/src/flash/flash.c
index 4c123f8..d1b023c 100644
--- a/src/flash/flash.c
+++ b/src/flash/flash.c
@@ -569,8 +569,8 @@ static int flash_check_sector_parameters(struct command_context_s *cmd_ctx,
 	}
 
 	if (!(last <= (num_sectors - 1))) {
-		command_print(cmd_ctx, "ERROR: "
-				"last sector must be <= %d", num_sectors - 1);
+		command_print(cmd_ctx, "ERROR: last sector must be <= %d",
+				(int) num_sectors - 1);
 		return ERROR_FAIL;
 	}
 
@@ -616,7 +616,8 @@ static int handle_flash_erase_command(struct command_context_s *cmd_ctx,
 				return retval;
 			command_print(cmd_ctx, "erased sectors %i through %i "
 					"on flash bank %i in %s",
-				first, last, bank_nr, duration_text);
+				(int) first, (int) last, (int) bank_nr,
+				duration_text);
 			free(duration_text);
 		}
 	}
@@ -667,8 +668,8 @@ static int handle_flash_protect_command(struct command_context_s *cmd_ctx,
 		if (retval == ERROR_OK) {
 			command_print(cmd_ctx, "%s protection for sectors %i "
 					"through %i on flash bank %i",
-				(set) ? "set" : "cleared", first,
-				last, bank_nr);
+				(set) ? "set" : "cleared", (int) first,
+				(int) last, (int) bank_nr);
 		}
 	}
 	else
diff --git a/src/flash/lpc2900.c b/src/flash/lpc2900.c
index 26ca67f..e39c531 100644
--- a/src/flash/lpc2900.c
+++ b/src/flash/lpc2900.c
@@ -444,9 +444,9 @@ static int lpc2900_write_index_page( struct flash_bank_s *bank,
                                      uint8_t (*page)[FLASH_PAGE_SIZE] )
 {
 	/* Only pages 4...7 are user writable */
-	if( (pagenum < 4) || (pagenum > 7) )
+	if ((pagenum < 4) || (pagenum > 7))
 	{
-		LOG_ERROR( "Refuse to burn index sector page %" PRIu32, pagenum );
+		LOG_ERROR("Refuse to burn index sector page %d", pagenum);
 		return ERROR_COMMAND_ARGUMENT_INVALID;
 	}
 
@@ -479,7 +479,7 @@ static int lpc2900_write_index_page( struct flash_bank_s *bank,
 	                         bank->base + pagenum * FLASH_PAGE_SIZE,
 	                         4, FLASH_PAGE_SIZE / 4, (uint8_t *)page) != ERROR_OK )
 	{
-		LOG_ERROR( "Index sector write failed @ page %" PRIu32, pagenum );
+		LOG_ERROR("Index sector write failed @ page %d", pagenum);
 		target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB );
 
 		return ERROR_FLASH_OPERATION_FAILED;
@@ -501,10 +501,10 @@ static int lpc2900_write_index_page( struct flash_bank_s *bank,
 	/* Wait for the end of the write operation. If it's not over after one
 	 * second, something went dreadfully wrong... :-(
 	 */
-	if( lpc2900_wait_status( bank, INTSRC_END_OF_BURN, 1000 ) != ERROR_OK )
+	if (lpc2900_wait_status(bank, INTSRC_END_OF_BURN, 1000) != ERROR_OK)
 	{
-		LOG_ERROR( "Index sector write failed @ page %" PRIu32, pagenum );
-		target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB );
+		LOG_ERROR("Index sector write failed @ page %d", pagenum);
+		target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
 
 		return ERROR_FLASH_OPERATION_FAILED;
 	}
@@ -796,7 +796,8 @@ static int lpc2900_handle_write_custom_command( struct command_context_s *cmd_ct
 	if( (image.sections[0].base_address != 0) ||
         (image.sections[0].size != ISS_CUSTOMER_SIZE) )
 	{
-		LOG_ERROR("Incorrect image file size. Expected %" PRIu32 ", got %" PRIu32,
+		LOG_ERROR("Incorrect image file size. Expected %d, "
+			"got %" PRIu32,
                    ISS_CUSTOMER_SIZE, image.sections[0].size);
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
@@ -1477,12 +1478,13 @@ static int lpc2900_write(struct flash_bank_s *bank, uint8_t *buffer,
 			}
 
 			/* Skip the current sector if it is secured */
-			if( bank->sectors[start_sector].is_protected )
+			if (bank->sectors[start_sector].is_protected)
 			{
-				LOG_DEBUG( "Skip secured sector %" PRIu32, start_sector );
+				LOG_DEBUG("Skip secured sector %d",
+						start_sector);
 
 				/* Stop if this is the last sector */
-				if( start_sector == bank->num_sectors - 1 )
+				if (start_sector == bank->num_sectors - 1)
 				{
 					break;
 				}
@@ -1763,9 +1765,9 @@ static int lpc2900_probe(struct flash_bank_s *bank)
 	}
 
 	/* Show detected device */
-	LOG_INFO("Flash bank %" PRIu32
+	LOG_INFO("Flash bank %d"
 	         ": Device %s, %" PRIu32
-	         " KiB in %" PRIu32 " sectors",
+	         " KiB in %d sectors",
 	         bank->bank_number,
 	         lpc2900_info->target_name, bank->size / KiB,
 	         bank->num_sectors);
@@ -1805,7 +1807,7 @@ static int lpc2900_probe(struct flash_bank_s *bank)
 			 * that has more than 19 sectors. Politely ask for a fix then.
 			 */
 			bank->sectors[i].size = 0;
-			LOG_ERROR("Never heard about sector %" PRIu32 " (FIXME please)", i);
+			LOG_ERROR("Never heard about sector %d", i);
 		}
 
 		offset += bank->sectors[i].size;
diff --git a/src/flash/mx3_nand.c b/src/flash/mx3_nand.c
index 20ab91e..a5df003 100644
--- a/src/flash/mx3_nand.c
+++ b/src/flash/mx3_nand.c
@@ -40,9 +40,9 @@ get_next_halfword_from_sram_buffer() not tested
 static const char target_not_halted_err_msg[] =
 	"target must be halted to use mx3 NAND flash controller";
 static const char data_block_size_err_msg[] =
-	"minimal granularity is one half-word, %d is incorrect";
+	"minimal granularity is one half-word, %" PRId32 " is incorrect";
 static const char sram_buffer_bounds_err_msg[] =
-	"trying to access out of SRAM buffer bound (addr=0x%x)";
+	"trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
 static const char get_status_register_err_msg[] = "can't get NAND status";
 static uint32_t in_sram_address;
 unsigned char sign_of_sequental_byte_read;
diff --git a/src/jtag/core.c b/src/jtag/core.c
index 14c28fb..564b93f 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -1167,7 +1167,7 @@ static int jtag_validate_ircapture(void)
 					(tap->ir_length + 7) / tap->ir_length,
 					val,
 					(tap->ir_length + 7) / tap->ir_length,
-					tap->ir_capture_value);
+					(unsigned) tap->ir_capture_value);
 
 			retval = ERROR_JTAG_INIT_FAILED;
 			goto done;
diff --git a/src/target/arm11.c b/src/target/arm11.c
index dc46597..588ea3c 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1480,8 +1480,10 @@ int arm11_write_memory(struct target_s *target, uint32_t address, uint32_t size,
 
 		if (address + size * count != r0)
 		{
-			LOG_ERROR("Data transfer failed. Expected end address 0x%08x, got 0x%08x",
-					address + size * count, r0);
+			LOG_ERROR("Data transfer failed. Expected end "
+					"address 0x%08x, got 0x%08x",
+					(unsigned) (address + size * count),
+					(unsigned) r0);
 
 			if (arm11_config_memwrite_burst)
 				LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
diff --git a/src/target/etm.c b/src/target/etm.c
index 5a774f4..34e2ca8 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -1497,29 +1497,29 @@ static int handle_etm_info_command(struct command_context_s *cmd_ctx,
 	command_print(cmd_ctx, "ETM v%d.%d",
 			etm->bcd_vers >> 4, etm->bcd_vers & 0xf);
 	command_print(cmd_ctx, "pairs of address comparators: %i",
-			(etm->config >> 0) & 0x0f);
+			(int) (etm->config >> 0) & 0x0f);
 	command_print(cmd_ctx, "data comparators: %i",
-			(etm->config >> 4) & 0x0f);
+			(int) (etm->config >> 4) & 0x0f);
 	command_print(cmd_ctx, "memory map decoders: %i",
-			(etm->config >> 8) & 0x1f);
+			(int) (etm->config >> 8) & 0x1f);
 	command_print(cmd_ctx, "number of counters: %i",
-			(etm->config >> 13) & 0x07);
+			(int) (etm->config >> 13) & 0x07);
 	command_print(cmd_ctx, "sequencer %spresent",
-			(etm->config & (1 << 16)) ? "" : "not ");
+			(int) (etm->config & (1 << 16)) ? "" : "not ");
 	command_print(cmd_ctx, "number of ext. inputs: %i",
-			(etm->config >> 17) & 0x07);
+			(int) (etm->config >> 17) & 0x07);
 	command_print(cmd_ctx, "number of ext. outputs: %i",
-			(etm->config >> 20) & 0x07);
+			(int) (etm->config >> 20) & 0x07);
 	command_print(cmd_ctx, "FIFO full %spresent",
-			(etm->config & (1 << 23)) ? "" : "not ");
+			(int) (etm->config & (1 << 23)) ? "" : "not ");
 	if (etm->bcd_vers < 0x20)
 		command_print(cmd_ctx, "protocol version: %i",
-				(etm->config >> 28) & 0x07);
+				(int) (etm->config >> 28) & 0x07);
 	else {
 		command_print(cmd_ctx, "trace start/stop %spresent",
 				(etm->config & (1 << 26)) ? "" : "not ");
 		command_print(cmd_ctx, "number of context comparators: %i",
-				(etm->config >> 24) & 0x03);
+				(int) (etm->config >> 24) & 0x03);
 	}
 
 	/* SYS_CONFIG isn't present before ETMv1.2 */

-----------------------------------------------------------------------

Summary of changes:
 src/flash/flash.c    |   11 ++++++-----
 src/flash/lpc2900.c  |   28 +++++++++++++++-------------
 src/flash/mx3_nand.c |    4 ++--
 src/jtag/core.c      |    2 +-
 src/target/arm11.c   |    6 ++++--
 src/target/etm.c     |   20 ++++++++++----------
 6 files changed, 38 insertions(+), 33 deletions(-)


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[Øyvind H. <go...@us...>]

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- Log -----------------------------------------------------------------
commit 2ff66fee7b5b24eee162ee25d22726a04739e2c7
Author: Wookey <wo...@wo...>
Date:   Sat Oct 10 09:08:06 2009 +0200

    Fix reset delays and tinker with ID's

diff --git a/tcl/target/pxa270.cfg b/tcl/target/pxa270.cfg
index 81ecac7..84fc2f7 100644
--- a/tcl/target/pxa270.cfg
+++ b/tcl/target/pxa270.cfg
@@ -12,14 +12,19 @@ if { [info exists ENDIAN] } {
    set  _ENDIAN little
 }
 
-#IDs for pxa270. Choose one. Are there others?#
-#set CPUTAPID 0x79265013
-#set CPUTAPID 0x49265013
+#IDs for pxa270. Are there more?
 if { [info exists CPUTAPID ] } {
    set _CPUTAPID $CPUTAPID
 } else {
-  # force an error till we get a good number
-   set _CPUTAPID 0xffffffff
+  # set useful default
+   set _CPUTAPID 0x49265013
+}
+
+if { [info exists CPUTAPID2 ] } {
+   set _CPUTAPID2 $CPUTAPID2
+} else {
+  # set useful default
+   set _CPUTAPID2 0x79265013
 }
 
 
@@ -28,10 +33,10 @@ if { [info exists CPUTAPID ] } {
 jtag_nsrst_delay 260
 # set the jtag_ntrst_delay to the delay introduced by a reset circuit
 # the rest of the needed delays are built into the openocd program
-jtag_ntrst_delay 0
+jtag_ntrst_delay 250
 
 set _TARGETNAME $_CHIPNAME.cpu
-jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
+jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID -expected-id $_CPUTAPID2
 
 target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa27x
 # maps to PXA internal RAM. If you are using a PXA255

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/pxa270.cfg |   19 ++++++++++++-------
 1 files changed, 12 insertions(+), 7 deletions(-)


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- Log -----------------------------------------------------------------
commit bff92a106938759e1d3375d5b50771f7dd37b5c5
Author: David Brownell <dbr...@us...>
Date:   Fri Oct 9 15:51:16 2009 -0700

    tweak new "translating ..." text
    
    Fix formatting and layout bugs in the new "translating configuration
    files" bit.  Make it a section within the chapter about config files.
    Add a crossreference.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index bf80e12..d41f422 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -66,7 +66,6 @@ Free Documentation License''.
 * Running::                          Running OpenOCD
 * OpenOCD Project Setup::            OpenOCD Project Setup
 * Config File Guidelines::           Config File Guidelines
-* Translating Configuration Files::  Translating Configuration Files
 * Daemon Configuration::             Daemon Configuration
 * Interface - Dongle Configuration:: Interface - Dongle Configuration
 * Reset Configuration::              Reset Configuration
@@ -1186,7 +1185,9 @@ handlers too, if just for developer convenience.
 Because this is so very board-specific, and chip-specific, no examples
 are included here.
 Instead, look at the board config files distributed with OpenOCD.
-If you have a boot loader, its source code may also be useful.
+If you have a boot loader, its source code will help; so will
+configuration files for other JTAG tools
+(@pxref{Translating Configuration Files}).
 @end quotation
 
 Some of this code could probably be shared between different boards.
@@ -1464,17 +1465,18 @@ Examples:
 @item pxa270 - again - CS0 flash - it goes in the board file.
 @end itemize
 
-@node Translating Configuration Files
-@chapter Translating Configuration Files
+@anchor{Translating Configuration Files}
+@section Translating Configuration Files
 @cindex translation
-If you have a configuration file for another hardware debugger(Abatron,
-BDI2000, BDI3000, Lauterbach, Segger, MacRaigor, etc.), translating
+If you have a configuration file for another hardware debugger
+or toolset (Abatron, BDI2000, BDI3000, CCS,
+Lauterbach, Segger, Macraigor, etc.), translating
 it into OpenOCD syntax is often quite straightforward. The most tricky
 part of creating a configuration script is oftentimes the reset init
 sequence where e.g. PLLs, DRAM and the like is set up.
 
 One trick that you can use when translating is to write small
-Tcl proc's to translate the syntax into OpenOCD syntax. This
+Tcl procedures to translate the syntax into OpenOCD syntax. This
 can avoid manual translation errors and make it easier to
 convert other scripts later on.
 
@@ -1482,23 +1484,22 @@ Example of transforming quirky arguments to a simple search and
 replace job:
 
 @example
-# rewrite commands of the form below to arm11 mcr...
-#
 #   Lauterbach syntax(?)
 #
-#	Data.Set c15:0x042f %long 0x40000015
+#       Data.Set c15:0x042f %long 0x40000015
 #
 #   OpenOCD syntax when using procedure below.
 #
-#   setc15 0x01 0x00050078
-#
-#
+#       setc15 0x01 0x00050078
+
 proc setc15 @{regs value@} @{
-	global TARGETNAME 
+    global TARGETNAME
 
-	echo [format "set p15 0x%04x, 0x%08x" $regs $value] 
+    echo [format "set p15 0x%04x, 0x%08x" $regs $value]
 
-	arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] [expr ($regs>>8)&0x7] $value 
+    arm11 mcr $TARGETNAME 15 [expr ($regs>>12)&0x7] \
+        [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
+        [expr ($regs>>8)&0x7] $value
 @}
 @end example
 
@@ -2322,6 +2323,7 @@ powerup and pressing a reset button.
 @end deffn
 
 @section Custom Reset Handling
+@cindex events
 
 OpenOCD has several ways to help support the various reset
 mechanisms provided by chip and board vendors.

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi |   34 ++++++++++++++++++----------------
 1 files changed, 18 insertions(+), 16 deletions(-)


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