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From: David B. <dbr...@us...> - 2009-10-27 07:17:27
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 1020569b9ffa5073df0966b519f05dd492bfa460 (commit)
via 0b476c9f4c0235f52f1a6c522f4835b5ca7e05c5 (commit)
via 4a26390eec5b969c07684ab5d4b7e957011d71bd (commit)
from 4a91b070ffd7890c5a0b6381997787136d797bd5 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 1020569b9ffa5073df0966b519f05dd492bfa460
Author: David Brownell <dbr...@us...>
Date: Mon Oct 26 23:10:40 2009 -0700
ft2232: less noise with _DEBUG_JTAG_IO_
Don't log "Yes, I'm *still* in TAP_IDLE" every seven runtest clocks.
diff --git a/src/jtag/ft2232.c b/src/jtag/ft2232.c
index 839976f..fad07dc 100644
--- a/src/jtag/ft2232.c
+++ b/src/jtag/ft2232.c
@@ -1552,7 +1552,6 @@ static int ft2232_execute_runtest(jtag_command_t *cmd)
/* TMS data bits */
buffer_write(0x0);
- tap_set_state(TAP_IDLE);
i -= (i > 7) ? 7 : i;
/* LOG_DEBUG("added TMS scan (no read)"); */
commit 0b476c9f4c0235f52f1a6c522f4835b5ca7e05c5
Author: David Brownell <dbr...@us...>
Date: Mon Oct 26 23:06:22 2009 -0700
JTAG: "jtag newtap ..." cleanup
Get rid of needless variable, improve and shrink diagnostic.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index 6a6e3ae..5056a5c 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -197,7 +197,6 @@ static int jim_newtap_cmd(Jim_GetOptInfo *goi)
jim_wide w;
int x;
int e;
- int reqbits;
Jim_Nvp *n;
char *cp;
const Jim_Nvp opts[] = {
@@ -252,9 +251,6 @@ static int jim_newtap_cmd(Jim_GetOptInfo *goi)
pTap->ir_capture_mask = 0x03;
pTap->ir_capture_value = 0x01;
- /* clear flags for "required options" them as we find them */
- reqbits = 1;
-
while (goi->argc) {
e = Jim_GetOpt_Nvp(goi, opts, &n);
if (e != JIM_OK) {
@@ -317,7 +313,6 @@ static int jim_newtap_cmd(Jim_GetOptInfo *goi)
pTap->dotted_name,
(int) w);
pTap->ir_length = w;
- reqbits = 0;
break;
case NTAP_OPT_IRMASK:
if (is_bad_irval(pTap->ir_length, w)) {
@@ -355,14 +350,14 @@ static int jim_newtap_cmd(Jim_GetOptInfo *goi)
pTap->enabled = !pTap->disabled_after_reset;
/* Did all the required option bits get cleared? */
- if (0 == reqbits)
+ if (pTap->ir_length != 0)
{
jtag_tap_init(pTap);
return ERROR_OK;
}
Jim_SetResult_sprintf(goi->interp,
- "newtap: %s missing required parameters",
+ "newtap: %s missing IR length",
pTap->dotted_name);
jtag_tap_free(pTap);
return JIM_ERR;
commit 4a26390eec5b969c07684ab5d4b7e957011d71bd
Author: David Brownell <dbr...@us...>
Date: Mon Oct 26 22:59:46 2009 -0700
PXA255: force reset config
These chips need both SRST and TRST when debugging,
and SRST doesn't gate JTAG.
diff --git a/tcl/target/pxa255.cfg b/tcl/target/pxa255.cfg
index 7137621..44efdaa 100644
--- a/tcl/target/pxa255.cfg
+++ b/tcl/target/pxa255.cfg
@@ -31,6 +31,10 @@ target create $_TARGETNAME xscale -endian $_ENDIAN \
jtag_khz 300
$_TARGETNAME configure -event "reset-start" { jtag_khz 300 }
+# both TRST and SRST are *required* for debug
+# DCSR is often accessed with SRST active
+reset_config trst_and_srst separate srst_nogate
+
# reset processing that works with PXA
proc init_reset {mode} {
# assert both resets; equivalent to power-on reset
-----------------------------------------------------------------------
Summary of changes:
src/jtag/ft2232.c | 1 -
src/jtag/tcl.c | 9 ++-------
tcl/target/pxa255.cfg | 4 ++++
3 files changed, 6 insertions(+), 8 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-10-27 06:53:36
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 4a91b070ffd7890c5a0b6381997787136d797bd5 (commit)
from ddade10d4a9309ea252b0a03cde9f757b5c71778 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 4a91b070ffd7890c5a0b6381997787136d797bd5
Author: David Brownell <dbr...@us...>
Date: Mon Oct 26 22:53:18 2009 -0700
omap3530: target reset/init improvements
Now I can issue "reset halt" and have everything act smoothly;
the vector_catch hardware is obviously not kicking in, but the
rest of the reset sequence acts sanely.
- TAP "setup" event enables the DAP, not omap3_dbginit
(resolving a chicken/egg bug I noted a while back)
- Remove stuff from omap3_dbginit which should never be
used in event handlers
- Cope better with slow clocking during reset
Also, stop hard-wiring the target name: use the input params in
the standard way, and set up $_TARGETNAME as an output param.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/tcl/target/omap3530.cfg b/tcl/target/omap3530.cfg
index 8446070..45f3c01 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/omap3530.cfg
@@ -34,28 +34,38 @@ if { [info exists JRC_TAPID ] } {
jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f \
-expected-id $_JRC_TAPID
-jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
-
# GDB target: Cortex-A8, using DAP
-target create omap3.cpu cortex_a8 -chain-position $_CHIPNAME.dap
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_a8 -chain-position $_CHIPNAME.dap
+
+###################
-# FIXME much of this should be in reset event handlers
-proc omap3_dbginit { } {
- poll off
- sleep 100
+# the reset sequence is event-driven
+# and kind of finicky...
+
+# some TCK tycles are required to activate the DEBUG power domain
+jtag configure $_CHIPNAME.jrc -event post-reset "runtest 100"
- jtag tapenable omap3530.dap
- targets
+# have the DAP "always" be active
+jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
+
+proc omap3_dbginit {target} {
# General Cortex A8 debug initialisation
cortex_a8 dbginit
# Enable DBGU signal for OMAP353x
- omap3.cpu mww 0x5401d030 0x00002000
- poll on
+ $target mww 0x5401d030 0x00002000
}
-set PRM_RSTCTRL 0x48307250
-
-omap3.cpu configure -event reset-start "omap3.cpu mww $PRM_RSTCTRL 2"
-omap3.cpu configure -event reset-assert-pre "omap3_dbginit"
+# be absolutely certain the JTAG clock will work with the worst-case
+# 16.8MHz/2 = 8.4MHz core clock, even before a bootloader kicks in.
+# OK to speed up *after* PLL and clock tree setup.
+jtag_rclk 1000
+$_TARGETNAME configure -event "reset-start" { jtag_rclk 1000 }
+# REVISIT This assumes that SRST is unavailable, so we must assert reset
+# ourselves using PRM_RSTCTRL. RST_GS (2) is a warm reset, like ICEpick
+# would issue. RST_DPLL3 (4) is a cold reset.
+set PRM_RSTCTRL 0x48307250
+$_TARGETNAME configure -event reset-assert-pre "$_TARGETNAME mww $PRM_RSTCTRL 2"
+$_TARGETNAME configure -event reset-assert-post "omap3_dbginit $_TARGETNAME"
-----------------------------------------------------------------------
Summary of changes:
tcl/target/omap3530.cfg | 40 +++++++++++++++++++++++++---------------
1 files changed, 25 insertions(+), 15 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-10-27 00:03:14
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via ddade10d4a9309ea252b0a03cde9f757b5c71778 (commit)
from 8f3b28ff4199a64d6f7aff1584a48f18661969ae (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit ddade10d4a9309ea252b0a03cde9f757b5c71778
Author: David Brownell <dbr...@us...>
Date: Mon Oct 26 16:02:45 2009 -0700
ARM ADIv5: "dap info" gets more readable
Make the "dap info" output more comprehensible:
- Don't show CIDs unless they're incorrect (only four bits matter)
- For CoreSight parts, interpret the part type
- Interpret the part number
- Show all five PID bytes together
- Other minor cleanups
Also some whitespace fixes, and shrink a few overlong source lines.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 90423f4..3364132 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1007,11 +1007,20 @@ int ahbap_debugport_init(swjdp_common_t *swjdp)
return ERROR_OK;
}
-
-char * class_description[16] ={
- "Reserved",
- "ROM table","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved",
- "CoreSight component","Reserved","Peripheral Test Block","Reserved","DESS","Generic IP component","Non standard layout"};
+/* CID interpretation -- see ARM IHI 0029B section 3 */
+static const char *class_description[16] ={
+ "Reserved", "ROM table", "Reserved", "Reserved",
+ "Reserved", "Reserved", "Reserved", "Reserved",
+ "Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
+ "Reserved", "DESS", "Generic IP component", "PrimeCell or System component"
+};
+
+static bool
+is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
+{
+ return cid3 == 0xb1 && cid2 == 0x05
+ && ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
+}
int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, int apsel)
{
@@ -1058,15 +1067,13 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i
{
uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
uint16_t entry_offset;
+
/* bit 16 of apid indicates a memory access port */
- if (dbgbase&0x02)
- {
+ if (dbgbase & 0x02)
command_print(cmd_ctx, "\tValid ROM table present");
- }
else
- {
command_print(cmd_ctx, "\tROM table in legacy format");
- }
+
/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
@@ -1074,15 +1081,17 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i
mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
swjdp_transaction_endcheck(swjdp);
- command_print(cmd_ctx, "\tCID3 0x%" PRIx32 ", CID2 0x%" PRIx32 ", CID1 0x%" PRIx32 " CID0, 0x%" PRIx32,cid3,cid2,cid1,cid0);
- if (memtype&0x01)
- {
+ if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
+ command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
+ ", CID2 0x%2.2" PRIx32
+ ", CID1 0x%2.2" PRIx32
+ ", CID0 0x%2.2" PRIx32,
+ cid3, cid2, cid1, cid0);
+ if (memtype & 0x01)
command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
- }
else
- {
- command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus");
- }
+ command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
+ "Dedicated debug bus.");
/* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
entry_offset = 0;
@@ -1092,23 +1101,249 @@ int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, i
command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
if (romentry&0x01)
{
- uint32_t c_cid0,c_cid1,c_cid2,c_cid3,c_pid0,c_pid1,c_pid2,c_pid3,c_pid4,component_start;
- uint32_t component_base = (uint32_t)((dbgbase&0xFFFFF000) + (int)(romentry&0xFFFFF000));
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE0, &c_pid0);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE4, &c_pid1);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFE8, &c_pid2);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFEC, &c_pid3);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFD0, &c_pid4);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF0, &c_cid0);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF4, &c_cid1);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFF8, &c_cid2);
- mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000) | 0xFFC, &c_cid3);
+ uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
+ uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
+ uint32_t component_start, component_base;
+ unsigned part_num;
+ char *type, *full;
+
+ component_base = (uint32_t)((dbgbase & 0xFFFFF000)
+ + (int)(romentry & 0xFFFFF000));
+ mem_ap_read_atomic_u32(swjdp,
+ (component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
+ mem_ap_read_atomic_u32(swjdp,
+ (component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
+ mem_ap_read_atomic_u32(swjdp,
+ (component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
+ mem_ap_read_atomic_u32(swjdp,
+ (component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
+ mem_ap_read_atomic_u32(swjdp,
+ (component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
+ mem_ap_read_atomic_u32(swjdp,
+ (component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
+ mem_ap_read_atomic_u32(swjdp,
+ (component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
+ mem_ap_read_atomic_u32(swjdp,
+ (component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
+ mem_ap_read_atomic_u32(swjdp,
+ (component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
component_start = component_base - 0x1000*(c_pid4 >> 4);
- command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", pid4 0x%" PRIx32 ", start address 0x%" PRIx32 "",component_base,c_pid4,component_start);
- command_print(cmd_ctx, "\t\tComponent cid1 0x%" PRIx32 ", class is %s",c_cid1,class_description[(c_cid1 >> 4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */
- command_print(cmd_ctx, "\t\tCID3 0x%" PRIx32 ", CID2 0x%" PRIx32 ", CID1 0x%" PRIx32 ", CID0, 0x%" PRIx32 "",c_cid3,c_cid2,c_cid1,c_cid0);
- command_print(cmd_ctx, "\t\tPID3 0x%" PRIx32 ", PID2 0x%" PRIx32 ", PID1 0x%" PRIx32 ", PID0, 0x%" PRIx32 "",c_pid3,c_pid2,c_pid1,c_pid0);
- /* For CoreSight components, (c_cid1 >> 4)&0xF == 9 , we also read 0xFC8 DevId and 0xFCC DevType */
+
+ command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
+ ", start address 0x%" PRIx32,
+ component_base, component_start);
+ command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
+ (int) (c_cid1 >> 4) & 0xf,
+ /* See ARM IHI 0029B Table 3-3 */
+ class_description[(c_cid1 >> 4) & 0xf]);
+
+ /* CoreSight component? */
+ if (((c_cid1 >> 4) & 0x0f) == 9) {
+ uint32_t devtype;
+ unsigned minor;
+ char *major = "Reserved", *subtype = "Reserved";
+
+ mem_ap_read_atomic_u32(swjdp,
+ (component_base & 0xfffff000) | 0xfcc,
+ &devtype);
+ minor = (devtype >> 4) & 0x0f;
+ switch (devtype & 0x0f) {
+ case 0:
+ major = "Miscellaneous";
+ switch (minor) {
+ case 0:
+ subtype = "other";
+ break;
+ case 4:
+ subtype = "Validation component";
+ break;
+ }
+ break;
+ case 1:
+ major = "Trace Sink";
+ switch (minor) {
+ case 0:
+ subtype = "other";
+ break;
+ case 1:
+ subtype = "Port";
+ break;
+ case 2:
+ subtype = "Buffer";
+ break;
+ }
+ break;
+ case 2:
+ major = "Trace Link";
+ switch (minor) {
+ case 0:
+ subtype = "other";
+ break;
+ case 1:
+ subtype = "Funnel, router";
+ break;
+ case 2:
+ subtype = "Filter";
+ break;
+ case 3:
+ subtype = "FIFO, buffer";
+ break;
+ }
+ break;
+ case 3:
+ major = "Trace Source";
+ switch (minor) {
+ case 0:
+ subtype = "other";
+ break;
+ case 1:
+ subtype = "Processor";
+ break;
+ case 2:
+ subtype = "DSP";
+ break;
+ case 3:
+ subtype = "Engine/Coprocessor";
+ break;
+ case 4:
+ subtype = "Bus";
+ break;
+ }
+ break;
+ case 4:
+ major = "Debug Control";
+ switch (minor) {
+ case 0:
+ subtype = "other";
+ break;
+ case 1:
+ subtype = "Trigger Matrix";
+ break;
+ case 2:
+ subtype = "Debug Auth";
+ break;
+ }
+ break;
+ case 5:
+ major = "Debug Logic";
+ switch (minor) {
+ case 0:
+ subtype = "other";
+ break;
+ case 1:
+ subtype = "Processor";
+ break;
+ case 2:
+ subtype = "DSP";
+ break;
+ case 3:
+ subtype = "Engine/Coprocessor";
+ break;
+ }
+ break;
+ }
+ command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
+ (unsigned) (devtype & 0xff),
+ major, subtype);
+ /* REVISIT also show 0xfc8 DevId */
+ }
+
+ if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
+ command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
+ ", CID2 0x%2.2" PRIx32
+ ", CID1 0x%2.2" PRIx32
+ ", CID0 0x%2.2" PRIx32,
+ c_cid3, c_cid2, c_cid1, c_cid0);
+ command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
+ "%2.2x %2.2x %2.2x %2.2x %2.2x",
+ (int) c_pid4,
+ (int) c_pid3, (int) c_pid2,
+ (int) c_pid1, (int) c_pid0);
+
+ /* Part number interpretations are from Cortex
+ * core specs, the CoreSight components TRM
+ * (ARM DDI 0314H), and ETM specs; also from
+ * chip observation (e.g. TI SDTI).
+ */
+ part_num = c_pid0 & 0xff;
+ part_num |= (c_pid1 & 0x0f) << 8;
+ switch (part_num) {
+ case 0x000:
+ type = "Cortex-M3 NVIC";
+ full = "(Interrupt Controller)";
+ break;
+ case 0x001:
+ type = "Cortex-M3 ITM";
+ full = "(Instrumentation Trace Module)";
+ break;
+ case 0x002:
+ type = "Cortex-M3 DWT";
+ full = "(Data Watchpoint and Trace)";
+ break;
+ case 0x003:
+ type = "Cortex-M3 FBP";
+ full = "(Flash Patch and Breakpoint)";
+ break;
+ case 0x00d:
+ type = "CoreSight ETM11";
+ full = "(Embedded Trace)";
+ break;
+ // case 0x113: what?
+ case 0x120: /* from OMAP3 memmap */
+ type = "TI SDTI";
+ full = "(System Debug Trace Interface)";
+ break;
+ case 0x343: /* from OMAP3 memmap */
+ type = "TI DAPCTL";
+ full = "";
+ break;
+ case 0x4e0:
+ type = "Cortex-M3 ETM";
+ full = "(Embedded Trace)";
+ break;
+ case 0x906:
+ type = "Coresight CTI";
+ full = "(Cross Trigger)";
+ break;
+ case 0x907:
+ type = "Coresight ETB";
+ full = "(Trace Buffer)";
+ break;
+ case 0x908:
+ type = "Coresight CSTF";
+ full = "(Trace Funnel)";
+ break;
+ case 0x910:
+ type = "CoreSight ETM9";
+ full = "(Embedded Trace)";
+ break;
+ case 0x912:
+ type = "Coresight TPIU";
+ full = "(Trace Port Interface Unit)";
+ break;
+ case 0x921:
+ type = "Cortex-A8 ETM";
+ full = "(Embedded Trace)";
+ break;
+ case 0x922:
+ type = "Cortex-A8 CTI";
+ full = "(Cross Trigger)";
+ break;
+ case 0x923:
+ type = "Cortex-M3 TPIU";
+ full = "(Trace Port Interface Unit)";
+ break;
+ case 0xc08:
+ type = "Cortex-A8 Debug";
+ full = "(Debug Unit)";
+ break;
+ default:
+ type = "-*- unrecognized -*-";
+ full = "";
+ break;
+ }
+ command_print(cmd_ctx, "\t\tPart is %s %s",
+ type, full);
}
else
{
-----------------------------------------------------------------------
Summary of changes:
src/target/arm_adi_v5.c | 301 +++++++++++++++++++++++++++++++++++++++++-----
1 files changed, 268 insertions(+), 33 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Spencer O. <nt...@us...> - 2009-10-26 23:43:58
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 8f3b28ff4199a64d6f7aff1584a48f18661969ae (commit)
from d87ee640c7a8e77a34d2d72185be157a97b39061 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 8f3b28ff4199a64d6f7aff1584a48f18661969ae
Author: Spencer Oliver <nt...@us...>
Date: Mon Oct 26 22:39:24 2009 +0000
Fix incorrect line endings
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/tcl/test/selftest.cfg b/tcl/test/selftest.cfg
old mode 100644
new mode 100755
index d1a00ae..912d1c0
--- a/tcl/test/selftest.cfg
+++ b/tcl/test/selftest.cfg
@@ -1,17 +1,17 @@
-
-add_help_text selftest "run selftest using working ram <tmpfile> <address> <size>"
-
-proc selftest {tmpfile address size} {
-
- for {set i 0} {$i < $size } {set i [expr $i+4]} {
- mww [expr $address+$i] $i
- }
-
- for {set i 0} {$i < 10 } {set i [expr $i+1]} {
- puts "Test iteration $i"
- dump_image $tmpfile $address $size
- verify_image $tmpfile $address bin
- load_image $tmpfile $address bin
- }
-
-}
\ No newline at end of file
+
+add_help_text selftest "run selftest using working ram <tmpfile> <address> <size>"
+
+proc selftest {tmpfile address size} {
+
+ for {set i 0} {$i < $size } {set i [expr $i+4]} {
+ mww [expr $address+$i] $i
+ }
+
+ for {set i 0} {$i < 10 } {set i [expr $i+1]} {
+ puts "Test iteration $i"
+ dump_image $tmpfile $address $size
+ verify_image $tmpfile $address bin
+ load_image $tmpfile $address bin
+ }
+
+}
diff --git a/testing/examples/AT91R40008Test/test_ram.hex b/testing/examples/AT91R40008Test/test_ram.hex
index f3e72d9..28a1f40 100644
--- a/testing/examples/AT91R40008Test/test_ram.hex
+++ b/testing/examples/AT91R40008Test/test_ram.hex
@@ -1,23 +1,23 @@
-:1000000018F09FE518F09FE518F09FE518F09FE5C0
-:1000100018F09FE518F09FE518F09FE518F09FE5B0
-:1000200040000000B0000000B4000000B800000074
-:10003000BC00000000000000C0000000C400000080
-:10004000DBF021E37CD09FE5D7F021E378D09FE57A
-:10005000D1F021E374D09FE5D2F021E370D09FE589
-:10006000D3F021E36CD09FE56C109FE56C209FE5F9
-:100070000030A0E3020051E104308114FCFFFF1ABC
-:1000800000000FE1C000C0E300F029E10000A0E3A0
-:100090000010A0E348209FE50FE0A0E112FF2FE150
-:1000A0000000A0E10000A0E10000A0E1FBFFFFEAEA
-:1000B000FEFFFFEAFEFFFFEAFEFFFFEAFEFFFFEAA8
-:1000C000FEFFFFEAFEFFFFEA000600000005000059
-:1000D0000003000000040000000A00004C010000C2
-:1000E0004C010000E80000000CD04DE20130A0E31C
-:1000F00000308DE50230A0E304308DE50030A0E350
-:1001000008308DE538309FE5002093E500309DE50F
-:10011000023083E000308DE500309DE5013083E260
-:1001200000308DE504309DE5013083E204308DE53B
-:1001300000209DE504309DE5033082E008308DE528
-:0C014000F4FFFFEA480100000700000087
-:0400000300000040B9
-:00000001FF
+:1000000018F09FE518F09FE518F09FE518F09FE5C0
+:1000100018F09FE518F09FE518F09FE518F09FE5B0
+:1000200040000000B0000000B4000000B800000074
+:10003000BC00000000000000C0000000C400000080
+:10004000DBF021E37CD09FE5D7F021E378D09FE57A
+:10005000D1F021E374D09FE5D2F021E370D09FE589
+:10006000D3F021E36CD09FE56C109FE56C209FE5F9
+:100070000030A0E3020051E104308114FCFFFF1ABC
+:1000800000000FE1C000C0E300F029E10000A0E3A0
+:100090000010A0E348209FE50FE0A0E112FF2FE150
+:1000A0000000A0E10000A0E10000A0E1FBFFFFEAEA
+:1000B000FEFFFFEAFEFFFFEAFEFFFFEAFEFFFFEAA8
+:1000C000FEFFFFEAFEFFFFEA000600000005000059
+:1000D0000003000000040000000A00004C010000C2
+:1000E0004C010000E80000000CD04DE20130A0E31C
+:1000F00000308DE50230A0E304308DE50030A0E350
+:1001000008308DE538309FE5002093E500309DE50F
+:10011000023083E000308DE500309DE5013083E260
+:1001200000308DE504309DE5013083E204308DE53B
+:1001300000209DE504309DE5033082E008308DE528
+:0C014000F4FFFFEA480100000700000087
+:0400000300000040B9
+:00000001FF
diff --git a/testing/examples/AT91R40008Test/test_ram.map b/testing/examples/AT91R40008Test/test_ram.map
index 5377a5d..1df9053 100644
--- a/testing/examples/AT91R40008Test/test_ram.map
+++ b/testing/examples/AT91R40008Test/test_ram.map
@@ -1,170 +1,170 @@
-
-Memory Configuration
-
-Name Origin Length Attributes
-ram 0x00000000 0x00040000
-*default* 0x00000000 0xffffffff
-
-Linker script and memory map
-
-LOAD ./src/crt.o
-LOAD ./src/main.o
-START GROUP
-LOAD d:/compiler/yagarto/bin/../lib/gcc/arm-elf/4.2.2\libgcc.a
-LOAD d:/compiler/yagarto/bin/../lib/gcc/arm-elf/4.2.2/../../../../arm-elf/lib\libc.a
-END GROUP
- 0x00000100 FIQ_STACK_SIZE = 0x100
- 0x00000100 IRQ_STACK_SIZE = 0x100
- 0x00000100 ABT_STACK_SIZE = 0x100
- 0x00000100 UND_STACK_SIZE = 0x100
- 0x00000400 SVC_STACK_SIZE = 0x400
-
-.text 0x00000000 0x14c
- *(.vectors)
- .vectors 0x00000000 0x40 ./src/crt.o
- 0x00000040 . = ALIGN (0x4)
- *(.init)
- .init 0x00000040 0xa8 ./src/crt.o
- 0x000000c4 FIQHandler
- 0x000000b8 PAbortHandler
- 0x000000a0 ExitFunction
- 0x00000040 ResetHandler
- 0x000000bc DAbortHandler
- 0x000000c0 IRQHandler
- 0x000000b0 UndefHandler
- 0x000000e8 . = ALIGN (0x4)
- *(.text)
- .text 0x000000e8 0x0 ./src/crt.o
- .text 0x000000e8 0x60 ./src/main.o
- 0x000000e8 main
- 0x00000148 . = ALIGN (0x4)
- *(.rodata)
- .rodata 0x00000148 0x4 ./src/main.o
- 0x0000014c . = ALIGN (0x4)
- *(.rodata*)
- 0x0000014c . = ALIGN (0x4)
- *(.glue_7t)
- .glue_7t 0x0000014c 0x0 ./src/crt.o
- .glue_7t 0x0000014c 0x0 ./src/main.o
- 0x0000014c . = ALIGN (0x4)
- *(.glue_7)
- .glue_7 0x0000014c 0x0 ./src/crt.o
- .glue_7 0x0000014c 0x0 ./src/main.o
- 0x0000014c . = ALIGN (0x4)
- 0x0000014c etext = .
-
-.vfp11_veneer 0x00000000 0x0
- .vfp11_veneer 0x00000000 0x0 ./src/crt.o
- .vfp11_veneer 0x00000000 0x0 ./src/main.o
-
-.data 0x0000014c 0x0
- 0x0000014c PROVIDE (__data_start, .)
- *(.data)
- .data 0x0000014c 0x0 ./src/crt.o
- .data 0x0000014c 0x0 ./src/main.o
- 0x0000014c . = ALIGN (0x4)
- 0x0000014c edata = .
- 0x0000014c _edata = .
- 0x0000014c PROVIDE (__data_end, .)
-
-.bss 0x0000014c 0x8b4
- 0x0000014c PROVIDE (__bss_start, .)
- *(.bss)
- .bss 0x0000014c 0x0 ./src/crt.o
- .bss 0x0000014c 0x0 ./src/main.o
- *(COMMON)
- 0x0000014c . = ALIGN (0x4)
- 0x0000014c PROVIDE (__bss_end, .)
- 0x00000200 . = ALIGN (0x100)
- *fill* 0x0000014c 0xb4 00
- 0x00000200 PROVIDE (__stack_start, .)
- 0x00000200 PROVIDE (__stack_fiq_start, .)
- 0x00000300 . = (. + FIQ_STACK_SIZE)
- *fill* 0x00000200 0x100 00
- 0x00000300 . = ALIGN (0x4)
- 0x00000300 PROVIDE (__stack_fiq_end, .)
- 0x00000300 PROVIDE (__stack_irq_start, .)
- 0x00000400 . = (. + IRQ_STACK_SIZE)
- *fill* 0x00000300 0x100 00
- 0x00000400 . = ALIGN (0x4)
- 0x00000400 PROVIDE (__stack_irq_end, .)
- 0x00000400 PROVIDE (__stack_abt_start, .)
- 0x00000500 . = (. + ABT_STACK_SIZE)
- *fill* 0x00000400 0x100 00
- 0x00000500 . = ALIGN (0x4)
- 0x00000500 PROVIDE (__stack_abt_end, .)
- 0x00000500 PROVIDE (__stack_und_start, .)
- 0x00000600 . = (. + UND_STACK_SIZE)
- *fill* 0x00000500 0x100 00
- 0x00000600 . = ALIGN (0x4)
- 0x00000600 PROVIDE (__stack_und_end, .)
- 0x00000600 PROVIDE (__stack_svc_start, .)
- 0x00000a00 . = (. + SVC_STACK_SIZE)
- *fill* 0x00000600 0x400 00
- 0x00000a00 . = ALIGN (0x4)
- 0x00000a00 PROVIDE (__stack_svc_end, .)
- 0x00000a00 PROVIDE (__stack_end, .)
- 0x00000a00 PROVIDE (__heap_start, .)
-OUTPUT(test_ram.elf elf32-littlearm)
-
-.ARM.attributes
- 0x00000000 0x10
- .ARM.attributes
- 0x00000000 0x10 ./src/crt.o
- .ARM.attributes
- 0x00000010 0x10 ./src/main.o
-
-.debug_line 0x00000000 0xc8
- .debug_line 0x00000000 0x71 ./src/crt.o
- .debug_line 0x00000071 0x57 ./src/main.o
-
-.debug_info 0x00000000 0x208
- .debug_info 0x00000000 0x77 ./src/crt.o
- .debug_info 0x00000077 0x191 ./src/main.o
-
-.debug_abbrev 0x00000000 0x76
- .debug_abbrev 0x00000000 0x12 ./src/crt.o
- .debug_abbrev 0x00000012 0x64 ./src/main.o
-
-.debug_aranges 0x00000000 0x48
- .debug_aranges
- 0x00000000 0x28 ./src/crt.o
- .debug_aranges
- 0x00000028 0x20 ./src/main.o
-
-.debug_ranges 0x00000000 0x20
- .debug_ranges 0x00000000 0x20 ./src/crt.o
-
-.debug_frame 0x00000000 0x24
- .debug_frame 0x00000000 0x24 ./src/main.o
-
-.debug_loc 0x00000000 0x1f
- .debug_loc 0x00000000 0x1f ./src/main.o
-
-.debug_pubnames
- 0x00000000 0x1b
- .debug_pubnames
- 0x00000000 0x1b ./src/main.o
-
-.comment 0x00000000 0x12
- .comment 0x00000000 0x12 ./src/main.o
-
-Cross Reference Table
-
-Symbol File
-DAbortHandler ./src/crt.o
-ExitFunction ./src/crt.o
-FIQHandler ./src/crt.o
-IRQHandler ./src/crt.o
-PAbortHandler ./src/crt.o
-ResetHandler ./src/crt.o
-UndefHandler ./src/crt.o
-__bss_end ./src/crt.o
-__bss_start ./src/crt.o
-__stack_abt_end ./src/crt.o
-__stack_fiq_end ./src/crt.o
-__stack_irq_end ./src/crt.o
-__stack_svc_end ./src/crt.o
-__stack_und_end ./src/crt.o
-main ./src/main.o
- ./src/crt.o
+
+Memory Configuration
+
+Name Origin Length Attributes
+ram 0x00000000 0x00040000
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+LOAD ./src/crt.o
+LOAD ./src/main.o
+START GROUP
+LOAD d:/compiler/yagarto/bin/../lib/gcc/arm-elf/4.2.2\libgcc.a
+LOAD d:/compiler/yagarto/bin/../lib/gcc/arm-elf/4.2.2/../../../../arm-elf/lib\libc.a
+END GROUP
+ 0x00000100 FIQ_STACK_SIZE = 0x100
+ 0x00000100 IRQ_STACK_SIZE = 0x100
+ 0x00000100 ABT_STACK_SIZE = 0x100
+ 0x00000100 UND_STACK_SIZE = 0x100
+ 0x00000400 SVC_STACK_SIZE = 0x400
+
+.text 0x00000000 0x14c
+ *(.vectors)
+ .vectors 0x00000000 0x40 ./src/crt.o
+ 0x00000040 . = ALIGN (0x4)
+ *(.init)
+ .init 0x00000040 0xa8 ./src/crt.o
+ 0x000000c4 FIQHandler
+ 0x000000b8 PAbortHandler
+ 0x000000a0 ExitFunction
+ 0x00000040 ResetHandler
+ 0x000000bc DAbortHandler
+ 0x000000c0 IRQHandler
+ 0x000000b0 UndefHandler
+ 0x000000e8 . = ALIGN (0x4)
+ *(.text)
+ .text 0x000000e8 0x0 ./src/crt.o
+ .text 0x000000e8 0x60 ./src/main.o
+ 0x000000e8 main
+ 0x00000148 . = ALIGN (0x4)
+ *(.rodata)
+ .rodata 0x00000148 0x4 ./src/main.o
+ 0x0000014c . = ALIGN (0x4)
+ *(.rodata*)
+ 0x0000014c . = ALIGN (0x4)
+ *(.glue_7t)
+ .glue_7t 0x0000014c 0x0 ./src/crt.o
+ .glue_7t 0x0000014c 0x0 ./src/main.o
+ 0x0000014c . = ALIGN (0x4)
+ *(.glue_7)
+ .glue_7 0x0000014c 0x0 ./src/crt.o
+ .glue_7 0x0000014c 0x0 ./src/main.o
+ 0x0000014c . = ALIGN (0x4)
+ 0x0000014c etext = .
+
+.vfp11_veneer 0x00000000 0x0
+ .vfp11_veneer 0x00000000 0x0 ./src/crt.o
+ .vfp11_veneer 0x00000000 0x0 ./src/main.o
+
+.data 0x0000014c 0x0
+ 0x0000014c PROVIDE (__data_start, .)
+ *(.data)
+ .data 0x0000014c 0x0 ./src/crt.o
+ .data 0x0000014c 0x0 ./src/main.o
+ 0x0000014c . = ALIGN (0x4)
+ 0x0000014c edata = .
+ 0x0000014c _edata = .
+ 0x0000014c PROVIDE (__data_end, .)
+
+.bss 0x0000014c 0x8b4
+ 0x0000014c PROVIDE (__bss_start, .)
+ *(.bss)
+ .bss 0x0000014c 0x0 ./src/crt.o
+ .bss 0x0000014c 0x0 ./src/main.o
+ *(COMMON)
+ 0x0000014c . = ALIGN (0x4)
+ 0x0000014c PROVIDE (__bss_end, .)
+ 0x00000200 . = ALIGN (0x100)
+ *fill* 0x0000014c 0xb4 00
+ 0x00000200 PROVIDE (__stack_start, .)
+ 0x00000200 PROVIDE (__stack_fiq_start, .)
+ 0x00000300 . = (. + FIQ_STACK_SIZE)
+ *fill* 0x00000200 0x100 00
+ 0x00000300 . = ALIGN (0x4)
+ 0x00000300 PROVIDE (__stack_fiq_end, .)
+ 0x00000300 PROVIDE (__stack_irq_start, .)
+ 0x00000400 . = (. + IRQ_STACK_SIZE)
+ *fill* 0x00000300 0x100 00
+ 0x00000400 . = ALIGN (0x4)
+ 0x00000400 PROVIDE (__stack_irq_end, .)
+ 0x00000400 PROVIDE (__stack_abt_start, .)
+ 0x00000500 . = (. + ABT_STACK_SIZE)
+ *fill* 0x00000400 0x100 00
+ 0x00000500 . = ALIGN (0x4)
+ 0x00000500 PROVIDE (__stack_abt_end, .)
+ 0x00000500 PROVIDE (__stack_und_start, .)
+ 0x00000600 . = (. + UND_STACK_SIZE)
+ *fill* 0x00000500 0x100 00
+ 0x00000600 . = ALIGN (0x4)
+ 0x00000600 PROVIDE (__stack_und_end, .)
+ 0x00000600 PROVIDE (__stack_svc_start, .)
+ 0x00000a00 . = (. + SVC_STACK_SIZE)
+ *fill* 0x00000600 0x400 00
+ 0x00000a00 . = ALIGN (0x4)
+ 0x00000a00 PROVIDE (__stack_svc_end, .)
+ 0x00000a00 PROVIDE (__stack_end, .)
+ 0x00000a00 PROVIDE (__heap_start, .)
+OUTPUT(test_ram.elf elf32-littlearm)
+
+.ARM.attributes
+ 0x00000000 0x10
+ .ARM.attributes
+ 0x00000000 0x10 ./src/crt.o
+ .ARM.attributes
+ 0x00000010 0x10 ./src/main.o
+
+.debug_line 0x00000000 0xc8
+ .debug_line 0x00000000 0x71 ./src/crt.o
+ .debug_line 0x00000071 0x57 ./src/main.o
+
+.debug_info 0x00000000 0x208
+ .debug_info 0x00000000 0x77 ./src/crt.o
+ .debug_info 0x00000077 0x191 ./src/main.o
+
+.debug_abbrev 0x00000000 0x76
+ .debug_abbrev 0x00000000 0x12 ./src/crt.o
+ .debug_abbrev 0x00000012 0x64 ./src/main.o
+
+.debug_aranges 0x00000000 0x48
+ .debug_aranges
+ 0x00000000 0x28 ./src/crt.o
+ .debug_aranges
+ 0x00000028 0x20 ./src/main.o
+
+.debug_ranges 0x00000000 0x20
+ .debug_ranges 0x00000000 0x20 ./src/crt.o
+
+.debug_frame 0x00000000 0x24
+ .debug_frame 0x00000000 0x24 ./src/main.o
+
+.debug_loc 0x00000000 0x1f
+ .debug_loc 0x00000000 0x1f ./src/main.o
+
+.debug_pubnames
+ 0x00000000 0x1b
+ .debug_pubnames
+ 0x00000000 0x1b ./src/main.o
+
+.comment 0x00000000 0x12
+ .comment 0x00000000 0x12 ./src/main.o
+
+Cross Reference Table
+
+Symbol File
+DAbortHandler ./src/crt.o
+ExitFunction ./src/crt.o
+FIQHandler ./src/crt.o
+IRQHandler ./src/crt.o
+PAbortHandler ./src/crt.o
+ResetHandler ./src/crt.o
+UndefHandler ./src/crt.o
+__bss_end ./src/crt.o
+__bss_start ./src/crt.o
+__stack_abt_end ./src/crt.o
+__stack_fiq_end ./src/crt.o
+__stack_irq_end ./src/crt.o
+__stack_svc_end ./src/crt.o
+__stack_und_end ./src/crt.o
+main ./src/main.o
+ ./src/crt.o
diff --git a/testing/examples/LPC2148Test/test_ram.hex b/testing/examples/LPC2148Test/test_ram.hex
index 109ebc5..6caf035 100644
--- a/testing/examples/LPC2148Test/test_ram.hex
+++ b/testing/examples/LPC2148Test/test_ram.hex
@@ -1,26 +1,26 @@
-:020000044000BA
-:1000000018F09FE518F09FE518F09FE518F09FE5C0
-:1000100018F09FE5606FA0B818F09FE518F09FE515
-:1000200040000040D0000040D4000040D800004014
-:10003000DC00004000000000E0000040E400004060
-:100040000000A0E10000A0E10000A0E10000A0E1AC
-:100050000000A0E10000A0E10000A0E10000A0E19C
-:10006000DBF021E37CD09FE5D7F021E378D09FE55A
-:10007000D1F021E374D09FE5D2F021E370D09FE569
-:10008000D3F021E36CD09FE56C109FE56C209FE5D9
-:100090000030A0E3020051E104308114FCFFFF1A9C
-:1000A00000000FE1C000C0E300F029E10000A0E380
-:1000B0000010A0E348209FE50FE0A0E112FF2FE130
-:1000C0000000A0E10000A0E10000A0E1FBFFFFEACA
-:1000D000FEFFFFEAFEFFFFEAFEFFFFEAFEFFFFEA88
-:1000E000FEFFFFEAFEFFFFEA0006004000050040B9
-:1000F0000003004000040040000A00406C01004082
-:100100006C010040080100400CD04DE20130A0E33A
-:1001100000308DE50230A0E304308DE50030A0E32F
-:1001200008308DE538309FE5002093E500309DE5EF
-:10013000023083E000308DE500309DE5013083E240
-:1001400000308DE504309DE5013083E204308DE51B
-:1001500000209DE504309DE5033082E008308DE508
-:0C016000F4FFFFEA680100400700000007
-:040000054000004077
-:00000001FF
+:020000044000BA
+:1000000018F09FE518F09FE518F09FE518F09FE5C0
+:1000100018F09FE5606FA0B818F09FE518F09FE515
+:1000200040000040D0000040D4000040D800004014
+:10003000DC00004000000000E0000040E400004060
+:100040000000A0E10000A0E10000A0E10000A0E1AC
+:100050000000A0E10000A0E10000A0E10000A0E19C
+:10006000DBF021E37CD09FE5D7F021E378D09FE55A
+:10007000D1F021E374D09FE5D2F021E370D09FE569
+:10008000D3F021E36CD09FE56C109FE56C209FE5D9
+:100090000030A0E3020051E104308114FCFFFF1A9C
+:1000A00000000FE1C000C0E300F029E10000A0E380
+:1000B0000010A0E348209FE50FE0A0E112FF2FE130
+:1000C0000000A0E10000A0E10000A0E1FBFFFFEACA
+:1000D000FEFFFFEAFEFFFFEAFEFFFFEAFEFFFFEA88
+:1000E000FEFFFFEAFEFFFFEA0006004000050040B9
+:1000F0000003004000040040000A00406C01004082
+:100100006C010040080100400CD04DE20130A0E33A
+:1001100000308DE50230A0E304308DE50030A0E32F
+:1001200008308DE538309FE5002093E500309DE5EF
+:10013000023083E000308DE500309DE5013083E240
+:1001400000308DE504309DE5013083E204308DE51B
+:1001500000209DE504309DE5033082E008308DE508
+:0C016000F4FFFFEA680100400700000007
+:040000054000004077
+:00000001FF
diff --git a/testing/examples/LPC2148Test/test_ram.map b/testing/examples/LPC2148Test/test_ram.map
index 20baad2..73d4e72 100644
--- a/testing/examples/LPC2148Test/test_ram.map
+++ b/testing/examples/LPC2148Test/test_ram.map
@@ -1,170 +1,170 @@
-
-Memory Configuration
-
-Name Origin Length Attributes
-ram 0x40000000 0x00008000
-*default* 0x00000000 0xffffffff
-
-Linker script and memory map
-
-LOAD ./src/crt.o
-LOAD ./src/main.o
-START GROUP
-LOAD d:/compiler/yagarto/bin/../lib/gcc/arm-elf/4.2.2\libgcc.a
-LOAD d:/compiler/yagarto/bin/../lib/gcc/arm-elf/4.2.2/../../../../arm-elf/lib\libc.a
-END GROUP
- 0x00000100 FIQ_STACK_SIZE = 0x100
- 0x00000100 IRQ_STACK_SIZE = 0x100
- 0x00000100 ABT_STACK_SIZE = 0x100
- 0x00000100 UND_STACK_SIZE = 0x100
- 0x00000400 SVC_STACK_SIZE = 0x400
-
-.text 0x40000000 0x16c
- *(.vectors)
- .vectors 0x40000000 0x40 ./src/crt.o
- 0x40000040 . = ALIGN (0x4)
- *(.init)
- .init 0x40000040 0xc8 ./src/crt.o
- 0x400000e4 FIQHandler
- 0x400000d8 PAbortHandler
- 0x400000c0 ExitFunction
- 0x40000040 ResetHandler
- 0x400000dc DAbortHandler
- 0x400000e0 IRQHandler
- 0x400000d0 UndefHandler
- 0x40000108 . = ALIGN (0x4)
- *(.text)
- .text 0x40000108 0x0 ./src/crt.o
- .text 0x40000108 0x60 ./src/main.o
- 0x40000108 main
- 0x40000168 . = ALIGN (0x4)
- *(.rodata)
- .rodata 0x40000168 0x4 ./src/main.o
- 0x4000016c . = ALIGN (0x4)
- *(.rodata*)
- 0x4000016c . = ALIGN (0x4)
- *(.glue_7t)
- .glue_7t 0x4000016c 0x0 ./src/crt.o
- .glue_7t 0x4000016c 0x0 ./src/main.o
- 0x4000016c . = ALIGN (0x4)
- *(.glue_7)
- .glue_7 0x4000016c 0x0 ./src/crt.o
- .glue_7 0x4000016c 0x0 ./src/main.o
- 0x4000016c . = ALIGN (0x4)
- 0x4000016c etext = .
-
-.vfp11_veneer 0x00000000 0x0
- .vfp11_veneer 0x00000000 0x0 ./src/crt.o
- .vfp11_veneer 0x00000000 0x0 ./src/main.o
-
-.data 0x4000016c 0x0
- 0x4000016c PROVIDE (__data_start, .)
- *(.data)
- .data 0x4000016c 0x0 ./src/crt.o
- .data 0x4000016c 0x0 ./src/main.o
- 0x4000016c . = ALIGN (0x4)
- 0x4000016c edata = .
- 0x4000016c _edata = .
- 0x4000016c PROVIDE (__data_end, .)
-
-.bss 0x4000016c 0x894
- 0x4000016c PROVIDE (__bss_start, .)
- *(.bss)
- .bss 0x4000016c 0x0 ./src/crt.o
- .bss 0x4000016c 0x0 ./src/main.o
- *(COMMON)
- 0x4000016c . = ALIGN (0x4)
- 0x4000016c PROVIDE (__bss_end, .)
- 0x40000200 . = ALIGN (0x100)
- *fill* 0x4000016c 0x94 00
- 0x40000200 PROVIDE (__stack_start, .)
- 0x40000200 PROVIDE (__stack_fiq_start, .)
- 0x40000300 . = (. + FIQ_STACK_SIZE)
- *fill* 0x40000200 0x100 00
- 0x40000300 . = ALIGN (0x4)
- 0x40000300 PROVIDE (__stack_fiq_end, .)
- 0x40000300 PROVIDE (__stack_irq_start, .)
- 0x40000400 . = (. + IRQ_STACK_SIZE)
- *fill* 0x40000300 0x100 00
- 0x40000400 . = ALIGN (0x4)
- 0x40000400 PROVIDE (__stack_irq_end, .)
- 0x40000400 PROVIDE (__stack_abt_start, .)
- 0x40000500 . = (. + ABT_STACK_SIZE)
- *fill* 0x40000400 0x100 00
- 0x40000500 . = ALIGN (0x4)
- 0x40000500 PROVIDE (__stack_abt_end, .)
- 0x40000500 PROVIDE (__stack_und_start, .)
- 0x40000600 . = (. + UND_STACK_SIZE)
- *fill* 0x40000500 0x100 00
- 0x40000600 . = ALIGN (0x4)
- 0x40000600 PROVIDE (__stack_und_end, .)
- 0x40000600 PROVIDE (__stack_svc_start, .)
- 0x40000a00 . = (. + SVC_STACK_SIZE)
- *fill* 0x40000600 0x400 00
- 0x40000a00 . = ALIGN (0x4)
- 0x40000a00 PROVIDE (__stack_svc_end, .)
- 0x40000a00 PROVIDE (__stack_end, .)
- 0x40000a00 PROVIDE (__heap_start, .)
-OUTPUT(test_ram.elf elf32-littlearm)
-
-.ARM.attributes
- 0x00000000 0x10
- .ARM.attributes
- 0x00000000 0x10 ./src/crt.o
- .ARM.attributes
- 0x00000010 0x10 ./src/main.o
-
-.debug_line 0x00000000 0xd0
- .debug_line 0x00000000 0x79 ./src/crt.o
- .debug_line 0x00000079 0x57 ./src/main.o
-
-.debug_info 0x00000000 0x202
- .debug_info 0x00000000 0x74 ./src/crt.o
- .debug_info 0x00000074 0x18e ./src/main.o
-
-.debug_abbrev 0x00000000 0x76
- .debug_abbrev 0x00000000 0x12 ./src/crt.o
- .debug_abbrev 0x00000012 0x64 ./src/main.o
-
-.debug_aranges 0x00000000 0x48
- .debug_aranges
- 0x00000000 0x28 ./src/crt.o
- .debug_aranges
- 0x00000028 0x20 ./src/main.o
-
-.debug_ranges 0x00000000 0x20
- .debug_ranges 0x00000000 0x20 ./src/crt.o
-
-.debug_frame 0x00000000 0x24
- .debug_frame 0x00000000 0x24 ./src/main.o
-
-.debug_loc 0x00000000 0x1f
- .debug_loc 0x00000000 0x1f ./src/main.o
-
-.debug_pubnames
- 0x00000000 0x1b
- .debug_pubnames
- 0x00000000 0x1b ./src/main.o
-
-.comment 0x00000000 0x12
- .comment 0x00000000 0x12 ./src/main.o
-
-Cross Reference Table
-
-Symbol File
-DAbortHandler ./src/crt.o
-ExitFunction ./src/crt.o
-FIQHandler ./src/crt.o
-IRQHandler ./src/crt.o
-PAbortHandler ./src/crt.o
-ResetHandler ./src/crt.o
-UndefHandler ./src/crt.o
-__bss_end ./src/crt.o
-__bss_start ./src/crt.o
-__stack_abt_end ./src/crt.o
-__stack_fiq_end ./src/crt.o
-__stack_irq_end ./src/crt.o
-__stack_svc_end ./src/crt.o
-__stack_und_end ./src/crt.o
-main ./src/main.o
- ./src/crt.o
+
+Memory Configuration
+
+Name Origin Length Attributes
+ram 0x40000000 0x00008000
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+LOAD ./src/crt.o
+LOAD ./src/main.o
+START GROUP
+LOAD d:/compiler/yagarto/bin/../lib/gcc/arm-elf/4.2.2\libgcc.a
+LOAD d:/compiler/yagarto/bin/../lib/gcc/arm-elf/4.2.2/../../../../arm-elf/lib\libc.a
+END GROUP
+ 0x00000100 FIQ_STACK_SIZE = 0x100
+ 0x00000100 IRQ_STACK_SIZE = 0x100
+ 0x00000100 ABT_STACK_SIZE = 0x100
+ 0x00000100 UND_STACK_SIZE = 0x100
+ 0x00000400 SVC_STACK_SIZE = 0x400
+
+.text 0x40000000 0x16c
+ *(.vectors)
+ .vectors 0x40000000 0x40 ./src/crt.o
+ 0x40000040 . = ALIGN (0x4)
+ *(.init)
+ .init 0x40000040 0xc8 ./src/crt.o
+ 0x400000e4 FIQHandler
+ 0x400000d8 PAbortHandler
+ 0x400000c0 ExitFunction
+ 0x40000040 ResetHandler
+ 0x400000dc DAbortHandler
+ 0x400000e0 IRQHandler
+ 0x400000d0 UndefHandler
+ 0x40000108 . = ALIGN (0x4)
+ *(.text)
+ .text 0x40000108 0x0 ./src/crt.o
+ .text 0x40000108 0x60 ./src/main.o
+ 0x40000108 main
+ 0x40000168 . = ALIGN (0x4)
+ *(.rodata)
+ .rodata 0x40000168 0x4 ./src/main.o
+ 0x4000016c . = ALIGN (0x4)
+ *(.rodata*)
+ 0x4000016c . = ALIGN (0x4)
+ *(.glue_7t)
+ .glue_7t 0x4000016c 0x0 ./src/crt.o
+ .glue_7t 0x4000016c 0x0 ./src/main.o
+ 0x4000016c . = ALIGN (0x4)
+ *(.glue_7)
+ .glue_7 0x4000016c 0x0 ./src/crt.o
+ .glue_7 0x4000016c 0x0 ./src/main.o
+ 0x4000016c . = ALIGN (0x4)
+ 0x4000016c etext = .
+
+.vfp11_veneer 0x00000000 0x0
+ .vfp11_veneer 0x00000000 0x0 ./src/crt.o
+ .vfp11_veneer 0x00000000 0x0 ./src/main.o
+
+.data 0x4000016c 0x0
+ 0x4000016c PROVIDE (__data_start, .)
+ *(.data)
+ .data 0x4000016c 0x0 ./src/crt.o
+ .data 0x4000016c 0x0 ./src/main.o
+ 0x4000016c . = ALIGN (0x4)
+ 0x4000016c edata = .
+ 0x4000016c _edata = .
+ 0x4000016c PROVIDE (__data_end, .)
+
+.bss 0x4000016c 0x894
+ 0x4000016c PROVIDE (__bss_start, .)
+ *(.bss)
+ .bss 0x4000016c 0x0 ./src/crt.o
+ .bss 0x4000016c 0x0 ./src/main.o
+ *(COMMON)
+ 0x4000016c . = ALIGN (0x4)
+ 0x4000016c PROVIDE (__bss_end, .)
+ 0x40000200 . = ALIGN (0x100)
+ *fill* 0x4000016c 0x94 00
+ 0x40000200 PROVIDE (__stack_start, .)
+ 0x40000200 PROVIDE (__stack_fiq_start, .)
+ 0x40000300 . = (. + FIQ_STACK_SIZE)
+ *fill* 0x40000200 0x100 00
+ 0x40000300 . = ALIGN (0x4)
+ 0x40000300 PROVIDE (__stack_fiq_end, .)
+ 0x40000300 PROVIDE (__stack_irq_start, .)
+ 0x40000400 . = (. + IRQ_STACK_SIZE)
+ *fill* 0x40000300 0x100 00
+ 0x40000400 . = ALIGN (0x4)
+ 0x40000400 PROVIDE (__stack_irq_end, .)
+ 0x40000400 PROVIDE (__stack_abt_start, .)
+ 0x40000500 . = (. + ABT_STACK_SIZE)
+ *fill* 0x40000400 0x100 00
+ 0x40000500 . = ALIGN (0x4)
+ 0x40000500 PROVIDE (__stack_abt_end, .)
+ 0x40000500 PROVIDE (__stack_und_start, .)
+ 0x40000600 . = (. + UND_STACK_SIZE)
+ *fill* 0x40000500 0x100 00
+ 0x40000600 . = ALIGN (0x4)
+ 0x40000600 PROVIDE (__stack_und_end, .)
+ 0x40000600 PROVIDE (__stack_svc_start, .)
+ 0x40000a00 . = (. + SVC_STACK_SIZE)
+ *fill* 0x40000600 0x400 00
+ 0x40000a00 . = ALIGN (0x4)
+ 0x40000a00 PROVIDE (__stack_svc_end, .)
+ 0x40000a00 PROVIDE (__stack_end, .)
+ 0x40000a00 PROVIDE (__heap_start, .)
+OUTPUT(test_ram.elf elf32-littlearm)
+
+.ARM.attributes
+ 0x00000000 0x10
+ .ARM.attributes
+ 0x00000000 0x10 ./src/crt.o
+ .ARM.attributes
+ 0x00000010 0x10 ./src/main.o
+
+.debug_line 0x00000000 0xd0
+ .debug_line 0x00000000 0x79 ./src/crt.o
+ .debug_line 0x00000079 0x57 ./src/main.o
+
+.debug_info 0x00000000 0x202
+ .debug_info 0x00000000 0x74 ./src/crt.o
+ .debug_info 0x00000074 0x18e ./src/main.o
+
+.debug_abbrev 0x00000000 0x76
+ .debug_abbrev 0x00000000 0x12 ./src/crt.o
+ .debug_abbrev 0x00000012 0x64 ./src/main.o
+
+.debug_aranges 0x00000000 0x48
+ .debug_aranges
+ 0x00000000 0x28 ./src/crt.o
+ .debug_aranges
+ 0x00000028 0x20 ./src/main.o
+
+.debug_ranges 0x00000000 0x20
+ .debug_ranges 0x00000000 0x20 ./src/crt.o
+
+.debug_frame 0x00000000 0x24
+ .debug_frame 0x00000000 0x24 ./src/main.o
+
+.debug_loc 0x00000000 0x1f
+ .debug_loc 0x00000000 0x1f ./src/main.o
+
+.debug_pubnames
+ 0x00000000 0x1b
+ .debug_pubnames
+ 0x00000000 0x1b ./src/main.o
+
+.comment 0x00000000 0x12
+ .comment 0x00000000 0x12 ./src/main.o
+
+Cross Reference Table
+
+Symbol File
+DAbortHandler ./src/crt.o
+ExitFunction ./src/crt.o
+FIQHandler ./src/crt.o
+IRQHandler ./src/crt.o
+PAbortHandler ./src/crt.o
+ResetHandler ./src/crt.o
+UndefHandler ./src/crt.o
+__bss_end ./src/crt.o
+__bss_start ./src/crt.o
+__stack_abt_end ./src/crt.o
+__stack_fiq_end ./src/crt.o
+__stack_irq_end ./src/crt.o
+__stack_svc_end ./src/crt.o
+__stack_und_end ./src/crt.o
+main ./src/main.o
+ ./src/crt.o
diff --git a/testing/examples/LPC2148Test/test_rom.hex b/testing/examples/LPC2148Test/test_rom.hex
index 48f6aa9..3ee04ee 100644
--- a/testing/examples/LPC2148Test/test_rom.hex
+++ b/testing/examples/LPC2148Test/test_rom.hex
@@ -1,25 +1,25 @@
-:1000000018F09FE518F09FE518F09FE518F09FE5C0
-:1000100018F09FE5606FA0B818F09FE518F09FE515
-:1000200040000000D0000000D4000000D800000014
-:10003000DC00000000000000E0000000E400000020
-:100040000000A0E10000A0E10000A0E10000A0E1AC
-:100050000000A0E10000A0E10000A0E10000A0E19C
-:10006000DBF021E37CD09FE5D7F021E378D09FE55A
-:10007000D1F021E374D09FE5D2F021E370D09FE569
-:10008000D3F021E36CD09FE56C109FE56C209FE5D9
-:100090000030A0E3020051E104308114FCFFFF1A9C
-:1000A00000000FE1C000C0E300F029E10000A0E380
-:1000B0000010A0E348209FE50FE0A0E112FF2FE130
-:1000C0000000A0E10000A0E10000A0E1FBFFFFEACA
-:1000D000FEFFFFEAFEFFFFEAFEFFFFEAFEFFFFEA88
-:1000E000FEFFFFEAFEFFFFEA0004004000030040BD
-:1000F00000010040000200400008004000000040F5
-:1001000000000040080100000CD04DE20130A0E3E7
-:1001100000308DE50230A0E304308DE50030A0E32F
-:1001200008308DE538309FE5002093E500309DE5EF
-:10013000023083E000308DE500309DE5013083E240
-:1001400000308DE504309DE5013083E204308DE51B
-:1001500000209DE504309DE5033082E008308DE508
-:0C016000F4FFFFEA680100000700000047
-:0400000300000040B9
-:00000001FF
+:1000000018F09FE518F09FE518F09FE518F09FE5C0
+:1000100018F09FE5606FA0B818F09FE518F09FE515
+:1000200040000000D0000000D4000000D800000014
+:10003000DC00000000000000E0000000E400000020
+:100040000000A0E10000A0E10000A0E10000A0E1AC
+:100050000000A0E10000A0E10000A0E10000A0E19C
+:10006000DBF021E37CD09FE5D7F021E378D09FE55A
+:10007000D1F021E374D09FE5D2F021E370D09FE569
+:10008000D3F021E36CD09FE56C109FE56C209FE5D9
+:100090000030A0E3020051E104308114FCFFFF1A9C
+:1000A00000000FE1C000C0E300F029E10000A0E380
+:1000B0000010A0E348209FE50FE0A0E112FF2FE130
+:1000C0000000A0E10000A0E10000A0E1FBFFFFEACA
+:1000D000FEFFFFEAFEFFFFEAFEFFFFEAFEFFFFEA88
+:1000E000FEFFFFEAFEFFFFEA0004004000030040BD
+:1000F00000010040000200400008004000000040F5
+:1001000000000040080100000CD04DE20130A0E3E7
+:1001100000308DE50230A0E304308DE50030A0E32F
+:1001200008308DE538309FE5002093E500309DE5EF
+:10013000023083E000308DE500309DE5013083E240
+:1001400000308DE504309DE5013083E204308DE51B
+:1001500000209DE504309DE5033082E008308DE508
+:0C016000F4FFFFEA680100000700000047
+:0400000300000040B9
+:00000001FF
diff --git a/testing/examples/LPC2148Test/test_rom.map b/testing/examples/LPC2148Test/test_rom.map
index 1b7c73a..b737e20 100644
--- a/testing/examples/LPC2148Test/test_rom.map
+++ b/testing/examples/LPC2148Test/test_rom.map
@@ -1,170 +1,170 @@
-
-Memory Configuration
-
-Name Origin Length Attributes
-rom 0x00000000 0x00080000
-ram 0x40000000 0x00008000
-*default* 0x00000000 0xffffffff
-
-Linker script and memory map
-
-LOAD ./src/crt.o
-LOAD ./src/main.o
-START GROUP
-LOAD d:/compiler/yagarto/bin/../lib/gcc/arm-elf/4.2.2\libgcc.a
-LOAD d:/compiler/yagarto/bin/../lib/gcc/arm-elf/4.2.2/../../../../arm-elf/lib\libc.a
-END GROUP
- 0x00000100 FIQ_STACK_SIZE = 0x100
- 0x00000100 IRQ_STACK_SIZE = 0x100
- 0x00000100 ABT_STACK_SIZE = 0x100
- 0x00000100 UND_STACK_SIZE = 0x100
- 0x00000400 SVC_STACK_SIZE = 0x400
-
-.text 0x00000000 0x16c
- *(.vectors)
- .vectors 0x00000000 0x40 ./src/crt.o
- 0x00000040 . = ALIGN (0x4)
- *(.init)
- .init 0x00000040 0xc8 ./src/crt.o
- 0x000000e4 FIQHandler
- 0x000000d8 PAbortHandler
- 0x000000c0 ExitFunction
- 0x00000040 ResetHandler
- 0x000000dc DAbortHandler
- 0x000000e0 IRQHandler
- 0x000000d0 UndefHandler
- 0x00000108 . = ALIGN (0x4)
- *(.text)
- .text 0x00000108 0x0 ./src/crt.o
- .text 0x00000108 0x60 ./src/main.o
- 0x00000108 main
- 0x00000168 . = ALIGN (0x4)
- *(.rodata)
- .rodata 0x00000168 0x4 ./src/main.o
- 0x0000016c . = ALIGN (0x4)
- *(.rodata*)
- 0x0000016c . = ALIGN (0x4)
- *(.glue_7t)
- .glue_7t 0x0000016c 0x0 ./src/crt.o
- .glue_7t 0x0000016c 0x0 ./src/main.o
- 0x0000016c . = ALIGN (0x4)
- *(.glue_7)
- .glue_7 0x0000016c 0x0 ./src/crt.o
- .glue_7 0x0000016c 0x0 ./src/main.o
- 0x0000016c . = ALIGN (0x4)
- 0x0000016c etext = .
-
-.vfp11_veneer 0x00000000 0x0
- .vfp11_veneer 0x00000000 0x0 ./src/crt.o
- .vfp11_veneer 0x00000000 0x0 ./src/main.o
-
-.data 0x40000000 0x0
- 0x40000000 PROVIDE (__data_start, .)
- *(.data)
- .data 0x40000000 0x0 ./src/crt.o
- .data 0x40000000 0x0 ./src/main.o
- 0x40000000 . = ALIGN (0x4)
- 0x40000000 edata = .
- 0x40000000 _edata = .
- 0x40000000 PROVIDE (__data_end, .)
-
-.bss 0x40000000 0x800
- 0x40000000 PROVIDE (__bss_start, .)
- *(.bss)
- .bss 0x40000000 0x0 ./src/crt.o
- .bss 0x40000000 0x0 ./src/main.o
- *(COMMON)
- 0x40000000 . = ALIGN (0x4)
- 0x40000000 PROVIDE (__bss_end, .)
- 0x40000000 . = ALIGN (0x100)
- 0x40000000 PROVIDE (__stack_start, .)
- 0x40000000 PROVIDE (__stack_fiq_start, .)
- 0x40000100 . = (. + FIQ_STACK_SIZE)
- *fill* 0x40000000 0x100 00
- 0x40000100 . = ALIGN (0x4)
- 0x40000100 PROVIDE (__stack_fiq_end, .)
- 0x40000100 PROVIDE (__stack_irq_start, .)
- 0x40000200 . = (. + IRQ_STACK_SIZE)
- *fill* 0x40000100 0x100 00
- 0x40000200 . = ALIGN (0x4)
- 0x40000200 PROVIDE (__stack_irq_end, .)
- 0x40000200 PROVIDE (__stack_abt_start, .)
- 0x40000300 . = (. + ABT_STACK_SIZE)
- *fill* 0x40000200 0x100 00
- 0x40000300 . = ALIGN (0x4)
- 0x40000300 PROVIDE (__stack_abt_end, .)
- 0x40000300 PROVIDE (__stack_und_start, .)
- 0x40000400 . = (. + UND_STACK_SIZE)
- *fill* 0x40000300 0x100 00
- 0x40000400 . = ALIGN (0x4)
- 0x40000400 PROVIDE (__stack_und_end, .)
- 0x40000400 PROVIDE (__stack_svc_start, .)
- 0x40000800 . = (. + SVC_STACK_SIZE)
- *fill* 0x40000400 0x400 00
- 0x40000800 . = ALIGN (0x4)
- 0x40000800 PROVIDE (__stack_svc_end, .)
- 0x40000800 PROVIDE (__stack_end, .)
- 0x40000800 PROVIDE (__heap_start, .)
-OUTPUT(test_rom.elf elf32-littlearm)
-
-.ARM.attributes
- 0x00000000 0x10
- .ARM.attributes
- 0x00000000 0x10 ./src/crt.o
- .ARM.attributes
- 0x00000010 0x10 ./src/main.o
-
-.debug_line 0x00000000 0xd0
- .debug_line 0x00000000 0x79 ./src/crt.o
- .debug_line 0x00000079 0x57 ./src/main.o
-
-.debug_info 0x00000000 0x202
- .debug_info 0x00000000 0x74 ./src/crt.o
- .debug_info 0x00000074 0x18e ./src/main.o
-
-.debug_abbrev 0x00000000 0x76
- .debug_abbrev 0x00000000 0x12 ./src/crt.o
- .debug_abbrev 0x00000012 0x64 ./src/main.o
-
-.debug_aranges 0x00000000 0x48
- .debug_aranges
- 0x00000000 0x28 ./src/crt.o
- .debug_aranges
- 0x00000028 0x20 ./src/main.o
-
-.debug_ranges 0x00000000 0x20
- .debug_ranges 0x00000000 0x20 ./src/crt.o
-
-.debug_frame 0x00000000 0x24
- .debug_frame 0x00000000 0x24 ./src/main.o
-
-.debug_loc 0x00000000 0x1f
- .debug_loc 0x00000000 0x1f ./src/main.o
-
-.debug_pubnames
- 0x00000000 0x1b
- .debug_pubnames
- 0x00000000 0x1b ./src/main.o
-
-.comment 0x00000000 0x12
- .comment 0x00000000 0x12 ./src/main.o
-
-Cross Reference Table
-
-Symbol File
-DAbortHandler ./src/crt.o
-ExitFunction ./src/crt.o
-FIQHandler ./src/crt.o
-IRQHandler ./src/crt.o
-PAbortHandler ./src/crt.o
-ResetHandler ./src/crt.o
-UndefHandler ./src/crt.o
-__bss_end ./src/crt.o
-__bss_start ./src/crt.o
-__stack_abt_end ./src/crt.o
-__stack_fiq_end ./src/crt.o
-__stack_irq_end ./src/crt.o
-__stack_svc_end ./src/crt.o
-__stack_und_end ./src/crt.o
-main ./src/main.o
- ./src/crt.o
+
+Memory Configuration
+
+Name Origin Length Attributes
+rom 0x00000000 0x00080000
+ram 0x40000000 0x00008000
+*default* 0x00000000 0xffffffff
+
+Linker script and memory map
+
+LOAD ./src/crt.o
+LOAD ./src/main.o
+START GROUP
+LOAD d:/compiler/yagarto/bin/../lib/gcc/arm-elf/4.2.2\libgcc.a
+LOAD d:/compiler/yagarto/bin/../lib/gcc/arm-elf/4.2.2/../../../../arm-elf/lib\libc.a
+END GROUP
+ 0x00000100 FIQ_STACK_SIZE = 0x100
+ 0x00000100 IRQ_STACK_SIZE = 0x100
+ 0x00000100 ABT_STACK_SIZE = 0x100
+ 0x00000100 UND_STACK_SIZE = 0x100
+ 0x00000400 SVC_STACK_SIZE = 0x400
+
+.text 0x00000000 0x16c
+ *(.vectors)
+ .vectors 0x00000000 0x40 ./src/crt.o
+ 0x00000040 . = ALIGN (0x4)
+ *(.init)
+ .init 0x00000040 0xc8 ./src/crt.o
+ 0x000000e4 FIQHandler
+ 0x000000d8 PAbortHandler
+ 0x000000c0 ExitFunction
+ 0x00000040 ResetHandler
+ 0x000000dc DAbortHandler
+ 0x000000e0 IRQHandler
+ 0x000000d0 UndefHandler
+ 0x00000108 . = ALIGN (0x4)
+ *(.text)
+ .text 0x00000108 0x0 ./src/crt.o
+ .text 0x00000108 0x60 ./src/main.o
+ 0x00000108 main
+ 0x00000168 . = ALIGN (0x4)
+ *(.rodata)
+ .rodata 0x00000168 0x4 ./src/main.o
+ 0x0000016c . = ALIGN (0x4)
+ *(.rodata*)
+ 0x0000016c . = ALIGN (0x4)
+ *(.glue_7t)
+ .glue_7t 0x0000016c 0x0 ./src/crt.o
+ .glue_7t 0x0000016c 0x0 ./src/main.o
+ 0x0000016c . = ALIGN (0x4)
+ *(.glue_7)
+ .glue_7 0x0000016c 0x0 ./src/crt.o
+ .glue_7 0x0000016c 0x0 ./src/main.o
+ 0x0000016c . = ALIGN (0x4)
+ 0x0000016c etext = .
+
+.vfp11_veneer 0x00000000 0x0
+ .vfp11_veneer 0x00000000 0x0 ./src/crt.o
+ .vfp11_veneer 0x00000000 0x0 ./src/main.o
+
+.data 0x40000000 0x0
+ 0x40000000 PROVIDE (__data_start, .)
+ *(.data)
+ .data 0x40000000 0x0 ./src/crt.o
+ .data 0x40000000 0x0 ./src/main.o
+ 0x40000000 . = ALIGN (0x4)
+ 0x40000000 edata = .
+ 0x40000000 _edata = .
+ 0x40000000 PROVIDE (__data_end, .)
+
+.bss 0x40000000 0x800
+ 0x40000000 PROVIDE (__bss_start, .)
+ *(.bss)
+ .bss 0x40000000 0x0 ./src/crt.o
+ .bss 0x40000000 0x0 ./src/main.o
+ *(COMMON)
+ 0x40000000 . = ALIGN (0x4)
+ 0x40000000 PROVIDE (__bss_end, .)
+ 0x40000000 . = ALIGN (0x100)
+ 0x40000000 PROVIDE (__stack_start, .)
+ 0x40000000 PROVIDE (__stack_fiq_start, .)
+ 0x40000100 . = (. + FIQ_STACK_SIZE)
+ *fill* 0x40000000 0x100 00
+ 0x40000100 . = ALIGN (0x4)
+ 0x40000100 PROVIDE (__stack_fiq_end, .)
+ 0x40000100 PROVIDE (__stack_irq_start, .)
+ 0x40000200 . = (. + IRQ_STACK_SIZE)
+ *fill* 0x40000100 0x100 00
+ 0x40000200 . = ALIGN (0x4)
+ 0x40000200 PROVIDE (__stack_irq_end, .)
+ 0x40000200 PROVIDE (__stack_abt_start, .)
+ 0x40000300 . = (. + ABT_STACK_SIZE)
+ *fill* 0x40000200 0x100 00
+ 0x40000300 . = ALIGN (0x4)
+ 0x40000300 PROVIDE (__stack_abt_end, .)
+ 0x40000300 PROVIDE (__stack_und_start, .)
+ 0x40000400 . = (. + UND_STACK_SIZE)
+ *fill* 0x40000300 0x100 00
+ 0x40000400 . = ALIGN (0x4)
+ 0x40000400 PROVIDE (__stack_und_end, .)
+ 0x40000400 PROVIDE (__stack_svc_start, .)
+ 0x40000800 . = (. + SVC_STACK_SIZE)
+ *fill* 0x40000400 0x400 00
+ 0x40000800 . = ALIGN (0x4)
+ 0x40000800 PROVIDE (__stack_svc_end, .)
+ 0x40000800 PROVIDE (__stack_end, .)
+ 0x40000800 PROVIDE (__heap_start, .)
+OUTPUT(test_rom.elf elf32-littlearm)
+
+.ARM.attributes
+ 0x00000000 0x10
+ .ARM.attributes
+ 0x00000000 0x10 ./src/crt.o
+ .ARM.attributes
+ 0x00000010 0x10 ./src/main.o
+
+.debug_line 0x00000000 0xd0
+ .debug_line 0x00000000 0x79 ./src/crt.o
+ .debug_line 0x00000079 0x57 ./src/main.o
+
+.debug_info 0x00000000 0x202
+ .debug_info 0x00000000 0x74 ./src/crt.o
+ .debug_info 0x00000074 0x18e ./src/main.o
+
+.debug_abbrev 0x00000000 0x76
+ .debug_abbrev 0x00000000 0x12 ./src/crt.o
+ .debug_abbrev 0x00000012 0x64 ./src/main.o
+
+.debug_aranges 0x00000000 0x48
+ .debug_aranges
+ 0x00000000 0x28 ./src/crt.o
+ .debug_aranges
+ 0x00000028 0x20 ./src/main.o
+
+.debug_ranges 0x00000000 0x20
+ .debug_ranges 0x00000000 0x20 ./src/crt.o
+
+.debug_frame 0x00000000 0x24
+ .debug_frame 0x00000000 0x24 ./src/main.o
+
+.debug_loc 0x00000000 0x1f
+ .debug_loc 0x00000000 0x1f ./src/main.o
+
+.debug_pubnames
+ 0x00000000 0x1b
+ .debug_pubnames
+ 0x00000000 0x1b ./src/main.o
+
+.comment 0x00000000 0x12
+ .comment 0x00000000 0x12 ./src/main.o
+
+Cross Reference Table
+
+Symbol File
+DAbortHandler ./src/crt.o
+ExitFunction ./src/crt.o
+FIQHandler ./src/crt.o
+IRQHandler ./src/crt.o
+PAbortHandler ./src/crt.o
+ResetHandler ./src/crt.o
+UndefHandler ./src/crt.o
+__bss_end ./src/crt.o
+__bss_start ./src/crt.o
+__stack_abt_end ./src/crt.o
+__stack_fiq_end ./src/crt.o
+__stack_irq_end ./src/crt.o
+__stack_svc_end ./src/crt.o
+__stack_und_end ./src/crt.o
+main ./src/main.o
+ ./src/crt.o
diff --git a/testing/examples/LPC2294Test/test_ram.hex b/testing/examples/LPC2294Test/test_ram.hex
index 1a922b1..e54b9e3 100644
--- a/testing/examples/LPC2294Test/test_ram.hex
+++ b/testing/examples/LPC2294Test/test_ram.hex
@@ -1,26 +1,26 @@
-:020000044000BA
-:1000000018F09FE518F09FE518F09FE518F09FE5C0
-:1000100018F09FE518F09FE518F09FE518F09FE5B0
-:1000200040000040D0000040D4000040D800004014
-:10003000DC00004000000000E0000040E400004060
-:100040000000A0E10000A0E10000A0E10000A0E1AC
-:100050000000A0E10000A0E10000A0E10000A0E19C
-:10006000DBF021E37CD09FE5D7F021E378D09FE55A
-:10007000D1F021E374D09FE5D2F021E370D09FE569
-:10008000D3F021E36CD09FE56C109FE56C209FE5D9
-:100090000030A0E3020051E104308114FCFFFF1A9C
-:1000A00000000FE1C000C0E300F029E10000A0E380
-:1000B0000010A0E348209FE50FE0A0E112FF2FE130
-:1000C0000000A0E10000A0E10000A0E1FBFFFFEACA
-:1000D000FEFFFFEAFEFFFFEAFEFFFFEAFEFFFFEA88
-:1000E000FEFFFFEAFEFFFFEA0006004000050040B9
-:1000F0000003004000040040000A00406C01004082
-:100100006C010040080100400CD04DE20130A0E33A
-:1001100000308DE50230A0E304308DE50030A0E32F
-:1001200008308DE538309FE5002093E500309DE5EF
-:10013000023083E000308DE500309DE5013083E240
-:1001400000308DE504309DE5013083E204308DE51B
-:1001500000209DE504309DE5033082E008308DE508
-:0C016000F4FFFFEA680100400700000007
-:040000054000004077
-:00000001FF
+:020000044000BA
+:1000000018F09FE518F09FE518F09FE518F09FE5C0
+:1000100018F09FE518F09FE518F09FE518F09FE5B0
+:1000200040000040D0000040D4000040D800004014
+:10003000DC00004000000000E0000040E400004060
+:100040000000A0E10000A0E10000A0E10000A0E1AC
+:100050000000A0E10000A0E10000A0E10000A0E19C
+:10006000DBF021E37CD09FE5D7F021E378D09FE55A
+:10007000D1F021E374D09FE5D2F021E370D09FE569
+:10008000D3F021E36CD09FE56C109FE56C209FE5D9
+:100090000030A0E3020051E104308114FCFFFF1A9C
+:1000A00000000FE1C000C0E300F029E10000A0E380
+:1000B0000010A0E348209FE50FE0A0E112FF2FE130
+:1000C0000000A0E10000A0E10000A0E1FBFFFFEACA
+:1000D000FEFFFFEAFEFFFFEAFEFFFFEAFEFFFFEA88
+:1000E000FEFFFFEAFEFFFFEA0006004000050040B9
+:1000F0000003004000040040000A00406C01004082
+:100100006C010040080100400CD04DE20130A0E33A
+:1001100000308DE50230A0E304308DE50030A0E32F
+:1001200008308DE538309FE5002093E500309DE5EF
+:10013000023083E000308DE500309DE5013083E240
+:1001400000308DE504309DE5013083E204308DE51B
+:1001500000209DE504309DE5033082E008308DE508
+:0C016000F4FFFFEA680100400700000007
+:040000054000004077
+:00000001FF
diff --git a/testing/examples/LPC2294Test/test_ram.map b/testing/examples/LPC2294Test/test_ram.map
index c92c5e2..20b9c68 100644
--- a/testing/examples/LPC2294Test/test_ram.map
+++ b/testing/examples/LPC2294Test/test_ram.map
@@ -1,170 +1,170 @@
-
-Memory Configuration
-
-Name Origin Length Attributes
-ram 0x40000000 0x00004000
-*default* 0x00000000 0xffffffff
-
-Linker script and memory map
-
-LOAD ./src/crt.o
-LOAD ./src/main.o
-START GROUP
-LOAD d:/compiler/yagarto/bin/../lib/gcc/arm-elf/4.2.2\libgcc.a
-LOAD d:/compiler/yagarto/bin/../lib/gcc/arm-elf/4.2.2/../../../../arm-elf/lib\libc.a
-END GROUP
- 0x00000100 FIQ_STACK_SIZE = 0x100
- 0x00000100 IRQ_STACK_SIZE = 0x100
- 0x00000100 ABT_STACK_SIZE = 0x100
- 0x00000100 UND_STACK_SIZE = 0x100
- 0x00000400 SVC_STACK_SIZE = 0x400
-
-.text 0x40000000 0x16c
- *(.vectors)
- .vectors 0x40000000 0x40 ./src/crt.o
- 0x40000040 . = ALIGN (0x4)
- *(.init)
- .init 0x40000040 0xc8 ./src/crt.o
- 0x400000e4 FIQHandler
- 0x400000d8 PAbortHandler
- 0x400000c0 ExitFunction
- 0x40000040 ResetHandler
- 0x400000dc DAbortHandler
- 0x400000e0 IRQHandler
- 0x400000d0 UndefHandler
- 0x40000108 . = ALIGN (0x4)
- *(.text)
- .text 0x40000108 0x0 ./src/crt.o
- .text 0x40000108 0x60 ./src/main.o
- 0x40000108 main
- 0x40000168 . = ALIGN (0x4)
- *(.rodata)
- .rodata 0x40000168 0x4 ./src/main.o
- 0x4000016c . = ALIGN (0x4)
- *(.rodata*)
- 0x4000016c . = ALIGN (0x4)
- *(.glue_7t)
- .glue_7t 0x4000016c 0x0 ./src/crt.o
- .glue_7t 0x4000016c 0x0 ./src/main.o
- 0x4000016c . = ALIGN (0x4)
- *(.glue_7)
- .glue_7 0x4000016c 0x0 ./src/crt.o
- .glue_7 0x4000016c 0x0 ./src/main.o
- 0x4000016c . = ALIGN (0x4)
- 0x4000016c etext = .
-
-.vfp11_veneer 0x00000000 0x0
- .vfp11_veneer 0x00000000 0x0 ./src/crt.o
- .vfp11_veneer 0x00000000 0x0 ./src/main.o
-
-.data 0x4000016c 0x0
- 0x4000016c PROVIDE (__data_start, .)
...
[truncated message content] |
|
From: David B. <dbr...@us...> - 2009-10-26 19:14:51
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via d87ee640c7a8e77a34d2d72185be157a97b39061 (commit)
via eaebc6cd699bcf414dc307dc65354a9f991dba59 (commit)
via 592e021543353e6ef2814713f0a1412e4119710a (commit)
from 8b30f22dec336003159039202a68a85670ca9b8b (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit d87ee640c7a8e77a34d2d72185be157a97b39061
Merge: eaebc6c 8b30f22
Author: David Brownell <dbr...@us...>
Date: Mon Oct 26 11:14:28 2009 -0700
Merge branch 'master' of ssh://dbr...@op.../gitroot/openocd/openocd
commit eaebc6cd699bcf414dc307dc65354a9f991dba59
Author: Wookey <wo...@wo...>
Date: Mon Oct 26 17:06:05 2009 +0000
balloon3 board base config
This is the very basic board config for the balloon3 board cpu JTAG
channel.
The rest of the config comprises another 14 .cfg files which I suspect
openocd doesn't really want all of. I'm still not sure how to deal
with this. I'll post another mail/patch to discuss.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/tcl/board/balloon3-cpu.cfg b/tcl/board/balloon3-cpu.cfg
new file mode 100644
index 0000000..8a646b7
--- /dev/null
+++ b/tcl/board/balloon3-cpu.cfg
@@ -0,0 +1,13 @@
+# Config for balloon3 board, cpu JTAG port. http://balloonboard.org/
+# The board has separate JTAG ports for cpu and CPLD/FPGA devices
+# Chaining is done on IO interfaces if desired.
+
+source [find target/pxa270.cfg]
+
+# The board supports separate reset lines
+# Override this in the interface config for parallel dongles
+reset_config trst_and_srst separate
+
+# flash bank <driver> <base> <size> <chip_width> <bus_width>
+# 29LV650 64Mbit Flash
+flash bank cfi 0x00000000 0x800000 2 2 0
commit 592e021543353e6ef2814713f0a1412e4119710a
Author: Michael Roth <mr...@ne...>
Date: Mon Oct 26 14:01:42 2009 +0100
SVF: fix parsing hex strings containing leading '0' characters
Ignore leading '0' characters on hex strings. For example a bit
pattern consisting of 6 bits could be written as 3f, 03f or 003f and
so on.
Signed-off-by: Michael Roth <mr...@ne...>
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/svf/svf.c b/src/svf/svf.c
index dec4b19..276a374 100644
--- a/src/svf/svf.c
+++ b/src/svf/svf.c
@@ -680,6 +680,10 @@ static int svf_copy_hexstring_to_binary(char *str, uint8_t **bin, int orig_bit_l
}
}
+ // consume optional leading '0' characters
+ while (str_len > 0 && str[str_len - 1] == '0')
+ str_len--;
+
// check valid
if (str_len > 0 || (ch & ~((1 << (4 - (bit_len % 4))) - 1)) != 0)
{
-----------------------------------------------------------------------
Summary of changes:
src/svf/svf.c | 4 ++++
tcl/board/balloon3-cpu.cfg | 13 +++++++++++++
2 files changed, 17 insertions(+), 0 deletions(-)
create mode 100644 tcl/board/balloon3-cpu.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2009-10-26 09:16:12
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 8b30f22dec336003159039202a68a85670ca9b8b (commit)
from 6cb1d10cdad509939e3decf089e08c289d85d5cf (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 8b30f22dec336003159039202a68a85670ca9b8b
Author: Ãyvind Harboe <oyv...@zy...>
Date: Fri Oct 23 16:13:10 2009 +0200
Idea for adding watchpoint masks.
diff --git a/TODO b/TODO
index f567a82..7bdd626 100644
--- a/TODO
+++ b/TODO
@@ -217,6 +217,11 @@ https://lists.berlios.de/pipermail/openocd-development/2009-October/011506.html
https://lists.berlios.de/pipermail/openocd-development/2009-October/011507.html
- breakpoints can get lost in some circumstances: @par
https://lists.berlios.de/pipermail/openocd-development/2009-June/008853.html
+- add support for masks in watchpoints. The trick is that GDB does not
+ support a breakpoint mask in the remote protocol. One way to work around
+ this is to add a separate command "watchpoint_mask add/rem <addr> <mask>", that
+ is run to register a list of masks that the gdb_server knows to use with
+ a particular watchpoint address.
- integrate Keil AGDI interface to OpenOCD? (submitted by Dario Vecchio)
@section thelisttesting Testing Suite
-----------------------------------------------------------------------
Summary of changes:
TODO | 5 +++++
1 files changed, 5 insertions(+), 0 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-10-26 08:36:24
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 6cb1d10cdad509939e3decf089e08c289d85d5cf (commit)
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- Log -----------------------------------------------------------------
commit 6cb1d10cdad509939e3decf089e08c289d85d5cf
Author: David Brownell <dbr...@us...>
Date: Mon Oct 26 00:36:03 2009 -0700
JTAG: simple autoprobing
This patch adds basic autoprobing support for the JTAG scan chains
which cooperate. To use, you can invoke OpenOCD with just:
- interface spec: "-f interface/...cfg"
- possibly with "-c 'reset_config ...'" for SRST/TRST
- possibly with "-c 'jtag_khz ...'" for the JTAG clock
Then set up config files matching the reported TAPs. It doesn't
declare targets ... just TAPs. So facilities above the JTAG and
SVF/XSVF levels won't be available without a real config; this is
almost purely a way to generate diagnostics.
Autoprobe was successful with most boards I tested, except ones
incorporating C55x DSPs (which don't cooperate with this scheme
for IR length autodetection). Here's what one multi-TAP chip
reported, with the "Warn:" prefixes removed:
clock speed 500 kHz
There are no enabled taps. AUTO PROBING MIGHT NOT WORK!!
AUTO auto0.tap - use "jtag newtap auto0 tap -expected-id 0x2b900f0f ..."
AUTO auto1.tap - use "jtag newtap auto1 tap -expected-id 0x07926001 ..."
AUTO auto2.tap - use "jtag newtap auto2 tap -expected-id 0x0b73b02f ..."
AUTO auto0.tap - use "... -irlen 4"
AUTO auto1.tap - use "... -irlen 4"
AUTO auto2.tap - use "... -irlen 6"
no gdb ports allocated as no target has been specified
The patch tweaks IR setup a bit, so we can represent TAPs with
undeclared IR length.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/TODO b/TODO
index 6f9c749..f567a82 100644
--- a/TODO
+++ b/TODO
@@ -55,8 +55,10 @@ directly in minidriver API for better embedded host performance.
The following tasks have been suggested for adding new core JTAG support:
-- autodetect devices present on the scan chain
- - implement 'discover_taps' command
+- Improve autodetection of TAPs by supporting tcl escape procedures that
+ can configure discovered TAPs based on IDCODE value ... they could:
+ - Remove guessing for irlen
+ - Allow non-default irmask/ircapture values
- SPI/UART emulation:
- (ab)use bit-banging JTAG interfaces to emulate SPI/UART
- allow SPI to program flash, MCUs, etc.
@@ -94,6 +96,8 @@ interface support:
- FT2232 (libftdi):
- make performance comparable to alternatives (on Win32, D2XX is faster)
- make usability comparable to alternatives
+- Autodetect USB based adapters; this should be easy on Linux. If there's
+ more than one, list the options; otherwise, just select that one.
The following tasks have been suggested for adding new JTAG interfaces:
@@ -133,6 +137,7 @@ Once the above are completed:
@section thelisttargets Target Support
+- Many common ARM cores could be autodetected using IDCODE
- general layer cleanup: @par
https://lists.berlios.de/pipermail/openocd-development/2009-May/006590.html
- regression: "reset halt" between 729(works) and 788(fails): @par
diff --git a/src/jtag/core.c b/src/jtag/core.c
index 08cfe43..8bb45bc 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -890,6 +890,9 @@ void jtag_sleep(uint32_t us)
*/
#define END_OF_CHAIN_FLAG 0x000000ff
+/* a larger IR length than we ever expect to autoprobe */
+#define JTAG_IRLEN_MAX 60
+
static int jtag_examine_chain_execute(uint8_t *idcode_buffer, unsigned num_idcode)
{
scan_field_t field = {
@@ -1027,6 +1030,8 @@ static int jtag_examine_chain(void)
uint8_t idcode_buffer[JTAG_MAX_CHAIN_SIZE * 4];
unsigned bit_count;
int retval;
+ int tapcount = 0;
+ bool autoprobe = false;
/* DR scan to collect BYPASS or IDCODE register contents.
* Then make sure the scan data has both ones and zeroes.
@@ -1040,11 +1045,9 @@ static int jtag_examine_chain(void)
/* point at the 1st tap */
jtag_tap_t *tap = jtag_tap_next_enabled(NULL);
- if (tap == NULL)
- {
- LOG_ERROR("JTAG: No taps enabled?");
- return ERROR_JTAG_INIT_FAILED;
- }
+
+ if (!tap)
+ autoprobe = true;
for (bit_count = 0;
tap && bit_count < (JTAG_MAX_CHAIN_SIZE * 32) - 31;
@@ -1086,6 +1089,59 @@ static int jtag_examine_chain(void)
return ERROR_JTAG_INIT_FAILED;
}
+ /* if autoprobing, the tap list is still empty ... populate it! */
+ while (autoprobe && bit_count < (JTAG_MAX_CHAIN_SIZE * 32) - 31) {
+ uint32_t idcode;
+ char buf[12];
+
+ /* Is there another TAP? */
+ idcode = buf_get_u32(idcode_buffer, bit_count, 32);
+ if (jtag_idcode_is_final(idcode))
+ break;
+
+ /* Default everything in this TAP except IR length.
+ *
+ * REVISIT create a jtag_alloc(chip, tap) routine, and
+ * share it with jim_newtap_cmd().
+ */
+ tap = calloc(1, sizeof *tap);
+ if (!tap)
+ return ERROR_FAIL;
+
+ sprintf(buf, "auto%d", tapcount++);
+ tap->chip = strdup(buf);
+ tap->tapname = strdup("tap");
+
+ sprintf(buf, "%s.%s", tap->chip, tap->tapname);
+ tap->dotted_name = strdup(buf);
+
+ /* tap->ir_length == 0 ... signifying irlen autoprobe */
+ tap->ir_capture_mask = 0x03;
+ tap->ir_capture_value = 0x01;
+
+ tap->enabled = true;
+
+ if ((idcode & 1) == 0) {
+ bit_count += 1;
+ tap->hasidcode = false;
+ } else {
+ bit_count += 32;
+ tap->hasidcode = true;
+ tap->idcode = idcode;
+
+ tap->expected_ids_cnt = 1;
+ tap->expected_ids = malloc(sizeof(uint32_t));
+ tap->expected_ids[0] = idcode;
+ }
+
+ LOG_WARNING("AUTO %s - use \"jtag newtap "
+ "%s %s -expected-id 0x%8.8" PRIx32 " ...\"",
+ tap->dotted_name, tap->chip, tap->tapname,
+ tap->idcode);
+
+ jtag_tap_init(tap);
+ }
+
/* After those IDCODE or BYPASS register values should be
* only the data we fed into the scan chain.
*/
@@ -1120,10 +1176,13 @@ static int jtag_validate_ircapture(void)
int chain_pos = 0;
int retval;
+ /* when autoprobing, accomodate huge IR lengths */
for (tap = NULL, total_ir_length = 0;
(tap = jtag_tap_next_enabled(tap)) != NULL;
- total_ir_length += tap->ir_length)
- continue;
+ total_ir_length += tap->ir_length) {
+ if (tap->ir_length == 0)
+ total_ir_length += JTAG_IRLEN_MAX;
+ }
/* increase length to add 2 bit sentinel after scan */
total_ir_length += 2;
@@ -1156,6 +1215,25 @@ static int jtag_validate_ircapture(void)
break;
}
+ /* If we're autoprobing, guess IR lengths. They must be at
+ * least two bits. Guessing will fail if (a) any TAP does
+ * not conform to the JTAG spec; or (b) when the upper bits
+ * captured from some conforming TAP are nonzero.
+ *
+ * REVISIT alternative approach: escape to some tcl code
+ * which could provide more knowledge, based on IDCODE; and
+ * only guess when that has no success.
+ */
+ if (tap->ir_length == 0) {
+ tap->ir_length = 2;
+ while ((val = buf_get_u32(ir_test, chain_pos,
+ tap->ir_length + 1)) == 1) {
+ tap->ir_length++;
+ }
+ LOG_WARNING("AUTO %s - use \"... -irlen %d\"",
+ jtag_tap_name(tap), tap->ir_length);
+ }
+
/* Validate the two LSBs, which must be 01 per JTAG spec.
*
* Or ... more bits could be provided by TAP declaration.
@@ -1207,9 +1285,8 @@ void jtag_tap_init(jtag_tap_t *tap)
unsigned ir_len_bits;
unsigned ir_len_bytes;
- assert(0 != tap->ir_length);
-
- ir_len_bits = tap->ir_length;
+ /* if we're autoprobing, cope with potentially huge ir_length */
+ ir_len_bits = tap->ir_length ? : JTAG_IRLEN_MAX;
ir_len_bytes = CEIL(ir_len_bits, 8);
tap->expected = calloc(1, ir_len_bytes);
@@ -1302,8 +1379,21 @@ int jtag_init_inner(struct command_context_s *cmd_ctx)
tap = jtag_tap_next_enabled(NULL);
if (tap == NULL) {
- LOG_ERROR("There are no enabled taps?");
- return ERROR_JTAG_INIT_FAILED;
+ /* Once JTAG itself is properly set up, and the scan chain
+ * isn't absurdly large, IDCODE autoprobe should work fine.
+ *
+ * But ... IRLEN autoprobe can fail even on systems which
+ * are fully conformant to JTAG. Also, JTAG setup can be
+ * quite finicky on some systems.
+ *
+ * REVISIT: if TAP autoprobe works OK, then in many cases
+ * we could escape to tcl code and set up targets based on
+ * the TAP's IDCODE values.
+ */
+ LOG_WARNING("There are no enabled taps. "
+ "AUTO PROBING MIGHT NOT WORK!!");
+
+ /* REVISIT default clock will often be too fast ... */
}
jtag_add_tlr();
-----------------------------------------------------------------------
Summary of changes:
TODO | 9 +++-
src/jtag/core.c | 114 +++++++++++++++++++++++++++++++++++++++++++++++++------
2 files changed, 109 insertions(+), 14 deletions(-)
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From: David B. <dbr...@us...> - 2009-10-26 00:30:54
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 0cac8b67be5c6f6f5b2bc3a86f78d4d02e364792 (commit)
from a07422c26cb0a659c7615d6c0aa2cf09d8a48829 (commit)
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- Log -----------------------------------------------------------------
commit 0cac8b67be5c6f6f5b2bc3a86f78d4d02e364792
Author: David Brownell <dbr...@us...>
Date: Sun Oct 25 16:30:30 2009 -0700
minor fixes to TODO list
diff --git a/TODO b/TODO
index 611bdd3..6f9c749 100644
--- a/TODO
+++ b/TODO
@@ -78,6 +78,10 @@ There are some known bugs to fix in JTAG adapter drivers:
- usbprog.c
- vsllink.c
- rlink/rlink.c
+- bug: USBprog is broken with new tms sequence; it needs 7-clock cycles.
+ Fix promised from Peter Denison openwrt at marshadder.org
+ Workaround: use "tms_sequence long" @par
+ https://lists.berlios.de/pipermail/openocd-development/2009-July/009426.html
The following tasks have been suggeted for improving OpenOCD's JTAG
interface support:
@@ -131,10 +135,6 @@ Once the above are completed:
- general layer cleanup: @par
https://lists.berlios.de/pipermail/openocd-development/2009-May/006590.html
-- bug: either USBprog is broken with new tms sequence or there is a general
- problem with XScale and the new tms sequence. Workaround: use "tms_sequence long"
- @par
- https://lists.berlios.de/pipermail/openocd-development/2009-July/009426.html
- regression: "reset halt" between 729(works) and 788(fails): @par
https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
- ARM7/9:
@@ -144,7 +144,7 @@ https://lists.berlios.de/pipermail/openocd-development/2009-October/011506.html
- add reset option to allow programming embedded ice while srst is asserted.
Some CPUs will gate the JTAG clock when srst is asserted and in this case,
it is necessary to program embedded ice and then assert srst afterwards.
-- ARM923EJS:
+- ARM926EJS:
- reset run/halt/step is not robust; needs testing to map out problems.
- ARM11 improvements (MB?)
- add support for asserting srst to reset the core.
-----------------------------------------------------------------------
Summary of changes:
TODO | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
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From: Øyvind H. <go...@us...> - 2009-10-25 22:16:36
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via a07422c26cb0a659c7615d6c0aa2cf09d8a48829 (commit)
via d785f552ee034aedb26aefc3e47e5c78cdcce065 (commit)
from 19b84dafb0a9902df78aa021330cbcfae93a89a7 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit a07422c26cb0a659c7615d6c0aa2cf09d8a48829
Author: Ãyvind Harboe <oyv...@zy...>
Date: Sun Oct 25 18:29:17 2009 +0100
fix syntax of mww phys.
diff --git a/tcl/board/atmel_at91sam9260-ek.cfg b/tcl/board/atmel_at91sam9260-ek.cfg
index 06a54e2..e74ccf4 100644
--- a/tcl/board/atmel_at91sam9260-ek.cfg
+++ b/tcl/board/atmel_at91sam9260-ek.cfg
@@ -24,7 +24,7 @@ $_TARGETNAME configure -event reset-start {
jtag_rclk 5
halt
# RSTC_MR : enable user reset, MMU may be enabled... use physical address
- arm926ejs mww phys 0xfffffd08 0xa5000501
+ mww phys 0xfffffd08 0xa5000501
}
$_TARGETNAME configure -event reset-init {
diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg
index 2981950..90acafa 100644
--- a/tcl/board/mini2440.cfg
+++ b/tcl/board/mini2440.cfg
@@ -177,10 +177,10 @@ proc init_2440 { } {
# usb clock are off 12mHz xtal
#-----------------------------------------------
- arm920t mww phys 0x4C000014 0x00000005 # Clock Divider control Reg
- arm920t mww phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register
- arm920t mww phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg
- arm920t mww phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg
+ mww phys 0x4C000014 0x00000005 # Clock Divider control Reg
+ mww phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register
+ mww phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg
+ mww phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg
#-----------------------------------------------
# Configure Memory controller
@@ -188,45 +188,45 @@ proc init_2440 { } {
# DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7
#-----------------------------------------------
- arm920t mww phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width
- arm920t mww phys 0x48000010 0x00001112 # BANKCON4 - ?
- arm920t mww phys 0x4800001c 0x00018009 # BANKCON6 - DRAM
- arm920t mww phys 0x48000020 0x00018009 # BANKCON7 - DRAM
- arm920t mww phys 0x48000024 0x008E04EB # REFRESH - DRAM
- arm920t mww phys 0x48000028 0x000000B2 # BANKSIZE - DRAM
- arm920t mww phys 0x4800002C 0x00000030 # MRSRB6 - DRAM
- arm920t mww phys 0x48000030 0x00000030 # MRSRB7 - DRAM
+ mww phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width
+ mww phys 0x48000010 0x00001112 # BANKCON4 - ?
+ mww phys 0x4800001c 0x00018009 # BANKCON6 - DRAM
+ mww phys 0x48000020 0x00018009 # BANKCON7 - DRAM
+ mww phys 0x48000024 0x008E04EB # REFRESH - DRAM
+ mww phys 0x48000028 0x000000B2 # BANKSIZE - DRAM
+ mww phys 0x4800002C 0x00000030 # MRSRB6 - DRAM
+ mww phys 0x48000030 0x00000030 # MRSRB7 - DRAM
#-----------------------------------------------
# Now port configuration for enables for memory
# and other stuff.
#-----------------------------------------------
- arm920t mww phys 0x56000000 0x007FFFFF # GPACON
+ mww phys 0x56000000 0x007FFFFF # GPACON
- arm920t mww phys 0x56000010 0x00295559 # GPBCON
- arm920t mww phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE)
- arm920t mww phys 0x56000014 0x000007C2 # GPBDAT
+ mww phys 0x56000010 0x00295559 # GPBCON
+ mww phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE)
+ mww phys 0x56000014 0x000007C2 # GPBDAT
- arm920t mww phys 0x56000020 0xAAAAA6AA # GPCCON
- arm920t mww phys 0x56000028 0x0000FFFF # GPCUP
- arm920t mww phys 0x56000024 0x00000020 # GPCDAT
+ mww phys 0x56000020 0xAAAAA6AA # GPCCON
+ mww phys 0x56000028 0x0000FFFF # GPCUP
+ mww phys 0x56000024 0x00000020 # GPCDAT
- arm920t mww phys 0x56000030 0xAAAAAAAA # GPDCON
- arm920t mww phys 0x56000038 0x0000FFFF # GPDUP
+ mww phys 0x56000030 0xAAAAAAAA # GPDCON
+ mww phys 0x56000038 0x0000FFFF # GPDUP
- arm920t mww phys 0x56000040 0xAAAAAAAA # GPECON
- arm920t mww phys 0x56000048 0x0000FFFF # GPEUP
+ mww phys 0x56000040 0xAAAAAAAA # GPECON
+ mww phys 0x56000048 0x0000FFFF # GPEUP
- arm920t mww phys 0x56000050 0x00001555 # GPFCON
- arm920t mww phys 0x56000058 0x0000007F # GPFUP
- arm920t mww phys 0x56000054 0x00000000 # GPFDAT
+ mww phys 0x56000050 0x00001555 # GPFCON
+ mww phys 0x56000058 0x0000007F # GPFUP
+ mww phys 0x56000054 0x00000000 # GPFDAT
- arm920t mww phys 0x56000060 0x00150114 # GPGCON
- arm920t mww phys 0x56000068 0x0000007F # GPGUP
+ mww phys 0x56000060 0x00150114 # GPGCON
+ mww phys 0x56000068 0x0000007F # GPGUP
- arm920t mww phys 0x56000070 0x0015AAAA # GPHCON
- arm920t mww phys 0x56000078 0x000003FF # GPGUP
+ mww phys 0x56000070 0x0015AAAA # GPHCON
+ mww phys 0x56000078 0x000003FF # GPGUP
}
diff --git a/tcl/board/olimex_sam9_l9260.cfg b/tcl/board/olimex_sam9_l9260.cfg
index 935d7cd..5c4714e 100644
--- a/tcl/board/olimex_sam9_l9260.cfg
+++ b/tcl/board/olimex_sam9_l9260.cfg
@@ -26,7 +26,7 @@ $_TARGETNAME configure -event reset-start {
# RSTC_MR : enable user reset, reset length is 64 slow clock cycles. MMU may
# be enabled... use physical address.
- arm926ejs mww phys 0xfffffd08 0xa5000501
+ mww phys 0xfffffd08 0xa5000501
}
$_TARGETNAME configure -event reset-init {
diff --git a/tcl/board/unknown_at91sam9260.cfg b/tcl/board/unknown_at91sam9260.cfg
index 7286a96..2abd367 100644
--- a/tcl/board/unknown_at91sam9260.cfg
+++ b/tcl/board/unknown_at91sam9260.cfg
@@ -18,7 +18,7 @@ $_TARGETNAME configure -event reset-start {
jtag_rclk 3
halt
# RSTC_MR : enable user reset, MMU may be enabled... use physical address
- arm926ejs mww phys 0xfffffd08 0xa5000501
+ mww phys 0xfffffd08 0xa5000501
}
diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg
index c14c98e..ee840c8 100644
--- a/tcl/target/davinci.cfg
+++ b/tcl/target/davinci.cfg
@@ -204,34 +204,34 @@ proc davinci_wdog_reset {} {
#
# EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
- arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000
+ mww phys [expr $timer2_phys + 0x28] 0x00004000
#
# Part II -- in case watchdog hasn't been set up
#
# TCR: disable, force internal clock source
- arm926ejs mww phys [expr $timer2_phys + 0x20] 0
+ mww phys [expr $timer2_phys + 0x20] 0
# TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
- arm926ejs mww phys [expr $timer2_phys + 0x24] 0
- arm926ejs mww phys [expr $timer2_phys + 0x24] 0x110b
+ mww phys [expr $timer2_phys + 0x24] 0
+ mww phys [expr $timer2_phys + 0x24] 0x110b
# clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
# so watchdog triggers ASAP
- arm926ejs mww phys [expr $timer2_phys + 0x10] 0
- arm926ejs mww phys [expr $timer2_phys + 0x14] 0
- arm926ejs mww phys [expr $timer2_phys + 0x18] 0
- arm926ejs mww phys [expr $timer2_phys + 0x1c] 0
+ mww phys [expr $timer2_phys + 0x10] 0
+ mww phys [expr $timer2_phys + 0x14] 0
+ mww phys [expr $timer2_phys + 0x18] 0
+ mww phys [expr $timer2_phys + 0x1c] 0
# WDTCR: put into pre-active state, then active
- arm926ejs mww phys [expr $timer2_phys + 0x28] 0xa5c64000
- arm926ejs mww phys [expr $timer2_phys + 0x28] 0xda7e4000
+ mww phys [expr $timer2_phys + 0x28] 0xa5c64000
+ mww phys [expr $timer2_phys + 0x28] 0xda7e4000
#
# Part III -- it's ready to rumble
#
# WDTCR: write invalid WDKEY to trigger reset
- arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000
+ mww phys [expr $timer2_phys + 0x28] 0x00004000
}
commit d785f552ee034aedb26aefc3e47e5c78cdcce065
Author: Ãyvind Harboe <oyv...@zy...>
Date: Sun Oct 25 18:24:18 2009 +0100
check if mmu is enabled before using mmu code path
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 9061174..ef9a494 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -713,7 +713,7 @@ int arm926ejs_write_memory(struct target_s *target, uint32_t address, uint32_t s
/* FIX!!!! this should be cleaned up and made much more general. The
* plan is to write up and test on arm926ejs specifically and
* then generalize and clean up afterwards. */
- if ((count == 1) && ((size==2) || (size==4)))
+ if (arm926ejs->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) || (size==4)))
{
/* special case the handling of single word writes to bypass MMU
* to allow implementation of breakpoints in memory marked read only
-----------------------------------------------------------------------
Summary of changes:
src/target/arm926ejs.c | 2 +-
tcl/board/atmel_at91sam9260-ek.cfg | 2 +-
tcl/board/mini2440.cfg | 60 ++++++++++++++++++------------------
tcl/board/olimex_sam9_l9260.cfg | 2 +-
tcl/board/unknown_at91sam9260.cfg | 2 +-
tcl/target/davinci.cfg | 22 ++++++------
6 files changed, 45 insertions(+), 45 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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|
From: David B. <dbr...@us...> - 2009-10-25 22:06:13
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 19b84dafb0a9902df78aa021330cbcfae93a89a7 (commit)
from e98817c4636f45b45db4332d2a5fbf36676f2f39 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 19b84dafb0a9902df78aa021330cbcfae93a89a7
Author: David Brownell <dbr...@us...>
Date: Sun Oct 25 14:03:14 2009 -0700
ARM: rename "arm9tdmi vector_catch" to "arm9 ..."
And update doc accordingly. That EmbeddedICE register was
introduced for ARM9TDMI and then carried forward into most
new chips that use EmbeddedICE.
diff --git a/NEWS b/NEWS
index 81fce82..436dab7 100644
--- a/NEWS
+++ b/NEWS
@@ -19,6 +19,8 @@ Target Layer:
VERY EARLY Cortex-A8 and ARMv7A support
Updated BeagleBoard.org hardware support
New commands for use with XScale processors: "xscale vector_table"
+ ARM9
+ name change: "arm9 vector_catch" not "arm9tdmi vector_catch"
ARM11
single stepping support for i.MX31
bugfix for missing "arm11" prefix on "arm11 memwrite ..."
diff --git a/TODO b/TODO
index fa9477a..611bdd3 100644
--- a/TODO
+++ b/TODO
@@ -138,9 +138,8 @@ Once the above are completed:
- regression: "reset halt" between 729(works) and 788(fails): @par
https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
- ARM7/9:
- - clean up "arm9tdmi vector_catch". Should be available for other arm9
- (e.g. arm926ejs) and some(???) arm7 cores. @par
-https://lists.berlios.de/pipermail/openocd-development/2009-October/011488.html
+ - clean up "arm9tdmi vector_catch". Available for some arm7 cores? @par
+https://lists.berlios.de/pipermail/openocd-development/2009-October/011488.html
https://lists.berlios.de/pipermail/openocd-development/2009-October/011506.html
- add reset option to allow programming embedded ice while srst is asserted.
Some CPUs will gate the JTAG clock when srst is asserted and in this case,
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 6760994..b91fb3b 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -768,7 +768,7 @@ early boot code, which performs some of the same actions
that the @code{reset-init} event handler does.
@item
-Likewise, the @command{arm9tdmi vector_catch} command (or
+Likewise, the @command{arm9 vector_catch} command (or
@cindex vector_catch
its siblings @command{xscale vector_catch}
and @command{cortex_m3 vector_catch}) can be a timesaver
@@ -5028,7 +5028,7 @@ at @var{address} for @var{length} bytes.
This is a software breakpoint, unless @option{hw} is specified
in which case it will be a hardware breakpoint.
-(@xref{arm9tdmi vector_catch}, or @pxref{xscale vector_catch},
+(@xref{arm9 vector_catch}, or @pxref{xscale vector_catch},
for similar mechanisms that do not consume hardware breakpoints.)
@end deffn
@@ -5453,18 +5453,13 @@ ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
integer processors.
Such cores include the ARM920T, ARM926EJ-S, and ARM966.
-For historical reasons, one command shared by these cores starts
-with the @command{arm9tdmi} prefix.
-This is true even for ARM9E based processors, which implement the
-ARMv5TE architecture instead of ARMv4T.
-
@c 9-june-2009: tried this on arm920t, it didn't work.
@c no-params always lists nothing caught, and that's how it acts.
@c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
@c versions have different rules about when they commit writes.
-@anchor{arm9tdmi vector_catch}
-@deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
+@anchor{arm9 vector_catch}
+@deffn Command {arm9 vector_catch} [@option{all}|@option{none}|list]
@cindex vector_catch
Vector Catch hardware provides a sort of dedicated breakpoint
for hardware events such as reset, interrupt, and abort.
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 12b68ae..e3c6ca3 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -1061,14 +1061,12 @@ int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
command_t *arm9tdmi_cmd;
retval = arm7_9_register_commands(cmd_ctx);
- arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi",
+ arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9",
NULL, COMMAND_ANY,
- "arm9tdmi specific commands");
+ "arm9 specific commands");
register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch",
handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC,
- "arm9 vector_catch [all|none|reset|undef|swi|pabt|dabt|irq|fiq] - separate vectors to catch by space");
-
-
+ "arm9 vector_catch [all|none|reset|undef|swi|pabt|dabt|irq|fiq] ...");
return retval;
}
-----------------------------------------------------------------------
Summary of changes:
NEWS | 2 ++
TODO | 5 ++---
doc/openocd.texi | 13 ++++---------
src/target/arm9tdmi.c | 8 +++-----
4 files changed, 11 insertions(+), 17 deletions(-)
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From: David B. <dbr...@us...> - 2009-10-25 21:09:35
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via e98817c4636f45b45db4332d2a5fbf36676f2f39 (commit)
via 2a8aa3b7efb590cabd7ee930dbb68fd64e028099 (commit)
from 0b436497e047a13ff3dbae46af0eb67376ea5acf (commit)
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- Log -----------------------------------------------------------------
commit e98817c4636f45b45db4332d2a5fbf36676f2f39
Author: David Brownell <dbr...@us...>
Date: Sun Oct 25 13:07:57 2009 -0700
JTAG: jtag_tap_init() bugfixes
Stop allocating three bytes per IR bit, and cope somewhat better
with IR lengths over 32 bits.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/jtag/core.c b/src/jtag/core.c
index 7c85839..08cfe43 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -1204,20 +1204,29 @@ done:
void jtag_tap_init(jtag_tap_t *tap)
{
+ unsigned ir_len_bits;
+ unsigned ir_len_bytes;
+
assert(0 != tap->ir_length);
- /// @todo fix, this allocates one byte per bit for all three fields!
- tap->expected = malloc(tap->ir_length);
- tap->expected_mask = malloc(tap->ir_length);
- tap->cur_instr = malloc(tap->ir_length);
+ ir_len_bits = tap->ir_length;
+ ir_len_bytes = CEIL(ir_len_bits, 8);
- /// @todo cope sanely with ir_length bigger than 32 bits
- buf_set_u32(tap->expected, 0, tap->ir_length, tap->ir_capture_value);
- buf_set_u32(tap->expected_mask, 0, tap->ir_length, tap->ir_capture_mask);
- buf_set_ones(tap->cur_instr, tap->ir_length);
+ tap->expected = calloc(1, ir_len_bytes);
+ tap->expected_mask = calloc(1, ir_len_bytes);
+ tap->cur_instr = malloc(ir_len_bytes);
+
+ /// @todo cope better with ir_length bigger than 32 bits
+ if (ir_len_bits > 32)
+ ir_len_bits = 32;
- // place TAP in bypass mode
+ buf_set_u32(tap->expected, 0, ir_len_bits, tap->ir_capture_value);
+ buf_set_u32(tap->expected_mask, 0, ir_len_bits, tap->ir_capture_mask);
+
+ // TAP will be in bypass mode after jtag_validate_ircapture()
tap->bypass = 1;
+ buf_set_ones(tap->cur_instr, tap->ir_length);
+
// register the reset callback for the TAP
jtag_register_event_callback(&jtag_reset_callback, tap);
commit 2a8aa3b7efb590cabd7ee930dbb68fd64e028099
Author: David Brownell <dbr...@us...>
Date: Sun Oct 25 13:06:47 2009 -0700
xscale: always reload handler after reset
Remove needless debug handler state.
- "handler_installed" became wrong as soon as the second TRST+SRST
reset was issued ... so the handler was never reloaded after the
reset removed it from the mini-icache.
This fixes the bug where subsequent resets fail on PXA255 (if the
first one even worked, which is uncommon). Other XScale chips
would have problems too; PXA270 seems to have, IXP425 maybe not.
- "handler_running" was never tested; it's pointless.
Plus a related bugfix: invalidate OpenOCD's ARM register cache on reset.
It was no more valid than the XScale's mini-icache. (Though ... such
invalidations might be better done in "SRST asserted" callbacks.)
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 640eb01..ee9d88d 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -890,8 +890,6 @@ static int xscale_arch_state(struct target_s *target)
static int xscale_poll(target_t *target)
{
int retval = ERROR_OK;
- armv4_5_common_t *armv4_5 = target->arch_info;
- xscale_common_t *xscale = armv4_5->arch_info;
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
{
@@ -900,8 +898,6 @@ static int xscale_poll(target_t *target)
{
/* there's data to read from the tx register, we entered debug state */
- xscale->handler_running = 1;
-
target->state = TARGET_HALTED;
/* process debug entry, fetching current mode regs */
@@ -1365,8 +1361,6 @@ static int xscale_resume(struct target_s *target, int current,
LOG_DEBUG("target resumed");
- xscale->handler_running = 1;
-
return ERROR_OK;
}
@@ -1574,7 +1568,17 @@ static int xscale_deassert_reset(target_t *target)
breakpoint = breakpoint->next;
}
- if (!xscale->handler_installed)
+ armv4_5_invalidate_core_regs(target);
+
+ /* FIXME mark hardware watchpoints got unset too. Also,
+ * at least some of the XScale registers are invalid...
+ */
+
+ /*
+ * REVISIT: *assumes* we had a SRST+TRST reset so the mini-icache
+ * contents got invalidated. Safer to force that, so writing new
+ * contents can't ever fail..
+ */
{
uint32_t address;
unsigned buf_cnt;
@@ -1599,10 +1603,6 @@ static int xscale_deassert_reset(target_t *target)
* it's using halt mode (not monitor mode), it runs in
* "Special Debug State" for access to registers, memory,
* coprocessors, trace data, etc.
- *
- * REVISIT: *assumes* we've had a SRST+TRST reset so the
- * mini-icache contents have been invalidated. Safest to
- * force that, so writing new contents is reliable...
*/
address = xscale->handler_address;
for (unsigned binary_size = sizeof xscale_debug_handler - 1;
@@ -1673,10 +1673,6 @@ static int xscale_deassert_reset(target_t *target)
xscale_resume(target, 1, 0x0, 1, 0);
}
}
- else
- {
- jtag_add_reset(0, 0);
- }
return ERROR_OK;
}
@@ -2967,8 +2963,6 @@ static int xscale_init_arch_info(target_t *target,
}
/* the debug handler isn't installed (and thus not running) at this time */
- xscale->handler_installed = 0;
- xscale->handler_running = 0;
xscale->handler_address = 0xfe000800;
/* clear the vectors we keep locally for reference */
diff --git a/src/target/xscale.h b/src/target/xscale.h
index a5d83ee..4b34cf8 100644
--- a/src/target/xscale.h
+++ b/src/target/xscale.h
@@ -86,8 +86,6 @@ typedef struct xscale_common_s
reg_cache_t *reg_cache;
/* current state of the debug handler */
- int handler_installed;
- int handler_running;
uint32_t handler_address;
/* target-endian buffers with exception vectors */
-----------------------------------------------------------------------
Summary of changes:
src/jtag/core.c | 27 ++++++++++++++++++---------
src/target/xscale.c | 28 +++++++++++-----------------
src/target/xscale.h | 2 --
3 files changed, 29 insertions(+), 28 deletions(-)
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Main OpenOCD repository
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From: Øyvind H. <go...@us...> - 2009-10-24 13:06:49
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 0b436497e047a13ff3dbae46af0eb67376ea5acf (commit)
from 75cdc8a260e081752698f374d4cd6e97e84eb6cb (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 0b436497e047a13ff3dbae46af0eb67376ea5acf
Author: Ãyvind Harboe <oyv...@zy...>
Date: Sat Oct 24 13:06:13 2009 +0200
vector_catch and watchpoint TODO items.
diff --git a/TODO b/TODO
index 180a9da..fa9477a 100644
--- a/TODO
+++ b/TODO
@@ -138,6 +138,10 @@ Once the above are completed:
- regression: "reset halt" between 729(works) and 788(fails): @par
https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
- ARM7/9:
+ - clean up "arm9tdmi vector_catch". Should be available for other arm9
+ (e.g. arm926ejs) and some(???) arm7 cores. @par
+https://lists.berlios.de/pipermail/openocd-development/2009-October/011488.html
+https://lists.berlios.de/pipermail/openocd-development/2009-October/011506.html
- add reset option to allow programming embedded ice while srst is asserted.
Some CPUs will gate the JTAG clock when srst is asserted and in this case,
it is necessary to program embedded ice and then assert srst afterwards.
@@ -205,6 +209,8 @@ https://lists.berlios.de/pipermail/openocd-development/2009-July/009206.html
@section thelistdebug Debugger Support
+- add support for masks in watchpoints? @par
+ https://lists.berlios.de/pipermail/openocd-development/2009-October/011507.html
- breakpoints can get lost in some circumstances: @par
https://lists.berlios.de/pipermail/openocd-development/2009-June/008853.html
- integrate Keil AGDI interface to OpenOCD? (submitted by Dario Vecchio)
-----------------------------------------------------------------------
Summary of changes:
TODO | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
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From: David B. <dbr...@us...> - 2009-10-23 21:30:56
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 75cdc8a260e081752698f374d4cd6e97e84eb6cb (commit)
from bfefe85645a51d8e5f94879dcd0321abafdcbf7c (commit)
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- Log -----------------------------------------------------------------
commit 75cdc8a260e081752698f374d4cd6e97e84eb6cb
Author: David Brownell <dbr...@us...>
Date: Fri Oct 23 12:28:03 2009 -0700
arm9tdmi vector_catch: reserved means "don't use"
Bit 5 shouldn't be used. Remove all support for modifying it.
Matches the exception vector table, of course ... more than one
bootloader uses that non-vector to help distinguish valid boot
images from random garbage in flash.
diff --git a/doc/openocd.texi b/doc/openocd.texi
index c9e48bf..6760994 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5460,6 +5460,8 @@ ARMv5TE architecture instead of ARMv4T.
@c 9-june-2009: tried this on arm920t, it didn't work.
@c no-params always lists nothing caught, and that's how it acts.
+@c 23-oct-2009: doesn't work _consistently_ ... as if the ICE
+@c versions have different rules about when they commit writes.
@anchor{arm9tdmi vector_catch}
@deffn Command {arm9tdmi vector_catch} [@option{all}|@option{none}|list]
@@ -5476,7 +5478,7 @@ vector catch hardware to intercept
@option{all} of the hardware vectors,
@option{none} of them,
or a list with one or more of the following:
-@option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt} @option{reserved}
+@option{reset} @option{undef} @option{swi} @option{pabt} @option{dabt}
@option{irq} @option{fiq}.
@end deffn
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index f941922..12b68ae 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -95,7 +95,6 @@ static arm9tdmi_vector_t arm9tdmi_vectors[] =
{"swi", ARM9TDMI_SWI_VECTOR},
{"pabt", ARM9TDMI_PABT_VECTOR},
{"dabt", ARM9TDMI_DABT_VECTOR},
- {"reserved", ARM9TDMI_RESERVED_VECTOR},
{"irq", ARM9TDMI_IRQ_VECTOR},
{"fiq", ARM9TDMI_FIQ_VECTOR},
{0, 0},
@@ -1067,7 +1066,7 @@ int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
"arm9tdmi specific commands");
register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch",
handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC,
- "arm9 vector_catch [all|none|reset|undef|swi|pabt|dabt|reserved|irq|fiq] - separate vectors to catch by space");
+ "arm9 vector_catch [all|none|reset|undef|swi|pabt|dabt|irq|fiq] - separate vectors to catch by space");
diff --git a/src/target/arm9tdmi.h b/src/target/arm9tdmi.h
index 28be9b6..9dfa886 100644
--- a/src/target/arm9tdmi.h
+++ b/src/target/arm9tdmi.h
@@ -47,7 +47,7 @@ enum arm9tdmi_vector
ARM9TDMI_SWI_VECTOR = 0x04,
ARM9TDMI_PABT_VECTOR = 0x08,
ARM9TDMI_DABT_VECTOR = 0x10,
- ARM9TDMI_RESERVED_VECTOR = 0x20,
+ /* BIT(5) reserved -- must be zero */
ARM9TDMI_IRQ_VECTOR = 0x40,
ARM9TDMI_FIQ_VECTOR = 0x80,
};
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 4 +++-
src/target/arm9tdmi.c | 3 +--
src/target/arm9tdmi.h | 2 +-
3 files changed, 5 insertions(+), 4 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: Øyvind H. <go...@us...> - 2009-10-23 16:18:54
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via bfefe85645a51d8e5f94879dcd0321abafdcbf7c (commit)
from cb854323c999f79b75b57d476f7625933f9ebe2c (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit bfefe85645a51d8e5f94879dcd0321abafdcbf7c
Author: Ãyvind Harboe <oyv...@zy...>
Date: Fri Oct 23 16:02:42 2009 +0200
Improve help for arm9 vector_catch.
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 8ebb91d..f941922 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -1067,7 +1067,9 @@ int arm9tdmi_register_commands(struct command_context_s *cmd_ctx)
"arm9tdmi specific commands");
register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch",
handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC,
- "catch arm9 vectors ['all'|'none'|'<vec1 vec2 ...>']");
+ "arm9 vector_catch [all|none|reset|undef|swi|pabt|dabt|reserved|irq|fiq] - separate vectors to catch by space");
+
+
return retval;
}
-----------------------------------------------------------------------
Summary of changes:
src/target/arm9tdmi.c | 4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
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--
Main OpenOCD repository
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From: Øyvind H. <go...@us...> - 2009-10-23 13:09:47
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via cb854323c999f79b75b57d476f7625933f9ebe2c (commit)
from 0a1356c9ccff42e2c41af3a3c0ae8b1330aa970b (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit cb854323c999f79b75b57d476f7625933f9ebe2c
Author: Ãyvind Harboe <oyv...@zy...>
Date: Fri Oct 23 13:09:16 2009 +0200
Remove debug output that could cause compile warnings.
diff --git a/src/target/target.c b/src/target/target.c
index 336a7f7..99b3d18 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -4824,8 +4824,6 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
value = 0;
- LOG_DEBUG("%d %d %d %d %d %d", cpnum, op1, op2, CRn, CRm, value);
-
if (argc == 7)
{
e = Jim_GetLong(interp, argv[6], &l);
-----------------------------------------------------------------------
Summary of changes:
src/target/target.c | 2 --
1 files changed, 0 insertions(+), 2 deletions(-)
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Main OpenOCD repository
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From: Øyvind H. <go...@us...> - 2009-10-23 12:42:51
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 0a1356c9ccff42e2c41af3a3c0ae8b1330aa970b (commit)
via 18aad44f7121a4fa76d53a4ae653b047cd9ad916 (commit)
from 79f71fad58f3cd1a59142b65c3b79b145943b6e6 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 0a1356c9ccff42e2c41af3a3c0ae8b1330aa970b
Author: Ãyvind Harboe <oyv...@zy...>
Date: Fri Oct 23 12:38:19 2009 +0200
mcr/mrc interface work. Implemented for arm926ejs and arm720t. mcr/mrc commands added.
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 71440eb..6ed66cd 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -2,6 +2,9 @@
* Copyright (C) 2005 by Dominic Rath *
* Dom...@gm... *
* *
+ * Copyright (C) 2009 by Ãyvind Harboe *
+ * oyv...@zy... *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
@@ -46,6 +49,9 @@ int arm720t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t
int arm720t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int arm720t_soft_reset_halt(struct target_s *target);
+static int arm720t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
+static int arm720t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
+
target_type_t arm720t_target =
{
.name = "arm720t",
@@ -82,7 +88,9 @@ target_type_t arm720t_target =
.target_create = arm720t_target_create,
.init_target = arm720t_init_target,
.examine = arm7tdmi_examine,
- .quit = arm720t_quit
+ .quit = arm720t_quit,
+ .mrc = arm720t_mrc,
+ .mcr = arm720t_mcr,
};
@@ -574,3 +582,29 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
return ERROR_OK;
}
+
+
+static int arm720t_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+{
+ if (cpnum!=15)
+ {
+ LOG_ERROR("Only cp15 is supported");
+ return ERROR_FAIL;
+ }
+
+ return arm720t_read_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value);
+
+}
+
+static int arm720t_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+{
+ if (cpnum!=15)
+ {
+ LOG_ERROR("Only cp15 is supported");
+ return ERROR_FAIL;
+ }
+
+ return arm720t_write_cp15(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), value);
+}
+
+
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 9c9628a..9061174 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -2,7 +2,7 @@
* Copyright (C) 2007 by Dominic Rath *
* Dom...@gm... *
* *
- * Copyright (C) 2009 by Ãyvind Harboe *
+ * Copyright (C) 2007,2008,2009 by Ãyvind Harboe *
* oyv...@zy... *
* *
* This program is free software; you can redistribute it and/or modify *
@@ -35,7 +35,6 @@
/* cli handling */
int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
@@ -52,6 +51,29 @@ int arm926ejs_write_phys_memory(struct target_s *target, uint32_t address, uint3
static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical);
static int arm926ejs_mmu(struct target_s *target, int *enabled);
+int arm926ejs_cp15_read(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
+int arm926ejs_cp15_write(target_t *target, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
+
+static int arm926ejs_mrc(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+{
+ if (cpnum!=15)
+ {
+ LOG_ERROR("Only cp15 is supported");
+ return ERROR_FAIL;
+ }
+ return arm926ejs_cp15_read(target, op1, op2, CRn, CRm, value);
+}
+
+static int arm926ejs_mcr(target_t *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+{
+ if (cpnum!=15)
+ {
+ LOG_ERROR("Only cp15 is supported");
+ return ERROR_FAIL;
+ }
+ return arm926ejs_cp15_write(target, op1, op2, CRn, CRm, value);
+}
+
target_type_t arm926ejs_target =
{
.name = "arm926ejs",
@@ -94,6 +116,8 @@ target_type_t arm926ejs_target =
.read_phys_memory = arm926ejs_read_phys_memory,
.write_phys_memory = arm926ejs_write_phys_memory,
+ .mrc = arm926ejs_mrc,
+ .mcr = arm926ejs_mcr,
};
int arm926ejs_catch_broken_irscan(uint8_t *captured, void *priv, scan_field_t *field)
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 7ea3826..80f28db 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -5,6 +5,9 @@
* Copyright (C) 2008 by Spencer Oliver *
* sp...@sp... *
* *
+ * Copyright (C) 2009 by Ãyvind Harboe *
+ * oyv...@zy... *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
@@ -315,4 +318,19 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
*/
#define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
+/* build basic mrc/mcr opcode */
+
+static inline uint32_t mrc_opcode(int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
+{
+ uint32_t t = 0;
+ t|=op1<<21;
+ t|=op2<<5;
+ t|=CRn<<16;
+ t|=CRm<<0;
+ return t;
+}
+
+
+
+
#endif /* ARMV4_5_H */
diff --git a/src/target/target.c b/src/target/target.c
index eb93fb7..336a7f7 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -69,6 +69,7 @@ static int handle_fast_load_image_command(struct command_context_s *cmd_ctx, cha
static int handle_fast_load_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
static int jim_array2mem(Jim_Interp *interp, int argc, Jim_Obj *const *argv);
+static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv);
static int jim_mem2array(Jim_Interp *interp, int argc, Jim_Obj *const *argv);
static int jim_target(Jim_Interp *interp, int argc, Jim_Obj *const *argv);
@@ -687,6 +688,60 @@ void target_reset_examined(struct target_s *target)
}
+
+static int default_mrc(struct target_s *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+{
+ LOG_ERROR("Not implemented");
+ return ERROR_FAIL;
+}
+
+static int default_mcr(struct target_s *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+{
+ LOG_ERROR("Not implemented");
+ return ERROR_FAIL;
+}
+
+static int arm_cp_check(struct target_s *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm)
+{
+ /* basic check */
+ if (!target_was_examined(target))
+ {
+ LOG_ERROR("Target not examined yet");
+ return ERROR_FAIL;
+ }
+
+ if ((cpnum <0) || (cpnum > 15))
+ {
+ LOG_ERROR("Illegal co-processor %d", cpnum);
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+int target_mrc(struct target_s *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value)
+{
+ int retval;
+
+ retval = arm_cp_check(target, cpnum, op1, op2, CRn, CRm);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return target->type->mrc(target, cpnum, op1, op2, CRn, CRm, value);
+}
+
+int target_mcr(struct target_s *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+{
+ int retval;
+
+ retval = arm_cp_check(target, cpnum, op1, op2, CRn, CRm);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return target->type->mcr(target, cpnum, op1, op2, CRn, CRm, value);
+}
+
+
int target_init(struct command_context_s *cmd_ctx)
{
target_t *target = all_targets;
@@ -722,6 +777,17 @@ int target_init(struct command_context_s *cmd_ctx)
target->type->write_phys_memory = target->type->write_memory;
}
+ if (target->type->mcr == NULL)
+ {
+ target->type->mcr = default_mcr;
+ }
+
+ if (target->type->mrc == NULL)
+ {
+ target->type->mrc = default_mrc;
+ }
+
+
/* a non-invasive way(in terms of patches) to add some code that
* runs before the type->write/read_memory implementation
*/
@@ -1538,6 +1604,9 @@ int target_register_user_commands(struct command_context_s *cmd_ctx)
register_jim(cmd_ctx, "ocd_mem2array", jim_mem2array, "read memory and return as a TCL array for script processing <ARRAYNAME> <WIDTH = 32/16/8> <ADDRESS> <COUNT>");
register_jim(cmd_ctx, "ocd_array2mem", jim_array2mem, "convert a TCL array to memory locations and write the values <ARRAYNAME> <WIDTH = 32/16/8> <ADDRESS> <COUNT>");
+ register_jim(cmd_ctx, "mrc", jim_mcrmrc, "read coprocessor <cpnum> <op1> <op2> <CRn> <CRm>");
+ register_jim(cmd_ctx, "mcr", jim_mcrmrc, "write coprocessor <cpnum> <op1> <op2> <CRn> <CRm> <value>");
+
register_command(cmd_ctx, NULL, "fast_load_image", handle_fast_load_image_command, COMMAND_ANY,
"same args as load_image, image stored in memory - mainly for profiling purposes");
@@ -3355,7 +3424,6 @@ static int jim_array2mem(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
return target_array2mem(interp,target, argc-1, argv + 1);
}
-
static int target_array2mem(Jim_Interp *interp, target_t *target, int argc, Jim_Obj *const *argv)
{
long l;
@@ -4693,10 +4761,90 @@ static int handle_fast_load_command(struct command_context_s *cmd_ctx, char *cmd
return retval;
}
+static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
+{
+ command_context_t *context;
+ target_t *target;
+ int retval;
-/*
- * Local Variables:
- * c-basic-offset: 4
- * tab-width: 4
- * End:
- */
+ context = Jim_GetAssocData(interp, "context");
+ if (context == NULL) {
+ LOG_ERROR("array2mem: no command context");
+ return JIM_ERR;
+ }
+ target = get_current_target(context);
+ if (target == NULL) {
+ LOG_ERROR("array2mem: no current target");
+ return JIM_ERR;
+ }
+
+ if ((argc < 6) || (argc > 7))
+ {
+ return JIM_ERR;
+ }
+
+ int cpnum;
+ uint32_t op1;
+ uint32_t op2;
+ uint32_t CRn;
+ uint32_t CRm;
+ uint32_t value;
+
+ int e;
+ long l;
+ e = Jim_GetLong(interp, argv[1], &l);
+ if (e != JIM_OK) {
+ return e;
+ }
+ cpnum = l;
+
+ e = Jim_GetLong(interp, argv[2], &l);
+ if (e != JIM_OK) {
+ return e;
+ }
+ op1 = l;
+
+ e = Jim_GetLong(interp, argv[3], &l);
+ if (e != JIM_OK) {
+ return e;
+ }
+ op2 = l;
+
+ e = Jim_GetLong(interp, argv[4], &l);
+ if (e != JIM_OK) {
+ return e;
+ }
+ CRn = l;
+
+ e = Jim_GetLong(interp, argv[5], &l);
+ if (e != JIM_OK) {
+ return e;
+ }
+ CRm = l;
+
+ value = 0;
+
+ LOG_DEBUG("%d %d %d %d %d %d", cpnum, op1, op2, CRn, CRm, value);
+
+ if (argc == 7)
+ {
+ e = Jim_GetLong(interp, argv[6], &l);
+ if (e != JIM_OK) {
+ return e;
+ }
+ value = l;
+
+ retval = target_mcr(target, cpnum, op1, op2, CRn, CRm, value);
+ if (retval != ERROR_OK)
+ return JIM_ERR;
+ } else
+ {
+ retval = target_mrc(target, cpnum, op1, op2, CRn, CRm, &value);
+ if (retval != ERROR_OK)
+ return JIM_ERR;
+
+ Jim_SetResult(interp, Jim_NewIntObj(interp, value));
+ }
+
+ return JIM_OK;
+}
diff --git a/src/target/target.h b/src/target/target.h
index 19d8013..ef57837 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -2,7 +2,7 @@
* Copyright (C) 2005 by Dominic Rath *
* Dom...@gm... *
* *
- * Copyright (C) 2007,2008 Ãyvind Harboe *
+ * Copyright (C) 2007,2008,2009 Ãyvind Harboe *
* oyv...@zy... *
* *
* Copyright (C) 2008 by Spencer Oliver *
diff --git a/src/target/target_type.h b/src/target/target_type.h
index aab4321..83baa25 100644
--- a/src/target/target_type.h
+++ b/src/target/target_type.h
@@ -2,7 +2,7 @@
* Copyright (C) 2005 by Dominic Rath *
* Dom...@gm... *
* *
- * Copyright (C) 2007,2008 Ãyvind Harboe *
+ * Copyright (C) 2007,2008,2009 Ãyvind Harboe *
* oyv...@zy... *
* *
* Copyright (C) 2008 by Spencer Oliver *
@@ -202,6 +202,11 @@ struct target_type_s
int (*mmu)(struct target_s *target, int *enabled);
+ /* Read coprocessor - arm specific. Default implementation returns error. */
+ int (*mrc)(struct target_s *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t *value);
+
+ /* Write coprocessor. Default implementation returns error. */
+ int (*mcr)(struct target_s *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value);
};
#endif // TARGET_TYPE_H
commit 18aad44f7121a4fa76d53a4ae653b047cd9ad916
Author: Ãyvind Harboe <oyv...@zy...>
Date: Fri Oct 23 09:54:43 2009 +0200
Embedded ICE version is now dumped with debug_level 1
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 39f87c7..9909084 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -2,7 +2,7 @@
* Copyright (C) 2005 by Dominic Rath *
* Dom...@gm... *
* *
- * Copyright (C) 2007,2008 Ãyvind Harboe *
+ * Copyright (C) 2007,2008,2009 Ãyvind Harboe *
* oyv...@zy... *
* *
* Copyright (C) 2008 by Spencer Oliver *
@@ -203,7 +203,7 @@ reg_cache_t* embeddedice_build_reg_cache(target_t *target, arm7_9_common_t *arm7
}
eice_version = buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 28, 4);
- LOG_DEBUG("Embedded ICE version %d", eice_version);
+ LOG_INFO("Embedded ICE version %d", eice_version);
switch (eice_version)
{
-----------------------------------------------------------------------
Summary of changes:
src/target/arm720t.c | 36 ++++++++++-
src/target/arm926ejs.c | 28 +++++++-
src/target/armv4_5.h | 18 +++++
src/target/embeddedice.c | 4 +-
src/target/target.c | 162 ++++++++++++++++++++++++++++++++++++++++++++--
src/target/target.h | 2 +-
src/target/target_type.h | 7 ++-
7 files changed, 243 insertions(+), 14 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-10-23 10:02:58
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 79f71fad58f3cd1a59142b65c3b79b145943b6e6 (commit)
via 814183a5c41cad14b83c29c9473084e6d1a11d9b (commit)
from 517e812de3782a6b592cb69416d1327a9b94ac9f (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 79f71fad58f3cd1a59142b65c3b79b145943b6e6
Author: David Brownell <dbr...@us...>
Date: Fri Oct 23 01:02:22 2009 -0700
jtag: clean up TAP state name handling
Some cosmetic cleanup, and switch to a single table mapping
between state names and symbols (vs two routines which only
share that state with difficulty).
Get rid of TAP_NUM_STATES, and some related knowledge about
how TAP numbers are assigned. Later on, this will help us
get rid of more such hardwired knowlege.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/jtag/interface.c b/src/jtag/interface.c
index fcdb8ee..e475b48 100644
--- a/src/jtag/interface.c
+++ b/src/jtag/interface.c
@@ -73,20 +73,23 @@ tap_state_t tap_get_end_state()
int tap_move_ndx(tap_state_t astate)
{
- /* given a stable state, return the index into the tms_seqs[] array within tap_get_tms_path() */
+ /* given a stable state, return the index into the tms_seqs[]
+ * array within tap_get_tms_path()
+ */
int ndx;
switch (astate)
{
case TAP_RESET: ndx = 0; break;
+ case TAP_IDLE: ndx = 1; break;
case TAP_DRSHIFT: ndx = 2; break;
case TAP_DRPAUSE: ndx = 3; break;
- case TAP_IDLE: ndx = 1; break;
case TAP_IRSHIFT: ndx = 4; break;
case TAP_IRPAUSE: ndx = 5; break;
default:
- LOG_ERROR("fatal: unstable state \"%s\" used in tap_move_ndx()", tap_state_name(astate));
+ LOG_ERROR("FATAL: unstable state \"%s\" in tap_move_ndx()",
+ tap_state_name(astate));
exit(1);
}
@@ -95,12 +98,7 @@ int tap_move_ndx(tap_state_t astate)
/* tap_move[i][j]: tap movement command to go from state i to state j
- * 0: Test-Logic-Reset
- * 1: Run-Test/Idle
- * 2: Shift-DR
- * 3: Pause-DR
- * 4: Shift-IR
- * 5: Pause-IR
+ * encodings of i and j are what tap_move_ndx() reports.
*
* DRSHIFT->DRSHIFT and IRSHIFT->IRSHIFT have to be caught in interface specific code
*/
@@ -108,7 +106,6 @@ struct tms_sequences
{
uint8_t bits;
uint8_t bit_count;
-
};
/*
@@ -333,47 +330,54 @@ tap_state_t tap_state_transition(tap_state_t cur_state, bool tms)
return new_state;
}
-const char* tap_state_name(tap_state_t state)
+
+/* NOTE: do not change these state names. They're documented,
+ * and we rely on them to match SVF input (except for "RUN/IDLE").
+ */
+static const struct name_mapping {
+ enum tap_state symbol;
+ const char *name;
+} tap_name_mapping[] = {
+ { TAP_RESET, "RESET", },
+ { TAP_IDLE, "RUN/IDLE", },
+ { TAP_DRSELECT, "DRSELECT", },
+ { TAP_DRCAPTURE,"DRCAPTURE", },
+ { TAP_DRSHIFT, "DRSHIFT", },
+ { TAP_DREXIT1, "DREXIT1", },
+ { TAP_DRPAUSE, "DRPAUSE", },
+ { TAP_DREXIT2, "DREXIT2", },
+ { TAP_DRUPDATE, "DRUPDATE", },
+ { TAP_IRSELECT, "IRSELECT", },
+ { TAP_IRCAPTURE,"IRCAPTURE", },
+ { TAP_IRSHIFT, "IRSHIFT", },
+ { TAP_IREXIT1, "IREXIT1", },
+ { TAP_IRPAUSE, "IRPAUSE", },
+ { TAP_IREXIT2, "IREXIT2", },
+ { TAP_IRUPDATE, "IRUPDATE", },
+
+ /* only for input: accept standard SVF name */
+ { TAP_IDLE, "IDLE", },
+};
+
+const char *tap_state_name(tap_state_t state)
{
- const char* ret;
+ unsigned i;
- switch (state)
- {
- case TAP_RESET: ret = "RESET"; break;
- case TAP_IDLE: ret = "RUN/IDLE"; break;
- case TAP_DRSELECT: ret = "DRSELECT"; break;
- case TAP_DRCAPTURE: ret = "DRCAPTURE"; break;
- case TAP_DRSHIFT: ret = "DRSHIFT"; break;
- case TAP_DREXIT1: ret = "DREXIT1"; break;
- case TAP_DRPAUSE: ret = "DRPAUSE"; break;
- case TAP_DREXIT2: ret = "DREXIT2"; break;
- case TAP_DRUPDATE: ret = "DRUPDATE"; break;
- case TAP_IRSELECT: ret = "IRSELECT"; break;
- case TAP_IRCAPTURE: ret = "IRCAPTURE"; break;
- case TAP_IRSHIFT: ret = "IRSHIFT"; break;
- case TAP_IREXIT1: ret = "IREXIT1"; break;
- case TAP_IRPAUSE: ret = "IRPAUSE"; break;
- case TAP_IREXIT2: ret = "IREXIT2"; break;
- case TAP_IRUPDATE: ret = "IRUPDATE"; break;
- default: ret = "???";
+ for (i = 0; i < DIM(tap_name_mapping); i++) {
+ if (tap_name_mapping[i].symbol == state)
+ return tap_name_mapping[i].name;
}
-
- return ret;
+ return "???";
}
tap_state_t tap_state_by_name(const char *name)
{
- tap_state_t x;
-
- /* standard SVF name is "IDLE" */
- if (0 == strcasecmp(name, "IDLE"))
- return TAP_IDLE;
+ unsigned i;
- for (x = 0 ; x < TAP_NUM_STATES ; x++) {
+ for (i = 0; i < DIM(tap_name_mapping); i++) {
/* be nice to the human */
- if (0 == strcasecmp(name, tap_state_name(x))) {
- return x;
- }
+ if (strcasecmp(name, tap_name_mapping[i].name) == 0)
+ return tap_name_mapping[i].symbol;
}
/* not found */
return TAP_INVALID;
diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h
index 1dae00f..ca09f92 100644
--- a/src/jtag/jtag.h
+++ b/src/jtag/jtag.h
@@ -57,13 +57,17 @@
*
* These definitions were gleaned from the ARM7TDMI-S Technical
* Reference Manual and validated against several other ARM core
- * technical manuals. tap_get_tms_path() is sensitive to this numbering
- * and ordering of the TAP states; furthermore, some interfaces require
- * specific numbers be used, as they are handed-off directly to their
- * hardware implementations.
+ * technical manuals.
+ *
+ * FIXME some interfaces require specific numbers be used, as they
+ * are handed-off directly to their hardware implementations.
+ * Fix those drivers to map as appropriate ... then pick some
+ * sane set of numbers here (where 0/uninitialized == INVALID).
*/
typedef enum tap_state
{
+ TAP_INVALID = -1,
+
#if BUILD_ZY1000
/* These are the old numbers. Leave as-is for now... */
TAP_RESET = 0, TAP_IDLE = 8,
@@ -72,7 +76,6 @@ typedef enum tap_state
TAP_IRSELECT = 9, TAP_IRCAPTURE = 10, TAP_IRSHIFT = 11, TAP_IREXIT1 = 12,
TAP_IRPAUSE = 13, TAP_IREXIT2 = 14, TAP_IRUPDATE = 15,
- TAP_NUM_STATES = 16, TAP_INVALID = -1,
#else
/* Proper ARM recommended numbers */
TAP_DREXIT2 = 0x0,
@@ -92,9 +95,6 @@ typedef enum tap_state
TAP_IRCAPTURE = 0xe,
TAP_RESET = 0x0f,
- TAP_NUM_STATES = 0x10,
-
- TAP_INVALID = -1,
#endif
} tap_state_t;
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index e080279..6a6e3ae 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -1248,6 +1248,8 @@ static int handle_runtest_command(struct command_context_s *cmd_ctx,
* For "irscan" or "drscan" commands, the "end" (really, "next") state
* should be stable ... and *NOT* a shift state, otherwise free-running
* jtag clocks could change the values latched by the update state.
+ * Not surprisingly, this is the same constraint as SVF; the "irscan"
+ * and "drscan" commands are a write-only subset of what SVF provides.
*/
static bool scan_is_safe(tap_state_t state)
{
@@ -1285,25 +1287,14 @@ static int handle_irscan_command(struct command_context_s *cmd_ctx, char *cmd, c
if (argc >= 4) {
/* have at least one pair of numbers. */
/* is last pair the magic text? */
- if (0 == strcmp("-endstate", args[ argc - 2 ])) {
- const char *cpA;
- const char *cpS;
- cpA = args[ argc-1 ];
- for (endstate = 0 ; endstate < TAP_NUM_STATES ; endstate++) {
- cpS = tap_state_name(endstate);
- if (0 == strcmp(cpA, cpS)) {
- break;
- }
- }
- if (endstate >= TAP_NUM_STATES) {
+ if (strcmp("-endstate", args[argc - 2]) == 0) {
+ endstate = tap_state_by_name(args[argc - 1]);
+ if (endstate == TAP_INVALID)
return ERROR_COMMAND_SYNTAX_ERROR;
- } else {
- if (!scan_is_safe(endstate))
- LOG_WARNING("irscan with unsafe "
- "endstate \"%s\"", cpA);
- /* found - remove the last 2 args */
- argc -= 2;
- }
+ if (!scan_is_safe(endstate))
+ LOG_WARNING("unstable irscan endstate \"%s\"",
+ args[argc - 1]);
+ argc -= 2;
}
}
commit 814183a5c41cad14b83c29c9473084e6d1a11d9b
Author: David Brownell <dbr...@us...>
Date: Fri Oct 23 01:00:32 2009 -0700
SVF: clean up, mostly for TAP state name handling
- Use the name mappings all the other code uses:
+ name-to-state ... needed to add one special case
+ state-to-name
- Improve various diagnostics:
+ don't complain about a "valid" state when the issue
is actually that it must be "stable"
+ say which command was affected
- Misc:
+ make more private data and code be static
+ use public DIM() not private dimof()
+ shorten the affected lines
Re the mappings, this means we're more generous in inputs we
accept, since case won't matter. Also our output diagnostics
will be a smidgeon more informative, saying "RUN/IDLE" not
just "IDLE" (emphasizing that there can be side effects).
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/TODO b/TODO
index 0d88812..180a9da 100644
--- a/TODO
+++ b/TODO
@@ -46,7 +46,6 @@ This section list issues that need to be resolved in the JTAG layer.
The following tasks have been suggested for cleaning up the JTAG layer:
- use tap_set_state everywhere to allow logging TAP state transitions
-- rename other tap_states to use standard JTAG names (suggested by ML)
- Encapsulate cmd_queue_cur_state and related varaible handling.
- add slick 32 bit versions of jtag_add_xxx_scan() that avoids
buf_set_u32() calls and other evidence of poor impedance match between
diff --git a/src/jtag/interface.c b/src/jtag/interface.c
index e83a772..fcdb8ee 100644
--- a/src/jtag/interface.c
+++ b/src/jtag/interface.c
@@ -365,6 +365,10 @@ tap_state_t tap_state_by_name(const char *name)
{
tap_state_t x;
+ /* standard SVF name is "IDLE" */
+ if (0 == strcasecmp(name, "IDLE"))
+ return TAP_IDLE;
+
for (x = 0 ; x < TAP_NUM_STATES ; x++) {
/* be nice to the human */
if (0 == strcasecmp(name, tap_state_name(x))) {
diff --git a/src/jtag/interface.h b/src/jtag/interface.h
index 899f163..afe2108 100644
--- a/src/jtag/interface.h
+++ b/src/jtag/interface.h
@@ -160,9 +160,6 @@ bool tap_is_state_stable(tap_state_t astate);
*/
tap_state_t tap_state_transition(tap_state_t current_state, bool tms);
-/// Provides user-friendly name lookup of TAP states.
-tap_state_t tap_state_by_name(const char *name);
-
/// Allow switching between old and new TMS tables. @see tap_get_tms_path
void tap_use_new_tms_table(bool use_new);
/// @returns True if new TMS table is active; false otherwise.
diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h
index 7253c3e..1dae00f 100644
--- a/src/jtag/jtag.h
+++ b/src/jtag/jtag.h
@@ -102,7 +102,10 @@ typedef enum tap_state
* Function tap_state_name
* Returns a string suitable for display representing the JTAG tap_state
*/
-const char* tap_state_name(tap_state_t state);
+const char *tap_state_name(tap_state_t state);
+
+/// Provides user-friendly name lookup of TAP states.
+tap_state_t tap_state_by_name(const char *name);
/// The current TAP state of the pending JTAG command queue.
extern tap_state_t cmd_queue_cur_state;
diff --git a/src/svf/svf.c b/src/svf/svf.c
index dfbbde4..dec4b19 100644
--- a/src/svf/svf.c
+++ b/src/svf/svf.c
@@ -55,7 +55,7 @@ typedef enum
TRST,
}svf_command_t;
-const char *svf_command_name[14] =
+static const char *svf_command_name[14] =
{
"ENDDR",
"ENDIR",
@@ -81,7 +81,7 @@ typedef enum
TRST_ABSENT
}trst_mode_t;
-const char *svf_trst_mode_name[4] =
+static const char *svf_trst_mode_name[4] =
{
"ON",
"OFF",
@@ -136,7 +136,6 @@ static const svf_statemove_t svf_statemoves[] =
{TAP_IRPAUSE, TAP_IRPAUSE, 8, {TAP_IRPAUSE, TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IREXIT1, TAP_IRPAUSE}}
};
-char *svf_tap_state_name[TAP_NUM_STATES];
#define XXR_TDI (1 << 0)
#define XXR_TDO (1 << 1)
@@ -169,8 +168,8 @@ typedef struct
svf_xxr_para_t sdr_para;
}svf_para_t;
-svf_para_t svf_para;
-const svf_para_t svf_para_init =
+static svf_para_t svf_para;
+static const svf_para_t svf_para_init =
{
// frequency, ir_end_state, dr_end_state, runtest_run_state, runtest_end_state, trst_mode
0, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TRST_Z,
@@ -207,8 +206,6 @@ typedef struct
static svf_check_tdo_para_t *svf_check_tdo_para = NULL;
static int svf_check_tdo_para_index = 0;
-#define dimof(a) (sizeof(a) / sizeof((a)[0]))
-
static int svf_read_command_from_file(int fd);
static int svf_check_tdo(void);
static int svf_add_check_para(uint8_t enabled, int buffer_offset, int bit_len);
@@ -236,7 +233,7 @@ int svf_register_commands(struct command_context_s *cmd_ctx)
return ERROR_OK;
}
-void svf_free_xxd_para(svf_xxr_para_t *para)
+static void svf_free_xxd_para(svf_xxr_para_t *para)
{
if (NULL != para)
{
@@ -263,7 +260,7 @@ void svf_free_xxd_para(svf_xxr_para_t *para)
}
}
-unsigned svf_get_mask_u32(int bitlen)
+static unsigned svf_get_mask_u32(int bitlen)
{
uint32_t bitmask;
@@ -283,34 +280,6 @@ unsigned svf_get_mask_u32(int bitlen)
return bitmask;
}
-static const char* tap_state_svf_name(tap_state_t state)
-{
- const char* ret;
-
- switch (state)
- {
- case TAP_RESET: ret = "RESET"; break;
- case TAP_IDLE: ret = "IDLE"; break;
- case TAP_DRSELECT: ret = "DRSELECT"; break;
- case TAP_DRCAPTURE: ret = "DRCAPTURE"; break;
- case TAP_DRSHIFT: ret = "DRSHIFT"; break;
- case TAP_DREXIT1: ret = "DREXIT1"; break;
- case TAP_DRPAUSE: ret = "DRPAUSE"; break;
- case TAP_DREXIT2: ret = "DREXIT2"; break;
- case TAP_DRUPDATE: ret = "DRUPDATE"; break;
- case TAP_IRSELECT: ret = "IRSELECT"; break;
- case TAP_IRCAPTURE: ret = "IRCAPTURE"; break;
- case TAP_IRSHIFT: ret = "IRSHIFT"; break;
- case TAP_IREXIT1: ret = "IREXIT1"; break;
- case TAP_IRPAUSE: ret = "IRPAUSE"; break;
- case TAP_IREXIT2: ret = "IREXIT2"; break;
- case TAP_IRUPDATE: ret = "IRUPDATE"; break;
- default: ret = "???"; break;
- }
-
- return ret;
-}
-
int svf_add_statemove(tap_state_t state_to)
{
tap_state_t state_from = cmd_queue_cur_state;
@@ -322,7 +291,7 @@ int svf_add_statemove(tap_state_t state_to)
return ERROR_OK;
}
- for (index = 0; index < dimof(svf_statemoves); index++)
+ for (index = 0; index < DIM(svf_statemoves); index++)
{
if ((svf_statemoves[index].from == state_from)
&& (svf_statemoves[index].to == state_to))
@@ -337,7 +306,7 @@ int svf_add_statemove(tap_state_t state_to)
return ERROR_OK;
}
}
- LOG_ERROR("SVF: can not move to %s", tap_state_svf_name(state_to));
+ LOG_ERROR("SVF: can not move to %s", tap_state_name(state_to));
return ERROR_FAIL;
}
@@ -426,10 +395,6 @@ static int handle_svf_command(struct command_context_s *cmd_ctx, char *cmd, char
svf_buffer_size = 2 * SVF_MAX_BUFFER_SIZE_TO_COMMIT;
memcpy(&svf_para, &svf_para_init, sizeof(svf_para));
- for (i = 0; i < (int)dimof(svf_tap_state_name); i++)
- {
- svf_tap_state_name[i] = (char *)tap_state_svf_name(i);
- }
// TAP_RESET
jtag_add_tlr();
@@ -625,11 +590,6 @@ bool svf_tap_state_is_stable(tap_state_t state)
|| (TAP_DRPAUSE == state) || (TAP_IRPAUSE == state);
}
-static int svf_tap_state_is_valid(tap_state_t state)
-{
- return state >= 0 && state < TAP_NUM_STATES;
-}
-
static int svf_find_string_in_array(char *str, char **strs, int num_of_element)
{
int i;
@@ -823,7 +783,12 @@ static int svf_run_command(struct command_context_s *cmd_ctx, char *cmd_str)
return ERROR_FAIL;
}
- command = svf_find_string_in_array(argus[0], (char **)svf_command_name, dimof(svf_command_name));
+ /* NOTE: we're a bit loose here, because we ignore case in
+ * TAP state names (instead of insisting on uppercase).
+ */
+
+ command = svf_find_string_in_array(argus[0],
+ (char **)svf_command_name, DIM(svf_command_name));
switch (command)
{
case ENDDR:
@@ -833,23 +798,28 @@ static int svf_run_command(struct command_context_s *cmd_ctx, char *cmd_str)
LOG_ERROR("invalid parameter of %s", argus[0]);
return ERROR_FAIL;
}
- i_tmp = svf_find_string_in_array(argus[1], (char **)svf_tap_state_name, dimof(svf_tap_state_name));
+
+ i_tmp = tap_state_by_name(argus[1]);
+
if (svf_tap_state_is_stable(i_tmp))
{
if (command == ENDIR)
{
svf_para.ir_end_state = i_tmp;
- LOG_DEBUG("\tir_end_state = %s", svf_tap_state_name[svf_para.ir_end_state]);
+ LOG_DEBUG("\tIR end_state = %s",
+ tap_state_name(i_tmp));
}
else
{
svf_para.dr_end_state = i_tmp;
- LOG_DEBUG("\tdr_end_state = %s", svf_tap_state_name[svf_para.dr_end_state]);
+ LOG_DEBUG("\tDR end_state = %s",
+ tap_state_name(i_tmp));
}
}
else
{
- LOG_ERROR("%s is not valid state", argus[1]);
+ LOG_ERROR("%s: %s is not a stable state",
+ argus[0], argus[1]);
return ERROR_FAIL;
}
break;
@@ -1203,25 +1173,31 @@ static int svf_run_command(struct command_context_s *cmd_ctx, char *cmd_str)
min_time = 0;
max_time = 0;
i = 1;
+
// run_state
- i_tmp = svf_find_string_in_array(argus[i], (char **)svf_tap_state_name, dimof(svf_tap_state_name));
- if (svf_tap_state_is_valid(i_tmp))
+ i_tmp = tap_state_by_name(argus[i]);
+ if (i_tmp != TAP_INVALID)
{
if (svf_tap_state_is_stable(i_tmp))
{
svf_para.runtest_run_state = i_tmp;
- // When a run_state is specified, the new run_state becomes the default end_state
+ /* When a run_state is specified, the new
+ * run_state becomes the default end_state.
+ */
svf_para.runtest_end_state = i_tmp;
- LOG_DEBUG("\trun_state = %s", svf_tap_state_name[svf_para.runtest_run_state]);
+ LOG_DEBUG("\trun_state = %s",
+ tap_state_name(i_tmp));
i++;
}
else
{
- LOG_ERROR("%s is not valid state", svf_tap_state_name[i_tmp]);
+ LOG_ERROR("%s: %s is not a stable state",
+ argus[0], tap_state_name(i_tmp));
return ERROR_FAIL;
}
}
+
// run_count run_clk
if (((i + 2) <= num_of_argu) && strcmp(argus[i + 1], "SEC"))
{
@@ -1255,15 +1231,18 @@ static int svf_run_command(struct command_context_s *cmd_ctx, char *cmd_str)
// ENDSTATE end_state
if (((i + 2) <= num_of_argu) && !strcmp(argus[i], "ENDSTATE"))
{
- i_tmp = svf_find_string_in_array(argus[i + 1], (char **)svf_tap_state_name, dimof(svf_tap_state_name));
+ i_tmp = tap_state_by_name(argus[i + 1]);
+
if (svf_tap_state_is_stable(i_tmp))
{
svf_para.runtest_end_state = i_tmp;
- LOG_DEBUG("\tend_state = %s", svf_tap_state_name[svf_para.runtest_end_state]);
+ LOG_DEBUG("\tend_state = %s",
+ tap_state_name(i_tmp));
}
else
{
- LOG_ERROR("%s is not valid state", svf_tap_state_name[i_tmp]);
+ LOG_ERROR("%s: %s is not a stable state",
+ argus[0], tap_state_name(i_tmp));
return ERROR_FAIL;
}
i += 2;
@@ -1301,8 +1280,8 @@ static int svf_run_command(struct command_context_s *cmd_ctx, char *cmd_str)
#else
if (svf_para.runtest_run_state != TAP_IDLE)
{
- // RUNTEST can only executed in TAP_IDLE
- LOG_ERROR("cannot runtest in %s state", svf_tap_state_name[svf_para.runtest_run_state]);
+ LOG_ERROR("cannot runtest in %s state",
+ tap_state_name(svf_para.runtest_run_state));
return ERROR_FAIL;
}
@@ -1333,13 +1312,14 @@ static int svf_run_command(struct command_context_s *cmd_ctx, char *cmd_str)
return ERROR_FAIL;
}
num_of_argu--; // num of path
- i_tmp = 1; // path is from patameter 1
- for (i = 0; i < num_of_argu; i++)
+ i_tmp = 1; /* path is from parameter 1 */
+ for (i = 0; i < num_of_argu; i++, i_tmp++)
{
- path[i] = svf_find_string_in_array(argus[i_tmp++], (char **)svf_tap_state_name, dimof(svf_tap_state_name));
- if (!svf_tap_state_is_valid(path[i]))
+ path[i] = tap_state_by_name(argus[i_tmp]);
+ if (path[i] == TAP_INVALID)
{
- LOG_ERROR("%s is not valid state", svf_tap_state_name[path[i]]);
+ LOG_ERROR("%s: %s is not a valid state",
+ argus[0], argus[i_tmp]);
free(path);
return ERROR_FAIL;
}
@@ -1362,13 +1342,15 @@ static int svf_run_command(struct command_context_s *cmd_ctx, char *cmd_str)
if (svf_tap_state_is_stable(path[num_of_argu - 1]))
{
// last state MUST be stable state
- // TODO: call path_move
jtag_add_pathmove(num_of_argu, path);
- LOG_DEBUG("\tmove to %s by path_move", svf_tap_state_name[path[num_of_argu - 1]]);
+ LOG_DEBUG("\tmove to %s by path_move",
+ tap_state_name(path[num_of_argu - 1]));
}
else
{
- LOG_ERROR("%s is not valid state", svf_tap_state_name[path[num_of_argu - 1]]);
+ LOG_ERROR("%s: %s is not a stable state",
+ argus[0],
+ tap_state_name(path[num_of_argu - 1]));
free(path);
return ERROR_FAIL;
}
@@ -1383,17 +1365,18 @@ static int svf_run_command(struct command_context_s *cmd_ctx, char *cmd_str)
else
{
// STATE stable_state
- state = svf_find_string_in_array(argus[1], (char **)svf_tap_state_name, dimof(svf_tap_state_name));
+ state = tap_state_by_name(argus[1]);
if (svf_tap_state_is_stable(state))
{
LOG_DEBUG("\tmove to %s by svf_add_statemove",
- svf_tap_state_name[state]);
+ tap_state_name(state));
/* FIXME handle statemove failures */
svf_add_statemove(state);
}
else
{
- LOG_ERROR("%s is not valid state", svf_tap_state_name[state]);
+ LOG_ERROR("%s: %s is not a stable state",
+ argus[0], tap_state_name(state));
return ERROR_FAIL;
}
}
@@ -1411,7 +1394,9 @@ static int svf_run_command(struct command_context_s *cmd_ctx, char *cmd_str)
{
return ERROR_FAIL;
}
- i_tmp = svf_find_string_in_array(argus[1], (char **)svf_trst_mode_name, dimof(svf_trst_mode_name));
+ i_tmp = svf_find_string_in_array(argus[1],
+ (char **)svf_trst_mode_name,
+ DIM(svf_trst_mode_name));
switch (i_tmp)
{
case TRST_ON:
-----------------------------------------------------------------------
Summary of changes:
TODO | 1 -
src/jtag/interface.c | 84 +++++++++++++++++--------------
src/jtag/interface.h | 3 -
src/jtag/jtag.h | 21 +++++---
src/jtag/tcl.c | 27 +++-------
src/svf/svf.c | 135 ++++++++++++++++++++++----------------------------
6 files changed, 127 insertions(+), 144 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-10-23 06:21:54
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 517e812de3782a6b592cb69416d1327a9b94ac9f (commit)
from f593ff0a3dd08052648da61a75f5ad5a35945194 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 517e812de3782a6b592cb69416d1327a9b94ac9f
Author: Nicolas Pitre <ni...@fl...>
Date: Thu Oct 22 23:23:44 2009 -0400
Ferocion: fix corruption of r0 when resuming Thumb mode
The wrong variable (pc instead of r0) was used. Furthermore, someone
did cover this error by stupidly silencing the compiler warning that
occurred before a dummy void reference to r0 was added to the code.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 8eea33e..f084201 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -335,7 +335,6 @@ void feroceon_branch_resume_thumb(target_t *target)
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
uint32_t r0 = buf_get_u32(armv4_5->core_cache->reg_list[0].value, 0, 32);
uint32_t pc = buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32);
- (void)(r0); // use R0...
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);
@@ -351,7 +350,7 @@ void feroceon_branch_resume_thumb(target_t *target)
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
- arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, pc, NULL, 0);
+ arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, r0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
arm9tdmi_clock_out(jtag_info, ARMV4_5_T_NOP, 0, NULL, 0);
-----------------------------------------------------------------------
Summary of changes:
src/target/feroceon.c | 3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-10-22 21:05:20
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via f593ff0a3dd08052648da61a75f5ad5a35945194 (commit)
from 344bed2f7eab5f4ff05fd944b1c476fc8a2103ba (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit f593ff0a3dd08052648da61a75f5ad5a35945194
Author: David Brownell <dbr...@us...>
Date: Thu Oct 22 12:05:04 2009 -0700
have "reg" command print cache names too
When dumping over 100 registers (as on most ARM9 + ETM cores),
aid readability by splitting them into logical groups.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/target.c b/src/target/target.c
index 4516207..eb93fb7 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -1823,6 +1823,8 @@ static int handle_reg_command(struct command_context_s *cmd_ctx, char *cmd, char
{
int i;
+ command_print(cmd_ctx, "===== %s", cache->name);
+
for (i = 0, reg = cache->reg_list;
i < cache->num_regs;
i++, reg++, count++)
-----------------------------------------------------------------------
Summary of changes:
src/target/target.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-10-22 21:01:43
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 344bed2f7eab5f4ff05fd944b1c476fc8a2103ba (commit)
from 3537c368feb28b288e4a8449de703f1b972396d0 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 344bed2f7eab5f4ff05fd944b1c476fc8a2103ba
Author: David Brownell <dbr...@us...>
Date: Thu Oct 22 12:01:27 2009 -0700
ETM: rename registers, doc tweaks
The register names are perversely not documented as zero-indexed,
so rename them to match that convention. Also switch to lowercase
suffixes and infix numbering, matching ETB and EmbeddedICE usage.
Update docs to be a bit more accurate, especially regarding what
the "trigger" event can cause; and to split the issues into a few
more paragraphs, for clarity.
Make "configure" helptext point out that "oocd_trace" is prototype
hardware, not anything "real".
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/configure.in b/configure.in
index 1d3f0ec..99f97da 100644
--- a/configure.in
+++ b/configure.in
@@ -377,7 +377,8 @@ AC_ARG_ENABLE(usbprog,
[build_usbprog=$enableval], [build_usbprog=no])
AC_ARG_ENABLE(oocd_trace,
- AS_HELP_STRING([--enable-oocd_trace], [Enable building support for the OpenOCD+trace ETM capture device]),
+ AS_HELP_STRING([--enable-oocd_trace],
+ [Enable building support for some prototype OpenOCD+trace ETM capture hardware]),
[build_oocd_trace=$enableval], [build_oocd_trace=no])
AC_ARG_ENABLE(jlink,
diff --git a/doc/openocd.texi b/doc/openocd.texi
index e04b83c..c9e48bf 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5114,14 +5114,23 @@ ETM support in OpenOCD doesn't seem to be widely used yet.
@quotation Issues
ETM support may be buggy, and at least some @command{etm config}
parameters should be detected by asking the ETM for them.
+
+ETM trigger events could also implement a kind of complex
+hardware breakpoint, much more powerful than the simple
+watchpoint hardware exported by EmbeddedICE modules.
+@emph{Such breakpoints can be triggered even when using the
+dummy trace port driver}.
+
It seems like a GDB hookup should be possible,
-as well as triggering trace on specific events
+as well as tracing only during specific states
(perhaps @emph{handling IRQ 23} or @emph{calls foo()}).
+
There should be GUI tools to manipulate saved trace data and help
analyse it in conjunction with the source code.
It's unclear how much of a common interface is shared
with the current XScale trace support, or should be
shared with eventual Nexus-style trace module support.
+
At this writing (September 2009) only ARM7 and ARM9 support
for ETM modules is available. The code should be able to
work with some newer cores; but not all of them support
@@ -5135,7 +5144,10 @@ ETM setup is coupled with the trace port driver configuration.
Declares the ETM associated with @var{target}, and associates it
with a given trace port @var{driver}. @xref{Trace Port Drivers}.
-Several of the parameters must reflect the trace port configuration.
+Several of the parameters must reflect the trace port capabilities,
+which are a function of silicon capabilties (exposed later
+using @command{etm info}) and of what hardware is connected to
+that port (such as an external pod, or ETB).
The @var{width} must be either 4, 8, or 16.
The @var{mode} must be @option{normal}, @option{multiplexted},
or @option{demultiplexted}.
@@ -5151,6 +5163,9 @@ what CPU activities are traced.
@deffn Command {etm info}
Displays information about the current target's ETM.
+This includes resource counts from the @code{ETM_CONFIG} register,
+as well as silicon capabilities (except on rather old modules).
+from the @code{ETM_SYS_CONFIG} register.
@end deffn
@deffn Command {etm status}
diff --git a/src/target/etm.c b/src/target/etm.c
index 34e2ca8..5106581 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -76,47 +76,46 @@ struct etm_reg_info {
/* basic registers that are always there given the right ETM version */
static const struct etm_reg_info etm_core[] = {
/* NOTE: we "know" ETM_CONFIG is listed first */
- { ETM_CONFIG, 32, RO, 0x10, "ETM_CONFIG", },
+ { ETM_CONFIG, 32, RO, 0x10, "ETM_config", },
/* ETM Trace Registers */
- { ETM_CTRL, 32, RW, 0x10, "ETM_CTRL", },
- { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_TRIG_EVENT", },
- { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_ASIC_CTRL", },
- { ETM_STATUS, 3, RO, 0x11, "ETM_STATUS", },
- { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_SYS_CONFIG", },
+ { ETM_CTRL, 32, RW, 0x10, "ETM_ctrl", },
+ { ETM_TRIG_EVENT, 17, WO, 0x10, "ETM_trig_event", },
+ { ETM_ASIC_CTRL, 8, WO, 0x10, "ETM_asic_ctrl", },
+ { ETM_STATUS, 3, RO, 0x11, "ETM_status", },
+ { ETM_SYS_CONFIG, 9, RO, 0x12, "ETM_sys_config", },
/* TraceEnable configuration */
- { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_TRACE_RESOURCE_CTRL", },
- { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_TRACE_EN_CTRL2", },
- { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_TRACE_EN_EVENT", },
- { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_TRACE_EN_CTRL1", },
+ { ETM_TRACE_RESOURCE_CTRL, 32, WO, 0x12, "ETM_trace_resource_ctrl", },
+ { ETM_TRACE_EN_CTRL2, 16, WO, 0x12, "ETM_trace_en_ctrl2", },
+ { ETM_TRACE_EN_EVENT, 17, WO, 0x10, "ETM_trace_en_event", },
+ { ETM_TRACE_EN_CTRL1, 26, WO, 0x10, "ETM_trace_en_ctrl1", },
/* ViewData configuration (data trace) */
- { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_VIEWDATA_EVENT", },
- { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_VIEWDATA_CTRL1", },
- { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_VIEWDATA_CTRL2", },
- { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_VIEWDATA_CTRL3", },
+ { ETM_VIEWDATA_EVENT, 17, WO, 0x10, "ETM_viewdata_event", },
+ { ETM_VIEWDATA_CTRL1, 32, WO, 0x10, "ETM_viewdata_ctrl1", },
+ { ETM_VIEWDATA_CTRL2, 32, WO, 0x10, "ETM_viewdata_ctrl2", },
+ { ETM_VIEWDATA_CTRL3, 17, WO, 0x10, "ETM_viewdata_ctrl3", },
/* REVISIT exclude VIEWDATA_CTRL2 when it's not there */
- { 0x78, 12, WO, 0x20, "ETM_SYNC_FREQ", },
- { 0x79, 32, RO, 0x20, "ETM_ID", },
+ { 0x78, 12, WO, 0x20, "ETM_sync_freq", },
+ { 0x79, 32, RO, 0x20, "ETM_id", },
};
static const struct etm_reg_info etm_fifofull[] = {
/* FIFOFULL configuration */
- { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_FIFOFULL_REGION", },
- { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_FIFOFULL_LEVEL", },
+ { ETM_FIFOFULL_REGION, 25, WO, 0x10, "ETM_fifofull_region", },
+ { ETM_FIFOFULL_LEVEL, 8, WO, 0x10, "ETM_fifofull_level", },
};
static const struct etm_reg_info etm_addr_comp[] = {
/* Address comparator register pairs */
#define ADDR_COMPARATOR(i) \
- { ETM_ADDR_COMPARATOR_VALUE + (i), 32, WO, 0x10, \
- "ETM_ADDR_COMPARATOR_VALUE" #i, }, \
- { ETM_ADDR_ACCESS_TYPE + (i), 7, WO, 0x10, \
- "ETM_ADDR_ACCESS_TYPE" #i, }
- ADDR_COMPARATOR(0),
+ { ETM_ADDR_COMPARATOR_VALUE + (i) - 1, 32, WO, 0x10, \
+ "ETM_addr_" #i "_comparator_value", }, \
+ { ETM_ADDR_ACCESS_TYPE + (i) - 1, 7, WO, 0x10, \
+ "ETM_addr_" #i "_access_type", }
ADDR_COMPARATOR(1),
ADDR_COMPARATOR(2),
ADDR_COMPARATOR(3),
@@ -124,8 +123,8 @@ static const struct etm_reg_info etm_addr_comp[] = {
ADDR_COMPARATOR(5),
ADDR_COMPARATOR(6),
ADDR_COMPARATOR(7),
-
ADDR_COMPARATOR(8),
+
ADDR_COMPARATOR(9),
ADDR_COMPARATOR(10),
ADDR_COMPARATOR(11),
@@ -133,17 +132,17 @@ static const struct etm_reg_info etm_addr_comp[] = {
ADDR_COMPARATOR(13),
ADDR_COMPARATOR(14),
ADDR_COMPARATOR(15),
+ ADDR_COMPARATOR(16),
#undef ADDR_COMPARATOR
};
static const struct etm_reg_info etm_data_comp[] = {
/* Data Value Comparators (NOTE: odd addresses are reserved) */
#define DATA_COMPARATOR(i) \
- { ETM_DATA_COMPARATOR_VALUE + 2*(i), 32, WO, 0x10, \
- "ETM_DATA_COMPARATOR_VALUE" #i, }, \
- { ETM_DATA_COMPARATOR_MASK + 2*(i), 32, WO, 0x10, \
- "ETM_DATA_COMPARATOR_MASK" #i, }
- DATA_COMPARATOR(0),
+ { ETM_DATA_COMPARATOR_VALUE + 2*(i) - 1, 32, WO, 0x10, \
+ "ETM_data_" #i "_comparator_value", }, \
+ { ETM_DATA_COMPARATOR_MASK + 2*(i) - 1, 32, WO, 0x10, \
+ "ETM_data_" #i "_comparator_mask", }
DATA_COMPARATOR(1),
DATA_COMPARATOR(2),
DATA_COMPARATOR(3),
@@ -151,30 +150,31 @@ static const struct etm_reg_info etm_data_comp[] = {
DATA_COMPARATOR(5),
DATA_COMPARATOR(6),
DATA_COMPARATOR(7),
+ DATA_COMPARATOR(8),
#undef DATA_COMPARATOR
};
static const struct etm_reg_info etm_counters[] = {
#define ETM_COUNTER(i) \
- { ETM_COUNTER_RELOAD_VALUE + (i), 16, WO, 0x10, \
- "ETM_COUNTER_RELOAD_VALUE" #i, }, \
- { ETM_COUNTER_ENABLE + (i), 18, WO, 0x10, \
- "ETM_COUNTER_ENABLE" #i, }, \
- { ETM_COUNTER_RELOAD_EVENT + (i), 17, WO, 0x10, \
- "ETM_COUNTER_RELOAD_EVENT" #i, }, \
- { ETM_COUNTER_VALUE + (i), 16, RO, 0x10, \
- "ETM_COUNTER_VALUE" #i, }
- ETM_COUNTER(0),
+ { ETM_COUNTER_RELOAD_VALUE + (i) - 1, 16, WO, 0x10, \
+ "ETM_counter_" #i "_reload_value", }, \
+ { ETM_COUNTER_ENABLE + (i) - 1, 18, WO, 0x10, \
+ "ETM_counter_" #i "_enable", }, \
+ { ETM_COUNTER_RELOAD_EVENT + (i) - 1, 17, WO, 0x10, \
+ "ETM_counter_" #i "_reload_event", }, \
+ { ETM_COUNTER_VALUE + (i) - 1, 16, RO, 0x10, \
+ "ETM_counter_" #i "_value", }
ETM_COUNTER(1),
ETM_COUNTER(2),
ETM_COUNTER(3),
+ ETM_COUNTER(4),
#undef ETM_COUNTER
};
static const struct etm_reg_info etm_sequencer[] = {
#define ETM_SEQ(i) \
{ ETM_SEQUENCER_EVENT + (i), 17, WO, 0x10, \
- "ETM_SEQUENCER_EVENT" #i, }
+ "ETM_sequencer_event" #i, }
ETM_SEQ(0), /* 1->2 */
ETM_SEQ(1), /* 2->1 */
ETM_SEQ(2), /* 2->3 */
@@ -183,18 +183,18 @@ static const struct etm_reg_info etm_sequencer[] = {
ETM_SEQ(5), /* 1->3 */
#undef ETM_SEQ
/* 0x66 reserved */
- { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_SEQUENCER_STATE", },
+ { ETM_SEQUENCER_STATE, 2, RO, 0x10, "ETM_sequencer_state", },
};
static const struct etm_reg_info etm_outputs[] = {
#define ETM_OUTPUT(i) \
- { ETM_EXTERNAL_OUTPUT + (i), 17, WO, 0x10, \
- "ETM_EXTERNAL_OUTPUT" #i, }
+ { ETM_EXTERNAL_OUTPUT + (i) - 1, 17, WO, 0x10, \
+ "ETM_external_output" #i, }
- ETM_OUTPUT(0),
ETM_OUTPUT(1),
ETM_OUTPUT(2),
ETM_OUTPUT(3),
+ ETM_OUTPUT(4),
#undef ETM_OUTPUT
};
@@ -202,10 +202,10 @@ static const struct etm_reg_info etm_outputs[] = {
/* registers from 0x6c..0x7f were added after ETMv1.3 */
/* Context ID Comparators */
- { 0x6c, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
- { 0x6d, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
- { 0x6e, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_VALUE1", }
- { 0x6f, 32, RO, 0x20, "ETM_CONTEXTID_COMPARATOR_MASK", }
+ { 0x6c, 32, RO, 0x20, "ETM_contextid_comparator_value1", }
+ { 0x6d, 32, RO, 0x20, "ETM_contextid_comparator_value2", }
+ { 0x6e, 32, RO, 0x20, "ETM_contextid_comparator_value3", }
+ { 0x6f, 32, RO, 0x20, "ETM_contextid_comparator_mask", }
#endif
static int etm_reg_arch_type = -1;
@@ -1180,6 +1180,7 @@ static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char
if (argc == 4)
{
+ /* what parts of data access are traced? */
if (strcmp(args[0], "none") == 0)
{
tracemode = ETMV1_TRACE_NONE;
@@ -1248,6 +1249,12 @@ static int handle_etm_tracemode_command(struct command_context_s *cmd_ctx, char
command_print(cmd_ctx, "invalid option '%s'", args[2]);
return ERROR_OK;
}
+
+ /* IGNORED:
+ * - CPRT tracing (coprocessor register transfers)
+ * - debug request (causes debug entry on trigger)
+ * - stall on FIFOFULL (preventing tracedata lossage)
+ */
}
else if (argc != 0)
{
-----------------------------------------------------------------------
Summary of changes:
configure.in | 3 +-
doc/openocd.texi | 19 +++++++++-
src/target/etm.c | 101 +++++++++++++++++++++++++++++-------------------------
3 files changed, 73 insertions(+), 50 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2009-10-22 10:26:21
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 3537c368feb28b288e4a8449de703f1b972396d0 (commit)
from fcf1301e5269fdf734946ccf03177511f2eda851 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 3537c368feb28b288e4a8449de703f1b972396d0
Author: Ãyvind Harboe <oyv...@zy...>
Date: Thu Oct 22 10:22:34 2009 +0200
disable ZY1000's UART forwarding test code.
diff --git a/src/ecosboard.c b/src/ecosboard.c
index 4af38e8..bad5fd5 100644
--- a/src/ecosboard.c
+++ b/src/ecosboard.c
@@ -625,6 +625,9 @@ void setNoDelay(int session, int flag)
#endif
}
+#define TEST_TCPIP() 0
+
+#if TEST_TCPIP
struct
{
int req;
@@ -633,6 +636,7 @@ struct
int actual2;
} tcpipSent[512 * 1024];
int cur;
+#endif
static void zylinjtag_uart(cyg_addrword_t data)
{
@@ -697,7 +701,9 @@ static void zylinjtag_uart(cyg_addrword_t data)
size_t pos, pos2;
pos = 0;
pos2 = 0;
+#if TEST_TCPIP
cur = 0;
+#endif
for (;;)
{
fd_set write_fds;
@@ -798,6 +804,7 @@ static void zylinjtag_uart(cyg_addrword_t data)
}
y2 = written;
}
+#if TEST_TCPIP
if (cur < 1024)
{
tcpipSent[cur].req = x;
@@ -806,11 +813,12 @@ static void zylinjtag_uart(cyg_addrword_t data)
tcpipSent[cur].actual2 = y2;
cur++;
}
-
+#endif
}
closeSession: close(session);
close(serHandle);
+#if TEST_TCPIP
int i;
for (i = 0; i < 1024; i++)
{
@@ -818,6 +826,7 @@ static void zylinjtag_uart(cyg_addrword_t data)
tcpipSent[i].req2, tcpipSent[i].actual2);
}
+#endif
}
close(fd);
-----------------------------------------------------------------------
Summary of changes:
src/ecosboard.c | 11 ++++++++++-
1 files changed, 10 insertions(+), 1 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2009-10-22 07:44:52
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via fcf1301e5269fdf734946ccf03177511f2eda851 (commit)
via e996452089fd5ffba34094958e87d51c1fcf8619 (commit)
from 1e5daf5886999a8ff01a4957e17c1466d76e022d (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit fcf1301e5269fdf734946ccf03177511f2eda851
Author: Ãyvind Harboe <oyv...@zy...>
Date: Wed Oct 21 20:19:47 2009 +0200
mww_phys retired. Replaced by generic mww phys in target.c
diff --git a/doc/openocd.texi b/doc/openocd.texi
index de73bec..e04b83c 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5431,23 +5431,6 @@ Display cp15 register @var{regnum};
else if a @var{value} is provided, that value is written to that register.
@end deffn
-@deffn Command {arm720t mdw_phys} addr [count]
-@deffnx Command {arm720t mdh_phys} addr [count]
-@deffnx Command {arm720t mdb_phys} addr [count]
-Display contents of physical address @var{addr}, as
-32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
-or 8-bit bytes (@command{mdb_phys}).
-If @var{count} is specified, displays that many units.
-@end deffn
-
-@deffn Command {arm720t mww_phys} addr word
-@deffnx Command {arm720t mwh_phys} addr halfword
-@deffnx Command {arm720t mwb_phys} addr byte
-Writes the specified @var{word} (32 bits),
-@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
-at the specified physical address @var{addr}.
-@end deffn
-
@subsection ARM9 specific commands
@cindex ARM9
@@ -5508,23 +5491,6 @@ Else if that value is written using the specified @var{address},
or using zero if no other address is not provided.
@end deffn
-@deffn Command {arm920t mdw_phys} addr [count]
-@deffnx Command {arm920t mdh_phys} addr [count]
-@deffnx Command {arm920t mdb_phys} addr [count]
-Display contents of physical address @var{addr}, as
-32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
-or 8-bit bytes (@command{mdb_phys}).
-If @var{count} is specified, displays that many units.
-@end deffn
-
-@deffn Command {arm920t mww_phys} addr word
-@deffnx Command {arm920t mwh_phys} addr halfword
-@deffnx Command {arm920t mwb_phys} addr byte
-Writes the specified @var{word} (32 bits),
-@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
-at the specified physical address @var{addr}.
-@end deffn
-
@deffn Command {arm920t read_cache} filename
Dump the content of ICache and DCache to a file named @file{filename}.
@end deffn
@@ -5556,23 +5522,6 @@ If a @var{value} is provided, that value is written to that register.
Else that register is read and displayed.
@end deffn
-@deffn Command {arm926ejs mdw_phys} addr [count]
-@deffnx Command {arm926ejs mdh_phys} addr [count]
-@deffnx Command {arm926ejs mdb_phys} addr [count]
-Display contents of physical address @var{addr}, as
-32-bit words (@command{mdw_phys}), 16-bit halfwords (@command{mdh_phys}),
-or 8-bit bytes (@command{mdb_phys}).
-If @var{count} is specified, displays that many units.
-@end deffn
-
-@deffn Command {arm926ejs mww_phys} addr word
-@deffnx Command {arm926ejs mwh_phys} addr halfword
-@deffnx Command {arm926ejs mwb_phys} addr byte
-Writes the specified @var{word} (32 bits),
-@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
-at the specified physical address @var{addr}.
-@end deffn
-
@subsection ARM966E specific commands
@cindex ARM966E
diff --git a/tcl/board/atmel_at91sam9260-ek.cfg b/tcl/board/atmel_at91sam9260-ek.cfg
index 099d93d..06a54e2 100644
--- a/tcl/board/atmel_at91sam9260-ek.cfg
+++ b/tcl/board/atmel_at91sam9260-ek.cfg
@@ -24,7 +24,7 @@ $_TARGETNAME configure -event reset-start {
jtag_rclk 5
halt
# RSTC_MR : enable user reset, MMU may be enabled... use physical address
- arm926ejs mww_phys 0xfffffd08 0xa5000501
+ arm926ejs mww phys 0xfffffd08 0xa5000501
}
$_TARGETNAME configure -event reset-init {
diff --git a/tcl/board/mini2440.cfg b/tcl/board/mini2440.cfg
index 277f61f..2981950 100644
--- a/tcl/board/mini2440.cfg
+++ b/tcl/board/mini2440.cfg
@@ -177,10 +177,10 @@ proc init_2440 { } {
# usb clock are off 12mHz xtal
#-----------------------------------------------
- arm920t mww_phys 0x4C000014 0x00000005 # Clock Divider control Reg
- arm920t mww_phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register
- arm920t mww_phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg
- arm920t mww_phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg
+ arm920t mww phys 0x4C000014 0x00000005 # Clock Divider control Reg
+ arm920t mww phys 0x4C000000 0xFFFFFFFF # LOCKTIME count register
+ arm920t mww phys 0x4C000008 0x00038022 # UPPLCON USB clock config Reg
+ arm920t mww phys 0x4C000004 0x0007F021 # MPPLCON Proc clock config Reg
#-----------------------------------------------
# Configure Memory controller
@@ -188,45 +188,45 @@ proc init_2440 { } {
# DRAM - 64MB - 32 bit bus, uses BANKCON6 BANKCON7
#-----------------------------------------------
- arm920t mww_phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width
- arm920t mww_phys 0x48000010 0x00001112 # BANKCON4 - ?
- arm920t mww_phys 0x4800001c 0x00018009 # BANKCON6 - DRAM
- arm920t mww_phys 0x48000020 0x00018009 # BANKCON7 - DRAM
- arm920t mww_phys 0x48000024 0x008E04EB # REFRESH - DRAM
- arm920t mww_phys 0x48000028 0x000000B2 # BANKSIZE - DRAM
- arm920t mww_phys 0x4800002C 0x00000030 # MRSRB6 - DRAM
- arm920t mww_phys 0x48000030 0x00000030 # MRSRB7 - DRAM
+ arm920t mww phys 0x48000000 0x22111112 # BWSCON - Bank and Bus Width
+ arm920t mww phys 0x48000010 0x00001112 # BANKCON4 - ?
+ arm920t mww phys 0x4800001c 0x00018009 # BANKCON6 - DRAM
+ arm920t mww phys 0x48000020 0x00018009 # BANKCON7 - DRAM
+ arm920t mww phys 0x48000024 0x008E04EB # REFRESH - DRAM
+ arm920t mww phys 0x48000028 0x000000B2 # BANKSIZE - DRAM
+ arm920t mww phys 0x4800002C 0x00000030 # MRSRB6 - DRAM
+ arm920t mww phys 0x48000030 0x00000030 # MRSRB7 - DRAM
#-----------------------------------------------
# Now port configuration for enables for memory
# and other stuff.
#-----------------------------------------------
- arm920t mww_phys 0x56000000 0x007FFFFF # GPACON
+ arm920t mww phys 0x56000000 0x007FFFFF # GPACON
- arm920t mww_phys 0x56000010 0x00295559 # GPBCON
- arm920t mww_phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE)
- arm920t mww_phys 0x56000014 0x000007C2 # GPBDAT
+ arm920t mww phys 0x56000010 0x00295559 # GPBCON
+ arm920t mww phys 0x56000018 0x000003FF # GPBUP (PULLUP ENABLE)
+ arm920t mww phys 0x56000014 0x000007C2 # GPBDAT
- arm920t mww_phys 0x56000020 0xAAAAA6AA # GPCCON
- arm920t mww_phys 0x56000028 0x0000FFFF # GPCUP
- arm920t mww_phys 0x56000024 0x00000020 # GPCDAT
+ arm920t mww phys 0x56000020 0xAAAAA6AA # GPCCON
+ arm920t mww phys 0x56000028 0x0000FFFF # GPCUP
+ arm920t mww phys 0x56000024 0x00000020 # GPCDAT
- arm920t mww_phys 0x56000030 0xAAAAAAAA # GPDCON
- arm920t mww_phys 0x56000038 0x0000FFFF # GPDUP
+ arm920t mww phys 0x56000030 0xAAAAAAAA # GPDCON
+ arm920t mww phys 0x56000038 0x0000FFFF # GPDUP
- arm920t mww_phys 0x56000040 0xAAAAAAAA # GPECON
- arm920t mww_phys 0x56000048 0x0000FFFF # GPEUP
+ arm920t mww phys 0x56000040 0xAAAAAAAA # GPECON
+ arm920t mww phys 0x56000048 0x0000FFFF # GPEUP
- arm920t mww_phys 0x56000050 0x00001555 # GPFCON
- arm920t mww_phys 0x56000058 0x0000007F # GPFUP
- arm920t mww_phys 0x56000054 0x00000000 # GPFDAT
+ arm920t mww phys 0x56000050 0x00001555 # GPFCON
+ arm920t mww phys 0x56000058 0x0000007F # GPFUP
+ arm920t mww phys 0x56000054 0x00000000 # GPFDAT
- arm920t mww_phys 0x56000060 0x00150114 # GPGCON
- arm920t mww_phys 0x56000068 0x0000007F # GPGUP
+ arm920t mww phys 0x56000060 0x00150114 # GPGCON
+ arm920t mww phys 0x56000068 0x0000007F # GPGUP
- arm920t mww_phys 0x56000070 0x0015AAAA # GPHCON
- arm920t mww_phys 0x56000078 0x000003FF # GPGUP
+ arm920t mww phys 0x56000070 0x0015AAAA # GPHCON
+ arm920t mww phys 0x56000078 0x000003FF # GPGUP
}
diff --git a/tcl/board/olimex_sam9_l9260.cfg b/tcl/board/olimex_sam9_l9260.cfg
index b5cd10e..935d7cd 100644
--- a/tcl/board/olimex_sam9_l9260.cfg
+++ b/tcl/board/olimex_sam9_l9260.cfg
@@ -26,7 +26,7 @@ $_TARGETNAME configure -event reset-start {
# RSTC_MR : enable user reset, reset length is 64 slow clock cycles. MMU may
# be enabled... use physical address.
- arm926ejs mww_phys 0xfffffd08 0xa5000501
+ arm926ejs mww phys 0xfffffd08 0xa5000501
}
$_TARGETNAME configure -event reset-init {
diff --git a/tcl/board/unknown_at91sam9260.cfg b/tcl/board/unknown_at91sam9260.cfg
index 017f793..7286a96 100644
--- a/tcl/board/unknown_at91sam9260.cfg
+++ b/tcl/board/unknown_at91sam9260.cfg
@@ -18,7 +18,7 @@ $_TARGETNAME configure -event reset-start {
jtag_rclk 3
halt
# RSTC_MR : enable user reset, MMU may be enabled... use physical address
- arm926ejs mww_phys 0xfffffd08 0xa5000501
+ arm926ejs mww phys 0xfffffd08 0xa5000501
}
diff --git a/tcl/target/davinci.cfg b/tcl/target/davinci.cfg
index e1eb48f..c14c98e 100644
--- a/tcl/target/davinci.cfg
+++ b/tcl/target/davinci.cfg
@@ -204,34 +204,34 @@ proc davinci_wdog_reset {} {
#
# EMUMGT_CLKSPEED: write FREE bit to run despite emulation halt
- arm926ejs mww_phys [expr $timer2_phys + 0x28] 0x00004000
+ arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000
#
# Part II -- in case watchdog hasn't been set up
#
# TCR: disable, force internal clock source
- arm926ejs mww_phys [expr $timer2_phys + 0x20] 0
+ arm926ejs mww phys [expr $timer2_phys + 0x20] 0
# TGCR: reset, force to 64-bit wdog mode, un-reset ("initial" state)
- arm926ejs mww_phys [expr $timer2_phys + 0x24] 0
- arm926ejs mww_phys [expr $timer2_phys + 0x24] 0x110b
+ arm926ejs mww phys [expr $timer2_phys + 0x24] 0
+ arm926ejs mww phys [expr $timer2_phys + 0x24] 0x110b
# clear counter (TIM12, TIM34) and period (PRD12, PRD34) registers
# so watchdog triggers ASAP
- arm926ejs mww_phys [expr $timer2_phys + 0x10] 0
- arm926ejs mww_phys [expr $timer2_phys + 0x14] 0
- arm926ejs mww_phys [expr $timer2_phys + 0x18] 0
- arm926ejs mww_phys [expr $timer2_phys + 0x1c] 0
+ arm926ejs mww phys [expr $timer2_phys + 0x10] 0
+ arm926ejs mww phys [expr $timer2_phys + 0x14] 0
+ arm926ejs mww phys [expr $timer2_phys + 0x18] 0
+ arm926ejs mww phys [expr $timer2_phys + 0x1c] 0
# WDTCR: put into pre-active state, then active
- arm926ejs mww_phys [expr $timer2_phys + 0x28] 0xa5c64000
- arm926ejs mww_phys [expr $timer2_phys + 0x28] 0xda7e4000
+ arm926ejs mww phys [expr $timer2_phys + 0x28] 0xa5c64000
+ arm926ejs mww phys [expr $timer2_phys + 0x28] 0xda7e4000
#
# Part III -- it's ready to rumble
#
# WDTCR: write invalid WDKEY to trigger reset
- arm926ejs mww_phys [expr $timer2_phys + 0x28] 0x00004000
+ arm926ejs mww phys [expr $timer2_phys + 0x28] 0x00004000
}
commit e996452089fd5ffba34094958e87d51c1fcf8619
Author: Ãyvind Harboe <oyv...@zy...>
Date: Wed Oct 21 20:16:31 2009 +0200
virt2phys is now implemented by target.c globally, retire target specific documentation.
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 4f22832..de73bec 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5448,11 +5448,6 @@ Writes the specified @var{word} (32 bits),
at the specified physical address @var{addr}.
@end deffn
-@deffn Command {arm720t virt2phys} va
-Translate a virtual address @var{va} to a physical address
-and display the result.
-@end deffn
-
@subsection ARM9 specific commands
@cindex ARM9
@@ -5538,11 +5533,6 @@ Dump the content of ICache and DCache to a file named @file{filename}.
Dump the content of the ITLB and DTLB to a file named @file{filename}.
@end deffn
-@deffn Command {arm920t virt2phys} va
-Translate a virtual address @var{va} to a physical address
-and display the result.
-@end deffn
-
@subsection ARM926ej-s specific commands
@cindex ARM926ej-s
@@ -5583,11 +5573,6 @@ Writes the specified @var{word} (32 bits),
at the specified physical address @var{addr}.
@end deffn
-@deffn Command {arm926ejs virt2phys} va
-Translate a virtual address @var{va} to a physical address
-and display the result.
-@end deffn
-
@subsection ARM966E specific commands
@cindex ARM966E
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 66 ------------------------------------
tcl/board/atmel_at91sam9260-ek.cfg | 2 +-
tcl/board/mini2440.cfg | 60 ++++++++++++++++----------------
tcl/board/olimex_sam9_l9260.cfg | 2 +-
tcl/board/unknown_at91sam9260.cfg | 2 +-
tcl/target/davinci.cfg | 22 ++++++------
6 files changed, 44 insertions(+), 110 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2009-10-21 15:36:53
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 1e5daf5886999a8ff01a4957e17c1466d76e022d (commit)
from 2d45a10dfd70f9f13a8d07553d728e5025feabb5 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 1e5daf5886999a8ff01a4957e17c1466d76e022d
Author: Ãyvind Harboe <oyv...@zy...>
Date: Wed Oct 21 15:36:31 2009 +0200
retire obsolete mXY_phys commands. Handled by generic memory read/modify commands and target read/write physical memory callbacks.
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 7bf181c..71440eb 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -34,8 +34,6 @@
int arm720t_register_commands(struct command_context_s *cmd_ctx);
int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
/* forward declarations */
int arm720t_target_create(struct target_s *target,Jim_Interp *interp);
@@ -514,14 +512,6 @@ int arm720t_register_commands(struct command_context_s *cmd_ctx)
register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
- register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
- register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
- register_command(cmd_ctx, arm720t_cmd, "mdb_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
-
- register_command(cmd_ctx, arm720t_cmd, "mww_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
- register_command(cmd_ctx, arm720t_cmd, "mwh_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
- register_command(cmd_ctx, arm720t_cmd, "mwb_phys", arm720t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
-
return ERROR_OK;
}
@@ -584,55 +574,3 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
return ERROR_OK;
}
-
-int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
-{
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm7tdmi_common_t *arm7tdmi;
- arm720t_common_t *arm720t;
- arm_jtag_t *jtag_info;
-
- if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
- {
- command_print(cmd_ctx, "current target isn't an ARM720t target");
- return ERROR_OK;
- }
-
- jtag_info = &arm7_9->jtag_info;
-
- if (target->state != TARGET_HALTED)
- {
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
- return ERROR_OK;
- }
-
- return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
-}
-
-int arm720t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
-{
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm7tdmi_common_t *arm7tdmi;
- arm720t_common_t *arm720t;
- arm_jtag_t *jtag_info;
-
- if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
- {
- command_print(cmd_ctx, "current target isn't an ARM720t target");
- return ERROR_OK;
- }
-
- jtag_info = &arm7_9->jtag_info;
-
- if (target->state != TARGET_HALTED)
- {
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
- return ERROR_OK;
- }
-
- return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
-}
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 08c3b44..2531d9b 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -34,8 +34,6 @@
int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm920t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm920t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm920t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int arm920t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
@@ -726,14 +724,6 @@ int arm920t_register_commands(struct command_context_s *cmd_ctx)
register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
- register_command(cmd_ctx, arm920t_cmd, "mdw_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
- register_command(cmd_ctx, arm920t_cmd, "mdh_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
- register_command(cmd_ctx, arm920t_cmd, "mdb_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
-
- register_command(cmd_ctx, arm920t_cmd, "mww_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
- register_command(cmd_ctx, arm920t_cmd, "mwh_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
- register_command(cmd_ctx, arm920t_cmd, "mwb_phys", arm920t_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
-
register_command(cmd_ctx, arm920t_cmd, "read_cache", arm920t_handle_read_cache_command, COMMAND_EXEC, "display I/D cache content");
register_command(cmd_ctx, arm920t_cmd, "read_mmu", arm920t_handle_read_mmu_command, COMMAND_EXEC, "display I/D mmu content");
@@ -1425,55 +1415,3 @@ int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *c
return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
}
-
-int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
-{
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm9tdmi_common_t *arm9tdmi;
- arm920t_common_t *arm920t;
- arm_jtag_t *jtag_info;
-
- if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
- {
- command_print(cmd_ctx, "current target isn't an ARM920t target");
- return ERROR_OK;
- }
-
- jtag_info = &arm7_9->jtag_info;
-
- if (target->state != TARGET_HALTED)
- {
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
- return ERROR_OK;
- }
-
- return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
-}
-
-int arm920t_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
-{
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm9tdmi_common_t *arm9tdmi;
- arm920t_common_t *arm920t;
- arm_jtag_t *jtag_info;
-
- if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
- {
- command_print(cmd_ctx, "current target isn't an ARM920t target");
- return ERROR_OK;
- }
-
- jtag_info = &arm7_9->jtag_info;
-
- if (target->state != TARGET_HALTED)
- {
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
- return ERROR_OK;
- }
-
- return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
-}
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index d5ea082..9c9628a 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -37,8 +37,6 @@
int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm926ejs_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
@@ -835,14 +833,6 @@ int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
- register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
- register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
- register_command(cmd_ctx, arm926ejs_cmd, "mdb_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory bytes <physical addr> [count]");
-
- register_command(cmd_ctx, arm926ejs_cmd, "mww_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory word <physical addr> <value>");
- register_command(cmd_ctx, arm926ejs_cmd, "mwh_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory half-word <physical addr> <value>");
- register_command(cmd_ctx, arm926ejs_cmd, "mwb_phys", arm926ejs_handle_mw_phys_command, COMMAND_EXEC, "write memory byte <physical addr> <value>");
-
return retval;
}
@@ -928,58 +918,6 @@ int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char
return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
}
-int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
-{
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm9tdmi_common_t *arm9tdmi;
- arm926ejs_common_t *arm926ejs;
- arm_jtag_t *jtag_info;
-
- if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
- {
- command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
- return ERROR_OK;
- }
-
- jtag_info = &arm7_9->jtag_info;
-
- if (target->state != TARGET_HALTED)
- {
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
- return ERROR_OK;
- }
-
- return armv4_5_mmu_handle_md_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
-}
-
-int arm926ejs_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
-{
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm9tdmi_common_t *arm9tdmi;
- arm926ejs_common_t *arm926ejs;
- arm_jtag_t *jtag_info;
-
- if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
- {
- command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
- return ERROR_OK;
- }
-
- jtag_info = &arm7_9->jtag_info;
-
- if (target->state != TARGET_HALTED)
- {
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
- return ERROR_OK;
- }
-
- return armv4_5_mmu_handle_mw_phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
-}
-
static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical)
{
int retval;
diff --git a/src/target/armv4_5_mmu.c b/src/target/armv4_5_mmu.c
index 3380012..4088fd2 100644
--- a/src/target/armv4_5_mmu.c
+++ b/src/target/armv4_5_mmu.c
@@ -169,154 +169,3 @@ int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_m
return retval;
}
-
-int armv4_5_mmu_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu)
-{
- int count = 1;
- int size = 4;
- uint32_t address = 0;
- int i;
-
- char output[128];
- int output_len;
-
- int retval;
-
- uint8_t *buffer;
-
- if (target->state != TARGET_HALTED)
- {
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
- return ERROR_OK;
- }
-
- if (argc < 1)
- return ERROR_OK;
-
- if (argc == 2)
- count = strtoul(args[1], NULL, 0);
-
- address = strtoul(args[0], NULL, 0);
-
- switch (cmd[2])
- {
- case 'w':
- size = 4;
- break;
- case 'h':
- size = 2;
- break;
- case 'b':
- size = 1;
- break;
- default:
- return ERROR_OK;
- }
-
- buffer = calloc(count, size);
- if ((retval = armv4_5_mmu_read_physical(target, armv4_5_mmu, address, size, count, buffer)) != ERROR_OK)
- {
- switch (retval)
- {
- case ERROR_TARGET_UNALIGNED_ACCESS:
- command_print(cmd_ctx, "error: address not aligned");
- break;
- case ERROR_TARGET_NOT_HALTED:
- command_print(cmd_ctx, "error: target must be halted for memory accesses");
- break;
- case ERROR_TARGET_DATA_ABORT:
- command_print(cmd_ctx, "error: access caused data abort, system possibly corrupted");
- break;
- default:
- command_print(cmd_ctx, "error: unknown error");
- }
- }
-
- output_len = 0;
-
- for (i = 0; i < count; i++)
- {
- if (i%8 == 0)
- output_len += snprintf(output + output_len, 128 - output_len, "0x%8.8" PRIx32 ": ", address + (i*size));
-
- switch (size)
- {
- case 4:
- output_len += snprintf(output + output_len, 128 - output_len, "%8.8" PRIx32 " ", target_buffer_get_u32(target, &buffer[i*4]));
- break;
- case 2:
- output_len += snprintf(output + output_len, 128 - output_len, "%4.4x ", target_buffer_get_u16(target, &buffer[i*2]));
- break;
- case 1:
- output_len += snprintf(output + output_len, 128 - output_len, "%2.2x ", buffer[i*1]);
- break;
- }
-
- if ((i % 8 == 7) || (i == count - 1))
- {
- command_print(cmd_ctx, "%s", output);
- output_len = 0;
- }
- }
-
- free(buffer);
-
- return ERROR_OK;
-}
-
-int armv4_5_mmu_handle_mw_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu)
-{
- uint32_t address = 0;
- uint32_t value = 0;
- int retval;
- uint8_t value_buf[4];
-
- if (target->state != TARGET_HALTED)
- {
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
- return ERROR_OK;
- }
-
- if (argc < 2)
- return ERROR_OK;
-
- address = strtoul(args[0], NULL, 0);
- value = strtoul(args[1], NULL, 0);
-
- switch (cmd[2])
- {
- case 'w':
- target_buffer_set_u32(target, value_buf, value);
- retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 4, 1, value_buf);
- break;
- case 'h':
- target_buffer_set_u16(target, value_buf, value);
- retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 2, 1, value_buf);
- break;
- case 'b':
- value_buf[0] = value;
- retval = armv4_5_mmu_write_physical(target, armv4_5_mmu, address, 1, 1, value_buf);
- break;
- default:
- return ERROR_OK;
- }
-
- switch (retval)
- {
- case ERROR_TARGET_UNALIGNED_ACCESS:
- command_print(cmd_ctx, "error: address not aligned");
- break;
- case ERROR_TARGET_DATA_ABORT:
- command_print(cmd_ctx, "error: access caused data abort, system possibly corrupted");
- break;
- case ERROR_TARGET_NOT_HALTED:
- command_print(cmd_ctx, "error: target must be halted for memory accesses");
- break;
- case ERROR_OK:
- break;
- default:
- command_print(cmd_ctx, "error: unknown error");
- }
-
- return ERROR_OK;
-}
diff --git a/src/target/armv4_5_mmu.h b/src/target/armv4_5_mmu.h
index dc9f595..0c9b550 100644
--- a/src/target/armv4_5_mmu.h
+++ b/src/target/armv4_5_mmu.h
@@ -46,10 +46,6 @@ extern uint32_t armv4_5_mmu_translate_va(target_t *target, armv4_5_mmu_common_t
extern int armv4_5_mmu_read_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
extern int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_mmu, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
-extern int armv4_5_mmu_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu);
-extern int armv4_5_mmu_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu);
-extern int armv4_5_mmu_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu);
-
enum
{
ARMV4_5_MMU_ENABLED = 0x1,
-----------------------------------------------------------------------
Summary of changes:
src/target/arm720t.c | 62 -------------------
src/target/arm920t.c | 62 -------------------
src/target/arm926ejs.c | 62 -------------------
src/target/armv4_5_mmu.c | 151 ----------------------------------------------
src/target/armv4_5_mmu.h | 4 -
5 files changed, 0 insertions(+), 341 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2009-10-21 15:32:49
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 2d45a10dfd70f9f13a8d07553d728e5025feabb5 (commit)
from 85bf1627cd15e56b1382aa9fe887a3e246999758 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 2d45a10dfd70f9f13a8d07553d728e5025feabb5
Author: Ãyvind Harboe <oyv...@zy...>
Date: Wed Oct 21 15:32:29 2009 +0200
read/write physical target fn's
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 2ebd83a..7bf181c 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -44,6 +44,8 @@ int arm720t_quit(void);
int arm720t_arch_state(struct target_s *target);
int arm720t_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int arm720t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int arm720t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int arm720t_soft_reset_halt(struct target_s *target);
target_type_t arm720t_target =
@@ -65,6 +67,8 @@ target_type_t arm720t_target =
.read_memory = arm720t_read_memory,
.write_memory = arm720t_write_memory,
+ .read_phys_memory = arm720t_read_phys_memory,
+ .write_phys_memory = arm720t_write_phys_memory,
.bulk_write_memory = arm7_9_bulk_write_memory,
.checksum_memory = arm7_9_checksum_memory,
.blank_check_memory = arm7_9_blank_check_memory,
@@ -81,6 +85,7 @@ target_type_t arm720t_target =
.init_target = arm720t_init_target,
.examine = arm7tdmi_examine,
.quit = arm720t_quit
+
};
int arm720t_scan_cp15(target_t *target, uint32_t out, uint32_t *in, int instruction, int clock)
@@ -358,6 +363,28 @@ int arm720t_write_memory(struct target_s *target, uint32_t address, uint32_t siz
return retval;
}
+
+int arm720t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
+ arm720t_common_t *arm720t = arm7tdmi->arch_info;
+
+ return armv4_5_mmu_read_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
+}
+
+int arm720t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ arm7tdmi_common_t *arm7tdmi = arm7_9->arch_info;
+ arm720t_common_t *arm720t = arm7tdmi->arch_info;
+
+ return armv4_5_mmu_write_physical(target, &arm720t->armv4_5_mmu, address, size, count, buffer);
+}
+
+
int arm720t_soft_reset_halt(struct target_s *target)
{
int retval = ERROR_OK;
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 5ade82b..08c3b44 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -36,6 +36,8 @@ int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, c
int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm920t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm920t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+int arm920t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int arm920t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
int arm920t_handle_read_cache_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm920t_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
@@ -68,6 +70,8 @@ target_type_t arm920t_target =
.read_memory = arm920t_read_memory,
.write_memory = arm920t_write_memory,
+ .read_phys_memory = arm920t_read_phys_memory,
+ .write_phys_memory = arm920t_write_phys_memory,
.bulk_write_memory = arm7_9_bulk_write_memory,
.checksum_memory = arm7_9_checksum_memory,
.blank_check_memory = arm7_9_blank_check_memory,
@@ -520,6 +524,28 @@ int arm920t_read_memory(struct target_s *target, uint32_t address, uint32_t size
return retval;
}
+
+int arm920t_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
+ arm920t_common_t *arm920t = arm9tdmi->arch_info;
+
+ return armv4_5_mmu_read_physical(target, &arm920t->armv4_5_mmu, address, size, count, buffer);
+}
+
+int arm920t_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
+ arm920t_common_t *arm920t = arm9tdmi->arch_info;
+
+ return armv4_5_mmu_write_physical(target, &arm920t->armv4_5_mmu, address, size, count, buffer);
+}
+
+
int arm920t_write_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
int retval;
-----------------------------------------------------------------------
Summary of changes:
src/target/arm720t.c | 27 +++++++++++++++++++++++++++
src/target/arm920t.c | 26 ++++++++++++++++++++++++++
2 files changed, 53 insertions(+), 0 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2009-10-21 14:46:53
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 85bf1627cd15e56b1382aa9fe887a3e246999758 (commit)
via 2783cba8106a86bd81635b509ccb5edb0ebd3d29 (commit)
via 818cedaff315d4ca44541012d5e4a8882cda1c85 (commit)
via 69a6037ce6e76dca4117689208358231dffa0929 (commit)
from e895246966e3aa6e78f9d0816c72c6fbb9160122 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 85bf1627cd15e56b1382aa9fe887a3e246999758
Author: Ãyvind Harboe <oyv...@zy...>
Date: Wed Oct 21 14:46:12 2009 +0200
add support for target_read/write_phys_memory callbacks.
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index c3c5097..d5ea082 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -47,7 +47,9 @@ int arm926ejs_handle_read_mmu_command(struct command_context_s *cmd_ctx, char *c
int arm926ejs_target_create(struct target_s *target, Jim_Interp *interp);
int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm926ejs_quit(void);
-int arm926ejs_read_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+
+int arm926ejs_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+int arm926ejs_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
static int arm926ejs_virt2phys(struct target_s *target, uint32_t virtual, uint32_t *physical);
static int arm926ejs_mmu(struct target_s *target, int *enabled);
@@ -90,7 +92,10 @@ target_type_t arm926ejs_target =
.examine = arm9tdmi_examine,
.quit = arm926ejs_quit,
.virt2phys = arm926ejs_virt2phys,
- .mmu = arm926ejs_mmu
+ .mmu = arm926ejs_mmu,
+
+ .read_phys_memory = arm926ejs_read_phys_memory,
+ .write_phys_memory = arm926ejs_write_phys_memory,
};
int arm926ejs_catch_broken_irscan(uint8_t *captured, void *priv, scan_field_t *field)
@@ -738,6 +743,26 @@ int arm926ejs_write_memory(struct target_s *target, uint32_t address, uint32_t s
return retval;
}
+int arm926ejs_write_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
+ arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
+
+ return armv4_5_mmu_write_physical(target, &arm926ejs->armv4_5_mmu, address, size, count, buffer);
+}
+
+int arm926ejs_read_phys_memory(struct target_s *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ armv4_5_common_t *armv4_5 = target->arch_info;
+ arm7_9_common_t *arm7_9 = armv4_5->arch_info;
+ arm9tdmi_common_t *arm9tdmi = arm7_9->arch_info;
+ arm926ejs_common_t *arm926ejs = arm9tdmi->arch_info;
+
+ return armv4_5_mmu_read_physical(target, &arm926ejs->armv4_5_mmu, address, size, count, buffer);
+}
+
int arm926ejs_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
{
arm9tdmi_init_target(cmd_ctx, target);
commit 2783cba8106a86bd81635b509ccb5edb0ebd3d29
Author: Ãyvind Harboe <oyv...@zy...>
Date: Wed Oct 21 14:45:39 2009 +0200
Added target_read/write_phys_memory() fn's. mdX/mwX commands updated to support phys flag to specify bypassing of MMU.
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 500faf9..4f22832 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4938,23 +4938,27 @@ Please use their TARGET object siblings to avoid making assumptions
about what TAP is the current target, or about MMU configuration.
@end enumerate
-@deffn Command mdw addr [count]
-@deffnx Command mdh addr [count]
-@deffnx Command mdb addr [count]
+@deffn Command mdw [phys] addr [count]
+@deffnx Command mdh [phys] addr [count]
+@deffnx Command mdb [phys] addr [count]
Display contents of address @var{addr}, as
32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
or 8-bit bytes (@command{mdb}).
If @var{count} is specified, displays that many units.
+@var{phys} is an optional flag to indicate to use
+physical address and bypass MMU
(If you want to manipulate the data instead of displaying it,
see the @code{mem2array} primitives.)
@end deffn
-@deffn Command mww addr word
-@deffnx Command mwh addr halfword
-@deffnx Command mwb addr byte
+@deffn Command mww [phys] addr word
+@deffnx Command mwh [phys] addr halfword
+@deffnx Command mwb [phys] addr byte
Writes the specified @var{word} (32 bits),
@var{halfword} (16 bits), or @var{byte} (8-bit) pattern,
at the specified address @var{addr}.
+@var{phys} is an optional flag to indicate to use
+physical address and bypass MMU
@end deffn
diff --git a/src/target/target.c b/src/target/target.c
index 7763b95..4516207 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -601,11 +601,24 @@ int target_read_memory(struct target_s *target,
return target->type->read_memory(target, address, size, count, buffer);
}
+int target_read_phys_memory(struct target_s *target,
+ uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ return target->type->read_phys_memory(target, address, size, count, buffer);
+}
+
int target_write_memory(struct target_s *target,
uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
{
return target->type->write_memory(target, address, size, count, buffer);
}
+
+int target_write_phys_memory(struct target_s *target,
+ uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+{
+ return target->type->write_phys_memory(target, address, size, count, buffer);
+}
+
int target_bulk_write_memory(struct target_s *target,
uint32_t address, uint32_t count, uint8_t *buffer)
{
@@ -698,6 +711,17 @@ int target_init(struct command_context_s *cmd_ctx)
{
target->type->virt2phys = default_virt2phys;
}
+
+ if (target->type->read_phys_memory == NULL)
+ {
+ target->type->read_phys_memory = target->type->read_memory;
+ }
+
+ if (target->type->write_phys_memory == NULL)
+ {
+ target->type->write_phys_memory = target->type->write_memory;
+ }
+
/* a non-invasive way(in terms of patches) to add some code that
* runs before the type->write/read_memory implementation
*/
@@ -1531,13 +1555,13 @@ int target_register_user_commands(struct command_context_s *cmd_ctx)
register_command(cmd_ctx, NULL, "reset", handle_reset_command, COMMAND_EXEC, "reset target [run | halt | init] - default is run");
register_command(cmd_ctx, NULL, "soft_reset_halt", handle_soft_reset_halt_command, COMMAND_EXEC, "halt the target and do a soft reset");
- register_command(cmd_ctx, NULL, "mdw", handle_md_command, COMMAND_EXEC, "display memory words <addr> [count]");
- register_command(cmd_ctx, NULL, "mdh", handle_md_command, COMMAND_EXEC, "display memory half-words <addr> [count]");
- register_command(cmd_ctx, NULL, "mdb", handle_md_command, COMMAND_EXEC, "display memory bytes <addr> [count]");
+ register_command(cmd_ctx, NULL, "mdw", handle_md_command, COMMAND_EXEC, "display memory words [phys] <addr> [count]");
+ register_command(cmd_ctx, NULL, "mdh", handle_md_command, COMMAND_EXEC, "display memory half-words [phys] <addr> [count]");
+ register_command(cmd_ctx, NULL, "mdb", handle_md_command, COMMAND_EXEC, "display memory bytes [phys] <addr> [count]");
- register_command(cmd_ctx, NULL, "mww", handle_mw_command, COMMAND_EXEC, "write memory word <addr> <value> [count]");
- register_command(cmd_ctx, NULL, "mwh", handle_mw_command, COMMAND_EXEC, "write memory half-word <addr> <value> [count]");
- register_command(cmd_ctx, NULL, "mwb", handle_mw_command, COMMAND_EXEC, "write memory byte <addr> <value> [count]");
+ register_command(cmd_ctx, NULL, "mww", handle_mw_command, COMMAND_EXEC, "write memory word [phys] <addr> <value> [count]");
+ register_command(cmd_ctx, NULL, "mwh", handle_mw_command, COMMAND_EXEC, "write memory half-word [phys] <addr> <value> [count]");
+ register_command(cmd_ctx, NULL, "mwb", handle_mw_command, COMMAND_EXEC, "write memory byte [phys] <addr> <value> [count]");
register_command(cmd_ctx, NULL, "bp",
handle_bp_command, COMMAND_EXEC,
@@ -2183,6 +2207,22 @@ static int handle_md_command(struct command_context_s *cmd_ctx, char *cmd, char
default: return ERROR_COMMAND_SYNTAX_ERROR;
}
+ bool physical=strcmp(args[0], "phys")==0;
+ int (*fn)(struct target_s *target,
+ uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+ if (physical)
+ {
+ argc--;
+ args++;
+ fn=target_read_phys_memory;
+ } else
+ {
+ fn=target_read_memory;
+ }
+ if ((argc < 1) || (argc > 2))
+ {
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
uint32_t address;
int retval = parse_u32(args[0], &address);
if (ERROR_OK != retval)
@@ -2199,8 +2239,7 @@ static int handle_md_command(struct command_context_s *cmd_ctx, char *cmd, char
uint8_t *buffer = calloc(count, size);
target_t *target = get_current_target(cmd_ctx);
- retval = target_read_memory(target,
- address, size, count, buffer);
+ retval = fn(target, address, size, count, buffer);
if (ERROR_OK == retval)
handle_md_output(cmd_ctx, target, address, size, count, buffer);
@@ -2211,7 +2250,23 @@ static int handle_md_command(struct command_context_s *cmd_ctx, char *cmd, char
static int handle_mw_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
- if ((argc < 2) || (argc > 3))
+ if (argc < 2)
+ {
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+ bool physical=strcmp(args[0], "phys")==0;
+ int (*fn)(struct target_s *target,
+ uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+ if (physical)
+ {
+ argc--;
+ args++;
+ fn=target_write_phys_memory;
+ } else
+ {
+ fn=target_write_memory;
+ }
+ if ((argc < 2) || (argc > 3))
return ERROR_COMMAND_SYNTAX_ERROR;
uint32_t address;
@@ -2254,7 +2309,7 @@ static int handle_mw_command(struct command_context_s *cmd_ctx, char *cmd, char
}
for (unsigned i = 0; i < count; i++)
{
- retval = target_write_memory(target,
+ retval = fn(target,
address + i * wordsize, wordsize, 1, value_buf);
if (ERROR_OK != retval)
return retval;
diff --git a/src/target/target_type.h b/src/target/target_type.h
index d28608f..aab4321 100644
--- a/src/target/target_type.h
+++ b/src/target/target_type.h
@@ -180,7 +180,26 @@ struct target_type_s
int (*init_target)(struct command_context_s *cmd_ctx, struct target_s *target);
int (*quit)(void);
+ /* translate from virtual to physical address. Default implementation is successful
+ * no-op(i.e. virtual==physical).
+ */
int (*virt2phys)(struct target_s *target, uint32_t address, uint32_t *physical);
+
+ /* read directly from physical memory. caches are bypassed and untouched.
+ *
+ * If the target does not support disabling caches, leaving them untouched,
+ * then minimally the actual physical memory location will be read even
+ * if cache states are unchanged, flushed, etc.
+ *
+ * Default implementation is to call read_memory.
+ */
+ int (*read_phys_memory)(struct target_s *target, uint32_t phys_address, uint32_t size, uint32_t count, uint8_t *buffer);
+
+ /*
+ * same as read_phys_memory, except that it writes...
+ */
+ int (*write_phys_memory)(struct target_s *target, uint32_t phys_address, uint32_t size, uint32_t count, uint8_t *buffer);
+
int (*mmu)(struct target_s *target, int *enabled);
};
commit 818cedaff315d4ca44541012d5e4a8882cda1c85
Merge: 69a6037 e895246
Author: Ãyvind Harboe <oyv...@zy...>
Date: Wed Oct 21 13:20:29 2009 +0200
Merge branch 'master' of ssh://go...@op.../gitroot/openocd/openocd into HEAD
commit 69a6037ce6e76dca4117689208358231dffa0929
Author: Ãyvind Harboe <oyv...@zy...>
Date: Wed Oct 21 13:10:32 2009 +0200
Retire obsolete and superfluous implementations of virt2phys in each target. This is done in a polymorphic implementation in target.c
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index a5916aa..2ebd83a 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -34,7 +34,6 @@
int arm720t_register_commands(struct command_context_s *cmd_ctx);
int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm720t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm720t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm720t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
@@ -487,7 +486,6 @@ int arm720t_register_commands(struct command_context_s *cmd_ctx)
arm720t_cmd = register_command(cmd_ctx, NULL, "arm720t", NULL, COMMAND_ANY, "arm720t specific commands");
register_command(cmd_ctx, arm720t_cmd, "cp15", arm720t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode> [value]");
- register_command(cmd_ctx, arm720t_cmd, "virt2phys", arm720t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
register_command(cmd_ctx, arm720t_cmd, "mdw_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
register_command(cmd_ctx, arm720t_cmd, "mdh_phys", arm720t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
@@ -560,32 +558,6 @@ int arm720t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, ch
return ERROR_OK;
}
-int arm720t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
-{
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm7tdmi_common_t *arm7tdmi;
- arm720t_common_t *arm720t;
- arm_jtag_t *jtag_info;
-
- if (arm720t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm7tdmi, &arm720t) != ERROR_OK)
- {
- command_print(cmd_ctx, "current target isn't an ARM720t target");
- return ERROR_OK;
- }
-
- jtag_info = &arm7_9->jtag_info;
-
- if (target->state != TARGET_HALTED)
- {
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
- return ERROR_OK;
- }
-
- return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm720t->armv4_5_mmu);
-}
-
int arm720t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 3d119bd..5ade82b 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -33,7 +33,6 @@
/* cli handling */
int arm920t_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm920t_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm920t_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm920t_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm920t_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
@@ -700,7 +699,6 @@ int arm920t_register_commands(struct command_context_s *cmd_ctx)
register_command(cmd_ctx, arm920t_cmd, "cp15", arm920t_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <num> [value]");
register_command(cmd_ctx, arm920t_cmd, "cp15i", arm920t_handle_cp15i_command, COMMAND_EXEC, "display/modify cp15 (interpreted access) <opcode> [value] [address]");
register_command(cmd_ctx, arm920t_cmd, "cache_info", arm920t_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
- register_command(cmd_ctx, arm920t_cmd, "virt2phys", arm920t_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
register_command(cmd_ctx, arm920t_cmd, "mdw_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
register_command(cmd_ctx, arm920t_cmd, "mdh_phys", arm920t_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
@@ -1402,32 +1400,6 @@ int arm920t_handle_cache_info_command(struct command_context_s *cmd_ctx, char *c
return armv4_5_handle_cache_info_command(cmd_ctx, &arm920t->armv4_5_mmu.armv4_5_cache);
}
-int arm920t_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
-{
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm9tdmi_common_t *arm9tdmi;
- arm920t_common_t *arm920t;
- arm_jtag_t *jtag_info;
-
- if (arm920t_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm920t) != ERROR_OK)
- {
- command_print(cmd_ctx, "current target isn't an ARM920t target");
- return ERROR_OK;
- }
-
- jtag_info = &arm7_9->jtag_info;
-
- if (target->state != TARGET_HALTED)
- {
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
- return ERROR_OK;
- }
-
- return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm920t->armv4_5_mmu);
-}
-
int arm920t_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 3c80802..9d2404e 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -33,7 +33,6 @@
/* cli handling */
int arm926ejs_handle_cp15_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm926ejs_handle_cp15i_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-int arm926ejs_handle_virt2phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm926ejs_handle_md_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int arm926ejs_handle_mw_phys_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
@@ -775,7 +774,6 @@ int arm926ejs_register_commands(struct command_context_s *cmd_ctx)
register_command(cmd_ctx, arm926ejs_cmd, "cp15", arm926ejs_handle_cp15_command, COMMAND_EXEC, "display/modify cp15 register <opcode_1> <opcode_2> <CRn> <CRm> [value]");
register_command(cmd_ctx, arm926ejs_cmd, "cache_info", arm926ejs_handle_cache_info_command, COMMAND_EXEC, "display information about target caches");
- register_command(cmd_ctx, arm926ejs_cmd, "virt2phys", arm926ejs_handle_virt2phys_command, COMMAND_EXEC, "translate va to pa <va>");
register_command(cmd_ctx, arm926ejs_cmd, "mdw_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory words <physical addr> [count]");
register_command(cmd_ctx, arm926ejs_cmd, "mdh_phys", arm926ejs_handle_md_phys_command, COMMAND_EXEC, "display memory half-words <physical addr> [count]");
@@ -870,32 +868,6 @@ int arm926ejs_handle_cache_info_command(struct command_context_s *cmd_ctx, char
return armv4_5_handle_cache_info_command(cmd_ctx, &arm926ejs->armv4_5_mmu.armv4_5_cache);
}
-int arm926ejs_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
-{
- target_t *target = get_current_target(cmd_ctx);
- armv4_5_common_t *armv4_5;
- arm7_9_common_t *arm7_9;
- arm9tdmi_common_t *arm9tdmi;
- arm926ejs_common_t *arm926ejs;
- arm_jtag_t *jtag_info;
-
- if (arm926ejs_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi, &arm926ejs) != ERROR_OK)
- {
- command_print(cmd_ctx, "current target isn't an ARM926EJ-S target");
- return ERROR_OK;
- }
-
- jtag_info = &arm7_9->jtag_info;
-
- if (target->state != TARGET_HALTED)
- {
- command_print(cmd_ctx, "target must be stopped for \"%s\" command", cmd);
- return ERROR_OK;
- }
-
- return armv4_5_mmu_handle_virt2phys_command(cmd_ctx, cmd, args, argc, target, &arm926ejs->armv4_5_mmu);
-}
-
int arm926ejs_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
diff --git a/src/target/armv4_5_mmu.c b/src/target/armv4_5_mmu.c
index e64021e..3380012 100644
--- a/src/target/armv4_5_mmu.c
+++ b/src/target/armv4_5_mmu.c
@@ -170,51 +170,6 @@ int armv4_5_mmu_write_physical(target_t *target, armv4_5_mmu_common_t *armv4_5_m
return retval;
}
-int armv4_5_mmu_handle_virt2phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu)
-{
- uint32_t va;
- uint32_t pa;
- int type;
- uint32_t cb;
- int domain;
- uint32_t ap;
-
- if (target->state != TARGET_HALTED)
- {
- command_print(cmd_ctx, "target must be stopped for \"virt2phys\" command");
- return ERROR_OK;
- }
-
- if (argc == 0)
- {
- command_print(cmd_ctx, "usage: virt2phys <virtual address>");
- return ERROR_OK;
- }
-
- if (argc == 1)
- {
- va = strtoul(args[0], NULL, 0);
- pa = armv4_5_mmu_translate_va(target, armv4_5_mmu, va, &type, &cb, &domain, &ap);
- if (type == -1)
- {
- switch (pa)
- {
- case ERROR_TARGET_TRANSLATION_FAULT:
- command_print(cmd_ctx, "no valid translation for 0x%8.8" PRIx32 "", va);
- break;
- default:
- command_print(cmd_ctx, "unknown translation error");
- }
- return ERROR_OK;
- }
-
- command_print(cmd_ctx, "0x%8.8" PRIx32 " -> 0x%8.8" PRIx32 ", type: %s, cb: %i, domain: %d, ap: %2.2x",
- va, pa, armv4_5_mmu_page_type_names[type], (int)cb, domain, (int)ap);
- }
-
- return ERROR_OK;
-}
-
int armv4_5_mmu_handle_md_phys_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc, target_t *target, armv4_5_mmu_common_t *armv4_5_mmu)
{
int count = 1;
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 16 ++++++----
src/target/arm926ejs.c | 29 ++++++++++++++++-
src/target/target.c | 75 +++++++++++++++++++++++++++++++++++++++------
src/target/target_type.h | 19 +++++++++++
4 files changed, 121 insertions(+), 18 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
