openocd-commit — OpenOCD commit maling list - read only

[Openocd-svn] r2739 - trunk/src/jtag

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-21 02:04:35 +0200 (Mon, 21 Sep 2009)
New Revision: 2739

Modified:
   trunk/src/jtag/core.c
Log:
Update the jtag-examine_chain() logic to verify that there's no
garbage after the expected data (from the TAPs' BYPASS or IDCODE
registers).

NOTE that there was previously some code that looked like it was
trying to do this ... which didn't work, because it was looping
over the list of expected TAPs, and never checked *after* that
list completed!  That could hide some *nasty* reset issues...

Also replace a now-obsolete scanchain length test with one that
behaves correctly; and update reporting of unexpected IDCODEs.


Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-09-20 23:54:13 UTC (rev 2738)
+++ trunk/src/jtag/core.c	2009-09-21 00:04:35 UTC (rev 2739)
@@ -837,13 +837,18 @@
 	alive_sleep(us/1000);
 }
 
-/// maximum number of JTAG devices expected in the chain
+/* Maximum number of enabled JTAG devices we expect in the scan chain,
+ * plus one (to detect garbage at the end).  Devices that don't support
+ * IDCODE take up fewer bits, possibly allowing a few more devices.
+ */
 #define JTAG_MAX_CHAIN_SIZE 20
 
 #define EXTRACT_MFG(X)  (((X) & 0xffe) >> 1)
 #define EXTRACT_PART(X) (((X) & 0xffff000) >> 12)
 #define EXTRACT_VER(X)  (((X) & 0xf0000000) >> 28)
 
+#define END_OF_CHAIN_FLAG	0x000000ff
+
 static int jtag_examine_chain_execute(uint8_t *idcode_buffer, unsigned num_idcode)
 {
 	scan_field_t field = {
@@ -855,7 +860,7 @@
 
 	// initialize to the end of chain ID value
 	for (unsigned i = 0; i < JTAG_MAX_CHAIN_SIZE; i++)
-		buf_set_u32(idcode_buffer, i * 32, 32, 0x000000FF);
+		buf_set_u32(idcode_buffer, i * 32, 32, END_OF_CHAIN_FLAG);
 
 	jtag_add_plain_dr_scan(1, &field, TAP_DRPAUSE);
 	jtag_add_tlr();
@@ -899,7 +904,12 @@
 
 static bool jtag_idcode_is_final(uint32_t idcode)
 {
-		return idcode == 0x000000FF || idcode == 0xFFFFFFFF;
+	/*
+	 * Some devices, such as AVR8, will output all 1's instead
+	 * of TDI input value at end of chain.  Allow those values
+	 * instead of failing.
+	 */
+	return idcode == END_OF_CHAIN_FLAG || idcode == 0xFFFFFFFF;
 }
 
 /**
@@ -907,8 +917,9 @@
  * all as expected, but a single JTAG device requires only 64 bits to be
  * read back correctly.  This can help identify and diagnose problems
  * with the JTAG chain earlier, gives more helpful/explicit error messages.
+ * Returns TRUE iff garbage was found.
  */
-static void jtag_examine_chain_end(uint8_t *idcodes, unsigned count, unsigned max)
+static bool jtag_examine_chain_end(uint8_t *idcodes, unsigned count, unsigned max)
 {
 	bool triggered = false;
 	for (; count < max - 31; count += 32)
@@ -921,19 +932,14 @@
 					count, (unsigned int)idcode);
 		triggered = true;
 	}
+	return triggered;
 }
 
 static bool jtag_examine_chain_match_tap(const struct jtag_tap_s *tap)
 {
-	if (0 == tap->expected_ids_cnt)
-	{
-		/// @todo Enable LOG_INFO to ask for reports about unknown TAP IDs.
-#if 0
-		LOG_INFO("Uknown JTAG TAP ID: 0x%08x", tap->idcode)
-		LOG_INFO("Please report the chip name and reported ID code to the openocd project");
-#endif
+	/* ignore expected BYPASS codes; warn otherwise */
+	if (0 == tap->expected_ids_cnt && !tap->idcode)
 		return true;
-	}
 
 	/* Loop over the expected identification codes and test for a match */
 	uint8_t ii;
@@ -944,7 +950,7 @@
 	}
 
 	/* If none of the expected ids matched, log an error */
-	jtag_examine_chain_display(LOG_LVL_ERROR, "got",
+	jtag_examine_chain_display(LOG_LVL_ERROR, "UNEXPECTED",
 			tap->dotted_name, tap->idcode);
 	for (ii = 0; ii < tap->expected_ids_cnt; ii++)
 	{
@@ -962,10 +968,12 @@
 static int jtag_examine_chain(void)
 {
 	uint8_t idcode_buffer[JTAG_MAX_CHAIN_SIZE * 4];
-	unsigned device_count = 0;
+	unsigned bit_count;
 
+	/* DR scan to collect BYPASS or IDCODE register contents.
+	 * Then make sure the scan data has both ones and zeroes.
+	 */
 	jtag_examine_chain_execute(idcode_buffer, JTAG_MAX_CHAIN_SIZE);
-
 	if (!jtag_examine_chain_check(idcode_buffer, JTAG_MAX_CHAIN_SIZE))
 		return ERROR_JTAG_INIT_FAILED;
 
@@ -977,7 +985,7 @@
 		return ERROR_JTAG_INIT_FAILED;
 	}
 
-	for (unsigned bit_count = 0;
+	for (bit_count = 0;
 			tap && bit_count < (JTAG_MAX_CHAIN_SIZE * 32) - 31;
 			tap = jtag_tap_next_enabled(tap))
 	{
@@ -995,26 +1003,13 @@
 		}
 		else
 		{
+			/* Friendly devices support IDCODE */
 			tap->hasidcode = true;
-
-			/*
-			 * End of chain (invalid manufacturer ID) some devices, such
-			 * as AVR will output all 1's instead of TDI input value at
-			 * end of chain.
-			 */
-			if (jtag_idcode_is_final(idcode))
-			{
-				jtag_examine_chain_end(idcode_buffer,
-						bit_count + 32, JTAG_MAX_CHAIN_SIZE * 32);
-				break;
-			}
-
 			jtag_examine_chain_display(LOG_LVL_INFO, "tap/device found",
 					tap->dotted_name, idcode);
 
 			bit_count += 32;
 		}
-		device_count++;
 		tap->idcode = idcode;
 
 		// ensure the TAP ID does matches what was expected
@@ -1022,17 +1017,23 @@
 			return ERROR_JTAG_INIT_FAILED;
 	}
 
-	/* see if number of discovered devices matches configuration */
-	if (device_count != jtag_tap_count_enabled())
-	{
-		LOG_ERROR("number of discovered devices in JTAG chain (%i) "
-				"does not match (enabled) configuration (%i), total taps: %d",
-				device_count, jtag_tap_count_enabled(), jtag_tap_count());
-		LOG_ERROR("check the config file and ensure proper JTAG communication"
-				" (connections, speed, ...)");
+	/* Fail if too many TAPs were enabled for us to verify them all. */
+	if (tap) {
+		LOG_ERROR("Too many TAPs enabled; '%s' ignored.",
+				tap->dotted_name);
 		return ERROR_JTAG_INIT_FAILED;
 	}
 
+	/* After those IDCODE or BYPASS register values should be
+	 * only the data we fed into the scan chain.
+	 */
+	if (jtag_examine_chain_end(idcode_buffer, bit_count,
+			8 * sizeof(idcode_buffer))) {
+		LOG_ERROR("double-check your JTAG setup (interface, "
+				"speed, TAPs, ...)");
+		return ERROR_JTAG_INIT_FAILED;
+	}
+
 	return ERROR_OK;
 }
 

[Openocd-svn] r2738 - trunk/src/flash

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-21 01:54:13 +0200 (Mon, 21 Sep 2009)
New Revision: 2738

Modified:
   trunk/src/flash/stm32x.c
Log:
Enhancement: stm32 flash protection error message

This patch modifies an error message which, in its original state,
I find somewhat unhelpful. So a small hint was added.

Signed-off-by: Johnny Halfmoon <jhalfmoon at milksnot.com>


Modified: trunk/src/flash/stm32x.c
===================================================================
--- trunk/src/flash/stm32x.c	2009-09-20 21:17:08 UTC (rev 2737)
+++ trunk/src/flash/stm32x.c	2009-09-20 23:54:13 UTC (rev 2738)
@@ -410,7 +410,7 @@
 
 	if ((first && (first % stm32x_info->ppage_size)) || ((last + 1) && (last + 1) % stm32x_info->ppage_size))
 	{
-		LOG_WARNING("sector start/end incorrect - stm32 has %dK sector protection", stm32x_info->ppage_size);
+		LOG_WARNING("Error: start and end sectors must be on a %d sector boundary", stm32x_info->ppage_size);
 		return ERROR_FLASH_SECTOR_INVALID;
 	}
 

[Openocd-svn] r2737 - trunk/doc

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-20 23:17:08 +0200 (Sun, 20 Sep 2009)
New Revision: 2737

Modified:
   trunk/doc/openocd.texi
Log:
Update the User's Guide to cover the scan chain verification step
done on exit from the config stage, how JTAG clocking issues can
trigger errors there, and how to avoid such problems.


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-09-20 07:55:11 UTC (rev 2736)
+++ trunk/doc/openocd.texi	2009-09-20 21:17:08 UTC (rev 2737)
@@ -486,17 +486,29 @@
 --pipe       | -p       use pipes when talking to gdb
 @end verbatim
 
-By default OpenOCD reads the file configuration file ``openocd.cfg''
+By default OpenOCD reads the file configuration file @file{openocd.cfg}
 in the current directory.  To specify a different (or multiple)
 configuration file, you can use the ``-f'' option. For example:
 
 @example
-  openocd -f config1.cfg -f config2.cfg -f config3.cfg
+openocd -f config1.cfg -f config2.cfg -f config3.cfg
 @end example
 
-Once started, OpenOCD runs as a daemon, waiting for connections from
-clients (Telnet, GDB, Other).
+OpenOCD starts by processing the configuration commands provided
+on the command line or in @file{openocd.cfg}.
+@xref{Configuration Stage}.
+At the end of the configuration stage it verifies the JTAG scan
+chain defined using those commands; your configuration should
+ensure that this always succeeds.
+Normally, OpenOCD then starts running as a daemon.
+Alternatively, commands may be used to terminate the configuration
+stage early, perform work (such as updating some flash memory),
+and then shut down without acting as a daemon.
 
+Once OpenOCD starts running as a daemon, it waits for connections from
+clients (Telnet, GDB, Other) and processes the commands issued through
+those channels.
+
 If you are having problems, you can enable internal debug messages via
 the ``-d'' option.
 
@@ -1061,8 +1073,16 @@
 @subsection JTAG Clock Rate
 
 Before your @code{reset-init} handler has set up
-the PLLs and clocking, you may need to use
-a low JTAG clock rate; then you'd increase it later.
+the PLLs and clocking, you may need to run with
+a low JTAG clock rate.
+@xref{JTAG Speed}.
+Then you'd increase that rate after your handler has
+made it possible to use the faster JTAG clock.
+When the initial low speed is board-specific, for example
+because it depends on a board-specific oscillator speed, then
+you should probably set it up in the board config file;
+if it's target-specific, it belongs in the target config file.
+
 For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
 @uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
 is one sixth of the CPU clock; or one eighth for ARM11 cores.
@@ -1252,6 +1272,24 @@
 @code{reset-deassert-post} event handler that writes a chip
 register to report that JTAG debugging is being done.
 
+JTAG clocking constraints often change during reset, and in
+some cases target config files (rather than board config files)
+are the right places to handle some of those issues.
+For example, immediately after reset most chips run using a
+slower clock than they will use later.
+That means that after reset (and potentially, as OpenOCD
+first starts up) they must use a slower JTAG clock rate
+than they will use later.
+@xref{JTAG Speed}.
+
+@quotation Important
+When you are debugging code that runs right after chip
+reset, getting these issues right is critical.
+In particular, if you see intermittent failures when
+OpenOCD verifies the scan chain after reset,
+look at how you are setting up JTAG clocking.
+@end quotation
+
 @subsection ARM Core Specific Hacks
 
 If the chip has a DCC, enable it. If the chip is an ARM9 with some
@@ -1298,6 +1336,7 @@
 used to specify what TCP/IP ports are used, and how GDB should be
 supported.
 
+@anchor{Configuration Stage}
 @section Configuration Stage
 @cindex configuration stage
 @cindex config command
@@ -1318,6 +1357,18 @@
 After it leaves this stage, configuration commands may no
 longer be issued.
 
+The first thing OpenOCD does after leaving the configuration
+stage is to verify that it can talk to the scan chain
+(list of TAPs) which has been configured.
+It will warn if it doesn't find TAPs it expects to find,
+or finds TAPs that aren't supposed to be there.
+You should see no errors at this point.
+If you see errors, resolve them by correcting the
+commands you used to configure the server.
+Common errors include using an initial JTAG speed that's too
+fast, and not providing the right IDCODE values for the TAPs
+on the scan chain.
+
 @deffn {Config Command} init
 This command terminates the configuration stage and
 enters the normal command mode. This can be useful to add commands to
@@ -1787,10 +1838,29 @@
 oscillators used, the chip, the board design, and sometimes
 power management software that may be active.
 
-The speed used during reset can be adjusted using pre_reset
-and post_reset event handlers.
+The speed used during reset, and the scan chain verification which
+follows reset, can be adjusted using a @code{reset-start}
+target event handler.
+It can then be reconfigured to a faster speed by a
+@code{reset-init} target event handler after it reprograms those
+CPU clocks, or manually (if something else, such as a boot loader,
+sets up those clocks).
 @xref{Target Events}.
+When the initial low JTAG speed is a chip characteristic, perhaps
+because of a required oscillator speed, provide such a handler
+in the target config file.
+When that speed is a function of a board-specific characteristic
+such as which speed oscillator is used, it belongs in the board
+config file instead.
+In both cases it's safest to also set the initial JTAG clock rate
+to that same slow speed, so that OpenOCD never starts up using a
+clock speed that's faster than the scan chain can support.
 
+@example
+jtag_rclk 3000
+$_TARGET.cpu configure -event reset-start @{ jtag_rclk 3000 @}
+@end example
+
 If your system supports adaptive clocking (RTCK), configuring
 JTAG to use that is probably the most robust approach.
 However, it introduces delays to synchronize clocks; so it
@@ -2892,20 +2962,16 @@
 @item @b{reset-assert-pre}
 @* Issued as part of @command{reset} processing
 after SRST and/or TRST were activated and deactivated,
-but before reset is asserted on the tap.
+but before SRST alone is re-asserted on the tap.
 @item @b{reset-assert-post}
 @* Issued as part of @command{reset} processing
-when reset is asserted on the tap.
+when SRST is asserted on the tap.
 @item @b{reset-deassert-pre}
 @* Issued as part of @command{reset} processing
-when reset is about to be released on the tap.
-
-For some chips, this may be a good place to make sure
-the JTAG clock is slow enough to work before the PLL
-has been set up to allow faster JTAG speeds.
+when SRST is about to be released on the tap.
 @item @b{reset-deassert-post}
 @* Issued as part of @command{reset} processing
-when reset has been released on the tap.
+when SRST has been released on the tap.
 @item @b{reset-end}
 @* Issued as the final step in @command{reset} processing.
 @ignore
@@ -2921,9 +2987,14 @@
 This is where you would configure PLLs and clocking, set up DRAM so
 you can download programs that don't fit in on-chip SRAM, set up pin
 multiplexing, and so on.
+(You may be able to switch to a fast JTAG clock rate here, after
+the target clocks are fully set up.)
 @item @b{reset-start}
 @* Issued as part of @command{reset} processing
 before either SRST or TRST are activated.
+
+This is the most robust place to switch to a low JTAG clock rate, if
+SRST disables PLLs needed to use a fast clock.
 @ignore
 @item @b{reset-wait-pos}
 @* Currently not used

[Openocd-svn] r2736 - in trunk/src: jtag target

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-20 09:55:11 +0200 (Sun, 20 Sep 2009)
New Revision: 2736

Modified:
   trunk/src/jtag/core.c
   trunk/src/jtag/tcl.c
   trunk/src/target/target.c
Log:
Debug message updates:

 - Shrink messaging during resets, primarily by getting rid of
   "nothing happened" noise that hides *useful* information.

 - Improve: the "no IDCODE" message by identifying which tap only
   supports BYPASS; and the TAP event strings.

Related minor code updates:

 - Remove two needless tests when examining the chain:  we know
   we have a TAP, and that all TAPs have names.

 - Clean up two loops, turning "while"s into "for"s which better
   show what's actually being done.


Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-09-20 07:46:22 UTC (rev 2735)
+++ trunk/src/jtag/core.c	2009-09-20 07:55:11 UTC (rev 2736)
@@ -60,9 +60,9 @@
 
 static const char *jtag_event_strings[] =
 {
-	[JTAG_TRST_ASSERTED] = "JTAG controller reset (TLR or TRST)",
+	[JTAG_TRST_ASSERTED] = "TAP reset",
 	[JTAG_TAP_EVENT_ENABLE] = "TAP enabled",
-	[JTAG_TAP_EVENT_POST_RESET] = "post reset",
+	[JTAG_TAP_EVENT_POST_RESET] = "TAP post reset",
 	[JTAG_TAP_EVENT_DISABLE] = "TAP disabled",
 };
 
@@ -820,9 +820,6 @@
 {
 	jtag_tap_t *tap = priv;
 
-	LOG_DEBUG("TAP %s event %s", tap->dotted_name,
-			jtag_event_strings[event]);
-
 	if (event == JTAG_TRST_ASSERTED)
 	{
 		tap->enabled = !tap->disabled_after_reset;
@@ -943,15 +940,10 @@
 	for (ii = 0; ii < tap->expected_ids_cnt; ii++)
 	{
 		if (tap->idcode == tap->expected_ids[ii])
-			break;
+			return true;
 	}
 
 	/* If none of the expected ids matched, log an error */
-	if (ii != tap->expected_ids_cnt)
-	{
-		LOG_DEBUG("JTAG Tap/device matched");
-		return true;
-	}
 	jtag_examine_chain_display(LOG_LVL_ERROR, "got",
 			tap->dotted_name, tap->idcode);
 	for (ii = 0; ii < tap->expected_ids_cnt; ii++)
@@ -994,7 +986,8 @@
 		if ((idcode & 1) == 0)
 		{
 			/* LSB must not be 0, this indicates a device in bypass */
-			LOG_WARNING("Tap/Device does not have IDCODE");
+			LOG_WARNING("TAP %s does not have IDCODE",
+					tap->dotted_name);
 			idcode = 0;
 			tap->hasidcode = false;
 
@@ -1017,15 +1010,11 @@
 			}
 
 			jtag_examine_chain_display(LOG_LVL_INFO, "tap/device found",
-					tap ? tap->dotted_name : "(not-named)",
-					idcode);
+					tap->dotted_name, idcode);
 
 			bit_count += 32;
 		}
 		device_count++;
-		if (!tap)
-			continue;
-
 		tap->idcode = idcode;
 
 		// ensure the TAP ID does matches what was expected

Modified: trunk/src/jtag/tcl.c
===================================================================
--- trunk/src/jtag/tcl.c	2009-09-20 07:46:22 UTC (rev 2735)
+++ trunk/src/jtag/tcl.c	2009-09-20 07:55:11 UTC (rev 2736)
@@ -358,14 +358,9 @@
 static void jtag_tap_handle_event(jtag_tap_t *tap, enum jtag_event e)
 {
 	jtag_tap_event_action_t * jteap;
-	int done;
 
-	jteap = tap->event_action;
-
-	done = 0;
-	while (jteap) {
+	for (jteap = tap->event_action; jteap != NULL; jteap = jteap->next) {
 		if (jteap->event == e) {
-			done = 1;
 			LOG_DEBUG("JTAG tap: %s event: %d (%s) action: %s\n",
 					tap->dotted_name,
 					e,
@@ -386,15 +381,7 @@
 				break;
 			}
 		}
-
-		jteap = jteap->next;
 	}
-
-	if (!done) {
-		LOG_DEBUG("event %d %s - no action",
-				e,
-				Jim_Nvp_value2name_simple(nvp_jtag_tap_event, e)->name);
-	}
 }
 
 

Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c	2009-09-20 07:46:22 UTC (rev 2735)
+++ trunk/src/target/target.c	2009-09-20 07:55:11 UTC (rev 2736)
@@ -3409,14 +3409,9 @@
 void target_handle_event(target_t *target, enum target_event e)
 {
 	target_event_action_t *teap;
-	int done;
 
-	teap = target->event_action;
-
-	done = 0;
-	while (teap) {
+	for (teap = target->event_action; teap != NULL; teap = teap->next) {
 		if (teap->event == e) {
-			done = 1;
 			LOG_DEBUG("target: (%d) %s (%s) event: %d (%s) action: %s",
 					   target->target_number,
 					   target->cmd_name,
@@ -3429,13 +3424,7 @@
 				Jim_PrintErrorMessage(interp);
 			}
 		}
-		teap = teap->next;
 	}
-	if (!done) {
-		LOG_DEBUG("event: %d %s - no action",
-				   e,
-				   Jim_Nvp_value2name_simple(nvp_target_event, e)->name);
-	}
 }
 
 enum target_cfg_param {

[Openocd-svn] r2735 - trunk/src/jtag

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-20 09:46:22 +0200 (Sun, 20 Sep 2009)
New Revision: 2735

Modified:
   trunk/src/jtag/tcl.c
Log:
Minor regression bugfix for the jtag_tap_handle_event() case
for disabling TAPs.  We don't actually know how to make any
JRCs which do that yet; but when we do, this will matter.


Modified: trunk/src/jtag/tcl.c
===================================================================
--- trunk/src/jtag/tcl.c	2009-09-19 20:38:38 UTC (rev 2734)
+++ trunk/src/jtag/tcl.c	2009-09-20 07:46:22 UTC (rev 2735)
@@ -373,13 +373,17 @@
 					Jim_GetString(jteap->body, NULL));
 			if (Jim_EvalObj(interp, jteap->body) != JIM_OK) {
 				Jim_PrintErrorMessage(interp);
-			} else {
+			} else switch (e) {
+			case JTAG_TAP_EVENT_ENABLE:
+			case JTAG_TAP_EVENT_DISABLE:
 				/* NOTE:  we currently assume the handlers
 				 * can't fail.  That presumes later code
 				 * will be verifying the scan chains ...
 				 */
-				if (e == JTAG_TAP_EVENT_ENABLE)
-					tap->enabled = true;
+				tap->enabled = (e == JTAG_TAP_EVENT_ENABLE);
+				break;
+			default:
+				break;
 			}
 		}
 

[Openocd-svn] r2734 - trunk/src/target

[<ml...@ma...>]

Author: mlu
Date: 2009-09-19 22:38:38 +0200 (Sat, 19 Sep 2009)
New Revision: 2734

Modified:
   trunk/src/target/cortex_a8.h
Log:
Added  CPUDBG_WCR_BASE define

Modified: trunk/src/target/cortex_a8.h
===================================================================
--- trunk/src/target/cortex_a8.h	2009-09-19 14:50:18 UTC (rev 2733)
+++ trunk/src/target/cortex_a8.h	2009-09-19 20:38:38 UTC (rev 2734)
@@ -53,6 +53,7 @@
 #define CPUDBG_BVR_BASE	0x100
 #define CPUDBG_BCR_BASE	0x140
 #define CPUDBG_WVR_BASE	0x180
+#define CPUDBG_WCR_BASE	0x1C0
 
 #define CPUDBG_OSLAR	0x300
 #define CPUDBG_OSLSR	0x304

[Openocd-svn] r2733 - trunk/src/target

[<ml...@ma...>]

Author: mlu
Date: 2009-09-19 16:50:18 +0200 (Sat, 19 Sep 2009)
New Revision: 2733

Modified:
   trunk/src/target/cortex_a8.c
Log:
Avoid cache invalidation when writing to hardware debug registers

Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-09-19 14:47:53 UTC (rev 2732)
+++ trunk/src/target/cortex_a8.c	2009-09-19 14:50:18 UTC (rev 2733)
@@ -332,6 +332,21 @@
 	return retval;
 }
 
+/* Write to memory mapped registers directly with no cache or mmu handling */
+int cortex_a8_dap_write_memap_register_u32(target_t *target, uint32_t address, uint32_t value)
+{
+	int retval;
+
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
+
+	retval = mem_ap_write_atomic_u32(swjdp, address, value);
+
+	return retval;
+}
+
 /*
  * Cortex-A8 Run control
  */
@@ -1022,10 +1037,10 @@
 		brp_list[brp_i].used = 1;
 		brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
 		brp_list[brp_i].control = control;
-		target_write_u32(target, armv7a->debug_base
+		cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
 				+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
 				brp_list[brp_i].value);
-		target_write_u32(target, armv7a->debug_base
+		cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
 				+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
 				brp_list[brp_i].control);
 		LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
@@ -1088,10 +1103,10 @@
 		brp_list[brp_i].used = 0;
 		brp_list[brp_i].value = 0;
 		brp_list[brp_i].control = 0;
-		target_write_u32(target, armv7a->debug_base
+		cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
 				+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
 				brp_list[brp_i].control);
-		target_write_u32(target, armv7a->debug_base
+		cortex_a8_dap_write_memap_register_u32(target, armv7a->debug_base
 				+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
 				brp_list[brp_i].value);
 	}

[Openocd-svn] r2732 - trunk/tcl/target

[<ml...@ma...>]

Author: mlu
Date: 2009-09-19 16:47:53 +0200 (Sat, 19 Sep 2009)
New Revision: 2732

Modified:
   trunk/tcl/target/omap3530.cfg
Log:
Reduced sleep time after reset 

Modified: trunk/tcl/target/omap3530.cfg
===================================================================
--- trunk/tcl/target/omap3530.cfg	2009-09-19 06:54:01 UTC (rev 2731)
+++ trunk/tcl/target/omap3530.cfg	2009-09-19 14:47:53 UTC (rev 2732)
@@ -43,7 +43,7 @@
 proc omap3_dbginit { } {
      poll off
      reset
-     sleep 500
+     sleep 100
 
      jtag tapenable omap3530.dap
      targets
@@ -53,3 +53,4 @@
      omap3.cpu mww 0x5401d030 0x00002000
      poll on
 }
+

[Openocd-svn] r2731 - trunk/src/jtag

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-19 08:54:01 +0200 (Sat, 19 Sep 2009)
New Revision: 2731

Modified:
   trunk/src/jtag/ft2232.c
Log:
Style cleanup for the updated ft2232_add_pathmove().
Indentation, whitespace, line lengths.


Modified: trunk/src/jtag/ft2232.c
===================================================================
--- trunk/src/jtag/ft2232.c	2009-09-19 06:49:40 UTC (rev 2730)
+++ trunk/src/jtag/ft2232.c	2009-09-19 06:54:01 UTC (rev 2731)
@@ -773,38 +773,41 @@
 	/* this loop verifies that the path is legal and logs each state in the path */
 	while (num_states)
 	{
-		unsigned char  tms_byte = 0;       /* zero this on each MPSSE batch */
+		unsigned char	tms_byte = 0;       /* zero this on each MPSSE batch */
+		int		bit_count = 0;
+		int		num_states_batch = num_states > 7 ? 7 : num_states;
 
-		int bit_count = 0;
-
-		int num_states_batch = num_states > 7 ? 7 : num_states;
-
 		/* command "Clock Data to TMS/CS Pin (no Read)" */
 		buffer_write(0x4b);
 
 		/* number of states remaining */
 		buffer_write(num_states_batch - 1);
 
-		while (num_states_batch--)
-		{
-		  if (tap_state_transition(tap_get_state(), false) == path[state_count])
+		while (num_states_batch--) {
+			/* either TMS=0 or TMS=1 must work ... */
+			if (tap_state_transition(tap_get_state(), false)
+						== path[state_count])
 				buf_set_u32(&tms_byte, bit_count++, 1, 0x0);
-		  else if (tap_state_transition(tap_get_state(), true) == path[state_count])
+			else if (tap_state_transition(tap_get_state(), true)
+						== path[state_count])
 				buf_set_u32(&tms_byte, bit_count++, 1, 0x1);
-			else
-			{
-				LOG_ERROR( "BUG: %s -> %s isn't a valid TAP transition", tap_state_name(
-								 tap_get_state() ), tap_state_name(path[state_count]) );
+
+			/* ... or else the caller goofed BADLY */
+			else {
+				LOG_ERROR("BUG: %s -> %s isn't a valid "
+						"TAP state transition",
+					tap_state_name(tap_get_state()),
+					tap_state_name(path[state_count]));
 				exit(-1);
 			}
 
-		  tap_set_state(path[state_count]);
+			tap_set_state(path[state_count]);
 			state_count++;
 			num_states--;
 		}
 
 		buffer_write(tms_byte);
-	}	
+	}
 	tap_set_end_state(tap_get_state());
 }
 

[Openocd-svn] r2730 - in trunk/src: jtag target

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-19 08:49:40 +0200 (Sat, 19 Sep 2009)
New Revision: 2730

Modified:
   trunk/src/jtag/core.c
   trunk/src/target/target.c
Log:
Minor behavior fixes for the two JTAG reset events (C/internal,
and Tcl/external):

 - Reorder so *both* paths (TCK/TMS or TRST) can enable TAPs with
   ICEpick ... first C code flags TAPs that got disabled, then call
   any Tcl code that might want to re-enable them.

 - Always call the C/internal handlers when JTAG operations can be
   issued; previously that wasn't done when TRST was used. 

Plus some small cleanups (whitespace, strings, better messaging
during debug and on some errors) to reset-related code.


Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-09-19 06:42:50 UTC (rev 2729)
+++ trunk/src/jtag/core.c	2009-09-19 06:49:40 UTC (rev 2730)
@@ -446,7 +446,7 @@
 		tap_state_t state)
 {
 	assert(state != TAP_RESET);
-	
+
 	jtag_prelude(state);
 
 	int retval;
@@ -458,7 +458,7 @@
 		tap_state_t state)
 {
 	assert(state != TAP_RESET);
-	
+
 	jtag_prelude(state);
 
 	int retval;
@@ -471,7 +471,6 @@
 		tap_state_t end_state)
 {
 	assert(end_state != TAP_RESET);
-	
 	assert(end_state != TAP_INVALID);
 
 	cmd_queue_cur_state = end_state;
@@ -486,9 +485,9 @@
 	jtag_prelude(TAP_RESET);
 	jtag_set_error(interface_jtag_add_tlr());
 
-	jtag_notify_reset();
-
+	/* NOTE: order here matches TRST path in jtag_add_reset() */
 	jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
+	jtag_notify_reset();
 }
 
 void jtag_add_pathmove(int num_states, const tap_state_t *path)
@@ -684,21 +683,19 @@
 	} else if (jtag_trst != new_trst) {
 		jtag_trst = new_trst;
 		if (jtag_trst) {
-			/* we just asserted nTRST, so we're now in TAP_RESET;
-			 * inform possible listeners about this
-			 *
-			 * REVISIT asserting TRST is less significant than
-			 * being in TAP_RESET ... both entries (TRST, TLR)
-			 * should trigger a callback.
-			 */
 			LOG_DEBUG("TRST line asserted");
 			tap_set_state(TAP_RESET);
-			jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
 		} else {
 			LOG_DEBUG("TRST line released");
 			if (jtag_ntrst_delay)
 				jtag_add_sleep(jtag_ntrst_delay * 1000);
 
+			/* We just asserted nTRST, so we're now in TAP_RESET.
+			 * Inform possible listeners about this, now that
+			 * JTAG instructions and data can be shifted.  This
+			 * sequence must match jtag_add_tlr().
+			 */
+			jtag_call_event_callbacks(JTAG_TRST_ASSERTED);
 			jtag_notify_reset();
 		}
 	}
@@ -823,7 +820,8 @@
 {
 	jtag_tap_t *tap = priv;
 
-	LOG_DEBUG("-");
+	LOG_DEBUG("TAP %s event %s", tap->dotted_name,
+			jtag_event_strings[event]);
 
 	if (event == JTAG_TRST_ASSERTED)
 	{

Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c	2009-09-19 06:42:50 UTC (rev 2729)
+++ trunk/src/target/target.c	2009-09-19 06:49:40 UTC (rev 2730)
@@ -4028,7 +4028,8 @@
 		break;
 	case TS_CMD_RESET:
 		if (goi.argc != 2) {
-			Jim_WrongNumArgs(interp, 2, argv, "t | f|assert | deassert BOOL");
+			Jim_WrongNumArgs(interp, 2, argv,
+					"([tT]|[fF]|assert|deassert) BOOL");
 			return JIM_ERR;
 		}
 		e = Jim_GetOpt_Nvp(&goi, nvp_assert, &n);

[Openocd-svn] r2729 - trunk/doc

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-19 08:42:50 +0200 (Sat, 19 Sep 2009)
New Revision: 2729

Modified:
   trunk/doc/openocd.texi
Log:
Minor tweaks to description of JTAG adapter/dongle issues.


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-09-18 15:11:46 UTC (rev 2728)
+++ trunk/doc/openocd.texi	2009-09-19 06:42:50 UTC (rev 2729)
@@ -250,12 +250,16 @@
 
 @section Choosing a Dongle
 
-There are three things you should keep in mind when choosing a dongle. 
+There are several things you should keep in mind when choosing a dongle.
 
 @enumerate 
-@item @b{Voltage} What voltage is your target? 1.8, 2.8, 3.3, or 5V? Does your dongle support it?
-@item @b{Connection} Printer Ports - Does your computer have one?
-@item @b{Connection} Is that long printer bit-bang cable practical? 
+@item @b{Voltage} What voltage is your target - 1.8, 2.8, 3.3, or 5V?
+Does your dongle support it?  You might need a level converter.
+@item @b{Pinout} What pinout does your target board use?
+Does your dongle support it?  You may be able to use jumper
+wires, or an "octopus" connector, to convert pinouts.
+@item @b{Connection} Does your computer have the USB, printer, or
+Ethernet port needed?
 @item @b{RTCK} Do you require RTCK? Also known as ``adaptive clocking'' 
 @end enumerate
 
@@ -356,6 +360,10 @@
 and the MacGraigor Wiggler. There are many clones and variations of
 these on the market.
 
+Note that parallel ports are becoming much less common, so if you
+have the choice you should probably avoid these adapters in favor
+of USB-based ones.
+
 @itemize @bullet
 
 @item @b{Wiggler} - There are many clones of this.

[Openocd-svn] r2728 - in trunk: src/target tcl/target

[<ml...@ma...>]

Author: mlu
Date: 2009-09-18 17:11:46 +0200 (Fri, 18 Sep 2009)
New Revision: 2728

Modified:
   trunk/src/target/cortex_a8.c
   trunk/tcl/target/omap3530.cfg
Log:
Move Cortex A8 debug access initialisation from omap3530.cfg to cortex_a8.c

Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-09-18 07:09:44 UTC (rev 2727)
+++ trunk/src/target/cortex_a8.c	2009-09-18 15:11:46 UTC (rev 2728)
@@ -120,34 +120,27 @@
  */
 int cortex_a8_init_debug_access(target_t *target)
 {
-#if 0
-# Unlocking the debug registers for modification
-mww 0x54011FB0 0xC5ACCE55 4
+	/* get pointers to arch-specific information */
+	armv4_5_common_t *armv4_5 = target->arch_info;
+	armv7a_common_t *armv7a = armv4_5->arch_info;
+	swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
-# Clear Sticky Power Down status Bit to enable access to
-# the registers in the Core Power Domain
-mdw 0x54011314
-# Check that it is cleared
-mdw 0x54011314
-# Now we can read Core Debug Registers at offset 0x080
-mdw 0x54011080 4
-# We can also read RAM.
-mdw 0x80000000 32
+	int retval;
+	uint32_t dummy;
 
-mdw 0x5401d030
-mdw 0x54011FB8
+	LOG_DEBUG(" ");
 
-# Set DBGEN line for hardware debug (OMAP35xx)
-mww 0x5401d030 0x00002000
-
-#Check AUTHSTATUS
-mdw 0x54011FB8
-
-# Instr enable
-mww 0x54011088 0x2000
-mdw 0x54011080 4
-#endif
-	return ERROR_OK;
+	/* Unlocking the debug registers for modification */
+	/* The debugport might be uninitialised so try twice */
+	retval = mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
+	if (retval != ERROR_OK)
+		mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_LOCKACCESS, 0xC5ACCE55);
+	/* Clear Sticky Power Down status Bit in PRSR to enable access to
+	   the registers in the Core Power Domain */
+	retval = mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_PRSR, &dummy);
+	/* Enabling of instruction execution in debug mode is done in debug_entry code */ 
+	
+	return retval;
 }
 
 int cortex_a8_exec_opcode(target_t *target, uint32_t opcode)
@@ -1441,6 +1434,9 @@
 	LOG_DEBUG("Configured %i hw breakpoint pairs and %i hw watchpoint pairs",
 			cortex_a8->brp_num , cortex_a8->wrp_num);
 
+	/* Configure core debug access */
+	cortex_a8_init_debug_access(target);
+	
 	target->type->examined = 1;
 
 	return retval;
@@ -1559,6 +1555,17 @@
 }
 
 
+static int cortex_a8_handle_dbginit_command(struct command_context_s *cmd_ctx,
+		char *cmd, char **args, int argc)
+{
+	target_t *target = get_current_target(cmd_ctx);
+
+	cortex_a8_init_debug_access(target);
+
+	return ERROR_OK;
+}
+
+
 int cortex_a8_register_commands(struct command_context_s *cmd_ctx)
 {
 	command_t *cortex_a8_cmd;
@@ -1575,5 +1582,9 @@
 			cortex_a8_handle_cache_info_command, COMMAND_EXEC,
 			"display information about target caches");
 
+	register_command(cmd_ctx, cortex_a8_cmd, "dbginit",
+			cortex_a8_handle_dbginit_command, COMMAND_EXEC,
+			"Initialize core debug");
+
 	return retval;
 }

Modified: trunk/tcl/target/omap3530.cfg
===================================================================
--- trunk/tcl/target/omap3530.cfg	2009-09-18 07:09:44 UTC (rev 2727)
+++ trunk/tcl/target/omap3530.cfg	2009-09-18 15:11:46 UTC (rev 2728)
@@ -47,24 +47,9 @@
 
      jtag tapenable omap3530.dap
      targets
-     # sleep 1000
-     # dap apsel 1
-     # sleep 1000
-     # dap apsel 1
-     # dap info 1
-
-     # 0xd401.0000 - ETM
-     # 0xd401.1000 - Cortex-A8
-     # 0xd401.9000 - TPIU (traceport)
-     # 0xd401.b000 - ETB
-     # 0xd401.d000 - DAPCTL
-
-     omap3.cpu mww 0x54011FB0 0xC5ACCE55
-
-     omap3.cpu mdw 0x54011314
-     omap3.cpu mdw 0x54011314
-     # omap3.cpu mdw 0x54011080
-
+     # General Cortex A8 debug initialisation
+     cortex_a8 dbginit
+     # Enable DBGU singal for OMAP353x
      omap3.cpu mww 0x5401d030 0x00002000
      poll on
 }

[Openocd-svn] r2727 - trunk/src/jtag/zy1000

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-18 09:09:44 +0200 (Fri, 18 Sep 2009)
New Revision: 2727

Modified:
   trunk/src/jtag/zy1000/zy1000.c
Log:
remove unused externs

Modified: trunk/src/jtag/zy1000/zy1000.c
===================================================================
--- trunk/src/jtag/zy1000/zy1000.c	2009-09-18 00:11:51 UTC (rev 2726)
+++ trunk/src/jtag/zy1000/zy1000.c	2009-09-18 07:09:44 UTC (rev 2727)
@@ -657,9 +657,6 @@
 
 
 
-extern int jtag_nsrst_delay;
-extern int jtag_ntrst_delay;
-
 int interface_jtag_add_reset(int req_trst, int req_srst)
 {
 	zy1000_reset(req_trst, req_srst);

[Openocd-svn] r2726 - trunk/src/helper

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-18 02:11:51 +0200 (Fri, 18 Sep 2009)
New Revision: 2726

Modified:
   trunk/src/helper/startup.tcl
Log:
Tweak TCL reset script ... mostly improving descriptions of
the various steps, but also calling [target names] only once.


Modified: trunk/src/helper/startup.tcl
===================================================================
--- trunk/src/helper/startup.tcl	2009-09-17 19:20:18 UTC (rev 2725)
+++ trunk/src/helper/startup.tcl	2009-09-18 00:11:51 UTC (rev 2726)
@@ -157,6 +157,7 @@
 }
 
 proc ocd_process_reset_inner { MODE } {
+	set targets [target names]
 
 	# If this target must be halted...
 	set halt -1
@@ -175,26 +176,38 @@
 
 	# Target event handlers *might* change which TAPs are enabled
 	# or disabled, so we fire all of them.  But don't issue any
-	# of the "arp_*" commands, which may issue JTAG transactions,
+	# target "arp_*" commands, which may issue JTAG transactions,
 	# unless we know the underlying TAP is active.
+	#
+	# NOTE:  ARP == "Advanced Reset Process" ... "advanced" is
+	# relative to a previous restrictive scheme
 
-	foreach t [ target names ] {
+	foreach t $targets {
 		# New event script.
 		$t invoke-event reset-start
 	}
 
-	# Init the tap controller.
+	# Use TRST or TMS/TCK operations to reset all the tap controllers.
+	# TAP reset events get reported; they might enable some taps.
+	#
+	# REVISIT arp_init-reset pulses SRST (if it can) with TRST active;
+	# but SRST events aren't reported (unlike "jtag arp_reset", below)
 	jtag arp_init-reset
 
 	# Examine all targets on enabled taps.
-	foreach t [ target names ] {
+	foreach t $targets {
 		if {[jtag tapisenabled [$t cget -chain-position]]} {
 			$t arp_examine
 		}
 	}
 
-	# Let the C code know we are asserting reset.
-	foreach t [ target names ] {
+	# Assert SRST, and report the pre/post events.
+	#
+	# REVISIT this presumes a single-target config, since SRST
+	# applies to the whole device-under-test.  When two targets
+	# both need special setup before SRST, it's only done for
+	# the first one...
+	foreach t $targets {
 		$t invoke-event reset-assert-pre
 		# C code needs to know if we expect to 'halt'
 		if {[jtag tapisenabled [$t cget -chain-position]]} {
@@ -203,8 +216,8 @@
 		$t invoke-event reset-assert-post
 	}
 
-	# Now de-assert reset.
-	foreach t [ target names ] {
+	# Now de-assert SRST, and report the pre/post events.
+	foreach t $targets {
 		$t invoke-event reset-deassert-pre
 		# Again, de-assert code needs to know..
 		if {[jtag tapisenabled [$t cget -chain-position]]} {
@@ -213,9 +226,11 @@
 		$t invoke-event reset-deassert-post
 	}
 
-	# Pass 1 - Now try to halt.
+	# Pass 1 - Now wait for any halt (requested as part of reset
+	# assert/deassert) to happen.  Ideally it takes effect without
+	# first executing any instructions.
 	if { $halt } {
-		foreach t [target names] {
+		foreach t $targets {
 			if {[jtag tapisenabled [$t cget -chain-position]] == 0} {
 				continue
 			}
@@ -239,7 +254,7 @@
 
 	#Pass 2 - if needed "init"
 	if { 0 == [string compare init $MODE] } {
-		foreach t [target names] {
+		foreach t $targets {
 			if {[jtag tapisenabled [$t cget -chain-position]] == 0} {
 				continue
 			}
@@ -252,7 +267,7 @@
 		}
 	}
 
-	foreach t [ target names ] {
+	foreach t $targets {
 		$t invoke-event reset-end
 	}
 }

[Openocd-svn] r2725 - trunk/src/jtag

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-17 21:20:18 +0200 (Thu, 17 Sep 2009)
New Revision: 2725

Modified:
   trunk/src/jtag/core.c
   trunk/src/jtag/tcl.c
Log:
Address codereview comment from Steve Grubb <sg...@re...>:
avoid a duplicate test.

Plus other cleanup in the same code: be "static", sane line lengths
for source and diagnostics, and fix misleading variable names.


Modified: trunk/src/jtag/core.c
===================================================================
--- trunk/src/jtag/core.c	2009-09-17 18:56:17 UTC (rev 2724)
+++ trunk/src/jtag/core.c	2009-09-17 19:20:18 UTC (rev 2725)
@@ -385,7 +385,8 @@
 	interface_jtag_add_callback4(f, data0, data1, data2, data3);
 }
 
-int jtag_check_value_inner(uint8_t *captured, uint8_t *in_check_value, uint8_t *in_check_mask, int num_bits);
+static int jtag_check_value_inner(uint8_t *captured, uint8_t *in_check_value,
+		uint8_t *in_check_mask, int num_bits);
 
 static int jtag_check_value_mask_callback(jtag_callback_data_t data0, jtag_callback_data_t data1, jtag_callback_data_t data2, jtag_callback_data_t data3)
 {
@@ -727,7 +728,8 @@
 	jtag_set_error(interface_jtag_add_sleep(us));
 }
 
-int jtag_check_value_inner(uint8_t *captured, uint8_t *in_check_value, uint8_t *in_check_mask, int num_bits)
+static int jtag_check_value_inner(uint8_t *captured, uint8_t *in_check_value,
+		uint8_t *in_check_mask, int num_bits)
 {
 	int retval = ERROR_OK;
 
@@ -739,39 +741,32 @@
 		compare_failed = buf_cmp(captured, in_check_value, num_bits);
 
 	if (compare_failed) {
-		/* An error handler could have caught the failing check
-		 * only report a problem when there wasn't a handler, or if the handler
-		 * acknowledged the error
-		 */
-		/*
-		LOG_WARNING("TAP %s:",
-					jtag_tap_name(field->tap));
-					*/
-		if (compare_failed)
-		{
-			char *captured_char = buf_to_str(captured, (num_bits > DEBUG_JTAG_IOZ) ? DEBUG_JTAG_IOZ : num_bits, 16);
-			char *in_check_value_char = buf_to_str(in_check_value, (num_bits > DEBUG_JTAG_IOZ) ? DEBUG_JTAG_IOZ : num_bits, 16);
+		char *captured_str, *in_check_value_str;
+		int bits = (num_bits > DEBUG_JTAG_IOZ)
+				? DEBUG_JTAG_IOZ
+				: num_bits;
 
-			if (in_check_mask)
-			{
-				char *in_check_mask_char;
-				in_check_mask_char = buf_to_str(in_check_mask, (num_bits > DEBUG_JTAG_IOZ) ? DEBUG_JTAG_IOZ : num_bits, 16);
-				LOG_WARNING("value captured during scan didn't pass the requested check:");
-				LOG_WARNING("captured: 0x%s check_value: 0x%s check_mask: 0x%s",
-							captured_char, in_check_value_char, in_check_mask_char);
-				free(in_check_mask_char);
-			}
-			else
-			{
-				LOG_WARNING("value captured during scan didn't pass the requested check: captured: 0x%s check_value: 0x%s", captured_char, in_check_value_char);
-			}
+		/* NOTE:  we've lost diagnostic context here -- 'which tap' */
 
-			free(captured_char);
-			free(in_check_value_char);
+		captured_str = buf_to_str(captured, bits, 16);
+		in_check_value_str = buf_to_str(in_check_value, bits, 16);
 
-			retval = ERROR_JTAG_QUEUE_FAILED;
+		LOG_WARNING("Bad value '%s' captured during DR or IR scan:",
+				captured_str);
+		LOG_WARNING(" check_value: 0x%s", in_check_value_str);
+
+		free(captured_str);
+		free(in_check_value_str);
+
+		if (in_check_mask) {
+			char *in_check_mask_str;
+
+			in_check_mask_str = buf_to_str(in_check_mask, bits, 16);
+			LOG_WARNING(" check_mask: 0x%s", in_check_mask_str);
+			free(in_check_mask_str);
 		}
 
+		retval = ERROR_JTAG_QUEUE_FAILED;
 	}
 	return retval;
 }
@@ -974,7 +969,7 @@
 
 /* Try to examine chain layout according to IEEE 1149.1 §12
  */
-int jtag_examine_chain(void)
+static int jtag_examine_chain(void)
 {
 	uint8_t idcode_buffer[JTAG_MAX_CHAIN_SIZE * 4];
 	unsigned device_count = 0;

Modified: trunk/src/jtag/tcl.c
===================================================================
--- trunk/src/jtag/tcl.c	2009-09-17 18:56:17 UTC (rev 2724)
+++ trunk/src/jtag/tcl.c	2009-09-17 19:20:18 UTC (rev 2725)
@@ -75,8 +75,6 @@
 static int handle_verify_jtag_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 static int handle_tms_sequence_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
 
-extern int jtag_examine_chain(void);
-extern int jtag_validate_chain(void);
 
 enum jtag_tap_cfg_param {
 	JCFG_EVENT

[Openocd-svn] r2724 - in trunk: doc src/flash

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-17 20:56:17 +0200 (Thu, 17 Sep 2009)
New Revision: 2724

Modified:
   trunk/doc/openocd.texi
   trunk/src/flash/nand.c
Log:
Minor fixes to NAND code and docs

Erase logic:
 - command invocation
    + treat "nand erase N" (no offset/length) as "erase whole chip N"
    + catch a few more bogus parameter cases, like length == 0 (sigh)
 - nand_erase() should be static
 - on error
    + say which block failed, and if it was a bad block
    + don't give up after the first error; try to erase the rest
 - on success, say which nand device was erased (name isn't unique)

Device list ("nand list"):
 - say how many blocks there are
 - split summary into two lines
 - give example in the docs

Doc tweaks:
 - Use @option{...} for DaVinci's supported hardware ECC options

For the record, I've observed that _sometimes_ erasing bad blocks causes
failure reports, and that manufacturer bad block markers aren't always
erasable (even when erasing their blocks doesn't trigger an error report).


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-09-17 18:52:32 UTC (rev 2723)
+++ trunk/doc/openocd.texi	2009-09-17 18:56:17 UTC (rev 2724)
@@ -3898,9 +3898,17 @@
 @end deffn
 
 @deffn Command {nand list}
-Prints a one-line summary of each device declared
+Prints a summary of each device declared
 using @command{nand device}, numbered from zero.
 Note that un-probed devices show no details.
+@example
+> nand list
+#0: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
+        blocksize: 131072, blocks: 8192
+#1: NAND 1GiB 3,3V 8-bit (Micron) pagesize: 2048, buswidth: 8,
+        blocksize: 131072, blocks: 8192
+>
+@end example
 @end deffn
 
 @deffn Command {nand probe} num
@@ -3950,13 +3958,15 @@
 @end itemize
 @end deffn
 
-@deffn Command {nand erase} num offset length
+@deffn Command {nand erase} num [offset length]
 @cindex NAND erasing
 @cindex NAND programming
 Erases blocks on the specified NAND device, starting at the
 specified @var{offset} and continuing for @var{length} bytes.
 Both of those values must be exact multiples of the device's
 block size, and the region they specify must fit entirely in the chip.
+If those parameters are not specified,
+the whole NAND chip will be erased.
 The @var{num} parameter is the value shown by @command{nand list}.
 
 @b{NOTE:} This command will try to erase bad blocks, when told
@@ -4079,7 +4089,8 @@
 chips from Texas Instruments.
 It takes three extra parameters:
 address of the NAND chip;
-hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix);
+hardware ECC mode to use (@option{hwecc1},
+@option{hwecc4}, @option{hwecc4_infix});
 address of the AEMIF controller on this processor.
 @example
 nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000

Modified: trunk/src/flash/nand.c
===================================================================
--- trunk/src/flash/nand.c	2009-09-17 18:52:32 UTC (rev 2723)
+++ trunk/src/flash/nand.c	2009-09-17 18:56:17 UTC (rev 2724)
@@ -309,8 +309,9 @@
 						 "identify NAND flash device <num>");
 		register_command(cmd_ctx, nand_cmd, "check_bad_blocks", handle_nand_check_bad_blocks_command, COMMAND_EXEC,
 						 "check NAND flash device <num> for bad blocks [<offset> <length>]");
-		register_command(cmd_ctx, nand_cmd, "erase", handle_nand_erase_command, COMMAND_EXEC,
-						 "erase blocks on NAND flash device <num> <offset> <length>");
+		register_command(cmd_ctx, nand_cmd, "erase",
+				handle_nand_erase_command, COMMAND_EXEC,
+				"erase blocks on NAND flash device <num> [<offset> <length>]");
 		register_command(cmd_ctx, nand_cmd, "dump", handle_nand_dump_command, COMMAND_EXEC,
 						 "dump from NAND flash device <num> <filename> "
 						 "<offset> <length> [oob_raw | oob_only]");
@@ -637,7 +638,7 @@
 	return ERROR_OK;
 }
 
-int nand_erase(struct nand_device_s *device, int first_block, int last_block)
+static int nand_erase(struct nand_device_s *device, int first_block, int last_block)
 {
 	int i;
 	uint32_t page;
@@ -712,8 +713,11 @@
 
 		if (status & 0x1)
 		{
-			LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status);
-			return ERROR_NAND_OPERATION_FAILED;
+			LOG_ERROR("didn't erase %sblock %d; status: 0x%2.2x",
+					(device->blocks[i].is_bad == 1)
+						? "bad " : "",
+					i, status);
+			/* continue; other blocks might still be erasable */
 		}
 
 		device->blocks[i].is_erased = 1;
@@ -1075,8 +1079,12 @@
 	for (p = nand_devices, i = 0; p; p = p->next, i++)
 	{
 		if (p->device)
-			command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
-				i, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
+			command_print(cmd_ctx, "#%i: %s (%s) "
+				"pagesize: %i, buswidth: %i,\n\t"
+				"blocksize: %i, blocks: %i",
+				i, p->device->name, p->manufacturer->name,
+				p->page_size, p->bus_width,
+				p->erase_size, p->num_blocks);
 		else
 			command_print(cmd_ctx, "#%i: not probed", i);
 	}
@@ -1197,7 +1205,7 @@
 	nand_device_t *p;
 	int retval;
 
-	if (argc != 3)
+	if (argc != 1 && argc != 3)
 	{
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
@@ -1210,27 +1218,37 @@
 		unsigned long offset;
 		unsigned long length;
 
-		offset = strtoul(args[1], &cp, 0);
-		if (*cp || offset == ULONG_MAX || offset % p->erase_size)
-		{
-			return ERROR_INVALID_ARGUMENTS;
-		}
-		offset /= p->erase_size;
+		/* erase specified part of the chip; or else everything */
+		if (argc == 3) {
+			unsigned long size = p->erase_size * p->num_blocks;
 
-		length = strtoul(args[2], &cp, 0);
-		if (*cp || length == ULONG_MAX || length % p->erase_size)
-		{
-			return ERROR_INVALID_ARGUMENTS;
+			offset = strtoul(args[1], &cp, 0);
+			if (*cp || (offset == ULONG_MAX)
+					|| (offset % p->erase_size) != 0
+					|| offset >= size)
+				return ERROR_INVALID_ARGUMENTS;
+
+			length = strtoul(args[2], &cp, 0);
+			if (*cp || (length == ULONG_MAX)
+					|| (length == 0)
+					|| (length % p->erase_size) != 0
+					|| (length + offset) > size)
+				return ERROR_INVALID_ARGUMENTS;
+
+			offset /= p->erase_size;
+			length /= p->erase_size;
+		} else {
+			offset = 0;
+			length = p->num_blocks;
 		}
-		length -= 1;
-		length /= p->erase_size;
 
-		retval = nand_erase(p, offset, offset + length);
+		retval = nand_erase(p, offset, offset + length - 1);
 		if (retval == ERROR_OK)
 		{
-			command_print(cmd_ctx, "successfully erased blocks "
-					"%lu to %lu on NAND flash device '%s'",
-					offset, offset + length, p->device->name);
+			command_print(cmd_ctx, "erased blocks %lu to %lu "
+					"on NAND flash device #%s '%s'",
+					offset, offset + length,
+					args[0], p->device->name);
 		}
 		else if (retval == ERROR_NAND_OPERATION_FAILED)
 		{

[Openocd-svn] r2723 - trunk/src/helper

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-17 20:52:32 +0200 (Thu, 17 Sep 2009)
New Revision: 2723

Modified:
   trunk/src/helper/jim.c
Log:
Fix coredump seen in some code paths.


Modified: trunk/src/helper/jim.c
===================================================================
--- trunk/src/helper/jim.c	2009-09-17 12:25:53 UTC (rev 2722)
+++ trunk/src/helper/jim.c	2009-09-17 18:52:32 UTC (rev 2723)
@@ -2828,6 +2828,9 @@
     int i;
     struct ScriptObj *script = (void*) objPtr->internalRep.ptr;
 
+    if (!script)
+	    return;
+
     script->inUse--;
     if (script->inUse != 0) return;
     for (i = 0; i < script->len; i++) {

[Openocd-svn] r2722 - trunk/src/jtag

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-17 14:25:53 +0200 (Thu, 17 Sep 2009)
New Revision: 2722

Modified:
   trunk/src/jtag/ft2232.c
Log:
michal smulski <mic...@oo...> fix regression in jtag_add_pathmove() which broke arm11 in r1825. Other uses of jtag_add_pathmove are svn + xsvf + xscale...

Modified: trunk/src/jtag/ft2232.c
===================================================================
--- trunk/src/jtag/ft2232.c	2009-09-17 11:44:14 UTC (rev 2721)
+++ trunk/src/jtag/ft2232.c	2009-09-17 12:25:53 UTC (rev 2722)
@@ -766,33 +766,45 @@
  */
 static void ft2232_add_pathmove(tap_state_t* path, int num_states)
 {
-	int			tms_bits = 0;
-	int			state_ndx;
-	tap_state_t	walker = tap_get_state();
+	int state_count = 0;
 
 	assert((unsigned) num_states <= 32u);		/* tms_bits only holds 32 bits */
 
 	/* this loop verifies that the path is legal and logs each state in the path */
-	for (state_ndx = 0; state_ndx < num_states;  ++state_ndx)
+	while (num_states)
 	{
-		tap_state_t	desired_next_state = path[state_ndx];
+		unsigned char  tms_byte = 0;       /* zero this on each MPSSE batch */
 
-		if (tap_state_transition(walker, false) == desired_next_state)
-			;	/* bit within tms_bits at index state_ndx is already zero */
-		else if (tap_state_transition(walker, true) == desired_next_state)
-			tms_bits |= (1 << state_ndx);
-		else
+		int bit_count = 0;
+
+		int num_states_batch = num_states > 7 ? 7 : num_states;
+
+		/* command "Clock Data to TMS/CS Pin (no Read)" */
+		buffer_write(0x4b);
+
+		/* number of states remaining */
+		buffer_write(num_states_batch - 1);
+
+		while (num_states_batch--)
 		{
-			LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition",
-					tap_state_name(walker), tap_state_name(desired_next_state));
-			exit(-1);
+		  if (tap_state_transition(tap_get_state(), false) == path[state_count])
+				buf_set_u32(&tms_byte, bit_count++, 1, 0x0);
+		  else if (tap_state_transition(tap_get_state(), true) == path[state_count])
+				buf_set_u32(&tms_byte, bit_count++, 1, 0x1);
+			else
+			{
+				LOG_ERROR( "BUG: %s -> %s isn't a valid TAP transition", tap_state_name(
+								 tap_get_state() ), tap_state_name(path[state_count]) );
+				exit(-1);
+			}
+
+		  tap_set_state(path[state_count]);
+			state_count++;
+			num_states--;
 		}
 
-		walker = desired_next_state;
-	}
-
-	clock_tms(0x4b,  tms_bits, num_states, 0);
-
+		buffer_write(tms_byte);
+	}	
 	tap_set_end_state(tap_get_state());
 }
 

[Openocd-svn] r2721 - trunk/src zy1000/trunk/build zy1000/trunk/build/menu

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-17 13:44:14 +0200 (Thu, 17 Sep 2009)
New Revision: 2721

Modified:
   trunk/src/ecosboard.c
   zy1000/trunk/build/makefw.sh
   zy1000/trunk/build/menu/zy1000menu.xml
Log:
prefix zy1000_reboot command to avoid name conflicts

Modified: trunk/src/ecosboard.c
===================================================================
--- trunk/src/ecosboard.c	2009-09-17 11:23:41 UTC (rev 2720)
+++ trunk/src/ecosboard.c	2009-09-17 11:44:14 UTC (rev 2721)
@@ -503,7 +503,7 @@
 
 	Jim_CreateCommand(httpstate.jim_interp, "log", zylinjtag_Jim_Command_log,
 			NULL, NULL);
-	Jim_CreateCommand(httpstate.jim_interp, "reboot",
+	Jim_CreateCommand(httpstate.jim_interp, "zy1000_reboot",
 			zylinjtag_Jim_Command_reboot, NULL, NULL);
 	Jim_CreateCommand(httpstate.jim_interp, "threads",
 			zylinjtag_Jim_Command_threads, NULL, NULL);

Modified: zy1000/trunk/build/makefw.sh
===================================================================
--- zy1000/trunk/build/makefw.sh	2009-09-17 11:23:41 UTC (rev 2720)
+++ zy1000/trunk/build/makefw.sh	2009-09-17 11:44:14 UTC (rev 2721)
@@ -1,4 +1,4 @@
-arm-elf-objcopy -R .fastbss -O binary src/openocd src/openocd.bin
+arm-elf-objcopy -O binary src/openocd src/openocd.bin
 cat >deflateopenocd.bin $OPENOCD/deflate.bin
 cp src/openocd.bin openocd.bin
 rm -f openocd.bin.gz

Modified: zy1000/trunk/build/menu/zy1000menu.xml
===================================================================
--- zy1000/trunk/build/menu/zy1000menu.xml	2009-09-17 11:23:41 UTC (rev 2720)
+++ zy1000/trunk/build/menu/zy1000menu.xml	2009-09-17 11:44:14 UTC (rev 2721)
@@ -144,7 +144,7 @@
 			<tcl>
 				if {[string compare $form_action "Reboot ZY1000"]==0} {
 					append buffer "Rebooting ZY1000..."
-					reboot
+					zy1000_reboot
 				}
 			</tcl>
 
@@ -188,7 +188,7 @@
 			if {[string compare $form_action "Select and reload"]==0} {
 				capture "trunc /config/settings/openocd.cfg"
 				capture "append_file /config/settings/openocd.cfg script $form_target"
-				reboot 
+				zy1000_reboot 
 			}
 			
 			set form_target [load_target] 
@@ -410,7 +410,7 @@
 	
 				if {[string compare $form_action "Reload"]==0} {
 					append buffer "Reloading Config Scripts...<p>"
-					reboot
+					zy1000_reboot
 				}
 			</tcl>
 			<form enctype="multipart/form-data" action="reload.tcl" method="post">
@@ -1257,7 +1257,7 @@
 					if {[check_firmware $form_filecontent]} {
 						write_firmware $form_filecontent
 						append buffer "<br><div style='font-size:14px;'>Upgraded Zylin JTAG, rebooting (wait ca. 30 seconds)...</div><br>"
-						reboot
+						zy1000_reboot
 					} else {
 						append buffer "<br>Not a valid Zylin JTAG firmware file.<br>"
 					}
@@ -1271,7 +1271,7 @@
 						}
 					}				
 					rmdir /config/settings
-					reboot
+					zy1000_reboot
 					append buffer "Restoring factory settings (wait ca. 30 seconds)...<br>"
 				} else {
 					append buffer {<div style="font-size:14px;">Upgrade Zylin JTAG firmware + reboot. </div><p>}
@@ -1480,13 +1480,13 @@
 					$fp puts -nonewline "$form_ip,$form_mask,$form_gateway"
 					$fp close
 					append buffer "Set $form_ip,$form_mask,$form_gateway to $form_filename. Reloading settings..."
-					reboot
+					zy1000_reboot
 				} elseif {[string compare $form_action "Use DHCP"]==0} {
 					set fp [aio.open $form_filename w];
 					$fp puts -nonewline ""
 					$fp close
 					append buffer "Using DHCP. Reloading settings..."
-					reboot
+					zy1000_reboot
 				} else {
 				</tcl>
 					<form action="zy1000.tcl" method="post"> 

[Openocd-svn] r2720 - in trunk: doc src/jtag src/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-17 13:23:41 +0200 (Thu, 17 Sep 2009)
New Revision: 2720

Modified:
   trunk/doc/openocd.texi
   trunk/src/jtag/jtag.h
   trunk/src/jtag/tcl.c
   trunk/src/target/arm7_9_common.c
Log:
srst_gates_jtag option. at91sam9260 needs retesting, and possibly srst_gates_jtag added to reset_config. Could i.MX27 be a case where srst does not pull trst, but really srst gates jtag clock?

Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-09-17 08:02:43 UTC (rev 2719)
+++ trunk/doc/openocd.texi	2009-09-17 11:23:41 UTC (rev 2720)
@@ -2018,6 +2018,10 @@
 @option{combined} implies both @option{srst_pulls_trst} and
 @option{trst_pulls_srst}.
 
+@option{srst_gates_jtag} indicates that asserting SRST gates the
+JTAG clock. This means that no communication can happen on JTAG
+while SRST is asserted. 
+
 The optional @var{trst_type} and @var{srst_type} parameters allow the
 driver mode of each reset line to be specified.  These values only affect
 JTAG interfaces with support for different driver modes, like the Amontec

Modified: trunk/src/jtag/jtag.h
===================================================================
--- trunk/src/jtag/jtag.h	2009-09-17 08:02:43 UTC (rev 2719)
+++ trunk/src/jtag/jtag.h	2009-09-17 11:23:41 UTC (rev 2720)
@@ -277,6 +277,7 @@
 	RESET_TRST_PULLS_SRST = 0x8,
 	RESET_TRST_OPEN_DRAIN = 0x10,
 	RESET_SRST_PUSH_PULL  = 0x20,
+	RESET_SRST_GATES_JTAG = 0x40,
 };
 
 enum reset_types jtag_get_reset_config(void);

Modified: trunk/src/jtag/tcl.c
===================================================================
--- trunk/src/jtag/tcl.c	2009-09-17 08:02:43 UTC (rev 2719)
+++ trunk/src/jtag/tcl.c	2009-09-17 11:23:41 UTC (rev 2720)
@@ -845,6 +845,14 @@
 		int tmp = 0;
 		int m;
 
+		m = RESET_SRST_GATES_JTAG;
+		tmp = 0;
+		if (strcmp(*args, "srst_gates_jtag") == 0)
+		{
+			tmp = RESET_SRST_GATES_JTAG;
+			goto next;
+		}
+
 		/* signals */
 		m = RESET_HAS_TRST | RESET_HAS_SRST;
 		if (strcmp(*args, "none") == 0)

Modified: trunk/src/target/arm7_9_common.c
===================================================================
--- trunk/src/target/arm7_9_common.c	2009-09-17 08:02:43 UTC (rev 2719)
+++ trunk/src/target/arm7_9_common.c	2009-09-17 11:23:41 UTC (rev 2720)
@@ -1021,6 +1021,17 @@
 		return ERROR_FAIL;
 	}
 
+	/* at this point trst has been asserted/deasserted once. We want to
+	 * program embedded ice while SRST is asserted, but some CPUs gate
+	 * the JTAG clock while SRST is asserted
+	 */
+	bool srst_asserted = false;
+	if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0) && ((jtag_reset_config & RESET_SRST_GATES_JTAG) == 0))
+	{
+		jtag_add_reset(0, 1);
+		srst_asserted = true;
+	}
+
 	if (target->reset_halt)
 	{
 		/*
@@ -1053,7 +1064,7 @@
 	if (jtag_reset_config & RESET_SRST_PULLS_TRST)
 	{
 		jtag_add_reset(1, 1);
-	} else
+	} else if (!srst_asserted)
 	{
 		jtag_add_reset(0, 1);
 	}

[Openocd-svn] r2719 - in trunk: doc src/target

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-17 10:02:43 +0200 (Thu, 17 Sep 2009)
New Revision: 2719

Modified:
   trunk/doc/openocd.texi
   trunk/src/target/arm9tdmi.c
Log:
The "arm9tdmi.c" file is more of a generic ARM9 support file:

 - update comments to say so.
 - update docs to clarify that the "arm9tdmi" command prefix
   is a misnomer.
 - bugfix some messages that wrongly assume only ARM9TDMI
   based processors use this code.


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-09-17 07:56:24 UTC (rev 2718)
+++ trunk/doc/openocd.texi	2009-09-17 08:02:43 UTC (rev 2719)
@@ -4932,13 +4932,18 @@
 and display the result.
 @end deffn
 
-@subsection ARM9TDMI specific commands
-@cindex ARM9TDMI
+@subsection ARM9 specific commands
+@cindex ARM9
 
-Many ARM9-family CPUs are built around ARM9TDMI integer cores,
-or processors resembling ARM9TDMI, and can use these commands.
+ARM9-family cores are built around ARM9TDMI or ARM9E (including ARM9EJS)
+integer processors.
 Such cores include the ARM920T, ARM926EJ-S, and ARM966.
 
+For historical reasons, one command shared by these cores starts
+with the @command{arm9tdmi} prefix.
+This is true even for ARM9E based processors, which implement the
+ARMv5TE architecture instead of ARMv4T.
+
 @c 9-june-2009:  tried this on arm920t, it didn't work.
 @c no-params always lists nothing caught, and that's how it acts.
 

Modified: trunk/src/target/arm9tdmi.c
===================================================================
--- trunk/src/target/arm9tdmi.c	2009-09-17 07:56:24 UTC (rev 2718)
+++ trunk/src/target/arm9tdmi.c	2009-09-17 08:02:43 UTC (rev 2719)
@@ -31,6 +31,16 @@
 #include "target_type.h"
 
 
+/*
+ * NOTE:  this holds code that's used with multiple ARM9 processors:
+ *  - ARM9TDMI (ARMv4T) ... in ARM920, ARM922, and ARM940 cores
+ *  - ARM9E-S (ARMv5TE) ... in ARM946, ARM966, and ARM968 cores
+ *  - ARM9EJS (ARMv5TEJ) ... in ARM926 core
+ *
+ * In short, the file name is a misnomer ... it is NOT specific to
+ * that first generation ARM9 processor, or cores using it.
+ */
+
 #if 0
 #define _DEBUG_INSTRUCTION_EXECUTION_
 #endif
@@ -967,8 +977,12 @@
 	command_t *arm9tdmi_cmd;
 
 	retval = arm7_9_register_commands(cmd_ctx);
-	arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi", NULL, COMMAND_ANY, "arm9tdmi specific commands");
-	register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch", handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC, "catch arm920t vectors ['all'|'none'|'<vec1 vec2 ...>']");
+	arm9tdmi_cmd = register_command(cmd_ctx, NULL, "arm9tdmi",
+			NULL, COMMAND_ANY,
+			"arm9tdmi specific commands");
+	register_command(cmd_ctx, arm9tdmi_cmd, "vector_catch",
+			handle_arm9tdmi_catch_vectors_command, COMMAND_EXEC,
+			"catch arm9 vectors ['all'|'none'|'<vec1 vec2 ...>']");
 
 	return retval;
 }
@@ -985,7 +999,7 @@
 
 	if (arm9tdmi_get_arch_pointers(target, &armv4_5, &arm7_9, &arm9tdmi) != ERROR_OK)
 	{
-		command_print(cmd_ctx, "current target isn't an ARM9TDMI based target");
+		command_print(cmd_ctx, "current target isn't an ARM9 based target");
 		return ERROR_OK;
 	}
 

[Openocd-svn] r2718 - trunk/doc

[dbrownell at B. <dbr...@ma...>]

Author: dbrownell
Date: 2009-09-17 09:56:24 +0200 (Thu, 17 Sep 2009)
New Revision: 2718

Modified:
   trunk/doc/openocd.texi
Log:
Doc update:  mention how ARM's WFI instruction affects
JTAG clocking by gating the core clock, and workarounds.
Most details are with the "halt" command, which is one
of the first places this issue will be noticed.


Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-09-16 18:18:38 UTC (rev 2717)
+++ trunk/doc/openocd.texi	2009-09-17 07:56:24 UTC (rev 2718)
@@ -1055,7 +1055,19 @@
 Before your @code{reset-init} handler has set up
 the PLLs and clocking, you may need to use
 a low JTAG clock rate; then you'd increase it later.
-(The rule of thumb for ARM-based processors is 1/8 the CPU clock.)
+For most ARM-based processors the fastest JTAG clock@footnote{A FAQ
+@uref{http://www.arm.com/support/faqdev/4170.html} gives details.}
+is one sixth of the CPU clock; or one eighth for ARM11 cores.
+Consult chip documentation to determine the peak JTAG clock rate,
+which might be less than that.
+
+@quotation Warning
+On most ARMs, JTAG clock detection is coupled to the core clock, so
+software using a @option{wait for interrupt} operation blocks JTAG access.
+Adaptive clocking provides a partial workaround, but a more complete
+solution just avoids using that instruction with JTAG debuggers.
+@end quotation
+
 If the board supports adaptive clocking, use the @command{jtag_rclk}
 command, in case your board is used with JTAG adapter which
 also supports it.  Otherwise use @command{jtag_khz}.
@@ -1785,9 +1797,10 @@
 speeds.  The speed actually used won't be faster
 than the speed specified.
 
-As a rule of thumb, if you specify a clock rate make
-sure the JTAG clock is no more than @math{1/6th CPU-Clock}.
-This is especially true for synthesized cores (ARMxxx-S).
+Chip data sheets generally include a top JTAG clock rate.
+The actual rate is often a function of a CPU core clock,
+and is normally less than that peak rate.
+For example, most ARM cores accept at most one sixth of the CPU clock.
 
 Speed 0 (khz) selects RTCK method.
 @xref{FAQ RTCK}.
@@ -1799,6 +1812,7 @@
 @end deffn
 
 @defun jtag_rclk fallback_speed_kHz
+@cindex adaptive clocking
 @cindex RTCK
 This Tcl proc (defined in @file{startup.tcl}) attempts to enable RTCK/RCLK.
 If that fails (maybe the interface, board, or target doesn't
@@ -4321,6 +4335,31 @@
 or 5 seconds if there is no parameter, for the target to halt
 (and enter debug mode).
 Using 0 as the @var{ms} parameter prevents OpenOCD from waiting.
+
+@quotation Warning
+On ARM cores, software using the @emph{wait for interrupt} operation
+often blocks the JTAG access needed by a @command{halt} command.
+This is because that operation also puts the core into a low
+power mode by gating the core clock;
+but the core clock is needed to detect JTAG clock transitions.
+
+One partial workaround uses adaptive clocking:  when the core is
+interrupted the operation completes, then JTAG clocks are accepted
+at least until the interrupt handler completes.
+However, this workaround is often unusable since the processor, board,
+and JTAG adapter must all support adaptive JTAG clocking.
+Also, it can't work until an interrupt is issued.
+
+A more complete workaround is to not use that operation while you
+work with a JTAG debugger.
+Tasking environments generaly have idle loops where the body is the
+@emph{wait for interrupt} operation.
+(On older cores, it is a coprocessor action;
+newer cores have a @option{wfi} instruction.)
+Such loops can just remove that operation, at the cost of higher
+power consumption (because the CPU is needlessly clocked).
+@end quotation
+
 @end deffn
 
 @deffn Command resume [address]
@@ -5984,9 +6023,10 @@
 
 In most simple terms: Often the JTAG clock must be 1/10 to 1/12 of
 the target clock speed. But what that ``magic division'' is varies
-depending on the chips on your board. @b{ARM rule of thumb} Most ARM
-based systems require an 8:1 division. @b{Xilinx rule of thumb} is
-1/12 the clock speed.
+depending on the chips on your board.
+@b{ARM rule of thumb} Most ARM based systems require an 6:1 division;
+ARM11 cores use an 8:1 division.
+@b{Xilinx rule of thumb} is 1/12 the clock speed.
 
 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
 
@@ -5999,11 +6039,18 @@
 sleep''. If you are careful - 98% of your problems can be debugged
 this way.
 
+Note that on ARM you may need to avoid using the @emph{wait for interrupt}
+operation in your idle loops even if you don't otherwise change the CPU
+clock rate.
+That operation gates the CPU clock, and thus the JTAG clock; which
+prevents JTAG access.  One consequence is not being able to @command{halt}
+cores which are executing that @emph{wait for interrupt} operation.
+
 To set the JTAG frequency use the command:
 
 @example
-        # Example: 1.234MHz
-        jtag_khz 1234
+# Example: 1.234MHz
+jtag_khz 1234
 @end example
 
 

[Openocd-svn] r2717 - trunk/src/target

[<ml...@ma...>]

Author: mlu
Date: 2009-09-16 20:18:38 +0200 (Wed, 16 Sep 2009)
New Revision: 2717

Modified:
   trunk/src/target/cortex_a8.h
Log:
Remove unused varables (moved to armv7a)

Modified: trunk/src/target/cortex_a8.h
===================================================================
--- trunk/src/target/cortex_a8.h	2009-09-16 18:17:26 UTC (rev 2716)
+++ trunk/src/target/cortex_a8.h	2009-09-16 18:18:38 UTC (rev 2717)
@@ -103,11 +103,6 @@
 	int common_magic;
 	arm_jtag_t jtag_info;
 
-	/* Core Debug Unit */
-	uint32_t debug_base;
-	uint8_t debug_ap;
-	uint8_t memory_ap;
-
 	/* Context information */
 	uint32_t cpudbg_dscr;
 	uint32_t nvic_dfsr;  /* Debug Fault Status Register - shows reason for debug halt */

[Openocd-svn] r2716 - trunk/src/target

[<ml...@ma...>]

Author: mlu
Date: 2009-09-16 20:17:26 +0200 (Wed, 16 Sep 2009)
New Revision: 2716

Modified:
   trunk/src/target/cortex_a8.c
Log:
Use a variable armv7a->debug_base instead of hardedcoded  OMAP3530_DEBUG_BASE

Modified: trunk/src/target/cortex_a8.c
===================================================================
--- trunk/src/target/cortex_a8.c	2009-09-16 12:38:26 UTC (rev 2715)
+++ trunk/src/target/cortex_a8.c	2009-09-16 18:17:26 UTC (rev 2716)
@@ -163,21 +163,21 @@
 	do
 	{
 		retval = mem_ap_read_atomic_u32(swjdp,
-				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+				armv7a->debug_base + CPUDBG_DSCR, &dscr);
 		if (retval != ERROR_OK)
 			return retval;
-	}
+		}
 	while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
-	mem_ap_write_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_ITR, opcode);
+	mem_ap_write_u32(swjdp, armv7a->debug_base + CPUDBG_ITR, opcode);
 
 	do
 	{
 		retval = mem_ap_read_atomic_u32(swjdp,
-				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+				armv7a->debug_base + CPUDBG_DSCR, &dscr);
 		if (retval != ERROR_OK)
 			return retval;
-	}
+		}
 	while ((dscr & (1 << DSCR_INSTR_COMP)) == 0); /* Wait for InstrCompl bit to be set */
 
 	return retval;
@@ -221,7 +221,7 @@
 
 	/* Read DCCTX */
 	retval = mem_ap_read_atomic_u32(swjdp,
-			OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
+			armv7a->debug_base + CPUDBG_DTRTX, value);
 
 	return retval;
 }
@@ -236,7 +236,7 @@
 	swjdp_common_t *swjdp = &armv7a->swjdp_info;
 
 	retval = mem_ap_write_u32(swjdp,
-			OMAP3530_DEBUG_BASE + CPUDBG_DTRRX, value);
+			armv7a->debug_base + CPUDBG_DTRRX, value);
 	/* Move DTRRX to r0 */
 	cortex_a8_exec_opcode(target, ARMV4_5_MRC(14, 0, 0, 0, 5, 0));
 
@@ -291,12 +291,12 @@
 	do
 	{
 		retval = mem_ap_read_atomic_u32(swjdp,
-				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+				armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	}
 	while ((dscr & (1 << DSCR_DTR_TX_FULL)) == 0); /* Wait for DTRRXfull */
 
 	retval = mem_ap_read_atomic_u32(swjdp,
-			OMAP3530_DEBUG_BASE + CPUDBG_DTRTX, value);
+			armv7a->debug_base + CPUDBG_DTRTX, value);
 
 	return retval;
 }
@@ -316,7 +316,7 @@
 
 	/* Write to DCCRX */
 	retval = mem_ap_write_u32(swjdp,
-			OMAP3530_DEBUG_BASE + CPUDBG_DTRRX, value);
+			armv7a->debug_base + CPUDBG_DTRRX, value);
 
 	if (Rd < 15)
 	{
@@ -359,7 +359,7 @@
 	uint8_t saved_apsel = dap_ap_get_select(swjdp);
 	dap_ap_select(swjdp, swjdp_debugap);
 	retval = mem_ap_read_atomic_u32(swjdp,
-			OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+			armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	if (retval != ERROR_OK)
 	{
 		dap_ap_select(swjdp, saved_apsel);
@@ -430,21 +430,21 @@
 	 * and then wait for the core to be halted.
 	 */
 	retval = mem_ap_write_atomic_u32(swjdp,
-			OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x1);
+			armv7a->debug_base + CPUDBG_DRCR, 0x1);
 
 	/*
 	 * enter halting debug mode
 	 */
-	mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+	mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	retval = mem_ap_write_atomic_u32(swjdp,
-		OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
+		armv7a->debug_base + CPUDBG_DSCR, dscr | (1 << DSCR_HALT_DBG_MODE));
 
 	if (retval != ERROR_OK)
 		goto out;
 
 	do {
 		mem_ap_read_atomic_u32(swjdp,
-			OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+			armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	} while ((dscr & (1 << DSCR_CORE_HALTED)) == 0);
 
 	target->debug_reason = DBG_REASON_DBGRQ;
@@ -545,11 +545,11 @@
 
 #endif
 	/* Restart core and wait for it to be started */
-	mem_ap_write_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_DRCR, 0x2);
+	mem_ap_write_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_DRCR, 0x2);
 
 	do {
 		mem_ap_read_atomic_u32(swjdp,
-			OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+			armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	} while ((dscr & (1 << DSCR_CORE_RESTARTED)) == 0);
 
 	target->debug_reason = DBG_REASON_NOTHALTED;
@@ -596,10 +596,10 @@
 
 	/* Enable the ITR execution once we are in debug mode */
 	mem_ap_read_atomic_u32(swjdp,
-				OMAP3530_DEBUG_BASE + CPUDBG_DSCR, &dscr);
+				armv7a->debug_base + CPUDBG_DSCR, &dscr);
 	dscr |= (1 << DSCR_EXT_INT_EN);
 	retval = mem_ap_write_atomic_u32(swjdp,
-			OMAP3530_DEBUG_BASE + CPUDBG_DSCR, dscr);
+			armv7a->debug_base + CPUDBG_DSCR, dscr);
 
 	/* Examine debug reason */
 	switch ((cortex_a8->cpudbg_dscr >> 2)&0xF)
@@ -1029,10 +1029,10 @@
 		brp_list[brp_i].used = 1;
 		brp_list[brp_i].value = (breakpoint->address & 0xFFFFFFFC);
 		brp_list[brp_i].control = control;
-		target_write_u32(target, OMAP3530_DEBUG_BASE
+		target_write_u32(target, armv7a->debug_base
 				+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
 				brp_list[brp_i].value);
-		target_write_u32(target, OMAP3530_DEBUG_BASE
+		target_write_u32(target, armv7a->debug_base
 				+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
 				brp_list[brp_i].control);
 		LOG_DEBUG("brp %i control 0x%0" PRIx32 " value 0x%0" PRIx32, brp_i,
@@ -1095,10 +1095,10 @@
 		brp_list[brp_i].used = 0;
 		brp_list[brp_i].value = 0;
 		brp_list[brp_i].control = 0;
-		target_write_u32(target, OMAP3530_DEBUG_BASE
+		target_write_u32(target, armv7a->debug_base
 				+ CPUDBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
 				brp_list[brp_i].control);
-		target_write_u32(target, OMAP3530_DEBUG_BASE
+		target_write_u32(target, armv7a->debug_base
 				+ CPUDBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
 				brp_list[brp_i].value);
 	}
@@ -1366,35 +1366,38 @@
 	uint32_t didr, ctypr, ttypr, cpuid;
 
 	LOG_DEBUG("TODO");
+	
+	/* Here we shall insert a proper ROM Table scan */
+	armv7a->debug_base = OMAP3530_DEBUG_BASE;
 
 	/* We do one extra read to ensure DAP is configured,
 	 * we call ahbap_debugport_init(swjdp) instead
 	 */
 	ahbap_debugport_init(swjdp);
-	mem_ap_read_atomic_u32(swjdp, OMAP3530_DEBUG_BASE + CPUDBG_CPUID, &cpuid);
+	mem_ap_read_atomic_u32(swjdp, armv7a->debug_base + CPUDBG_CPUID, &cpuid);
 	if ((retval = mem_ap_read_atomic_u32(swjdp,
-			OMAP3530_DEBUG_BASE + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
+			armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
 	{
 		LOG_DEBUG("Examine failed");
 		return retval;
 	}
 
 	if ((retval = mem_ap_read_atomic_u32(swjdp,
-			OMAP3530_DEBUG_BASE + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
+			armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
 	{
 		LOG_DEBUG("Examine failed");
 		return retval;
 	}
 
 	if ((retval = mem_ap_read_atomic_u32(swjdp,
-			OMAP3530_DEBUG_BASE + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
+			armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
 	{
 		LOG_DEBUG("Examine failed");
 		return retval;
 	}
 
 	if ((retval = mem_ap_read_atomic_u32(swjdp,
-			OMAP3530_DEBUG_BASE + CPUDBG_DIDR, &didr)) != ERROR_OK)
+			armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK)
 	{
 		LOG_DEBUG("Examine failed");
 		return retval;

[Openocd-svn] r2715 - in trunk: doc src/flash tcl/board tcl/target

[oharboe at B. <oh...@ma...>]

Author: oharboe
Date: 2009-09-16 14:38:26 +0200 (Wed, 16 Sep 2009)
New Revision: 2715

Added:
   trunk/src/flash/lpc2900.c
   trunk/src/flash/lpc2900.h
   trunk/tcl/board/hitex_lpc2929.cfg
   trunk/tcl/target/lpc2900.cfg
Modified:
   trunk/doc/openocd.texi
   trunk/src/flash/Makefile.am
   trunk/src/flash/flash.c
Log:
Rolf Meeser <rol...@ya...> adds flash support for NXP's LPC2900 family (ARM968E).

Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi	2009-09-15 16:20:39 UTC (rev 2714)
+++ trunk/doc/openocd.texi	2009-09-16 12:38:26 UTC (rev 2715)
@@ -3309,7 +3309,15 @@
 
 @deffn {Flash Driver} lpc2000
 Most members of the LPC1700 and LPC2000 microcontroller families from NXP
-include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000)  cores.
+include internal flash and use Cortex-M3 (LPC1700) or ARM7TDMI (LPC2000) cores.
+
+@quotation Note
+There are LPC2000 devices which are not supported by the @var{lpc2000}
+driver:
+The LPC2888 is supported by the @var{lpc288x} driver.
+The LPC29xx family is supported by the @var{lpc2900} driver.
+@end quotation
+
 The @var{lpc2000} driver defines two mandatory and one optional parameters,
 which must appear in the following order:
 
@@ -3349,6 +3357,129 @@
 @end example
 @end deffn
 
+@deffn {Flash Driver} lpc2900
+This driver supports the LPC29xx ARM968E based microcontroller family
+from NXP.
+
+The predefined parameters @var{base}, @var{size}, @var{chip_width} and
+@var{bus_width} of the @code{flash bank} command are ignored. Flash size and
+sector layout are auto-configured by the driver.
+The driver has one additional mandatory parameter: The CPU clock rate
+(in kHz) at the time the flash operations will take place. Most of the time this
+will not be the crystal frequency, but a higher PLL frequency. The
+@code{reset-init} event handler in the board script is usually the place where
+you start the PLL.
+
+The driver rejects flashless devices (currently the LPC2930).
+
+The EEPROM in LPC2900 devices is not mapped directly into the address space.
+It must be handled much more like NAND flash memory, and will therefore be
+handled by a separate @code{lpc2900_eeprom} driver (not yet available).
+
+Sector protection in terms of the LPC2900 is handled transparently. Every time a
+sector needs to be erased or programmed, it is automatically unprotected.
+What is shown as protection status in the @code{flash info} command, is
+actually the LPC2900 @emph{sector security}. This is a mechanism to prevent a
+sector from ever being erased or programmed again. As this is an irreversible
+mechanism, it is handled by a special command (@code{lpc2900 secure_sector}),
+and not by the standard @code{flash protect} command.
+
+Example for a 125 MHz clock frequency:
+@example
+flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
+@end example
+
+Some @code{lpc2900}-specific commands are defined. In the following command list,
+the @var{bank} parameter is the bank number as obtained by the
+@code{flash banks} command.
+
+@deffn Command {lpc2900 signature} bank
+Calculates a 128-bit hash value, the @emph{signature}, from the whole flash
+content. This is a hardware feature of the flash block, hence the calculation is
+very fast. You may use this to verify the content of a programmed device against
+a known signature.
+Example:
+@example
+lpc2900 signature 0
+  signature: 0x5f40cdc8:0xc64e592e:0x10490f89:0x32a0f317
+@end example
+@end deffn
+
+@deffn Command {lpc2900 read_custom} bank filename
+Reads the 912 bytes of customer information from the flash index sector, and
+saves it to a file in binary format.
+Example:
+@example
+lpc2900 read_custom 0 /path_to/customer_info.bin
+@end example
+@end deffn
+
+The index sector of the flash is a @emph{write-only} sector. It cannot be
+erased! In order to guard against unintentional write access, all following
+commands need to be preceeded by a successful call to the @code{password}
+command:
+
+@deffn Command {lpc2900 password} bank password
+You need to use this command right before each of the following commands:
+@code{lpc2900 write_custom}, @code{lpc2900 secure_sector},
+@code{lpc2900 secure_jtag}.
+
+The password string is fixed to "I_know_what_I_am_doing".
+Example:
+@example
+lpc2900 password 0 I_know_what_I_am_doing
+  Potentially dangerous operation allowed in next command!
+@end example
+@end deffn
+
+@deffn Command {lpc2900 write_custom} bank filename type
+Writes the content of the file into the customer info space of the flash index
+sector. The filetype can be specified with the @var{type} field. Possible values
+for @var{type} are: @var{bin} (binary), @var{ihex} (Intel hex format),
+@var{elf} (ELF binary) or @var{s19} (Motorola S-records). The file must
+contain a single section, and the contained data length must be exactly
+912 bytes.
+@quotation Attention
+This cannot be reverted! Be careful!
+@end quotation
+Example:
+@example
+lpc2900 write_custom 0 /path_to/customer_info.bin bin
+@end example
+@end deffn
+
+@deffn Command {lpc2900 secure_sector} bank first last
+Secures the sector range from @var{first} to @var{last} (including) against
+further program and erase operations. The sector security will be effective
+after the next power cycle.
+@quotation Attention
+This cannot be reverted! Be careful!
+@end quotation
+Secured sectors appear as @emph{protected} in the @code{flash info} command.
+Example:
+@example
+lpc2900 secure_sector 0 1 1
+flash info 0
+  #0 : lpc2900 at 0x20000000, size 0x000c0000, (...)
+          #  0: 0x00000000 (0x2000 8kB) not protected
+          #  1: 0x00002000 (0x2000 8kB) protected
+          #  2: 0x00004000 (0x2000 8kB) not protected
+@end example
+@end deffn
+
+@deffn Command {lpc2900 secure_jtag} bank
+Irreversibly disable the JTAG port. The new JTAG security setting will be
+effective after the next power cycle.
+@quotation Attention
+This cannot be reverted! Be careful!
+@end quotation
+Examples:
+@example
+lpc2900 secure_jtag 0
+@end example
+@end deffn
+@end deffn
+
 @deffn {Flash Driver} ocl
 @emph{No idea what this is, other than using some arm7/arm9 core.}
 

Modified: trunk/src/flash/Makefile.am
===================================================================
--- trunk/src/flash/Makefile.am	2009-09-15 16:20:39 UTC (rev 2714)
+++ trunk/src/flash/Makefile.am	2009-09-16 12:38:26 UTC (rev 2715)
@@ -9,6 +9,8 @@
 	arm_nandio.c \
 	flash.c \
 	lpc2000.c \
+	lpc288x.c \
+	lpc2900.c \
 	cfi.c \
 	non_cfi.c \
 	at91sam7.c \
@@ -32,7 +34,6 @@
 	s3c2412_nand.c \
 	s3c2440_nand.c \
 	s3c2443_nand.c \
-	lpc288x.c \
 	ocl.c \
 	mflash.c \
 	pic32mx.c \
@@ -43,6 +44,8 @@
 	arm_nandio.h \
 	flash.h \
 	lpc2000.h \
+	lpc288x.h \
+	lpc2900.h \
 	cfi.h \
 	non_cfi.h \
 	at91sam7.h \
@@ -57,7 +60,6 @@
 	tms470.h \
 	s3c24xx_nand.h \
 	s3c24xx_regs_nand.h \
-	lpc288x.h \
 	mflash.h \
 	ocl.h \
 	pic32mx.h \

Modified: trunk/src/flash/flash.c
===================================================================
--- trunk/src/flash/flash.c	2009-09-15 16:20:39 UTC (rev 2714)
+++ trunk/src/flash/flash.c	2009-09-16 12:38:26 UTC (rev 2715)
@@ -47,6 +47,8 @@
 /* flash drivers
  */
 extern flash_driver_t lpc2000_flash;
+extern flash_driver_t lpc288x_flash;
+extern flash_driver_t lpc2900_flash;
 extern flash_driver_t cfi_flash;
 extern flash_driver_t at91sam3_flash;
 extern flash_driver_t at91sam7_flash;
@@ -58,13 +60,14 @@
 extern flash_driver_t stm32x_flash;
 extern flash_driver_t tms470_flash;
 extern flash_driver_t ecosflash_flash;
-extern flash_driver_t lpc288x_flash;
 extern flash_driver_t ocl_flash;
 extern flash_driver_t pic32mx_flash;
 extern flash_driver_t avr_flash;
 
 flash_driver_t *flash_drivers[] = {
 	&lpc2000_flash,
+	&lpc288x_flash,
+	&lpc2900_flash,
 	&cfi_flash,
 	&at91sam7_flash,
 	&at91sam3_flash,
@@ -76,7 +79,6 @@
 	&stm32x_flash,
 	&tms470_flash,
 	&ecosflash_flash,
-	&lpc288x_flash,
 	&ocl_flash,
 	&pic32mx_flash,
 	&avr_flash,

Added: trunk/src/flash/lpc2900.c
===================================================================
--- trunk/src/flash/lpc2900.c	2009-09-15 16:20:39 UTC (rev 2714)
+++ trunk/src/flash/lpc2900.c	2009-09-16 12:38:26 UTC (rev 2715)
@@ -0,0 +1,1926 @@
+/***************************************************************************
+ *   Copyright (C) 2009 by                                                 *
+ *   Rolf Meeser <rol...@ya...>                                      *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+
+#include "image.h"
+
+#include "lpc2900.h"
+#include "binarybuffer.h"
+#include "armv4_5.h"
+
+
+/* 1024 bytes */
+#define KiB                 1024
+
+/* Some flash constants */
+#define FLASH_PAGE_SIZE     512     /* bytes */
+#define FLASH_ERASE_TIME    100000  /* microseconds */
+#define FLASH_PROGRAM_TIME  1000    /* microseconds */
+
+/* Chip ID / Feature Registers */
+#define CHIPID          0xE0000000  /* Chip ID */
+#define FEAT0           0xE0000100  /* Chip feature 0 */
+#define FEAT1           0xE0000104  /* Chip feature 1 */
+#define FEAT2           0xE0000108  /* Chip feature 2 (contains flash size indicator) */
+#define FEAT3           0xE000010C  /* Chip feature 3 */
+
+#define EXPECTED_CHIPID 0x209CE02B  /* Chip ID of all LPC2900 devices */
+
+/* Flash/EEPROM Control Registers */
+#define FCTR            0x20200000  /* Flash control */
+#define FPTR            0x20200008  /* Flash program-time */
+#define FTCTR           0x2020000C  /* Flash test control */
+#define FBWST           0x20200010  /* Flash bridge wait-state */
+#define FCRA            0x2020001C  /* Flash clock divider */
+#define FMSSTART        0x20200020  /* Flash Built-In Selft Test start address */
+#define FMSSTOP         0x20200024  /* Flash Built-In Selft Test stop address */
+#define FMS16           0x20200028  /* Flash 16-bit signature */
+#define FMSW0           0x2020002C  /* Flash 128-bit signature Word 0 */
+#define FMSW1           0x20200030  /* Flash 128-bit signature Word 1 */
+#define FMSW2           0x20200034  /* Flash 128-bit signature Word 2 */
+#define FMSW3           0x20200038  /* Flash 128-bit signature Word 3 */
+
+#define EECMD           0x20200080  /* EEPROM command */
+#define EEADDR          0x20200084  /* EEPROM address */
+#define EEWDATA         0x20200088  /* EEPROM write data */
+#define EERDATA         0x2020008C  /* EEPROM read data */
+#define EEWSTATE        0x20200090  /* EEPROM wait state */
+#define EECLKDIV        0x20200094  /* EEPROM clock divider */
+#define EEPWRDWN        0x20200098  /* EEPROM power-down/start */
+#define EEMSSTART       0x2020009C  /* EEPROM BIST start address */
+#define EEMSSTOP        0x202000A0  /* EEPROM BIST stop address */
+#define EEMSSIG         0x202000A4  /* EEPROM 24-bit BIST signature */
+
+#define INT_CLR_ENABLE  0x20200FD8  /* Flash/EEPROM interrupt clear enable */
+#define INT_SET_ENABLE  0x20200FDC  /* Flash/EEPROM interrupt set enable */
+#define INT_STATUS      0x20200FE0  /* Flash/EEPROM interrupt status */
+#define INT_ENABLE      0x20200FE4  /* Flash/EEPROM interrupt enable */
+#define INT_CLR_STATUS  0x20200FE8  /* Flash/EEPROM interrupt clear status */
+#define INT_SET_STATUS  0x20200FEC  /* Flash/EEPROM interrupt set status */
+
+/* Interrupt sources */
+#define INTSRC_END_OF_PROG    (1 << 28)
+#define INTSRC_END_OF_BIST    (1 << 27)
+#define INTSRC_END_OF_RDWR    (1 << 26)
+#define INTSRC_END_OF_MISR    (1 << 2)
+#define INTSRC_END_OF_BURN    (1 << 1)
+#define INTSRC_END_OF_ERASE   (1 << 0)
+
+
+/* FCTR bits */
+#define FCTR_FS_LOADREQ       (1 << 15)
+#define FCTR_FS_CACHECLR      (1 << 14)
+#define FCTR_FS_CACHEBYP      (1 << 13)
+#define FCTR_FS_PROGREQ       (1 << 12)
+#define FCTR_FS_RLS           (1 << 11)
+#define FCTR_FS_PDL           (1 << 10)
+#define FCTR_FS_PD            (1 << 9)
+#define FCTR_FS_WPB           (1 << 7)
+#define FCTR_FS_ISS           (1 << 6)
+#define FCTR_FS_RLD           (1 << 5)
+#define FCTR_FS_DCR           (1 << 4)
+#define FCTR_FS_WEB           (1 << 2)
+#define FCTR_FS_WRE           (1 << 1)
+#define FCTR_FS_CS            (1 << 0)
+/* FPTR bits */
+#define FPTR_EN_T             (1 << 15)
+/* FTCTR bits */
+#define FTCTR_FS_BYPASS_R     (1 << 29)
+#define FTCTR_FS_BYPASS_W     (1 << 28)
+/* FMSSTOP bits */
+#define FMSSTOP_MISR_START    (1 << 17)
+/* EEMSSTOP bits */
+#define EEMSSTOP_STRTBIST     (1 << 31)
+
+/* Index sector */
+#define ISS_CUSTOMER_START1   (0x830)
+#define ISS_CUSTOMER_END1     (0xA00)
+#define ISS_CUSTOMER_SIZE1    (ISS_CUSTOMER_END1 - ISS_CUSTOMER_START1)
+#define ISS_CUSTOMER_NWORDS1  (ISS_CUSTOMER_SIZE1 / 4)
+#define ISS_CUSTOMER_START2   (0xA40)
+#define ISS_CUSTOMER_END2     (0xC00)
+#define ISS_CUSTOMER_SIZE2    (ISS_CUSTOMER_END2 - ISS_CUSTOMER_START2)
+#define ISS_CUSTOMER_NWORDS2  (ISS_CUSTOMER_SIZE2 / 4)
+#define ISS_CUSTOMER_SIZE     (ISS_CUSTOMER_SIZE1 + ISS_CUSTOMER_SIZE2)
+
+
+
+/**
+ * Private data for \c lpc2900 flash driver.
+ */
+typedef struct lpc2900_flash_bank_s
+{
+	/**
+	 * Holds the value read from CHIPID register.
+	 * The driver will not load if the chipid doesn't match the expected
+	 * value of 0x209CE02B of the LPC2900 family. A probe will only be done
+	 * if the chipid does not yet contain the expected value.
+	 */
+	uint32_t chipid;
+
+	/**
+	 * String holding device name.
+	 * This string is set by the probe function to the type number of the
+	 * device. It takes the form "LPC29xx".
+	 */
+	char * target_name;
+
+	/**
+	 * System clock frequency.
+	 * Holds the clock frequency in Hz, as passed by the configuration file
+	 * to the <tt>flash bank</tt> command.
+	 */
+	uint32_t clk_sys_fmc;
+
+	/**
+	 * Flag to indicate that dangerous operations are possible.
+	 * This flag can be set by passing the correct password to the
+	 * <tt>lpc2900 password</tt> command. If set, other dangerous commands,
+	 * which operate on the index sector, can be executed.
+	 */
+	uint32_t risky;
+
+	/**
+	 * Maximum contiguous block of internal SRAM (bytes).
+	 * Autodetected by the driver. Not the total amount of SRAM, only the
+	 * the largest \em contiguous block!
+	 */
+	uint32_t max_ram_block;
+
+} lpc2900_flash_bank_t;
+
+
+
+
+static int lpc2900_register_commands(struct command_context_s *cmd_ctx);
+static int lpc2900_flash_bank_command(struct command_context_s *cmd_ctx,
+                                      char *cmd, char **args, int argc,
+                                      struct flash_bank_s *bank);
+static int lpc2900_erase(struct flash_bank_s *bank, int first, int last);
+static int lpc2900_protect(struct flash_bank_s *bank, int set, int first, int last);
+static int lpc2900_write(struct flash_bank_s *bank,
+                         uint8_t *buffer, uint32_t offset, uint32_t count);
+static int lpc2900_probe(struct flash_bank_s *bank);
+static int lpc2900_erase_check(struct flash_bank_s *bank);
+static int lpc2900_protect_check(struct flash_bank_s *bank);
+static int lpc2900_info(struct flash_bank_s *bank, char *buf, int buf_size);
+
+static uint32_t lpc2900_wait_status(flash_bank_t *bank, uint32_t mask, int timeout);
+static void lpc2900_setup(struct flash_bank_s *bank);
+static uint32_t lpc2900_is_ready(struct flash_bank_s *bank);
+static uint32_t lpc2900_read_security_status(struct flash_bank_s *bank);
+static uint32_t lpc2900_run_bist128(struct flash_bank_s *bank,
+                                    uint32_t addr_from, uint32_t addr_to,
+                                    uint32_t (*signature)[4] );
+static uint32_t lpc2900_address2sector(struct flash_bank_s *bank, uint32_t offset);
+static uint32_t lpc2900_calc_tr( uint32_t clock, uint32_t time );
+
+
+/***********************  Helper functions  **************************/
+
+
+/**
+ * Wait for an event in mask to occur in INT_STATUS.
+ *
+ * Return when an event occurs, or after a timeout.
+ *
+ * @param[in] bank Pointer to the flash bank descriptor
+ * @param[in] mask Mask to be used for INT_STATUS
+ * @param[in] timeout Timeout in ms
+ */
+static uint32_t lpc2900_wait_status( flash_bank_t *bank,
+                                     uint32_t mask,
+                                     int timeout )
+{
+	uint32_t int_status;
+	target_t *target = bank->target;
+
+
+	do
+	{
+		alive_sleep(1);
+		timeout--;
+		target_read_u32(target, INT_STATUS, &int_status);
+	}
+	while( ((int_status & mask) == 0) && (timeout != 0) );
+
+	if (timeout == 0)
+	{
+		LOG_DEBUG("Timeout!");
+		return ERROR_FLASH_OPERATION_FAILED;
+	}
+
+	return ERROR_OK;
+}
+
+
+
+/**
+ * Set up the flash for erase/program operations.
+ *
+ * Enable the flash, and set the correct CRA clock of 66 kHz.
+ *
+ * @param bank Pointer to the flash bank descriptor
+ */
+static void lpc2900_setup( struct flash_bank_s *bank )
+{
+	uint32_t fcra;
+	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
+
+
+	/* Power up the flash block */
+	target_write_u32( bank->target, FCTR, FCTR_FS_WEB | FCTR_FS_CS );
+
+
+	fcra = (lpc2900_info->clk_sys_fmc / (3 * 66000)) - 1;
+	target_write_u32( bank->target, FCRA, fcra );
+}
+
+
+
+/**
+ * Check if device is ready.
+ *
+ * Check if device is ready for flash operation:
+ * Must have been successfully probed.
+ * Must be halted.
+ */
+static uint32_t lpc2900_is_ready( struct flash_bank_s *bank )
+{
+	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
+
+	if( lpc2900_info->chipid != EXPECTED_CHIPID )
+	{
+		return ERROR_FLASH_BANK_NOT_PROBED;
+	}
+
+	if( bank->target->state != TARGET_HALTED )
+	{
+		LOG_ERROR( "Target not halted" );
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	return ERROR_OK;
+}
+
+
+/**
+ * Read the status of sector security from the index sector.
+ *
+ * @param bank Pointer to the flash bank descriptor
+ */
+static uint32_t lpc2900_read_security_status( struct flash_bank_s *bank )
+{
+	uint32_t status;
+	if( (status = lpc2900_is_ready( bank )) != ERROR_OK )
+	{
+		return status;
+	}
+
+	target_t *target = bank->target;
+
+	/* Enable ISS access */
+	target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB | FCTR_FS_ISS);
+
+	/* Read the relevant block of memory from the ISS sector */
+	uint32_t iss_secured_field[ 0x230/16 ][ 4 ];
+	target_read_memory(target, bank->base + 0xC00, 4, 0x230/4,
+	                           (uint8_t *)iss_secured_field);
+
+	/* Disable ISS access */
+	target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
+
+	/* Check status of each sector. Note that the sector numbering in the LPC2900
+	 * is different from the logical sector numbers used in OpenOCD!
+	 * Refer to the user manual for details.
+	 *
+	 * All zeros (16x 0x00) are treated as a secured sector (is_protected = 1)
+	 * All ones (16x 0xFF) are treated as a non-secured sector (is_protected = 0)
+	 * Anything else is undefined (is_protected = -1). This is treated as
+	 * a protected sector!
+	 */
+	int sector;
+	int index;
+	for( sector = 0; sector < bank->num_sectors; sector++ )
+	{
+		/* Convert logical sector number to physical sector number */
+		if( sector <= 4 )
+		{
+			index = sector + 11;
+		}
+		else if( sector <= 7 )
+		{
+			index = sector + 27;
+		}
+		else
+		{
+			index = sector - 8;
+		}
+
+		bank->sectors[sector].is_protected = -1;
+
+		if (
+		    (iss_secured_field[index][0] == 0x00000000) &&
+		    (iss_secured_field[index][1] == 0x00000000) &&
+		    (iss_secured_field[index][2] == 0x00000000) &&
+		    (iss_secured_field[index][3] == 0x00000000) )
+		{
+			bank->sectors[sector].is_protected = 1;
+		}
+
+		if (
+		    (iss_secured_field[index][0] == 0xFFFFFFFF) &&
+		    (iss_secured_field[index][1] == 0xFFFFFFFF) &&
+		    (iss_secured_field[index][2] == 0xFFFFFFFF) &&
+		    (iss_secured_field[index][3] == 0xFFFFFFFF) )
+		{
+			bank->sectors[sector].is_protected = 0;
+		}
+	}
+
+	return ERROR_OK;
+}
+
+
+/**
+ * Use BIST to calculate a 128-bit hash value over a range of flash.
+ *
+ * @param bank Pointer to the flash bank descriptor
+ * @param addr_from
+ * @param addr_to
+ * @param signature
+ */
+static uint32_t lpc2900_run_bist128(struct flash_bank_s *bank,
+                                    uint32_t addr_from,
+                                    uint32_t addr_to,
+                                    uint32_t (*signature)[4] )
+{
+	target_t *target = bank->target;
+
+	/* Clear END_OF_MISR interrupt status */
+	target_write_u32( target, INT_CLR_STATUS, INTSRC_END_OF_MISR );
+
+	/* Start address */
+	target_write_u32( target, FMSSTART, addr_from >> 4);
+	/* End address, and issue start command */
+	target_write_u32( target, FMSSTOP, (addr_to >> 4) | FMSSTOP_MISR_START );
+
+	/* Poll for end of operation. Calculate a reasonable timeout. */
+	if( lpc2900_wait_status( bank, INTSRC_END_OF_MISR, 1000 ) != ERROR_OK )
+	{
+		return ERROR_FLASH_OPERATION_FAILED;
+	}
+
+	/* Return the signature */
+	target_read_memory( target, FMSW0, 4, 4, (uint8_t *)signature );
+
+	return ERROR_OK;
+}
+
+
+/**
+ * Return sector number for given address.
+ *
+ * Return the (logical) sector number for a given relative address.
+ * No sanity check is done. It assumed that the address is valid.
+ *
+ * @param bank Pointer to the flash bank descriptor
+ * @param offset Offset address relative to bank start
+ */
+static uint32_t lpc2900_address2sector( struct flash_bank_s *bank,
+                                        uint32_t offset )
+{
+	uint32_t address = bank->base + offset;
+
+
+	/* Run through all sectors of this bank */
+	int sector;
+	for( sector = 0; sector < bank->num_sectors; sector++ )
+	{
+		/* Return immediately if address is within the current sector */
+		if( address < (bank->sectors[sector].offset + bank->sectors[sector].size) )
+		{
+			return sector;
+		}
+	}
+
+	/* We should never come here. If we do, return an arbitrary sector number. */
+	return 0;
+}
+
+
+
+
+/**
+ * Write one page to the index sector.
+ *
+ * @param bank Pointer to the flash bank descriptor
+ * @param pagenum Page number (0...7)
+ * @param page Page array (FLASH_PAGE_SIZE bytes)
+ */
+static int lpc2900_write_index_page( struct flash_bank_s *bank,
+                                     int pagenum,
+                                     uint8_t (*page)[FLASH_PAGE_SIZE] )
+{
+	/* Only pages 4...7 are user writable */
+	if( (pagenum < 4) || (pagenum > 7) )
+	{
+		LOG_ERROR( "Refuse to burn index sector page %" PRIu32, pagenum );
+		return ERROR_COMMAND_ARGUMENT_INVALID;
+	}
+
+	/* Get target, and check if it's halted */
+	target_t *target = bank->target;
+	if( target->state != TARGET_HALTED )
+	{
+		LOG_ERROR( "Target not halted" );
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	/* Private info */
+	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
+
+	/* Enable flash block and set the correct CRA clock of 66 kHz */
+	lpc2900_setup( bank );
+
+	/* Un-protect the index sector */
+	target_write_u32( target, bank->base, 0 );
+	target_write_u32( target, FCTR,
+	                  FCTR_FS_LOADREQ | FCTR_FS_WPB | FCTR_FS_ISS |
+	                  FCTR_FS_WEB | FCTR_FS_WRE | FCTR_FS_CS );
+
+	/* Set latch load mode */
+	target_write_u32( target, FCTR,
+	                  FCTR_FS_ISS | FCTR_FS_WEB | FCTR_FS_WRE | FCTR_FS_CS );
+
+	/* Write whole page to flash data latches */
+	if( target_write_memory( target,
+	                         bank->base + pagenum * FLASH_PAGE_SIZE,
+	                         4, FLASH_PAGE_SIZE / 4, (uint8_t *)page) != ERROR_OK )
+	{
+		LOG_ERROR( "Index sector write failed @ page %" PRIu32, pagenum );
+		target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB );
+
+		return ERROR_FLASH_OPERATION_FAILED;
+	}
+
+	/* Clear END_OF_BURN interrupt status */
+	target_write_u32( target, INT_CLR_STATUS, INTSRC_END_OF_BURN );
+
+	/* Set the program/erase time to FLASH_PROGRAM_TIME */
+	target_write_u32(target, FPTR,
+	                 FPTR_EN_T | lpc2900_calc_tr( lpc2900_info->clk_sys_fmc,
+	                                              FLASH_PROGRAM_TIME ));
+
+	/* Trigger flash write */
+	target_write_u32( target, FCTR,
+	                  FCTR_FS_PROGREQ | FCTR_FS_ISS |
+	                  FCTR_FS_WPB | FCTR_FS_WRE | FCTR_FS_CS );
+
+	/* Wait for the end of the write operation. If it's not over after one
+	 * second, something went dreadfully wrong... :-(
+	 */
+	if( lpc2900_wait_status( bank, INTSRC_END_OF_BURN, 1000 ) != ERROR_OK )
+	{
+		LOG_ERROR( "Index sector write failed @ page %" PRIu32, pagenum );
+		target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB );
+
+		return ERROR_FLASH_OPERATION_FAILED;
+	}
+
+	target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB );
+
+	return ERROR_OK;
+}
+
+
+
+/**
+ * Calculate FPTR.TR register value for desired program/erase time.
+ *
+ * @param clock System clock in Hz
+ * @param time Program/erase time in µs
+ */
+static uint32_t lpc2900_calc_tr( uint32_t clock, uint32_t time )
+{
+	/*           ((time[µs]/1e6) * f[Hz]) + 511
+	 * FPTR.TR = -------------------------------
+	 *                         512
+	 *
+	 * The result is the 
+	 */
+
+	uint32_t tr_val = (uint32_t)((((time / 1e6) * clock) + 511.0) / 512.0);
+
+	return tr_val;
+}
+
+
+/***********************  Private flash commands  **************************/
+
+
+/**
+ * Command to determine the signature of the whole flash.
+ *
+ * Uses the Built-In-Self-Test (BIST) to generate a 128-bit hash value
+ * of the flash content.
+ *
+ * @param cmd_ctx
+ * @param cmd
+ * @param args
+ * @param argc
+ */
+static int lpc2900_handle_signature_command( struct command_context_s *cmd_ctx,
+                                             char *cmd, char **args, int argc )
+{
+	flash_bank_t *bank;
+	uint32_t status;
+	uint32_t signature[4];
+
+
+	if( argc < 1 )
+	{
+		LOG_WARNING( "Too few arguments. Call: lpc2900 signature <bank#>" );
+		return ERROR_FLASH_BANK_INVALID;
+	}
+
+	/* Get the bank descriptor */
+	bank = get_flash_bank_by_num( strtoul(args[0], NULL, 0) );
+	if( !bank )
+	{
+		command_print( cmd_ctx, "flash bank '#%s' is out of bounds", args[0] );
+		return ERROR_OK;
+	}
+
+	if( bank->target->state != TARGET_HALTED )
+	{
+		LOG_ERROR( "Target not halted" );
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	/* Run BIST over whole flash range */
+	if( (status = lpc2900_run_bist128( bank,
+	                                   bank->base,
+	                                   bank->base + (bank->size - 1),
+	                                   &signature)
+	                                 ) != ERROR_OK )
+	{
+		return status;
+	}
+
+	command_print( cmd_ctx, "signature: 0x%8.8" PRIx32
+	                                  ":0x%8.8" PRIx32
+	                                  ":0x%8.8" PRIx32
+	                                  ":0x%8.8" PRIx32,
+	              signature[3], signature[2], signature[1], signature[0] );
+
+	return ERROR_OK;
+}
+
+
+
+/**
+ * Store customer info in file.
+ *
+ * Read customer info from index sector, and store that block of data into
+ * a disk file. The format is binary.
+ *
+ * @param cmd_ctx
+ * @param cmd
+ * @param args
+ * @param argc
+ */
+static int lpc2900_handle_read_custom_command( struct command_context_s *cmd_ctx,
+                                               char *cmd, char **args, int argc )
+{
+	flash_bank_t *bank;
+
+
+	if( argc < 2 )
+	{
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+
+	/* Get the bank descriptor */
+	bank = get_flash_bank_by_num( strtoul(args[0], NULL, 0) );
+	if( !bank )
+	{
+		command_print( cmd_ctx, "flash bank '#%s' is out of bounds", args[0] );
+		return ERROR_OK;
+	}
+	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
+	lpc2900_info->risky = 0;
+
+	/* Get target, and check if it's halted */
+	target_t *target = bank->target;
+	if( target->state != TARGET_HALTED )
+	{
+		LOG_ERROR( "Target not halted" );
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	/* Storage for customer info. Read in two parts */
+	uint32_t customer[ ISS_CUSTOMER_NWORDS1 + ISS_CUSTOMER_NWORDS2 ];
+
+	/* Enable access to index sector */
+	target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB | FCTR_FS_ISS );
+
+	/* Read two parts */
+	target_read_memory( target, bank->base+ISS_CUSTOMER_START1, 4,
+	                            ISS_CUSTOMER_NWORDS1,
+	                            (uint8_t *)&customer[0] );
+	target_read_memory( target, bank->base+ISS_CUSTOMER_START2, 4,
+	                            ISS_CUSTOMER_NWORDS2,
+	                            (uint8_t *)&customer[ISS_CUSTOMER_NWORDS1] );
+
+	/* Deactivate access to index sector */
+	target_write_u32( target, FCTR, FCTR_FS_CS | FCTR_FS_WEB );
+
+	/* Try and open the file */
+	fileio_t fileio;
+	char *filename = args[1];
+	int ret = fileio_open( &fileio, filename, FILEIO_WRITE, FILEIO_BINARY );
+	if( ret != ERROR_OK )
+	{
+		LOG_WARNING( "Could not open file %s", filename );
+		return ret;
+	}
+
+	uint32_t nwritten;
+	ret = fileio_write( &fileio, sizeof(customer),
+                        (const uint8_t *)customer, &nwritten );
+	if( ret != ERROR_OK )
+	{
+		LOG_ERROR( "Write operation to file %s failed", filename );
+		fileio_close( &fileio );
+		return ret;
+	}
+
+	fileio_close( &fileio );
+
+	return ERROR_OK;
+}
+
+
+
+
+/**
+ * Enter password to enable potentially dangerous options.
+ *
+ * @param cmd_ctx
+ * @param cmd
+ * @param args
+ * @param argc
+ */
+static int lpc2900_handle_password_command(struct command_context_s *cmd_ctx,
+                                           char *cmd, char **args, int argc)
+{
+	flash_bank_t *bank;
+
+
+	if (argc < 2)
+	{
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+
+	/* Get the bank descriptor */
+	bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
+	if (!bank)
+	{
+		command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
+		return ERROR_OK;
+	}
+	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
+
+#define ISS_PASSWORD "I_know_what_I_am_doing"
+
+	lpc2900_info->risky = !strcmp( args[1], ISS_PASSWORD );
+
+	if( !lpc2900_info->risky )
+	{
+		command_print(cmd_ctx, "Wrong password (use '%s')", ISS_PASSWORD);
+		return ERROR_COMMAND_ARGUMENT_INVALID;
+	}
+
+	command_print(cmd_ctx,
+                  "Potentially dangerous operation allowed in next command!");
+
+	return ERROR_OK;
+}
+
+
+
+/**
+ * Write customer info from file to the index sector.
+ *
+ * @param cmd_ctx
+ * @param cmd
+ * @param args
+ * @param argc
+ */
+static int lpc2900_handle_write_custom_command( struct command_context_s *cmd_ctx,
+                                                char *cmd, char **args, int argc )
+{
+	if (argc < 2)
+	{
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+
+	/* Get the bank descriptor */
+	flash_bank_t *bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
+	if (!bank)
+	{
+		command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
+		return ERROR_OK;
+	}
+	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
+
+	/* Check if command execution is allowed. */
+	if( !lpc2900_info->risky )
+	{
+		command_print( cmd_ctx, "Command execution not allowed!" );
+		return ERROR_COMMAND_ARGUMENT_INVALID;
+	}
+	lpc2900_info->risky = 0;
+
+	/* Get target, and check if it's halted */
+	target_t *target = bank->target;
+	if (target->state != TARGET_HALTED)
+	{
+		LOG_ERROR("Target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	/* The image will always start at offset 0 */
+	image_t image;
+	image.base_address_set = 1;
+	image.base_address = 0;
+	image.start_address_set = 0;
+
+	char *filename = args[1];
+	char *type = (argc >= 3) ? args[2] : NULL;
+	int retval = image_open(&image, filename, type);
+	if (retval != ERROR_OK)
+	{
+		return retval;
+	}
+
+	/* Do a sanity check: The image must be exactly the size of the customer
+	   programmable area. Any other size is rejected. */
+	if( image.num_sections != 1 )
+	{
+		LOG_ERROR("Only one section allowed in image file.");
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+	if( (image.sections[0].base_address != 0) ||
+        (image.sections[0].size != ISS_CUSTOMER_SIZE) )
+	{
+		LOG_ERROR("Incorrect image file size. Expected %" PRIu32 ", got %" PRIu32,
+                   ISS_CUSTOMER_SIZE, image.sections[0].size);
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+
+	/* Well boys, I reckon this is it... */
+
+	/* Customer info is split into two blocks in pages 4 and 5. */
+	uint8_t page[FLASH_PAGE_SIZE];
+
+	/* Page 4 */
+	uint32_t offset = ISS_CUSTOMER_START1 % FLASH_PAGE_SIZE;
+	memset( page, 0xff, FLASH_PAGE_SIZE );
+	uint32_t size_read;
+	retval = image_read_section( &image, 0, 0,
+	                             ISS_CUSTOMER_SIZE1, &page[offset], &size_read);
+	if( retval != ERROR_OK )
+	{
+		LOG_ERROR("couldn't read from file '%s'", filename);
+		image_close(&image);
+		return retval;
+	}
+	if( (retval = lpc2900_write_index_page( bank, 4, &page )) != ERROR_OK )
+	{
+		image_close(&image);
+		return retval;
+	}
+
+	/* Page 5 */
+	offset = ISS_CUSTOMER_START2 % FLASH_PAGE_SIZE;
+	memset( page, 0xff, FLASH_PAGE_SIZE );
+	retval = image_read_section( &image, 0, ISS_CUSTOMER_SIZE1,
+	                             ISS_CUSTOMER_SIZE2, &page[offset], &size_read);
+	if( retval != ERROR_OK )
+	{
+		LOG_ERROR("couldn't read from file '%s'", filename);
+		image_close(&image);
+		return retval;
+	}
+	if( (retval = lpc2900_write_index_page( bank, 5, &page )) != ERROR_OK )
+	{
+		image_close(&image);
+		return retval;
+	}
+
+	image_close(&image);
+
+	return ERROR_OK;
+}
+
+
+
+/**
+ * Activate 'sector security' for a range of sectors.
+ *
+ * @param cmd_ctx
+ * @param cmd
+ * @param args
+ * @param argc
+ */
+static int lpc2900_handle_secure_sector_command(struct command_context_s *cmd_ctx,
+                                                char *cmd, char **args, int argc)
+{
+	if (argc < 3)
+	{
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+
+	/* Get the bank descriptor */
+	flash_bank_t *bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
+	if (!bank)
+	{
+		command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
+		return ERROR_OK;
+	}
+	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
+
+	/* Check if command execution is allowed. */
+	if( !lpc2900_info->risky )
+	{
+		command_print( cmd_ctx, "Command execution not allowed! "
+		"(use 'password' command first)");
+		return ERROR_COMMAND_ARGUMENT_INVALID;
+	}
+	lpc2900_info->risky = 0;
+
+	/* Read sector range, and do a sanity check. */
+	int first = strtoul(args[1], NULL, 0);
+	int last = strtoul(args[2], NULL, 0);
+	if( (first >= bank->num_sectors) ||
+	    (last >= bank->num_sectors) ||
+	    (first > last) )
+	{
+		command_print( cmd_ctx, "Illegal sector range" );
+		return ERROR_COMMAND_ARGUMENT_INVALID;
+	}
+
+	uint8_t page[FLASH_PAGE_SIZE];
+	int sector;
+	int retval;
+
+	/* Sectors in page 6 */
+	if( (first <= 4) || (last >= 8) )
+	{
+		memset( &page, 0xff, FLASH_PAGE_SIZE );
+		for( sector = first; sector <= last; sector++ )
+		{
+			if( sector <= 4 )
+			{
+				memset( &page[0xB0 + 16*sector], 0, 16 );
+			}
+			else if( sector >= 8 )
+			{
+				memset( &page[0x00 + 16*(sector - 8)], 0, 16 );
+			}
+		}
+
+		if( (retval = lpc2900_write_index_page( bank, 6, &page )) != ERROR_OK )
+		{
+			LOG_ERROR("failed to update index sector page 6");
+			return retval;
+		}
+	}
+
+	/* Sectors in page 7 */
+	if( (first <= 7) && (last >= 5) )
+	{
+		memset( &page, 0xff, FLASH_PAGE_SIZE );
+		for( sector = first; sector <= last; sector++ )
+		{
+			if( (sector >= 5) && (sector <= 7) )
+			{
+				memset( &page[0x00 + 16*(sector - 5)], 0, 16 );
+			}
+		}
+
+		if( (retval = lpc2900_write_index_page( bank, 7, &page )) != ERROR_OK )
+		{
+			LOG_ERROR("failed to update index sector page 7");
+			return retval;
+		}
+	}
+
+	command_print( cmd_ctx,
+	        "Sectors security will become effective after next power cycle");
+
+	/* Update the sector security status */
+	if ( lpc2900_read_security_status(bank) != ERROR_OK )
+	{
+		LOG_ERROR( "Cannot determine sector security status" );
+		return ERROR_FLASH_OPERATION_FAILED;
+	}
+
+	return ERROR_OK;
+}
+
+
+
+/**
+ * Activate JTAG protection.
+ *
+ * @param cmd_ctx
+ * @param cmd
+ * @param args
+ * @param argc
+ */
+static int lpc2900_handle_secure_jtag_command(struct command_context_s *cmd_ctx,
+                                              char *cmd, char **args, int argc)
+{
+	if (argc < 1)
+	{
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+
+	/* Get the bank descriptor */
+	flash_bank_t *bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
+	if (!bank)
+	{
+		command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
+		return ERROR_OK;
+	}
+	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
+
+	/* Check if command execution is allowed. */
+	if( !lpc2900_info->risky )
+	{
+		command_print( cmd_ctx, "Command execution not allowed! "
+		                        "(use 'password' command first)");
+		return ERROR_COMMAND_ARGUMENT_INVALID;
+	}
+	lpc2900_info->risky = 0;
+
+	/* Prepare page */
+	uint8_t page[FLASH_PAGE_SIZE];
+	memset( &page, 0xff, FLASH_PAGE_SIZE );
+
+
+	/* Insert "soft" protection word */
+	page[0x30 + 15] = 0x7F;
+	page[0x30 + 11] = 0x7F;
+	page[0x30 +  7] = 0x7F;
+	page[0x30 +  3] = 0x7F;
+
+	/* Write to page 5 */
+	int retval;
+	if( (retval = lpc2900_write_index_page( bank, 5, &page ))
+			!= ERROR_OK )
+	{
+		LOG_ERROR("failed to update index sector page 5");
+		return retval;
+	}
+
+	LOG_INFO("JTAG security set. Good bye!");
+
+	return ERROR_OK;
+}
+
+
+
+/***********************  Flash interface functions  **************************/
+
+
+/**
+ * Register private command handlers.
+ *
+ * @param cmd_ctx
+ */
+static int lpc2900_register_commands(struct command_context_s *cmd_ctx)
+{
+	command_t *lpc2900_cmd = register_command(cmd_ctx, NULL, "lpc2900",
+	                                          NULL, COMMAND_ANY, NULL);
+
+	register_command(
+	    cmd_ctx,
+	    lpc2900_cmd,
+	    "signature",
+	    lpc2900_handle_signature_command,
+	    COMMAND_EXEC,
+	    "<bank> | "
+            "print device signature of flash bank");
+
+	register_command(
+	    cmd_ctx,
+	    lpc2900_cmd,
+	    "read_custom",
+	    lpc2900_handle_read_custom_command,
+	    COMMAND_EXEC,
+	    "<bank> <filename> | "
+            "read customer information from index sector to file");
+
+	register_command(
+	    cmd_ctx,
+	    lpc2900_cmd,
+	    "password",
+	    lpc2900_handle_password_command,
+	    COMMAND_EXEC,
+	    "<bank> <password> | "
+            "enter password to enable 'dangerous' options");
+
+	register_command(
+	    cmd_ctx,
+	    lpc2900_cmd,
+	    "write_custom",
+	    lpc2900_handle_write_custom_command,
+	    COMMAND_EXEC,
+	    "<bank> <filename> [<type>] | "
+            "write customer info from file to index sector");
+
+	register_command(
+	    cmd_ctx,
+	    lpc2900_cmd,
+	    "secure_sector",
+	    lpc2900_handle_secure_sector_command,
+	    COMMAND_EXEC,
+	    "<bank> <first> <last> | "
+            "activate sector security for a range of sectors");
+
+	register_command(
+	    cmd_ctx,
+	    lpc2900_cmd,
+	    "secure_jtag",
+	    lpc2900_handle_secure_jtag_command,
+	    COMMAND_EXEC,
+	    "<bank> <level> | "
+            "activate JTAG security");
+
+	return ERROR_OK;
+}
+
+
+/**
+ * Evaluate flash bank command.
+ *
+ * Syntax: flash bank lpc2900 0 0 0 0 target# system_base_clock
+ *
+ * @param cmd_ctx
+ * @param cmd
+ * @param args
+ * @param argc
+ * @param bank Pointer to the flash bank descriptor
+ */
+static int lpc2900_flash_bank_command(struct command_context_s *cmd_ctx,
+                                      char *cmd, char **args, int argc,
+                                      struct flash_bank_s *bank)
+{
+	lpc2900_flash_bank_t *lpc2900_info;
+
+	if (argc < 6)
+	{
+		LOG_WARNING("incomplete flash_bank LPC2900 configuration");
+		return ERROR_FLASH_BANK_INVALID;
+	}
+
+	lpc2900_info = malloc(sizeof(lpc2900_flash_bank_t));
+	bank->driver_priv = lpc2900_info;
+
+	/* Get flash clock.
+	 * Reject it if we can't meet the requirements for program time
+	 * (if clock too slow), or for erase time (clock too fast).
+	 */
+	lpc2900_info->clk_sys_fmc = strtoul(args[6], NULL, 0) * 1000;
+
+	uint32_t clock_limit;
+	/* Check program time limit */
+	clock_limit = 512000000l / FLASH_PROGRAM_TIME;
+	if (lpc2900_info->clk_sys_fmc < clock_limit)
+	{
+		LOG_WARNING("flash clock must be at least %" PRIu32 " kHz",
+                    (clock_limit / 1000));
+		return ERROR_FLASH_BANK_INVALID;
+	}
+
+	/* Check erase time limit */
+	clock_limit = (uint32_t)((32767.0 * 512.0 * 1e6) / FLASH_ERASE_TIME);
+	if (lpc2900_info->clk_sys_fmc > clock_limit)
+	{
+		LOG_WARNING("flash clock must be a maximum of %" PRIu32" kHz",
+                    (clock_limit / 1000));
+		return ERROR_FLASH_BANK_INVALID;
+	}
+
+	/* Chip ID will be obtained by probing the device later */
+	lpc2900_info->chipid = 0;
+
+	return ERROR_OK;
+}
+
+
+/**
+ * Erase sector(s).
+ *
+ * @param bank Pointer to the flash bank descriptor
+ * @param first First sector to be erased
+ * @param last Last sector (including) to be erased
+ */
+static int lpc2900_erase(struct flash_bank_s *bank, int first, int last)
+{
+	uint32_t status;
+	int sector;
+	int last_unsecured_sector;
+	target_t *target = bank->target;
+	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
+
+
+	status = lpc2900_is_ready(bank);
+	if (status != ERROR_OK)
+	{
+		return status;
+	}
+
+	/* Sanity check on sector range */
+	if ((first < 0) || (last < first) || (last >= bank->num_sectors))
+	{
+		LOG_INFO("Bad sector range");
+		return ERROR_FLASH_SECTOR_INVALID;
+	}
+
+	/* Update the info about secured sectors */
+	lpc2900_read_security_status( bank );
+
+	/* The selected sector range might include secured sectors. An attempt
+	 * to erase such a sector will cause the erase to fail also for unsecured
+	 * sectors. It is necessary to determine the last unsecured sector now,
+	 * because we have to treat the last relevant sector in the list in
+	 * a special way.
+	 */
+	last_unsecured_sector = -1;
+	for (sector = first; sector <= last; sector++)
+	{
+		if ( !bank->sectors[sector].is_protected )
+		{
+			last_unsecured_sector = sector;
+		}
+	}
+
+	/* Exit now, in case of the rare constellation where all sectors in range
+	 * are secured. This is regarded a success, since erasing/programming of
+	 * secured sectors shall be handled transparently.
+	 */
+	if ( last_unsecured_sector == -1 )
+	{
+		return ERROR_OK;
+	}
+
+	/* Enable flash block and set the correct CRA clock of 66 kHz */
+	lpc2900_setup(bank);
+
+	/* Clear END_OF_ERASE interrupt status */
+	target_write_u32(target, INT_CLR_STATUS, INTSRC_END_OF_ERASE);
+
+	/* Set the program/erase timer to FLASH_ERASE_TIME */
+	target_write_u32(target, FPTR,
+	                 FPTR_EN_T | lpc2900_calc_tr( lpc2900_info->clk_sys_fmc,
+	                                              FLASH_ERASE_TIME ));
+
+	/* Sectors are marked for erasure, then erased all together */
+	for (sector = first; sector <= last_unsecured_sector; sector++)
+	{
+		/* Only mark sectors that aren't secured. Any attempt to erase a group
+		 * of sectors will fail if any single one of them is secured!
+		 */
+		if ( !bank->sectors[sector].is_protected )
+		{
+			/* Unprotect the sector */
+			target_write_u32(target, bank->sectors[sector].offset, 0);
+			target_write_u32(target, FCTR,
+			                 FCTR_FS_LOADREQ | FCTR_FS_WPB |
+			                 FCTR_FS_WEB | FCTR_FS_WRE | FCTR_FS_CS);
+
+			/* Mark the sector for erasure. The last sector in the list
+			   triggers the erasure. */
+			target_write_u32(target, bank->sectors[sector].offset, 0);
+			if ( sector == last_unsecured_sector )
+			{
+				target_write_u32(target, FCTR,
+				                 FCTR_FS_PROGREQ | FCTR_FS_WPB | FCTR_FS_CS);
+			}
+			else
+			{
+				target_write_u32(target, FCTR,
+				                 FCTR_FS_LOADREQ | FCTR_FS_WPB |
+				                 FCTR_FS_WEB | FCTR_FS_CS);
+			}
+		}
+	}
+
+	/* Wait for the end of the erase operation. If it's not over after two seconds,
+	 * something went dreadfully wrong... :-(
+	 */
+	if( lpc2900_wait_status(bank, INTSRC_END_OF_ERASE, 2000) != ERROR_OK )
+	{
+		return ERROR_FLASH_OPERATION_FAILED;
+	}
+
+	/* Normal flash operating mode */
+	target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
+
+	return ERROR_OK;
+}
+
+
+
+static int lpc2900_protect(struct flash_bank_s *bank, int set, int first, int last)
+{
+	/* This command is not supported.
+     * "Protection" in LPC2900 terms is handled transparently. Sectors will
+     * automatically be unprotected as needed.
+     * Instead we use the concept of sector security. A secured sector is shown
+     * as "protected" in OpenOCD. Sector security is a permanent feature, and
+     * cannot be disabled once activated.
+     */
+
+	return ERROR_OK;
+}
+
+
+/**
+ * Write data to flash.
+ *
+ * @param bank Pointer to the flash bank descriptor
+ * @param buffer Buffer with data
+ * @param offset Start address (relative to bank start)
+ * @param count Number of bytes to be programmed
+ */
+static int lpc2900_write(struct flash_bank_s *bank, uint8_t *buffer,
+                         uint32_t offset, uint32_t count)
+{
+	uint8_t page[FLASH_PAGE_SIZE];
+	uint32_t status;
+	uint32_t num_bytes;
+	target_t *target = bank->target;
+	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
+	int sector;
+	int retval;
+
+	static const uint32_t write_target_code[] = {
+		/* Set auto latch mode: FCTR=CS|WRE|WEB */
+		0xe3a0a007,   /* loop       mov r10, #0x007 */
+		0xe583a000,   /*            str r10,[r3,#0] */
+
+		/* Load complete page into latches */
+		0xe3a06020,   /*            mov r6,#(512/16) */
+		0xe8b00f00,   /* next       ldmia r0!,{r8-r11} */
+		0xe8a10f00,   /*            stmia r1!,{r8-r11} */
+		0xe2566001,   /*            subs r6,#1 */
+		0x1afffffb,   /*            bne next */
+
+		/* Clear END_OF_BURN interrupt status */
+		0xe3a0a002,   /*            mov r10,#(1 << 1) */
+		0xe583afe8,   /*            str r10,[r3,#0xfe8] */
+
+		/* Set the erase time to FLASH_PROGRAM_TIME */
+		0xe5834008,   /*            str r4,[r3,#8] */
+
+		/* Trigger flash write
+			FCTR = CS | WRE | WPB | PROGREQ */
+		0xe3a0a083,   /*            mov r10,#0x83 */
+		0xe38aaa01,   /*            orr r10,#0x1000 */
+		0xe583a000,   /*            str r10,[r3,#0] */
+
+		/* Wait for end of burn */
+		0xe593afe0,   /* wait       ldr r10,[r3,#0xfe0] */
+		0xe21aa002,   /*            ands r10,#(1 << 1) */
+		0x0afffffc,   /*            beq wait */
+
+		/* End? */
+		0xe2522001,   /*            subs r2,#1 */
+		0x1affffed,   /*            bne loop */
+
+		0xeafffffe    /* done       b done */
+	};
+
+
+	status = lpc2900_is_ready(bank);
+	if (status != ERROR_OK)
+	{
+		return status;
+	}
+
+	/* Enable flash block and set the correct CRA clock of 66 kHz */
+	lpc2900_setup(bank);
+
+	/* Update the info about secured sectors */
+	lpc2900_read_security_status( bank );
+
+	/* Unprotect all involved sectors */
+	for (sector = 0; sector < bank->num_sectors; sector++)
+	{
+		/* Start address in or before this sector? */
+		/* End address in or behind this sector? */
+		if ( ((bank->base + offset) <
+		          (bank->sectors[sector].offset + bank->sectors[sector].size)) &&
+		     ((bank->base + (offset + count - 1)) >= bank->sectors[sector].offset) )
+		{
+			/* This sector is involved and needs to be unprotected.
+				* Don't do it for secured sectors.
+				*/
+			if ( !bank->sectors[sector].is_protected )
+			{
+				target_write_u32(target, bank->sectors[sector].offset, 0);
+				target_write_u32(target, FCTR,
+				                 FCTR_FS_LOADREQ | FCTR_FS_WPB |
+				                 FCTR_FS_WEB | FCTR_FS_WRE | FCTR_FS_CS);
+			}
+		}
+	}
+
+	/* Set the program/erase time to FLASH_PROGRAM_TIME */
+	uint32_t prog_time = FPTR_EN_T | lpc2900_calc_tr( lpc2900_info->clk_sys_fmc,
+	                                                  FLASH_PROGRAM_TIME );
+
+	/* If there is a working area of reasonable size, use it to program via
+	   a target algorithm. If not, fall back to host programming. */
+
+	/* We need some room for target code. */
+	uint32_t target_code_size = sizeof(write_target_code);
+
+	/* Try working area allocation. Start with a large buffer, and try with
+	   reduced size if that fails. */
+	working_area_t *warea;
+	uint32_t buffer_size = lpc2900_info->max_ram_block - 1 * KiB;
+	while( (retval = target_alloc_working_area(target,
+	                                           buffer_size + target_code_size,
+	                                           &warea)) != ERROR_OK )
+	{
+		/* Try a smaller buffer now, and stop if it's too small. */
+		buffer_size -= 1 * KiB;
+		if (buffer_size < 2 * KiB)
+		{
+			LOG_INFO( "no (large enough) working area"
+			          ", falling back to host mode" );
+			warea = NULL;
+			break;
+		}
+	};
+
+	if( warea )
+	{
+		reg_param_t reg_params[5];
+		armv4_5_algorithm_t armv4_5_info;
+
+		/* We can use target mode. Download the algorithm. */
+		retval = target_write_buffer( target,
+		                              (warea->address)+buffer_size,
+		                              target_code_size,
+		                              (uint8_t *)write_target_code);
+		if (retval != ERROR_OK)
+		{
+			LOG_ERROR("Unable to write block write code to target");
+			target_free_all_working_areas(target);
+			return ERROR_FLASH_OPERATION_FAILED;
+		}
+
+		init_reg_param(&reg_params[0], "r0", 32, PARAM_OUT);
+		init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);
+		init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);
+		init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);
+		init_reg_param(&reg_params[4], "r4", 32, PARAM_OUT);
+
+		/* Write to flash in large blocks */
+		while ( count != 0 )
+		{
+			uint32_t this_npages;
+			uint8_t *this_buffer;
+			int start_sector = lpc2900_address2sector( bank, offset );
+
+			/* First page / last page / rest */
+			if( offset % FLASH_PAGE_SIZE )
+			{
+				/* Block doesn't start on page boundary.
+				   Burn first partial page separately. */
+				memset( &page, 0xff, sizeof(page) );
+				memcpy( &page[offset % FLASH_PAGE_SIZE],
+				        buffer,
+				        FLASH_PAGE_SIZE - (offset % FLASH_PAGE_SIZE) );
+				this_npages = 1;
+				this_buffer = &page[0];
+				count = count + (offset % FLASH_PAGE_SIZE);
+				offset = offset - (offset % FLASH_PAGE_SIZE);
+			}
+			else if( count < FLASH_PAGE_SIZE )
+			{
+				/* Download last incomplete page separately. */
+				memset( &page, 0xff, sizeof(page) );
+				memcpy( &page, buffer, count );
+				this_npages = 1;
+				this_buffer = &page[0];
+				count = FLASH_PAGE_SIZE;
+			}
+			else
+			{
+				/* Download as many full pages as possible */
+				this_npages = (count < buffer_size) ?
+				               count / FLASH_PAGE_SIZE :
+				               buffer_size / FLASH_PAGE_SIZE;
+				this_buffer = buffer;
+
+				/* Make sure we stop at the next secured sector */
+				int sector = start_sector + 1;
+				while( sector < bank->num_sectors )
+				{
+					/* Secured? */
+					if( bank->sectors[sector].is_protected )
+					{
+						/* Is that next sector within the current block? */
+						if( (bank->sectors[sector].offset - bank->base) <
+							(offset + (this_npages * FLASH_PAGE_SIZE)) )
+						{
+							/* Yes! Split the block */
+							this_npages =
+							  (bank->sectors[sector].offset - bank->base - offset)
+							      / FLASH_PAGE_SIZE;
+							break;
+						}
+					}
+
+					sector++;
+				}
+			}
+
+			/* Skip the current sector if it is secured */
+			if( bank->sectors[start_sector].is_protected )
+			{
+				LOG_DEBUG( "Skip secured sector %" PRIu32, start_sector );
+
+				/* Stop if this is the last sector */
+				if( start_sector == bank->num_sectors - 1 )
+				{
+					break;
+				}
+
+				/* Skip */
+				uint32_t nskip = bank->sectors[start_sector].size -
+				                 (offset % bank->sectors[start_sector].size);
+				offset += nskip;
+				buffer += nskip;
+				count = (count >= nskip) ? (count - nskip) : 0;
+				continue;
+			}
+
+			/* Execute buffer download */
+			if ((retval = target_write_buffer(target,
+			                                  warea->address,
+			                                  this_npages * FLASH_PAGE_SIZE,
+			                                  this_buffer)) != ERROR_OK)
+			{
+				LOG_ERROR("Unable to write data to target");
+				target_free_all_working_areas(target);
+				return ERROR_FLASH_OPERATION_FAILED;
+			}
+
+			/* Prepare registers */
+			buf_set_u32(reg_params[0].value, 0, 32, warea->address);
+			buf_set_u32(reg_params[1].value, 0, 32, offset);
+			buf_set_u32(reg_params[2].value, 0, 32, this_npages);
+			buf_set_u32(reg_params[3].value, 0, 32, FCTR);
+			buf_set_u32(reg_params[4].value, 0, 32, FPTR_EN_T | prog_time);
+
+			/* Execute algorithm, assume breakpoint for last instruction */
+			armv4_5_info.common_magic = ARMV4_5_COMMON_MAGIC;
+			armv4_5_info.core_mode = ARMV4_5_MODE_SVC;
+			armv4_5_info.core_state = ARMV4_5_STATE_ARM;
+
+			retval = target_run_algorithm(target, 0, NULL, 5, reg_params,
+				(warea->address) + buffer_size,
+				(warea->address) + buffer_size + target_code_size - 4,
+				10000, /* 10s should be enough for max. 16 KiB of data */
+				&armv4_5_info);
+
+			if (retval != ERROR_OK)
+			{
+				LOG_ERROR("Execution of flash algorithm failed.");
+				target_free_all_working_areas(target);
+				retval = ERROR_FLASH_OPERATION_FAILED;
+				break;
+			}
+
+			count -= this_npages * FLASH_PAGE_SIZE;
+			buffer += this_npages * FLASH_PAGE_SIZE;
+			offset += this_npages * FLASH_PAGE_SIZE;
+		}
+
+		/* Free all resources */
+		destroy_reg_param(&reg_params[0]);
+		destroy_reg_param(&reg_params[1]);
+		destroy_reg_param(&reg_params[2]);
+		destroy_reg_param(&reg_params[3]);
+		destroy_reg_param(&reg_params[4]);
+		target_free_all_working_areas(target);
+	}
+	else
+	{
+		/* Write to flash memory page-wise */
+		while ( count != 0 )
+		{
+			/* How many bytes do we copy this time? */
+			num_bytes = (count >= FLASH_PAGE_SIZE) ?
+			            FLASH_PAGE_SIZE - (offset % FLASH_PAGE_SIZE) :
+			            count;
+
+			/* Don't do anything with it if the page is in a secured sector. */
+			if ( !bank->sectors[lpc2900_address2sector(bank, offset)].is_protected )
+			{
+				/* Set latch load mode */
+				target_write_u32(target, FCTR,
+				                 FCTR_FS_CS | FCTR_FS_WRE | FCTR_FS_WEB);
+
+				/* Always clear the buffer (a little overhead, but who cares) */
+				memset(page, 0xFF, FLASH_PAGE_SIZE);
+
+				/* Copy them to the buffer */
+				memcpy( &page[offset % FLASH_PAGE_SIZE],
+				        &buffer[offset % FLASH_PAGE_SIZE],
+				        num_bytes );
+
+				/* Write whole page to flash data latches */
+				if (target_write_memory(
+				                 target,
+				                 bank->base + (offset - (offset % FLASH_PAGE_SIZE)),
+				                 4, FLASH_PAGE_SIZE / 4, page) != ERROR_OK)
+				{
+					LOG_ERROR("Write failed @ 0x%8.8" PRIx32, offset);
+					target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
+
+					return ERROR_FLASH_OPERATION_FAILED;
+				}
+
+				/* Clear END_OF_BURN interrupt status */
+				target_write_u32(target, INT_CLR_STATUS, INTSRC_END_OF_BURN);
+
+				/* Set the programming time */
+				target_write_u32(target, FPTR, FPTR_EN_T | prog_time);
+
+				/* Trigger flash write */
+				target_write_u32(target, FCTR,
+				    FCTR_FS_CS | FCTR_FS_WRE | FCTR_FS_WPB | FCTR_FS_PROGREQ);
+
+				/* Wait for the end of the write operation. If it's not over
+				 * after one second, something went dreadfully wrong... :-(
+				 */
+				if (lpc2900_wait_status(bank, INTSRC_END_OF_BURN, 1000) != ERROR_OK)
+				{
+					LOG_ERROR("Write failed @ 0x%8.8" PRIx32, offset);
+					target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
+
+					return ERROR_FLASH_OPERATION_FAILED;
+				}
+			}
+
+			/* Update pointers and counters */
+			offset += num_bytes;
+			buffer += num_bytes;
+			count -= num_bytes;
+		}
+
+		retval = ERROR_OK;
+	}
+
+	/* Normal flash operating mode */
+	target_write_u32(target, FCTR, FCTR_FS_CS | FCTR_FS_WEB);
+
+	return retval;
+}
+
+
+/**
+ * Try and identify the device.
+ *
+ * Determine type number and its memory layout.
+ *
+ * @param bank Pointer to the flash bank descriptor
+ */
+static int lpc2900_probe(struct flash_bank_s *bank)
+{
+	lpc2900_flash_bank_t *lpc2900_info = bank->driver_priv;
+	target_t *target = bank->target;
+	int i = 0;
+	uint32_t offset;
+
+
+	if (target->state != TARGET_HALTED)
+	{
+		LOG_ERROR("Target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	/* We want to do this only once. Check if we already have a valid CHIPID,
+	 * because then we will have already successfully probed the device.
+	 */
+	if (lpc2900_info->chipid == EXPECTED_CHIPID)
+	{
+		return ERROR_OK;
+	}
+
+	/* Probing starts with reading the CHIPID register. We will continue only
+	 * if this identifies as an LPC2900 device.
+	 */
+	target_read_u32(target, CHIPID, &lpc2900_info->chipid);
+
+	if (lpc2900_info->chipid != EXPECTED_CHIPID)
+	{
+		LOG_WARNING("Device is not an LPC29xx");
+		return ERROR_FLASH_OPERATION_FAILED;
+	}
+
+	/* It's an LPC29xx device. Now read the feature register FEAT0...FEAT3. */
+	uint32_t feat0, feat1, feat2, feat3;
+	target_read_u32(target, FEAT0, &feat0);
+	target_read_u32(target, FEAT1, &feat1);
+	target_read_u32(target, FEAT2, &feat2);
+	target_read_u32(target, FEAT3, &feat3);
+
+	/* Base address */
+	bank->base = 0x20000000;
+
+	/* Determine flash layout from FEAT2 register */
+	uint32_t num_64k_sectors = (feat2 >> 16) & 0xFF;
+	uint32_t num_8k_sectors = (feat2 >> 0) & 0xFF;
+	bank->num_sectors = num_64k_sectors + num_8k_sectors;
+	bank->size = KiB * (64 * num_64k_sectors + 8 * num_8k_sectors);
+
+	/* Determine maximum contiguous RAM block */
+	lpc2900_info->max_ram_block = 16 * KiB;
+	if( (feat1 & 0x30) == 0x30 )
+	{
+		lpc2900_info->max_ram_block = 32 * KiB;
+		if( (feat1 & 0x0C) == 0x0C )
+		{
+			lpc2900_info->max_ram_block = 48 * KiB;
+		}
+	}
+
+	/* Determine package code and ITCM size */
+	uint32_t package_code = feat0 & 0x0F;
+	uint32_t itcm_code = (feat1 >> 16) & 0x1F;
+
+	/* Determine the exact type number. */
+	uint32_t found = 1;
+	if ( (package_code == 4) && (itcm_code == 5) )
+	{
+		/* Old LPC2917 or LPC2919 (non-/01 devices) */
+		lpc2900_info->target_name = (bank->size == 768*KiB) ? "LPC2919" : "LPC2917";
+	}
+	else
+	{
+		if ( package_code == 2 )
+		{
+			/* 100-pin package */
+			if ( bank->size == 128*KiB )
+			{
+				lpc2900_info->target_name = "LPC2921";
+			}
+			else if ( bank->size == 256*KiB )
+			{
+				lpc2900_info->target_name = "LPC2923";
+			}
+			else if ( bank->size == 512*KiB )
+			{
+				lpc2900_info->target_name = "LPC2925";
+			}
+			else
+			{
+				found = 0;
+			}
+		}
+		else if ( package_code == 4 )
+		{
+			/* 144-pin package */
+			if ( (bank->size == 512*KiB) && (feat3 == 0xFFFFFCF0) )
+			{
+				lpc2900_info->target_name = "LPC2917/01";
+			}
+			else if ( (bank->size == 512*KiB) && (feat3 == 0xFFFFFFF1) )
+			{
+				lpc2900_info->target_name = "LPC2927";
+			}
+			else if ( (bank->size == 768*KiB) && (feat3 == 0xFFFFFCF8) )
+			{
+				lpc2900_info->target_name = "LPC2919/01";
+			}
+			else if ( (bank->size == 768*KiB) && (feat3 == 0xFFFFFFF9) )
+			{
+				lpc2900_info->target_name = "LPC2929";
+			}
+			else
+			{
+				found = 0;
+			}
+		}
+		else if ( package_code == 5 )
+		{
+			/* 208-pin package */
+			lpc2900_info->target_name = (bank->size == 0) ? "LPC2930" : "LPC2939";
+		}
+		else
+		{
+			found = 0;
+		}
+	}
+
+	if ( !found )
+	{
+		LOG_WARNING("Unknown LPC29xx derivative");
+		return ERROR_FLASH_OPERATION_FAILED;
+	}
+
+	/* Show detected...
 
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