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[L4alpha-cvscommit] CVS: L4Alpha/pal ipc.mar,1.16,1.17

From: Daniel P. <dp...@us...> - 2002-01-03 04:17:26

Update of /cvsroot/l4alpha/L4Alpha/pal
In directory usw-pr-cvs1:/tmp/cvs-serv15606/pal

Modified Files:
	ipc.mar 
Log Message:
Whoops.. forgot to unwind the tack in 
ipc_ret_timeout


Index: ipc.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/ipc.mar,v
retrieving revision 1.16
retrieving revision 1.17
diff -C2 -d -r1.16 -r1.17
*** ipc.mar	2002/01/02 05:47:48	1.16
--- ipc.mar	2002/01/03 04:17:21	1.17
***************
*** 1029,1035 ****
  		bic	t0, #LLS_POLLING_QUEUE, t0
  		stl	t0, TCB_LIST_STATE(t12)	
! 	
! 		GET_16CONS v0, IPC_S_TIMEOUT
  		; now we unwind the stack
  	ENDIF
  	
--- 1029,1037 ----
  		bic	t0, #LLS_POLLING_QUEUE, t0
  		stl	t0, TCB_LIST_STATE(t12)	
! 
  		; now we unwind the stack
+ 		br	ra, ipc_polling_unstack
+ 
+ 		GET_16CONS v0, IPC_S_TIMEOUT
  	ENDIF

[L4alpha-cvscommit] CVS: L4Alpha/pal/21164 miata_platform.mar,1.7,1.8

From: Daniel P. <dp...@us...> - 2002-01-03 03:28:09

Update of /cvsroot/l4alpha/L4Alpha/pal/21164
In directory usw-pr-cvs1:/tmp/cvs-serv4863/pal/21164

Modified Files:
	miata_platform.mar 
Log Message:
This may or maynot reset the machine on a halt.


Index: miata_platform.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21164/miata_platform.mar,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -d -r1.7 -r1.8
*** miata_platform.mar	2002/01/02 04:08:46	1.7
--- miata_platform.mar	2002/01/03 03:28:05	1.8
***************
*** 344,347 ****
--- 344,355 ----
  	NewCom2SerialPutChar ^x68,p5,p7 ;h	
  	
+ 	GET_16CONS p7, ^x878
+ 	GET_16CONS p5, ^x900
+ 	sll	p7, #28, p7
+ 	bis	p7, p5, p7
+ 	GET_32CONS p5, ^xdead
+ 	stq_p p5, 0(p7)
+ 
+ 
  	mtpr	zero, dtbCm
  	mtpr	zero, ips

[L4alpha-cvscommit] CVS: L4Alpha/lib/l4 syscall.S,1.5,1.6

From: Daniel P. <dp...@us...> - 2002-01-03 03:26:18

Update of /cvsroot/l4alpha/L4Alpha/lib/l4
In directory usw-pr-cvs1:/tmp/cvs-serv4471/lib/l4

Modified Files:
	syscall.S 
Log Message:
Added interface to l4_whoami syscall.

Note this call is not part of the normal API.



Index: syscall.S
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/lib/l4/syscall.S,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** syscall.S	2001/04/05 08:23:40	1.5
--- syscall.S	2002/01/03 03:26:13	1.6
***************
*** 20,23 ****
--- 20,24 ----
  	.globl	l4_set_idt
  	.globl	l4_sys_time
+ 	.globl	l4_whoami
  	
  	.globl	l4_schedule
***************
*** 438,442 ****
  	ret	(ra)
  
  l4_test_cpu:
  	pal	0xAB
! 	ret	(ra)
\ No newline at end of file
--- 439,445 ----
  	ret	(ra)
  
+ l4_whoami:		
  l4_test_cpu:
  	pal	0xAB
! 	ret	(ra)
! 	
\ No newline at end of file

[L4alpha-cvscommit] CVS: L4Alpha/include/lib/l4 syscalls.h,1.6,1.7

From: Daniel P. <dp...@us...> - 2002-01-03 03:26:18

Update of /cvsroot/l4alpha/L4Alpha/include/lib/l4
In directory usw-pr-cvs1:/tmp/cvs-serv4471/include/lib/l4

Modified Files:
	syscalls.h 
Log Message:
Added interface to l4_whoami syscall.

Note this call is not part of the normal API.



Index: syscalls.h
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/include/lib/l4/syscalls.h,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** syscalls.h	2001/04/13 05:45:51	1.6
--- syscalls.h	2002/01/03 03:26:13	1.7
***************
*** 136,139 ****
--- 136,142 ----
  l4_sys_time(void);
  
+ L4_INLINE unsigned long
+ l4_whoami(void);
+ 
  #endif

[L4alpha-cvscommit] CVS: L4Alpha/user README,1.1.1.1,1.2

From: Daniel P. <dp...@us...> - 2002-01-03 02:14:42

Update of /cvsroot/l4alpha/L4Alpha/user
In directory usw-pr-cvs1:/tmp/cvs-serv21437

Modified Files:
	README 
Log Message:
Updated.


Index: README
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/user/README,v
retrieving revision 1.1.1.1
retrieving revision 1.2
diff -C2 -d -r1.1.1.1 -r1.2
*** README	2000/10/18 05:29:17	1.1.1.1
--- README	2002/01/03 02:14:37	1.2
***************
*** 4,9 ****
  To compile, simply type on of the following in the root L4/Alpha directory:
  
! make l4ecdl.boot       - to build an example application ECDL.
! make memstress.boot    - to build a simple memory/pagefault test program
! make clans.boot        - to build an ipc clans+chiefs test program
  
--- 4,9 ----
  To compile, simply type on of the following in the root L4/Alpha directory:
  
! make template-bootpfile
! 
! see L4Alpha-apps project for other example programs.

[L4alpha-cvscommit] Hi, ping

From: Goswin B. <gos...@st...> - 2002-01-02 14:47:48

Hi,

I should be on this list now.
If you can read this I am. :)

MfG
        Goswin

PS: Whats the email for the normal L4Alpha ML and where to subscribe to it?

[L4alpha-cvscommit] CVS: L4Alpha/pal ipc.mar,1.15,1.16 thread.mar,1.9,1.10

From: Daniel P. <dp...@us...> - 2002-01-02 05:47:53

Update of /cvsroot/l4alpha/L4Alpha/pal
In directory usw-pr-cvs1:/tmp/cvs-serv20720/pal

Modified Files:
	ipc.mar thread.mar 
Log Message:
Added ipc_ret_cancel_polling support
If thread being aborted or ex-reg'ed is aborted it should unwind it's stack corr
ectly (and not trash register contents)
This commit does it right for aborting threads that are currently trying to send to another thread.

Will clean up commented out code later.



Index: ipc.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/ipc.mar,v
retrieving revision 1.15
retrieving revision 1.16
diff -C2 -d -r1.15 -r1.16
*** ipc.mar	2002/01/02 04:08:46	1.15
--- ipc.mar	2002/01/02 05:47:48	1.16
***************
*** 1024,1038 ****
  		lda	AT, TCB_SEND_QUEUE (p0)			; delete this entry from send queue
  		delete_ll AT, p2, p3, ISLIST
  	
  		GET_16CONS v0, IPC_S_TIMEOUT
  		; now we unwind the stack
- .if df do_fast_asm_unfriendly_unstack
- 		lda	sp, <17 * 8>(sp)			; was 16 was 14
- .iff
- 		;; This should be the same as ipc_send_eq unstacking...
- 		pop	p_t0!p_t1!p_t2!p_t3!p_t4!p_t5!p_t6!p_t8!p_a4!p_a5!p_fp!p_v0
- 		pop	p_a0!p_a1!p_a2!p_a3
- 		pop	p_pp1
- .endc
  	ENDIF
  	
--- 1024,1035 ----
  		lda	AT, TCB_SEND_QUEUE (p0)			; delete this entry from send queue
  		delete_ll AT, p2, p3, ISLIST
+ 
+ 		;; Update list state.
+ 		ldl	t0, TCB_LIST_STATE(t12)
+ 		bic	t0, #LLS_POLLING_QUEUE, t0
+ 		stl	t0, TCB_LIST_STATE(t12)	
  	
  		GET_16CONS v0, IPC_S_TIMEOUT
  		; now we unwind the stack
  	ENDIF
  	
***************
*** 1057,1068 ****
  	full_close_frame
  
- ;;; Generic fail from IPC (reason is on stack).
  	ALIGN_FETCH_BLOCK
  ipc_ret_fail:
  .if df ev4
  	create_PPR_context
  .endc
  	enable_int	pp0
- 	pop	p_v0		; get failure result off stack
  	full_close_frame
  	
--- 1054,1079 ----
  	full_close_frame
  
  	ALIGN_FETCH_BLOCK
+ ipc_polling_unstack:
+ .if df do_fast_asm_unfriendly_unstack			;  you probably never want to enable this
+        	lda	sp, <17 * 8>(sp)
+ .iff
+        	;; This should be the same as ipc_send_eq unstacking...
+ 	pop	p_t0!p_t1!p_t2!p_t3!p_t4!p_t5!p_t6!p_t8!p_a4!p_a5!p_fp!p_v0
+ 	pop	p_a0!p_a1!p_a2!p_a3
+ 	pop	p_pp1
+ 	ret	zero, (ra)
+ .endc
+ 	
+ 				
+ ;;; ABORT fail routine from ex_reg/remote_abort (reason is on stack).
+ 	ALIGN_FETCH_BLOCK
  ipc_ret_fail:
  .if df ev4
  	create_PPR_context
  .endc
+ ;	pop	p_pp0		;  get failure off stack..
+ 
  	enable_int	pp0
  	full_close_frame
  	
***************
*** 1073,1077 ****
  .if df ev4
  	create_PPR_context
! .endc		
  	GET_16CONS	v0, IPC_S_CANCELLED
  	enable_int	t0
--- 1084,1092 ----
  .if df ev4
  	create_PPR_context
! .endc
! 
! ;	pop	p_pp0 
! 	bsr	ra, ipc_polling_unstack
! 	
  	GET_16CONS	v0, IPC_S_CANCELLED
  	enable_int	t0

Index: thread.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/thread.mar,v
retrieving revision 1.9
retrieving revision 1.10
diff -C2 -d -r1.9 -r1.10
*** thread.mar	2002/01/02 04:11:50	1.9
--- thread.mar	2002/01/02 05:47:48	1.10
***************
*** 519,525 ****
  
  	;; Restart thread and mark it as runnable
! ;	GET_16CONS t0, TFS_RUNNING
! ;	stq	t0, TCB_THREAD_STATE(t12)
! ;	enqueue_busy	t12, t0, t1, t2
  
  
--- 519,525 ----
  
  	;; Restart thread and mark it as runnable
! 	GET_16CONS t0, TFS_RUNNING
! 	stq	t0, TCB_THREAD_STATE(t12)
! 	enqueue_busy	t12, t0, t1, t2
  
  
***************
*** 896,900 ****
  	bic	t0, #TFS_POLLING, t1
  	IFZ	t1
! 		kmsg	<"Removing polling thread"<CR><LF>>
  
  		;; Thread is polling, so remove it from the other threads send root
--- 896,900 ----
  	bic	t0, #TFS_POLLING, t1
  	IFZ	t1
! ;		kmsg	<"Removing polling thread"<CR><LF>>
  
  		;; Thread is polling, so remove it from the other threads send root
***************
*** 906,914 ****
  		bic	t0, #LLS_POLLING_QUEUE, t0
  		stl	t0, TCB_LIST_STATE(t12)
! 	
! 		GET_16CONS	t1, IPC_S_CANCELLED
  		br	zero, remote_abort_out	
  	XENDIF
! 	
  	cmpeq	t0, #TFS_ABORTED, t1
  	IF	t1
--- 906,919 ----
  		bic	t0, #LLS_POLLING_QUEUE, t0
  		stl	t0, TCB_LIST_STATE(t12)
! 
! ;		GET_16CONS	t1, IPC_S_CANCELLED
! 		pal_addr t2, <ipc_ret_cancel_polling + 1>
  		br	zero, remote_abort_out	
  	XENDIF
! 
! 	;; FIXME - these cases below need a new entry point (not ipc_ret_fail)
!         ;;         like the POLLING case above has.
! 
! .if ne 0	; stupid case?
  	cmpeq	t0, #TFS_ABORTED, t1
  	IF	t1
***************
*** 916,927 ****
  		debug	; FIXME --- what to do here?
  
! 		GET_16CONS	t1, IPC_S_CANCELLED
  		br	zero, remote_abort_out	
  	XENDIF
! 		
  	cmpeq	t0, #TFS_LOCKED_RUNNING, t1
  	IF	t1
  		;; FIXME --- I probably need to clean up more state than I currently do.
! 		GET_16CONS	t1, IPC_S_ABORTED
  		br	zero, remote_abort_out	
  	XENDIF
--- 921,935 ----
  		debug	; FIXME --- what to do here?
  
! ;		GET_16CONS	t1, IPC_S_CANCELLED
! 		pal_addr t2, <ipc_ret_fail + 1>	
  		br	zero, remote_abort_out	
  	XENDIF
! .endc		
! 
  	cmpeq	t0, #TFS_LOCKED_RUNNING, t1
  	IF	t1
  		;; FIXME --- I probably need to clean up more state than I currently do.
! ;		GET_16CONS	t1, IPC_S_ABORTED
! 		pal_addr t2, <ipc_ret_fail + 1>	
  		br	zero, remote_abort_out	
  	XENDIF
***************
*** 930,934 ****
  	IF	t1
  		;; FIXME --- I probably need to clean up more state than I currently do.
! 		GET_16CONS	t1, IPC_R_ABORTED
  		br	zero, remote_abort_out	
  	XENDIF
--- 938,943 ----
  	IF	t1
  		;; FIXME --- I probably need to clean up more state than I currently do.
! ;		GET_16CONS	t1, IPC_R_ABORTED
! 		pal_addr t2, <ipc_ret_fail + 1>			
  		br	zero, remote_abort_out	
  	XENDIF
***************
*** 936,955 ****
  	;; Otherwise we were doing a receive
  	GET_16CONS	t1, IPC_R_CANCELLED
  		
         	ALIGN_FETCH_BLOCK <^x47FF041F>          ; align with nops
  remote_abort_out:
  	;; Store reason for cancel/abort on stack and reset KSP.
! 	lda	t0, <TCB_STACKTOP - <4*8>>(t12)
! 	stq	t1, 0(t0)	
! 	stq	t0, TCB_KSP(t12)
  
  	subq	zero, #1, t0
  	stq	t0, TCB_STACK_MODE(t12)
- 	
- 	pal_addr t1, <ipc_ret_fail + 1>
- 	stq	t1, TCB_RESTART(t12)
  
! 	GET_16CONS t1, TFS_ABORTED; FIXME --- Correct? (should I do this later?)
! 	stq	t1, TCB_THREAD_STATE(t12)
  
  	;; Return
--- 945,966 ----
  	;; Otherwise we were doing a receive
  	GET_16CONS	t1, IPC_R_CANCELLED
+ 	pal_addr t2, <ipc_ret_cancel_wait + 1>	
+ 	; more work to be done?
  		
         	ALIGN_FETCH_BLOCK <^x47FF041F>          ; align with nops
  remote_abort_out:
+ 	;;;  t2 is return entry point
  	;; Store reason for cancel/abort on stack and reset KSP.
! 
! ;	ldq	t0, TCB_KSP(t12)	; get stack pointer
! ;	subq	t0, #8, t0		; space for error result
! 
! ;	stq	t1, 0(t0)	
! ;	stq	t0, TCB_KSP(t12)
  
  	subq	zero, #1, t0
  	stq	t0, TCB_STACK_MODE(t12)
  
! 	stq	t2, TCB_RESTART(t12)
  
  	;; Return
***************
*** 1078,1091 ****
  		and	t0, #TCS_DEAD, t0
  		IFZ	t0			; not dying
! .if ne 0
  			kmsg	<"Aborting thread ">
  			khex	t1
  			kmsg	<<CR><LF>>
  .endc	
! 			; I'm not sure about this 
  			pal_addr t0, <ipc_ret_cancel_polling+1>	; state was polling
! 			lda	AT, <TCB_STACKTOP-<3*8>>(t1)
  
! 			stq	AT, TCB_KSP(t1)
  			stq	t0, TCB_RESTART(t1)
  			GET_16CONS t0, TFS_RUNNING
--- 1089,1106 ----
  		and	t0, #TCS_DEAD, t0
  		IFZ	t0			; not dying
! .if ne 1
  			kmsg	<"Aborting thread ">
  			khex	t1
  			kmsg	<<CR><LF>>
  .endc	
! 			; I'm not sure about this
! 	;; THIS NEEDS FIXING...
  			pal_addr t0, <ipc_ret_cancel_polling+1>	; state was polling
! ;			lda	AT, <TCB_STACKTOP-<3*8>>(t1) - changed to:	
  
! ;			ldq	AT, TCB_KSP(t1)
! ;			subq	AT, #8, AT
! 	
! ;			stq	AT, TCB_KSP(t1)
  			stq	t0, TCB_RESTART(t1)
  			GET_16CONS t0, TFS_RUNNING
***************
*** 1348,1354 ****
  				; I'm not sure about this 
  				pal_addr t6, <ipc_ret_cancel_polling+1>	; state was polling
! 				lda	AT, <TCB_STACKTOP-<3*8>>(t5)
  
! 				stq	AT, TCB_KSP(t5)
  				stq	t6, TCB_RESTART(t5)
  				GET_16CONS t6, TFS_RUNNING
--- 1363,1369 ----
  				; I'm not sure about this 
  				pal_addr t6, <ipc_ret_cancel_polling+1>	; state was polling
! ;				lda	AT, <TCB_STACKTOP-<3*8>>(t5)
  
! ;				stq	AT, TCB_KSP(t5)
  				stq	t6, TCB_RESTART(t5)
  				GET_16CONS t6, TFS_RUNNING

[L4alpha-cvscommit] CVS: L4Alpha/pal thread.mar,1.8,1.9

From: Daniel P. <dp...@us...> - 2002-01-02 04:11:54

Update of /cvsroot/l4alpha/L4Alpha/pal
In directory usw-pr-cvs1:/tmp/cvs-serv6396/pal

Modified Files:
	thread.mar 
Log Message:
whoops.. cvs didn't ask me for a comment last time.. dodgy
Some changes to remote_abort and related ex_regs stuff to make ex_reg do the right thing - ie. don't trash registers because people using l4_ex_reg for checkpointing want them...
Do other L4's do this right?

More patches will come shortly -
 this patch fixes only clean case where no IPCs are pending/polling.


Index: thread.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/thread.mar,v
retrieving revision 1.8
retrieving revision 1.9
diff -C2 -d -r1.8 -r1.9
*** thread.mar	2002/01/02 04:08:46	1.8
--- thread.mar	2002/01/02 04:11:50	1.9
***************
*** 896,900 ****
  	bic	t0, #TFS_POLLING, t1
  	IFZ	t1
! ;		kmsg	<"Removing polling thread"<CR><LF>>
  
  		;; Thread is polling, so remove it from the other threads send root
--- 896,900 ----
  	bic	t0, #TFS_POLLING, t1
  	IFZ	t1
! 		kmsg	<"Removing polling thread"<CR><LF>>
  
  		;; Thread is polling, so remove it from the other threads send root

[L4alpha-cvscommit] CVS: L4Alpha Makefile.conf,1.12,1.13

From: Daniel P. <dp...@us...> - 2002-01-02 04:08:52

Update of /cvsroot/l4alpha/L4Alpha
In directory usw-pr-cvs1:/tmp/cvs-serv6055

Modified Files:
	Makefile.conf 
Log Message:
Some extra comments...


Index: Makefile.conf
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/Makefile.conf,v
retrieving revision 1.12
retrieving revision 1.13
diff -C2 -d -r1.12 -r1.13
*** Makefile.conf	2001/12/10 04:35:39	1.12
--- Makefile.conf	2002/01/02 04:08:45	1.13
***************
*** 15,20 ****
  L4ARCH	      = 21164
  L4CPU	      = EV5
! #SYS_PLATFORM = miata
! SYS_PLATFORM = ruffian
  
  #L4ARCH	      = 21264
--- 15,20 ----
  L4ARCH	      = 21164
  L4CPU	      = EV5
! SYS_PLATFORM = miata
! #SYS_PLATFORM = ruffian
  
  #L4ARCH	      = 21264
***************
*** 28,32 ****
  	L4BL := $(L4ROOT)/../L4Alpha-bl/smp_l4bl.nh
  else
! 	L4BL := $(L4ROOT)/../L4Alpha-bl/l4bl.nh
  endif
  
--- 28,33 ----
  	L4BL := $(L4ROOT)/../L4Alpha-bl/smp_l4bl.nh
  else
! 	L4BL := $(L4ROOT)/../L4Alpha-bl/ruffian_l4bl
! #	L4BL := $(L4ROOT)/../L4Alpha-bl/l4bl.nh
  endif

[L4alpha-cvscommit] CVS: L4Alpha/pal ipc.mar,1.14,1.15 thread.mar,1.7,1.8

From: Daniel P. <dp...@us...> - 2002-01-02 04:08:52

Update of /cvsroot/l4alpha/L4Alpha/pal
In directory usw-pr-cvs1:/tmp/cvs-serv6055/pal

Modified Files:
	ipc.mar thread.mar 
Log Message:
Some extra comments...


Index: ipc.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/ipc.mar,v
retrieving revision 1.14
retrieving revision 1.15
diff -C2 -d -r1.14 -r1.15
*** ipc.mar	2001/04/13 05:45:51	1.14
--- ipc.mar	2002/01/02 04:08:46	1.15
***************
*** 512,519 ****
  	;; PROBLEM - registers covered by PALshadow need to be saved too!!!!
  
  .if df ev6
  
  	; push non-overlapping and shadow registers
! 	push	p_pp1!p_a0!p_a1!p_a2!p_a3
  
  	; now switch to kernel mode and store the others, then switch to the dispatcher
--- 512,523 ----
  	;; PROBLEM - registers covered by PALshadow need to be saved too!!!!
  
+ 	;; NOTE - ipc_ret_timeout and possibly others rely on the other of
+         ;;        pushed registers, so that it can unwind them
+ 
  .if df ev6
  
  	; push non-overlapping and shadow registers
! 	push	p_pp1
! 	push	p_a0!p_a1!p_a2!p_a3
  
  	; now switch to kernel mode and store the others, then switch to the dispatcher
***************
*** 530,534 ****
  
  .iff
! 	push	p_pp1!p_t0!p_t1!p_t2!p_t3!p_t4!p_t5!p_t6!p_t8!p_a0!p_a1!p_a2!p_a3!p_a4!p_a5!p_fp!p_v0
  	switch_dispatcher	pp0, ipc_send_eq, pp4, pp2; can optimise by going to kernel mode and coming back in kernel mode, then switching to pal...
  .endc
--- 534,541 ----
  
  .iff
! 	;; see note about as to why we do them separately...
! 	push	p_pp1
! 	push	p_a0!p_a1!p_a2!p_a3
! 	push	p_t0!p_t1!p_t2!p_t3!p_t4!p_t5!p_t6!p_t8!p_a4!p_a5!p_fp!p_v0
  	switch_dispatcher	pp0, ipc_send_eq, pp4, pp2; can optimise by going to kernel mode and coming back in kernel mode, then switching to pal...
  .endc
***************
*** 550,554 ****
  	mode_pal	
  ipc_send_eq_ev6:	
! 	pop	p_pp1!p_a0!p_a1!p_a2!p_a3
  	enable_int
  
--- 557,562 ----
  	mode_pal	
  ipc_send_eq_ev6:	
! 	pop	p_a0!p_a1!p_a2!p_a3
! 	pop	p_pp1
  	enable_int
  
***************
*** 558,564 ****
  .if df ev4
  	create_PPR_context
! .endc	
! 
! 	pop	p_pp1!p_t0!p_t1!p_t2!p_t3!p_t4!p_t5!p_t6!p_t8!p_a0!p_a1!p_a2!p_a3!p_a4!p_a5!p_fp!p_v0	
  .endc
  	
--- 566,573 ----
  .if df ev4
  	create_PPR_context
! .endc
! 	pop	p_t0!p_t1!p_t2!p_t3!p_t4!p_t5!p_t6!p_t8!p_a4!p_a5!p_fp!p_v0
! 	pop	p_a0!p_a1!p_a2!p_a3
! 	pop	p_pp1
  .endc
  	
***************
*** 1017,1022 ****
  	
  		GET_16CONS v0, IPC_S_TIMEOUT
! 		lda	sp, <16 * 8>(sp)			; was 14
  	ENDIF
  	enable_int	pp0
  	full_close_frame
--- 1026,1042 ----
  	
  		GET_16CONS v0, IPC_S_TIMEOUT
! 		; now we unwind the stack
! .if df do_fast_asm_unfriendly_unstack
! 		lda	sp, <17 * 8>(sp)			; was 16 was 14
! .iff
! 		;; This should be the same as ipc_send_eq unstacking...
! 		pop	p_t0!p_t1!p_t2!p_t3!p_t4!p_t5!p_t6!p_t8!p_a4!p_a5!p_fp!p_v0
! 		pop	p_a0!p_a1!p_a2!p_a3
! 		pop	p_pp1
! .endc
  	ENDIF
+ 	
+ 	;; Any other thread states we need to unstack for?
+ 	
  	enable_int	pp0
  	full_close_frame
***************
*** 1044,1048 ****
  .endc
  	enable_int	pp0
! 	pop	p_v0	
  	full_close_frame
  	
--- 1064,1068 ----
  .endc
  	enable_int	pp0
! 	pop	p_v0		; get failure result off stack
  	full_close_frame
  	

Index: thread.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/thread.mar,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -d -r1.7 -r1.8
*** thread.mar	2001/04/13 05:45:51	1.7
--- thread.mar	2002/01/02 04:08:46	1.8
***************
*** 515,523 ****
  	ENDIF
  
  	;; Restart thread and mark it as runnable
! 	GET_16CONS t0, TFS_RUNNING
! 	stq	t0, TCB_THREAD_STATE(t12)
! 	enqueue_busy	t12, t0, t1, t2
  
  lerk_out:	
  	pop	p_ra
--- 515,527 ----
  	ENDIF
  
+ 	;; FIXME - commented out as threads appear to be already running...
+ 	;;    this has bad effects for register contents... danielp 20011220
+ 
  	;; Restart thread and mark it as runnable
! ;	GET_16CONS t0, TFS_RUNNING
! ;	stq	t0, TCB_THREAD_STATE(t12)
! ;	enqueue_busy	t12, t0, t1, t2
  
+ 
  lerk_out:	
  	pop	p_ra
***************
*** 537,541 ****
  	ALIGN_FETCH_BLOCK
  	mode_normal
! lerk_remote:	
  	;; Push PC, SP, Pager, leave room for tid.
  	subq	sp, #<3 * 8>, sp
--- 541,545 ----
  	ALIGN_FETCH_BLOCK
  	mode_normal
! lerk_remote:
  	;; Push PC, SP, Pager, leave room for tid.
  	subq	sp, #<3 * 8>, sp
***************
*** 865,870 ****
  	ALIGN_FETCH_BLOCK
  remote_abort:	
! ;	kmsg	<"<L4> Remote Abort"<CR><LF>>
! 	
  	ldl	t0, TCB_LIST_STATE(t12)
  	and	t0, #LLS_SOON_WAKEUP_QUEUE, t1
--- 869,874 ----
  	ALIGN_FETCH_BLOCK
  remote_abort:	
! ;	kmsg	<"Remote Abort"<CR><LF>>
! 
  	ldl	t0, TCB_LIST_STATE(t12)
  	and	t0, #LLS_SOON_WAKEUP_QUEUE, t1
***************
*** 884,895 ****
  
  	ldq	t0, TCB_THREAD_STATE(t12)
! 	cmpeq	t0, #TFS_RUNNING, t1
! 	IF	t1
  		;; Thread was running, so we do nothing.
  		return_pk   ra
  	XENDIF
  	
! 	cmpeq	t0, #TFS_POLLING, t1
! 	IF	t1
  ;		kmsg	<"Removing polling thread"<CR><LF>>
  
--- 888,899 ----
  
  	ldq	t0, TCB_THREAD_STATE(t12)
! 	bic	t0, #TFS_RUNNING, t1
! 	IFZ	t1
  		;; Thread was running, so we do nothing.
  		return_pk   ra
  	XENDIF
  	
! 	bic	t0, #TFS_POLLING, t1
! 	IFZ	t1
  ;		kmsg	<"Removing polling thread"<CR><LF>>
  
***************
*** 988,992 ****
  	mov	t1, a4
  .endc
! 	
  	addq	a1, #1, t0
  	ldq	t1, TCB_PAGER (t12)
--- 992,996 ----
  	mov	t1, a4
  .endc
! 
  	addq	a1, #1, t0
  	ldq	t1, TCB_PAGER (t12)
***************
*** 1005,1017 ****
  		stq	a2, TCB_STACK_PC(t12)			
  
! 		lda	t0, <TCB_STACKTOP - <3*8>>(t12)
! 		stq	t0, TCB_KSP(t12)
  
! 		krn_addr t0, _thread_startup
! 		stq	t0, TCB_RESTART(t12)
  
  		;; Update mode to user
! 		subq	zero, #1, t0
! 		stq	t0, TCB_STACK_MODE(t12)
  
  		;; We need to delete the thread (update version etc.) so return 1.
--- 1009,1021 ----
  		stq	a2, TCB_STACK_PC(t12)			
  
! ;		lda	t0, <TCB_STACKTOP - <3*8>>(t12)
! ;		stq	t0, TCB_KSP(t12)
  
! ;		krn_addr t0, _thread_startup
! ;		stq	t0, TCB_RESTART(t12)
  
  		;; Update mode to user
! ;		subq	zero, #1, t0
! ;		stq	t0, TCB_STACK_MODE(t12)
  
  		;; We need to delete the thread (update version etc.) so return 1.
***************
*** 1305,1310 ****
  	
  	; remove if polling 
! 	and	t2, #TFS_POLLING, t5			; This may not be correct op
! 	IF	t5
  	
  		and     t1, #LLS_POLLING_QUEUE, t5	; is it really still there?
--- 1309,1314 ----
  	
  	; remove if polling 
! 	bic	t2, #TFS_POLLING, t5			; This may not be correct op
! 	IFZ	t5
  	
  		and     t1, #LLS_POLLING_QUEUE, t5	; is it really still there?

[L4alpha-cvscommit] CVS: L4Alpha/pal/21164 miata_platform.mar,1.6,1.7

From: Daniel P. <dp...@us...> - 2002-01-02 04:08:52

Update of /cvsroot/l4alpha/L4Alpha/pal/21164
In directory usw-pr-cvs1:/tmp/cvs-serv6055/pal/21164

Modified Files:
	miata_platform.mar 
Log Message:
Some extra comments...


Index: miata_platform.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21164/miata_platform.mar,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** miata_platform.mar	2001/04/13 05:45:52	1.6
--- miata_platform.mar	2002/01/02 04:08:46	1.7
***************
*** 777,781 ****
  	
  				stq_a	p4, TCB_KSP(p1)
! 				stq_a	p2, 0(p4)
  
  				GET_16CONS p2, TFS_RUNNING
--- 777,781 ----
  	
  				stq_a	p4, TCB_KSP(p1)
! 				stq_a	p2, 0(p4)			; write thread state onto stack for later processing
  
  				GET_16CONS p2, TFS_RUNNING

[L4alpha-cvscommit] CVS: L4Alpha/pal/21164 ruffian_platform.mar,1.1,1.2

From: Daniel P. <dp...@us...> - 2001-12-10 04:35:45

Update of /cvsroot/l4alpha/L4Alpha/pal/21164
In directory usw-pr-cvs1:/tmp/cvs-serv938/pal/21164

Modified Files:
	ruffian_platform.mar 
Log Message:
Added code to enable ruffian timer interrupt.
Details:

The Ruffian mother board did not correctly wire the timer tick interrupt to the CPU, as such no timer interrupts are received. The solution (a software fix) is to use the RTC timer interrupt INT0 on one of the ISA chips to do the same work.

Unfortunately this requires as to add PYXIS support into the L4 kernel, enable the timer interrupt and interrupt contoller, detect this interrupt via the device interrupt routines then check if it is INT0 timer interrupt. If so we reroute this to the L4 timer interrupt handler.

The we I have done this may cause issues with proper device driver interrupts - and vice versa.


Index: ruffian_platform.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21164/ruffian_platform.mar,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** ruffian_platform.mar	2001/12/10 00:52:19	1.1
--- ruffian_platform.mar	2001/12/10 04:35:39	1.2
***************
*** 848,853 ****
  	ALIGN_FETCH_BLOCK
  sys_int21_handler:
! 	; RUFFIAN - We need to check it this is int0 first, if we need to redirect it
  
  	open_frame
  	device_handler_cont			; generic device interrupt code.
--- 848,860 ----
  	ALIGN_FETCH_BLOCK
  sys_int21_handler:
! 	
! 	; RUFFIAN - We need to check it this is int0 first, 
! 	;	    if we need to redirect it
! 
! 	pyxis_IACK p0, p1
! 	and	p0, #^xff, p0
! 	br	p0, sys_int22_handler ;  redirect to timer interrupt
  
+ 	
  	open_frame
  	device_handler_cont			; generic device interrupt code.
***************
*** 943,947 ****
  	ALIGN_FETCH_BLOCK
  interrupt_init:	
! 	;; FIXME
  	PVC_JSR init_interrupts, bsr=1, dest=1
  	ret	zero, (ra)
--- 950,1023 ----
  	ALIGN_FETCH_BLOCK
  interrupt_init:	
! 
! 	OutPortByte ^x43,^xb6, t1, t2
! 	OutPortByte ^x42,^x31, t1, t2
! 	OutPortByte ^x42,^x13, t1, t2
! 
! 	GET_16CONS  t0, P_INT_BASE_B
! 	sll	t0, #P_INT_BASE_S, t0
! 
! 	;; Invert 6 & 7 for i82371
! 
! 	GET_16CONS  t1, ^x00c0
! 	stq_p	t1, PO_INT_HILO(t0)	; set HILO (invert bits)
! 	mb
! 	GET_16CONS  t1, ^x2064		; set CNFG - should this 2 be set?
! 	stq_p	t1, PO_INT_CNFG(t0)
! 	mb
! 	stq_p	zero, PO_INT_MASK(t0)	; set MASK
! 	mb
! 	subq	zero, #1, t1		; set REQ (correct??)
! 	stq_p	t1, PO_INT_REQ(t0)
! 	mb
! 
! 	;+ (Re)Initialise the PIC as already done in sys_reset
! 	;
! 	; Initialize the 82C59A priority interrupt controller (PIC)
! 	;
! 
! 	OutPortByte PIC2_ICW1,^x11,t0,t1
! 	OutPortByte PIC2_ICW2,^x08,t0,t1
! 	OutPortByte PIC2_ICW3,^x02,t0,t1
! 	OutPortByte PIC2_ICW4,^x01,t0,t1
! 
! 	OutPortByte PIC2_OCW1,^xFF,t0,t1
! 
! 	OutPortByte PIC1_ICW1,^x11,t0,t1
! 	OutPortByte PIC1_ICW2,^x00,t0,t1
! 	OutPortByte PIC1_ICW3,^x04,t0,t1
! 	OutPortByte PIC1_ICW4,^x01,t0,t1
! 
! 	OutPortByte PIC1_OCW1,^xFF,t0,t1
! 
! 	pyxis_IACK t2, t1	; PYXIS -INTA pulse (clear interrupts)
! 
! 	; Finish writing 82c59A PIC operation control words
! 
! 	OutPortByte PIC2_OCW2,^x20, t0, t1
! 	OutPortByte PIC1_OCW2,^x20, t0, t1
! 
! 	; Turn on interrupt controller and timer interrupt
! 	
! ;	GET_32CONS t3, ^xff7fffff	; ~(1 << (16 + 7))
! ;	GET_32CONS t4, ^xffffffbf
! 
! ;	sll	t3, #16, t3
! ;	ornot	zero, t3, t3	; not t3
! ;	and	t3, t4, t4
! 	; FIXME - the above code generates 0xffbf which seems wrong...
! 	; ofcourse it does what we expect as the right bits are cleared.
! 
! 	GET_32CONS t4, ^xffbf
! 
! 	stq_p	t4, PO_INT_MASK(t0)
! 	mb
! 	ldq_p	t4, PO_INT_MASK(t0)	; read back
! 
! 	; Invert bits 2 and 0
! 
! 	OutPortByte PIC1_OCW1, ^xfb, t1, t2	; enable 0
! 	OutPortByte PIC1_OCW1, ^xfa, t1, t2	; enable 2
! 	
  	PVC_JSR init_interrupts, bsr=1, dest=1
  	ret	zero, (ra)

[L4alpha-cvscommit] CVS: L4Alpha Makefile.conf,1.11,1.12

From: Daniel P. <dp...@us...> - 2001-12-10 04:35:44

Update of /cvsroot/l4alpha/L4Alpha
In directory usw-pr-cvs1:/tmp/cvs-serv938

Modified Files:
	Makefile.conf 
Log Message:
Added code to enable ruffian timer interrupt.
Details:

The Ruffian mother board did not correctly wire the timer tick interrupt to the CPU, as such no timer interrupts are received. The solution (a software fix) is to use the RTC timer interrupt INT0 on one of the ISA chips to do the same work.

Unfortunately this requires as to add PYXIS support into the L4 kernel, enable the timer interrupt and interrupt contoller, detect this interrupt via the device interrupt routines then check if it is INT0 timer interrupt. If so we reroute this to the L4 timer interrupt handler.

The we I have done this may cause issues with proper device driver interrupts - and vice versa.


Index: Makefile.conf
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/Makefile.conf,v
retrieving revision 1.11
retrieving revision 1.12
diff -C2 -d -r1.11 -r1.12
*** Makefile.conf	2001/11/12 05:23:25	1.11
--- Makefile.conf	2001/12/10 04:35:39	1.12
***************
*** 15,19 ****
  L4ARCH	      = 21164
  L4CPU	      = EV5
! SYS_PLATFORM = miata
  
  #L4ARCH	      = 21264
--- 15,20 ----
  L4ARCH	      = 21164
  L4CPU	      = EV5
! #SYS_PLATFORM = miata
! SYS_PLATFORM = ruffian
  
  #L4ARCH	      = 21264

[L4alpha-cvscommit] CVS: L4Alpha/pal kernel.mar,1.7,1.8

From: Daniel P. <dp...@us...> - 2001-12-10 04:35:44

Update of /cvsroot/l4alpha/L4Alpha/pal
In directory usw-pr-cvs1:/tmp/cvs-serv938/pal

Modified Files:
	kernel.mar 
Log Message:
Added code to enable ruffian timer interrupt.
Details:

The Ruffian mother board did not correctly wire the timer tick interrupt to the CPU, as such no timer interrupts are received. The solution (a software fix) is to use the RTC timer interrupt INT0 on one of the ISA chips to do the same work.

Unfortunately this requires as to add PYXIS support into the L4 kernel, enable the timer interrupt and interrupt contoller, detect this interrupt via the device interrupt routines then check if it is INT0 timer interrupt. If so we reroute this to the L4 timer interrupt handler.

The we I have done this may cause issues with proper device driver interrupts - and vice versa.


Index: kernel.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/kernel.mar,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -d -r1.7 -r1.8
*** kernel.mar	2001/04/13 05:45:51	1.7
--- kernel.mar	2001/12/10 04:35:39	1.8
***************
*** 382,387 ****
  	PVC_JSR interrupt_init bsr=1
  	bsr	ra, interrupt_init
! 	enable_int
! 	kmsg <"Interrupts configured and enabled."<CR><LF>>
  .endc	
  
--- 382,386 ----
  	PVC_JSR interrupt_init bsr=1
  	bsr	ra, interrupt_init
! 	kmsg <"Interrupts configured."<CR><LF>>
  .endc

[L4alpha-cvscommit] CVS: L4Alpha/pal/21164/macros ruffian.mar,1.1,1.2

From: Daniel P. <dp...@us...> - 2001-12-10 04:35:44

Update of /cvsroot/l4alpha/L4Alpha/pal/21164/macros
In directory usw-pr-cvs1:/tmp/cvs-serv938/pal/21164/macros

Modified Files:
	ruffian.mar 
Log Message:
Added code to enable ruffian timer interrupt.
Details:

The Ruffian mother board did not correctly wire the timer tick interrupt to the CPU, as such no timer interrupts are received. The solution (a software fix) is to use the RTC timer interrupt INT0 on one of the ISA chips to do the same work.

Unfortunately this requires as to add PYXIS support into the L4 kernel, enable the timer interrupt and interrupt contoller, detect this interrupt via the device interrupt routines then check if it is INT0 timer interrupt. If so we reroute this to the L4 timer interrupt handler.

The we I have done this may cause issues with proper device driver interrupts - and vice versa.


Index: ruffian.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21164/macros/ruffian.mar,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** ruffian.mar	2001/12/10 00:52:19	1.1
--- ruffian.mar	2001/12/10 04:35:40	1.2
***************
*** 42,46 ****
  ; Who   When            What
  ; ---   ----            ----
! ; DP	2000 03 07	Initial implementation
  ;
  ; These defines are taken from the 21174 TRM
--- 42,47 ----
  ; Who   When            What
  ; ---   ----            ----
! ; DP	2001 12 10	Initial implementation
! ; DP	2001 12 10	pyxis_IACK for pyxis interrupt ack
  ;
  ; These defines are taken from the 21174 TRM
***************
*** 76,78 ****
  	bis	zero, zero, res			; not implemented
  .endm
! 	
\ No newline at end of file
--- 77,85 ----
  	bis	zero, zero, res			; not implemented
  .endm
! 	
! ; pyxis_IACK - send PYXIS -INTA pulse to clear any pending interrupts
! .macro	pyxis_IACK res, tmp1
! 	GET_16CONS tmp1, P_IACK_SC_B
! 	sll	   tmp1, #P_IACK_SC_S, tmp1
! 	ldq_p	   res, 0(tmp1)
! .endm

[L4alpha-cvscommit] CVS: L4Alpha/pal/21164/macros ruffian.mar,NONE,1.1

From: Daniel P. <dp...@us...> - 2001-12-10 00:52:25

Update of /cvsroot/l4alpha/L4Alpha/pal/21164/macros
In directory usw-pr-cvs1:/tmp/cvs-serv12390/macros

Added Files:
	ruffian.mar 
Log Message:
Ruffian support file based on Miata (generic) 21164 support files.


--- NEW FILE: ruffian.mar ---
;+       
;        $Id: ruffian.mar,v 1.1 2001/12/10 00:52:19 dpotts Exp $
; 
;      Copyright (C) 1999 - 2001, Daniel Potts, University of New South Wales.
; 
;      Copyright (C) 1995, 1996, Sebastian Schoenberg, University of 
;      Technology Dresden, Department of Computer Science.
; 
;      This file is part of the L4/Alpha micro-kernel distribution.
; 
;      This program is free software; you can redistribute it and/or
;      modify it under the terms of the GNU General Public License
;      as published by the Free Software Foundation; either version 2
;      of the License, or (at your option) any later version.
;      
;      This program is distributed in the hope that it will be useful,
;      but WITHOUT ANY WARRANTY; without even the implied warranty of
;      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;      GNU General Public License for more details.
;      
;      You should have received a copy of the GNU General Public License
;      along with this program; if not, write to the Free Software
;      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
;      
;- 

;+ -*- asm -*-
; ruffian.mar - PYXIS chipset support 
;-

;+
; CPU:		21164
; CPU config:   Uniprocessor  (PYXIS)
; Written By:   Daniel Potts
; Creation:	2000 03 07
; Last Edit:    2000 03 07
; Description:	PYXIS (2117x)
;		
; Defines:	
; 
; Edit History
; Who   When            What
; ---   ----            ----
; DP	2000 03 07	Initial implementation
;
; These defines are taken from the 21174 TRM
;
; Defines for Interrupt related stuff
;-

; We want interrupts to be initialised for the timer interrupt in particular
.iif ndf interrupts, interrupts = 1

	P_INT_BASEADDR	 = ^x87a0000000

	P_INT_BASE_B     = ^x87a
	P_INT_BASE_S     = 28

	PO_INT_REQ       = ^x000
	PO_INT_MASK      = ^x040
	PO_INT_HILO      = ^x0C0
	PO_INT_ROUTE     = ^x140
	PO_GPO           = ^x180
	PO_INT_CNFG      = ^x1C0
	PO_RT_COUNT      = ^x200
	PO_IIC_CTRL      = ^x2C0

; Defines for other PYXIS related stuff

	P_IACK_SC	  = ^x8720000000

	P_IACK_SC_B	  = ^x872
	P_IACK_SC_S	  = 28

.macro probe_int_src res, tmp1, tmp2, tmp3
	bis	zero, zero, res			; not implemented
.endm

[L4alpha-cvscommit] CVS: L4Alpha/pal/21164 ruffian_platform.mar,NONE,1.1

From: Daniel P. <dp...@us...> - 2001-12-10 00:52:25

Update of /cvsroot/l4alpha/L4Alpha/pal/21164
In directory usw-pr-cvs1:/tmp/cvs-serv12390

Added Files:
	ruffian_platform.mar 
Log Message:
Ruffian support file based on Miata (generic) 21164 support files.


--- NEW FILE: ruffian_platform.mar ---
;+       
;        $Id: ruffian_platform.mar,v 1.1 2001/12/10 00:52:19 dpotts Exp $
; 
;      Copyright (C) 1999 - 2001, Daniel Potts, University of New South Wales.
; 
;      Copyright (C) 1995, 1996, Sebastian Schoenberg, University of 
;      Technology Dresden, Department of Computer Science.
; 
;      This file is part of the L4/Alpha micro-kernel distribution.
; 
;      This program is free software; you can redistribute it and/or
;      modify it under the terms of the GNU General Public License
;      as published by the Free Software Foundation; either version 2
;      of the License, or (at your option) any later version.
;      
;      This program is distributed in the hope that it will be useful,
;      but WITHOUT ANY WARRANTY; without even the implied warranty of
;      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;      GNU General Public License for more details.
[...1070 lines suppressed...]
	srl     v0, #39, pp1			; Get high bit of bad pa.
	blbs    pp1, CrdScrubMemory_exit	; Don't fixup IO space.

	NOP					; Load must be on octaword.
	NOP

	ldq_lp  pp1, 0(v0)			; Attempt to read the bad memory.
	NOP					; Keep request in E0 pipe.

	stq_cp  pp1, 0(v0)			; Store it back if still there.

	; If store fails, it was scrubbed by someone else.
	; At this point, eiStat or bcStat could be locked due to a new correctable
	; error on the load, so read eiStat to unlock AFTER this routine.

CrdScrubMemory_exit:
	ret     zero, (pp5)			; Back we go.

			
	END_FREE_CODE

[L4alpha-cvscommit] CVS: L4Alpha/pal memory.mar,1.5,1.6

From: Daniel P. <dp...@us...> - 2001-12-10 00:21:40

Update of /cvsroot/l4alpha/L4Alpha/pal
In directory usw-pr-cvs1:/tmp/cvs-serv6248

Modified Files:
	memory.mar 
Log Message:
Outputs a % when a mapping that already exists is present.
This is a temporary measure....


Index: memory.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/memory.mar,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** memory.mar	2001/11/27 00:36:49	1.5
--- memory.mar	2001/12/10 00:21:35	1.6
***************
*** 707,711 ****
  ipte_translation_valid:
  	bne	t4, ipte_guard_fault
! ;	NewCom2SerialPutChar ^x78,t10,t9 ; x
  	; Here there is already a translation
  	; we should get the pointer and update the (new) permissions
--- 707,711 ----
  ipte_translation_valid:
  	bne	t4, ipte_guard_fault
! 	NewCom2SerialPutChar ^x25,t10,t9 ; %
  	; Here there is already a translation
  	; we should get the pointer and update the (new) permissions
***************
*** 716,722 ****
  
  	; We don't bother flushing entry here, it can be done in TLB fault handler.
  	
! ;	PVC_JSR mem_insert_pte bsr=1 dest=1; 
! ;	ret	zero, (ra)			; Entry is always in tabls
  	
  	;+
--- 716,723 ----
  
  	; We don't bother flushing entry here, it can be done in TLB fault handler.
+ 
  	
! 	PVC_JSR mem_insert_pte bsr=1 dest=1; 
! 	ret	zero, (ra)			; Entry is always in tabls
  	
  	;+

[L4alpha-cvscommit] CVS: L4Alpha/pal/21164 l4_pal.mar,1.8,1.9

From: Daniel P. <dp...@us...> - 2001-11-28 03:03:50

Update of /cvsroot/l4alpha/L4Alpha/pal/21164
In directory usw-pr-cvs1:/tmp/cvs-serv31344/pal/21164

Modified Files:
	l4_pal.mar 
Log Message:
Pass OPCDEC (illegal instruction - IDT_INSTRUCTION) to l4_do_exception idt handler.


Index: l4_pal.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21164/l4_pal.mar,v
retrieving revision 1.8
retrieving revision 1.9
diff -C2 -d -r1.8 -r1.9
*** l4_pal.mar	2001/04/13 05:45:52	1.8
--- l4_pal.mar	2001/11/28 03:03:44	1.9
***************
*** 629,642 ****
  	START_HW_VECTOR <OPCDEC>
  
!        	open_frame
! 	push	p_r0
! 	mfpr	r0, excAddr
! 	STALL
! 	STALL
! 	debug
! 	STALL
! 	syshalt	^xdec
! 	;; ldiq	p0, IDT_INSTRUCTION
! 	;; br	l4_do_exception
  
  	END_HW_VECTOR
--- 629,643 ----
  	START_HW_VECTOR <OPCDEC>
  
! 	;open_frame
! 	;push	p_r0
! 	;mfpr	r0, excAddr
! 	;STALL
! 	;STALL
! 	;debug
! 	;STALL
! 	;syshalt	^xdec
! 
! 	GET_16CONS p0, IDT_INSTRUCTION
! 	br	zero, l4_do_exception
  
  	END_HW_VECTOR

[L4alpha-cvscommit] CVS: L4Alpha/pal memory.mar,1.4,1.5

From: Daniel P. <dp...@us...> - 2001-11-27 00:36:54

Update of /cvsroot/l4alpha/L4Alpha/pal
In directory usw-pr-cvs1:/tmp/cvs-serv26003/pal

Modified Files:
	memory.mar 
Log Message:
Intermediate fix to check for PT entries already present before adding matching entry.
If a matching entry is discovered, it is overwritten so that the new permissions will be updated.



Index: memory.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/memory.mar,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** memory.mar	2001/04/13 05:45:51	1.4
--- memory.mar	2001/11/27 00:36:49	1.5
***************
*** 669,672 ****
--- 669,674 ----
  	GET_16CONS	t5, ^x1c0
  
+ 	bis	t6, #PP_INTREE, t6		; we want to check it doesn't already exist..
+ 	
  	task_nr	t0, t0				; t0 - task_nr
  	pal_addr t1, pal_ptroots		; root pointer of ptabs
***************
*** 705,710 ****
  ipte_translation_valid:
  	bne	t4, ipte_guard_fault
! 	PVC_JSR mem_insert_pte bsr=1 dest=1
! 	ret	zero, (ra)			; Entry is always in tabls
  	
  	;+
--- 707,722 ----
  ipte_translation_valid:
  	bne	t4, ipte_guard_fault
! ;	NewCom2SerialPutChar ^x78,t10,t9 ; x
! 	; Here there is already a translation
! 	; we should get the pointer and update the (new) permissions
! 
! 	GET_16CONS AT, ^x3ff
! 	bic	t3, AT, t2
! 	br	zero, ipte_insert_empty		; overwrite old entry
! 
! 	; We don't bother flushing entry here, it can be done in TLB fault handler.
! 	
! ;	PVC_JSR mem_insert_pte bsr=1 dest=1; 
! ;	ret	zero, (ra)			; Entry is always in tabls
  	
  	;+

[L4alpha-cvscommit] CVS: L4Alpha-tools Makefile,1.3,1.4

From: Daniel P. <dp...@us...> - 2001-11-26 09:00:36

Update of /cvsroot/l4alpha/L4Alpha-tools
In directory usw-pr-cvs1:/tmp/cvs-serv12429

Modified Files:
	Makefile 
Log Message:
Creates bin/ dir for tools and installs them there.


Index: Makefile
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha-tools/Makefile,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** Makefile	2001/11/12 05:16:39	1.3
--- Makefile	2001/11/26 09:00:30	1.4
***************
*** 6,10 ****
  TOOL_PATH:=bin
  
! all:
  	make -C hal
  	make -C hal-ev5
--- 6,10 ----
  TOOL_PATH:=bin
  
! all: bin
  	make -C hal
  	make -C hal-ev5
***************
*** 24,27 ****
--- 24,30 ----
  	make clean -C mapcvt
  #	make clean -C sysgen
+ 
+ bin:
+ 	mkdir -p bin
  
  realclean: clean

[L4alpha-cvscommit] CVS: L4Alpha-bl Makefile,1.8,1.9

From: Daniel P. <dp...@us...> - 2001-11-26 02:49:26

Update of /cvsroot/l4alpha/L4Alpha-bl
In directory usw-pr-cvs1:/tmp/cvs-serv6753

Modified Files:
	Makefile 
Log Message:
The "export" is important!


Index: Makefile
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha-bl/Makefile,v
retrieving revision 1.8
retrieving revision 1.9
diff -C2 -d -r1.8 -r1.9
*** Makefile	2001/11/12 04:52:08	1.8
--- Makefile	2001/11/26 02:49:20	1.9
***************
*** 21,25 ****
  ASFLAGS = $(INCLUDES)
  
- 
  #
  # There shouldn't be any need to change anything below this line.
--- 21,24 ----
***************
*** 33,36 ****
--- 32,37 ----
  SIZEMAGIC=L4SIZ1
  
+ export
+ 
  all: all-recursive l4bl.nh
  
***************
*** 52,56 ****
  
  lib/%:
! 	$(MAKE) -C lib $* 
  
  clean: clean-recursive
--- 53,57 ----
  
  lib/%:
! 	$(MAKE) -C lib $* $(MFLAGS)
  
  clean: clean-recursive

[L4alpha-cvscommit] CVS: L4Alpha/Documentation INSTALL,1.5,1.6

From: Daniel P. <dp...@us...> - 2001-11-12 05:25:34

Update of /cvsroot/l4alpha/L4Alpha/Documentation
In directory usw-pr-cvs1:/tmp/cvs-serv14345/Documentation

Modified Files:
	INSTALL 
Log Message:
Updated to refer to dite rather then edit.


Index: INSTALL
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/Documentation/INSTALL,v
retrieving revision 1.5
retrieving revision 1.6
diff -C2 -d -r1.5 -r1.6
*** INSTALL	2001/04/05 13:31:14	1.5
--- INSTALL	2001/11/12 05:25:22	1.6
***************
*** 61,66 ****
  
  If you  are not compiling on  a Linux/Alpha system then  you need to  set up a
! cross  compiler.  ELF support  is  required  for  the Alpha  image  generator
! (edit/dite) tool which currently only understands ELF and raw files.
  
  Recommended setup is as follows:
--- 61,66 ----
  
  If you  are not compiling on  a Linux/Alpha system then  you need to  set up a
! cross compiler.   ELF support is required  for the Alpha  image generator dite
! tool which currently only understands ELF and raw files.
  
  Recommended setup is as follows:

[L4alpha-cvscommit] CVS: L4Alpha Makefile.conf,1.10,1.11

From: Daniel P. <dp...@us...> - 2001-11-12 05:23:30

Update of /cvsroot/l4alpha/L4Alpha
In directory usw-pr-cvs1:/tmp/cvs-serv14050

Modified Files:
	Makefile.conf 
Log Message:
Cleanup for Makefile.conf.



Index: Makefile.conf
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/Makefile.conf,v
retrieving revision 1.10
retrieving revision 1.11
diff -C2 -d -r1.10 -r1.11
*** Makefile.conf	2001/11/12 04:07:26	1.10
--- Makefile.conf	2001/11/12 05:23:25	1.11
***************
*** 6,13 ****
  BOOTPFILE := /tftp/bootpfile
  
- # Bootloader
- L4BL := $(L4ROOT)/../L4Alpha-bl/l4bl.nh
- 
- 
  # Define output format
  #DEBUG = GDB
--- 6,9 ----
***************
*** 25,31 ****
  #SYS_PLATFORM = dp264
  
- 
  MAX_NUM_CPUS = 1
  
  # The path of the cross-compiler binaries, should be blank if you are using 
  # a native compiler.
--- 21,33 ----
  #SYS_PLATFORM = dp264
  
  MAX_NUM_CPUS = 1
  
+ # Bootloader
+ ifneq ($(MAX_NUM_CPUS),  1)
+ 	L4BL := $(L4ROOT)/../L4Alpha-bl/smp_l4bl.nh
+ else
+ 	L4BL := $(L4ROOT)/../L4Alpha-bl/l4bl.nh
+ endif
+ 
  # The path of the cross-compiler binaries, should be blank if you are using 
  # a native compiler.
***************
*** 33,42 ****
  #XCCPREFIX := alpha-dec-osf-
  #XCCFLAGS := -DCROSS_COMPILE_32_TO_64_BITS
- 
- #XCCPATH := /import/ganter/1/disy/alphacrossdev/bin/
- #XCCPREFIX := alphaev56-elf-linux-
  
! #XCCPATH := /home/danielp/new-alpha/bin/
! #XCCPREFIX := alpha-linux-
  
  # User level GDB debugging support
--- 35,40 ----
  #XCCPREFIX := alpha-dec-osf-
  #XCCFLAGS := -DCROSS_COMPILE_32_TO_64_BITS
  
! XCCPREFIX := alpha-linux-
  
  # User level GDB debugging support
***************
*** 59,63 ****
  
  # location for digital's tools such as sysgen, hfcomp and compression images
! EB_TOOLBOX=/home/sjw/bin
  
  
--- 57,61 ----
  
  # location for digital's tools such as sysgen, hfcomp and compression images
! EB_TOOLBOX=$(L4ROOT)/../L4Alpha-tools/bin
  
  
***************
*** 88,92 ****
  PVC	:= $(EB_TOOLBOX)/pvc
  MAPCVT	:= $(EB_TOOLBOX)/mapcvt
! DITE	:= /home/sjw/bin/dite
  CPP     := cpp
  CC      := $(XCCPATH)$(XCCPREFIX)gcc
--- 86,90 ----
  PVC	:= $(EB_TOOLBOX)/pvc
  MAPCVT	:= $(EB_TOOLBOX)/mapcvt
! DITE	:= dite
  CPP     := cpp
  CC      := $(XCCPATH)$(XCCPREFIX)gcc

[L4alpha-cvscommit] CVS: L4Alpha-tools/pvc Makefile,1.1,1.2

From: Daniel P. <dp...@us...> - 2001-11-12 05:16:45

Update of /cvsroot/l4alpha/L4Alpha-tools/pvc
In directory usw-pr-cvs1:/tmp/cvs-serv10680/pvc

Modified Files:
	Makefile 
Log Message:
Added fixes from brett's tree for more friendly compiles. His comment is as follows:

Added an install target.
Also fixed standard ('all') target so you can actually type make more then once withit working.
Removed references to Simons and Dans home directories.
Changed C flags so it will compile using gcc (note the code uses a variable called 'inline' so its not going to compile on most compilers).



Index: Makefile
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha-tools/pvc/Makefile,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** Makefile	2000/11/27 04:22:13	1.1
--- Makefile	2001/11/12 05:16:39	1.2
***************
*** 7,11 ****
  #TOOLBOX	    	= $(EB_TOOLBOX)
  
! CFLAGS		= -DEV6 -g3
  
  LINT		= /usr/bin/lint
--- 7,11 ----
  #TOOLBOX	    	= $(EB_TOOLBOX)
  
! CFLAGS		= -DEV6 -g3 -ansi
  
  LINT		= /usr/bin/lint
***************
*** 29,32 ****
--- 29,33 ----
  		chmod 775 ../bin/pvc
  
+ MAKEFILE=Makefile
  depend: $(SFILES)
  		makedepend -f $(MAKEFILE) -- $(CFLAGS) -- $(SFILES)

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