[L4alpha-cvscommit] CVS: L4Alpha/pal/21164 ruffian_platform.mar,1.1,1.2

[Daniel P. <dp...@us...>]

Update of /cvsroot/l4alpha/L4Alpha/pal/21164
In directory usw-pr-cvs1:/tmp/cvs-serv938/pal/21164

Modified Files:
	ruffian_platform.mar 
Log Message:
Added code to enable ruffian timer interrupt.
Details:

The Ruffian mother board did not correctly wire the timer tick interrupt to the CPU, as such no timer interrupts are received. The solution (a software fix) is to use the RTC timer interrupt INT0 on one of the ISA chips to do the same work.

Unfortunately this requires as to add PYXIS support into the L4 kernel, enable the timer interrupt and interrupt contoller, detect this interrupt via the device interrupt routines then check if it is INT0 timer interrupt. If so we reroute this to the L4 timer interrupt handler.

The we I have done this may cause issues with proper device driver interrupts - and vice versa.


Index: ruffian_platform.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21164/ruffian_platform.mar,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** ruffian_platform.mar	2001/12/10 00:52:19	1.1
--- ruffian_platform.mar	2001/12/10 04:35:39	1.2
***************
*** 848,853 ****
  	ALIGN_FETCH_BLOCK
  sys_int21_handler:
! 	; RUFFIAN - We need to check it this is int0 first, if we need to redirect it
  
  	open_frame
  	device_handler_cont			; generic device interrupt code.
--- 848,860 ----
  	ALIGN_FETCH_BLOCK
  sys_int21_handler:
! 	
! 	; RUFFIAN - We need to check it this is int0 first, 
! 	;	    if we need to redirect it
! 
! 	pyxis_IACK p0, p1
! 	and	p0, #^xff, p0
! 	br	p0, sys_int22_handler ;  redirect to timer interrupt
  
+ 	
  	open_frame
  	device_handler_cont			; generic device interrupt code.
***************
*** 943,947 ****
  	ALIGN_FETCH_BLOCK
  interrupt_init:	
! 	;; FIXME
  	PVC_JSR init_interrupts, bsr=1, dest=1
  	ret	zero, (ra)
--- 950,1023 ----
  	ALIGN_FETCH_BLOCK
  interrupt_init:	
! 
! 	OutPortByte ^x43,^xb6, t1, t2
! 	OutPortByte ^x42,^x31, t1, t2
! 	OutPortByte ^x42,^x13, t1, t2
! 
! 	GET_16CONS  t0, P_INT_BASE_B
! 	sll	t0, #P_INT_BASE_S, t0
! 
! 	;; Invert 6 & 7 for i82371
! 
! 	GET_16CONS  t1, ^x00c0
! 	stq_p	t1, PO_INT_HILO(t0)	; set HILO (invert bits)
! 	mb
! 	GET_16CONS  t1, ^x2064		; set CNFG - should this 2 be set?
! 	stq_p	t1, PO_INT_CNFG(t0)
! 	mb
! 	stq_p	zero, PO_INT_MASK(t0)	; set MASK
! 	mb
! 	subq	zero, #1, t1		; set REQ (correct??)
! 	stq_p	t1, PO_INT_REQ(t0)
! 	mb
! 
! 	;+ (Re)Initialise the PIC as already done in sys_reset
! 	;
! 	; Initialize the 82C59A priority interrupt controller (PIC)
! 	;
! 
! 	OutPortByte PIC2_ICW1,^x11,t0,t1
! 	OutPortByte PIC2_ICW2,^x08,t0,t1
! 	OutPortByte PIC2_ICW3,^x02,t0,t1
! 	OutPortByte PIC2_ICW4,^x01,t0,t1
! 
! 	OutPortByte PIC2_OCW1,^xFF,t0,t1
! 
! 	OutPortByte PIC1_ICW1,^x11,t0,t1
! 	OutPortByte PIC1_ICW2,^x00,t0,t1
! 	OutPortByte PIC1_ICW3,^x04,t0,t1
! 	OutPortByte PIC1_ICW4,^x01,t0,t1
! 
! 	OutPortByte PIC1_OCW1,^xFF,t0,t1
! 
! 	pyxis_IACK t2, t1	; PYXIS -INTA pulse (clear interrupts)
! 
! 	; Finish writing 82c59A PIC operation control words
! 
! 	OutPortByte PIC2_OCW2,^x20, t0, t1
! 	OutPortByte PIC1_OCW2,^x20, t0, t1
! 
! 	; Turn on interrupt controller and timer interrupt
! 	
! ;	GET_32CONS t3, ^xff7fffff	; ~(1 << (16 + 7))
! ;	GET_32CONS t4, ^xffffffbf
! 
! ;	sll	t3, #16, t3
! ;	ornot	zero, t3, t3	; not t3
! ;	and	t3, t4, t4
! 	; FIXME - the above code generates 0xffbf which seems wrong...
! 	; ofcourse it does what we expect as the right bits are cleared.
! 
! 	GET_32CONS t4, ^xffbf
! 
! 	stq_p	t4, PO_INT_MASK(t0)
! 	mb
! 	ldq_p	t4, PO_INT_MASK(t0)	; read back
! 
! 	; Invert bits 2 and 0
! 
! 	OutPortByte PIC1_OCW1, ^xfb, t1, t2	; enable 0
! 	OutPortByte PIC1_OCW1, ^xfa, t1, t2	; enable 2
! 	
  	PVC_JSR init_interrupts, bsr=1, dest=1
  	ret	zero, (ra)