[L4alpha-cvscommit] CVS: L4Alpha Makefile.conf,1.11,1.12

[Daniel P. <dp...@us...>]

Update of /cvsroot/l4alpha/L4Alpha
In directory usw-pr-cvs1:/tmp/cvs-serv938

Modified Files:
	Makefile.conf 
Log Message:
Added code to enable ruffian timer interrupt.
Details:

The Ruffian mother board did not correctly wire the timer tick interrupt to the CPU, as such no timer interrupts are received. The solution (a software fix) is to use the RTC timer interrupt INT0 on one of the ISA chips to do the same work.

Unfortunately this requires as to add PYXIS support into the L4 kernel, enable the timer interrupt and interrupt contoller, detect this interrupt via the device interrupt routines then check if it is INT0 timer interrupt. If so we reroute this to the L4 timer interrupt handler.

The we I have done this may cause issues with proper device driver interrupts - and vice versa.


Index: Makefile.conf
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/Makefile.conf,v
retrieving revision 1.11
retrieving revision 1.12
diff -C2 -d -r1.11 -r1.12
*** Makefile.conf	2001/11/12 05:23:25	1.11
--- Makefile.conf	2001/12/10 04:35:39	1.12
***************
*** 15,19 ****
  L4ARCH	      = 21164
  L4CPU	      = EV5
! SYS_PLATFORM = miata
  
  #L4ARCH	      = 21264
--- 15,20 ----
  L4ARCH	      = 21164
  L4CPU	      = EV5
! #SYS_PLATFORM = miata
! SYS_PLATFORM = ruffian
  
  #L4ARCH	      = 21264