[L4alpha-cvscommit] CVS: L4Alpha/pal/21164/macros ruffian.mar,1.1,1.2

[Daniel P. <dp...@us...>]

Update of /cvsroot/l4alpha/L4Alpha/pal/21164/macros
In directory usw-pr-cvs1:/tmp/cvs-serv938/pal/21164/macros

Modified Files:
	ruffian.mar 
Log Message:
Added code to enable ruffian timer interrupt.
Details:

The Ruffian mother board did not correctly wire the timer tick interrupt to the CPU, as such no timer interrupts are received. The solution (a software fix) is to use the RTC timer interrupt INT0 on one of the ISA chips to do the same work.

Unfortunately this requires as to add PYXIS support into the L4 kernel, enable the timer interrupt and interrupt contoller, detect this interrupt via the device interrupt routines then check if it is INT0 timer interrupt. If so we reroute this to the L4 timer interrupt handler.

The we I have done this may cause issues with proper device driver interrupts - and vice versa.


Index: ruffian.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21164/macros/ruffian.mar,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** ruffian.mar	2001/12/10 00:52:19	1.1
--- ruffian.mar	2001/12/10 04:35:40	1.2
***************
*** 42,46 ****
  ; Who   When            What
  ; ---   ----            ----
! ; DP	2000 03 07	Initial implementation
  ;
  ; These defines are taken from the 21174 TRM
--- 42,47 ----
  ; Who   When            What
  ; ---   ----            ----
! ; DP	2001 12 10	Initial implementation
! ; DP	2001 12 10	pyxis_IACK for pyxis interrupt ack
  ;
  ; These defines are taken from the 21174 TRM
***************
*** 76,78 ****
  	bis	zero, zero, res			; not implemented
  .endm
! 	
\ No newline at end of file
--- 77,85 ----
  	bis	zero, zero, res			; not implemented
  .endm
! 	
! ; pyxis_IACK - send PYXIS -INTA pulse to clear any pending interrupts
! .macro	pyxis_IACK res, tmp1
! 	GET_16CONS tmp1, P_IACK_SC_B
! 	sll	   tmp1, #P_IACK_SC_S, tmp1
! 	ldq_p	   res, 0(tmp1)
! .endm