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[L4alpha-cvscommit] CVS: L4Alpha/pal/21264 l4_pal.mar,1.13,1.14

From: Daniel P. <dp...@us...> - 2002-02-10 12:38:04

Update of /cvsroot/l4alpha/L4Alpha/pal/21264
In directory usw-pr-cvs1:/tmp/cvs-serv32332/pal/21264

Modified Files:
	l4_pal.mar 
Log Message:
(Finally) added support for read-only pages.

Tested on 21264 only. 
WARNING: The 21064 and 21164 updates will come in a later commit.


Index: l4_pal.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21264/l4_pal.mar,v
retrieving revision 1.13
retrieving revision 1.14
diff -C2 -d -r1.13 -r1.14
*** l4_pal.mar	7 Feb 2002 07:30:08 -0000	1.13
--- l4_pal.mar	10 Feb 2002 12:37:58 -0000	1.14
***************
*** 127,130 ****
--- 127,145 ----
  
  
+ .macro pf_stack
+        ; WHY?
+        GET_32CONS    AT, ^x12345678, zero
+        push    p_AT
+        bis     zero, zero, AT
+ .endm
+ 
+ 	
+ 
+ .macro pf_restack
+ 	addq    sp, #8, sp
+ .endm
+ 
+ 	
+ 
  ;
  ; EV6 shadow register usage 
***************
*** 748,759 ****
  
  trap__dfault_no_dismiss:
  
! 	hw_mfpr	pp1, EV6__VA				; (4-7,1L) get va
  
! 	open_frame pp7
! 	debug
  
- 	; FIXME - needs to be implemented..
- 	br	zero, pal_halt_cont
  
  ;+
--- 763,787 ----
  
  trap__dfault_no_dismiss:
+ 	hw_mfpr	pp3, EV6__VA				; (4-7,1L) get va
  
! 	fast_open_frame pp7
  
! 	; User permissions or something is astray for this page,
! 	; lets call the right handler.
! 
! 	push   p_pp0!p_pp1 	; OPTIMISATION:	needed here? (same as dtb_protection_fault)
! 	push	p_a0!p_a1!p_a2!p_AT!p_gp
! 
! 	; Lets flush it here, so we don't need to later
! 	xtb_flush_entry pp3, a0	; warning, watch out for violations (we should stall)
! 		
! 	ldq_a	a1, ^x38(sp)    ; exception address
! 
! 	mov	pp3, a0		; faulting address
! 	mov	pp5, a2		; mm_stat
! 
! 	pf_stack
! 	kernel	l4_dtb_protection_fault
  
  
  ;+
***************
*** 1704,1707 ****
--- 1732,1756 ----
  	END_CALL_PAL
  	
+ ;+------------------------------------------------------------------------------
+ ;  FUNCTION [pal 0x??]: l4_profiling
+ ;	Turns syscall profiling on/off
+ ; 
+ ;  MODE: U
+ ; 
+ ;  INPUT PARAMETERS:
+ ;       a0: phys address of area to start writing profile data.
+ ; 
+ ;  OUTPUT PARAMTERES:
+ ;	
+ ;  
+ ;  SIDE EFFECTS
+ ;-	
+ .if df profiling_enabled
+ 	START_CALL_PAL	<PROFILE>
+ 	stq_p	a0, PROFILE_OFFSET(zero)		
+ 	hw_ret	(pp7)
+ 	END_CALL_PAL
+ .endc
+ 
  	END_FREE_CODE
  
***************
*** 1869,1886 ****
  	syshalt ^xdead
  	;; FIXME
- 
- 
- .macro pf_stack
-        ; WHY?
-        GET_32CONS    AT, ^x12345678, zero
-        push    p_AT
-        bis     zero, zero, AT
- .endm
- 
- 	
- 
- .macro pf_restack
- 	addq    sp, #8, sp
- .endm
  
  
--- 1918,1921 ----

[L4alpha-cvscommit] CVS: L4Alpha/pal/macros l4_pal_defs.mar,1.4,1.5

From: Daniel P. <dp...@us...> - 2002-02-10 12:38:04

Update of /cvsroot/l4alpha/L4Alpha/pal/macros
In directory usw-pr-cvs1:/tmp/cvs-serv32332/pal/macros

Modified Files:
	l4_pal_defs.mar 
Log Message:
(Finally) added support for read-only pages.

Tested on 21264 only. 
WARNING: The 21064 and 21164 updates will come in a later commit.


Index: l4_pal_defs.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/macros/l4_pal_defs.mar,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** l4_pal_defs.mar	13 Apr 2001 05:45:52 -0000	1.4
--- l4_pal_defs.mar	10 Feb 2002 12:37:58 -0000	1.5
***************
*** 104,107 ****
--- 104,109 ----
  	L4PAL_FUNC__L4_WHOAMI		= ^xAB
  
+ 	L4PAL_FUNC__PROFILE		= ^xAA ; profiling hack
+ 
  	CNF_SETIDT			= 0 ; L4_CONFIG def

[L4alpha-cvscommit] CVS: L4Alpha/pal/21264/macros dp264.mar,1.7,1.8

From: Daniel P. <dp...@us...> - 2002-02-10 12:38:04

Update of /cvsroot/l4alpha/L4Alpha/pal/21264/macros
In directory usw-pr-cvs1:/tmp/cvs-serv32332/pal/21264/macros

Modified Files:
	dp264.mar 
Log Message:
(Finally) added support for read-only pages.

Tested on 21264 only. 
WARNING: The 21064 and 21164 updates will come in a later commit.


Index: dp264.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21264/macros/dp264.mar,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -d -r1.7 -r1.8
*** dp264.mar	13 Apr 2001 05:45:52 -0000	1.7
--- dp264.mar	10 Feb 2002 12:37:58 -0000	1.8
***************
*** 65,69 ****
  	sll	tmp1, #28, tmp1			; move into place
  	stq_p	tmp2, ^x80(tmp1)		; write to 801.A000.0080
! 	ldq_p	tmp2, ^x80(tmp1)		; make sure write completes
  	mb			
  .endm
--- 65,69 ----
  	sll	tmp1, #28, tmp1			; move into place
  	stq_p	tmp2, ^x80(tmp1)		; write to 801.A000.0080
! ;	ldq_p	tmp2, ^x80(tmp1)		; make sure write completes
  	mb			
  .endm

[L4alpha-cvscommit] CVS: L4Alpha/user/sigma0 main.c,1.4,1.5

From: Daniel P. <dp...@us...> - 2002-02-10 08:00:33

Update of /cvsroot/l4alpha/L4Alpha/user/sigma0
In directory usw-pr-cvs1:/tmp/cvs-serv21259/user/sigma0

Modified Files:
	main.c 
Log Message:
Modifed sigma0 that maps/grants pages read-write. 

This is added as kernel now cares about write permissions.



Index: main.c
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/user/sigma0/main.c,v
retrieving revision 1.4
retrieving revision 1.5
diff -C2 -d -r1.4 -r1.5
*** main.c	14 Jan 2002 09:30:00 -0000	1.4
--- main.c	10 Feb 2002 08:00:26 -0000	1.5
***************
*** 196,200 ****
  */
  	      regs.val[0] = 
! 		  regs.val[1] = (regs.val[0] & ~PAGEMASK) | (13 << 2) | 1;
  /*
  	  }
--- 196,200 ----
  */
  	      regs.val[0] = 
! 		  regs.val[1] = (regs.val[0] & ~PAGEMASK) | (13 << 2) | 2| 1;
  /*
  	  }

[L4alpha-cvscommit] CVS: L4Alpha/pal/21264 l4_pal.mar,1.12,1.13

From: Daniel P. <dp...@us...> - 2002-02-07 07:30:14

Update of /cvsroot/l4alpha/L4Alpha/pal/21264
In directory usw-pr-cvs1:/tmp/cvs-serv32315/pal/21264

Modified Files:
	l4_pal.mar 
Log Message:

Update to l4_do_exception to also stack that stack pointer used by l4_return


Index: l4_pal.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21264/l4_pal.mar,v
retrieving revision 1.12
retrieving revision 1.13
diff -C2 -d -r1.12 -r1.13
*** l4_pal.mar	7 Feb 2002 07:17:17 -0000	1.12
--- l4_pal.mar	7 Feb 2002 07:30:08 -0000	1.13
***************
*** 2584,2589 ****
  			ldq_a	pp3, TCB_IDT(pp1)
  			IF	pp3
! 				subq	sp, #8, sp
! 				stq	pp2, 0(sp)	; Push user stackpointer  
  				s8addq	pp0, pp3, pp3	; p3 = p3 + 8 * p0 => idt entry
  				ldq	pp3, 0(pp3)	; Load interrupt entry		
--- 2584,2590 ----
  			ldq_a	pp3, TCB_IDT(pp1)
  			IF	pp3
! 				stq	sp, -8(sp)	; Push user stack-pointer
! 				subq	sp, #16, sp
! 				stq	pp2, 0(sp)	; Push user exc-pointer  
  				s8addq	pp0, pp3, pp3	; p3 = p3 + 8 * p0 => idt entry
  				ldq	pp3, 0(pp3)	; Load interrupt entry

[L4alpha-cvscommit] CVS: L4Alpha/pal/21064 l4_pal.mar,1.7,1.8

From: Daniel P. <dp...@us...> - 2002-02-07 07:30:14

Update of /cvsroot/l4alpha/L4Alpha/pal/21064
In directory usw-pr-cvs1:/tmp/cvs-serv32315/pal/21064

Modified Files:
	l4_pal.mar 
Log Message:

Update to l4_do_exception to also stack that stack pointer used by l4_return


Index: l4_pal.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21064/l4_pal.mar,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -d -r1.7 -r1.8
*** l4_pal.mar	7 Feb 2002 07:17:17 -0000	1.7
--- l4_pal.mar	7 Feb 2002 07:30:08 -0000	1.8
***************
*** 2435,2440 ****
  			ldq_a	p3, TCB_IDT(p1)
  			IF	p3
! 				subq	sp, #8, sp
! 				stq	p2, 0(sp)	; Push user stackpointer  
  				s8addq	p0, p3, p3	; p3 = p3 + 8 * p0 => idt entry
  				ldq	p3, 0(p3)	; Load interrupt entry		
--- 2435,2441 ----
  			ldq_a	p3, TCB_IDT(p1)
  			IF	p3
! 				stq	sp, -8(sp)	; Push user stack-pointer
! 				subq	sp, #16, sp
! 				stq	p2, 0(sp)	; Push user exc-pointer  
  				s8addq	p0, p3, p3	; p3 = p3 + 8 * p0 => idt entry
  				ldq	p3, 0(p3)	; Load interrupt entry

[L4alpha-cvscommit] CVS: L4Alpha/pal/21164 l4_pal.mar,1.10,1.11

From: Daniel P. <dp...@us...> - 2002-02-07 07:30:14

Update of /cvsroot/l4alpha/L4Alpha/pal/21164
In directory usw-pr-cvs1:/tmp/cvs-serv32315/pal/21164

Modified Files:
	l4_pal.mar 
Log Message:

Update to l4_do_exception to also stack that stack pointer used by l4_return


Index: l4_pal.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21164/l4_pal.mar,v
retrieving revision 1.10
retrieving revision 1.11
diff -C2 -d -r1.10 -r1.11
*** l4_pal.mar	7 Feb 2002 07:15:30 -0000	1.10
--- l4_pal.mar	7 Feb 2002 07:30:08 -0000	1.11
***************
*** 2183,2188 ****
  			ldq_a	p3, TCB_IDT(p1)
  			IF	p3
! 				subq	sp, #8, sp
! 				stq	p2, 0(sp)	; Push user stackpointer  
  				s8addq	p0, p3, p3	; p3 = p3 + 8 * p0 => idt entry
  				ldq	p3, 0(p3)	; Load interrupt entry		
--- 2183,2189 ----
  			ldq_a	p3, TCB_IDT(p1)
  			IF	p3
! 				stq	sp, -8(sp)	; Push user stack-pointer
! 				subq	sp, #16, sp
! 				stq	p2, 0(sp)	; Push user exc-pointer  
  				s8addq	p0, p3, p3	; p3 = p3 + 8 * p0 => idt entry
  				ldq	p3, 0(p3)	; Load interrupt entry

[L4alpha-cvscommit] CVS: L4Alpha/pal/21264 l4_pal.mar,1.11,1.12

From: Daniel P. <dp...@us...> - 2002-02-07 07:17:22

Update of /cvsroot/l4alpha/L4Alpha/pal/21264
In directory usw-pr-cvs1:/tmp/cvs-serv29804/pal/21264

Modified Files:
	l4_pal.mar 
Log Message:
L4_return now accepts new pc AND sp:
offset 0 bytes is pc
offset 8 bytes is sp



Index: l4_pal.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21264/l4_pal.mar,v
retrieving revision 1.11
retrieving revision 1.12
diff -C2 -d -r1.11 -r1.12
*** l4_pal.mar	13 Apr 2001 05:45:52 -0000	1.11
--- l4_pal.mar	7 Feb 2002 07:17:17 -0000	1.12
***************
*** 1539,1543 ****
  l4_return:
  	ldq	pp1, 0(sp)
! 	addq	sp, #8, sp
  	bic	pp1, #3, pp1
  
--- 1539,1543 ----
  l4_return:
  	ldq	pp1, 0(sp)
! 	ldq	sp, 8(sp)
  	bic	pp1, #3, pp1

[L4alpha-cvscommit] CVS: L4Alpha/pal/21064 l4_pal.mar,1.6,1.7

From: Daniel P. <dp...@us...> - 2002-02-07 07:17:22

Update of /cvsroot/l4alpha/L4Alpha/pal/21064
In directory usw-pr-cvs1:/tmp/cvs-serv29804/pal/21064

Modified Files:
	l4_pal.mar 
Log Message:
L4_return now accepts new pc AND sp:
offset 0 bytes is pc
offset 8 bytes is sp



Index: l4_pal.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21064/l4_pal.mar,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** l4_pal.mar	13 Apr 2001 05:45:52 -0000	1.6
--- l4_pal.mar	7 Feb 2002 07:17:17 -0000	1.7
***************
*** 1341,1347 ****
  	mini_save
  	ldq	p1, 0(sp)
! 	addq	sp, #8, sp
  	bic	p1, #3, p1
- 
  
  	mtpr	p1, excAddr
--- 1341,1346 ----
  	mini_save
  	ldq	p1, 0(sp)
! 	ldq	sp, 8(sp)
  	bic	p1, #3, p1
  
  	mtpr	p1, excAddr

[L4alpha-cvscommit] CVS: L4Alpha/pal/21164 l4_pal.mar,1.9,1.10

From: Daniel P. <dp...@us...> - 2002-02-07 07:15:36

Update of /cvsroot/l4alpha/L4Alpha/pal/21164
In directory usw-pr-cvs1:/tmp/cvs-serv29267/pal/21164

Modified Files:
	l4_pal.mar 
Log Message:
L4_return now accepts new pc AND sp:
offset 0 bytes is pc
offset 8 bytes is sp


Index: l4_pal.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21164/l4_pal.mar,v
retrieving revision 1.9
retrieving revision 1.10
diff -C2 -d -r1.9 -r1.10
*** l4_pal.mar	28 Nov 2001 03:03:44 -0000	1.9
--- l4_pal.mar	7 Feb 2002 07:15:30 -0000	1.10
***************
*** 1144,1148 ****
  l4_return:
  	ldq	p1, 0(sp)
! 	addq	sp, #8, sp
  	bic	p1, #3, p1
  	mtpr	p1, excAddr
--- 1144,1148 ----
  l4_return:
  	ldq	p1, 0(sp)
! 	ldq	sp, 8(sp)
  	bic	p1, #3, p1
  	mtpr	p1, excAddr

[L4alpha-cvscommit] CVS: L4Alpha/pal ipc.mar,1.20,1.21

From: Daniel P. <dp...@us...> - 2002-02-06 03:20:24

Update of /cvsroot/l4alpha/L4Alpha/pal
In directory usw-pr-cvs1:/tmp/cvs-serv18986/pal

Modified Files:
	ipc.mar 
Log Message:
Once again, I'm hopless with my debug trashing registers...


Index: ipc.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/ipc.mar,v
retrieving revision 1.20
retrieving revision 1.21
diff -C2 -d -r1.20 -r1.21
*** ipc.mar	2002/01/22 12:48:23	1.20
--- ipc.mar	2002/02/06 03:20:17	1.21
***************
*** 592,596 ****
  
  	IF	pp2
! 		NewCom2SerialPutChar ^x29,pp5,pp4 ; )
  
  		lda	AT, TCB_SEND_QUEUE(pp0)
--- 592,596 ----
  
  	IF	pp2
! ;		NewCom2SerialPutChar ^x29,pp5,pp3 ; )
  
  		lda	AT, TCB_SEND_QUEUE(pp0)

[L4alpha-cvscommit] CVS: L4Alpha/pal memory.mar,1.7,1.8

From: Daniel P. <dp...@us...> - 2002-02-05 06:24:08

Update of /cvsroot/l4alpha/L4Alpha/pal
In directory usw-pr-cvs1:/tmp/cvs-serv13134/L4Alpha/pal

Modified Files:
	memory.mar 
Log Message:
Heh.. sometimes I comment out too much. Weird weird bug where it seemed to work most of the time due to a random valid address in t9.




Index: memory.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/memory.mar,v
retrieving revision 1.7
retrieving revision 1.8
diff -C2 -d -r1.7 -r1.8
*** memory.mar	2002/01/18 09:22:10	1.7
--- memory.mar	2002/02/05 06:24:00	1.8
***************
*** 718,722 ****
  ;	bic	t3, AT, t2
  
! ;	mov	t8, t9
  ;	bis	t2, #13, t2			; set guard` length
  ;	or	t2, a4, t2
--- 718,722 ----
  ;	bic	t3, AT, t2
  
! 	mov	t8, t9
  ;	bis	t2, #13, t2			; set guard` length
  ;	or	t2, a4, t2

[L4alpha-cvscommit] CVS: L4Alpha/pal/macros generic_macros.mar,1.6,1.7

From: Daniel P. <dp...@us...> - 2002-01-28 03:40:32

Update of /cvsroot/l4alpha/L4Alpha/pal/macros
In directory usw-pr-cvs1:/tmp/cvs-serv1124/pal/macros

Modified Files:
	generic_macros.mar 
Log Message:
check_cpu_exists macro fix for uniprocessor.

added profiling macros. These require more kernel support to be used.



Index: generic_macros.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/macros/generic_macros.mar,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** generic_macros.mar	2001/04/13 05:45:52	1.6
--- generic_macros.mar	2002/01/28 03:40:25	1.7
***************
*** 497,501 ****
  L1:		
  .iff
! 	and	cpuid, #1, result	; only CPU0 exists (bad assumption that it is zero?)
  .endc
  .endm			
--- 497,501 ----
  L1:		
  .iff
! 	cmoveq	cpuid, #1, result	; only CPU0 exists (bad assumption that it is zero?)
  .endc
  .endm			
***************
*** 594,595 ****
--- 594,643 ----
  .endm
  
+ .iif ndf profiling_enabled, profiling_enabled = 1
+ PROFILE_OFFSET = ^x40
+ 
+ ;+
+ ; profile
+ ; this macro will store the cycle counter value in memory pointed to by 0x400<<16
+ ; with a code int_code.
+ ;-
+ 
+ .macro profile_end int_code, tmpa, tmpb, tmpc ?L1
+ .if df profiling_enabled
+        rpcc  tmpc
+        ldq_p tmpa, PROFILE_OFFSET(zero) ; pointer offset
+        beq   tmpa, L1		; if pointer not set dont profile.
+        addq  tmpa, #16, tmpb	; increment.
+        stq_p tmpb, PROFILE_OFFSET(zero) ; update pointer offset
+        lda   tmpb, int_code(zero) ; load code - syscall etc...
+        stq_p tmpb, 0(tmpa)
+        stq_p tmpc, 8(tmpa)	; store cycle count
+ L1:
+ .endc
+ .endm
+        
+ .macro profile_start int_code, tmpa, tmpb ?L1
+ .if df profiling_enabled
+        ldq_p tmpa, PROFILE_OFFSET(zero) ; pointer offset
+        beq   tmpa, L1		; if pointer not set dont profile.
+        addq  tmpa, #16, tmpb	; increment.
+        stq_p tmpb, PROFILE_OFFSET(zero) ; update pointer offset
+        lda   tmpb, int_code(zero) ; load code - syscall etc...
+        stq_p tmpb, 0(tmpa)
+        nop
+        nop
+ 	nop
+ 	nop
+ 	nop
+ 	nop
+ 
+        rpcc tmpb	
+ 	nop
+ 	nop
+ 	nop
+ 	nop
+        stq_p tmpb, 8(tmpa)	; store cycle count
+ L1:
+ .endc
+ .endm
+

[L4alpha-cvscommit] CVS: L4Alpha/pal ipi.mar,1.3,1.4 ipc.mar,1.19,1.20 thread.mar,1.11,1.12

From: Daniel P. <dp...@us...> - 2002-01-22 12:48:29

Update of /cvsroot/l4alpha/L4Alpha/pal
In directory usw-pr-cvs1:/tmp/cvs-serv29742/pal

Modified Files:
	ipi.mar ipc.mar thread.mar 
Log Message:
SMP kernel updates and fixes.
Corrected stack unrolling for ipc send - a result of recent ex_reg changes.
Fixed bug in SMP task_new to correctly pass the right tcb of new task. This hasn't worked since 1.5.2.5 from what I can tell!


Index: ipi.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/ipi.mar,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** ipi.mar	2001/04/13 05:45:51	1.3
--- ipi.mar	2002/01/22 12:48:23	1.4
***************
*** 60,64 ****
  	beq	pp3, ipi_exit
  
! ;	NewCom2SerialPutChar ^x58, pp2, pp4 ; X
  	
  	;; pp2 is the transaction type.
--- 60,64 ----
  	beq	pp3, ipi_exit
  
! ;	NewCom2SerialPutChar ^x58, pp1, pp4 ; X
  	
  	;; pp2 is the transaction type.
***************
*** 109,126 ****
  	free_slot pp3, pp1, pp2, pp6
  	
! 	tcb_ptr	pp0, pp1
  
! 	;; Normal checks.
! 	ldq_a	pp2, TCB_MYSELF(pp1)
! 	cmpeq	pp0, pp2, pp2
! ;	beq	pp2, ipi_message_loop
! 	beq	pp2, ipi_te_bugger
  	
- 	ldl_a	pp0, TCB_CPUID(pp1)
- 	ldl_p	pp2, PCPUB_CPUID(pp6)
- 	cmpeq	pp0, pp2, pp2
- ;	beq	pp0, ipi_message_loop; FIXME (sjw Sun Feb 11 21:01:10 2001 ) --- Should this be forwarded?  Don't think so ...
- 	beq	pp2, ipi_te_bugger
- 
  	mb
  	thread_fill_tcb_enqueue pp1, pp0, pp2, pp4, pp6
--- 109,116 ----
  	free_slot pp3, pp1, pp2, pp6
  	
! 	check_tid pp0, pp1, ipi_te_bugger, pp2 ; FIXME - should really forward it?
  
! 	check_cpuid pp1, pp0, ipi_te_bugger, pp2, pp6
  	
  	mb
  	thread_fill_tcb_enqueue pp1, pp0, pp2, pp4, pp6

Index: ipc.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/ipc.mar,v
retrieving revision 1.19
retrieving revision 1.20
diff -C2 -d -r1.19 -r1.20
*** ipc.mar	2002/01/17 04:39:04	1.19
--- ipc.mar	2002/01/22 12:48:23	1.20
***************
*** 1189,1193 ****
  
  
! 	push	p_pp1!p_a0!p_a1!p_a2!p_a3
  
  	bis	zero, #TFS_LOCKED_WAITING, pp7
--- 1189,1194 ----
  
  
! 	push	p_pp1
! 	push	p_a0!p_a1!p_a2!p_a3
  
  	bis	zero, #TFS_LOCKED_WAITING, pp7

Index: thread.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/thread.mar,v
retrieving revision 1.11
retrieving revision 1.12
diff -C2 -d -r1.11 -r1.12
*** thread.mar	2002/01/17 04:39:04	1.11
--- thread.mar	2002/01/22 12:48:23	1.12
***************
*** 1247,1256 ****
  	alloc_mailbox	t1, t3, AT, t2, t5
  
! 	;; Not really needed ...
! 	tcb	AT
! 	ldq_a	AT, TCB_MYSELF(AT)
! 	stq_p	AT, MB_DATA2(t1)
! 
! 	ldq_a	v0, TCB_MYSELF(v0)
  	stq_p	t0, MB_DATA0(t1)
  
--- 1247,1251 ----
  	alloc_mailbox	t1, t3, AT, t2, t5
  
! 	ldq_a	t0, TCB_MYSELF(t0)
  	stq_p	t0, MB_DATA0(t1)

[L4alpha-cvscommit] CVS: L4Alpha/include/pal palcalls.h,1.3,1.4

From: Daniel P. <dp...@us...> - 2002-01-22 06:44:25

Update of /cvsroot/l4alpha/L4Alpha/include/pal
In directory usw-pr-cvs1:/tmp/cvs-serv15935/include/pal

Modified Files:
	palcalls.h 
Log Message:
Minor cleaup for l4_migrate and l4_whoami functions
Added #define for syscall values.



Index: palcalls.h
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/include/pal/palcalls.h,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** palcalls.h	2001/04/05 08:23:40	1.3
--- palcalls.h	2002/01/22 06:44:19	1.4
***************
*** 49,52 ****
--- 49,55 ----
  #define L4_SYS_TIME		0x00B9		/* get system up time */
  
+ #define L4_WHOAMI		0x00AB
+ #define L4_MIGRATE		0x00AC
+ 
  #define UDBG_PRINT_DBG_CHAR    	0x00AF		/* GDB */
  #define UDBG_GET_DBG_CHAR      	0x00AE		/* GDB */

[L4alpha-cvscommit] CVS: L4Alpha/lib/l4 syscall.S,1.6,1.7

From: Daniel P. <dp...@us...> - 2002-01-22 06:44:25

Update of /cvsroot/l4alpha/L4Alpha/lib/l4
In directory usw-pr-cvs1:/tmp/cvs-serv15935/lib/l4

Modified Files:
	syscall.S 
Log Message:
Minor cleaup for l4_migrate and l4_whoami functions
Added #define for syscall values.



Index: syscall.S
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/lib/l4/syscall.S,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** syscall.S	2002/01/03 03:26:13	1.6
--- syscall.S	2002/01/22 06:44:19	1.7
***************
*** 435,439 ****
  l4_migrate:	
  	save
! 	pal	0xAC
  	load
  	ret	(ra)
--- 435,439 ----
  l4_migrate:	
  	save
! 	pal	L4_MIGRATE
  	load
  	ret	(ra)
***************
*** 441,445 ****
  l4_whoami:		
  l4_test_cpu:
! 	pal	0xAB
  	ret	(ra)
  	
--- 441,445 ----
  l4_whoami:		
  l4_test_cpu:
! 	pal	L4_WHOAMI
  	ret	(ra)

[L4alpha-cvscommit] CVS: L4Alpha/pal memory.mar,1.6,1.7

From: Daniel P. <dp...@us...> - 2002-01-18 09:22:16

Update of /cvsroot/l4alpha/L4Alpha/pal
In directory usw-pr-cvs1:/tmp/cvs-serv18320

Modified Files:
	memory.mar 
Log Message:
Fixed memory leak in mem_map_page when an explicit mapping is performed on a page already mapped.


Index: memory.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/memory.mar,v
retrieving revision 1.6
retrieving revision 1.7
diff -C2 -d -r1.6 -r1.7
*** memory.mar	2001/12/10 00:21:35	1.6
--- memory.mar	2002/01/18 09:22:10	1.7
***************
*** 499,506 ****
  	XENDIF
  
! 	; interrupts to be enabled when ready atomic changes.
! 	disable_int
! 	PVC_JSR mdb_add_mapping bsr=1
! 	bsr	ra, mdb_add_mapping
  	IFZ	v0
  		pop	p_ra
--- 499,509 ----
  	XENDIF
  
! 	clr v0
! 	IFZ t10
! 		; interrupts to be enabled when ready atomic changes.
! 		disable_int
! 		PVC_JSR mdb_add_mapping bsr=1
! 		bsr	ra, mdb_add_mapping
! 	ENDIF
  	IFZ	v0
  		pop	p_ra
***************
*** 660,663 ****
--- 663,667 ----
  ; 
  ;	t9 - target page table entry ptr
+ ;	t10 - ipte_translation_valid (1 == already present)
  ;
  ; SIDE EFFECTS
***************
*** 711,718 ****
  	; we should get the pointer and update the (new) permissions
  
! 	GET_16CONS AT, ^x3ff
! 	bic	t3, AT, t2
! 	br	zero, ipte_insert_empty		; overwrite old entry
  
  	; We don't bother flushing entry here, it can be done in TLB fault handler.
  
--- 715,729 ----
  	; we should get the pointer and update the (new) permissions
  
! ;	GET_16CONS AT, ^x3ff
! ;	bic	t3, AT, t2
  
+ ;	mov	t8, t9
+ ;	bis	t2, #13, t2			; set guard` length
+ ;	or	t2, a4, t2
+ ;	stq_p	t2, 0(t9)			; kpush new low part
+ ;	stq_p	a1, 8(t9)			; Store new high part	
+  	clr	a1
+ 	bis	zero, #1, t10
+ 	
  	; We don't bother flushing entry here, it can be done in TLB fault handler.
  
***************
*** 854,857 ****
--- 865,869 ----
  	stq_p	a1, 8(t9)			; Store new high part	
   	clr	a1
+ 	clr	t10
  	PVC_JSR mem_insert_pte bsr=1 dest=1
  	ret	zero, (ra)

[L4alpha-cvscommit] CVS: L4Alpha/pal ipc.mar,1.18,1.19 thread.mar,1.10,1.11

From: Daniel P. <dp...@us...> - 2002-01-17 04:39:09

Update of /cvsroot/l4alpha/L4Alpha/pal
In directory usw-pr-cvs1:/tmp/cvs-serv11910

Modified Files:
	ipc.mar thread.mar 
Log Message:
Some 21264 fixes to reflect ex_regs changes. Namely unwinding registers on the stack.
Tested using L4Alpha-apps/exregs which tests normal aborts and POLLING threads in both UP and SMP systems.


Index: ipc.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/ipc.mar,v
retrieving revision 1.18
retrieving revision 1.19
diff -C2 -d -r1.18 -r1.19
*** ipc.mar	2002/01/03 04:25:43	1.18
--- ipc.mar	2002/01/17 04:39:04	1.19
***************
*** 1005,1009 ****
  	NewCom2SerialPutChar ^x78,pp2,pp1 ; x
  	bis	zero, #IPC_NOTEXIST, v0
! 	debug
  	full_close_frame
  	
--- 1005,1009 ----
  	NewCom2SerialPutChar ^x78,pp2,pp1 ; x
  	bis	zero, #IPC_NOTEXIST, v0
! ;	debug
  	full_close_frame
  	
***************
*** 1061,1064 ****
--- 1061,1071 ----
         	lda	sp, <17 * 8>(sp)
  .iff
+ .if df ev6
+ 	kernel kernel_ipc_polling_unstack
+ ipc_polling_unstack_ev6:
+ 	pop	p_a0!p_a1!p_a2!p_a3
+ 	pop	p_pp1	
+ 	ret	zero, (ra)
+ .iff
         	;; This should be the same as ipc_send_eq unstacking...
  	pop	p_t0!p_t1!p_t2!p_t3!p_t4!p_t5!p_t6!p_t8!p_a4!p_a5!p_fp!p_v0
***************
*** 1067,1073 ****
  	ret	zero, (ra)
  .endc
! 	
  				
  ;;; ABORT fail routine from ex_reg/remote_abort (reason is on stack).
  	ALIGN_FETCH_BLOCK
  ipc_ret_fail:
--- 1074,1089 ----
  	ret	zero, (ra)
  .endc
! .endc
! 
! .if df ev6	
! 	mode_normal
! 	ALIGN_FETCH_BLOCK
! kernel_ipc_polling_unstack:
! 	pop	p_t0!p_t1!p_t2!p_t3!p_t4!p_t5!p_t6!p_t8!p_a4!p_a5!p_fp!p_v0
! 	return	ipc_polling_unstack_ev6
! .endc	
  				
  ;;; ABORT fail routine from ex_reg/remote_abort (reason is on stack).
+ 	mode_pal
  	ALIGN_FETCH_BLOCK
  ipc_ret_fail:
***************
*** 1092,1096 ****
  	
  	GET_16CONS	v0, IPC_S_CANCELLED
! 	enable_int	t0
  	full_close_frame
  	
--- 1108,1112 ----
  	
  	GET_16CONS	v0, IPC_S_CANCELLED
! 	enable_int	pp0
  	full_close_frame
  	
***************
*** 1763,1767 ****
  	; which should not have been scratched (in their registers at this stage)
  	; so we unwind the stack.
! 	lda	sp, <5*8>(sp)
  	bis	zero, #IPC_NOTEXIST, v0
  	return_frame
--- 1779,1783 ----
  	; which should not have been scratched (in their registers at this stage)
  	; so we unwind the stack.
! 	lda	sp, <5*8>(sp)		; pop	p_pp1!p_v0!p_t0!p_t1!p_t2
  	bis	zero, #IPC_NOTEXIST, v0
  	return_frame
***************
*** 1786,1789 ****
--- 1802,1806 ----
  	kernel	kernel_deceit_check
  
+ 	mode_normal
  	ALIGN_FETCH_BLOCK
  kernel_deceit_check:	
***************
*** 1821,1824 ****
--- 1838,1842 ----
  	return	ret_ipc_deceit_only
  	
+ 	mode_pal
  	ALIGN_FETCH_BLOCK	
  ret_ipc_deceit_only:

Index: thread.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/thread.mar,v
retrieving revision 1.10
retrieving revision 1.11
diff -C2 -d -r1.10 -r1.11
*** thread.mar	2002/01/02 05:47:48	1.10
--- thread.mar	2002/01/17 04:39:04	1.11
***************
*** 867,870 ****
--- 867,871 ----
  ; 
  ;-
+ 	mode_normal
  	ALIGN_FETCH_BLOCK
  remote_abort:	
***************
*** 896,900 ****
  	bic	t0, #TFS_POLLING, t1
  	IFZ	t1
! ;		kmsg	<"Removing polling thread"<CR><LF>>
  
  		;; Thread is polling, so remove it from the other threads send root
--- 897,901 ----
  	bic	t0, #TFS_POLLING, t1
  	IFZ	t1
! 		kmsg	<"Removing polling thread"<CR><LF>>
  
  		;; Thread is polling, so remove it from the other threads send root

[L4alpha-cvscommit] CVS: L4Alpha-apps/exreg head.S,NONE,1.1 main.c,1.1,1.2

From: Daniel P. <dp...@us...> - 2002-01-17 04:35:21

Update of /cvsroot/l4alpha/L4Alpha-apps/exreg
In directory usw-pr-cvs1:/tmp/cvs-serv10835

Modified Files:
	main.c 
Added Files:
	head.S 
Log Message:
ex_reg no longer updates pv when a destructive ex_reg (new ip etc) is called. This is to allow checkpointing to work correctly.
As all C functions and some compiled assembler need pv you can set it in an assembler stub as follows:
br pv, 1f
1: ldgp gp, 0(pv)

this is what head.S does for any function that is the entry point for ex_reg.



--- NEW FILE: head.S ---
/*
**	Copyright (c) 1995, Sebastian Schoenberg 
**	E-mail : ss...@ir...
**
**	University of Technology Dresden, Department of Computer Science
**	Inistute for Operating Systems, Databases and Computer Networks
**
**	$Id: head.S,v 1.1 2002/01/17 04:35:16 dpotts Exp $
**
*/


/* 
** This is base for Sigma 0
** It hopefully fits into one page
*/
	

#include <regdef.h>
#include <pal/palcalls.h>

	.text
	.align	3

        .globl  __other_cancel
	.globl	__other
	.globl	__other_send
	.globl	__other_smp
	
        .ent    __other_cancel

__other_cancel:	
	nop
	br	pv, 1f	
1:	ldgp    gp, 0(pv)		# Need a gp, for bootstrap
	lda     pv, other_cancel
	jsr     ra, (pv), other_cancel
	
2:	
	.long	UDBG_DEBUG
	br	zero, 2b

	.end	__other_cancel

	.align 3
        .ent    __other

__other:	
	nop
	br	pv, 1f	
1:	ldgp    gp, 0(pv)		# Need a gp, for bootstrap
	lda     pv, other
	jsr     ra, (pv), other
	
2:	
	.long	UDBG_DEBUG
	br	zero, 2b

	.end	__other

	.align 3	
        .ent    __other_send

__other_send:	
	nop
	br	pv, 1f	
1:	ldgp    gp, 0(pv)		# Need a gp, for bootstrap
	lda     pv, other_send
	jsr     ra, (pv), other_send
	
2:	
	.long	UDBG_DEBUG
	br	zero, 2b

	.end	__other_send

	.align 3	
        .ent    __other_smp

__other_smp:	
	nop
	br	pv, 1f	
1:	ldgp    gp, 0(pv)		# Need a gp, for bootstrap
	lda     pv, other_smp
	jsr     ra, (pv), other_smp
	
2:	
	.long	UDBG_DEBUG
	br	zero, 2b

	.end	__other_smp


Index: main.c
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha-apps/exreg/main.c,v
retrieving revision 1.1
retrieving revision 1.2
diff -C2 -d -r1.1 -r1.2
*** main.c	2001/03/27 12:10:36	1.1
--- main.c	2002/01/17 04:35:16	1.2
***************
*** 12,15 ****
--- 12,23 ----
   *
   * $Log$
+  * Revision 1.2  2002/01/17 04:35:16  dpotts
+  * ex_reg no longer updates pv when a destructive ex_reg (new ip etc) is called. This is to allow checkpointing to work correctly.
+  * As all C functions and some compiled assembler need pv you can set it in an assembler stub as follows:
+  * br pv, 1f
+  * 1: ldgp gp, 0(pv)
+  *
+  * this is what head.S does for any function that is the entry point for ex_reg.
+  *
   * Revision 1.1  2001/03/27 12:10:36  sjw
   * Added some existing code
***************
*** 41,44 ****
--- 49,58 ----
  void other_send(void);
  
+ /* Assembler stubs */
+ void __other_cancel(void);
+ void __other(void);
+ void __other_smp(void);
+ void __other_send(void);
+ 
  volatile int flags[4];
  
***************
*** 47,52 ****
  
  #define NTEST 100000
! //#define debug(a...) kprintf(##a)
! #define debug(a...) 
  
  extern int l4_test_cpu(void);
--- 61,66 ----
  
  #define NTEST 100000
! #define debug(a...) kprintf(##a)
! //#define debug(a...) 
  
  extern int l4_test_cpu(void);
***************
*** 100,104 ****
      debug("Exreg: UP test:\n");
      
!     thread_ids[0] = exreg(thread_ids[0], other, &(stack2[STACKSIZE - 1]));
  
      test(0, 1);
--- 114,118 ----
      debug("Exreg: UP test:\n");
      
!     thread_ids[0] = exreg(thread_ids[0], __other, &(stack2[STACKSIZE - 1]));
  
      test(0, 1);
***************
*** 106,110 ****
      debug("Exreg: UP: First ex-reg passed\n\r");
  
!     thread_ids[0] = exreg(thread_ids[0], other_cancel, &(stack2[STACKSIZE - 1]));
  
      test(0, 2);
--- 120,124 ----
      debug("Exreg: UP: First ex-reg passed\n\r");
  
!     thread_ids[0] = exreg(thread_ids[0], __other_cancel, &(stack2[STACKSIZE - 1]));
  
      test(0, 2);
***************
*** 112,116 ****
      debug("Exreg: UP: Second ex-reg passed\n\r");
  
!     dest_tid = thread_ids[0] = exreg(thread_ids[0], other, &(stack2[STACKSIZE - 1]));
  
      test(0, 2);
--- 126,130 ----
      debug("Exreg: UP: Second ex-reg passed\n\r");
  
!     dest_tid = thread_ids[0] = exreg(thread_ids[0], __other, &(stack2[STACKSIZE - 1]));
  
      test(0, 2);
***************
*** 118,126 ****
      debug("Exreg: UP: Third ex-reg passed\n\r");
  
!     thread_ids[1] = exreg(thread_ids[1], other_send, &(stack3[STACKSIZE - 1]));
  
      test(1, 2);
  
!     thread_ids[2] = exreg(thread_ids[2],  other_send, &(stack4[STACKSIZE - 1]));
  
      test(2, 3);
--- 132,140 ----
      debug("Exreg: UP: Third ex-reg passed\n\r");
  
!     thread_ids[1] = exreg(thread_ids[1], __other_send, &(stack3[STACKSIZE - 1]));
  
      test(1, 2);
  
!     thread_ids[2] = exreg(thread_ids[2],  __other_send, &(stack4[STACKSIZE - 1]));
  
      test(2, 3);
***************
*** 128,132 ****
      debug("Exreg: UP: Both senders started\n\r");
  
!     thread_ids[0] = exreg(thread_ids[0], other, &(stack2[STACKSIZE - 1]));
  
      test(0, 4);
--- 142,146 ----
      debug("Exreg: UP: Both senders started\n\r");
  
!     thread_ids[0] = exreg(thread_ids[0], __other, &(stack2[STACKSIZE - 1]));
  
      test(0, 4);
***************
*** 144,148 ****
      debug("Exreg: SMP test:\n");
      
!     thread_ids[0] = exreg(thread_ids[0], other_smp, &(stack2[STACKSIZE - 1]));
  
      test(0, 1);
--- 158,162 ----
      debug("Exreg: SMP test:\n");
      
!     thread_ids[0] = exreg(thread_ids[0], __other_smp, &(stack2[STACKSIZE - 1]));
  
      test(0, 1);
***************
*** 150,154 ****
      debug("Exreg: SMP: Migrate passed\n\r");
  
!     thread_ids[0] = exreg(thread_ids[0], other, &(stack2[STACKSIZE - 1]));
  
      test(0, 1);
--- 164,168 ----
      debug("Exreg: SMP: Migrate passed\n\r");
  
!     thread_ids[0] = exreg(thread_ids[0], __other, &(stack2[STACKSIZE - 1]));
  
      test(0, 1);
***************
*** 156,160 ****
      debug("Exreg: SMP: First ex-reg passed\n\r");
      
!     thread_ids[0] = exreg(thread_ids[0], other_cancel, &(stack2[STACKSIZE - 1]));
  
      test(0, 2);
--- 170,174 ----
      debug("Exreg: SMP: First ex-reg passed\n\r");
      
!     thread_ids[0] = exreg(thread_ids[0], __other_cancel, &(stack2[STACKSIZE - 1]));
  
      test(0, 2);
***************
*** 162,166 ****
      debug("Exreg: SMP: Second ex-reg passed\n\r");
  
!     dest_tid = thread_ids[0] = exreg(thread_ids[0], other, &(stack2[STACKSIZE - 1]));
  
      test(0, 2);
--- 176,180 ----
      debug("Exreg: SMP: Second ex-reg passed\n\r");
  
!     dest_tid = thread_ids[0] = exreg(thread_ids[0], __other, &(stack2[STACKSIZE - 1]));
  
      test(0, 2);
***************
*** 168,176 ****
      debug("Exreg: SMP: Third ex-reg passed\n\r");
  
!     thread_ids[1] = exreg(thread_ids[1], other_send, &(stack3[STACKSIZE - 1]));
  
      test(1, 2);
  
!     thread_ids[2] = exreg(thread_ids[2],  other_send, &(stack4[STACKSIZE - 1]));
  
      test(2, 3);
--- 182,190 ----
      debug("Exreg: SMP: Third ex-reg passed\n\r");
  
!     thread_ids[1] = exreg(thread_ids[1], __other_send, &(stack3[STACKSIZE - 1]));
  
      test(1, 2);
  
!     thread_ids[2] = exreg(thread_ids[2],  __other_send, &(stack4[STACKSIZE - 1]));
  
      test(2, 3);
***************
*** 178,182 ****
      debug("Exreg: SMP: Both senders started\n\r");
  
!     thread_ids[0] = exreg(thread_ids[0], other, &(stack2[STACKSIZE - 1]));
  
      test(0, 4);
--- 192,196 ----
      debug("Exreg: SMP: Both senders started\n\r");
  
!     thread_ids[0] = exreg(thread_ids[0], __other, &(stack2[STACKSIZE - 1]));
  
      test(0, 4);

[L4alpha-cvscommit] CVS: L4Alpha/user/sigma0 main.c,1.3,1.4

From: Daniel P. <dp...@us...> - 2002-01-14 09:30:05

Update of /cvsroot/l4alpha/L4Alpha/user/sigma0
In directory usw-pr-cvs1:/tmp/cvs-serv10487

Modified Files:
	main.c 
Log Message:
Cosmetic change.


Index: main.c
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/user/sigma0/main.c,v
retrieving revision 1.3
retrieving revision 1.4
diff -C2 -d -r1.3 -r1.4
*** main.c	2001/04/05 08:23:41	1.3
--- main.c	2002/01/14 09:30:00	1.4
***************
*** 116,120 ****
      } else {
  	if(sigma0_debug_level > 0)
! 	    print_string("Sigma0: Warning: No resource manager started\n");
      }
  
--- 116,120 ----
      } else {
  	if(sigma0_debug_level > 0)
! 	    print_string("Sigma0: Warning: No resource manager started\n\r");
      }

[L4alpha-cvscommit] CVS: L4Alpha/pal kernel.mar,1.8,1.9

From: Daniel P. <dp...@us...> - 2002-01-14 09:21:18

Update of /cvsroot/l4alpha/L4Alpha/pal
In directory usw-pr-cvs1:/tmp/cvs-serv8467

Modified Files:
	kernel.mar 
Log Message:
I mustn't be zeroing all kernel memory...
This fixes a crash I was getting on a dual up2000.


Index: kernel.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/kernel.mar,v
retrieving revision 1.8
retrieving revision 1.9
diff -C2 -d -r1.8 -r1.9
*** kernel.mar	2001/12/10 04:35:39	1.8
--- kernel.mar	2002/01/14 09:21:13	1.9
***************
*** 214,217 ****
--- 214,218 ----
  	stq	t1, <TCB_SEND_ROOT+8>(v0)
  
+ 	stq	zero, TCB_CHILD_TASK(v0)
  	
  	pal_addr t2, dispatcher_id

[L4alpha-cvscommit] CVS: L4Alpha Makefile,1.8,1.9

From: Daniel P. <dp...@us...> - 2002-01-04 03:29:24

Update of /cvsroot/l4alpha/L4Alpha
In directory usw-pr-cvs1:/tmp/cvs-serv13146

Modified Files:
	Makefile 
Log Message:
Minor cosmetic change courtesy of Goswin.


Index: Makefile
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/Makefile,v
retrieving revision 1.8
retrieving revision 1.9
diff -C2 -d -r1.8 -r1.9
*** Makefile	2001/11/12 04:07:26	1.8
--- Makefile	2002/01/04 03:29:19	1.9
***************
*** 152,156 ****
  %-bootpfile: %
  	cat $(L4BL) $(IMAGE) > $@
! 	@printf "\t\t---====---\nKernel Version: %s" "`sed -n 's/.*\(Build [^\"]*\)\".*/\1/p' < pal/version.mar`"
  	scp $@ $(BOOTPFILE)
  
--- 152,156 ----
  %-bootpfile: %
  	cat $(L4BL) $(IMAGE) > $@
! 	@printf "\t\t---====---\nKernel Version: %s\n" "`sed -n 's/.*\(Build [^\"]*\)\".*/\1/p' < pal/version.mar`"
  	scp $@ $(BOOTPFILE)

Re: [L4alpha-cvscommit] CVS: L4Alpha/pal/21164 ruffian_platform.mar,1.2,1.3

From: Goswin B. <gos...@st...> - 2002-01-03 11:44:55

Daniel Potts <dp...@us...> writes:

> ***************
> *** 950,954 ****
> --- 969,983 ----
>   	ALIGN_FETCH_BLOCK
>   interrupt_init:	
> + 	kmsg <"Enabling Ruffian interrupts"<CR><LF>>
>   
> + 	;; CLOCK_TICH_RATE = 1193180
> + 	;; HZ = 1024
> + 	;; LATCH = (CLOCK_TICK_RATE + 2/HZ) / HZ = 0x48D
> + .if ne 0	
> + 	OutPortByte ^x43, ^x34, t1, t2	; binary, mode 2, LSB/MSB, ch 0
> + 	OutPortByte ^x40, ^x8D, t1, t2  ; LSB - LATCH = 0x48D from linux
> + 	OutPortByte ^x40, ^x04, t1, t2  ; MSB
> + .endc
> + 		
>   	OutPortByte ^x43,^xb6, t1, t2
>   	OutPortByte ^x42,^x31, t1, t2
> ***************

Isn't HZ = 1200 except for rawhide?

But that should only give 20% error, not 2000%.

MfG
        Goswin

[L4alpha-cvscommit] CVS: L4Alpha/pal/21164 ruffian_platform.mar,1.2,1.3

From: Daniel P. <dp...@us...> - 2002-01-03 07:22:20

Update of /cvsroot/l4alpha/L4Alpha/pal/21164
In directory usw-pr-cvs1:/tmp/cvs-serv15091/pal/21164

Modified Files:
	ruffian_platform.mar 
Log Message:
I have (timer) interrupts on Ruffian working, but it seems to be 20x lower that it should be. No matter what values I change the counters to it doesn't seem to affect this number... perhaps they are being generated elsewhere.. 


Index: ruffian_platform.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21164/ruffian_platform.mar,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** ruffian_platform.mar	2001/12/10 04:35:39	1.2
--- ruffian_platform.mar	2002/01/03 07:22:14	1.3
***************
*** 287,291 ****
  	
  	OutPortByte RTCADD,^x0A,t0,p7
! 	OutPortByte RTCDAT,^x26,t0,p7; should be 0x25!!!!!!!
  
  	
--- 287,291 ----
  	
  	OutPortByte RTCADD,^x0A,t0,p7
! 	OutPortByte RTCDAT,^x23,t0,p7; should be 0x25!!!!!!!
  
  	
***************
*** 344,347 ****
--- 344,354 ----
  	NewCom2SerialPutChar ^x68,p5,p7 ;h	
  	
+ 	GET_16CONS p7, ^x878
+ 	GET_16CONS p5, ^x900
+ 	sll	p7, #28, p7
+ 	bis	p7, p5, p7
+ 	GET_32CONS p5, ^xdead
+ 	stq_p p5, 0(p7)
+ 
  	mtpr	zero, dtbCm
  	mtpr	zero, ips
***************
*** 610,614 ****
  
  	ALIGN_FETCH_BLOCK
! sys_interrupt_cont:		
  	;+
  	; Check for a system machine check interrupt or internally 
--- 617,621 ----
  
  	ALIGN_FETCH_BLOCK
! sys_interrupt_cont:
  	;+
  	; Check for a system machine check interrupt or internally 
***************
*** 649,652 ****
--- 656,661 ----
  	bne	p4, sys_int20_handler
  
+ 	NewCom2SerialPutChar ^x23,p5,p4 ; #
+ 
  	syshalt ^x2222
  
***************
*** 710,718 ****
  	ALIGN_FETCH_BLOCK
  sys_int22_handler:
- 	;;  FIXME
  	open_frame
  
  	tcb	p1
- 
  	ldq_a	p3, TCB_SCHED_ACCOUNT(p1)	
  
--- 719,725 ----
***************
*** 723,732 ****
  	InPortByte RTCDAT, p4, p7			; Read to clear interrupt.
  
! 	; miata/pyxis specific code
! 	
  	GET_16CONS p4, P_INT_BASE_B
  	sll	p4, #P_INT_BASE_S, p4
! 	ldq_p	p4, PO_INT_REQ(p4)
! 	
  	; end pyxis
  	
--- 730,749 ----
  	InPortByte RTCDAT, p4, p7			; Read to clear interrupt.
  
! 	; Ruffian specific ACK (overkill mode)
!         GET_16CONS p7, ^x80            ; (1 << 7)
  	GET_16CONS p4, P_INT_BASE_B
  	sll	p4, #P_INT_BASE_S, p4
! 	stq_p	p7, PO_INT_REQ(p4)
! 	mb
! 	ldq_p   p7, PO_INT_REQ(p4)
! 	OutPortByte PIC1_OCW2,^x20, p7, p4
! .if ne 0	
!         GET_16CONS p7, ^x80	; (1 << 7)  -- repeat, we probably don't need to.
! 	GET_16CONS p4, P_INT_BASE_B
! 	sll	p4, #P_INT_BASE_S, p4
! 	stq_p	p7, PO_INT_REQ(p4)
! 	mb
! 	ldq_p   p4, PO_INT_REQ(p4)	
! .endc	
  	; end pyxis
  	
***************
*** 854,858 ****
  	pyxis_IACK p0, p1
  	and	p0, #^xff, p0
! 	br	p0, sys_int22_handler ;  redirect to timer interrupt
  
  	
--- 871,877 ----
  	pyxis_IACK p0, p1
  	and	p0, #^xff, p0
! 	beq	p0, sys_int22_handler 		;  redirect to timer interrupt
! 
! 	NewCom2SerialPutChar ^x22,p0,p1 ; " 
  
  	
***************
*** 950,954 ****
--- 969,983 ----
  	ALIGN_FETCH_BLOCK
  interrupt_init:	
+ 	kmsg <"Enabling Ruffian interrupts"<CR><LF>>
  
+ 	;; CLOCK_TICH_RATE = 1193180
+ 	;; HZ = 1024
+ 	;; LATCH = (CLOCK_TICK_RATE + 2/HZ) / HZ = 0x48D
+ .if ne 0	
+ 	OutPortByte ^x43, ^x34, t1, t2	; binary, mode 2, LSB/MSB, ch 0
+ 	OutPortByte ^x40, ^x8D, t1, t2  ; LSB - LATCH = 0x48D from linux
+ 	OutPortByte ^x40, ^x04, t1, t2  ; MSB
+ .endc
+ 		
  	OutPortByte ^x43,^xb6, t1, t2
  	OutPortByte ^x42,^x31, t1, t2
***************
*** 968,972 ****
  	stq_p	zero, PO_INT_MASK(t0)	; set MASK
  	mb
! 	subq	zero, #1, t1		; set REQ (correct??)
  	stq_p	t1, PO_INT_REQ(t0)
  	mb
--- 997,1001 ----
  	stq_p	zero, PO_INT_MASK(t0)	; set MASK
  	mb
! 	subq	zero, #1, t1		; clear all interrupts.
  	stq_p	t1, PO_INT_REQ(t0)
  	mb
***************
*** 1010,1014 ****
--- 1039,1047 ----
  
  	GET_32CONS t4, ^xffbf
+ ;	subq	   zero, #1, t4	; a
  
+ 	GET_16CONS  t0, P_INT_BASE_B
+ 	sll	t0, #P_INT_BASE_S, t0
+ 
  	stq_p	t4, PO_INT_MASK(t0)
  	mb
***************
*** 1020,1024 ****
  	OutPortByte PIC1_OCW1, ^xfa, t1, t2	; enable 2
  	
! 	PVC_JSR init_interrupts, bsr=1, dest=1
  	ret	zero, (ra)
  
--- 1053,1084 ----
  	OutPortByte PIC1_OCW1, ^xfa, t1, t2	; enable 2
  	
! 	; extra stuff
! 
! ;+
! ; Initialize the real-time clock (RTC)
! ;
! ; Index into RTC Control Register A to set periodic interrupt rate
! ; to 488.281
! ;
! 
! 	
! 	OutPortByte RTCADD,^x0A,t1,t2
! 	OutPortByte RTCDAT,^x25,t1,t2 ; should be 25??
! 
! ;+
! ; Index into RTC Control Register B and then enable periodic
! ; interrupts.
! ;
! 
! 	OutPortByte RTCADD,^x0B,t0,p7
! 	InPortByte RTCDAT,p5,p7
! 	GET_16CONS t0, ^x40, zero		; Periodic interrupt bit
! 	bis	p5, t0, p5			; Merge it in
! 
! 	OutPortByte RTCADD,^x0B,t0,p7
! 	OutPortByteReg RTCDAT,p5,t0,p7
! 	
! 
! 	PVC_JSR interrupt_init, bsr=1, dest=1
  	ret	zero, (ra)

[L4alpha-cvscommit] CVS: L4Alpha/pal ipc.mar,1.17,1.18

From: Daniel P. <dp...@us...> - 2002-01-03 04:25:48

Update of /cvsroot/l4alpha/L4Alpha/pal
In directory usw-pr-cvs1:/tmp/cvs-serv17351/pal

Modified Files:
	ipc.mar 
Log Message:
It really hasn't been my week:

Bad Dan. I won't register trash every again.


Index: ipc.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/ipc.mar,v
retrieving revision 1.17
retrieving revision 1.18
diff -C2 -d -r1.17 -r1.18
*** ipc.mar	2002/01/03 04:17:21	1.17
--- ipc.mar	2002/01/03 04:25:43	1.18
***************
*** 1026,1032 ****
  
  		;; Update list state.
! 		ldl	t0, TCB_LIST_STATE(t12)
! 		bic	t0, #LLS_POLLING_QUEUE, t0
! 		stl	t0, TCB_LIST_STATE(t12)	
  
  		; now we unwind the stack
--- 1026,1032 ----
  
  		;; Update list state.
! 		ldl	AT, TCB_LIST_STATE(p0)
! 		bic	AT, #LLS_POLLING_QUEUE, AT
! 		stl	AT, TCB_LIST_STATE(p0)	
  
  		; now we unwind the stack

Flat | Threaded

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