[L4alpha-cvscommit] CVS: L4Alpha/pal/21164 ruffian_platform.mar,1.2,1.3

[Daniel P. <dp...@us...>]

Update of /cvsroot/l4alpha/L4Alpha/pal/21164
In directory usw-pr-cvs1:/tmp/cvs-serv15091/pal/21164

Modified Files:
	ruffian_platform.mar 
Log Message:
I have (timer) interrupts on Ruffian working, but it seems to be 20x lower that it should be. No matter what values I change the counters to it doesn't seem to affect this number... perhaps they are being generated elsewhere.. 


Index: ruffian_platform.mar
===================================================================
RCS file: /cvsroot/l4alpha/L4Alpha/pal/21164/ruffian_platform.mar,v
retrieving revision 1.2
retrieving revision 1.3
diff -C2 -d -r1.2 -r1.3
*** ruffian_platform.mar	2001/12/10 04:35:39	1.2
--- ruffian_platform.mar	2002/01/03 07:22:14	1.3
***************
*** 287,291 ****
  	
  	OutPortByte RTCADD,^x0A,t0,p7
! 	OutPortByte RTCDAT,^x26,t0,p7; should be 0x25!!!!!!!
  
  	
--- 287,291 ----
  	
  	OutPortByte RTCADD,^x0A,t0,p7
! 	OutPortByte RTCDAT,^x23,t0,p7; should be 0x25!!!!!!!
  
  	
***************
*** 344,347 ****
--- 344,354 ----
  	NewCom2SerialPutChar ^x68,p5,p7 ;h	
  	
+ 	GET_16CONS p7, ^x878
+ 	GET_16CONS p5, ^x900
+ 	sll	p7, #28, p7
+ 	bis	p7, p5, p7
+ 	GET_32CONS p5, ^xdead
+ 	stq_p p5, 0(p7)
+ 
  	mtpr	zero, dtbCm
  	mtpr	zero, ips
***************
*** 610,614 ****
  
  	ALIGN_FETCH_BLOCK
! sys_interrupt_cont:		
  	;+
  	; Check for a system machine check interrupt or internally 
--- 617,621 ----
  
  	ALIGN_FETCH_BLOCK
! sys_interrupt_cont:
  	;+
  	; Check for a system machine check interrupt or internally 
***************
*** 649,652 ****
--- 656,661 ----
  	bne	p4, sys_int20_handler
  
+ 	NewCom2SerialPutChar ^x23,p5,p4 ; #
+ 
  	syshalt ^x2222
  
***************
*** 710,718 ****
  	ALIGN_FETCH_BLOCK
  sys_int22_handler:
- 	;;  FIXME
  	open_frame
  
  	tcb	p1
- 
  	ldq_a	p3, TCB_SCHED_ACCOUNT(p1)	
  
--- 719,725 ----
***************
*** 723,732 ****
  	InPortByte RTCDAT, p4, p7			; Read to clear interrupt.
  
! 	; miata/pyxis specific code
! 	
  	GET_16CONS p4, P_INT_BASE_B
  	sll	p4, #P_INT_BASE_S, p4
! 	ldq_p	p4, PO_INT_REQ(p4)
! 	
  	; end pyxis
  	
--- 730,749 ----
  	InPortByte RTCDAT, p4, p7			; Read to clear interrupt.
  
! 	; Ruffian specific ACK (overkill mode)
!         GET_16CONS p7, ^x80            ; (1 << 7)
  	GET_16CONS p4, P_INT_BASE_B
  	sll	p4, #P_INT_BASE_S, p4
! 	stq_p	p7, PO_INT_REQ(p4)
! 	mb
! 	ldq_p   p7, PO_INT_REQ(p4)
! 	OutPortByte PIC1_OCW2,^x20, p7, p4
! .if ne 0	
!         GET_16CONS p7, ^x80	; (1 << 7)  -- repeat, we probably don't need to.
! 	GET_16CONS p4, P_INT_BASE_B
! 	sll	p4, #P_INT_BASE_S, p4
! 	stq_p	p7, PO_INT_REQ(p4)
! 	mb
! 	ldq_p   p4, PO_INT_REQ(p4)	
! .endc	
  	; end pyxis
  	
***************
*** 854,858 ****
  	pyxis_IACK p0, p1
  	and	p0, #^xff, p0
! 	br	p0, sys_int22_handler ;  redirect to timer interrupt
  
  	
--- 871,877 ----
  	pyxis_IACK p0, p1
  	and	p0, #^xff, p0
! 	beq	p0, sys_int22_handler 		;  redirect to timer interrupt
! 
! 	NewCom2SerialPutChar ^x22,p0,p1 ; " 
  
  	
***************
*** 950,954 ****
--- 969,983 ----
  	ALIGN_FETCH_BLOCK
  interrupt_init:	
+ 	kmsg <"Enabling Ruffian interrupts"<CR><LF>>
  
+ 	;; CLOCK_TICH_RATE = 1193180
+ 	;; HZ = 1024
+ 	;; LATCH = (CLOCK_TICK_RATE + 2/HZ) / HZ = 0x48D
+ .if ne 0	
+ 	OutPortByte ^x43, ^x34, t1, t2	; binary, mode 2, LSB/MSB, ch 0
+ 	OutPortByte ^x40, ^x8D, t1, t2  ; LSB - LATCH = 0x48D from linux
+ 	OutPortByte ^x40, ^x04, t1, t2  ; MSB
+ .endc
+ 		
  	OutPortByte ^x43,^xb6, t1, t2
  	OutPortByte ^x42,^x31, t1, t2
***************
*** 968,972 ****
  	stq_p	zero, PO_INT_MASK(t0)	; set MASK
  	mb
! 	subq	zero, #1, t1		; set REQ (correct??)
  	stq_p	t1, PO_INT_REQ(t0)
  	mb
--- 997,1001 ----
  	stq_p	zero, PO_INT_MASK(t0)	; set MASK
  	mb
! 	subq	zero, #1, t1		; clear all interrupts.
  	stq_p	t1, PO_INT_REQ(t0)
  	mb
***************
*** 1010,1014 ****
--- 1039,1047 ----
  
  	GET_32CONS t4, ^xffbf
+ ;	subq	   zero, #1, t4	; a
  
+ 	GET_16CONS  t0, P_INT_BASE_B
+ 	sll	t0, #P_INT_BASE_S, t0
+ 
  	stq_p	t4, PO_INT_MASK(t0)
  	mb
***************
*** 1020,1024 ****
  	OutPortByte PIC1_OCW1, ^xfa, t1, t2	; enable 2
  	
! 	PVC_JSR init_interrupts, bsr=1, dest=1
  	ret	zero, (ra)
  
--- 1053,1084 ----
  	OutPortByte PIC1_OCW1, ^xfa, t1, t2	; enable 2
  	
! 	; extra stuff
! 
! ;+
! ; Initialize the real-time clock (RTC)
! ;
! ; Index into RTC Control Register A to set periodic interrupt rate
! ; to 488.281
! ;
! 
! 	
! 	OutPortByte RTCADD,^x0A,t1,t2
! 	OutPortByte RTCDAT,^x25,t1,t2 ; should be 25??
! 
! ;+
! ; Index into RTC Control Register B and then enable periodic
! ; interrupts.
! ;
! 
! 	OutPortByte RTCADD,^x0B,t0,p7
! 	InPortByte RTCDAT,p5,p7
! 	GET_16CONS t0, ^x40, zero		; Periodic interrupt bit
! 	bis	p5, t0, p5			; Merge it in
! 
! 	OutPortByte RTCADD,^x0B,t0,p7
! 	OutPortByteReg RTCDAT,p5,t0,p7
! 	
! 
! 	PVC_JSR interrupt_init, bsr=1, dest=1
  	ret	zero, (ra)