[L4alpha-cvscommit] CVS: L4Alpha/pal/macros generic_macros.mar,1.6,1.7
Status: Beta
Brought to you by:
dpotts
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From: Daniel P. <dp...@us...> - 2002-01-28 03:40:32
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Update of /cvsroot/l4alpha/L4Alpha/pal/macros In directory usw-pr-cvs1:/tmp/cvs-serv1124/pal/macros Modified Files: generic_macros.mar Log Message: check_cpu_exists macro fix for uniprocessor. added profiling macros. These require more kernel support to be used. Index: generic_macros.mar =================================================================== RCS file: /cvsroot/l4alpha/L4Alpha/pal/macros/generic_macros.mar,v retrieving revision 1.6 retrieving revision 1.7 diff -C2 -d -r1.6 -r1.7 *** generic_macros.mar 2001/04/13 05:45:52 1.6 --- generic_macros.mar 2002/01/28 03:40:25 1.7 *************** *** 497,501 **** L1: .iff ! and cpuid, #1, result ; only CPU0 exists (bad assumption that it is zero?) .endc .endm --- 497,501 ---- L1: .iff ! cmoveq cpuid, #1, result ; only CPU0 exists (bad assumption that it is zero?) .endc .endm *************** *** 594,595 **** --- 594,643 ---- .endm + .iif ndf profiling_enabled, profiling_enabled = 1 + PROFILE_OFFSET = ^x40 + + ;+ + ; profile + ; this macro will store the cycle counter value in memory pointed to by 0x400<<16 + ; with a code int_code. + ;- + + .macro profile_end int_code, tmpa, tmpb, tmpc ?L1 + .if df profiling_enabled + rpcc tmpc + ldq_p tmpa, PROFILE_OFFSET(zero) ; pointer offset + beq tmpa, L1 ; if pointer not set dont profile. + addq tmpa, #16, tmpb ; increment. + stq_p tmpb, PROFILE_OFFSET(zero) ; update pointer offset + lda tmpb, int_code(zero) ; load code - syscall etc... + stq_p tmpb, 0(tmpa) + stq_p tmpc, 8(tmpa) ; store cycle count + L1: + .endc + .endm + + .macro profile_start int_code, tmpa, tmpb ?L1 + .if df profiling_enabled + ldq_p tmpa, PROFILE_OFFSET(zero) ; pointer offset + beq tmpa, L1 ; if pointer not set dont profile. + addq tmpa, #16, tmpb ; increment. + stq_p tmpb, PROFILE_OFFSET(zero) ; update pointer offset + lda tmpb, int_code(zero) ; load code - syscall etc... + stq_p tmpb, 0(tmpa) + nop + nop + nop + nop + nop + nop + + rpcc tmpb + nop + nop + nop + nop + stq_p tmpb, 8(tmpa) ; store cycle count + L1: + .endc + .endm + |