armadeus-commitlog — Armadeus GIT commit logs

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-316-g6783f97

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- Log -----------------------------------------------------------------
commit 6783f97581a28c6e5bdb2efb9b828cba54e2ad5e
Author: Philippe Reynes <tr...@ya...>
Date:   Wed May 23 01:18:56 2012 +0200

    [UBOOT] apf27: refactoring to be aligned with U-Boot 2011.12 coding conventions

-----------------------------------------------------------------------

Summary of changes:
 ...dule-and-I-O-Multiplexer-constant-for-mx2.patch |  295 +++++--------
 ...-Add-support-for-the-armadeus-apf27-board.patch |  449 +++++++++++---------
 .../u-boot/2011.12/340-apf27-misc-commands.patch   |   63 ++-
 3 files changed, 396 insertions(+), 411 deletions(-)

diff --git a/patches/u-boot/2011.12/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch b/patches/u-boot/2011.12/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
index c60fcba..8e80e02 100644
--- a/patches/u-boot/2011.12/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
+++ b/patches/u-boot/2011.12/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
@@ -1,134 +1,67 @@
-From c454b2c2ed3a4be1a0809c0f0fa49f46559e1fa6 Mon Sep 17 00:00:00 2001
-From: Philippe Reynes <tr...@ya...>
-Date: Sun, 25 Sep 2011 11:22:00 +0200
-Subject: [PATCH 1/6] Add GPIO Module and I/O Multiplexer constant for mx27
+Add WEIM, NFC SYSTEM_CTLconstants to the mx27 CPU
 
 Signed-off-by: Philippe Reynes <tr...@ya...>
 ---
- arch/arm/include/asm/arch-mx27/imx-regs.h |  216 +++++++++++++++++++++++++++++
- 1 files changed, 216 insertions(+), 0 deletions(-)
+ arch/arm/cpu/arm926ejs/mx27/asm-offsets.c |   28 +++++++++++
+ arch/arm/include/asm/arch-mx27/imx-regs.h |    9 ++++
+ arch/arm/include/asm/arch-mx27/mxc_nand.h |   73 +++++++++++++++++++++++++++++
+ 3 files changed, 110 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/include/asm/arch-mx27/mxc_nand.h
 
+diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
+index f3a8d7b..7dad00f 100644
+--- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
++++ b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
+@@ -34,6 +34,7 @@ int main(void)
+ 	DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
+ 	DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
+ 	DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
++	DEFINE(CCSR, IMX_PLL_BASE + offsetof(struct pll_regs, ccsr));
+ 
+ 	DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
+ 	DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
+@@ -41,5 +42,32 @@ int main(void)
+ 	DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
+ 	DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
+ 
++	DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, gpcr));
++	DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, fmcr));
++	DEFINE(DSCR2, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr2));
++	DEFINE(DSCR3, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr3));
++	DEFINE(DSCR7, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr7));
++	DEFINE(DSCR10, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr10));
++
++	DEFINE(CS0U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0u));
++	DEFINE(CS0L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0l));
++	DEFINE(CS0A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0a));
++	DEFINE(CS1U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1u));
++	DEFINE(CS1L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1l));
++	DEFINE(CS1A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1a));
++	DEFINE(CS2U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2u));
++	DEFINE(CS2L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2l));
++	DEFINE(CS2A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2a));
++	DEFINE(CS3U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3u));
++	DEFINE(CS3L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3l));
++	DEFINE(CS3A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3a));
++	DEFINE(CS4U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4u));
++	DEFINE(CS4L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4l));
++	DEFINE(CS4A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4a));
++	DEFINE(CS5U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5u));
++	DEFINE(CS5L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5l));
++	DEFINE(CS5A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5a));
++	DEFINE(EIM,  IMX_WEIM_BASE + offsetof(struct weim_regs, eim));
++
+ 	return 0;
+ }
 diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
-index ced5b2a..f1c0ce7 100644
+index ced5b2a..4df67d6 100644
 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h
 +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
-@@ -522,4 +522,220 @@ struct fuse_bank0_regs {
+@@ -522,4 +522,13 @@ struct fuse_bank0_regs {
  #define IIM_ERR_SNSE	(1 << 2)
  #define IIM_ERR_PARITYE	(1 << 1)
  
-+/* IIM Control Registers */
-+#define IIM_BANK_AREA	IMX_IIM_BASE + 0x800
-+#define IIM_BANK_REG(x,y) (IIM_BANK_AREA + 0x400 * x + (y<<2))
-+
-+# ifdef __ASSEMBLY__
-+#  define __REG(x) (x)
-+#  define __REG16(x) (x)
-+#  define __REG2(x,y) ((x)+(y))
-+
 +/*
-+ *  GPIO Module and I/O Multiplexer
-+ */
-+#define PORTA 0
-+#define PORTB 1
-+#define PORTC 2
-+#define PORTD 3
-+#define PORTE 4
-+#define PORTF 5
-+
-+#define AIPI1_PSR0	__REG(IMX_AIPI1_BASE + 0x00)
-+#define AIPI1_PSR1	__REG(IMX_AIPI1_BASE + 0x04)
-+#define AIPI2_PSR0	__REG(IMX_AIPI2_BASE + 0x00)
-+#define AIPI2_PSR1	__REG(IMX_AIPI2_BASE + 0x04)
-+
-+/* System Control */
-+#define FMCR	__REG(IMX_SYSTEM_CTL_BASE + 0x14)
-+#define GPCR	__REG(IMX_SYSTEM_CTL_BASE + 0x18)
-+#define WBCR	__REG(IMX_SYSTEM_CTL_BASE + 0x1C)
-+#define DSCR1	__REG(IMX_SYSTEM_CTL_BASE + 0x20)
-+#define DSCR2	__REG(IMX_SYSTEM_CTL_BASE + 0x24)
-+#define DSCR3	__REG(IMX_SYSTEM_CTL_BASE + 0x28)
-+#define DSCR4	__REG(IMX_SYSTEM_CTL_BASE + 0x2C)
-+#define DSCR5	__REG(IMX_SYSTEM_CTL_BASE + 0x30)
-+#define DSCR6	__REG(IMX_SYSTEM_CTL_BASE + 0x34)
-+#define DSCR7	__REG(IMX_SYSTEM_CTL_BASE + 0x38)
-+#define DSCR8	__REG(IMX_SYSTEM_CTL_BASE + 0x3C)
-+#define DSCR9	__REG(IMX_SYSTEM_CTL_BASE + 0x40)
-+#define DSCR10	__REG(IMX_SYSTEM_CTL_BASE + 0x44)
-+#define DSCR11	__REG(IMX_SYSTEM_CTL_BASE + 0x48)
-+#define DSCR12	__REG(IMX_SYSTEM_CTL_BASE + 0x4C)
-+#define DSCR13	__REG(IMX_SYSTEM_CTL_BASE + 0x50)
-+#define PSCR	__REG(IMX_SYSTEM_CTL_BASE + 0x54)
-+#define PMCR	__REG(IMX_SYSTEM_CTL_BASE + 0x58)
-+#define DCVR0	__REG(IMX_SYSTEM_CTL_BASE + 0x60)
-+#define DCVR1	__REG(IMX_SYSTEM_CTL_BASE + 0x64)
-+#define DCVR2	__REG(IMX_SYSTEM_CTL_BASE + 0x68)
-+#define DCVR3	__REG(IMX_SYSTEM_CTL_BASE + 0x6C)
-+
-+/* Chip Select Registers */
-+#define CS0U __REG(IMX_WEIM_BASE + 0x00) /* Chip Select 0 Upper Register    */
-+#define CS0L __REG(IMX_WEIM_BASE + 0x04) /* Chip Select 0 Lower Register    */
-+#define CS0A __REG(IMX_WEIM_BASE + 0x08) /* Chip Select 0 Addition Register */
-+#define CS1U __REG(IMX_WEIM_BASE + 0x10) /* Chip Select 1 Upper Register    */
-+#define CS1L __REG(IMX_WEIM_BASE + 0x14) /* Chip Select 1 Lower Register    */
-+#define CS1A __REG(IMX_WEIM_BASE + 0x18) /* Chip Select 1 Addition Register */
-+#define CS2U __REG(IMX_WEIM_BASE + 0x20) /* Chip Select 2 Upper Register    */
-+#define CS2L __REG(IMX_WEIM_BASE + 0x24) /* Chip Select 2 Lower Register    */
-+#define CS2A __REG(IMX_WEIM_BASE + 0x28) /* Chip Select 2 Addition Register */
-+#define CS3U __REG(IMX_WEIM_BASE + 0x30) /* Chip Select 3 Upper Register    */
-+#define CS3L __REG(IMX_WEIM_BASE + 0x34) /* Chip Select 3 Lower Register    */
-+#define CS3A __REG(IMX_WEIM_BASE + 0x38) /* Chip Select 3 Addition Register */
-+#define CS4U __REG(IMX_WEIM_BASE + 0x40) /* Chip Select 4 Upper Register    */
-+#define CS4L __REG(IMX_WEIM_BASE + 0x44) /* Chip Select 4 Lower Register    */
-+#define CS4A __REG(IMX_WEIM_BASE + 0x48) /* Chip Select 4 Addition Register */
-+#define CS5U __REG(IMX_WEIM_BASE + 0x50) /* Chip Select 5 Upper Register    */
-+#define CS5L __REG(IMX_WEIM_BASE + 0x54) /* Chip Select 5 Lower Register    */
-+#define CS5A __REG(IMX_WEIM_BASE + 0x58) /* Chip Select 5 Addition Register */
-+#define EIM  __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register     */
-+
-+/* SDRAM Controller registers */
-+#define ESDCTL0 __REG(IMX_ESD_BASE + 0x00) /* Enhanced SDRAM Control Register 0       */
-+#define ESDCFG0 __REG(IMX_ESD_BASE + 0x04) /* Enhanced SDRAM Configuration Register 0 */
-+#define ESDCTL1 __REG(IMX_ESD_BASE + 0x08) /* Enhanced SDRAM Control Register 1       */
-+#define ESDCFG1 __REG(IMX_ESD_BASE + 0x0C) /* Enhanced SDRAM Configuration Register 1 */
-+#define ESDMISC __REG(IMX_ESD_BASE + 0x10) /* Enhanced SDRAM Miscellanious Register   */
-+
-+/* PLL registers */
-+#define CSCR		__REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register       */
-+#define MPCTL0		__REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0          */
-+#define MPCTL1		__REG(IMX_PLL_BASE + 0x08) /* MCU PLL Control Register 1          */
-+#define SPCTL0		__REG(IMX_PLL_BASE + 0x0c) /* System PLL Control Register 0       */
-+#define SPCTL1		__REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1       */
-+#define OSC26MCTL	__REG(IMX_PLL_BASE + 0x14) /* Oscillator 26M Register             */
-+#define PCDR0		__REG(IMX_PLL_BASE + 0x18) /* Peripheral Clock Divider Register 0 */
-+#define PCDR1		__REG(IMX_PLL_BASE + 0x1c) /* Peripheral Clock Divider Register 1 */
-+#define PCCR0		__REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Control Register 0 */
-+#define PCCR1		__REG(IMX_PLL_BASE + 0x24) /* Peripheral Clock Control Register 1 */
-+#define CCSR		__REG(IMX_PLL_BASE + 0x28) /* Clock Control Status Register       */
-+
-+#define DDIR(x)    __REG2(IMX_GPIO_BASE + 0x00, ((x) & 7) << 8)
-+#define OCR1(x)    __REG2(IMX_GPIO_BASE + 0x04, ((x) & 7) << 8)
-+#define OCR2(x)    __REG2(IMX_GPIO_BASE + 0x08, ((x) & 7) << 8)
-+#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 7) << 8)
-+#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 7) << 8)
-+#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 7) << 8)
-+#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 7) << 8)
-+#define DR(x)      __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 7) << 8)
-+#define GIUS(x)    __REG2(IMX_GPIO_BASE + 0x20, ((x) & 7) << 8)
-+#define SSR(x)     __REG2(IMX_GPIO_BASE + 0x24, ((x) & 7) << 8)
-+#define ICR1(x)    __REG2(IMX_GPIO_BASE + 0x28, ((x) & 7) << 8)
-+#define ICR2(x)    __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 7) << 8)
-+#define IMR(x)     __REG2(IMX_GPIO_BASE + 0x30, ((x) & 7) << 8)
-+#define ISR(x)     __REG2(IMX_GPIO_BASE + 0x34, ((x) & 7) << 8)
-+#define GPR(x)     __REG2(IMX_GPIO_BASE + 0x38, ((x) & 7) << 8)
-+#define SWR(x)     __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 7) << 8)
-+#define PUEN(x)    __REG2(IMX_GPIO_BASE + 0x40, ((x) & 7) << 8)
-+
-+ /* Macros to get byte and bit positions of ECC
-+ */
-+#define COLPOS(x)			((x) >> 4)
-+#define BITPOS(x)			((x)& 0xf)
-+
-+/**
 + * Memory areas of the NFC
 + */
 +#define IMX_NFC_BASE                    (0xD8000000)
@@ -137,6 +70,38 @@ index ced5b2a..f1c0ce7 100644
 +#define IMX_NFC_SPARE_AREA0             (0xD8000800)
 +#define IMX_NFC_REGS                    (0xD8000E00)
 +
+ #endif				/* _IMX_REGS_H */
+diff --git a/arch/arm/include/asm/arch-mx27/mxc_nand.h b/arch/arm/include/asm/arch-mx27/mxc_nand.h
+new file mode 100644
+index 0000000..99af18b
+--- /dev/null
++++ b/arch/arm/include/asm/arch-mx27/mxc_nand.h
+@@ -0,0 +1,73 @@
++/*
++ * (c) 2012 Philippe Reynes <tr...@ya...>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __MXC_NAND_H
++#define __MXC_NAND_H
++
 +/*
 + * NFC registers address offest
 + */
@@ -157,82 +122,34 @@ index ced5b2a..f1c0ce7 100644
 +#define NFC_OFFSET_CONFIG1             (0x1A) /* Nand Flash Operation Configuration 1 */
 +#define NFC_OFFSET_CONFIG2             (0x1C) /* Nand Flash Operation Configuration 2 */
 +
-+/*
-+ * NFC registers
-+ */
-+	/* Internal SRAM Size */
-+#define NFC_BUFSIZE             __REG16(IMX_NFC_REGS + NFC_OFFSET_BUFSIZE)
-+	/* NAND Flash Block Address for Lock Check */
-+#define NFC_BLCK_ADD_LOCK       __REG16(IMX_NFC_REGS + NFC_OFFSET_BLCK_ADD_LOCK)
-+	/* Buffer Number for Page Data Transfer To From Flash Memory */
-+#define NFC_BUF_ADDR            __REG16(IMX_NFC_REGS + NFC_OFFSET_BUF_ADDR)
-+	/* NAND Flash Address */
-+#define NFC_FLASH_ADDR          __REG16(IMX_NFC_REGS + NFC_OFFSET_FLASH_ADDR)
-+	/* NAND Flash Command */
-+#define NFC_FLASH_CMD           __REG16(IMX_NFC_REGS + NFC_OFFSET_FLASH_CMD)
-+	/* NFC Internal Buffer Lock Control */
-+#define NFC_CONFIG              __REG16(IMX_NFC_REGS + NFC_OFFSET_CONFIG)
-+	/* Controller Status/Result of Flash Operation */
-+#define NFC_ECC_STATUS_RESULT   __REG16(IMX_NFC_REGS + NFC_OFFSET_ECC_STATUS_RESULT)
-+	/* ECC Error Position of Main Area Data Error */
-+#define NFC_ECC_RSLT_MAIN_AREA  __REG16(IMX_NFC_REGS + NFC_OFFSET_ECC_RSLT_MAIN_AREA)
-+	/* ECC Error Position of Spare Area Data Error */
-+#define NFC_ECC_RSLT_SPARE_AREA __REG16(IMX_NFC_REGS + NFC_OFFSET_ECC_RSLT_SPARE_AREA)
-+	/* Nand Flash Write Protection */
-+#define NFC_WRPROT              __REG16(IMX_NFC_REGS + NFC_OFFSET_WRPROT)
-+	/* Start Address for Write Protection Unlock */
-+#define NFC_UNLOCKSTART_BLKADDR __REG16(IMX_NFC_REGS + NFC_OFFSET_UNLOCKSTART_BLKADDR)
-+	/* End Address for Write Protection Unlock */
-+#define NFC_UNLOCKEND_BLKADDR   __REG16(IMX_NFC_REGS + NFC_OFFSET_UNLOCKEND_BLKADDR)
-+	/* Current Nand Flash Write Protection Status */
-+#define NFC_WRPR_STAT           __REG16(IMX_NFC_REGS + NFC_OFFSET_WRPR_STAT)
-+	/* Nand Flash Operation Configuration 1 */
-+#define NFC_CONFIG1             __REG16(IMX_NFC_REGS + NFC_OFFSET_CONFIG1)
-+	/* Nand Flash Operation Configuration 2 */
-+#define NFC_CONFIG2             __REG16(IMX_NFC_REGS + NFC_OFFSET_CONFIG2)
-+
 +/* NFC_ECC_STATUS_RESULT Status Register Bit Fields */
-+#define NFC_ECC_STAT_ERM_SHFT 	(2)		    /* ERM shift */
-+#define NFC_ECC_STAT_ERS_MASK 	(0x03)		/* ERS mask  */
-+#define NFC_ECC_STAT_ERROR1 	(1<<0)		/* correctable error */
-+#define NFC_ECC_STAT_ERROR2 	(1<<1)		/* non correctable error */
++#define NFC_ECC_STAT_ERM_SHFT  (2)                 /* ERM shift */
++#define NFC_ECC_STAT_ERS_MASK  (0x03)          /* ERS mask  */
++#define NFC_ECC_STAT_ERROR1    (1<<0)          /* correctable error */
++#define NFC_ECC_STAT_ERROR2    (1<<1)          /* non correctable error */
 +
 +/* NFC_CONFIG Control Register Bit Fields */
-+#define NFC_CONFIG_UNLOCKED     (1<<1)		/* unlocked */
-+#define NFC_CONFIG_LOCKED       (1<<0)		/* locked */
-+/* NFC_WRPROT Control Register Bit Fields */
-+#define NFC_WRPROT_UNLOCKBLK    (4<<0)		/* unlock block according to given address range */
-+#define NFC_WRPROT_LOCKALL 	    (2<<0)		/* lock all */
-+#define NFC_WRPROT_LOCKTIGHT    (1<<0)		/* lock-tight locked blocks */
-+/* NFC_WRPR_STAT Status Register Bit Fields */
-+#define NFC_WRPR_US 	        (1<<2)		/* Unlocked status	*/
-+#define NFC_WRPR_LS 	        (1<<1)		/* Locked status */
-+#define NFC_WRPR_LTS 	        (1<<0)		/* Lock-tight Status */
++#define NFC_CONFIG_UNLOCKED     (1<<1)         /* unlocked */
++#define NFC_CONFIG_LOCKED       (1<<0)         /* locked */
++
 +/* NFC_CONFIG1 Control Register Bit Fields */
-+#define NFC_CONFIG1_CEn 	    (1<<7)		/* Flash force CE */
-+#define NFC_CONFIG1_RST 	    (1<<6)		/* Reset */
-+#define NFC_CONFIG1_BIG 	    (1<<5)		/* Big Endian Mode */
-+#define NFC_CONFIG1_INT_MSK     (1<<4)		/* Mask Interrupt Bit	*/
-+#define NFC_CONFIG1_ECC_EN 	    (1<<3)		/* ECC operation enable */
-+#define NFC_CONFIG1_SP_EN 	    (1<<2)		/* Flash spare enable */
-+/* NFC_CONFIG2 Control Register Bit Fields */
-+#define NFC_CONFIG2_INT	        (1<<15)		/* Interrupt */
-+#define NFC_CONFIG2_FDO_STATUS	(4<<3)		/* Flash status output */
-+#define NFC_CONFIG2_FDO_ID	    (2<<3)		/* Flash ID output */
-+#define NFC_CONFIG2_FDO_PAGE    (1<<3)		/* Flash data output */
-+#define NFC_CONFIG2_FDI         (1<<2)		/* Flash data input	*/
-+#define NFC_CONFIG2_FADD 	    (1<<1)		/* Flash address input */
-+#define NFC_CONFIG2_FCMD 	    (1<<0)		/* Flash command input */
++#define NFC_CONFIG1_CEn            (1<<7)              /* Flash force CE */
++#define NFC_CONFIG1_RST            (1<<6)              /* Reset */
++#define NFC_CONFIG1_BIG            (1<<5)              /* Big Endian Mode */
++#define NFC_CONFIG1_INT_MSK     (1<<4)         /* Mask Interrupt Bit   */
++#define NFC_CONFIG1_ECC_EN         (1<<3)              /* ECC operation enable */
++#define NFC_CONFIG1_SP_EN          (1<<2)              /* Flash spare enable */
 +
-+#define NAND_CMD_LOCK		0x2a
-+#define NAND_CMD_LOCK_TIGHT	0x2c
-+#define NAND_CMD_UNLOCK1	0x23
-+#define NAND_CMD_UNLOCK2	0x24
-+#define NAND_CMD_LOCK_STATUS	0x7a
++/* NFC_CONFIG2 Control Register Bit Fields */
++#define NFC_CONFIG2_INT                (1<<15)         /* Interrupt */
++#define NFC_CONFIG2_FDO_STATUS (4<<3)          /* Flash status output */
++#define NFC_CONFIG2_FDO_ID         (2<<3)              /* Flash ID output */
++#define NFC_CONFIG2_FDO_PAGE    (1<<3)         /* Flash data output */
++#define NFC_CONFIG2_FDI         (1<<2)         /* Flash data input     */
++#define NFC_CONFIG2_FADD           (1<<1)              /* Flash address input */
++#define NFC_CONFIG2_FCMD           (1<<0)              /* Flash command input */
 +
 +#endif
-+
- #endif				/* _IMX_REGS_H */
 -- 
 1.7.4.4
 
diff --git a/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch b/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
index b3e53eb..6a4bf28 100644
--- a/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
+++ b/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
@@ -1,26 +1,35 @@
-From fe25e4695b704742eee8ff6e0d01cf0c3413dbd3 Mon Sep 17 00:00:00 2001
-From: Philippe Reynes <tr...@ya...>
-Date: Sun, 25 Sep 2011 11:25:10 +0200
-Subject: [PATCH 2/6] Add support for the armadeus apf27 board
+Add support for the armadeus APF27 board
 
 Signed-off-by: Philippe Reynes <tr...@ya...>
 ---
- board/armadeus/apf27/Makefile        |   50 ++
- board/armadeus/apf27/apf27.c         |  200 +++++++
- board/armadeus/apf27/config.mk       |   13 +
- board/armadeus/apf27/lowlevel_init.S |  343 ++++++++++++
- board/armadeus/apf27/u-boot-nand.lds |   56 ++
- boards.cfg                           |    1 +
- 6 files changed, 1649 insertions(+), 0 deletions(-)
+ board/armadeus/apf27/Makefile            |   50 +++
+ board/armadeus/apf27/apf27.c             |  305 +++++++++++++++++
+ board/armadeus/apf27/config.mk           |   13 +
+ board/armadeus/apf27/fpga.c              |  269 +++++++++++++++
+ board/armadeus/apf27/fpga.h              |   39 +++
+ board/armadeus/apf27/lowlevel_init.S     |  277 +++++++++++++++
+ board/armadeus/apf27/u-boot-nand.lds     |   56 +++
+ boards.cfg                               |    1 +
+ nand_spl/board/armadeus/apf27/Makefile   |   77 +++++
+ nand_spl/board/armadeus/apf27/config.mk  |   43 +++
+ nand_spl/board/armadeus/apf27/start.S    |  552 ++++++++++++++++++++++++++++++
+ nand_spl/board/armadeus/apf27/u-boot.lds |   37 ++
+ 12 files changed, 1719 insertions(+), 0 deletions(-)
  create mode 100644 board/armadeus/apf27/Makefile
  create mode 100644 board/armadeus/apf27/apf27.c
  create mode 100644 board/armadeus/apf27/config.mk
+ create mode 100644 board/armadeus/apf27/fpga.c
+ create mode 100644 board/armadeus/apf27/fpga.h
  create mode 100644 board/armadeus/apf27/lowlevel_init.S
  create mode 100644 board/armadeus/apf27/u-boot-nand.lds
+ create mode 100644 nand_spl/board/armadeus/apf27/Makefile
+ create mode 100644 nand_spl/board/armadeus/apf27/config.mk
+ create mode 100644 nand_spl/board/armadeus/apf27/start.S
+ create mode 100644 nand_spl/board/armadeus/apf27/u-boot.lds
 
 diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile
 new file mode 100644
-index 0000000..2a0f7d8
+index 0000000..b67334c
 --- /dev/null
 +++ b/board/armadeus/apf27/Makefile
 @@ -0,0 +1,50 @@
@@ -76,10 +85,10 @@ index 0000000..2a0f7d8
 +#########################################################################
 diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
 new file mode 100644
-index 0000000..e08b7a2
+index 0000000..1f1bd42
 --- /dev/null
 +++ b/board/armadeus/apf27/apf27.c
-@@ -0,0 +1,202 @@
+@@ -0,0 +1,305 @@
 +/*
 + * Copyright (C) 2007 Sascha Hauer, Pengutronix
 + * Copyright (C) 2008,2009 Eric Jarrige <jo...@us...>
@@ -107,11 +116,113 @@ index 0000000..e08b7a2
 +#include <jffs2/jffs2.h>
 +#include <nand.h>
 +#include <netdev.h>
++#include <asm/io.h>
 +#include <asm/arch/imx-regs.h>
 +#include <asm/errno.h>
 +
 +DECLARE_GLOBAL_DATA_PTR;
 +
++static void apf27_gpio_init(void)
++{
++  	struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
++
++    /* PORT A */
++    writel(CONFIG_SYS_DR_A_VAL,    &regs->port[PORTA].dr);
++    writel(CONFIG_SYS_OCR1_A_VAL,  &regs->port[PORTA].ocr1);
++    writel(CONFIG_SYS_OCR2_A_VAL,  &regs->port[PORTA].ocr2);
++    writel(CONFIG_SYS_ICFA1_A_VAL, &regs->port[PORTA].iconfa1);
++    writel(CONFIG_SYS_ICFA2_A_VAL, &regs->port[PORTA].iconfa2);
++    writel(CONFIG_SYS_ICFB1_A_VAL, &regs->port[PORTA].iconfb1);
++    writel(CONFIG_SYS_ICFB2_A_VAL, &regs->port[PORTA].iconfb2);
++    writel(CONFIG_SYS_ICR1_A_VAL,  &regs->port[PORTA].icr1);
++    writel(CONFIG_SYS_ICR2_A_VAL,  &regs->port[PORTA].icr2);
++    writel(CONFIG_SYS_IMR_A_VAL,   &regs->port[PORTA].imr);
++    writel(CONFIG_SYS_DDIR_A_VAL,  &regs->port[PORTA].ddir);
++    writel(CONFIG_SYS_GPR_A_VAL,   &regs->port[PORTA].gpr);
++    writel(CONFIG_SYS_PUEN_A_VAL,  &regs->port[PORTA].puen);
++    writel(CONFIG_SYS_GIUS_A_VAL,  &regs->port[PORTA].gius);
++
++    /* PORT B */
++    writel(CONFIG_SYS_DR_B_VAL,    &regs->port[PORTB].dr);
++    writel(CONFIG_SYS_OCR1_B_VAL,  &regs->port[PORTB].ocr1);
++    writel(CONFIG_SYS_OCR2_B_VAL,  &regs->port[PORTB].ocr2);
++    writel(CONFIG_SYS_ICFA1_B_VAL, &regs->port[PORTB].iconfa1);
++    writel(CONFIG_SYS_ICFA2_B_VAL, &regs->port[PORTB].iconfa2);
++    writel(CONFIG_SYS_ICFB1_B_VAL, &regs->port[PORTB].iconfb1);
++    writel(CONFIG_SYS_ICFB2_B_VAL, &regs->port[PORTB].iconfb2);
++    writel(CONFIG_SYS_ICR1_B_VAL,  &regs->port[PORTB].icr1);
++    writel(CONFIG_SYS_ICR2_B_VAL,  &regs->port[PORTB].icr2);
++    writel(CONFIG_SYS_IMR_B_VAL,   &regs->port[PORTB].imr);
++    writel(CONFIG_SYS_DDIR_B_VAL,  &regs->port[PORTB].ddir);
++    writel(CONFIG_SYS_GPR_B_VAL,   &regs->port[PORTB].gpr);
++    writel(CONFIG_SYS_PUEN_B_VAL,  &regs->port[PORTB].puen);
++    writel(CONFIG_SYS_GIUS_B_VAL,  &regs->port[PORTB].gius);
++
++    /* PORT C */
++    writel(CONFIG_SYS_DR_C_VAL,    &regs->port[PORTC].dr);
++    writel(CONFIG_SYS_OCR1_C_VAL,  &regs->port[PORTC].ocr1);
++    writel(CONFIG_SYS_OCR2_C_VAL,  &regs->port[PORTC].ocr2);
++    writel(CONFIG_SYS_ICFA1_C_VAL, &regs->port[PORTC].iconfa1);
++    writel(CONFIG_SYS_ICFA2_C_VAL, &regs->port[PORTC].iconfa2);
++    writel(CONFIG_SYS_ICFB1_C_VAL, &regs->port[PORTC].iconfb1);
++    writel(CONFIG_SYS_ICFB2_C_VAL, &regs->port[PORTC].iconfb2);
++    writel(CONFIG_SYS_ICR1_C_VAL,  &regs->port[PORTC].icr1);
++    writel(CONFIG_SYS_ICR2_C_VAL,  &regs->port[PORTC].icr2);
++    writel(CONFIG_SYS_IMR_C_VAL,   &regs->port[PORTC].imr);
++    writel(CONFIG_SYS_DDIR_C_VAL,  &regs->port[PORTC].ddir);
++    writel(CONFIG_SYS_GPR_C_VAL,   &regs->port[PORTC].gpr);
++    writel(CONFIG_SYS_PUEN_C_VAL,  &regs->port[PORTC].puen);
++    writel(CONFIG_SYS_GIUS_C_VAL,  &regs->port[PORTC].gius);
++
++    /* PORT D */
++    writel(CONFIG_SYS_DR_D_VAL,    &regs->port[PORTD].dr);
++    writel(CONFIG_SYS_OCR1_D_VAL,  &regs->port[PORTD].ocr1);
++    writel(CONFIG_SYS_OCR2_D_VAL,  &regs->port[PORTD].ocr2);
++    writel(CONFIG_SYS_ICFA1_D_VAL, &regs->port[PORTD].iconfa1);
++    writel(CONFIG_SYS_ICFA2_D_VAL, &regs->port[PORTD].iconfa2);
++    writel(CONFIG_SYS_ICFB1_D_VAL, &regs->port[PORTD].iconfb1);
++    writel(CONFIG_SYS_ICFB2_D_VAL, &regs->port[PORTD].iconfb2);
++    writel(CONFIG_SYS_ICR1_D_VAL,  &regs->port[PORTD].icr1);
++    writel(CONFIG_SYS_ICR2_D_VAL,  &regs->port[PORTD].icr2);
++    writel(CONFIG_SYS_IMR_D_VAL,   &regs->port[PORTD].imr);
++    writel(CONFIG_SYS_DDIR_D_VAL,  &regs->port[PORTD].ddir);
++    writel(CONFIG_SYS_GPR_D_VAL,   &regs->port[PORTD].gpr);
++    writel(CONFIG_SYS_PUEN_D_VAL,  &regs->port[PORTD].puen);
++    writel(CONFIG_SYS_GIUS_D_VAL,  &regs->port[PORTD].gius);
++
++    /* PORT E */
++    writel(CONFIG_SYS_DR_E_VAL,    &regs->port[PORTE].dr);
++    writel(CONFIG_SYS_OCR1_E_VAL,  &regs->port[PORTE].ocr1);
++    writel(CONFIG_SYS_OCR2_E_VAL,  &regs->port[PORTE].ocr2);
++    writel(CONFIG_SYS_ICFA1_E_VAL, &regs->port[PORTE].iconfa1);
++    writel(CONFIG_SYS_ICFA2_E_VAL, &regs->port[PORTE].iconfa2);
++    writel(CONFIG_SYS_ICFB1_E_VAL, &regs->port[PORTE].iconfb1);
++    writel(CONFIG_SYS_ICFB2_E_VAL, &regs->port[PORTE].iconfb2);
++    writel(CONFIG_SYS_ICR1_E_VAL,  &regs->port[PORTE].icr1);
++    writel(CONFIG_SYS_ICR2_E_VAL,  &regs->port[PORTE].icr2);
++    writel(CONFIG_SYS_IMR_E_VAL,   &regs->port[PORTE].imr);
++    writel(CONFIG_SYS_DDIR_E_VAL,  &regs->port[PORTE].ddir);
++    writel(CONFIG_SYS_GPR_E_VAL,   &regs->port[PORTE].gpr);
++    writel(CONFIG_SYS_PUEN_E_VAL,  &regs->port[PORTE].puen);
++    writel(CONFIG_SYS_GIUS_E_VAL,  &regs->port[PORTE].gius);
++
++    /* PORT F */
++    writel(CONFIG_SYS_DR_F_VAL,    &regs->port[PORTF].dr);
++    writel(CONFIG_SYS_OCR1_F_VAL,  &regs->port[PORTF].ocr1);
++    writel(CONFIG_SYS_OCR2_F_VAL,  &regs->port[PORTF].ocr2);
++    writel(CONFIG_SYS_ICFA1_F_VAL, &regs->port[PORTF].iconfa1);
++    writel(CONFIG_SYS_ICFA2_F_VAL, &regs->port[PORTF].iconfa2);
++    writel(CONFIG_SYS_ICFB1_F_VAL, &regs->port[PORTF].iconfb1);
++    writel(CONFIG_SYS_ICFB2_F_VAL, &regs->port[PORTF].iconfb2);
++    writel(CONFIG_SYS_ICR1_F_VAL,  &regs->port[PORTF].icr1);
++    writel(CONFIG_SYS_ICR2_F_VAL,  &regs->port[PORTF].icr2);
++    writel(CONFIG_SYS_IMR_F_VAL,   &regs->port[PORTF].imr);
++    writel(CONFIG_SYS_DDIR_F_VAL,  &regs->port[PORTF].ddir);
++    writel(CONFIG_SYS_GPR_F_VAL,   &regs->port[PORTF].gpr);
++    writel(CONFIG_SYS_PUEN_F_VAL,  &regs->port[PORTF].puen);
++    writel(CONFIG_SYS_GIUS_F_VAL,  &regs->port[PORTF].gius);
++}
++
 +static int apf27_devices_init(void)
 +{
 +	int i;
@@ -156,6 +267,7 @@ index 0000000..e08b7a2
 +{
 +	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
 +
++	apf27_gpio_init();
 +	apf27_devices_init();
 +
 +	return 0;
@@ -301,10 +413,11 @@ index 0000000..3354ba0
 +TEXT_BASE = 0xAFF00000
 +endif
 +# CONFIG_NAND_U_BOOT = y
-Index: u-boot-2010.03/board/armadeus/apf27/fpga.c
-===================================================================
---- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/board/armadeus/apf27/fpga.c	2011-01-05 18:09:44.000000000 +0100
+diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c
+new file mode 100644
+index 0000000..1d2c168
+--- /dev/null
++++ b/board/armadeus/apf27/fpga.c
 @@ -0,0 +1,269 @@
 +/*
 + * (C) Copyright 2002-2008
@@ -575,10 +688,11 @@ Index: u-boot-2010.03/board/armadeus/apf27/fpga.c
 +}
 +
 +#endif /* CONFIG_FPGA */
-Index: u-boot-2010.03/board/armadeus/apf27/fpga.h
-===================================================================
---- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/board/armadeus/apf27/fpga.h	2011-01-05 18:09:44.000000000 +0100
+diff --git a/board/armadeus/apf27/fpga.h b/board/armadeus/apf27/fpga.h
+new file mode 100644
+index 0000000..ca569e0
+--- /dev/null
++++ b/board/armadeus/apf27/fpga.h
 @@ -0,0 +1,39 @@
 +/*
 + * (C) Copyright 2002-2008
@@ -621,10 +735,10 @@ Index: u-boot-2010.03/board/armadeus/apf27/fpga.h
 +extern int fpga_busy_fn (int cookie);
 diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S
 new file mode 100644
-index 0000000..4d72d8c
+index 0000000..dab8d78
 --- /dev/null
 +++ b/board/armadeus/apf27/lowlevel_init.S
-@@ -0,0 +1,365 @@
+@@ -0,0 +1,277 @@
 +/*
 + * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
 + * Applications Processor Reference Manual, Rev. 0.2".
@@ -650,117 +764,25 @@ index 0000000..4d72d8c
 +
 +#include <config.h>
 +#include <version.h>
++#include <asm/macro.h>        
 +#include <asm/arch/imx-regs.h>
++#include <generated/asm-offsets.h>
 +
 +
 +
-+#define writel(reg, val) \
-+	ldr		r0,	=reg;	\
-+	ldr		r1,	=val;	\
-+	str		r1,   [r0];
 +
 +.macro port_init
-+    writel( FMCR, CONFIG_SYS_FMCR_VAL)
-+/* PORTA */
-+    writel( DR(PORTA), CONFIG_SYS_DR_A_VAL)
-+    writel( OCR1(PORTA), CONFIG_SYS_OCR1_A_VAL)
-+    writel( OCR2(PORTA), CONFIG_SYS_OCR2_A_VAL)
-+    writel( ICONFA1(PORTA), CONFIG_SYS_ICFA1_A_VAL)
-+    writel( ICONFA2(PORTA), CONFIG_SYS_ICFA2_A_VAL)
-+    writel( ICONFB1(PORTA), CONFIG_SYS_ICFB1_A_VAL)
-+    writel( ICONFB2(PORTA), CONFIG_SYS_ICFB2_A_VAL)
-+    writel( ICR1(PORTA), CONFIG_SYS_ICR1_A_VAL)
-+    writel( ICR2(PORTA), CONFIG_SYS_ICR2_A_VAL)
-+    writel( IMR(PORTA), CONFIG_SYS_IMR_A_VAL)
-+    writel( DDIR(PORTA), CONFIG_SYS_DDIR_A_VAL)
-+    writel( GPR(PORTA), CONFIG_SYS_GPR_A_VAL)
-+    writel( PUEN(PORTA), CONFIG_SYS_PUEN_A_VAL)
-+    writel( GIUS(PORTA), CONFIG_SYS_GIUS_A_VAL)
-+/* PORTB */
-+    writel( DR(PORTB), CONFIG_SYS_DR_B_VAL)
-+    writel( OCR1(PORTB), CONFIG_SYS_OCR1_B_VAL)
-+    writel( OCR2(PORTB), CONFIG_SYS_OCR2_B_VAL)
-+    writel( ICONFA1(PORTB), CONFIG_SYS_ICFA1_B_VAL)
-+    writel( ICONFA2(PORTB), CONFIG_SYS_ICFA2_B_VAL)
-+    writel( ICONFB1(PORTB), CONFIG_SYS_ICFB1_B_VAL)
-+    writel( ICONFB2(PORTB), CONFIG_SYS_ICFB2_B_VAL)
-+    writel( ICR1(PORTB), CONFIG_SYS_ICR1_B_VAL)
-+    writel( ICR2(PORTB), CONFIG_SYS_ICR2_B_VAL)
-+    writel( IMR(PORTB), CONFIG_SYS_IMR_B_VAL)
-+    writel( DDIR(PORTB), CONFIG_SYS_DDIR_B_VAL)
-+    writel( GPR(PORTB), CONFIG_SYS_GPR_B_VAL)
-+    writel( PUEN(PORTB), CONFIG_SYS_PUEN_B_VAL)
-+    writel( GIUS(PORTB), CONFIG_SYS_GIUS_B_VAL)
-+/* PORTC */
-+    writel( DR(PORTC), CONFIG_SYS_DR_C_VAL)
-+    writel( OCR1(PORTC), CONFIG_SYS_OCR1_C_VAL)
-+    writel( OCR2(PORTC), CONFIG_SYS_OCR2_C_VAL)
-+    writel( ICONFA1(PORTC), CONFIG_SYS_ICFA1_C_VAL)
-+    writel( ICONFA2(PORTC), CONFIG_SYS_ICFA2_C_VAL)
-+    writel( ICONFB1(PORTC), CONFIG_SYS_ICFB1_C_VAL)
-+    writel( ICONFB2(PORTC), CONFIG_SYS_ICFB2_C_VAL)
-+    writel( ICR1(PORTC), CONFIG_SYS_ICR1_C_VAL)
-+    writel( ICR2(PORTC), CONFIG_SYS_ICR2_C_VAL)
-+    writel( IMR(PORTC), CONFIG_SYS_IMR_C_VAL)
-+    writel( DDIR(PORTC), CONFIG_SYS_DDIR_C_VAL)
-+    writel( GPR(PORTC), CONFIG_SYS_GPR_C_VAL)
-+    writel( PUEN(PORTC), CONFIG_SYS_PUEN_C_VAL)
-+    writel( GIUS(PORTC), CONFIG_SYS_GIUS_C_VAL)
-+/* PORTD */
-+    writel( DR(PORTD), CONFIG_SYS_DR_D_VAL)
-+    writel( OCR1(PORTD), CONFIG_SYS_OCR1_D_VAL)
-+    writel( OCR2(PORTD), CONFIG_SYS_OCR2_D_VAL)
-+    writel( ICONFA1(PORTD), CONFIG_SYS_ICFA1_D_VAL)
-+    writel( ICONFA2(PORTD), CONFIG_SYS_ICFA2_D_VAL)
-+    writel( ICONFB1(PORTD), CONFIG_SYS_ICFB1_D_VAL)
-+    writel( ICONFB2(PORTD), CONFIG_SYS_ICFB2_D_VAL)
-+    writel( ICR1(PORTD), CONFIG_SYS_ICR1_D_VAL)
-+    writel( ICR2(PORTD), CONFIG_SYS_ICR2_D_VAL)
-+    writel( IMR(PORTD), CONFIG_SYS_IMR_D_VAL)
-+    writel( DDIR(PORTD), CONFIG_SYS_DDIR_D_VAL)
-+    writel( GPR(PORTD), CONFIG_SYS_GPR_D_VAL)
-+    writel( PUEN(PORTD), CONFIG_SYS_PUEN_D_VAL)
-+    writel( GIUS(PORTD), CONFIG_SYS_GIUS_D_VAL)
-+/* PORTE */
-+    writel( DR(PORTE), CONFIG_SYS_DR_E_VAL)
-+    writel( OCR1(PORTE), CONFIG_SYS_OCR1_E_VAL)
-+    writel( OCR2(PORTE), CONFIG_SYS_OCR2_E_VAL)
-+    writel( ICONFA1(PORTE), CONFIG_SYS_ICFA1_E_VAL)
-+    writel( ICONFA2(PORTE), CONFIG_SYS_ICFA2_E_VAL)
-+    writel( ICONFB1(PORTE), CONFIG_SYS_ICFB1_E_VAL)
-+    writel( ICONFB2(PORTE), CONFIG_SYS_ICFB2_E_VAL)
-+    writel( ICR1(PORTE), CONFIG_SYS_ICR1_E_VAL)
-+    writel( ICR2(PORTE), CONFIG_SYS_ICR2_E_VAL)
-+    writel( IMR(PORTE), CONFIG_SYS_IMR_E_VAL)
-+    writel( DDIR(PORTE), CONFIG_SYS_DDIR_E_VAL)
-+    writel( GPR(PORTE), CONFIG_SYS_GPR_E_VAL)
-+    writel( PUEN(PORTE), CONFIG_SYS_PUEN_E_VAL)
-+    writel( GIUS(PORTE), CONFIG_SYS_GIUS_E_VAL)
-+/* PORTF */
-+    writel( DR(PORTF), CONFIG_SYS_DR_F_VAL)
-+    writel( OCR1(PORTF), CONFIG_SYS_OCR1_F_VAL)
-+    writel( OCR2(PORTF), CONFIG_SYS_OCR2_F_VAL)
-+    writel( ICONFA1(PORTF), CONFIG_SYS_ICFA1_F_VAL)
-+    writel( ICONFA2(PORTF), CONFIG_SYS_ICFA2_F_VAL)
-+    writel( ICONFB1(PORTF), CONFIG_SYS_ICFB1_F_VAL)
-+    writel( ICONFB2(PORTF), CONFIG_SYS_ICFB2_F_VAL)
-+    writel( ICR1(PORTF), CONFIG_SYS_ICR1_F_VAL)
-+    writel( ICR2(PORTF), CONFIG_SYS_ICR2_F_VAL)
-+    writel( IMR(PORTF), CONFIG_SYS_IMR_F_VAL)
-+    writel( DDIR(PORTF), CONFIG_SYS_DDIR_F_VAL)
-+    writel( GPR(PORTF), CONFIG_SYS_GPR_F_VAL)
-+    writel( PUEN(PORTF), CONFIG_SYS_PUEN_F_VAL)
-+    writel( GIUS(PORTF), CONFIG_SYS_GIUS_F_VAL)
++    write32 FMCR, CONFIG_SYS_FMCR_VAL
 +.endm /* port_init */
 +
 +.macro init_aipi
 +	/*
 +	 * setup AIPI1 and AIPI2
 +	 */
-+	writel(AIPI1_PSR0, CONFIG_SYS_AIPI1_PSR0_VAL)
-+	writel(AIPI1_PSR1, CONFIG_SYS_AIPI1_PSR1_VAL)
-+	writel(AIPI2_PSR0, CONFIG_SYS_AIPI2_PSR0_VAL)
-+	writel(AIPI2_PSR1, CONFIG_SYS_AIPI2_PSR1_VAL)
++	write32 AIPI1_PSR0, CONFIG_SYS_AIPI1_PSR0_VAL
++	write32 AIPI1_PSR1, CONFIG_SYS_AIPI1_PSR1_VAL
++	write32 AIPI2_PSR0, CONFIG_SYS_AIPI2_PSR0_VAL
++	write32 AIPI2_PSR1, CONFIG_SYS_AIPI2_PSR1_VAL
 +
 +	/* Change SDRAM signal strengh */
 +	ldr r0, =GPCR
@@ -781,10 +803,10 @@ index 0000000..4d72d8c
 + 	/*
 +	 * pll clock initialization predefined in apf27.h
 +	 */
-+	writel(MPCTL0, CONFIG_SYS_MPCTL0_VAL)
-+	writel(SPCTL0, CONFIG_SYS_SPCTL0_VAL)
++	write32 MPCTL0, CONFIG_SYS_MPCTL0_VAL
++	write32 SPCTL0, CONFIG_SYS_SPCTL0_VAL
 +
-+	writel(CSCR, CONFIG_SYS_CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART)
++	write32 CSCR, CONFIG_SYS_CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART
 +
 +	/*
 +	 * add some delay here
@@ -794,29 +816,29 @@ index 0000000..4d72d8c
 +	bne 1b
 +
 +	/* peripheral clock divider */
-+	writel(PCDR0, CONFIG_SYS_PCDR0_VAL)
-+	writel(PCDR1, CONFIG_SYS_PCDR1_VAL)
++	write32 PCDR0, CONFIG_SYS_PCDR0_VAL
++	write32 PCDR1, CONFIG_SYS_PCDR1_VAL
 +
 +	/* Configure PCCR0 and PCCR1 */
-+	writel(PCCR0, CONFIG_SYS_PCCR0_VAL)
-+	writel(PCCR1, CONFIG_SYS_PCCR1_VAL)
++	write32 PCCR0, CONFIG_SYS_PCCR0_VAL
++	write32 PCCR1, CONFIG_SYS_PCCR1_VAL
 +
 +
 +.endm /* init_clock */
 +
 +.macro sdram_init
 +	/* wait for SDRAM/LPDDR ready (SDRAMRDY) */
-+	ldr  r0, =ESDMISC
++	ldr  r0, =IMX_ESD_BASE
 +	ldr  r4, =ESDMISC_SDRAM_RDY
-+2:	ldr  r1, [r0]
++2:	ldr  r1, [r0, #ESDMISC_ROF]
 +	ands r1, r1, r4
 +	bpl 2b
 +
 +	/* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
-+	ldr		r0, =ESDMISC
++	ldr		r0, =IMX_ESD_BASE
 +	ldr		r4, =CONFIG_SYS_ESDMISC_VAL
 +	orr		r1, r4, #ESDMISC_MDDR_DL_RST
-+	str		r1, [r0]
++	str		r1, [r0, #ESDMISC_ROF]
 +
 +	/* Hold for more than 200ns */
 +	ldr r1, =0x10000
@@ -825,12 +847,15 @@ index 0000000..4d72d8c
 +
 +	str		r4, [r0]
 +
-+	writel(ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL)
++	/* write32 ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL */
++	ldr		r0, =IMX_ESD_BASE
++	ldr		r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL
++	str		r1, [r0, #ESDCFG0_ROF]
 +
 +	/* writel(ESDCTL0, CONFIG_SYS_PRECHARGE_CMD) */
-+	ldr		r0, =ESDCTL0
++	ldr		r0, =IMX_ESD_BASE
 +	ldr		r1, =CONFIG_SYS_PRECHARGE_CMD
-+	str		r1, [r0]
++	str		r1, [r0, #ESDCTL0_ROF]
 +
 +	/* writeb(0xA0001000, any value) */
 +	ldr		r1, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
@@ -838,7 +863,7 @@ index 0000000..4d72d8c
 +
 +	/* writel(ESDCTL0, CONFIG_SYS_AUTOREFRESH_CMD) */
 +	ldr		r1, =CONFIG_SYS_AUTOREFRESH_CMD
-+	str		r1, [r0]
++	str		r1, [r0, #ESDCTL0_ROF]
 +
 +	ldr 		r4, =PHYS_SDRAM_1	/* CSD0 base address	*/
 +
@@ -849,7 +874,7 @@ index 0000000..4d72d8c
 +
 +	/* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_SET_MODE_REG_CMD) */
 +	ldr		r1, =CONFIG_SYS_SET_MODE_REG_CMD
-+	str		r1, [r0]
++	str		r1, [r0, #ESDCTL0_ROF]
 +
 +	/* set standard mode register */
 +	ldr		r4, = PHYS_SDRAM_1+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
@@ -861,16 +886,17 @@ index 0000000..4d72d8c
 +
 +	/* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_NORMAL_RW_CMD) */
 +	ldr		r1, =CONFIG_SYS_NORMAL_RW_CMD
-+	str		r1, [r0]
++	str		r1, [r0, #ESDCTL0_ROF]
 +
 +#if (CONFIG_NR_DRAM_BANKS > 1)
 +	/* 2nd sdram */
-+	writel(ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL )
++	/* write32 ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL */
++	ldr		r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL
++	str		r1, [r0, #ESDCFG1_ROF]        
 +
 +	/* writel(ESDCTL1, CONFIG_SYS_PRECHARGE_CMD) */
-+	ldr		r0, =ESDCTL1
 +	ldr		r1, =CONFIG_SYS_PRECHARGE_CMD
-+	str		r1, [r0]
++	str		r1, [r0, #ESDCTL1_ROF]
 +
 +	/* writeb(0xB0001000, any value) */
 +	ldr		r1, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
@@ -878,7 +904,7 @@ index 0000000..4d72d8c
 +
 +	/* writel(ESDCTL1, CONFIG_SYS_AUTOREFRESH_CMD) */
 +	ldr		r1, =CONFIG_SYS_AUTOREFRESH_CMD
-+	str		r1, [r0]
++	str		r1, [r0, #ESDCTL1_ROF]
 +
 +	ldr 		r4, =PHYS_SDRAM_2	/* CSD1 base address */
 +
@@ -889,7 +915,7 @@ index 0000000..4d72d8c
 +
 +	/* writel(ESDCTL1, CONFIG_SYS_SET_MODE_REG_CMD) */
 +	ldr		r1, =CONFIG_SYS_SET_MODE_REG_CMD
-+	str		r1, [r0]
++	str		r1, [r0, #ESDCTL1_ROF]
 +
 +	/* set standard mode register */
 +	ldr		r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
@@ -901,7 +927,7 @@ index 0000000..4d72d8c
 +
 +	/* writel(ESDCTL1, CONFIG_SYS_NORMAL_RW_CMD) */
 +	ldr		r1, =CONFIG_SYS_NORMAL_RW_CMD
-+	str		r1, [r0]
++	str		r1, [r0, #ESDCTL1_ROF]
 +#endif  /* CONFIG_NR_DRAM_BANKS > 1 */
 +.endm /* sdram_init */
 +
@@ -913,42 +939,42 @@ index 0000000..4d72d8c
 +	init_aipi
 +
 +	/* configure csx */
-+	writel(CS0U, CONFIG_SYS_CS0U_VAL)
-+	writel(CS0L, CONFIG_SYS_CS0L_VAL)
-+	writel(CS0A, CONFIG_SYS_CS0A_VAL)
++	write32 CS0U, CONFIG_SYS_CS0U_VAL
++	write32 CS0L, CONFIG_SYS_CS0L_VAL
++	write32 CS0A, CONFIG_SYS_CS0A_VAL
 +
-+	writel(CS1U, CONFIG_SYS_CS1U_VAL)
-+	writel(CS1L, CONFIG_SYS_CS1L_VAL)
-+	writel(CS1A, CONFIG_SYS_CS1A_VAL)
++	write32 CS1U, CONFIG_SYS_CS1U_VAL
++	write32 CS1L, CONFIG_SYS_CS1L_VAL
++	write32 CS1A, CONFIG_SYS_CS1A_VAL
 +
-+	writel(CS2U, CONFIG_SYS_CS2U_VAL)
-+	writel(CS2L, CONFIG_SYS_CS2L_VAL)
-+	writel(CS2A, CONFIG_SYS_CS2A_VAL)
++	write32 CS2U, CONFIG_SYS_CS2U_VAL
++	write32 CS2L, CONFIG_SYS_CS2L_VAL
++	write32 CS2A, CONFIG_SYS_CS2A_VAL
 +
-+	writel(CS3U, CONFIG_SYS_CS3U_VAL)
-+	writel(CS3L, CONFIG_SYS_CS3L_VAL)
-+	writel(CS3A, CONFIG_SYS_CS3A_VAL)
++	write32 CS3U, CONFIG_SYS_CS3U_VAL
++	write32 CS3L, CONFIG_SYS_CS3L_VAL
++	write32 CS3A, CONFIG_SYS_CS3A_VAL
 +
-+	writel(CS4U, CONFIG_SYS_CS4U_VAL)
-+	writel(CS4L, CONFIG_SYS_CS4L_VAL)
-+	writel(CS4A, CONFIG_SYS_CS4A_VAL)
++	write32 CS4U, CONFIG_SYS_CS4U_VAL
++	write32 CS4L, CONFIG_SYS_CS4L_VAL
++	write32 CS4A, CONFIG_SYS_CS4A_VAL
 +
-+	writel(CS5U, CONFIG_SYS_CS5U_VAL)
-+	writel(CS5L, CONFIG_SYS_CS5L_VAL)
-+	writel(CS5A, CONFIG_SYS_CS5A_VAL)
++	write32 CS5U, CONFIG_SYS_CS5U_VAL
++	write32 CS5L, CONFIG_SYS_CS5L_VAL
++	write32 CS5A, CONFIG_SYS_CS5A_VAL
 +
-+	writel(EIM,  CONFIG_SYS_EIM_VAL)
++	write32 EIM,  CONFIG_SYS_EIM_VAL
 +
 +	port_init
 +
 +    /* Configure FPGA CLKO */
-+	writel(CCSR, CONFIG_SYS_CCSR_VAL)
++	write32 CCSR, CONFIG_SYS_CCSR_VAL
 +
 +    /* Configure strentgh for FPGA */
-+	writel(DSCR10, CONFIG_SYS_DSCR10_VAL)
-+	writel(DSCR3, CONFIG_SYS_DSCR3_VAL)
-+	writel(DSCR7, CONFIG_SYS_DSCR7_VAL)
-+	writel(DSCR2, CONFIG_SYS_DSCR2_VAL)
++	write32 DSCR10, CONFIG_SYS_DSCR10_VAL
++	write32 DSCR3, CONFIG_SYS_DSCR3_VAL
++	write32 DSCR7, CONFIG_SYS_DSCR7_VAL
++	write32 DSCR2, CONFIG_SYS_DSCR2_VAL
 +
 +	init_clock
 +
@@ -1053,10 +1079,10 @@ index 0000000..f66f20e
 +}
 +
 diff --git a/boards.cfg b/boards.cfg
-index 66c27a4..f68c3a7 100644
+index 30eb74f..95d713a 100644
 --- a/boards.cfg
 +++ b/boards.cfg
-@@ -69,6 +69,7 @@ integratorcp_cm926ejs        arm         arm926ejs   integrator          armltd
+@@ -70,6 +70,7 @@ integratorcp_cm926ejs        arm         arm926ejs   integrator          armltd
  aspenite                     arm         arm926ejs   -                   Marvell        armada100
  gplugd                       arm         arm926ejs   -                   Marvell        armada100
  afeb9260                     arm         arm926ejs   -                   -              at91
@@ -1064,10 +1090,11 @@ index 66c27a4..f68c3a7 100644
  at91sam9260ek_dataflash_cs0  arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0
  at91sam9260ek_dataflash_cs1  arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1
  at91sam9260ek_nandflash      arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH
-Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/Makefile
-===================================================================
---- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/nand_spl/board/armadeus/apf27/Makefile	2011-01-05 18:09:44.000000000 +0100
+diff --git a/nand_spl/board/armadeus/apf27/Makefile b/nand_spl/board/armadeus/apf27/Makefile
+new file mode 100644
+index 0000000..79a250e
+--- /dev/null
++++ b/nand_spl/board/armadeus/apf27/Makefile
 @@ -0,0 +1,77 @@
 +#
 +# (C) Copyright 2007
@@ -1146,10 +1173,11 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/Makefile
 +sinclude $(obj).depend
 +
 +#########################################################################
-Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/config.mk
-===================================================================
---- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/nand_spl/board/armadeus/apf27/config.mk	2011-01-05 18:09:44.000000000 +0100
+diff --git a/nand_spl/board/armadeus/apf27/config.mk b/nand_spl/board/armadeus/apf27/config.mk
+new file mode 100644
+index 0000000..46802e3
+--- /dev/null
++++ b/nand_spl/board/armadeus/apf27/config.mk
 @@ -0,0 +1,43 @@
 +#
 +# (C) Copyright 2007
@@ -1194,11 +1222,12 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/config.mk
 +# PAD_TO used to generate a 2kByte binary needed for the combined image
 +# -> PAD_TO = TEXT_BASE + 0x0800
 +PAD_TO	= 0xa0000800
-Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
-===================================================================
---- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S	2011-01-05 18:09:44.000000000 +0100
-@@ -0,0 +1,544 @@
+diff --git a/nand_spl/board/armadeus/apf27/start.S b/nand_spl/board/armadeus/apf27/start.S
+new file mode 100644
+index 0000000..25dd7ad
+--- /dev/null
++++ b/nand_spl/board/armadeus/apf27/start.S
+@@ -0,0 +1,552 @@
 +/*
 + *  IMX27 NAND Flash SPL (Secondary Program Loader)
 + *
@@ -1231,7 +1260,9 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
 +
 +#include <config.h>
 +#include <version.h>
++#include <asm/arch/mxc_nand.h>
 +#include <asm/arch/imx-regs.h>
++#include <generated/asm-offsets.h>
 +
 +/*
 + * Standard NAND flash commands
@@ -1643,17 +1674,17 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
 +setup_sdram_ddr:
 +
 +	/* wait for SDRAM/LPDDR ready (SDRAMRDY) */
-+	ldr  r0, =ESDMISC
++	ldr  r0, =IMX_ESD_BASE
 +	ldr  r4, =ESDMISC_SDRAM_RDY
-+2:	ldr  r1, [r0]
++2:	ldr  r1, [r0, #ESDMISC_ROF]
 +	ands r1, r1, r4
 +	bpl 2b
 +
 +	/* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
-+	ldr		r0, =ESDMISC
++	ldr		r0, =IMX_ESD_BASE
 +	ldr		r4, =CONFIG_SYS_ESDMISC_VAL
 +	orr		r1, r4, #ESDMISC_MDDR_DL_RST
-+	str		r1, [r0]
++	str		r1, [r0, #ESDMISC_ROF]
 +
 +	/* Hold for more than 200ns */
 +	ldr r1, =0x10000
@@ -1662,12 +1693,15 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
 +
 +	str		r4, [r0]
 +
-+	writel(ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL)
++	/* writel(ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL) */
++	ldr		r0, =IMX_ESD_BASE
++	ldr		r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL
++	str		r1, [r0, #ESDCFG0_ROF]
 +
 +	/* writel(ESDCTL0, CONFIG_SYS_PRECHARGE_CMD) */
-+	ldr		r0, =ESDCTL0
++	ldr		r0, =IMX_ESD_BASE
 +	ldr		r1, =CONFIG_SYS_PRECHARGE_CMD
-+	str		r1, [r0]
++	str		r1, [r0, #ESDCTL0_ROF]
 +
 +	/* writeb(0xA0001000, any value) */
 +	ldr		r1, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
@@ -1675,7 +1709,7 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
 +
 +	/* writel(ESDCTL0, CONFIG_SYS_AUTOREFRESH_CMD) */
 +	ldr		r1, =CONFIG_SYS_AUTOREFRESH_CMD
-+	str		r1, [r0]
++	str		r1, [r0, #ESDCTL0_ROF]
 +
 +	ldr 		r4, =PHYS_SDRAM_1	/* CSD0 base address	*/
 +
@@ -1686,7 +1720,7 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
 +
 +	/* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_SET_MODE_REG_CMD) */
 +	ldr		r1, =CONFIG_SYS_SET_MODE_REG_CMD
-+	str		r1, [r0]
++	str		r1, [r0, #ESDCTL0_ROF]
 +
 +	/* set standard mode register */
 +	ldr		r4, = PHYS_SDRAM_1+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
@@ -1698,16 +1732,19 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
 +
 +	/* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_NORMAL_RW_CMD) */
 +	ldr		r1, =CONFIG_SYS_NORMAL_RW_CMD
-+	str		r1, [r0]
++	str		r1, [r0, #ESDCTL0_ROF]
 +
 +#if (CONFIG_NR_DRAM_BANKS > 1)
 +	/* 2nd sdram */
-+	writel(ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL )
++	/* writel(ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL ) */
++	ldr		r0, =IMX_ESD_BASE
++	ldr		r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL
++	str		r1, [r0, #ESDCFG1_ROF]
 +
 +	/* writel(ESDCTL1, CONFIG_SYS_PRECHARGE_CMD) */
-+	ldr		r0, =ESDCTL1
++	ldr		r0, =IMX_ESD_BASE
 +	ldr		r1, =CONFIG_SYS_PRECHARGE_CMD
-+	str		r1, [r0]
++	str		r1, [r0, #ESDCTL1_ROF]
 +
 +	/* writeb(0xB0001000, any value) */
 +	ldr		r1, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
@@ -1715,7 +1752,7 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
 +
 +	/* writel(ESDCTL1, CONFIG_SYS_AUTOREFRESH_CMD) */
 +	ldr		r1, =CONFIG_SYS_AUTOREFRESH_CMD
-+	str		r1, [r0]
++	str		r1, [r0, #ESDCTL1_ROF]
 +
 +	ldr 		r4, =PHYS_SDRAM_2	/* CSD1 base address */
 +
@@ -1726,7 +1763,7 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
 +
 +	/* writel(ESDCTL1, CONFIG_SYS_SET_MODE_REG_CMD) */
 +	ldr		r1, =CONFIG_SYS_SET_MODE_REG_CMD
-+	str		r1, [r0]
++	str		r1, [r0, #ESDCTL1_ROF]
 +
 +	/* set standard mode register */
 +	ldr		r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
@@ -1738,15 +1775,16 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
 +
 +	/* writel(ESDCTL1, CONFIG_SYS_NORMAL_RW_CMD) */
 +	ldr		r1, =CONFIG_SYS_NORMAL_RW_CMD
-+	str		r1, [r0]
++	str		r1, [r0, #ESDCTL1_ROF]
 +#endif  /* CONFIG_NR_DRAM_BANKS > 1 */
 +
 +	mov	pc, lr
 +
-Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/u-boot.lds
-===================================================================
---- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/nand_spl/board/armadeus/apf27/u-boot.lds	2011-01-05 18:09:44.000000000 +0100
+diff --git a/nand_spl/board/armadeus/apf27/u-boot.lds b/nand_spl/board/armadeus/apf27/u-boot.lds
+new file mode 100644
+index 0000000..aff356f
+--- /dev/null
++++ b/nand_spl/board/armadeus/apf27/u-boot.lds
 @@ -0,0 +1,37 @@
 +/*
 + * (C) Copyright 2007
@@ -1785,5 +1823,6 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/u-boot.lds
 +		*(.text)
 +	}
 +}
+-- 
 1.7.4.4
 
diff --git a/patches/u-boot/2011.12/340-apf27-misc-commands.patch b/patches/u-boot/2011.12/340-apf27-misc-commands.patch
index c231719..23ade88 100644
--- a/patches/u-boot/2011.12/340-apf27-misc-commands.patch
+++ b/patches/u-boot/2011.12/340-apf27-misc-commands.patch
@@ -1,7 +1,46 @@
-Index: /board/armadeus/apf27/cmd_imxfuse.c
-===================================================================
---- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ /board/armadeus/apf27/cmd_imxfuse.c	2011-01-05 18:08:44.000000000 +0100
+Add apf27 imxfuse command
+
+Signed-off-by: Philippe Reynes <tr...@ya...>
+---
+ arch/arm/include/asm/arch-mx27/imx-regs.h |    4 +
+ board/armadeus/apf27/Makefile             |    2 +-
+ board/armadeus/apf27/cmd_imxfuse.c        |  331 +++++++++++++++++++++++++++++
+ 3 files changed, 336 insertions(+), 1 deletions(-)
+ create mode 100644 board/armadeus/apf27/cmd_imxfuse.c
+
+diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
+index 4df67d6..be2bf41 100644
+--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
++++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
+@@ -522,6 +522,10 @@ struct fuse_bank0_regs {
+ #define IIM_ERR_SNSE	(1 << 2)
+ #define IIM_ERR_PARITYE	(1 << 1)
+ 
++/* IIM Control Registers */
++#define IIM_BANK_AREA	IMX_IIM_BASE + 0x800
++#define IIM_BANK_REG(x,y) (IIM_BANK_AREA + 0x400 * x + (y<<2))
++
+ /*
+  * Memory areas of the NFC
+  */
+diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile
+index b67334c..e87df1d 100644
+--- a/board/armadeus/apf27/Makefile
++++ b/board/armadeus/apf27/Makefile
+@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
+ 
+ LIB	= $(obj)lib$(BOARD).o
+ 
+-COBJS	:= apf27.o fpga.o
++COBJS	:= apf27.o fpga.o cmd_imxfuse.o
+ SOBJS	:= lowlevel_init.o
+ 
+ SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+diff --git a/board/armadeus/apf27/cmd_imxfuse.c b/board/armadeus/apf27/cmd_imxfuse.c
+new file mode 100644
+index 0000000..cd2078a
+--- /dev/null
++++ b/board/armadeus/apf27/cmd_imxfuse.c
 @@ -0,0 +1,331 @@
 +/*
 + * cmd_imxfuse-c Interface to iMX IC Identification Module
@@ -334,16 +373,6 @@ Index: /board/armadeus/apf27/cmd_imxfuse.c
 +	"imxfuse scc_key - read iMX SCC_KEY\n");
 +
 +#endif /* CONFIG_CMD_IMX_FUSE */
-Index: /board/armadeus/apf27/mx27/Makefile
-===================================================================
---- /board/armadeus/apf27/Makefile	2011-01-05 18:05:13.000000000 +0100
-+++ /board/armadeus/apf27/Makefile	2011-01-05 18:08:44.000000000 +0100
-@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
- 
- LIB	= $(obj)lib$(BOARD).o
- 
--COBJS	:= apf27.o fpga.o
-+COBJS	:= apf27.o fpga.o cmd_imxfuse.o
- SOBJS	:= lowlevel_init.o
- 
- SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+-- 
+1.7.4.4
+


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armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-315-g0da920b

[jorasse <jo...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  0da920b941b3c8c8144d0181c4ffec7f9ad5767c (commit)
      from  016e87336b375cd7657a7ccf040d50296577b672 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 0da920b941b3c8c8144d0181c4ffec7f9ad5767c
Author: Eric Jarrige <eri...@ar...>
Date:   Wed May 23 01:10:16 2012 +0200

    [UBOOT] apf27: cleanup and reorganize patchwork

-----------------------------------------------------------------------

Summary of changes:
 ...-Add-support-for-the-armadeus-apf27-board.patch | 1243 ++++++++++++++++----
 .../u-boot/2011.12/304-Add-type-for-apf27.patch    |   24 -
 patches/u-boot/2011.12/310-apf27-nand-spl.patch    |  721 ------------
 3 files changed, 982 insertions(+), 1006 deletions(-)
 delete mode 100644 patches/u-boot/2011.12/304-Add-type-for-apf27.patch
 delete mode 100644 patches/u-boot/2011.12/310-apf27-nand-spl.patch

diff --git a/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch b/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
index a8cde15..b3e53eb 100644
--- a/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
+++ b/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
@@ -301,6 +301,324 @@ index 0000000..3354ba0
 +TEXT_BASE = 0xAFF00000
 +endif
 +# CONFIG_NAND_U_BOOT = y
+Index: u-boot-2010.03/board/armadeus/apf27/fpga.c
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2010.03/board/armadeus/apf27/fpga.c	2011-01-05 18:09:44.000000000 +0100
+@@ -0,0 +1,269 @@
++/*
++ * (C) Copyright 2002-2008
++ * Eric Jarrige <eri...@ar...>
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++#include <common.h>
++
++#if defined(CONFIG_FPGA)
++
++#include <asm/arch/imx-regs.h>
++#include <asm/io.h>
++#include <command.h>
++#include <config.h>
++#include "fpga.h"
++#include <spartan3.h>
++
++#define GPIO_PORT(x)  ((x & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT)
++#define GPIO_SET(x)   writel(readl(&gpregs->port[GPIO_PORT(x)].dr) | (1 << (x & GPIO_PIN_MASK)), \
++				&gpregs->port[GPIO_PORT(x)].dr)
++//(DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK)))
++#define GPIO_CLEAR(x) writel(readl(&gpregs->port[GPIO_PORT(x)].dr) & ~(1 << (x & GPIO_PIN_MASK)), \
++				&gpregs->port[GPIO_PORT(x)].dr)
++//(DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK)))
++#define GPIO_WRITE(x,y) ( y ? GPIO_SET(x) : GPIO_CLEAR(x) )
++#define GPIO_READ(x) ((readl(&gpregs->port[GPIO_PORT(x)].ssr) & (1 << (x & GPIO_PIN_MASK))) \
++				>> (x & GPIO_PIN_MASK))
++//((SSR (GPIO_PORT(x)) & (1<<(x & GPIO_PIN_MASK)))>> (x & GPIO_PIN_MASK))
++#ifdef FPGA_DEBUG
++#define	PRINTF(fmt,args...)	printf (fmt ,##args)
++#else
++#define	PRINTF(fmt,args...)
++#endif
++
++/* Note that these are pointers to code that is in Flash.  They will be
++ * relocated at runtime.
++ * Spartan2 code is used to download our Spartan 3 :) code is compatible.
++ * Just take care about the file size
++*/
++Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
++	fpga_pre_fn,
++	fpga_pgm_fn,
++	fpga_init_fn,
++	NULL,
++	fpga_done_fn,
++	fpga_clk_fn,
++	fpga_cs_fn,
++	fpga_wr_fn,
++	fpga_rdata_fn,
++	fpga_wdata_fn,
++   fpga_busy_fn,
++	fpga_abort_fn,
++	fpga_post_fn,
++};
++
++Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
++	{Xilinx_Spartan3,
++	 slave_parallel,
++	 1196128l/8,
++	 (void *) &fpga_fns,
++	 0}
++};
++
++/*
++ * nitialize GPIO port B before download
++ */
++int
++fpga_pre_fn (int cookie)
++{
++       struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++	// Initialize GPIO pins
++	GPIO_SET(CONFIG_SYS_FPGA_PWR);
++	imx_gpio_mode (CONFIG_SYS_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
++	imx_gpio_mode (CONFIG_SYS_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
++	imx_gpio_mode (CONFIG_SYS_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++	imx_gpio_mode (CONFIG_SYS_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++	imx_gpio_mode (CONFIG_SYS_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++	imx_gpio_mode (CONFIG_SYS_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++	imx_gpio_mode (CONFIG_SYS_FPGA_SUSPEND | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++	GPIO_SET(CONFIG_SYS_FPGA_RESET);
++	imx_gpio_mode (CONFIG_SYS_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++	imx_gpio_mode (CONFIG_SYS_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++	GPIO_SET(CONFIG_SYS_FPGA_PRG);
++	GPIO_SET(CONFIG_SYS_FPGA_CLK);
++	GPIO_SET(CONFIG_SYS_FPGA_RW);
++	GPIO_SET(CONFIG_SYS_FPGA_CS);
++	GPIO_CLEAR(CONFIG_SYS_FPGA_SUSPEND);
++// 	GPIO_CLEAR(CONFIG_SYS_FPGA_RESET);
++	GPIO_CLEAR(CONFIG_SYS_FPGA_PWR);
++
++	return cookie;
++}
++
++/*
++ * Set the FPGA's active-low program line to the specified level
++ */
++int
++fpga_pgm_fn (int assert, int flush, int cookie)
++{
++       struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++	PRINTF ("%s:%d: FPGA PROGRAM %s", __FUNCTION__, __LINE__,
++					assert?"high":"low");
++	GPIO_WRITE( CONFIG_SYS_FPGA_PRG, !assert);
++	return assert;
++}
++
++/*
++ * Set the FPGA's active-high clock line to the specified level
++ */
++int
++fpga_clk_fn (int assert_clk, int flush, int cookie)
++{
++       struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++	PRINTF ("%s:%d: FPGA CLOCK %s", __FUNCTION__, __LINE__,
++					assert_clk?"high":"low");
++	GPIO_WRITE( CONFIG_SYS_FPGA_CLK, !assert_clk);
++	return assert_clk;
++}
++
++/*
++ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
++ * asserted (low).
++ */
++int
++fpga_init_fn (int cookie)
++{
++       struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++	int value;
++	PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
++	value = GPIO_READ(CONFIG_SYS_FPGA_INIT);
++	//printf("init value read %x",value);
++#ifdef CONFIG_SYS_FPGA_IS_PROTO
++	return value;
++#else
++	return !value;
++#endif
++}
++
++/*
++ * Test the state of the active-high FPGA DONE pin
++ */
++int
++fpga_done_fn (int cookie)
++{
++       struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++	PRINTF ("%s:%d: DONE check... %s", __FUNCTION__, __LINE__,
++					GPIO_READ(CONFIG_SYS_FPGA_DONE)?"high":"low");
++	return(GPIO_READ(CONFIG_SYS_FPGA_DONE)?FPGA_SUCCESS:FPGA_FAIL);
++}
++
++/*
++ * Set the FPGA's wr line to the specified level
++ */
++int
++fpga_wr_fn (int assert_write, int flush, int cookie)
++{
++       struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++	PRINTF ("%s:%d: FPGA RW... %s ", __FUNCTION__, __LINE__,
++					assert_write?"high":"low");
++	GPIO_WRITE( CONFIG_SYS_FPGA_RW, !assert_write);
++	return assert_write;
++}
++
++int
++fpga_cs_fn (int assert_cs, int flush, int cookie)
++{
++       struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++	PRINTF ("%s:%d: FPGA CS %s ", __FUNCTION__, __LINE__,
++					assert_cs?"high":"low");
++	GPIO_WRITE( CONFIG_SYS_FPGA_CS, !assert_cs);
++	return assert_cs;
++}
++
++int
++fpga_rdata_fn ( unsigned char *data, int cookie )
++{
++	PRINTF ("%s:%d: FPGA READ DATA %02X ", __FUNCTION__, __LINE__,
++					*((char*)CONFIG_SYS_FPGA_RDATA));
++	*data = (unsigned char)((*((unsigned short*)CONFIG_SYS_FPGA_RDATA))&0x00FF);
++	return *data;
++}
++
++int
++fpga_wdata_fn ( unsigned char data, int cookie )
++{
++	PRINTF ("%s:%d: FPGA WRITE DATA %02X ", __FUNCTION__, __LINE__,
++					data);
++	*((unsigned short*)CONFIG_SYS_FPGA_WDATA) = data;
++	return data;
++}
++
++int
++fpga_abort_fn ( int cookie )
++{
++	return cookie;
++}
++
++
++int
++fpga_busy_fn ( int cookie )
++{
++	return 1;
++}
++
++int
++fpga_post_fn (int cookie)
++{
++       struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++	PRINTF ("%s:%d: FPGA POST ", __FUNCTION__, __LINE__);
++
++	imx_gpio_mode (CONFIG_SYS_FPGA_RW | GPIO_PF | GPIO_PUEN);
++	imx_gpio_mode (CONFIG_SYS_FPGA_CS | GPIO_PF | GPIO_PUEN);
++	imx_gpio_mode (CONFIG_SYS_FPGA_CLK | GPIO_PF | GPIO_PUEN);
++	GPIO_SET(CONFIG_SYS_FPGA_PRG);
++	GPIO_CLEAR(CONFIG_SYS_FPGA_RESET);
++	imx_gpio_mode (CONFIG_SYS_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++	return cookie;
++}
++
++/*
++ * Initialize the fpga.  Return 1 on success, 0 on failure.
++ */
++int
++APF27_init_fpga (u_char * buffer, size_t size)
++{
++	char *autoload = getenv ("firmware_autoload");
++
++	int i,lout=0;
++
++       fpga_init();
++
++	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
++		PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
++		fpga_add (fpga_xilinx, &fpga[i]);
++	}
++
++	if ((size >= fpga[0].size) && ( autoload ) && (0 == strcmp(autoload, "1"))) {
++		if (ctrlc()) {
++			printf("Firmware download stopped!\n"); 
++		} else if (FPGA_SUCCESS != fpga_load( 0,(void *)buffer, size )) {
++			printf("Firmware download failed!\n");
++		} else {
++			printf("Firmware successfully programmed\n");
++			lout = 1;
++		}
++	}
++	return lout;
++}
++
++#endif /* CONFIG_FPGA */
+Index: u-boot-2010.03/board/armadeus/apf27/fpga.h
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2010.03/board/armadeus/apf27/fpga.h	2011-01-05 18:09:44.000000000 +0100
+@@ -0,0 +1,39 @@
++/*
++ * (C) Copyright 2002-2008
++ * Eric Jarrige <eri...@ar...>
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++extern int APF27_init_fpga (u_char * buffer, size_t size);
++
++extern int fpga_pre_fn (int cookie);
++extern int fpga_pgm_fn (int assert_pgm, int flush, int cookie);
++extern int fpga_cs_fn (int assert_cs, int flush, int cookie);
++extern int fpga_init_fn (int cookie);
++extern int fpga_done_fn (int cookie);
++extern int fpga_clk_fn (int assert_clk, int flush, int cookie);
++extern int fpga_wr_fn (int assert_write, int flush, int cookie);
++extern int fpga_rdata_fn ( unsigned char *data, int cookie );
++extern int fpga_wdata_fn ( unsigned char data, int cookie );
++extern int fpga_abort_fn (int cookie);
++extern int fpga_post_fn (int cookie);
++extern int fpga_busy_fn (int cookie);
 diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S
 new file mode 100644
 index 0000000..4d72d8c
@@ -721,42 +1039,175 @@ index 0000000..f66f20e
 +	. = ALIGN(4);
 +	.data : { *(.data) }
 +
-+	. = ALIGN(4);
-+	.got : { *(.got) }
++	. = ALIGN(4);
++	.got : { *(.got) }
++
++	__u_boot_cmd_start = .;
++	.u_boot_cmd : { *(.u_boot_cmd) }
++	__u_boot_cmd_end = .;
++
++	. = ALIGN(4);
++	__bss_start = .;
++	.bss : { *(.bss) }
++	_end = .;
++}
++
+diff --git a/boards.cfg b/boards.cfg
+index 66c27a4..f68c3a7 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -69,6 +69,7 @@ integratorcp_cm926ejs        arm         arm926ejs   integrator          armltd
+ aspenite                     arm         arm926ejs   -                   Marvell        armada100
+ gplugd                       arm         arm926ejs   -                   Marvell        armada100
+ afeb9260                     arm         arm926ejs   -                   -              at91
++apf27                        arm         arm926ejs   apf27               armadeus       mx27
+ at91sam9260ek_dataflash_cs0  arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0
+ at91sam9260ek_dataflash_cs1  arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1
+ at91sam9260ek_nandflash      arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH
+Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/Makefile
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2010.03/nand_spl/board/armadeus/apf27/Makefile	2011-01-05 18:09:44.000000000 +0100
+@@ -0,0 +1,77 @@
++#
++# (C) Copyright 2007
++# Stefan Roese, DENX Software Engineering, sr...@de....
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
++
++LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
++LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
++AFLAGS	+= -DCONFIG_NAND_SPL
++CFLAGS	+= -DCONFIG_NAND_SPL
++
++SOBJS	= start.o
++COBJS	=
++
++SRCS	:= $(addprefix $(src),$(SOBJS:.o=.S) $(COBJS:.o=.c))
++OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
++__OBJS	:= $(SOBJS) $(COBJS)
++LNDIR	:= $(OBJTREE)/nand_spl/board/$(BOARDDIR)
++
++nandobj	:= $(OBJTREE)/nand_spl/
++
++ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
++	$(nandobj)System.map
++
++all:	$(obj).depend $(ALL)
++
++$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
++	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
++
++$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
++	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
++
++$(nandobj)u-boot-spl:	$(OBJS)
++	cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
++		-Map $(nandobj)u-boot-spl.map \
++		-o $(nandobj)u-boot-spl
++
++$(nandobj)System.map:	$(nandobj)u-boot-spl
++		@$(NM) $< | \
++		grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
++		sort > $(nandobj)System.map
++
++
++#########################################################################
++
++$(obj)%.o:	%.S
++	$(CC) $(AFLAGS) -c -o $@ $<
++
++$(obj)%.o:	%.c
++	$(CC) $(CFLAGS) -c -o $@ $<
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/config.mk
+===================================================================
+--- /dev/null	1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2010.03/nand_spl/board/armadeus/apf27/config.mk	2011-01-05 18:09:44.000000000 +0100
+@@ -0,0 +1,43 @@
++#
++# (C) Copyright 2007
++# Stefan Roese, DENX Software Engineering, sr...@de....
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++#
++# This config file is used for compilation of armadeus apf27 board
++#
 +
-+	__u_boot_cmd_start = .;
-+	.u_boot_cmd : { *(.u_boot_cmd) }
-+	__u_boot_cmd_end = .;
++#
++# TEXT_BASE for SPL:
++#
++#
++# This config file is used for compilation of armadeus sources
++#
++# You might change location of U-Boot in memory by setting right TEXT_BASE.
++# This allows for example having one copy located at the end of ram and stored
++# in flash device and later on while developing use other location to test
++# the code in RAM device only.
++#
 +
-+	. = ALIGN(4);
-+	__bss_start = .;
-+	.bss : { *(.bss) }
-+	_end = .;
-+}
++TEXT_BASE = 0xa0000000
 +
-diff --git a/boards.cfg b/boards.cfg
-index 66c27a4..f68c3a7 100644
---- a/boards.cfg
-+++ b/boards.cfg
-@@ -69,6 +69,7 @@ integratorcp_cm926ejs        arm         arm926ejs   integrator          armltd
- aspenite                     arm         arm926ejs   -                   Marvell        armada100
- gplugd                       arm         arm926ejs   -                   Marvell        armada100
- afeb9260                     arm         arm926ejs   -                   -              at91
-+apf27                        arm         arm926ejs   apf27               armadeus       mx27
- at91sam9260ek_dataflash_cs0  arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0
- at91sam9260ek_dataflash_cs1  arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1
- at91sam9260ek_nandflash      arm         arm926ejs   at91sam9260ek       atmel          at91        at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH
-1.7.4.4
-Index: u-boot-2010.03/board/armadeus/apf27/fpga.c
++# PAD_TO used to generate a 2kByte binary needed for the combined image
++# -> PAD_TO = TEXT_BASE + 0x0800
++PAD_TO	= 0xa0000800
+Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/board/armadeus/apf27/fpga.c	2011-01-05 18:09:44.000000000 +0100
-@@ -0,0 +1,269 @@
++++ u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S	2011-01-05 18:09:44.000000000 +0100
+@@ -0,0 +1,544 @@
 +/*
-+ * (C) Copyright 2002-2008
-+ * Eric Jarrige <eri...@ar...>
-+ * Rich Ireland, Enterasys Networks, rir...@en....
-+ * Keith Outwater, kei...@mv....
++ *  IMX27 NAND Flash SPL (Secondary Program Loader)
++ *
++ *  Copyright (c) 2008  Armadeus Project / eja
++ *
++ *  Based on Freescale NAND SPL
++ *
++ *  Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
++ *  Copyright (c) 2008	Eric Jarrige <eri...@ar...>
 + *
 + * See file CREDITS for list of people who contributed to this
 + * project.
@@ -775,262 +1226,531 @@ Index: u-boot-2010.03/board/armadeus/apf27/fpga.c
 + * along with this program; if not, write to the Free Software
 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 + * MA 02111-1307 USA
-+ *
 + */
-+#include <common.h>
 +
-+#if defined(CONFIG_FPGA)
 +
-+#include <asm/arch/imx-regs.h>
-+#include <asm/io.h>
-+#include <command.h>
 +#include <config.h>
-+#include "fpga.h"
-+#include <spartan3.h>
++#include <version.h>
++#include <asm/arch/imx-regs.h>
 +
-+#define GPIO_PORT(x)  ((x & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT)
-+#define GPIO_SET(x)   writel(readl(&gpregs->port[GPIO_PORT(x)].dr) | (1 << (x & GPIO_PIN_MASK)), \
-+				&gpregs->port[GPIO_PORT(x)].dr)
-+//(DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK)))
-+#define GPIO_CLEAR(x) writel(readl(&gpregs->port[GPIO_PORT(x)].dr) & ~(1 << (x & GPIO_PIN_MASK)), \
-+				&gpregs->port[GPIO_PORT(x)].dr)
-+//(DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK)))
-+#define GPIO_WRITE(x,y) ( y ? GPIO_SET(x) : GPIO_CLEAR(x) )
-+#define GPIO_READ(x) ((readl(&gpregs->port[GPIO_PORT(x)].ssr) & (1 << (x & GPIO_PIN_MASK))) \
-+				>> (x & GPIO_PIN_MASK))
-+//((SSR (GPIO_PORT(x)) & (1<<(x & GPIO_PIN_MASK)))>> (x & GPIO_PIN_MASK))
-+#ifdef FPGA_DEBUG
-+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
++/*
++ * Standard NAND flash commands
++ */
++#define NAND_CMD_READ0		0
++#define NAND_CMD_READ1		1
++#define NAND_CMD_PAGEPROG	0x10
++#define NAND_CMD_READOOB	0x50
++#define NAND_CMD_ERASE1		0x60
++#define NAND_CMD_STATUS		0x70
++#define NAND_CMD_STATUS_MULTI	0x71
++#define NAND_CMD_SEQIN		0x80
++#define NAND_CMD_READID		0x90
++#define NAND_CMD_ERASE2		0xd0
++#define NAND_CMD_RESET		0xff
++
++/* Extended commands for large page devices */
++#define NAND_CMD_READSTART	0x30
++#define NAND_CMD_CACHEDPROG	0x15
++
++/* Status bits */
++#define NAND_STATUS_FAIL	0x01
++#define NAND_STATUS_FAIL_N1	0x02
++#define NAND_STATUS_TRUE_READY	0x20
++#define NAND_STATUS_READY	0x40
++#define NAND_STATUS_WP		0x80
++
++#define writel(reg, val)		\
++	ldr		r0,	=reg;	\
++	ldr		r1,	=val;	\
++	str		r1,   [r0];
++
++	.macro nand_boot
++
++#ifdef CONFIG_BOOT_TRACE_REG
++/*
++ * If CONFIG_BOOT_TRACE_REG is a SDRAM address then be sure to use the following
++ * 2 command after SDRAM init
++ */
++
++/* Backup state of previous boot to CONFIG_BOOT_TRACE_REG+4*/
++#define BACKUP_TRACE()			\
++	ldr r4, =CONFIG_BOOT_TRACE_REG;	\
++	ldr r3, [r4];			\
++	str r3, [r4, #0x04];
++
++/* Save a state of boot at CONFIG_BOOT_TRACE_REG */
++#define BOOT_TRACE(val)		\
++	ldr r4, =CONFIG_BOOT_TRACE_REG;	\
++	ldr r3, =val;			\
++	str r3, [r4];
 +#else
-+#define	PRINTF(fmt,args...)
++#define BACKUP_TRACE()
++#define BOOT_TRACE(val)
 +#endif
 +
-+/* Note that these are pointers to code that is in Flash.  They will be
-+ * relocated at runtime.
-+ * Spartan2 code is used to download our Spartan 3 :) code is compatible.
-+ * Just take care about the file size
-+*/
-+Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
-+	fpga_pre_fn,
-+	fpga_pgm_fn,
-+	fpga_init_fn,
-+	NULL,
-+	fpga_done_fn,
-+	fpga_clk_fn,
-+	fpga_cs_fn,
-+	fpga_wr_fn,
-+	fpga_rdata_fn,
-+	fpga_wdata_fn,
-+   fpga_busy_fn,
-+	fpga_abort_fn,
-+	fpga_post_fn,
-+};
++nand_boot_setup:
 +
-+Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
-+	{Xilinx_Spartan3,
-+	 slave_parallel,
-+	 1196128l/8,
-+	 (void *) &fpga_fns,
-+	 0}
-+};
++	/* Copy SPL image from flash to SDRAM first */
++	BOOT_TRACE(1)
++	ldr r0, =IMX_NFC_MAIN_AREA0
++	add r2, r0, #(IMX_NFC_SPARE_AREA0-IMX_NFC_MAIN_AREA0) //2KB NFC Buff
++	ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST
 +
-+/*
-+ * nitialize GPIO port B before download
-+ */
-+int
-+fpga_pre_fn (int cookie)
-+{
-+       struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+	// Initialize GPIO pins
-+	GPIO_SET(CONFIG_SYS_FPGA_PWR);
-+	imx_gpio_mode (CONFIG_SYS_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
-+	imx_gpio_mode (CONFIG_SYS_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
-+	imx_gpio_mode (CONFIG_SYS_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+	imx_gpio_mode (CONFIG_SYS_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+	imx_gpio_mode (CONFIG_SYS_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+	imx_gpio_mode (CONFIG_SYS_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+	imx_gpio_mode (CONFIG_SYS_FPGA_SUSPEND | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+	GPIO_SET(CONFIG_SYS_FPGA_RESET);
-+	imx_gpio_mode (CONFIG_SYS_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+	imx_gpio_mode (CONFIG_SYS_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+	GPIO_SET(CONFIG_SYS_FPGA_PRG);
-+	GPIO_SET(CONFIG_SYS_FPGA_CLK);
-+	GPIO_SET(CONFIG_SYS_FPGA_RW);
-+	GPIO_SET(CONFIG_SYS_FPGA_CS);
-+	GPIO_CLEAR(CONFIG_SYS_FPGA_SUSPEND);
-+// 	GPIO_CLEAR(CONFIG_SYS_FPGA_RESET);
-+	GPIO_CLEAR(CONFIG_SYS_FPGA_PWR);
++	BOOT_TRACE(2)
++1:	ldmia r0!, {r3-r10}
++	stmia r1!, {r3-r10}
++	cmp r0, r2
++	blo 1b
 +
-+	return cookie;
-+}
 +
-+/*
-+ * Set the FPGA's active-low program line to the specified level
-+ */
-+int
-+fpga_pgm_fn (int assert, int flush, int cookie)
-+{
-+       struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+	PRINTF ("%s:%d: FPGA PROGRAM %s", __FUNCTION__, __LINE__,
-+					assert?"high":"low");
-+	GPIO_WRITE( CONFIG_SYS_FPGA_PRG, !assert);
-+	return assert;
-+}
 +
-+/*
-+ * Set the FPGA's active-high clock line to the specified level
-+ */
-+int
-+fpga_clk_fn (int assert_clk, int flush, int cookie)
-+{
-+       struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+	PRINTF ("%s:%d: FPGA CLOCK %s", __FUNCTION__, __LINE__,
-+					assert_clk?"high":"low");
-+	GPIO_WRITE( CONFIG_SYS_FPGA_CLK, !assert_clk);
-+	return assert_clk;
-+}
++	/* Jump to SDRAM */
++	BOOT_TRACE(3)
++	ldr r1, =0xFFF
++	and r0, pc, r1	 /* offset of pc */
++	ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST
++	add r1, r1, #0x10
++	add pc, r0, r1
++	nop
++	nop
++	nop
++	nop
++
++NAND_Copy_Main:
++	BOOT_TRACE(4)
++	/* r0: nfc base. Reloaded after each page copying		*/
++	ldr r0, =IMX_NFC_MAIN_AREA0
++
++	/* r1: starting flash addr to be copied. Updated constantly	*/
++	/* bypass the first preloaded pages				*/
++	ldr r1, =(IMX_NFC_SPARE_AREA0-IMX_NFC_MAIN_AREA0)
++
++	/* r2: end of 1st RAM buf. Doesn't change			*/
++	ldr r2, =IMX_NFC_MAIN_AREA1
++
++	/* r12: NFC register base. Doesn't change			*/
++	ldr r12, =IMX_NFC_REGS
++
++	ldr r11, =CONFIG_SYS_NAND_U_BOOT_DST
++
++	/* r13: end of SDRAM address for copying. Doesn't change	*/
++	add r13, r11, #CONFIG_SYS_NAND_U_BOOT_SIZE
++
++	/* r11: starting SDRAM address for copying. Updated constantly	*/
++	add r11, r11, r1
++
++	/* unlock internal buffer					*/
++	ldr r3, =NFC_CONFIG_UNLOCKED
++	strh r3, [r12, #NFC_OFFSET_CONFIG]
++
++	/* enable ECC and mask interrupts				*/
++	ldr r3, =(NFC_CONFIG1_ECC_EN | NFC_CONFIG1_INT_MSK)
++	strh r3, [r12, #NFC_OFFSET_CONFIG1]
++
++Nfc_Read_Page:
++	BOOT_TRACE(5)
++	/*  send NAND_CMD_READ0 command				*/
++	ldr r3, =NAND_CMD_READ0;
++	strh r3, [r12, #NFC_OFFSET_FLASH_CMD]
++
++	ldr r3, =NFC_CONFIG2_FCMD
++	strh r3, [r12, #NFC_OFFSET_CONFIG2]
++	bl do_wait_op_done
++
++	/* send NAND address to read. TODO small page support		*/
++	BOOT_TRACE(6)
++	mov r3, r1, lsr #1
++	bl do_addr_input	   /* 1st addr cycle */
++
++	mov r3, r1, lsr #9
++	and r3, r3, #0x03
++	bl do_addr_input	   /* 2nd addr cycle */
++
++	mov r3, r1, lsr #11
++	bl do_addr_input	   /* 3rd addr cycle */
++
++	mov r3, r1, lsr #19
++	bl do_addr_input	   /* 4th addr cycle */
++
++	/* Small NAND flashs (== 1Gb) support 5 addr cycles		*/
++	mov r3, r1, lsr #27
++	bl do_addr_input	   /* 5th addr cycle */
++
++	/* send NAND_CMD_READSTART command. TODO small page support	*/
++	BOOT_TRACE(7)
++	mov r3, #NAND_CMD_READSTART;
++	strh r3, [r12, #NFC_OFFSET_FLASH_CMD]
++	mov r3, #NFC_CONFIG2_FCMD
++	strh r3, [r12, #NFC_OFFSET_CONFIG2]
++	bl do_wait_op_done
++
++	/* read and copy buf 0						*/
++	BOOT_TRACE(8)
++	mov r3, #0
++	strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
++
++	mov r3, #NFC_CONFIG2_FDO_PAGE
++	strh r3, [r12, #NFC_OFFSET_CONFIG2]
++	bl do_wait_op_done
++
++	bl Test_And_Copy_Buffer
++
++	/* read and copy buf 1						*/
++	mov r3, #1
++	strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
++
++	mov r3, #NFC_CONFIG2_FDO_PAGE
++	strh r3, [r12, #NFC_OFFSET_CONFIG2]
++	bl do_wait_op_done
++
++	bl Test_And_Copy_Buffer
++
++	/* here we should test if 512B page flash and bypass next buffers */
++	/* read and copy buf 2. TODO small page support		*/
++	mov r3, #2
++	strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
++
++	mov r3, #NFC_CONFIG2_FDO_PAGE
++	strh r3, [r12, #NFC_OFFSET_CONFIG2]
++	bl do_wait_op_done
++
++	bl Test_And_Copy_Buffer
++
++	/* read and copy buf 3						*/
++	mov r3, #3
++	strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
++
++	mov r3, #NFC_CONFIG2_FDO_PAGE
++	strh r3, [r12, #NFC_OFFSET_CONFIG2]
++	bl do_wait_op_done
++
++	bl Test_And_Copy_Buffer
++
++	/* is the last page ? */
++	BOOT_TRACE(12)
++	cmp r11, r13
++	bge NAND_Copy_Main_done
++
++	/* r0: nfc base. Reloaded after each page copying		*/
++	ldr r0, =IMX_NFC_MAIN_AREA0
++	/* r2: end of 1st RAM buf. Doesn't change 			*/
++	ldr r2, =IMX_NFC_MAIN_AREA1
++	b Nfc_Read_Page
++
++NAND_Copy_Main_done:
++	BOOT_TRACE(13)
++	.endm /* nand_boot */
++
++	.macro init_aipi
++	/*
++	 * setup AIPI1 and AIPI2
++	 */
++	writel(AIPI1_PSR0, CONFIG_SYS_AIPI1_PSR0_VAL)
++	writel(AIPI1_PSR1, CONFIG_SYS_AIPI1_PSR1_VAL)
++	writel(AIPI2_PSR0, CONFIG_SYS_AIPI2_PSR0_VAL)
++	writel(AIPI2_PSR1, CONFIG_SYS_AIPI2_PSR1_VAL)
++
++	/* Change SDRAM signal strengh */
++	ldr r0, =GPCR
++	ldr r1, =CONFIG_SYS_GPCR_VAL
++	ldr r5, [r0]
++	orr r5, r5, r1
++	str r5, [r0]
++
++	.endm /* init_aipi */
++
++	.macro init_clock
++	ldr r0, =CSCR
++	/* disable MPLL/SPLL first */
++	ldr r1, [r0]
++	bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
++	str r1, [r0]
++
++ 	/*
++	 * pll clock initialization predefined in apf27.h
++	 */
++	writel(MPCTL0, CONFIG_SYS_MPCTL0_VAL)
++	writel(SPCTL0, CONFIG_SYS_SPCTL0_VAL)
++
++	writel(CSCR, CONFIG_SYS_CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART)
++
++	/*
++	 * add some delay here
++	 */
++	mov r1, #0x1000
++	1:  subs r1, r1, #0x1
++	bne 1b
++
++	/* peripheral clock divider */
++	writel(PCDR0, CONFIG_SYS_PCDR0_VAL)
++	writel(PCDR1, CONFIG_SYS_PCDR1_VAL)
++
++	/* Configure PCCR0 and PCCR1 */
++	writel(PCCR0, CONFIG_SYS_PCCR0_VAL)
++	writel(PCCR1, CONFIG_SYS_PCCR1_VAL)
++
++	.endm /* init_clock */
 +
 +/*
-+ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
-+ * asserted (low).
++ *************************************************************************
++ *
++ * No jump vector table. Use reset vector as direct entry point.
++ * Do not support any interrupt event within SPL
++ *
++ *************************************************************************
 + */
-+int
-+fpga_init_fn (int cookie)
-+{
-+       struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+	int value;
-+	PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
-+	value = GPIO_READ(CONFIG_SYS_FPGA_INIT);
-+	//printf("init value read %x",value);
-+#ifdef CONFIG_SYS_FPGA_IS_PROTO
-+	return value;
-+#else
-+	return !value;
-+#endif
-+}
++
++
++.globl _start
++_start:
 +
 +/*
-+ * Test the state of the active-high FPGA DONE pin
++ *************************************************************************
++ *
++ * Startup Code (reset vector)
++ *
++ * do important init only if we don't start from memory!
++ * setup Memory and board specific bits prior to relocation.
++ * relocate armboot to ram
++ * setup stack
++ *
++ *************************************************************************
 + */
-+int
-+fpga_done_fn (int cookie)
-+{
-+       struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+	PRINTF ("%s:%d: DONE check... %s", __FUNCTION__, __LINE__,
-+					GPIO_READ(CONFIG_SYS_FPGA_DONE)?"high":"low");
-+	return(GPIO_READ(CONFIG_SYS_FPGA_DONE)?FPGA_SUCCESS:FPGA_FAIL);
-+}
++
 +
 +/*
-+ * Set the FPGA's wr line to the specified level
++ * the actual reset code
 + */
-+int
-+fpga_wr_fn (int assert_write, int flush, int cookie)
-+{
-+       struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+	PRINTF ("%s:%d: FPGA RW... %s ", __FUNCTION__, __LINE__,
-+					assert_write?"high":"low");
-+	GPIO_WRITE( CONFIG_SYS_FPGA_RW, !assert_write);
-+	return assert_write;
-+}
 +
-+int
-+fpga_cs_fn (int assert_cs, int flush, int cookie)
-+{
-+       struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+	PRINTF ("%s:%d: FPGA CS %s ", __FUNCTION__, __LINE__,
-+					assert_cs?"high":"low");
-+	GPIO_WRITE( CONFIG_SYS_FPGA_CS, !assert_cs);
-+	return assert_cs;
-+}
++reset:
++	/*
++	 * set the cpu to SVC32 mode
++	 */
++	mrs	r0,cpsr
++	bic	r0,r0,#0x1f
++	orr	r0,r0,#0xd3
++	msr	cpsr,r0
 +
-+int
-+fpga_rdata_fn ( unsigned char *data, int cookie )
-+{
-+	PRINTF ("%s:%d: FPGA READ DATA %02X ", __FUNCTION__, __LINE__,
-+					*((char*)CONFIG_SYS_FPGA_RDATA));
-+	*data = (unsigned char)((*((unsigned short*)CONFIG_SYS_FPGA_RDATA))&0x00FF);
-+	return *data;
-+}
++	/*
++	 * invalidate I/D cache/TLB and drain write buffer
++	 */
++	mov r0, #0
++	mcr p15, 0, r0, c7, c7, 0	/* invalidate I cache and D cache */
++	mcr p15, 0, r0, c8, c7, 0	/* invalidate TLBs */
++	mcr p15, 0, r0, c7, c10, 4   /* Drain the write buffer */
 +
-+int
-+fpga_wdata_fn ( unsigned char data, int cookie )
-+{
-+	PRINTF ("%s:%d: FPGA WRITE DATA %02X ", __FUNCTION__, __LINE__,
-+					data);
-+	*((unsigned short*)CONFIG_SYS_FPGA_WDATA) = data;
-+	return data;
-+}
++	/*
++	 * disable MMU stuff and caches
++	 */
++	mrc p15, 0, r0, c1, c0, 0
++	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
++	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
++	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
++	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
++	mcr p15, 0, r0, c1, c0, 0
++
++init_aipi_start:
++	init_aipi
 +
-+int
-+fpga_abort_fn ( int cookie )
-+{
-+	return cookie;
-+}
++	/* check if sdram has been setup (running within sdram) */
++	cmp pc, #0xa0000000 /* start of first sdram memory space */
++	blo init_clock_start
++	cmp pc, #0xc0000000 /* end of second sdram memory space */
++	blo regular_boot
 +
++	/* running from sdram with full code present -> regular_boot */
++init_clock_start:
++	init_clock
 +
-+int
-+fpga_busy_fn ( int cookie )
-+{
-+	return 1;
-+}
++init_sdram_start:
++	bl setup_sdram_ddr
++
++	/* save state of previous boot (SDRAM is configured)*/
++	BACKUP_TRACE()
++
++	/* nand_boot BOOT_TRACE(1..13) */
++
++	nand_boot
++
++	BOOT_TRACE(14) /* start regular U-Boot */
++
++regular_boot: /* jump to start of next 2kiB block (U-Boot) */
++	ldr r0, =0xfffff800
++	and r0, r0, pc
++	add pc, r0, #0x800
++
++do_wait_op_done:
++	1:
++	ldrh r3, [r12, #NFC_OFFSET_CONFIG2]
++	ands r3, r3, #NFC_CONFIG2_INT
++	beq 1b
++	mov r3, #0x0
++	strh r3, [r12, #NFC_OFFSET_CONFIG2]
++	mov	pc, lr
++
++do_addr_input:
++	mov r9, lr
++	and r3, r3, #0xFF
++	strh r3, [r12, #NFC_OFFSET_FLASH_ADDR]
++	mov r3, #NFC_CONFIG2_FADD
++	strh r3, [r12, #NFC_OFFSET_CONFIG2]
++	bl do_wait_op_done
++	mov pc, r9
++
++Test_And_Copy_Buffer:
++	/* check for bad block (2 bits error in main or spare are)*/
++	BOOT_TRACE(9)
++	ldrh r4, [r12, #NFC_OFFSET_ECC_STATUS_RESULT]
++	ands r4, r4, #(NFC_ECC_STAT_ERROR2|(NFC_ECC_STAT_ERROR2<<NFC_ECC_STAT_ERM_SHFT))
++	bne Skip_Bad_Buffer
++
++	/* check BI byte of the current spare buffer */
++	ldr r4, =IMX_NFC_SPARE_AREA0
++	ldrh r3, [r12, #NFC_OFFSET_BUF_ADDR] /* for the current buffer */
++	orr  r4, r3, lsl #0x04
++
++	/* at bi word offset 4. Fixme position change betwwen 8 and 16 bits bus */
++	ldrh r4, [r4, #0x04]
++	and r4, r4, #0x0FF00 /* has to be 0xFFxx */
++	cmp r4, #0x0FF00
++	bne Skip_Bad_Buffer
++
++Copy_Good_Buffer:
++	/* copying 512 bytes buffer */
++	BOOT_TRACE(10)
++1:  ldmia r0!, {r3-r10}
++	stmia r11!, {r3-r10}
++	cmp r0, r2
++	blo 1b
++	b End_Of_Copy
++
++Skip_Bad_Buffer:
++	BOOT_TRACE(11)
++	/* bad pages do not contain valid data and have to be skip	*/
++	add r0, r0, #0x200
++
++	/* rewind ram addr to start of buffer */
++	ldr r3, =(~0x1FF)
++	and r11, r11, r3
++
++End_Of_Copy:
++	add r2, r2, #0x200
++	add r1, r1, #0x200
++
++	mov	pc, lr
++
++
++setup_sdram_ddr:
 +
-+int
-+fpga_post_fn (int cookie)
-+{
-+       struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+	PRINTF ("%s:%d: FPGA POST ", __FUNCTION__, __LINE__);
++	/* wait for SDRAM/LPDDR ready (SDRAMRDY) */
++	ldr  r0, =ESDMISC
++	ldr  r4, =ESDMISC_SDRAM_RDY
++2:	ldr  r1, [r0]
++	ands r1, r1, r4
++	bpl 2b
 +
-+	imx_gpio_mode (CONFIG_SYS_FPGA_RW | GPIO_PF | GPIO_PUEN);
-+	imx_gpio_mode (CONFIG_SYS_FPGA_CS | GPIO_PF | GPIO_PUEN);
-+	imx_gpio_mode (CONFIG_SYS_FPGA_CLK | GPIO_PF | GPIO_PUEN);
-+	GPIO_SET(CONFIG_SYS_FPGA_PRG);
-+	GPIO_CLEAR(CONFIG_SYS_FPGA_RESET);
-+	imx_gpio_mode (CONFIG_SYS_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+	return cookie;
-+}
++	/* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
++	ldr		r0, =ESDMISC
++	ldr		r4, =CONFIG_SYS_ESDMISC_VAL
++	orr		r1, r4, #ESDMISC_MDDR_DL_RST
++	str		r1, [r0]
 +
-+/*
-+ * Initialize the fpga.  Return 1 on success, 0 on failure.
-+ */
-+int
-+APF27_init_fpga (u_char * buffer, size_t size)
-+{
-+	char *autoload = getenv ("firmware_autoload");
++	/* Hold for more than 200ns */
++	ldr r1, =0x10000
++	1:	subs r1, r1, #0x1
++	bne 1b
 +
-+	int i,lout=0;
++	str		r4, [r0]
 +
-+       fpga_init();
++	writel(ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL)
 +
-+	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
-+		PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
-+		fpga_add (fpga_xilinx, &fpga[i]);
-+	}
++	/* writel(ESDCTL0, CONFIG_SYS_PRECHARGE_CMD) */
++	ldr		r0, =ESDCTL0
++	ldr		r1, =CONFIG_SYS_PRECHARGE_CMD
++	str		r1, [r0]
 +
-+	if ((size >= fpga[0].size) && ( autoload ) && (0 == strcmp(autoload, "1"))) {
-+		if (ctrlc()) {
-+			printf("Firmware download stopped!\n"); 
-+		} else if (FPGA_SUCCESS != fpga_load( 0,(void *)buffer, size )) {
-+			printf("Firmware download failed!\n");
-+		} else {
-+			printf("Firmware successfully programmed\n");
-+			lout = 1;
-+		}
-+	}
-+	return lout;
-+}
++	/* writeb(0xA0001000, any value) */
++	ldr		r1, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
++	ldrb		r2, [r1]
 +
-+#endif /* CONFIG_FPGA */
-Index: u-boot-2010.03/board/armadeus/apf27/fpga.h
++	/* writel(ESDCTL0, CONFIG_SYS_AUTOREFRESH_CMD) */
++	ldr		r1, =CONFIG_SYS_AUTOREFRESH_CMD
++	str		r1, [r0]
++
++	ldr 		r4, =PHYS_SDRAM_1	/* CSD0 base address	*/
++
++	ldr 		r6,=0x7			/* load loop counter	*/
++1:	ldr 		r5,[r4]			/* run auto-refresh cycle to array 0 */
++	subs 		r6,r6,#1		/* decrease counter value */
++	bne 1b
++
++	/* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_SET_MODE_REG_CMD) */
++	ldr		r1, =CONFIG_SYS_SET_MODE_REG_CMD
++	str		r1, [r0]
++
++	/* set standard mode register */
++	ldr		r4, = PHYS_SDRAM_1+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
++	ldrb		r2, [r4]
++
++	/* set extended mode register */
++	ldr		r4, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
++	ldrb		r5, [r4]
++
++	/* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_NORMAL_RW_CMD) */
++	ldr		r1, =CONFIG_SYS_NORMAL_RW_CMD
++	str		r1, [r0]
++
++#if (CONFIG_NR_DRAM_BANKS > 1)
++	/* 2nd sdram */
++	writel(ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL )
++
++	/* writel(ESDCTL1, CONFIG_SYS_PRECHARGE_CMD) */
++	ldr		r0, =ESDCTL1
++	ldr		r1, =CONFIG_SYS_PRECHARGE_CMD
++	str		r1, [r0]
++
++	/* writeb(0xB0001000, any value) */
++	ldr		r1, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
++	ldrb		r2, [r1]
++
++	/* writel(ESDCTL1, CONFIG_SYS_AUTOREFRESH_CMD) */
++	ldr		r1, =CONFIG_SYS_AUTOREFRESH_CMD
++	str		r1, [r0]
++
++	ldr 		r4, =PHYS_SDRAM_2	/* CSD1 base address */
++
++	ldr 		r6,=0x7			/* load loop counter */
++1:	ldr 		r5,[r4]			/* run auto-refresh cycle to array 0 */
++	subs 		r6,r6,#1		/* decrease counter value */
++	bne 1b
++
++	/* writel(ESDCTL1, CONFIG_SYS_SET_MODE_REG_CMD) */
++	ldr		r1, =CONFIG_SYS_SET_MODE_REG_CMD
++	str		r1, [r0]
++
++	/* set standard mode register */
++	ldr		r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
++	ldrb		r2, [r4]
++
++	/* set extended mode register */
++	ldr		r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
++	ldrb		r2, [r4]
++
++	/* writel(ESDCTL1, CONFIG_SYS_NORMAL_RW_CMD) */
++	ldr		r1, =CONFIG_SYS_NORMAL_RW_CMD
++	str		r1, [r0]
++#endif  /* CONFIG_NR_DRAM_BANKS > 1 */
++
++	mov	pc, lr
++
+Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/u-boot.lds
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/board/armadeus/apf27/fpga.h	2011-01-05 18:09:44.000000000 +0100
-@@ -0,0 +1,39 @@
++++ u-boot-2010.03/nand_spl/board/armadeus/apf27/u-boot.lds	2011-01-05 18:09:44.000000000 +0100
+@@ -0,0 +1,37 @@
 +/*
-+ * (C) Copyright 2002-2008
-+ * Eric Jarrige <eri...@ar...>
-+ * Rich Ireland, Enterasys Networks, rir...@en....
-+ * Keith Outwater, kei...@mv....
++ * (C) Copyright 2007
++ * Stefan Roese, DENX Software Engineering, sr...@de....
 + *
 + * See file CREDITS for list of people who contributed to this
 + * project.
@@ -1049,20 +1769,21 @@ Index: u-boot-2010.03/board/armadeus/apf27/fpga.h
 + * along with this program; if not, write to the Free Software
 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 + * MA 02111-1307 USA
-+ *
 + */
-+extern int APF27_init_fpga (u_char * buffer, size_t size);
 +
-+extern int fpga_pre_fn (int cookie);
-+extern int fpga_pgm_fn (int assert_pgm, int flush, int cookie);
-+extern int fpga_cs_fn (int assert_cs, int flush, int cookie);
-+extern int fpga_init_fn (int cookie);
-+extern int fpga_done_fn (int cookie);
-+extern int fpga_clk_fn (int assert_clk, int flush, int cookie);
-+extern int fpga_wr_fn (int assert_write, int flush, int cookie);
-+extern int fpga_rdata_fn ( unsigned char *data, int cookie );
-+extern int fpga_wdata_fn ( unsigned char data, int cookie );
-+extern int fpga_abort_fn (int cookie);
-+extern int fpga_post_fn (int cookie);
-+extern int fpga_busy_fn (int cookie);
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++	. = 0x00000000;
++
++	. = ALIGN(4);
++	.text      :
++	{
++		start.o	(.text)
++		*(.text)
++	}
++}
+1.7.4.4
 
diff --git a/patches/u-boot/2011.12/304-Add-type-for-apf27.patch b/patches/u-boot/2011.12/304-Add-type-for-apf27.patch
deleted file mode 100644
index 29628c7..0000000
--- a/patches/u-boot/2011.12/304-Add-type-for-apf27.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-From bfedc74f6beae4f7bbb5f2ccf0c651a489fe7675 Mon Sep 17 00:00:00 2001
-From: Philippe Reynes <tr...@ya...>
-Date: Wed, 28 Dec 2011 14:26:52 +0100
-Subject: [PATCH 4/6] Add type for apf27
-
----
- arch/arm/include/asm/mach-types.h |    1 +
- 1 files changed, 1 insertions(+), 0 deletions(-)
-
-diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
-index 2d5c3bc..c38a816 100644
---- a/arch/arm/include/asm/mach-types.h
-+++ b/arch/arm/include/asm/mach-types.h
-@@ -286,6 +286,7 @@ extern unsigned int __machine_arch_type;
- #define MACH_TYPE_WBD111               1690
- #define MACH_TYPE_MV2120               1693
- #define MACH_TYPE_MX51_3DS             1696
-+#define MACH_TYPE_APF27                1698
- #define MACH_TYPE_IMX27LITE            1701
- #define MACH_TYPE_USB_A9260            1709
- #define MACH_TYPE_USB_A9263            1710
--- 
-1.7.4.4
-
diff --git a/patches/u-boot/2011.12/310-apf27-nand-spl.patch b/patches/u-boot/2011.12/310-apf27-nand-spl.patch
deleted file mode 100644
index daa8554..0000000
--- a/patches/u-boot/2011.12/310-apf27-nand-spl.patch
+++ /dev/null
@@ -1,721 +0,0 @@
-Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/config.mk
-===================================================================
---- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/nand_spl/board/armadeus/apf27/config.mk	2011-01-05 18:09:44.000000000 +0100
-@@ -0,0 +1,43 @@
-+#
-+# (C) Copyright 2007
-+# Stefan Roese, DENX Software Engineering, sr...@de....
-+#
-+# See file CREDITS for list of people who contributed to this
-+# project.
-+#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; either version 2 of
-+# the License, or (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+# MA 02111-1307 USA
-+#
-+#
-+# This config file is used for compilation of armadeus apf27 board
-+#
-+
-+#
-+# TEXT_BASE for SPL:
-+#
-+#
-+# This config file is used for compilation of armadeus sources
-+#
-+# You might change location of U-Boot in memory by setting right TEXT_BASE.
-+# This allows for example having one copy located at the end of ram and stored
-+# in flash device and later on while developing use other location to test
-+# the code in RAM device only.
-+#
-+
-+TEXT_BASE = 0xa0000000
-+
-+# PAD_TO used to generate a 2kByte binary needed for the combined image
-+# -> PAD_TO = TEXT_BASE + 0x0800
-+PAD_TO	= 0xa0000800
-Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/Makefile
-===================================================================
---- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/nand_spl/board/armadeus/apf27/Makefile	2011-01-05 18:09:44.000000000 +0100
-@@ -0,0 +1,77 @@
-+#
-+# (C) Copyright 2007
-+# Stefan Roese, DENX Software Engineering, sr...@de....
-+#
-+# See file CREDITS for list of people who contributed to this
-+# project.
-+#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; either version 2 of
-+# the License, or (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+# MA 02111-1307 USA
-+#
-+
-+include $(TOPDIR)/config.mk
-+include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-+
-+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-+LDFLAGS	= -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
-+AFLAGS	+= -DCONFIG_NAND_SPL
-+CFLAGS	+= -DCONFIG_NAND_SPL
-+
-+SOBJS	= start.o
-+COBJS	=
-+
-+SRCS	:= $(addprefix $(src),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-+OBJS	:= $(addprefix $(obj),$(SOBJS) $(COBJS))
-+__OBJS	:= $(SOBJS) $(COBJS)
-+LNDIR	:= $(OBJTREE)/nand_spl/board/$(BOARDDIR)
-+
-+nandobj	:= $(OBJTREE)/nand_spl/
-+
-+ALL	= $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
-+	$(nandobj)System.map
-+
-+all:	$(obj).depend $(ALL)
-+
-+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
-+	$(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-+
-+$(nandobj)u-boot-spl.bin:	$(nandobj)u-boot-spl
-+	$(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-+
-+$(nandobj)u-boot-spl:	$(OBJS)
-+	cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
-+		-Map $(nandobj)u-boot-spl.map \
-+		-o $(nandobj)u-boot-spl
-+
-+$(nandobj)System.map:	$(nandobj)u-boot-spl
-+		@$(NM) $< | \
-+		grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
-+		sort > $(nandobj)System.map
-+
-+
-+#########################################################################
-+
-+$(obj)%.o:	%.S
-+	$(CC) $(AFLAGS) -c -o $@ $<
-+
-+$(obj)%.o:	%.c
-+	$(CC) $(CFLAGS) -c -o $@ $<
-+
-+# defines $(obj).depend target
-+include $(SRCTREE)/rules.mk
-+
-+sinclude $(obj).depend
-+
-+#########################################################################
-Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
-===================================================================
---- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S	2011-01-05 18:09:44.000000000 +0100
-@@ -0,0 +1,544 @@
-+/*
-+ *  IMX27 NAND Flash SPL (Secondary Program Loader)
-+ *
-+ *  Copyright (c) 2008  Armadeus Project / eja
-+ *
-+ *  Based on Freescale NAND SPL
-+ *
-+ *  Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-+ *  Copyright (c) 2008	Eric Jarrige <eri...@ar...>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+
-+#include <config.h>
-+#include <version.h>
-+#include <asm/arch/imx-regs.h>
-+
-+/*
-+ * Standard NAND flash commands
-+ */
-+#define NAND_CMD_READ0		0
-+#define NAND_CMD_READ1		1
-+#define NAND_CMD_PAGEPROG	0x10
-+#define NAND_CMD_READOOB	0x50
-+#define NAND_CMD_ERASE1		0x60
-+#define NAND_CMD_STATUS		0x70
-+#define NAND_CMD_STATUS_MULTI	0x71
-+#define NAND_CMD_SEQIN		0x80
-+#define NAND_CMD_READID		0x90
-+#define NAND_CMD_ERASE2		0xd0
-+#define NAND_CMD_RESET		0xff
-+
-+/* Extended commands for large page devices */
-+#define NAND_CMD_READSTART	0x30
-+#define NAND_CMD_CACHEDPROG	0x15
-+
-+/* Status bits */
-+#define NAND_STATUS_FAIL	0x01
-+#define NAND_STATUS_FAIL_N1	0x02
-+#define NAND_STATUS_TRUE_READY	0x20
-+#define NAND_STATUS_READY	0x40
-+#define NAND_STATUS_WP		0x80
-+
-+#define writel(reg, val)		\
-+	ldr		r0,	=reg;	\
-+	ldr		r1,	=val;	\
-+	str		r1,   [r0];
-+
-+	.macro nand_boot
-+
-+#ifdef CONFIG_BOOT_TRACE_REG
-+/*
-+ * If CONFIG_BOOT_TRACE_REG is a SDRAM address then be sure to use the following
-+ * 2 command after SDRAM init
-+ */
-+
-+/* Backup state of previous boot to CONFIG_BOOT_TRACE_REG+4*/
-+#define BACKUP_TRACE()			\
-+	ldr r4, =CONFIG_BOOT_TRACE_REG;	\
-+	ldr r3, [r4];			\
-+	str r3, [r4, #0x04];
-+
-+/* Save a state of boot at CONFIG_BOOT_TRACE_REG */
-+#define BOOT_TRACE(val)		\
-+	ldr r4, =CONFIG_BOOT_TRACE_REG;	\
-+	ldr r3, =val;			\
-+	str r3, [r4];
-+#else
-+#define BACKUP_TRACE()
-+#define BOOT_TRACE(val)
-+#endif
-+
-+nand_boot_setup:
-+
-+	/* Copy SPL image from flash to SDRAM first */
-+	BOOT_TRACE(1)
-+	ldr r0, =IMX_NFC_MAIN_AREA0
-+	add r2, r0, #(IMX_NFC_SPARE_AREA0-IMX_NFC_MAIN_AREA0) //2KB NFC Buff
-+	ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST
-+
-+	BOOT_TRACE(2)
-+1:	ldmia r0!, {r3-r10}
-+	stmia r1!, {r3-r10}
-+	cmp r0, r2
-+	blo 1b
-+
-+
-+
-+	/* Jump to SDRAM */
-+	BOOT_TRACE(3)
-+	ldr r1, =0xFFF
-+	and r0, pc, r1	 /* offset of pc */
-+	ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST
-+	add r1, r1, #0x10
-+	add pc, r0, r1
-+	nop
-+	nop
-+	nop
-+	nop
-+
-+NAND_Copy_Main:
-+	BOOT_TRACE(4)
-+	/* r0: nfc base. Reloaded after each page copying		*/
-+	ldr r0, =IMX_NFC_MAIN_AREA0
-+
-+	/* r1: starting flash addr to be copied. Updated constantly	*/
-+	/* bypass the first preloaded pages				*/
-+	ldr r1, =(IMX_NFC_SPARE_AREA0-IMX_NFC_MAIN_AREA0)
-+
-+	/* r2: end of 1st RAM buf. Doesn't change			*/
-+	ldr r2, =IMX_NFC_MAIN_AREA1
-+
-+	/* r12: NFC register base. Doesn't change			*/
-+	ldr r12, =IMX_NFC_REGS
-+
-+	ldr r11, =CONFIG_SYS_NAND_U_BOOT_DST
-+
-+	/* r13: end of SDRAM address for copying. Doesn't change	*/
-+	add r13, r11, #CONFIG_SYS_NAND_U_BOOT_SIZE
-+
-+	/* r11: starting SDRAM address for copying. Updated constantly	*/
-+	add r11, r11, r1
-+
-+	/* unlock internal buffer					*/
-+	ldr r3, =NFC_CONFIG_UNLOCKED
-+	strh r3, [r12, #NFC_OFFSET_CONFIG]
-+
-+	/* enable ECC and mask interrupts				*/
-+	ldr r3, =(NFC_CONFIG1_ECC_EN | NFC_CONFIG1_INT_MSK)
-+	strh r3, [r12, #NFC_OFFSET_CONFIG1]
-+
-+Nfc_Read_Page:
-+	BOOT_TRACE(5)
-+	/*  send NAND_CMD_READ0 command				*/
-+	ldr r3, =NAND_CMD_READ0;
-+	strh r3, [r12, #NFC_OFFSET_FLASH_CMD]
-+
-+	ldr r3, =NFC_CONFIG2_FCMD
-+	strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+	bl do_wait_op_done
-+
-+	/* send NAND address to read. TODO small page support		*/
-+	BOOT_TRACE(6)
-+	mov r3, r1, lsr #1
-+	bl do_addr_input	   /* 1st addr cycle */
-+
-+	mov r3, r1, lsr #9
-+	and r3, r3, #0x03
-+	bl do_addr_input	   /* 2nd addr cycle */
-+
-+	mov r3, r1, lsr #11
-+	bl do_addr_input	   /* 3rd addr cycle */
-+
-+	mov r3, r1, lsr #19
-+	bl do_addr_input	   /* 4th addr cycle */
-+
-+	/* Small NAND flashs (== 1Gb) support 5 addr cycles		*/
-+	mov r3, r1, lsr #27
-+	bl do_addr_input	   /* 5th addr cycle */
-+
-+	/* send NAND_CMD_READSTART command. TODO small page support	*/
-+	BOOT_TRACE(7)
-+	mov r3, #NAND_CMD_READSTART;
-+	strh r3, [r12, #NFC_OFFSET_FLASH_CMD]
-+	mov r3, #NFC_CONFIG2_FCMD
-+	strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+	bl do_wait_op_done
-+
-+	/* read and copy buf 0						*/
-+	BOOT_TRACE(8)
-+	mov r3, #0
-+	strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
-+
-+	mov r3, #NFC_CONFIG2_FDO_PAGE
-+	strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+	bl do_wait_op_done
-+
-+	bl Test_And_Copy_Buffer
-+
-+	/* read and copy buf 1						*/
-+	mov r3, #1
-+	strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
-+
-+	mov r3, #NFC_CONFIG2_FDO_PAGE
-+	strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+	bl do_wait_op_done
-+
-+	bl Test_And_Copy_Buffer
-+
-+	/* here we should test if 512B page flash and bypass next buffers */
-+	/* read and copy buf 2. TODO small page support		*/
-+	mov r3, #2
-+	strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
-+
-+	mov r3, #NFC_CONFIG2_FDO_PAGE
-+	strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+	bl do_wait_op_done
-+
-+	bl Test_And_Copy_Buffer
-+
-+	/* read and copy buf 3						*/
-+	mov r3, #3
-+	strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
-+
-+	mov r3, #NFC_CONFIG2_FDO_PAGE
-+	strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+	bl do_wait_op_done
-+
-+	bl Test_And_Copy_Buffer
-+
-+	/* is the last page ? */
-+	BOOT_TRACE(12)
-+	cmp r11, r13
-+	bge NAND_Copy_Main_done
-+
-+	/* r0: nfc base. Reloaded after each page copying		*/
-+	ldr r0, =IMX_NFC_MAIN_AREA0
-+	/* r2: end of 1st RAM buf. Doesn't change 			*/
-+	ldr r2, =IMX_NFC_MAIN_AREA1
-+	b Nfc_Read_Page
-+
-+NAND_Copy_Main_done:
-+	BOOT_TRACE(13)
-+	.endm /* nand_boot */
-+
-+	.macro init_aipi
-+	/*
-+	 * setup AIPI1 and AIPI2
-+	 */
-+	writel(AIPI1_PSR0, CONFIG_SYS_AIPI1_PSR0_VAL)
-+	writel(AIPI1_PSR1, CONFIG_SYS_AIPI1_PSR1_VAL)
-+	writel(AIPI2_PSR0, CONFIG_SYS_AIPI2_PSR0_VAL)
-+	writel(AIPI2_PSR1, CONFIG_SYS_AIPI2_PSR1_VAL)
-+
-+	/* Change SDRAM signal strengh */
-+	ldr r0, =GPCR
-+	ldr r1, =CONFIG_SYS_GPCR_VAL
-+	ldr r5, [r0]
-+	orr r5, r5, r1
-+	str r5, [r0]
-+
-+	.endm /* init_aipi */
-+
-+	.macro init_clock
-+	ldr r0, =CSCR
-+	/* disable MPLL/SPLL first */
-+	ldr r1, [r0]
-+	bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
-+	str r1, [r0]
-+
-+ 	/*
-+	 * pll clock initialization predefined in apf27.h
-+	 */
-+	writel(MPCTL0, CONFIG_SYS_MPCTL0_VAL)
-+	writel(SPCTL0, CONFIG_SYS_SPCTL0_VAL)
-+
-+	writel(CSCR, CONFIG_SYS_CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART)
-+
-+	/*
-+	 * add some delay here
-+	 */
-+	mov r1, #0x1000
-+	1:  subs r1, r1, #0x1
-+	bne 1b
-+
-+	/* peripheral clock divider */
-+	writel(PCDR0, CONFIG_SYS_PCDR0_VAL)
-+	writel(PCDR1, CONFIG_SYS_PCDR1_VAL)
-+
-+	/* Configure PCCR0 and PCCR1 */
-+	writel(PCCR0, CONFIG_SYS_PCCR0_VAL)
-+	writel(PCCR1, CONFIG_SYS_PCCR1_VAL)
-+
-+	.endm /* init_clock */
-+
-+/*
-+ *************************************************************************
-+ *
-+ * No jump vector table. Use reset vector as direct entry point.
-+ * Do not support any interrupt event within SPL
-+ *
-+ *************************************************************************
-+ */
-+
-+
-+.globl _start
-+_start:
-+
-+/*
-+ *************************************************************************
-+ *
-+ * Startup Code (reset vector)
-+ *
-+ * do important init only if we don't start from memory!
-+ * setup Memory and board specific bits prior to relocation.
-+ * relocate armboot to ram
-+ * setup stack
-+ *
-+ *************************************************************************
-+ */
-+
-+
-+/*
-+ * the actual reset code
-+ */
-+
-+reset:
-+	/*
-+	 * set the cpu to SVC32 mode
-+	 */
-+	mrs	r0,cpsr
-+	bic	r0,r0,#0x1f
-+	orr	r0,r0,#0xd3
-+	msr	cpsr,r0
-+
-+	/*
-+	 * invalidate I/D cache/TLB and drain write buffer
-+	 */
-+	mov r0, #0
-+	mcr p15, 0, r0, c7, c7, 0	/* invalidate I cache and D cache */
-+	mcr p15, 0, r0, c8, c7, 0	/* invalidate TLBs */
-+	mcr p15, 0, r0, c7, c10, 4   /* Drain the write buffer */
-+
-+	/*
-+	 * disable MMU stuff and caches
-+	 */
-+	mrc p15, 0, r0, c1, c0, 0
-+	bic	r0, r0, #0x00002300	/* clear bits 13, 9:8 (--V- --RS) */
-+	bic	r0, r0, #0x00000087	/* clear bits 7, 2:0 (B--- -CAM) */
-+	orr	r0, r0, #0x00000002	/* set bit 2 (A) Align */
-+	orr	r0, r0, #0x00001000	/* set bit 12 (I) I-Cache */
-+	mcr p15, 0, r0, c1, c0, 0
-+
-+init_aipi_start:
-+	init_aipi
-+
-+	/* check if sdram has been setup (running within sdram) */
-+	cmp pc, #0xa0000000 /* start of first sdram memory space */
-+	blo init_clock_start
-+	cmp pc, #0xc0000000 /* end of second sdram memory space */
-+	blo regular_boot
-+
-+	/* running from sdram with full code present -> regular_boot */
-+init_clock_start:
-+	init_clock
-+
-+init_sdram_start:
-+	bl setup_sdram_ddr
-+
-+	/* save state of previous boot (SDRAM is configured)*/
-+	BACKUP_TRACE()
-+
-+	/* nand_boot BOOT_TRACE(1..13) */
-+
-+	nand_boot
-+
-+	BOOT_TRACE(14) /* start regular U-Boot */
-+
-+regular_boot: /* jump to start of next 2kiB block (U-Boot) */
-+	ldr r0, =0xfffff800
-+	and r0, r0, pc
-+	add pc, r0, #0x800
-+
-+do_wait_op_done:
-+	1:
-+	ldrh r3, [r12, #NFC_OFFSET_CONFIG2]
-+	ands r3, r3, #NFC_CONFIG2_INT
-+	beq 1b
-+	mov r3, #0x0
-+	strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+	mov	pc, lr
-+
-+do_addr_input:
-+	mov r9, lr
-+	and r3, r3, #0xFF
-+	strh r3, [r12, #NFC_OFFSET_FLASH_ADDR]
-+	mov r3, #NFC_CONFIG2_FADD
-+	strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+	bl do_wait_op_done
-+	mov pc, r9
-+
-+Test_And_Copy_Buffer:
-+	/* check for bad block (2 bits error in main or spare are)*/
-+	BOOT_TRACE(9)
-+	ldrh r4, [r12, #NFC_OFFSET_ECC_STATUS_RESULT]
-+	ands r4, r4, #(NFC_ECC_STAT_ERROR2|(NFC_ECC_STAT_ERROR2<<NFC_ECC_STAT_ERM_SHFT))
-+	bne Skip_Bad_Buffer
-+
-+	/* check BI byte of the current spare buffer */
-+	ldr r4, =IMX_NFC_SPARE_AREA0
-+	ldrh r3, [r12, #NFC_OFFSET_BUF_ADDR] /* for the current buffer */
-+	orr  r4, r3, lsl #0x04
-+
-+	/* at bi word offset 4. Fixme position change betwwen 8 and 16 bits bus */
-+	ldrh r4, [r4, #0x04]
-+	and r4, r4, #0x0FF00 /* has to be 0xFFxx */
-+	cmp r4, #0x0FF00
-+	bne Skip_Bad_Buffer
-+
-+Copy_Good_Buffer:
-+	/* copying 512 bytes buffer */
-+	BOOT_TRACE(10)
-+1:  ldmia r0!, {r3-r10}
-+	stmia r11!, {r3-r10}
-+	cmp r0, r2
-+	blo 1b
-+	b End_Of_Copy
-+
-+Skip_Bad_Buffer:
-+	BOOT_TRACE(11)
-+	/* bad pages do not contain valid data and have to be skip	*/
-+	add r0, r0, #0x200
-+
-+	/* rewind ram addr to start of buffer */
-+	ldr r3, =(~0x1FF)
-+	and r11, r11, r3
-+
-+End_Of_Copy:
-+	add r2, r2, #0x200
-+	add r1, r1, #0x200
-+
-+	mov	pc, lr
-+
-+
-+setup_sdram_ddr:
-+
-+	/* wait for SDRAM/LPDDR ready (SDRAMRDY) */
-+	ldr  r0, =ESDMISC
-+	ldr  r4, =ESDMISC_SDRAM_RDY
-+2:	ldr  r1, [r0]
-+	ands r1, r1, r4
-+	bpl 2b
-+
-+	/* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
-+	ldr		r0, =ESDMISC
-+	ldr		r4, =CONFIG_SYS_ESDMISC_VAL
-+	orr		r1, r4, #ESDMISC_MDDR_DL_RST
-+	str		r1, [r0]
-+
-+	/* Hold for more than 200ns */
-+	ldr r1, =0x10000
-+	1:	subs r1, r1, #0x1
-+	bne 1b
-+
-+	str		r4, [r0]
-+
-+	writel(ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL)
-+
-+	/* writel(ESDCTL0, CONFIG_SYS_PRECHARGE_CMD) */
-+	ldr		r0, =ESDCTL0
-+	ldr		r1, =CONFIG_SYS_P...
 
[truncated message content]

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-314-g016e873

[jorasse <jo...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  016e87336b375cd7657a7ccf040d50296577b672 (commit)
      from  1f7876c13221e763807e08db3dd03a5e0f7e2b65 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 016e87336b375cd7657a7ccf040d50296577b672
Author: Eric Jarrige <eri...@ar...>
Date:   Mon May 21 16:39:16 2012 +0200

    [LINUX] apf28dev: add configuration for the second ethernet interface

-----------------------------------------------------------------------

Summary of changes:
 .../armadeus/apf28/apf28-linux-2.6.35.config       |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config b/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
index c83acd8..27ec7e8 100644
--- a/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
+++ b/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
@@ -813,7 +813,7 @@ CONFIG_MII=y
 # CONFIG_KS8851_MLL is not set
 CONFIG_FEC=y
 # CONFIG_FEC_1588 is not set
-# CONFIG_FEC2 is not set
+CONFIG_FEC2=y
 # CONFIG_NETDEV_1000 is not set
 # CONFIG_NETDEV_10000 is not set
 CONFIG_WLAN=y


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-313-g1f7876c

[jorasse <jo...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  1f7876c13221e763807e08db3dd03a5e0f7e2b65 (commit)
      from  5e10423791ebe4eef46ddcde2140857de1f0e5cd (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 1f7876c13221e763807e08db3dd03a5e0f7e2b65
Author: Eric Jarrige <eri...@ar...>
Date:   Mon May 21 16:27:52 2012 +0200

    [LINUX] apf28: Support both ethernet interfaces (eth0 / apf28 and eth1 / apf28dev)

-----------------------------------------------------------------------

Summary of changes:
 .../450-armadeus-add_apf28_module_support.patch    |  313 ++++++++++----------
 ...1-armadeus-add_apf28dev_baseboard_support.patch |  161 ++++++++++-
 2 files changed, 322 insertions(+), 152 deletions(-)

diff --git a/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch b/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch
index 42b7c8a..1940bea 100644
--- a/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch
+++ b/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch
@@ -37,7 +37,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
 +++ linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c	2012-02-03 17:39:56.000000000 +0100
-@@ -0,0 +1,310 @@
+@@ -0,0 +1,323 @@
 +/*
 + * Copyright (C) 2012 Armadeus systems
 + *
@@ -81,203 +81,210 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +
 +#include "mx28_pins.h"
 +#include "device.h"
-+//#include "mx28evk.h"
 +
 +extern void apf28_baseboard_init(void);
 +
 +static struct pin_desc apf28_fixed_pins[] = {
 +	{
-+		.name = "DUART.RX",
-+		.id = PINID_PWM0,
-+		.fun = PIN_FUN3,
++		.name		= "DUART.RX",
++		.id		= PINID_PWM0,
++		.fun		= PIN_FUN3,
 +	},
 +	{
-+		.name = "DUART.TX",
-+		.id = PINID_PWM1,
-+		.fun = PIN_FUN3,
-+	},
-+	{
-+		.name = "ENET0_MDC",
-+		.id = PINID_ENET0_MDC,
-+		.fun = PIN_FUN1,
-+		.strength = PAD_8MA,
-+		.pull = 1,
-+		.pullup = 1,
-+		.voltage = PAD_3_3V,
-+		.drive = 1,
-+	},
-+	{
-+		.name = "ENET0_MDIO",
-+		.id = PINID_ENET0_MDIO,
-+		.fun = PIN_FUN1,
-+		.strength = PAD_8MA,
-+		.pull = 1,
-+		.pullup = 1,
-+		.voltage = PAD_3_3V,
-+		.drive = 1,
-+	},
-+	{
-+		.name = "ENET0_RX_EN",
-+		.id = PINID_ENET0_RX_EN,
-+		.fun = PIN_FUN1,
-+		.strength = PAD_8MA,
-+		.pull = 1,
-+		.pullup = 1,
-+		.voltage = PAD_3_3V,
-+		.drive = 1,
-+	},
-+	{
-+		.name = "ENET0_RXD0",
-+		.id = PINID_ENET0_RXD0,
-+		.fun = PIN_FUN1,
-+		.strength = PAD_8MA,
-+		.pull = 1,
-+		.pullup = 1,
-+		.voltage = PAD_3_3V,
-+		.drive = 1,
++		.name		= "DUART.TX",
++		.id		= PINID_PWM1,
++		.fun		= PIN_FUN3,
 +	},
++};
++
++static struct pin_desc apf28_eth_pins[] = {
++#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\
++	|| defined(CONFIG_FEC_L2SWITCH)
 +	{
-+		.name = "ENET0_RXD1",
-+		.id = PINID_ENET0_RXD1,
-+		.fun = PIN_FUN1,
-+		.strength = PAD_8MA,
-+		.pull = 1,
-+		.pullup = 1,
-+		.voltage = PAD_3_3V,
-+		.drive = 1,
++		.name		= "ENET0_MDC",
++		.id		= PINID_ENET0_MDC,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_8MA,
++		.pull		= 1,
++		.pullup		= 1,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
 +	},
 +	{
-+		.name = "ENET0_TX_EN",
-+		.id = PINID_ENET0_TX_EN,
-+		.fun = PIN_FUN1,
-+		.strength = PAD_8MA,
-+		.pull = 1,
-+		.pullup = 1,
-+		.voltage = PAD_3_3V,
-+		.drive = 1,
++		.name		= "ENET0_MDIO",
++		.id		= PINID_ENET0_MDIO,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_8MA,
++		.pull		= 1,
++		.pullup		= 1,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
 +	},
 +	{
-+		.name = "ENET0_TXD0",
-+		.id = PINID_ENET0_TXD0,
-+		.fun = PIN_FUN1,
-+		.strength = PAD_8MA,
-+		.pull = 1,
-+		.pullup = 1,
-+		.voltage = PAD_3_3V,
-+		.drive = 1,
++		.name		= "ENET0_RX_EN",
++		.id		= PINID_ENET0_RX_EN,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_8MA,
++		.pull		= 1,
++		.pullup		= 1,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
 +	},
 +	{
-+		.name = "ENET0_TXD1",
-+		.id = PINID_ENET0_TXD1,
-+		.fun = PIN_FUN1,
-+		.strength = PAD_8MA,
-+		.pull = 1,
-+		.pullup = 1,
-+		.voltage = PAD_3_3V,
-+		.drive = 1,
++		.name		= "ENET0_RXD0",
++		.id		= PINID_ENET0_RXD0,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_8MA,
++		.pull		= 1,
++		.pullup		= 1,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
 +	},
 +	{
-+		.name = "ENET1_RX_EN",
-+		.id = PINID_ENET0_CRS,
-+		.fun = PIN_FUN2,
-+		.strength = PAD_8MA,
-+		.pull = 1,
-+		.pullup = 1,
-+		.voltage = PAD_3_3V,
-+		.drive = 1,
++		.name		= "ENET0_RXD1",
++		.id		= PINID_ENET0_RXD1,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_8MA,
++		.pull		= 1,
++		.pullup		= 1,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
 +	},
 +	{
-+		.name = "ENET1_RXD0",
-+		.id = PINID_ENET0_RXD2,
-+		.fun = PIN_FUN2,
-+		.strength = PAD_8MA,
-+		.pull = 1,
-+		.pullup = 1,
-+		.voltage = PAD_3_3V,
-+		.drive = 1,
++		.name		= "ENET0_TX_EN",
++		.id		= PINID_ENET0_TX_EN,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_8MA,
++		.pull		= 1,
++		.pullup		= 1,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
 +	},
 +	{
-+		.name = "ENET1_RXD1",
-+		.id = PINID_ENET0_RXD3,
-+		.fun = PIN_FUN2,
-+		.strength = PAD_8MA,
-+		.pull = 1,
-+		.pullup = 1,
-+		.voltage = PAD_3_3V,
-+		.drive = 1,
++		.name		= "ENET0_TXD0",
++		.id		= PINID_ENET0_TXD0,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_8MA,
++		.pull		= 1,
++		.pullup		= 1,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
 +	},
 +	{
-+		.name = "ENET1_TX_EN",
-+		.id = PINID_ENET0_COL,
-+		.fun = PIN_FUN2,
-+		.strength = PAD_8MA,
-+		.pull = 1,
-+		.pullup = 1,
-+		.voltage = PAD_3_3V,
-+		.drive = 1,
++		.name		= "ENET0_TXD1",
++		.id		= PINID_ENET0_TXD1,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_8MA,
++		.pull		= 1,
++		.pullup		= 1,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
 +	},
 +	{
-+		.name = "ENET1_TXD0",
-+		.id = PINID_ENET0_TXD2,
-+		.fun = PIN_FUN2,
-+		.strength = PAD_8MA,
-+		.pull = 1,
-+		.pullup = 1,
-+		.voltage = PAD_3_3V,
-+		.drive = 1,
++		.name		= "ENET_CLK",
++		.id		= PINID_ENET_CLK,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_8MA,
++		.pull		= 1,
++		.pullup		= 1,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
 +	},
 +	{
-+		.name = "ENET1_TXD1",
-+		.id = PINID_ENET0_TXD3,
-+		.fun = PIN_FUN2,
-+		.strength = PAD_8MA,
-+		.pull = 1,
-+		.pullup = 1,
-+		.voltage = PAD_3_3V,
-+		.drive = 1,
++		.name		= "PHY0_RESET",
++		.id		= PINID_ENET0_RX_CLK,
++		.fun		= PIN_GPIO,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= 1,
++		.pull		= 0,
++		.output		= 1,
++		.data		= 1,
 +	},
 +	{
-+		.name = "ENET_CLK",
-+		.id = PINID_ENET_CLK,
-+		.fun = PIN_FUN1,
-+		.strength = PAD_8MA,
-+		.pull = 1,
-+		.pullup = 1,
-+		.voltage = PAD_3_3V,
-+		.drive = 1,
++		.name		= "ETH0_INT",
++		.id		= PINID_ENET0_TX_CLK,
++		.fun		= PIN_GPIO,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= 1,
++		.pull		= 0,
++		.output		= 0,
 +	},
++#endif /* defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) */
 +};
 +
-+/* used by device.c (mx28evk makes it a bootcmd option) */
-+int enable_gpmi = 1;
-+
-+/* another Freescale hack: */
-+int mx28evk_enet_gpio_init(void)
++int __inline__ apf28_enet0_gpio_init(void)
 +{
 +	/* reset phy */
-+	gpio_request(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), "PHY_RESET");
 +	gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 0);
 +
-+	/*
-+	 * Before timer bug fix(set wrong match value of timer),
-+	 * mdelay(10) delay 50ms actually.
-+	 * So change delay to 50ms after timer issue fix.
-+	 */
-+	mdelay(50);
++	udelay(100);
 +	gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 1);
 +
 +	return 0;
 +}
 +
++void __inline__ apf28_enet0_io_lowerpower_enter(void)
++{
++	int i;
++	for (i = 0; i < ARRAY_SIZE(apf28_eth_pins); i++) {
++		mxs_release_pin(apf28_eth_pins[i].id,
++			apf28_eth_pins[i].name);
++		gpio_request(MXS_PIN_TO_GPIO(apf28_eth_pins[i].id),
++			apf28_eth_pins[i].name);
++		gpio_direction_output(
++			MXS_PIN_TO_GPIO(apf28_eth_pins[i].id), 0);
++	}
++}
++
++void __inline__ apf28_enet0_io_lowerpower_exit(void)
++{
++	int i;
++	for (i = 0; i < ARRAY_SIZE(apf28_eth_pins); i++) {
++		gpio_free(MXS_PIN_TO_GPIO(apf28_eth_pins[i].id));
++		if (apf28_eth_pins[i].fun != PIN_GPIO)
++			mxs_request_pin(apf28_eth_pins[i].id,
++				apf28_eth_pins[i].fun,
++				apf28_eth_pins[i].name);
++		else {
++			gpio_request(MXS_PIN_TO_GPIO(apf28_eth_pins[i].id),
++				apf28_eth_pins[i].name);
++			if (apf28_eth_pins[i].output)
++				gpio_direction_output(
++					MXS_PIN_TO_GPIO(apf28_eth_pins[i].id),
++					apf28_eth_pins[i].data);
++			else
++				gpio_direction_input(
++					MXS_PIN_TO_GPIO(apf28_eth_pins[i].id));
++		}
++	}
++}
++
++#if !defined(CONFIG_FEC2) && !defined(CONFIG_FEC2_MODULE)\
++	&& !defined(CONFIG_FEC_L2SWITCH)
++int mx28evk_enet_gpio_init(void)
++{
++	apf28_enet0_gpio_init();
++	return 0;
++}
++
 +void mx28evk_enet_io_lowerpower_enter(void)
 +{
-+	printk("--- %s not implemented (yet)\n", __func__);
++	apf28_enet0_io_lowerpower_enter();
 +}
 +
 +void mx28evk_enet_io_lowerpower_exit(void)
 +{
-+	printk("--- %s not implemented (yet)\n", __func__);
++	apf28_enet0_io_lowerpower_exit();
 +}
++#endif
++
++/* used by device.c (mx28evk makes it a bootcmd option) */
++int enable_gpmi = 1;
++
 +
 +static void __init fixup_board(struct machine_desc *desc, struct tag *tags,
 +			       char **cmdline, struct meminfo *mi)
@@ -330,6 +337,12 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +
 +	mx28_gpio_init();
 +	apf28_init_pin_group(apf28_fixed_pins, ARRAY_SIZE(apf28_fixed_pins));
++
++#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\
++	|| defined(CONFIG_FEC_L2SWITCH)
++	apf28_init_pin_group(apf28_eth_pins, ARRAY_SIZE(apf28_eth_pins));
++#endif /* defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) */
++
 +	mx28_device_init();
 +	apf28_device_init();
 +
diff --git a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
index 45e56cb..233ac93 100644
--- a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
+++ b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
@@ -45,7 +45,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
 +++ linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c	2012-02-15 15:51:09.000000000 +0100
-@@ -0,0 +1,381 @@
+@@ -0,0 +1,539 @@
 +/*
 + * Copyright (C) 2012 Armadeus systems
 + *
@@ -72,6 +72,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +#include <linux/io.h>
 +#include <linux/err.h>
 +#include <linux/clk.h>
++#include <linux/delay.h>
 +#include <linux/gpio_keys.h>
 +#include <linux/input.h>
 +#include <linux/leds.h>
@@ -354,6 +355,95 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +	},
 +};
 +
++#if defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE)\
++	|| defined(CONFIG_FEC_L2SWITCH)
++static struct pin_desc apf28dev_eth_pins[] = {
++	{
++		.name		= "ENET1_RX_EN",
++		.id		= PINID_ENET0_CRS,
++		.fun		= PIN_FUN2,
++		.strength	= PAD_8MA,
++		.pull		= 1,
++		.pullup		= 1,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
++	},
++	{
++		.name		= "ENET1_RXD0",
++		.id		= PINID_ENET0_RXD2,
++		.fun		= PIN_FUN2,
++		.strength	= PAD_8MA,
++		.pull		= 1,
++		.pullup		= 1,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
++	},
++	{
++		.name		= "ENET1_RXD1",
++		.id		= PINID_ENET0_RXD3,
++		.fun		= PIN_FUN2,
++		.strength	= PAD_8MA,
++		.pull		= 1,
++		.pullup		= 1,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
++	},
++	{
++		.name		= "ENET1_TX_EN",
++		.id		= PINID_ENET0_COL,
++		.fun		= PIN_FUN2,
++		.strength	= PAD_8MA,
++		.pull		= 1,
++		.pullup		= 1,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
++	},
++	{
++		.name		= "ENET1_TXD0",
++		.id		= PINID_ENET0_TXD2,
++		.fun		= PIN_FUN2,
++		.strength	= PAD_8MA,
++		.pull		= 1,
++		.pullup		= 1,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
++	},
++	{
++		.name		= "ENET1_TXD1",
++		.id		= PINID_ENET0_TXD3,
++		.fun		= PIN_FUN2,
++		.strength	= PAD_8MA,
++		.pull		= 1,
++		.pullup		= 1,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
++	},
++	{
++		.name		= "PHY1_RESET",
++		.id		= PINID_LCD_HSYNC,
++		.fun		= PIN_GPIO,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= 1,
++		.pull		= 0,
++		.output		= 1,
++		.data		= 1,
++	},
++	{
++		.name		= "ETH1_INT",
++		.id		= PINID_LCD_VSYNC,
++		.fun		= PIN_GPIO,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= 1,
++		.pull		= 0,
++		.output		= 0,
++	},
++};
++#endif /* defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE).. */
++
 +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 +static struct gpio_keys_button apf28dev_gpio_keys[] = {
 +	{
@@ -412,6 +502,68 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +#endif
 +};
 +
++#if defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE)\
++	|| defined(CONFIG_FEC_L2SWITCH)
++extern int apf28_enet0_gpio_init(void);
++extern void apf28_enet0_io_lowerpower_enter(void);
++extern void apf28_enet0_io_lowerpower_exit(void);
++
++int mx28evk_enet_gpio_init(void)
++{
++	/* reset phy */
++	apf28_enet0_gpio_init();
++
++	gpio_direction_output(MXS_PIN_TO_GPIO(PINID_LCD_HSYNC), 0);
++
++	udelay(100);
++	gpio_direction_output(MXS_PIN_TO_GPIO(PINID_LCD_HSYNC), 1);
++
++	return 0;
++}
++
++void mx28evk_enet_io_lowerpower_enter(void)
++{
++	int i;
++
++	apf28_enet0_io_lowerpower_enter();
++
++	for (i = 0; i < ARRAY_SIZE(apf28dev_eth_pins); i++) {
++		mxs_release_pin(apf28dev_eth_pins[i].id,
++			apf28dev_eth_pins[i].name);
++		gpio_request(MXS_PIN_TO_GPIO(apf28dev_eth_pins[i].id),
++			apf28dev_eth_pins[i].name);
++		gpio_direction_output(
++			MXS_PIN_TO_GPIO(apf28dev_eth_pins[i].id), 0);
++	}
++}
++
++void mx28evk_enet_io_lowerpower_exit(void)
++{
++	int i;
++
++	apf28_enet0_io_lowerpower_exit();
++
++	for (i = 0; i < ARRAY_SIZE(apf28dev_eth_pins); i++) {
++		gpio_free(MXS_PIN_TO_GPIO(apf28dev_eth_pins[i].id));
++		if (apf28dev_eth_pins[i].fun != PIN_GPIO)
++			mxs_request_pin(apf28dev_eth_pins[i].id,
++				apf28dev_eth_pins[i].fun,
++				apf28dev_eth_pins[i].name);
++		else {
++			gpio_request(MXS_PIN_TO_GPIO(apf28dev_eth_pins[i].id),
++				apf28dev_eth_pins[i].name);
++			if (apf28dev_eth_pins[i].output)
++				gpio_direction_output(
++					MXS_PIN_TO_GPIO(apf28dev_eth_pins[i].id),
++					apf28dev_eth_pins[i].data);
++			else
++				gpio_direction_input(
++					MXS_PIN_TO_GPIO(apf28dev_eth_pins[i].id));
++		}
++	}
++}
++#endif /* defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE).. */
++
 +static void __init apf28dev_device_init(void)
 +{
 +	/* Add apf28dev special code */
@@ -425,9 +577,14 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +	printk("--- apf28_baseboard_init %d\n", MXS_PIN_TO_GPIO(PINID_PWM3));
 +
 +	apf28_init_pin_group(apf28dev_fixed_pins, ARRAY_SIZE(apf28dev_fixed_pins));
++
++#if defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE)\
++	|| defined(CONFIG_FEC_L2SWITCH)
++	apf28_init_pin_group(apf28dev_eth_pins, ARRAY_SIZE(apf28dev_eth_pins));
++#endif /* defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE).. */
++
 +	apf28dev_device_init();
 +}
-+
 Index: linux-2.6.35.3/drivers/video/mxs/Kconfig
 ===================================================================
 --- linux-2.6.35.3.orig/drivers/video/mxs/Kconfig	2012-02-15 14:42:20.000000000 +0100


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-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-312-g5e10423

[jorasse <jo...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  5e10423791ebe4eef46ddcde2140857de1f0e5cd (commit)
      from  1960e430c13619b09305107c0a1e391f89880c57 (commit)

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- Log -----------------------------------------------------------------
commit 5e10423791ebe4eef46ddcde2140857de1f0e5cd
Author: Eric Jarrige <eri...@ar...>
Date:   Mon May 21 00:23:29 2012 +0200

    [LINUX] apf28: disable automatic battery charger to be safe - the type of battery should be validated with the CPU module first

-----------------------------------------------------------------------

Summary of changes:
 .../armadeus/apf28/apf28-linux-2.6.35.config       |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config b/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
index c2b5ba1..c83acd8 100644
--- a/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
+++ b/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
@@ -1136,7 +1136,7 @@ CONFIG_POWER_SUPPLY=y
 # CONFIG_BATTERY_DS2782 is not set
 # CONFIG_BATTERY_BQ27x00 is not set
 # CONFIG_BATTERY_MAX17040 is not set
-CONFIG_BATTERY_MXS=y
+CONFIG_BATTERY_MXS=m
 # CONFIG_MXS_VBUS_CURRENT_DRAW is not set
 # CONFIG_BATTERY_DS2438 is not set
 # CONFIG_HWMON is not set


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-311-g1960e43

[jorasse <jo...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  1960e430c13619b09305107c0a1e391f89880c57 (commit)
      from  4bad4aa07b100eddef973d8e3ba2c0168d1bbf0f (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 1960e430c13619b09305107c0a1e391f89880c57
Author: Eric Jarrige <eri...@ar...>
Date:   Mon May 21 00:10:00 2012 +0200

    [UBOOT] apf51: fix FPGA autoload issue on boot

-----------------------------------------------------------------------

Summary of changes:
 patches/u-boot/2011.12/401-apf51.patch |   49 ++++++++-----------------------
 1 files changed, 13 insertions(+), 36 deletions(-)

diff --git a/patches/u-boot/2011.12/401-apf51.patch b/patches/u-boot/2011.12/401-apf51.patch
index 75036b8..b752760 100644
--- a/patches/u-boot/2011.12/401-apf51.patch
+++ b/patches/u-boot/2011.12/401-apf51.patch
@@ -2,7 +2,7 @@ Index: u-boot-2011.12/board/armadeus/apf51/apf51.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
 +++ u-boot-custom/board/armadeus/apf51/apf51.c	2012-01-12 17:19:58.434303119 +0100
-@@ -0,0 +1,1244 @@
+@@ -0,0 +1,1221 @@
 +/*
 + * (C) Copyright 2010-2012 Eric Jarrige, Armadeus Project
 + *
@@ -39,6 +39,7 @@ Index: u-boot-2011.12/board/armadeus/apf51/apf51.c
 +#include <asm/gpio.h>
 +#include <asm/errno.h>
 +#include <i2c.h>
++#include <jffs2/jffs2.h>
 +#include <asm/arch/mxc_nand.h>
 +#include "fpga.h"
 +#include <nand.h>
@@ -47,31 +48,6 @@ Index: u-boot-2011.12/board/armadeus/apf51/apf51.c
 +
 +unsigned long boot_verb = 0;
 +
-+static int read_firmware(size_t offset, size_t end, u_char * buf)
-+{
-+	size_t amount_loaded = 0;
-+	size_t blocksize;
-+
-+	u_char *char_ptr;
-+
-+	blocksize = nand_info[0].erasesize;
-+
-+	while (offset < end) {
-+		if (nand_block_isbad(&nand_info[0], offset)) {
-+			offset += blocksize;
-+		} else {
-+			char_ptr = &buf[amount_loaded];
-+			if (nand_read
-+			    (&nand_info[0], offset, &blocksize, char_ptr))
-+				return 1;
-+			offset += blocksize;
-+			amount_loaded += blocksize;
-+		}
-+	}
-+
-+	return amount_loaded;
-+}
-+
 +u32 get_board_rev(void)
 +{
 +
@@ -961,24 +937,25 @@ Index: u-boot-2011.12/board/armadeus/apf51/apf51.c
 +	char *s;
 +	u_char *firmware_buffer =
 +	    (u_char *) (CONFIG_SYS_LOAD_ADDR + CONFIG_SYS_MONITOR_LEN);
-+	size_t end = 0;
 +	size_t size = 0;
-+	size_t offset = -1;
 +	char *autoload = getenv("firmware_autoload");
++	u8 pnum;
++	struct mtd_device *dev;
++	struct part_info *part;
 +
 +#if defined(CONFIG_FPGA)
 +	/* init and download fpga */
 +	if ((autoload) && (0 == strcmp(autoload, "1"))) {
-+		if ((s = getenv("firmware_offset")) != NULL) {
-+			offset = simple_strtoul(s, NULL, 16);
-+		}
-+		if ((s = getenv("firmware_len")) != NULL) {
-+			end = offset + simple_strtoul(s, NULL, 16);
++		if (mtdparts_init() == 0)
++		if (find_dev_and_part("firmware", &dev, &pnum, &part) == 0) {
++			size = part->size;
++			if (nand_read_skip_bad(&nand_info[0], part->offset,
++				&size, firmware_buffer))
++				size = 0;
 +		}
 +		if (ctrlc()) {
-+			printf("Firmware download stopped!\n"); 
-+		} else if ((-1 != offset) && (offset != end)) {
-+			size = read_firmware(offset, end, firmware_buffer);
++			printf("Firmware download stopped!\n");
++			size = 0;
 +		}
 +	}
 +	APF51_init_fpga(firmware_buffer, size);


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-310-g4bad4aa

[jorasse <jo...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  4bad4aa07b100eddef973d8e3ba2c0168d1bbf0f (commit)
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- Log -----------------------------------------------------------------
commit 4bad4aa07b100eddef973d8e3ba2c0168d1bbf0f
Author: Eric Jarrige <eri...@ar...>
Date:   Sun May 20 23:41:45 2012 +0200

    [UBOOT] apf9328: Refactor FPGA autoload feature

-----------------------------------------------------------------------

Summary of changes:
 patches/u-boot/2011.12/103-apf9328.patch |   26 +++++++++++++++++---------
 1 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/patches/u-boot/2011.12/103-apf9328.patch b/patches/u-boot/2011.12/103-apf9328.patch
index 37cd173..c5ca405 100644
--- a/patches/u-boot/2011.12/103-apf9328.patch
+++ b/patches/u-boot/2011.12/103-apf9328.patch
@@ -197,7 +197,7 @@ Index: u-boot-custom/board/armadeus/apf9328/apf9328fpga.c
 ===================================================================
 --- /dev/null
 +++ u-boot-custom/board/armadeus/apf9328/apf9328fpga.c
-@@ -0,0 +1,93 @@
+@@ -0,0 +1,101 @@
 +/*
 + * (C) Copyright 2005-2011
 + * Nicolas Colombin <th...@us...>
@@ -230,6 +230,7 @@ Index: u-boot-custom/board/armadeus/apf9328/apf9328fpga.c
 +#include <common.h>
 +#include <spartan3.h>
 +#include <command.h>
++#include <jffs2/jffs2.h>
 +#include <asm/arch/imx-regs.h>
 +#include <asm/io.h>
 +#include "apf9328fpga.h"
@@ -265,6 +266,9 @@ Index: u-boot-custom/board/armadeus/apf9328/apf9328fpga.c
 +{
 +	char *autoload = getenv("firmware_autoload");
 +	int i, lout = 1;
++	u8 pnum;
++	struct mtd_device *dev;
++	struct part_info *part;
 +
 +	debug("%s:%d: Initialize FPGA interface (relocation offset= 0x%.8lx)\n",
 +		__func__, __LINE__, gd->reloc_off);
@@ -277,14 +281,18 @@ Index: u-boot-custom/board/armadeus/apf9328/apf9328fpga.c
 +	}
 +
 +	if ((autoload) && (0 == strcmp(autoload, "1"))) {
-+		if (ctrlc()) {
-+			printf("Firmware download stopped!\n"); 
-+			lout = 0;
-+		} else if (FPGA_SUCCESS != fpga_load(0,
-+						(void *)CONFIG_FIRMWARE_ADDR,
-+						(size_t) CONFIG_FIRMWARE_LEN)) {
-+			lout = 0;
-+			printf("Firmware not loaded!\n");
++		if (mtdparts_init() == 0)
++		if (find_dev_and_part("firmware", &dev, &pnum, &part) == 0)
++		{
++			if (ctrlc()) {
++				printf("Firmware download stopped!\n");
++				lout = 0;
++			} else if (FPGA_SUCCESS != fpga_load(0,
++							(void *)part->offset,
++							(size_t)part->size)) {
++				lout = 0;
++				printf("Firmware not loaded!\n");
++			}
 +		}
 +	}
 +	return lout;


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-309-gd2ed37e

[jorasse <jo...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  d2ed37ed5125e32f4e0241ee0a27cb7442e18a6c (commit)
      from  c99eb077701053abbdd77d921bf3e4930c7918e5 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit d2ed37ed5125e32f4e0241ee0a27cb7442e18a6c
Author: Eric Jarrige <eri...@ar...>
Date:   Sun May 20 23:12:56 2012 +0200

    [UBOOT] apf27: fix FPGA autoload issue on boot

-----------------------------------------------------------------------

Summary of changes:
 ...-Add-support-for-the-armadeus-apf27-board.patch |   49 +++++--------------
 1 files changed, 13 insertions(+), 36 deletions(-)

diff --git a/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch b/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
index ba99f40..a8cde15 100644
--- a/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
+++ b/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
@@ -79,7 +79,7 @@ new file mode 100644
 index 0000000..e08b7a2
 --- /dev/null
 +++ b/board/armadeus/apf27/apf27.c
-@@ -0,0 +1,225 @@
+@@ -0,0 +1,202 @@
 +/*
 + * Copyright (C) 2007 Sascha Hauer, Pengutronix
 + * Copyright (C) 2008,2009 Eric Jarrige <jo...@us...>
@@ -104,37 +104,14 @@ index 0000000..e08b7a2
 +#include <common.h>
 +#include "crc.h"
 +#include "fpga.h"
++#include <jffs2/jffs2.h>
 +#include <nand.h>
++#include <netdev.h>
 +#include <asm/arch/imx-regs.h>
 +#include <asm/errno.h>
 +
 +DECLARE_GLOBAL_DATA_PTR;
 +
-+static int read_firmware (size_t offset, size_t end, u_char * buf)
-+{
-+	size_t amount_loaded = 0;
-+	size_t blocksize;
-+
-+	u_char *char_ptr;
-+
-+	blocksize = nand_info[0].erasesize;
-+
-+	while (offset < end) {
-+		if (nand_block_isbad(&nand_info[0], offset)) {
-+			offset += blocksize;
-+		} else {
-+			char_ptr = &buf[amount_loaded];
-+			if (nand_read(&nand_info[0], offset, &blocksize, char_ptr))
-+				return 1;
-+			offset += blocksize;
-+			amount_loaded += blocksize;
-+		}
-+	}
-+
-+	return amount_loaded;
-+}
-+
-+
 +static int apf27_devices_init(void)
 +{
 +	int i;
@@ -215,22 +192,22 @@ index 0000000..e08b7a2
 +{
 +	char *s;
 +	u_char * firmware_buffer = (u_char *)(CONFIG_SYS_LOAD_ADDR + CONFIG_SYS_MONITOR_LEN);
-+	size_t end	= 0;
 +	size_t size	= 0;
 +	size_t offset	= -1;
-+ 	char *autoload = getenv ("firmware_autoload");
++	char *autoload = getenv ("firmware_autoload");
++	u8 pnum;
++	struct mtd_device *dev;
++	struct part_info *part;
 +
 +#if defined(CONFIG_FPGA)
 +	/* init and download fpga */
 +	if (( autoload ) && (0 == strcmp(autoload, "1"))) {
-+		if ((s = getenv("firmware_offset")) != NULL) {
-+			offset = simple_strtoul(s, NULL, 16);
-+		}
-+		if ((s = getenv("firmware_len")) != NULL) {
-+			end = offset + simple_strtoul(s, NULL, 16);
-+		}
-+		if ((-1 != offset) && (offset != end)) {
-+		    size = read_firmware (offset, end, firmware_buffer);
++		if (mtdparts_init() == 0)
++		if (find_dev_and_part("firmware", &dev, &pnum, &part) == 0) {
++			size = part->size;
++			if (nand_read_skip_bad(&nand_info[0], part->offset,
++				&size, firmware_buffer))
++				size = 0;
 +		}
 +	}
 +	APF27_init_fpga (firmware_buffer, size);


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-308-gc99eb07

[jorasse <jo...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  c99eb077701053abbdd77d921bf3e4930c7918e5 (commit)
      from  3f44dd9b60a3ee5a51cd83d6307ff21fa23a1d42 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit c99eb077701053abbdd77d921bf3e4930c7918e5
Author: Eric Jarrige <eri...@ar...>
Date:   Mon May 14 17:40:34 2012 +0200

    [LINUX] Update LED naming convention for developement boards: devicename=apfdev colour=green function=user

-----------------------------------------------------------------------

Summary of changes:
 .../2.6.29/281-apf27-armadeus-add_apf27.c.patch    |    2 +-
 ...1-armadeus-add_apf28dev_baseboard_support.patch |    3 ++-
 .../2.6.38/281-apf27-armadeus-add_apf27.c.patch    |    2 +-
 .../408-armadeus-add_apf51-dev_baseboard.patch     |    2 +-
 4 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/patches/linux/2.6.29/281-apf27-armadeus-add_apf27.c.patch b/patches/linux/2.6.29/281-apf27-armadeus-add_apf27.c.patch
index cbe0193..be2112a 100644
--- a/patches/linux/2.6.29/281-apf27-armadeus-add_apf27.c.patch
+++ b/patches/linux/2.6.29/281-apf27-armadeus-add_apf27.c.patch
@@ -901,7 +901,7 @@ Index: linux-2.6.29.6/arch/arm/mach-mx2/apf27-dev.c
 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
 +static struct gpio_led apf27dev_led[] = {
 +	{
-+		.name = "apf27dev:green:led",
++		.name = "apfdev:green:user",
 +		.default_trigger = "heartbeat",
 +		.gpio = (GPIO_PORTF | 14),
 +		.active_low = 1,
diff --git a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
index 6871627..45e56cb 100644
--- a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
+++ b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
@@ -382,9 +382,10 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
 +static struct gpio_led apf28dev_led[] = {
 +	{
-+		.name = "apf28dev:green:led",
++		.name = "apfdev:green:user",
 +		.default_trigger = "heartbeat",
 +		.gpio = MXS_PIN_TO_GPIO(PINID_GPMI_RDY1),
++		.active_low = 0,
 +	},
 +};
 +
diff --git a/patches/linux/2.6.38/281-apf27-armadeus-add_apf27.c.patch b/patches/linux/2.6.38/281-apf27-armadeus-add_apf27.c.patch
index 01e4d25..8847abe 100644
--- a/patches/linux/2.6.38/281-apf27-armadeus-add_apf27.c.patch
+++ b/patches/linux/2.6.38/281-apf27-armadeus-add_apf27.c.patch
@@ -880,7 +880,7 @@ Index: linux-2.6.38.1/arch/arm/mach-imx/apf27-dev.c
 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
 +static struct gpio_led apf27dev_led[] = {
 +	{
-+		.name = "apf27dev:green:led",
++		.name = "apfdev:green:user",
 +		.default_trigger = "heartbeat",
 +		.gpio = (GPIO_PORTF | 14),
 +		.active_low = 1,
diff --git a/patches/linux/2.6.38/408-armadeus-add_apf51-dev_baseboard.patch b/patches/linux/2.6.38/408-armadeus-add_apf51-dev_baseboard.patch
index 714cc68..50ac23d 100644
--- a/patches/linux/2.6.38/408-armadeus-add_apf51-dev_baseboard.patch
+++ b/patches/linux/2.6.38/408-armadeus-add_apf51-dev_baseboard.patch
@@ -415,7 +415,7 @@ Index: linux-2.6.38.8/arch/arm/mach-mx5/apf51dev-baseboard.c
 +#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
 +static struct gpio_led apf51dev_led[] = {
 +	{
-+		.name = "apf51dev:green:led",
++		.name = "apfdev:green:user",
 +		.default_trigger = "heartbeat",
 +		.gpio = (GPIO_PORTA | 2),
 +		.active_low = 0,


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-307-g3f44dd9

[jorasse <jo...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  3f44dd9b60a3ee5a51cd83d6307ff21fa23a1d42 (commit)
      from  caf0603970b10ef962330ec9d7f99cec19d8fd56 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 3f44dd9b60a3ee5a51cd83d6307ff21fa23a1d42
Author: Eric Jarrige <eri...@ar...>
Date:   Sun May 13 00:53:32 2012 +0200

    [LINUX] 2.6.38: Add gpio_key and gpio_led structures to support APF27 board user LED and SWITCH

-----------------------------------------------------------------------

Summary of changes:
 .../2.6.38/281-apf27-armadeus-add_apf27.c.patch    |   60 +++++++++++++++++++-
 1 files changed, 59 insertions(+), 1 deletions(-)

diff --git a/patches/linux/2.6.38/281-apf27-armadeus-add_apf27.c.patch b/patches/linux/2.6.38/281-apf27-armadeus-add_apf27.c.patch
index 2031c77..01e4d25 100644
--- a/patches/linux/2.6.38/281-apf27-armadeus-add_apf27.c.patch
+++ b/patches/linux/2.6.38/281-apf27-armadeus-add_apf27.c.patch
@@ -633,7 +633,7 @@ Index: linux-2.6.38.1/arch/arm/mach-imx/apf27-dev.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
 +++ linux-2.6.38.1/arch/arm/mach-imx/apf27-dev.c	2011-06-03 17:23:24.000000000 +0200
-@@ -0,0 +1,941 @@
+@@ -0,0 +1,999 @@
 + /*
 + * apf27-dev.c
 + * Support for AFP27 module's development baseboard
@@ -666,7 +666,10 @@ Index: linux-2.6.38.1/arch/arm/mach-imx/apf27-dev.c
 +#include <linux/platform_device.h>
 +#include <linux/spi/spi.h>
 +#include <linux/spi/spidev.h>
++#include <linux/gpio_keys.h>
 +#include <linux/i2c.h>
++#include <linux/input.h>
++#include <linux/leds.h>
 +#include <linux/serial.h>
 +#include <linux/delay.h>
 +#include <linux/irq.h>
@@ -849,6 +852,55 @@ Index: linux-2.6.38.1/arch/arm/mach-imx/apf27-dev.c
 +};
 +
 +
++#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
++static struct gpio_keys_button apf27dev_gpio_keys[] = {
++	{
++		.code = BTN_EXTRA, /* See include/linux/input.h */
++		.gpio = (GPIO_PORTF | 13), /* GPIO number */
++		.active_low = 1,
++		.desc = "s1", /* Button description*/
++		.wakeup = 0,
++	},
++};
++
++static struct gpio_keys_platform_data apf27dev_gpio_keys_data = {
++	.buttons = apf27dev_gpio_keys,
++	.nbuttons = ARRAY_SIZE(apf27dev_gpio_keys),
++};
++
++static struct platform_device apf27dev_gpio_keys_device = {
++	.name = "gpio-keys",
++	.id = -1,
++	.dev = {
++		.platform_data = &apf27dev_gpio_keys_data,
++	},
++};
++#endif /* CONFIG_KEYBOARD_GPIO */
++
++#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
++static struct gpio_led apf27dev_led[] = {
++	{
++		.name = "apf27dev:green:led",
++		.default_trigger = "heartbeat",
++		.gpio = (GPIO_PORTF | 14),
++		.active_low = 1,
++	},
++};
++
++static struct gpio_led_platform_data apf27dev_led_data = {
++	.num_leds	= ARRAY_SIZE(apf27dev_led),
++	.leds		= apf27dev_led
++};
++
++static struct platform_device apf27dev_led_dev = {
++	.name		= "leds-gpio",
++	.id		= -1,
++	.dev		= {
++		.platform_data	= &apf27dev_led_data,
++	},
++};
++#endif /* CONFIG_LEDS_GPIO */
++
 +#ifdef CONFIG_I2C
 +
 +/* APF27Dev makes I2C1 bus available */
@@ -1262,6 +1314,12 @@ Index: linux-2.6.38.1/arch/arm/mach-imx/apf27-dev.c
 +#endif /* CONFIG_SND_IMX_TSC2102 || CONFIG_SND_IMX_TSC2102_MODULE */
 +
 +static struct platform_device *platform_devices[] __initdata = {
++#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
++	&apf27dev_led_dev,
++#endif
++#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
++	&apf27dev_gpio_keys_device,
++#endif
 +	ALSA_SOUND
 +};
 +


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-306-gcaf0603

[jorasse <jo...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  caf0603970b10ef962330ec9d7f99cec19d8fd56 (commit)
       via  23f7118b6aa230bfb871aa0fcecf2e898dc5bd2b (commit)
      from  9851a588f202ebcd5c01cd8457b084ec8a79cf7c (commit)

Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit caf0603970b10ef962330ec9d7f99cec19d8fd56
Merge: 23f7118 9851a58
Author: Eric Jarrige <eri...@ar...>
Date:   Sun May 13 00:50:49 2012 +0200

    Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus

commit 23f7118b6aa230bfb871aa0fcecf2e898dc5bd2b
Author: Eric Jarrige <eri...@ar...>
Date:   Sun May 13 00:50:27 2012 +0200

    [LINUX] 2.6.38: Update gpio_key and gpio_led structures to support APF51 board LED and SWITCH

-----------------------------------------------------------------------

Summary of changes:
 .../408-armadeus-add_apf51-dev_baseboard.patch     |   69 ++++++++++++++++---
 1 files changed, 58 insertions(+), 11 deletions(-)

diff --git a/patches/linux/2.6.38/408-armadeus-add_apf51-dev_baseboard.patch b/patches/linux/2.6.38/408-armadeus-add_apf51-dev_baseboard.patch
index d317315..714cc68 100644
--- a/patches/linux/2.6.38/408-armadeus-add_apf51-dev_baseboard.patch
+++ b/patches/linux/2.6.38/408-armadeus-add_apf51-dev_baseboard.patch
@@ -50,7 +50,7 @@ Index: linux-2.6.38.8/arch/arm/mach-mx5/apf51dev-baseboard.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
 +++ linux-2.6.38.8/arch/arm/mach-mx5/apf51dev-baseboard.c	2012-03-19 19:01:24.000000000 +0100
-@@ -0,0 +1,500 @@
+@@ -0,0 +1,547 @@
 + /*
 + * Support for APF51's official development baseboard (APF51Dev)
 + *
@@ -70,7 +70,10 @@ Index: linux-2.6.38.8/arch/arm/mach-mx5/apf51dev-baseboard.c
 +
 +#include <linux/gpio.h>
 +#include <linux/platform_device.h>
++#include <linux/gpio_keys.h>
 +#include <linux/io.h>
++#include <linux/input.h>
++#include <linux/leds.h>
 +#include <linux/spi/spi.h>
 +#include <linux/fb.h>
 +#include <linux/mfd/imx-ipu-v3.h>
@@ -384,22 +387,55 @@ Index: linux-2.6.38.8/arch/arm/mach-mx5/apf51dev-baseboard.c
 +	.no_sdio_irq = 1,	/* Temporary ! (for Wi2Wi) */
 +};
 +
-+/* board key switchs */
-+static struct gpio_keys_button apf51_buttons[] = {
++#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
++static struct gpio_keys_button apf51dev_gpio_keys[] = {
 +	{
 +		.gpio		= IMX_GPIO_NR(1, 3),
-+		.code		= BTN_0,
-+		.desc		= "USER",
++		.code		= BTN_EXTRA, /* See include/linux/input.h */
++		.desc		= "user",
 +		.active_low	= 1,
-+		.wakeup		= 1, /* GPIO1_3 cannot wakeup anyway */
++		.wakeup		= 1,
 +	},
 +};
 +
-+static const struct gpio_keys_platform_data imx_button_data __initconst = {
-+	.buttons	= apf51_buttons,
-+	.nbuttons	= ARRAY_SIZE(apf51_buttons),
++static struct gpio_keys_platform_data apf51dev_gpio_keys_data = {
++	.buttons	= apf51dev_gpio_keys,
++	.nbuttons	= ARRAY_SIZE(apf51dev_gpio_keys),
 +};
 +
++static struct platform_device apf51dev_gpio_keys_device = {
++	.name = "gpio-keys",
++	.id = -1,
++	.dev = {
++		.platform_data = &apf51dev_gpio_keys_data,
++	},
++};
++#endif /* CONFIG_KEYBOARD_GPIO */
++
++#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
++static struct gpio_led apf51dev_led[] = {
++	{
++		.name = "apf51dev:green:led",
++		.default_trigger = "heartbeat",
++		.gpio = (GPIO_PORTA | 2),
++		.active_low = 0,
++	},
++};
++
++static struct gpio_led_platform_data apf51dev_led_data = {
++	.num_leds	= ARRAY_SIZE(apf51dev_led),
++	.leds		= apf51dev_led
++};
++
++static struct platform_device apf51dev_led_dev = {
++	.name		= "leds-gpio",
++	.id		= -1,
++	.dev		= {
++		.platform_data	= &apf51dev_led_data,
++	},
++};
++#endif /* CONFIG_LEDS_GPIO */
++
 +static int init_gpio(void)
 +{
 +#define USER_LED_GPIO		(GPIO_PORTA | 2)
@@ -490,6 +526,16 @@ Index: linux-2.6.38.8/arch/arm/mach-mx5/apf51dev-baseboard.c
 +};
 +#endif
 +
++static struct platform_device *platform_devices[] __initdata = {
++#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
++	&apf51dev_led_dev,
++#endif
++#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
++	&apf51dev_gpio_keys_device,
++#endif
++};
++
++
 +void __init apf51_baseboard_init(void)
 +{
 +#if defined(CONFIG_CPU_FREQ_IMX)
@@ -508,8 +554,6 @@ Index: linux-2.6.38.8/arch/arm/mach-mx5/apf51dev-baseboard.c
 +
 +	init_gpio();
 +
-+	imx_add_gpio_keys(&imx_button_data);
-+
 +	imx51_add_sdhci_esdhc_imx(0, &edshc0_pdata);
 +	imx51_add_sdhci_esdhc_imx(1, &edshc1_pdata);
 +
@@ -550,4 +594,7 @@ Index: linux-2.6.38.8/arch/arm/mach-mx5/apf51dev-baseboard.c
 +#ifdef APF51DEV_USE_SWITCH_AS_PWM
 +	imx51_add_mxc_pwm(1);
 +#endif
++
++	platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
++
 +}


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-304-g9851a58

[jorasse <jo...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  9851a588f202ebcd5c01cd8457b084ec8a79cf7c (commit)
      from  4b4be023227a1322d0db618d4983177bedd9c04c (commit)

Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 9851a588f202ebcd5c01cd8457b084ec8a79cf7c
Author: Eric Jarrige <eri...@ar...>
Date:   Sun May 13 00:47:21 2012 +0200

    [LINUX] 2.6.29: Add gpio_key and gpio_led structures to support APF27 board LED and SWITCH

-----------------------------------------------------------------------

Summary of changes:
 .../2.6.29/281-apf27-armadeus-add_apf27.c.patch    |   60 +++++++++++++++++++-
 1 files changed, 59 insertions(+), 1 deletions(-)

diff --git a/patches/linux/2.6.29/281-apf27-armadeus-add_apf27.c.patch b/patches/linux/2.6.29/281-apf27-armadeus-add_apf27.c.patch
index 45a4b5b..cbe0193 100644
--- a/patches/linux/2.6.29/281-apf27-armadeus-add_apf27.c.patch
+++ b/patches/linux/2.6.29/281-apf27-armadeus-add_apf27.c.patch
@@ -754,7 +754,7 @@ Index: linux-2.6.29.6/arch/arm/mach-mx2/apf27-dev.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
 +++ linux-2.6.29.6/arch/arm/mach-mx2/apf27-dev.c	2012-01-26 10:53:41.000000000 +0100
-@@ -0,0 +1,1094 @@
+@@ -0,0 +1,1152 @@
 + /*
 + * apf27-dev.c
 + * Support for AFP27 module's development baseboard
@@ -782,7 +782,10 @@ Index: linux-2.6.29.6/arch/arm/mach-mx2/apf27-dev.c
 +#include <asm/mach/flash.h>
 +#include <linux/spi/spi.h>
 +#include <linux/spi/spidev.h>
++#include <linux/gpio_keys.h>
 +#include <linux/i2c.h>
++#include <linux/input.h>
++#include <linux/leds.h>
 +#include <linux/serial.h>
 +#include <linux/delay.h>
 +#include <linux/irq.h>
@@ -870,6 +873,55 @@ Index: linux-2.6.29.6/arch/arm/mach-mx2/apf27-dev.c
 +#endif
 +
 +
++#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
++static struct gpio_keys_button apf27dev_gpio_keys[] = {
++	{
++		.code = BTN_EXTRA, /* See include/linux/input.h */
++		.gpio = (GPIO_PORTF | 13), /* GPIO number */
++		.active_low = 1,
++		.desc = "s1", /* Button description*/
++		.wakeup = 0,
++	},
++};
++
++static struct gpio_keys_platform_data apf27dev_gpio_keys_data = {
++	.buttons = apf27dev_gpio_keys,
++	.nbuttons = ARRAY_SIZE(apf27dev_gpio_keys),
++};
++
++static struct platform_device apf27dev_gpio_keys_device = {
++	.name = "gpio-keys",
++	.id = -1,
++	.dev = {
++		.platform_data = &apf27dev_gpio_keys_data,
++	},
++};
++#endif /* CONFIG_KEYBOARD_GPIO */
++
++#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
++static struct gpio_led apf27dev_led[] = {
++	{
++		.name = "apf27dev:green:led",
++		.default_trigger = "heartbeat",
++		.gpio = (GPIO_PORTF | 14),
++		.active_low = 1,
++	},
++};
++
++static struct gpio_led_platform_data apf27dev_led_data = {
++	.num_leds	= ARRAY_SIZE(apf27dev_led),
++	.leds		= apf27dev_led
++};
++
++static struct platform_device apf27dev_led_dev = {
++	.name		= "leds-gpio",
++	.id		= -1,
++	.dev		= {
++		.platform_data	= &apf27dev_led_data,
++	},
++};
++#endif /* CONFIG_LEDS_GPIO */
++
 +#ifdef CONFIG_I2C
 +
 +/* APF27Dev makes I2C1 bus available */
@@ -1559,6 +1611,12 @@ Index: linux-2.6.29.6/arch/arm/mach-mx2/apf27-dev.c
 +#endif /* CONFIG_SND_IMX_TSC2102 || CONFIG_SND_IMX_TSC2102_MODULE */
 +
 +static struct platform_device *platform_devices[] __initdata = {
++#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
++	&apf27dev_led_dev,
++#endif
++#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
++	&apf27dev_gpio_keys_device,
++#endif
 +	ALSA_SOUND
 +};
 +


hooks/post-receive
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armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-303-g4b4be02

[Julien B a. A. <ar...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  4b4be023227a1322d0db618d4983177bedd9c04c (commit)
       via  cec905e3738c164df223a87fee99290e10c3ccef (commit)
       via  af8c92e476c5faea728619181437050dd4e34a21 (commit)
       via  61ea8a61754a4186ec1aed30649c9a8b3dd7b301 (commit)
      from  fd18e0d5ef2517e6208997666d137786ab7c7533 (commit)

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- Log -----------------------------------------------------------------
commit 4b4be023227a1322d0db618d4983177bedd9c04c
Merge: cec905e fd18e0d
Author: Julien Boibessot <jul...@ar...>
Date:   Fri May 11 17:17:54 2012 +0200

    Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus

commit cec905e3738c164df223a87fee99290e10c3ccef
Author: Julien Boibessot <jul...@ar...>
Date:   Fri May 11 17:17:06 2012 +0200

    [BUILD] quiltify: support big custom patch only for apf28 & 2.6.35.3 kernel

commit af8c92e476c5faea728619181437050dd4e34a21
Author: Julien Boibessot <jul...@ar...>
Date:   Fri May 11 17:16:00 2012 +0200

    [TOOLS] Add possibility to build imxregs for i.MX53

commit 61ea8a61754a4186ec1aed30649c9a8b3dd7b301
Author: Julien Boibessot <jul...@ar...>
Date:   Fri May 11 17:13:04 2012 +0200

    [TOOLS] Add (partial) IPU support to imxregs

-----------------------------------------------------------------------

Summary of changes:
 scripts/quiltify.sh                   |    2 +-
 target/linux/debug/imxregs/Makefile   |    5 +++-
 target/linux/debug/imxregs/imx5regs.h |   36 +++++++++++++++++++++++++++++++++
 target/linux/debug/imxregs/imxregs.c  |    2 +-
 4 files changed, 42 insertions(+), 3 deletions(-)

diff --git a/scripts/quiltify.sh b/scripts/quiltify.sh
index 42d0ed0..da1264c 100755
--- a/scripts/quiltify.sh
+++ b/scripts/quiltify.sh
@@ -51,7 +51,7 @@ fi
 make shell_env
 . armadeus_env.sh
 
-if [ "$ARMADEUS_BOARD_NAME" == "apf28" ]; then
+if [ "$ARMADEUS_BOARD_NAME" == "apf28" ] && [ "$ARMADEUS_LINUX_VERSION" == "2.6.35.3" ]; then
 	FREESCALE_PATCH=linux-2.6.35.3-imx_10.12.01.patch.tar.gz
 else
 	FREESCALE_PATCH=""
diff --git a/target/linux/debug/imxregs/Makefile b/target/linux/debug/imxregs/Makefile
index 5ef8944..1ffa7e7 100644
--- a/target/linux/debug/imxregs/Makefile
+++ b/target/linux/debug/imxregs/Makefile
@@ -1,5 +1,5 @@
 CC = arm-linux-gcc
-EXECS = imxlregs imx27regs imx28regs imx51regs
+EXECS = imxlregs imx27regs imx28regs imx51regs imx53regs
 
 all: $(EXECS)
 
@@ -15,6 +15,9 @@ imx28regs: imxregs.c imx28regs.h definitions.h
 imx51regs: imxregs.c imx5regs.h definitions.h
 	$(CC) -DIMX51 imxregs.c -o $@
 
+imx53regs: imxregs.c imx5regs.h definitions.h
+	$(CC) -DIMX53 imxregs.c -o $@
+
 clean:
 	rm -f *.o
 	rm -f $(EXECS)
diff --git a/target/linux/debug/imxregs/imx5regs.h b/target/linux/debug/imxregs/imx5regs.h
index b658853..543133d 100644
--- a/target/linux/debug/imxregs/imx5regs.h
+++ b/target/linux/debug/imxregs/imx5regs.h
@@ -25,17 +25,50 @@
 
 #ifdef IMX51
 #define IMX_TYPE "i.MX51"
+#define IPU_BASE(x)	(0x5e000000 + x)
 #define CSI0_BASE(x)	(0x5e030000 + x)
 #define CSI1_BASE(x)	(0x5e038000 + x)
+#define VDI_BASE(x)	(0x5e068000 + x)
 #else
 #define IMX_TYPE "i.MX53"
+#define IPU_BASE(x)	(0x1e000000 + x)
 #define CSI0_BASE(x)	(0x1e030000 + x)
 #define CSI1_BASE(x)	(0x1e038000 + x)
+#define VDI_BASE(x)	(0x1e068000 + x)
 #endif
 
 static struct reg_info regs[] =
 {
 /* IPU */
+{ "IPU_CONF",		IPU_BASE(0x00), 0, 0xffffffff, 'x', "Configuration Register" },
+{ "IPU_FS_PROC_FLOW1",	IPU_BASE(0xa8), 0, 0xffffffff, 'x', "FSU Processing Flow 1 Register" },
+{ "IPU_FS_PROC_FLOW2",	IPU_BASE(0xac), 0, 0xffffffff, 'x', "FSU Processing Flow 1 Register" },
+{ "IPU_FS_PROC_FLOW3",	IPU_BASE(0xb0), 0, 0xffffffff, 'x', "FSU Processing Flow 1 Register" },
+{ "IPU_SKIP",		IPU_BASE(0xbc), 0, 0xffffffff, 'x', "Skip Register" },
+{ "IPU_CH_DB_MODE_SEL0",IPU_BASE(0x150), 0, 0xffffffff, 'x', "Channel Double Buffer Mode Select 0 Register" },
+{ "IPU_CH_DB_MODE_SEL1",IPU_BASE(0x154), 0, 0xffffffff, 'x', "Channel Double Buffer Mode Select 0 Register" },
+{ "IPU_INT_STAT_1",	IPU_BASE(0x200), 0, 0xffffffff, 'x', "Interrupt Status Register 1" },
+{ "IPU_INT_STAT_2",	IPU_BASE(0x204), 0, 0xffffffff, 'x', "Interrupt Status Register 2" },
+{ "IPU_INT_STAT_3",	IPU_BASE(0x208), 0, 0xffffffff, 'x', "Interrupt Status Register 3" },
+{ "IPU_INT_STAT_5",	IPU_BASE(0x210), 0, 0xffffffff, 'x', "Interrupt Status Register 5" },
+{ "IPU_INT_STAT_6",	IPU_BASE(0x214), 0, 0xffffffff, 'x', "Interrupt Status Register 6" },
+{ "IPU_INT_STAT_7",	IPU_BASE(0x218), 0, 0xffffffff, 'x', "Interrupt Status Register 7" },
+{ "IPU_INT_STAT_8",	IPU_BASE(0x21c), 0, 0xffffffff, 'x', "Interrupt Status Register 8" },
+{ "IPU_INT_STAT_9",	IPU_BASE(0x220), 0, 0xffffffff, 'x', "Interrupt Status Register 9" },
+{ "IPU_INT_STAT_10",	IPU_BASE(0x224), 0, 0xffffffff, 'x', "Interrupt Status Register 10" },
+{ "IPU_INT_STAT_11",	IPU_BASE(0x228), 0, 0xffffffff, 'x', "Interrupt Status Register 11" },
+{ "IPU_INT_STAT_12",	IPU_BASE(0x22c), 0, 0xffffffff, 'x', "Interrupt Status Register 12" },
+{ "IPU_INT_STAT_13",	IPU_BASE(0x230), 0, 0xffffffff, 'x', "Interrupt Status Register 13" },
+{ "IPU_INT_STAT_14",	IPU_BASE(0x234), 0, 0xffffffff, 'x', "Interrupt Status Register 14" },
+{ "IPU_INT_STAT_15",	IPU_BASE(0x238), 0, 0xffffffff, 'x', "Interrupt Status Register 15" },
+{ "IPU_CUR_BUF_0",	IPU_BASE(0x23c), 0, 0xffffffff, 'x', "Current Buffer Register 0" },
+{ "IPU_CUR_BUF_1",	IPU_BASE(0x240), 0, 0xffffffff, 'x', "Current Buffer Register 1" },
+{ "IPU_ALT_CUR_0",	IPU_BASE(0x244), 0, 0xffffffff, 'x', "Alternate Current Buffer Register 0" },
+{ "IPU_ALT_CUR_1",	IPU_BASE(0x248), 0, 0xffffffff, 'x', "Alternate Current Buffer Register 1" },
+{ "IPU_CH_BUF0_RDY0",	IPU_BASE(0x268), 0, 0xffffffff, 'x', "Channels Buffer 0 Ready Register 0" },
+{ "IPU_CH_BUF0_RDY1",	IPU_BASE(0x26c), 0, 0xffffffff, 'x', "Channels Buffer 0 Ready Register 1" },
+{ "IPU_CH_BUF1_RDY0",	IPU_BASE(0x270), 0, 0xffffffff, 'x', "Channels Buffer 1 Ready Register 0" },
+{ "IPU_CH_BUF1_RDY1",	IPU_BASE(0x274), 0, 0xffffffff, 'x', "Channels Buffer 1 Ready Register 1" },
 { "CSI0_SENS_CONF",	CSI0_BASE(0x00), 0, 0xffffffff, 'x', "CSI0 Sensor Configuration Register" },
 { "CSI0_SENS_FRM_SIZE",	CSI0_BASE(0x04), 0, 0xffffffff, 'x', "CSI0 Sensor Frame Size Register" },
 { "CSI0_ACT_FRM_SIZE",	CSI0_BASE(0x08), 0, 0xffffffff, 'x', "CSI0 Actual Frame Size Register" },
@@ -58,6 +91,9 @@ static struct reg_info regs[] =
 { "CSI1_DI",		CSI1_BASE(0x20), 0, 0xffffffff, 'x', "CSI1 Data Identifier Register" },
 { "CSI1_SKIP",		CSI1_BASE(0x24), 0, 0xffffffff, 'x', "CSI1 Skip Register" },
 { "CSI1_CPD_CTRL",	CSI1_BASE(0x28), 0, 0xffffffff, 'x', "CSI1 Compander Control Register" },
+{ "IPU_VDI_SIZE",	VDI_BASE(0x00),  0, 0xffffffff, 'x', "VDI Field Size Register" },
+{ "IPU_VDI_C",		VDI_BASE(0x04),  0, 0xffffffff, 'x', "VDI Control Register" },
+{ "IPU_VDI_C2",		VDI_BASE(0x08),  0, 0xffffffff, 'x', "VDI Control Register 2" },
 /* CCM */
 { "CCR",	0x73fd4000, 0, 0xffffffff, 'x', "CCM Control Register" },
 { "CCDR",	0x73fd4004, 0, 0xffffffff, 'x', "CCM Control Divider Register" },
diff --git a/target/linux/debug/imxregs/imxregs.c b/target/linux/debug/imxregs/imxregs.c
index 90ad295..84c5885 100644
--- a/target/linux/debug/imxregs/imxregs.c
+++ b/target/linux/debug/imxregs/imxregs.c
@@ -35,7 +35,7 @@
 #include "imx27regs.h"
 #elif defined(IMX28)
 #include "imx28regs.h"
-#elif defined(IMX51)
+#elif defined(IMX51) || defined(IMX53)
 #include "imx5regs.h"
 #else
 #include "imxregs.h"


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-299-gfd18e0d

[jorasse <jo...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  fd18e0d5ef2517e6208997666d137786ab7c7533 (commit)
      from  d0272270eb76595069eb68c8c223fb60730e4b60 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit fd18e0d5ef2517e6208997666d137786ab7c7533
Author: Eric Jarrige <eri...@ar...>
Date:   Fri May 11 15:09:38 2012 +0200

    [linux] apf28: Support dual edge GPIO interrupts, GPIO_LEDs and GPIO_KEYS

-----------------------------------------------------------------------

Summary of changes:
 ...1-armadeus-add_apf28dev_baseboard_support.patch |   83 ++++++++++++-----
 ...eus-mx28_support_gpio_both_edge_interrupt.patch |   97 ++++++++++++++++++++
 2 files changed, 157 insertions(+), 23 deletions(-)
 create mode 100644 patches/linux/2.6.35/454-armadeus-mx28_support_gpio_both_edge_interrupt.patch

diff --git a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
index 6d8c4c0..6871627 100644
--- a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
+++ b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
@@ -45,7 +45,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
 +++ linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c	2012-02-15 15:51:09.000000000 +0100
-@@ -0,0 +1,344 @@
+@@ -0,0 +1,381 @@
 +/*
 + * Copyright (C) 2012 Armadeus systems
 + *
@@ -72,6 +72,9 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +#include <linux/io.h>
 +#include <linux/err.h>
 +#include <linux/clk.h>
++#include <linux/gpio_keys.h>
++#include <linux/input.h>
++#include <linux/leds.h>
 +#include <linux/platform_device.h>
 +#include <linux/i2c.h>
 +
@@ -349,35 +352,69 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.drive = 1,
 +		.pull = 0,
 +	},
++};
++
++#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
++static struct gpio_keys_button apf28dev_gpio_keys[] = {
 +	{
-+		.name		= "BT0",
-+		.id		= PINID_GPMI_CE1N,
-+		.fun		= PIN_GPIO,
-+		.strength	= PAD_4MA,
-+		.voltage	= PAD_3_3V,
-+		.pullup		= 0,
-+		.drive		= !0,
-+		.pull		= 0,
-+		.output		= 0,
++		.code = BTN_EXTRA, /* See include/linux/input.h */
++		.gpio = MXS_PIN_TO_GPIO(PINID_GPMI_CE1N), /* GPIO number */
++		.active_low = 1,
++		.desc = "user", /* Button description*/
++		.wakeup = 0, /* no wakeup possible with this button */
 +	},
++};
++
++static struct gpio_keys_platform_data apf28dev_gpio_keys_data = {
++	.buttons = apf28dev_gpio_keys,
++	.nbuttons = ARRAY_SIZE(apf28dev_gpio_keys),
++};
++
++static struct platform_device apf28dev_gpio_keys_device = {
++	.name = "gpio-keys",
++	.id = -1,
++	.dev = {
++		.platform_data = &apf28dev_gpio_keys_data,
++	},
++};
++#endif /* CONFIG_KEYBOARD_GPIO */
++
++#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
++static struct gpio_led apf28dev_led[] = {
 +	{
-+		.name		= "LED",
-+		.id		= PINID_GPMI_RDY1,
-+		.fun		= PIN_GPIO,
-+		.strength	= PAD_4MA,
-+		.voltage	= PAD_3_3V,
-+		.pullup		= 0,
-+		.drive		= !0,
-+		.pull		= 0,
-+		.output		= 1,
-+		.data		= 1,
++		.name = "apf28dev:green:led",
++		.default_trigger = "heartbeat",
++		.gpio = MXS_PIN_TO_GPIO(PINID_GPMI_RDY1),
 +	},
 +};
 +
++static struct gpio_led_platform_data apf28dev_led_data = {
++	.num_leds	= ARRAY_SIZE(apf28dev_led),
++	.leds		= apf28dev_led
++};
++
++static struct platform_device apf28dev_led_dev = {
++	.name		= "leds-gpio",
++	.id		= -1,
++	.dev		= {
++		.platform_data	= &apf28dev_led_data,
++	},
++};
++#endif /* CONFIG_LEDS_GPIO */
++
++static struct platform_device *apf28dev_platform_devices[] __initdata = {
++#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
++	&apf28dev_gpio_keys_device,
++#endif
++#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
++	&apf28dev_led_dev
++#endif
++};
++
 +static void __init apf28dev_device_init(void)
 +{
 +	/* Add apf28dev special code */
-+	;
++	platform_add_devices(apf28dev_platform_devices, ARRAY_SIZE(apf28dev_platform_devices));
 +}
 +
 +extern void __init apf28_init_pin_group(struct pin_desc *pins, unsigned count);
diff --git a/patches/linux/2.6.35/454-armadeus-mx28_support_gpio_both_edge_interrupt.patch b/patches/linux/2.6.35/454-armadeus-mx28_support_gpio_both_edge_interrupt.patch
new file mode 100644
index 0000000..1ee59e5
--- /dev/null
+++ b/patches/linux/2.6.35/454-armadeus-mx28_support_gpio_both_edge_interrupt.patch
@@ -0,0 +1,97 @@
+Fix gpio driver to support raising and falling edge interrupts -
+used by some drivers like gpio-keys, matrix keypad, USB Vbus...
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+--- a/arch/arm/plat-mxs/include/mach/gpio.h
++++ b/arch/arm/plat-mxs/include/mach/gpio.h
+@@ -41,6 +41,7 @@ struct mxs_gpio_chip {
+ 	void (*unmask_irq) (struct mxs_gpio_port *, int);
+ 	void (*mask_irq) (struct mxs_gpio_port *, int);
+ 	void (*ack_irq) (struct mxs_gpio_port *, int);
++	void (*flip_edge_irq) (struct mxs_gpio_port *, int);
+ };
+ 
+ struct mxs_gpio_port {
+@@ -49,6 +50,7 @@ struct mxs_gpio_port {
+ 	int child_irq;
+ 	struct mxs_gpio_chip *chip;
+ 	struct gpio_chip port;
++	u32 both_edges;
+ };
+ 
+ extern int mxs_add_gpio_port(struct mxs_gpio_port *port);
+--- a/arch/arm/plat-mxs/gpio.c
++++ b/arch/arm/plat-mxs/gpio.c
+@@ -114,12 +114,20 @@ static void mxs_gpio_irq_handler(u32 irq
+ 	struct mxs_gpio_port *port = get_irq_data(irq);
+ 	int gpio_irq = port->child_irq;
+ 	u32 irq_stat = port->chip->get_irq_stat(port);
++	int pin;
+ 
+ 	desc->chip->mask(irq);
+ 
+ 	while (irq_stat) {
+-		if (irq_stat & 1)
++		if (irq_stat & 1) {
++
++			pin = GPIO_TO_PINS(irq_to_gpio(gpio_irq));
++			if ((port->both_edges & (1 << pin))
++				&&(port->chip->flip_edge_irq))
++				port->chip->flip_edge_irq(port, pin);
++
+ 			generic_handle_irq(gpio_irq);
++		}
+ 		gpio_irq++;
+ 		irq_stat >>= 1;
+ 	}
+--- a/arch/arm/mach-mx28/gpio.c
++++ b/arch/arm/mach-mx28/gpio.c
+@@ -72,6 +72,7 @@ mx28_gpio_set_irq_type(struct mxs_gpio_p
+ {
+ 	unsigned int level, pol;
+ 	void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id;
++	u32 val;
+ 	switch (type) {
+ 	case IRQ_TYPE_EDGE_RISING:
+ 		level = 0;
+@@ -81,6 +82,18 @@ mx28_gpio_set_irq_type(struct mxs_gpio_p
+ 		level = 0;
+ 		pol = 0;
+ 		break;
++	case IRQ_TYPE_EDGE_BOTH:
++		val = mx28_gpio_get(port, pin);
++		level = 1;
++		if (val) {
++			pol = 0;
++			pr_debug("mx28: set pin %d on port %d to low trigger\n", pin, port->id);
++		} else {
++			level = 1;
++			pr_debug("mx28: set pin %d on port %d to high trigger\n", pin, port->id);
++		}
++		port->both_edges |= 1 << pin;
++		break;
+ 	case IRQ_TYPE_LEVEL_HIGH:
+ 		level = 1;
+ 		pol = 1;
+@@ -108,6 +121,12 @@ mx28_gpio_set_irq_type(struct mxs_gpio_p
+ 	return 0;
+ }
+ 
++static void mx28_flip_edge_irq(struct mxs_gpio_port *port, int pin)
++{
++	void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id;
++	__raw_writel(1 << pin, base + HW_PINCTRL_IRQPOL0_TOG);
++}
++
+ static void mx28_gpio_unmask_irq(struct mxs_gpio_port *port, int pin)
+ {
+ 	void __iomem *base = PINCTRL_BASE_ADDR + 0x10 * port->id;
+@@ -156,6 +175,7 @@ static struct mxs_gpio_chip mx28_gpio_ch
+ 	.unmask_irq = mx28_gpio_unmask_irq,
+ 	.mask_irq = mx28_gpio_mask_irq,
+ 	.ack_irq = mx28_gpio_ack_irq,
++	.flip_edge_irq = mx28_flip_edge_irq,
+ };
+ 
+ int __init mx28_gpio_init(void)


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-298-gd027227

[Julien B a. A. <ar...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  d0272270eb76595069eb68c8c223fb60730e4b60 (commit)
      from  1b45ccd796d1b3f5f9a661a672c03129dfbecde8 (commit)

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- Log -----------------------------------------------------------------
commit d0272270eb76595069eb68c8c223fb60730e4b60
Author: Julien Boibessot <jul...@ar...>
Date:   Tue May 8 20:50:52 2012 +0200

    [BUILDROOT] Add ttyAMA0 to /etc/securetty (Armadeus specific rootfs skeleton)

-----------------------------------------------------------------------

Summary of changes:
 .../armadeus/rootfs/target_skeleton/etc/securetty  |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/buildroot/target/device/armadeus/rootfs/target_skeleton/etc/securetty b/buildroot/target/device/armadeus/rootfs/target_skeleton/etc/securetty
index 59f1f78..dfcba27 100644
--- a/buildroot/target/device/armadeus/rootfs/target_skeleton/etc/securetty
+++ b/buildroot/target/device/armadeus/rootfs/target_skeleton/etc/securetty
@@ -17,3 +17,4 @@ ttymxc1
 ttymxc2
 ttyGS0
 ttyAM0
+ttyAMA0


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-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-297-g1b45ccd

[Julien B a. A. <ar...@us...>]

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       via  d5ca6ae35730dd8de1b14c5110a5bfa53c849847 (commit)
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- Log -----------------------------------------------------------------
commit 1b45ccd796d1b3f5f9a661a672c03129dfbecde8
Merge: d5ca6ae 35b8245
Author: Julien Boibessot <jul...@ar...>
Date:   Tue May 8 19:35:26 2012 +0200

    Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus

commit d5ca6ae35730dd8de1b14c5110a5bfa53c849847
Author: Julien Boibessot <jul...@ar...>
Date:   Tue May 8 19:34:45 2012 +0200

    [LINUX] Updates APF28 vanilla kernel (experimental) support from 3.1 to 3.3.5

-----------------------------------------------------------------------

Summary of changes:
 .../device/armadeus/apf28/apf28-linux-3.3.5.config |    1 +
 ...f28-linux-3.1.config => apf28-linux-3.3.config} |    3 +-
 patches/linux/3.3.5                                |    1 +
 .../450-armadeus-add_apf28_module_support.patch    |   57 ++++++++++++-------
 ...1-armadeus-add_apf28dev_baseboard_support.patch |    0
 5 files changed, 40 insertions(+), 22 deletions(-)
 create mode 120000 buildroot/target/device/armadeus/apf28/apf28-linux-3.3.5.config
 rename buildroot/target/device/armadeus/apf28/{apf28-linux-3.1.config => apf28-linux-3.3.config} (98%)
 create mode 120000 patches/linux/3.3.5
 rename patches/linux/{3.1 => 3.3}/450-armadeus-add_apf28_module_support.patch (70%)
 rename patches/linux/{3.1 => 3.3}/451-armadeus-add_apf28dev_baseboard_support.patch (100%)

diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.3.5.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.3.5.config
new file mode 120000
index 0000000..e18fadf
--- /dev/null
+++ b/buildroot/target/device/armadeus/apf28/apf28-linux-3.3.5.config
@@ -0,0 +1 @@
+apf28-linux-3.3.config
\ No newline at end of file
diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-3.1.config b/buildroot/target/device/armadeus/apf28/apf28-linux-3.3.config
similarity index 98%
rename from buildroot/target/device/armadeus/apf28/apf28-linux-3.1.config
rename to buildroot/target/device/armadeus/apf28/apf28-linux-3.3.config
index 4e50d65..460fc5e 100644
--- a/buildroot/target/device/armadeus/apf28/apf28-linux-3.1.config
+++ b/buildroot/target/device/armadeus/apf28/apf28-linux-3.3.config
@@ -93,8 +93,9 @@ CONFIG_INPUT_TOUCHSCREEN=y
 CONFIG_INPUT_MISC=y
 CONFIG_INPUT_UINPUT=m
 # CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
 CONFIG_SERIAL_MXS_AUART=y
-CONFIG_SERIAL_MXS_AUART_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 CONFIG_I2C_CHARDEV=y
diff --git a/patches/linux/3.3.5 b/patches/linux/3.3.5
new file mode 120000
index 0000000..f30101c
--- /dev/null
+++ b/patches/linux/3.3.5
@@ -0,0 +1 @@
+3.3
\ No newline at end of file
diff --git a/patches/linux/3.1/450-armadeus-add_apf28_module_support.patch b/patches/linux/3.3/450-armadeus-add_apf28_module_support.patch
similarity index 70%
rename from patches/linux/3.1/450-armadeus-add_apf28_module_support.patch
rename to patches/linux/3.3/450-armadeus-add_apf28_module_support.patch
index 4f0bcd1..5c50cfb 100644
--- a/patches/linux/3.1/450-armadeus-add_apf28_module_support.patch
+++ b/patches/linux/3.3/450-armadeus-add_apf28_module_support.patch
@@ -2,13 +2,13 @@ Add Armadeus systems APF28 SOM support.
 
 Signed-off-by: Julien Boibessot <jul...@ar...>
 
-Index: linux-3.1/arch/arm/mach-mxs/Kconfig
+Index: linux-3.3.5/arch/arm/mach-mxs/Kconfig
 ===================================================================
---- linux-3.1.orig/arch/arm/mach-mxs/Kconfig	2011-11-08 17:02:08.000000000 +0100
-+++ linux-3.1/arch/arm/mach-mxs/Kconfig	2011-11-09 15:52:13.000000000 +0100
-@@ -68,4 +68,13 @@
- 	bool "Ka-Ro TX28 module"
- 	select MODULE_TX28
+--- linux-3.3.5.orig/arch/arm/mach-mxs/Kconfig	2012-05-07 17:55:30.000000000 +0200
++++ linux-3.3.5/arch/arm/mach-mxs/Kconfig	2012-05-08 14:59:27.000000000 +0200
+@@ -91,4 +91,13 @@
+ 	bool "Support DENX M28EVK Platform"
+ 	select MODULE_M28
  
 +config MACH_APF28
 +	bool "Armadeus APF28 module"
@@ -20,21 +20,21 @@ Index: linux-3.1/arch/arm/mach-mxs/Kconfig
 +	  specific configurations for the module and its peripherals.
 +
  endif
-Index: linux-3.1/arch/arm/mach-mxs/Makefile
+Index: linux-3.3.5/arch/arm/mach-mxs/Makefile
 ===================================================================
---- linux-3.1.orig/arch/arm/mach-mxs/Makefile	2011-11-08 17:09:03.000000000 +0100
-+++ linux-3.1/arch/arm/mach-mxs/Makefile	2011-11-09 15:52:13.000000000 +0100
-@@ -12,5 +12,6 @@
- obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
+--- linux-3.3.5.orig/arch/arm/mach-mxs/Makefile	2012-05-07 17:55:30.000000000 +0200
++++ linux-3.3.5/arch/arm/mach-mxs/Makefile	2012-05-08 14:59:27.000000000 +0200
+@@ -13,5 +13,6 @@
+ obj-$(CONFIG_MACH_M28EVK)    += mach-m28evk.o
  obj-$(CONFIG_MODULE_TX28) += module-tx28.o
  obj-$(CONFIG_MACH_TX28)    += mach-tx28.o
 +obj-$(CONFIG_MACH_APF28)	+= mach-apf28.o
  
  obj-y += devices/
-Index: linux-3.1/arch/arm/mach-mxs/mach-apf28.c
+Index: linux-3.3.5/arch/arm/mach-mxs/mach-apf28.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-3.1/arch/arm/mach-mxs/mach-apf28.c	2011-11-09 15:53:02.000000000 +0100
++++ linux-3.3.5/arch/arm/mach-mxs/mach-apf28.c	2012-05-08 14:59:27.000000000 +0200
 @@ -0,0 +1,106 @@
 +/*
 + * Copyright 2011 Armadeus systems.
@@ -142,12 +142,27 @@ Index: linux-3.1/arch/arm/mach-mxs/mach-apf28.c
 +	.init_machine	= apf28_init,
 +	.timer		= &apf28_timer,
 +MACHINE_END
-Index: linux-3.1/arch/arm/tools/mach-types
+Index: linux-3.3.5/arch/arm/mach-mxs/include/mach/mxs.h
 ===================================================================
---- linux-3.1.orig/arch/arm/tools/mach-types	2011-11-09 11:01:00.000000000 +0100
-+++ linux-3.1/arch/arm/tools/mach-types	2011-11-09 11:02:38.000000000 +0100
-@@ -1113,3 +1113,4 @@
- thales_adc		MACH_THALES_ADC		THALES_ADC		3492
- ubisys_p9d_evp		MACH_UBISYS_P9D_EVP	UBISYS_P9D_EVP		3493
- atdgp318		MACH_ATDGP318		ATDGP318		3494
-+apf28			MACH_APF28		APF28			3845
+--- linux-3.3.5.orig/arch/arm/mach-mxs/include/mach/mxs.h	2012-05-08 14:59:50.000000000 +0200
++++ linux-3.3.5/arch/arm/mach-mxs/include/mach/mxs.h	2012-05-08 15:00:14.000000000 +0200
+@@ -36,6 +36,7 @@
+ 		machine_is_mx28evk() ||					\
+ 		machine_is_m28evk() ||					\
+ 		machine_is_tx28() ||					\
++		machine_is_apf28() ||					\
+ 		0)
+ 
+ /*
+Index: linux-3.3.5/arch/arm/mach-mxs/include/mach/uncompress.h
+===================================================================
+--- linux-3.3.5.orig/arch/arm/mach-mxs/include/mach/uncompress.h	2012-05-08 15:00:38.000000000 +0200
++++ linux-3.3.5/arch/arm/mach-mxs/include/mach/uncompress.h	2012-05-08 15:01:01.000000000 +0200
+@@ -65,6 +65,7 @@
+ 	case MACH_TYPE_MX28EVK:
+ 	case MACH_TYPE_M28EVK:
+ 	case MACH_TYPE_TX28:
++	case MACH_TYPE_APF28:
+ 		mxs_duart_base = MX28_DUART_BASE_ADDR;
+ 		break;
+ 	default:
diff --git a/patches/linux/3.1/451-armadeus-add_apf28dev_baseboard_support.patch b/patches/linux/3.3/451-armadeus-add_apf28dev_baseboard_support.patch
similarity index 100%
rename from patches/linux/3.1/451-armadeus-add_apf28dev_baseboard_support.patch
rename to patches/linux/3.3/451-armadeus-add_apf28dev_baseboard_support.patch


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-295-g35b8245

[jscheer <js...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  35b82458979f3f0550f00c9e39827ca718292566 (commit)
      from  72e00f4e5869198a8e428f32b5c028e7c8f41cc2 (commit)

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- Log -----------------------------------------------------------------
commit 35b82458979f3f0550f00c9e39827ca718292566
Author: Jeremie Scheer <jer...@ar...>
Date:   Fri May 4 18:12:00 2012 +0200

    [BUILDROOT] Fix QWT package source URL.
    [BUILDROOT] Fix QWT package qmake path for configuration.

-----------------------------------------------------------------------

Summary of changes:
 .../buildroot/2012.02/133-qwt-add_package.patch    |   14 +++++++-------
 1 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/patches/buildroot/2012.02/133-qwt-add_package.patch b/patches/buildroot/2012.02/133-qwt-add_package.patch
index 8d2d1a9..552296a 100644
--- a/patches/buildroot/2012.02/133-qwt-add_package.patch
+++ b/patches/buildroot/2012.02/133-qwt-add_package.patch
@@ -4,8 +4,8 @@ Signed-off-by: Jérémie Scheer <jer...@ar...>
 
 Index: buildroot/package/Config.in
 ===================================================================
---- buildroot.orig/package/Config.in	2012-03-16 17:30:27.000000000 +0100
-+++ buildroot/package/Config.in	2012-03-19 18:24:10.000000000 +0100
+--- buildroot.orig/package/Config.in	2012-05-04 18:01:25.000000000 +0200
++++ buildroot/package/Config.in	2012-05-04 18:09:24.000000000 +0200
 @@ -140,6 +140,7 @@
  comment "other GUIs"
  source "package/efl/Config.in"
@@ -17,7 +17,7 @@ Index: buildroot/package/Config.in
 Index: buildroot/package/qwt/Config.in
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ buildroot/package/qwt/Config.in	2012-03-19 15:48:04.000000000 +0100
++++ buildroot/package/qwt/Config.in	2012-05-04 18:01:25.000000000 +0200
 @@ -0,0 +1,20 @@
 +comment "Qwt requires Qt to be installed"
 +	depends on !BR2_PACKAGE_QT
@@ -42,7 +42,7 @@ Index: buildroot/package/qwt/Config.in
 Index: buildroot/package/qwt/qwt-5.2.1-change_install_dir_and_no_designer.patch
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ buildroot/package/qwt/qwt-5.2.1-change_install_dir_and_no_designer.patch	2012-03-19 15:48:04.000000000 +0100
++++ buildroot/package/qwt/qwt-5.2.1-change_install_dir_and_no_designer.patch	2012-05-04 18:01:25.000000000 +0200
 @@ -0,0 +1,30 @@
 +--- qwt-5.2.1/qwtconfig.pri.orig	2010-09-28 14:34:01.000000000 +0200
 ++++ qwt-5.2.1/qwtconfig.pri	2010-09-28 15:37:02.000000000 +0200
@@ -77,7 +77,7 @@ Index: buildroot/package/qwt/qwt-5.2.1-change_install_dir_and_no_designer.patch
 Index: buildroot/package/qwt/qwt.mk
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ buildroot/package/qwt/qwt.mk	2012-03-19 18:24:33.000000000 +0100
++++ buildroot/package/qwt/qwt.mk	2012-05-04 18:03:07.000000000 +0200
 @@ -0,0 +1,82 @@
 +######################################################################
 +#
@@ -87,7 +87,7 @@ Index: buildroot/package/qwt/qwt.mk
 +
 +QWT_VERSION:=5.2.1
 +QWT_SOURCE:=qwt-$(QWT_VERSION).zip
-+QWT_SITE:=https://sourceforge.net/projects/qwt/files/qwt/$(QWT_VERSION)
++QWT_SITE:=http://sourceforge.net/projects/qwt/files/qwt/$(QWT_VERSION)
 +QWT_UNZIP:=unzip
 +QWT_TARGET_DIR:=$(BUILD_DIR)/qwt-$(QWT_VERSION)
 +QWT_CONFIG_FILE:=qwt.pro
@@ -109,7 +109,7 @@ Index: buildroot/package/qwt/qwt.mk
 +
 +$(QWT_TARGET_DIR)/.configured: $(QWT_TARGET_DIR)/.unpacked
 +	-[ -f $(QWT_TARGET_DIR)/Makefile ] && $(MAKE) -C $(QWT_TARGET_DIR) distclean
-+	$(QT_DIR)/bin/qmake $(QWT_TARGET_DIR)/$(QWT_CONFIG_FILE)
++	$(QT_HOST_DIR)/bin/qmake $(QWT_TARGET_DIR)/$(QWT_CONFIG_FILE)
 +	touch $@
 +
 +$(QWT_TARGET_DIR)/.compiled: $(QWT_TARGET_DIR)/.configured


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-294-g72e00f4

[jscheer <js...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  72e00f4e5869198a8e428f32b5c028e7c8f41cc2 (commit)
      from  0c8b34305e19404bb381b1bc81c98f4a91e373f8 (commit)

Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 72e00f4e5869198a8e428f32b5c028e7c8f41cc2
Author: Jeremie Scheer <jer...@ar...>
Date:   Fri May 4 17:38:10 2012 +0200

    [BUILDROOT] Cleanup package QtCreator in BR 2012.02

-----------------------------------------------------------------------

Summary of changes:
 patches/buildroot/2012.02/cleanup_buildroot.sh |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/patches/buildroot/2012.02/cleanup_buildroot.sh b/patches/buildroot/2012.02/cleanup_buildroot.sh
index 83d6ed6..ccd10cf 100755
--- a/patches/buildroot/2012.02/cleanup_buildroot.sh
+++ b/patches/buildroot/2012.02/cleanup_buildroot.sh
@@ -72,3 +72,4 @@ rm -rf buildroot/package/multimedia/gst-fsl-plugin/
 rm -rf buildroot/package/multimedia/fsl-mm-codeclib/
 rm -rf buildroot/package/linux-firmware/
 rm -rf buildroot/package/uboot-tools/
+rm -rf buildroot/package/qtcreator/


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-293-g0c8b343

[Julien B a. A. <ar...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  0c8b34305e19404bb381b1bc81c98f4a91e373f8 (commit)
      from  9d1ccd2dab25022f95a542e17163b97a5e17c1f3 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 0c8b34305e19404bb381b1bc81c98f4a91e373f8
Author: Julien Boibessot <jul...@ar...>
Date:   Fri May 4 15:18:57 2012 +0200

    [BUILDROOT] Fixes 183-firmware-imx-add_package.patch

-----------------------------------------------------------------------

Summary of changes:
 .../2012.02/183-firmware-imx-add_package.patch     |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/patches/buildroot/2012.02/183-firmware-imx-add_package.patch b/patches/buildroot/2012.02/183-firmware-imx-add_package.patch
index 76fec76..f4c28f8 100644
--- a/patches/buildroot/2012.02/183-firmware-imx-add_package.patch
+++ b/patches/buildroot/2012.02/183-firmware-imx-add_package.patch
@@ -39,10 +39,10 @@ Index: buildroot/package/Config.in
 ===================================================================
 --- buildroot.orig/package/Config.in	2012-03-29 15:09:34.000000000 +0200
 +++ buildroot/package/Config.in	2012-03-29 15:10:35.000000000 +0200
-@@ -192,6 +192,7 @@
+@@ -191,6 +191,7 @@
+ source "package/e2fsprogs/Config.in"
  source "package/eeprog/Config.in"
  source "package/fconfig/Config.in"
- source "package/firmware/Config.in"
 +source "package/firmware-imx/Config.in"
  source "package/fis/Config.in"
  source "package/gadgetfs-test/Config.in"


hooks/post-receive
-- 
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-292-g9d1ccd2

[Julien B a. A. <ar...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  9d1ccd2dab25022f95a542e17163b97a5e17c1f3 (commit)
       via  a6d9b98ec8e1d23829869d14c461934d73055a2a (commit)
      from  5e34956b53bfa966849edc51249e8bbb14df7f8e (commit)

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- Log -----------------------------------------------------------------
commit 9d1ccd2dab25022f95a542e17163b97a5e17c1f3
Merge: a6d9b98 5e34956
Author: Julien Boibessot <jul...@ar...>
Date:   Fri May 4 14:51:44 2012 +0200

    Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus
    
    Conflicts:
    	patches/buildroot/2012.02/cleanup_buildroot.sh

commit a6d9b98ec8e1d23829869d14c461934d73055a2a
Author: Julien Boibessot <jul...@ar...>
Date:   Fri May 4 14:48:42 2012 +0200

    [BUILDROOT] Merge Armadeus specific firmware package with Buildroot linux-firmware one

-----------------------------------------------------------------------

Summary of changes:
 ...e-add_infrastructure_to_install_firmwares.patch |  149 --------------------
 ...-linux-firmware-add_marvell_libertas_8686.patch |   87 ++++++++++++
 patches/buildroot/2012.02/cleanup_buildroot.sh     |    3 +-
 3 files changed, 88 insertions(+), 151 deletions(-)
 delete mode 100644 patches/buildroot/2012.02/106-firmware-add_infrastructure_to_install_firmwares.patch
 create mode 100644 patches/buildroot/2012.02/186-linux-firmware-add_marvell_libertas_8686.patch

diff --git a/patches/buildroot/2012.02/106-firmware-add_infrastructure_to_install_firmwares.patch b/patches/buildroot/2012.02/106-firmware-add_infrastructure_to_install_firmwares.patch
deleted file mode 100644
index e838ffc..0000000
--- a/patches/buildroot/2012.02/106-firmware-add_infrastructure_to_install_firmwares.patch
+++ /dev/null
@@ -1,149 +0,0 @@
-Add infrastructure to download linux-firmwares.
-Currently only libertas 88W8686 firmwares are handled.
-
-Signed-off-by: Julien Boibessot <jul...@ar...>
-
-Index: buildroot/package/Config.in
-===================================================================
---- buildroot.orig/package/Config.in	2012-02-21 16:44:42.000000000 +0100
-+++ buildroot/package/Config.in	2012-02-21 16:44:50.000000000 +0100
-@@ -182,6 +182,7 @@
- source "package/e2fsprogs/Config.in"
- source "package/eeprog/Config.in"
- source "package/fconfig/Config.in"
-+source "package/firmware/Config.in"
- source "package/fis/Config.in"
- source "package/gadgetfs-test/Config.in"
- source "package/gdisk/Config.in"
-Index: buildroot/package/firmware/Config.in
-===================================================================
---- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ buildroot/package/firmware/Config.in	2012-02-21 16:44:50.000000000 +0100
-@@ -0,0 +1,49 @@
-+menuconfig BR2_PACKAGE_FIRMWARE
-+	bool "linux-firmware"
-+	help
-+	  Install selected firmware from linux-firmware.git repository.
-+
-+	  This repository was setup by David Woodhouse in order to:
-+	  "include firmware files from vendors who have chosen not to
-+	  contribute their firmware to be distributed as part of the GPL'd
-+	  kernel source tree, but would still like their firmware to be readily
-+	  available to Linux users."
-+
-+
-+if BR2_PACKAGE_FIRMWARE
-+
-+comment "Video"
-+
-+comment "WiFi chipsets"
-+
-+config BR2_PACKAGE_FIRMWARE_88W8686
-+	bool "Marvell's 88W8686 (Libertas)"
-+
-+config BR2_PACKAGE_FIRMWARE_88W8686_SDIO
-+	bool "SDIO"
-+	default y
-+	depends on BR2_PACKAGE_FIRMWARE_88W8686
-+
-+choice
-+	prompt "Firmware version"
-+	default BR2_PACKAGE_FIRMWARE_88W8686_SDIO_V9
-+	depends on BR2_PACKAGE_FIRMWARE_88W8686_SDIO
-+	help
-+	  SDIO firmware is available in v8 or v9 version.
-+
-+config BR2_PACKAGE_FIRMWARE_88W8686_SDIO_V8
-+	bool "v8"
-+
-+config BR2_PACKAGE_FIRMWARE_88W8686_SDIO_V9
-+	bool "v9"
-+
-+endchoice
-+
-+config BR2_PACKAGE_FIRMWARE_88W8686_GSPI
-+	bool "GSPI"
-+	depends on BR2_PACKAGE_FIRMWARE_88W8686
-+
-+comment "Others"
-+
-+endif
-+
-Index: buildroot/package/firmware/firmware.mk
-===================================================================
---- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ buildroot/package/firmware/firmware.mk	2012-02-21 16:44:50.000000000 +0100
-@@ -0,0 +1,73 @@
-+#############################################################
-+#
-+# Get and install some linux-firmware
-+#
-+#############################################################
-+FIRMWARE_VERSION:=af5222c5ded5d944267acfbd001571409bea7eeb
-+FIRMWARE_SOURCE:=firmware-$(FIRMWARE_VERSION).tar.gz
-+FIRMWARE_GIT:=git://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git
-+FIRMWARE_DIR:=$(BUILD_DIR)/firmware-$(FIRMWARE_VERSION)
-+FIRMWARE_TARGET_DIR:=$(TARGET_DIR)/lib/firmware
-+FIRMWARE_CAT:=$(ZCAT)
-+FIRMWARE_NAME:=firmware-$(FIRMWARE_VERSION)
-+
-+
-+ifeq ($(strip $(BR2_PACKAGE_FIRMWARE_88W8686_SDIO_V8)),y)
-+FIRMWARE_88W8686_SDIO_VERSION:=v8
-+else
-+FIRMWARE_88W8686_SDIO_VERSION:=v9
-+endif
-+ifeq ($(strip $(BR2_PACKAGE_FIRMWARE_88W8686_SDIO)),y)
-+FIRMWARE_BINARIES+=sd8686_$(FIRMWARE_88W8686_SDIO_VERSION)_helper.bin sd8686_$(FIRMWARE_88W8686_SDIO_VERSION).bin
-+endif
-+ifeq ($(strip $(BR2_PACKAGE_FIRMWARE_88W8686_GSPI)),y)
-+FIRMWARE_BINARIES+=gspi8686_$(FIRMWARE_88W8686_SDIO_VERSION)_helper.bin gspi8686_$(FIRMWARE_88W8686_SDIO_VERSION).bin
-+endif
-+
-+$(DL_DIR)/$(FIRMWARE_SOURCE):
-+	git clone $(FIRMWARE_GIT) $(FIRMWARE_DIR)
-+	(cd $(FIRMWARE_DIR); \
-+		git archive --prefix=$(FIRMWARE_NAME)/ $(FIRMWARE_VERSION) | \
-+		gzip > $(DL_DIR)/$(FIRMWARE_SOURCE) )
-+	rm -rf $(FIRMWARE_DIR)
-+
-+$(FIRMWARE_DIR)/.unpacked: $(DL_DIR)/$(FIRMWARE_SOURCE)
-+	$(FIRMWARE_CAT) $(DL_DIR)/$(FIRMWARE_SOURCE) | tar -C $(BUILD_DIR) $(TAR_OPTIONS) -
-+	touch $@
-+
-+$(FIRMWARE_DIR)/.installed: $(FIRMWARE_DIR)/.unpacked
-+	mkdir -p $(FIRMWARE_TARGET_DIR)/libertas
-+ifeq ($(strip $(BR2_PACKAGE_FIRMWARE_88W8686_SDIO)),y)
-+	$(INSTALL) -D $(FIRMWARE_DIR)/libertas/sd8686_$(FIRMWARE_88W8686_SDIO_VERSION)_helper.bin $(FIRMWARE_TARGET_DIR)/libertas/
-+	$(INSTALL) -D $(FIRMWARE_DIR)/libertas/sd8686_$(FIRMWARE_88W8686_SDIO_VERSION).bin $(FIRMWARE_TARGET_DIR)/libertas/
-+	# To be compatible with old kernels:
-+	ln -sf ./libertas/sd8686_$(FIRMWARE_88W8686_SDIO_VERSION)_helper.bin $(FIRMWARE_TARGET_DIR)/sd8686_helper.bin
-+	ln -sf ./libertas/sd8686_$(FIRMWARE_88W8686_SDIO_VERSION).bin $(FIRMWARE_TARGET_DIR)/sd8686.bin
-+endif
-+ifeq ($(strip $(BR2_PACKAGE_FIRMWARE_88W8686_GSPI)),y)
-+	$(INSTALL) -D $(FIRMWARE_DIR)/libertas/gspi8686_$(FIRMWARE_88W8686_SDIO_VERSION)_helper.bin $(FIRMWARE_TARGET_DIR)/libertas/
-+	$(INSTALL) -D $(FIRMWARE_DIR)/libertas/gspi8686_$(FIRMWARE_88W8686_SDIO_VERSION).bin $(FIRMWARE_TARGET_DIR)/libertas/
-+endif
-+	touch $@
-+
-+firmware: $(FIRMWARE_DIR)/.installed
-+
-+firmware-source: $(DL_DIR)/$(FIRMWARE_SOURCE)
-+
-+firmware-clean:
-+	rm -f $(FIRMWARE_DIR)/.installed
-+	(for file in $(FIRMWARE_BINARIES); do \
-+		rm -f "$(FIRMWARE_TARGET_DIR)/$$file"; \
-+	done)
-+
-+firmware-dirclean:
-+	rm -rf $(FIRMWARE_DIR)
-+
-+#############################################################
-+#
-+# Toplevel Makefile options
-+#
-+#############################################################
-+ifeq ($(strip $(BR2_PACKAGE_FIRMWARE)),y)
-+TARGETS+=firmware
-+endif
diff --git a/patches/buildroot/2012.02/186-linux-firmware-add_marvell_libertas_8686.patch b/patches/buildroot/2012.02/186-linux-firmware-add_marvell_libertas_8686.patch
new file mode 100644
index 0000000..b60882d
--- /dev/null
+++ b/patches/buildroot/2012.02/186-linux-firmware-add_marvell_libertas_8686.patch
@@ -0,0 +1,87 @@
+Add Marvell Libertas 88W8686 to linux-firmware.
+
+Signed-off-by: Julien Boibessot <jul...@ar...>
+
+Index: buildroot/package/linux-firmware/Config.in
+===================================================================
+--- buildroot.orig/package/linux-firmware/Config.in	2012-05-03 21:00:53.000000000 +0200
++++ buildroot/package/linux-firmware/Config.in	2012-05-03 21:37:17.000000000 +0200
+@@ -8,6 +8,37 @@
+ 
+ if BR2_PACKAGE_LINUX_FIRMWARE
+ 
++menu "Marvell"
++
++config BR2_PACKAGE_LINUX_FIRMWARE_88W8686
++	bool "88W8686 (Libertas)"
++
++choice
++	prompt "Firmware version"
++	default BR2_PACKAGE_LINUX_FIRMWARE_88W8686_V9
++	depends on BR2_PACKAGE_LINUX_FIRMWARE_88W8686
++	help
++	  SDIO firmware is available in v8 or v9 version.
++
++config BR2_PACKAGE_LINUX_FIRMWARE_88W8686_V8
++	bool "v8"
++
++config BR2_PACKAGE_LINUX_FIRMWARE_88W8686_V9
++	bool "v9"
++
++endchoice
++
++config BR2_PACKAGE_LINUX_FIRMWARE_88W8686_SDIO
++	bool "SDIO"
++	default y
++	depends on BR2_PACKAGE_LINUX_FIRMWARE_88W8686
++
++config BR2_PACKAGE_LINUX_FIRMWARE_88W8686_GSPI
++	bool "GSPI"
++	depends on BR2_PACKAGE_LINUX_FIRMWARE_88W8686
++
++endmenu
++
+ menu "Ralink"
+ 
+ config BR2_PACKAGE_LINUX_FIRMWARE_RALINK_RT61
+Index: buildroot/package/linux-firmware/linux-firmware.mk
+===================================================================
+--- buildroot.orig/package/linux-firmware/linux-firmware.mk	2012-05-03 21:01:00.000000000 +0200
++++ buildroot/package/linux-firmware/linux-firmware.mk	2012-05-03 21:34:45.000000000 +0200
+@@ -3,10 +3,25 @@
+ # linux-firmware
+ #
+ #############################################################
+-LINUX_FIRMWARE_VERSION = a2995d38c234e3d767df7223d84a0f33a1a24997
++#LINUX_FIRMWARE_VERSION = a2995d38c234e3d767df7223d84a0f33a1a24997
++LINUX_FIRMWARE_VERSION = af5222c5ded5d944267acfbd001571409bea7eeb
+ LINUX_FIRMWARE_SITE = git://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git
+ LINUX_FIRMWARE_SITE_METHOD = git
+ 
++# Libertas 88W8686
++ifeq ($(strip $(BR2_PACKAGE_LINUX_FIRMWARE_88W8686_V8)),y)
++LINUX_FIRMWARE_88W8686_VERSION = v8
++else
++LINUX_FIRMWARE_88W8686_VERSION = v9
++endif
++LINUX_FIRMWARE_FILES_$(BR2_PACKAGE_LINUX_FIRMWARE_88W8686_SDIO) += \
++	libertas/sd8686_$(LINUX_FIRMWARE_88W8686_VERSION)_helper.bin \
++	libertas/sd8686_$(LINUX_FIRMWARE_88W8686_VERSION).bin
++
++LINUX_FIRMWARE_FILES_$(BR2_PACKAGE_LINUX_FIRMWARE_88W8686_GSPI) += \
++	libertas/gspi8686_$(LINUX_FIRMWARE_88W8686_VERSION)_helper.bin \
++	libertas/gspi8686_$(LINUX_FIRMWARE_88W8686_VERSION).bin
++
+ # rt2501/rt61
+ LINUX_FIRMWARE_FILES_$(BR2_PACKAGE_LINUX_FIRMWARE_RALINK_RT61) += \
+ 	rt2561.bin rt2561s.bin rt2661.bin LICENCE.ralink-firmware.txt
+@@ -52,6 +67,9 @@
+ 	mkdir -p $(TARGET_DIR)/lib/firmware
+ 	$(TAR) c -C $(@D) $(LINUX_FIRMWARE_FILES_y) | \
+ 		$(TAR) x -C $(TARGET_DIR)/lib/firmware
++	# To be compatible with old Armadeus kernels:
++	ln -sf ./libertas/sd8686_$(LINUX_FIRMWARE_88W8686_SDIO_VERSION)_helper.bin $(FIRMWARE_TARGET_DIR)/sd8686_helper.bin
++	ln -sf ./libertas/sd8686_$(LINUX_FIRMWARE_88W8686_SDIO_VERSION).bin $(FIRMWARE_TARGET_DIR)/sd8686.bin
+ endef
+ 
+ endif
diff --git a/patches/buildroot/2012.02/cleanup_buildroot.sh b/patches/buildroot/2012.02/cleanup_buildroot.sh
index da47017..83d6ed6 100755
--- a/patches/buildroot/2012.02/cleanup_buildroot.sh
+++ b/patches/buildroot/2012.02/cleanup_buildroot.sh
@@ -15,7 +15,6 @@ rm -rf buildroot/package/multimedia/flite/
 rm -rf buildroot/package/libcurl/
 rm -f  buildroot/package/multimedia/mplayer/mplayer-1.0rc2-add_pld_asm_inst_for_non_armv5_arch.patch
 rm -f  buildroot/package/multimedia/madplay/madplay-audio-alsa.patch
-rm -rf buildroot/package/firmware/
 rm -f  buildroot/toolchain/gcc/4.2.1/999-4.2.1-armeabi-aapcs-linux.patch
 rm -f  buildroot/toolchain/gcc/4.2.4/999-4.2.4-armeabi-aapcs-linux.patch
 rm -rf buildroot/package/games/wolf4sdl/
@@ -71,5 +70,5 @@ rm -rf buildroot/package/e2fsprogs/
 rm -rf buildroot/package/firmware-imx/
 rm -rf buildroot/package/multimedia/gst-fsl-plugin/
 rm -rf buildroot/package/multimedia/fsl-mm-codeclib/
+rm -rf buildroot/package/linux-firmware/
 rm -rf buildroot/package/uboot-tools/
-


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armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-290-g5e34956

[jorasse <jo...@us...>]

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generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  5e34956b53bfa966849edc51249e8bbb14df7f8e (commit)
       via  9c9b2ea8d3b91e162493f55c38c7ac8c1aef7025 (commit)
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- Log -----------------------------------------------------------------
commit 5e34956b53bfa966849edc51249e8bbb14df7f8e
Merge: 9c9b2ea 7c6a388
Author: Eric Jarrige <eri...@ar...>
Date:   Tue Apr 24 19:46:04 2012 +0200

    Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus

commit 9c9b2ea8d3b91e162493f55c38c7ac8c1aef7025
Author: Eric Jarrige <eri...@ar...>
Date:   Tue Apr 24 19:45:15 2012 +0200

    [LINUX] APF28_DEV: add GPIO definition for user LED and button

-----------------------------------------------------------------------

Summary of changes:
 ...1-armadeus-add_apf28dev_baseboard_support.patch |   27 ++++++++++++++++++-
 1 files changed, 25 insertions(+), 2 deletions(-)

diff --git a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
index 3bc0ee7..6d8c4c0 100644
--- a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
+++ b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
@@ -45,7 +45,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
 +++ linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c	2012-02-15 15:51:09.000000000 +0100
-@@ -0,0 +1,321 @@
+@@ -0,0 +1,344 @@
 +/*
 + * Copyright (C) 2012 Armadeus systems
 + *
@@ -336,7 +336,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.strength = PAD_12MA,
 +		.voltage = PAD_3_3V,
 +		.pullup	= 0,
-+		.drive = 2,
++		.drive = 1,
 +		.pull = 0,
 +	},
 +	{
@@ -349,6 +349,29 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.drive = 1,
 +		.pull = 0,
 +	},
++	{
++		.name		= "BT0",
++		.id		= PINID_GPMI_CE1N,
++		.fun		= PIN_GPIO,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= !0,
++		.pull		= 0,
++		.output		= 0,
++	},
++	{
++		.name		= "LED",
++		.id		= PINID_GPMI_RDY1,
++		.fun		= PIN_GPIO,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= !0,
++		.pull		= 0,
++		.output		= 1,
++		.data		= 1,
++	},
 +};
 +
 +static void __init apf28dev_device_init(void)


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-288-g7c6a388

[jorasse <jo...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  7c6a3887cfe7fa5cb9ffd7ed0a0c238106d9c7dc (commit)
      from  0d340adcd9dfce419a70a1ae97f4e000ad9f9b82 (commit)

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- Log -----------------------------------------------------------------
commit 7c6a3887cfe7fa5cb9ffd7ed0a0c238106d9c7dc
Author: Eric Jarrige <eri...@ar...>
Date:   Tue Apr 24 11:39:46 2012 +0200

    [LINUX] APF27: Add resident imx watchdog to linux 2.6.29

-----------------------------------------------------------------------

Summary of changes:
 .../armadeus/apf27/apf27-linux-2.6.29.config       |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/buildroot/target/device/armadeus/apf27/apf27-linux-2.6.29.config b/buildroot/target/device/armadeus/apf27/apf27-linux-2.6.29.config
index eb35e88..80fff22 100644
--- a/buildroot/target/device/armadeus/apf27/apf27-linux-2.6.29.config
+++ b/buildroot/target/device/armadeus/apf27/apf27-linux-2.6.29.config
@@ -974,13 +974,13 @@ CONFIG_HWMON=m
 # CONFIG_HWMON_DEBUG_CHIP is not set
 # CONFIG_THERMAL is not set
 CONFIG_WATCHDOG=y
-# CONFIG_WATCHDOG_NOWAYOUT is not set
+CONFIG_WATCHDOG_NOWAYOUT=y
 
 #
 # Watchdog Device Drivers
 #
 # CONFIG_SOFT_WATCHDOG is not set
-CONFIG_IMX_WDT=m
+CONFIG_IMX_WDT=y
 
 #
 # USB-based Watchdog Cards


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-287-g0d340ad

[jorasse <jo...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  0d340adcd9dfce419a70a1ae97f4e000ad9f9b82 (commit)
      from  a445d12935581e081f28b5ad29ae397d4f895edb (commit)

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- Log -----------------------------------------------------------------
commit 0d340adcd9dfce419a70a1ae97f4e000ad9f9b82
Author: Eric Jarrige <eri...@ar...>
Date:   Tue Apr 24 11:35:27 2012 +0200

    [TEST] APF28: add watchdog test case

-----------------------------------------------------------------------

Summary of changes:
 target/test/test_helpers.sh  |    2 ++
 target/test/test_watchdog.sh |    9 ++++++---
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/target/test/test_helpers.sh b/target/test/test_helpers.sh
index 2f524ae..a773ff9 100644
--- a/target/test/test_helpers.sh
+++ b/target/test/test_helpers.sh
@@ -146,6 +146,8 @@ execute_for_target()
 	                $1 $BOARD
 	        elif [ "$BOARD" == "APF27" ]; then
 	                $1 $BOARD
+	        elif [ "$BOARD" == "APF28" ]; then
+	                $1 $BOARD
 	        elif [ "$BOARD" == "APF51" ]; then
 	                $1 $BOARD
 	        fi
diff --git a/target/test/test_watchdog.sh b/target/test/test_watchdog.sh
index 51f0208..fba9d97 100755
--- a/target/test/test_watchdog.sh
+++ b/target/test/test_watchdog.sh
@@ -41,13 +41,16 @@ test_watchdog()
 		exit_failed
 	fi
 
-	execute_for_target load_driver
-	if [ "$RES" != 0 ] || [ ! -c "$WATCHDOG_DEV" ] ; then
+	if [ ! -c "$WATCHDOG_DEV" ] ; then
+		execute_for_target load_driver
+	fi
+
+	if [ ! -c "$WATCHDOG_DEV" ] ; then
 		echo "Module failed to load"
 		exit_failed
 	fi
 
-	watchdog -t $(($SEC-2)) /dev/watchdog
+	watchdog -T $(($SEC)) -t $(($SEC-2)) /dev/watchdog
 	if [ "$?" != 0 ]; then
 		echo "Failed to launch userspace helper"
 		exit_failed


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-286-ga445d12

[jorasse <jo...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  a445d12935581e081f28b5ad29ae397d4f895edb (commit)
      from  98e5d1b2f84a1b1825bdd65f988decb1e86a02be (commit)

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- Log -----------------------------------------------------------------
commit a445d12935581e081f28b5ad29ae397d4f895edb
Author: Eric Jarrige <eri...@ar...>
Date:   Tue Apr 24 00:22:22 2012 +0200

    [LINUX] APF28: use more robust watchdog

-----------------------------------------------------------------------

Summary of changes:
 .../armadeus/apf28/apf28-linux-2.6.35.config       |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config b/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
index 9484aad..c2b5ba1 100644
--- a/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
+++ b/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
@@ -1142,7 +1142,7 @@ CONFIG_BATTERY_MXS=y
 # CONFIG_HWMON is not set
 # CONFIG_THERMAL is not set
 CONFIG_WATCHDOG=y
-# CONFIG_WATCHDOG_NOWAYOUT is not set
+CONFIG_WATCHDOG_NOWAYOUT=y
 
 #
 # Watchdog Device Drivers


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-- 
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-282-ga8a9310

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      from  eded072706c3595f717fdbf051d3761830d81240 (commit)

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- Log -----------------------------------------------------------------
commit a8a9310f8979be628f99a8fc63bf66f08bae3853
Merge: ed49591 eded072
Author: Eric Jarrige <eri...@ar...>
Date:   Fri Apr 20 18:25:30 2012 +0200

    Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus

commit ed49591ca50e54d81e70afd0b6c800e0321df176
Author: Eric Jarrige <eri...@ar...>
Date:   Fri Apr 20 18:24:38 2012 +0200

    [TOOLS] APF27: make recover tool ready for new generation of bootloader - update RAM initiliasation

-----------------------------------------------------------------------

Summary of changes:
 software/uboot_recover/apf27_recover.py |   94 ++++++++++++------------------
 1 files changed, 38 insertions(+), 56 deletions(-)

diff --git a/software/uboot_recover/apf27_recover.py b/software/uboot_recover/apf27_recover.py
index 30d4645..5ccd017 100644
--- a/software/uboot_recover/apf27_recover.py
+++ b/software/uboot_recover/apf27_recover.py
@@ -240,58 +240,39 @@ class apf27Bootloader:
 
     def initSDRAM2( self ):
         print "SDRAM INIT2 APF",
-        self.put("D800100C","00695728","l") 
-
-        self.put("D8001008","92100000","l") 
-        self.put("B0000F00","00000000","l") 
-        self.put("D8001008","A2100000","l") 
-        self.put("B0000F00","00000000","l") 
-        self.put("B0000F00","00000000","l") 
-        self.put("B0000F00","00000000","l") 
-        self.put("B0000F00","00000000","l") 
-        self.put("D8001008","A2100000","l") 
-        self.put("B0000F00","00000000","l") 
-        self.put("B0000F00","00000000","l") 
-        self.put("B0000F00","00000000","l") 
-        self.put("B0000F00","00000000","l") 
-        self.put("D8001008","b2100000","l") 
-        self.put("B0000033","DA0000DA","b") 
-        self.put("B2000000","00000000","b") 
-        self.put("D8001008","82126080","l") 
-
-    def initSDRAM1( self, sdramType ):
-
-            print "SDRAM INIT1 APF",
-            self.put("10027818","0000080f","l")
-            #self.put("D8001010","00000004","l") 
-            self.put("D8001010","0000000C","l") 
-
-            #self.put("10027828","55555555","l") 
-            #self.put("10027830","55555555","l") 
-            #self.put("10027834","55555555","l") 
-            #self.put("10027838","00005005","l") 
-            #self.put("1002783C","15555555","l") 
-            #self.put("D8001010","00000024","l") 
-            #self.put("D8001004","0069eb38","l")
-            #self.put("D8001004","007FFFFF","l") 
-            self.put("D8001004","00695728","l")
-
-            self.put("D8001000","92100000","l") 
-            self.put("A0000F00","00000000","l") 
-            self.put("D8001000","A2100000","l") 
-            self.put("A0000F00","00000000","l") 
-            self.put("A0000F00","00000000","l") 
-            self.put("A0000F00","00000000","l") 
-            self.put("A0000F00","00000000","l") 
-            self.put("D8001000","A2100000","l") 
-            self.put("A0000F00","00000000","l") 
-            self.put("A0000F00","00000000","l") 
-            self.put("A0000F00","00000000","l") 
-            self.put("A0000F00","00000000","l") 
-            self.put("D8001000","b2100000","l") 
-            self.put("A0000033","DA0000DA","b") 
-            self.put("A2000000","00000000","b") 
-            self.put("D8001000","82126080","l") 
+        self.put("D800100C","0069D42A","l")
+
+        self.put("D8001008","92126485","l")
+        self.put("B0000400","00000000","l")
+        self.put("D8001008","A2126485","l")
+        self.put("B0000000","00000000","l")
+        self.put("B0000000","00000000","l")
+        self.put("B0000000","00000000","l")
+        self.put("B0000000","00000000","l")
+        self.put("D8001008","B2126485","l")
+        self.put("B0000033","DA0000DA","b")
+        self.put("B2000000","00000000","b")
+        self.put("D8001008","82126485","l")
+
+    def initSDRAM1( self ):
+
+        print "SDRAM INIT1 APF",
+        self.put("10027818","0000080f","l")
+        self.put("D8001010","0000002C","l")
+
+        self.put("D8001004","0069D42A","l")
+
+        self.put("D8001000","92126485","l")
+        self.put("A0000400","00000000","l")
+        self.put("D8001000","A2126485","l")
+        self.put("A0000000","00000000","l")
+        self.put("A0000000","00000000","l")
+        self.put("A0000000","00000000","l")
+        self.put("A0000000","00000000","l")
+        self.put("D8001000","B2126485","l")
+        self.put("A0000033","DA0000DA","b")
+        self.put("A2000000","00000000","b")
+        self.put("D8001000","82126485","l")
 
 
     def consoleDump(tid):
@@ -327,8 +308,8 @@ class UBoot:
         BINARY = "apf27-u-boot.bin"
         if not os.path.exists(BINARY):
             raise Error("file "+BINARY+" doesn't exit",0)
-        fsize = "%08x" % os.path.getsize(BINARY) #os.stat(filesize)[6]
-        self.bootstrap.download("A0000000", BINARY, fsize)
+        self.fsize = "%08x" % os.path.getsize(BINARY) #os.stat(filesize)[6]
+        self.bootstrap.download("A0000000", BINARY, self.fsize)
 
     def resetenv(self):
         self.serial.flushInput()
@@ -345,7 +326,7 @@ class UBoot:
     def flash(self):
         """ flash uboot """
         self.serial.flushInput()
-        self.serial.write("run flash_uboot\n")
+        self.serial.write("setenv fileaddr A0000000; setenv filesize "+self.fsize+";run flash_uboot\n")
         try:
             ret = self.__getOutput()
         except Error,e:
@@ -377,7 +358,8 @@ if __name__ == "__main__":
     uboot = UBoot(apfBootloader, ser)
 
     apfBootloader.getstatus()
-    apfBootloader.initSDRAM1("APF27")
+    apfBootloader.initSDRAM1()
+    apfBootloader.initSDRAM2()
     uboot.load()
     uboot.waitForPrompt()
     eraseAll = raw_input('Would you like to erase the environment variables? y/n: ')


hooks/post-receive
-- 
armadeus