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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-352-gff39fcb

From: jorasse <jo...@us...> - 2012-06-08 07:01:43

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  ff39fcb4d6d3762a42bfd1fb3e347ff6f89146db (commit)
      from  1a2a3a9326f1a09863bac2f6e4a67ae2337d228d (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit ff39fcb4d6d3762a42bfd1fb3e347ff6f89146db
Author: Eric Jarrige <eri...@ar...>
Date:   Fri Jun 8 09:02:23 2012 +0200

    [LINUX] apf28: set GPMI_RDn/GPMI_WRn drive strengh according to reference manual

-----------------------------------------------------------------------

Summary of changes:
 .../450-armadeus-add_apf28_module_support.patch    |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch b/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch
index e9ac7ca..61dbc14 100644
--- a/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch
+++ b/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch
@@ -192,7 +192,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +		.name		= "GPMI RD-",
 +		.id		= PINID_GPMI_RDN,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_4MA,
++		.strength	= PAD_8MA,
 +		.voltage	= PAD_3_3V,
 +		.pullup		= 0,
 +		.drive		= !0
@@ -201,7 +201,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +		.name		= "GPMI WR-",
 +		.id		= PINID_GPMI_WRN,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_4MA,
++		.strength	= PAD_8MA,
 +		.voltage	= PAD_3_3V,
 +		.pullup		= 0,
 +		.drive		= !0


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-351-g1a2a3a9

From: jorasse <jo...@us...> - 2012-06-08 06:27:09

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  1a2a3a9326f1a09863bac2f6e4a67ae2337d228d (commit)
      from  5af65d53f2c509dc406915daca5041d5fbb8e0d5 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 1a2a3a9326f1a09863bac2f6e4a67ae2337d228d
Author: Eric Jarrige <eri...@ar...>
Date:   Fri Jun 8 08:27:56 2012 +0200

    [UBOOT] apf28: set GPMI_RDn/GPMI_WRn drive strengh and pull up according to reference manual

-----------------------------------------------------------------------

Summary of changes:
 .../device/armadeus/apf28/apf28-u-boot-2012.04.h   |    2 +-
 patches/u-boot/2012.04/502-add-apf28.patch         |   10 +++++++---
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h b/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h
index 3e503f7..98f5afe 100644
--- a/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h
+++ b/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h
@@ -26,7 +26,7 @@
 
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_ENV_VERSION 	"1.0"
-#define CONFIG_IDENT_STRING	" apf28 patch 1.2"
+#define CONFIG_IDENT_STRING	" apf28 patch 1.3"
 #define CONFIG_BOARD_NAME	apf28
 
 /*
diff --git a/patches/u-boot/2012.04/502-add-apf28.patch b/patches/u-boot/2012.04/502-add-apf28.patch
index abd0e09..4e92586 100644
--- a/patches/u-boot/2012.04/502-add-apf28.patch
+++ b/patches/u-boot/2012.04/502-add-apf28.patch
@@ -1115,7 +1115,7 @@ new file mode 100644
 index 0000000..3769d44
 --- /dev/null
 +++ b/board/armadeus/apf28/spl_boot.c
-@@ -0,0 +1,202 @@
+@@ -0,0 +1,206 @@
 +/*
 + * Freescale i.MX28 Boot setup for the APF28 board
 + *
@@ -1185,8 +1185,12 @@ index 0000000..3769d44
 +	MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
 +	MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
 +	MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
-+	MX28_PAD_GPMI_RDN__GPMI_RDN | MUX_CONFIG_GPMI,
-+	MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
++	/* see mx28 reference manual 9.2.2.1 notes for RD/WR 8mA reason */
++	MX28_PAD_GPMI_RDN__GPMI_RDN |
++		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_NOPULL),
++	/* see mx28 reference manual 9.4.36 pullup bit description */
++	MX28_PAD_GPMI_WRN__GPMI_WRN |
++		(MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP),
 +	MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
 +	MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,
 +	MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI,


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-350-g5af65d5

From: jorasse <jo...@us...> - 2012-06-07 16:16:46

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  5af65d53f2c509dc406915daca5041d5fbb8e0d5 (commit)
      from  6e188825b32f3908ba701b653888ba03d6002751 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 5af65d53f2c509dc406915daca5041d5fbb8e0d5
Author: Eric Jarrige <eri...@ar...>
Date:   Thu Jun 7 18:18:00 2012 +0200

    [LINUX] apf28: support variable intensity LCD backlight - preliminary draft

-----------------------------------------------------------------------

Summary of changes:
 ...1-armadeus-add_apf28dev_baseboard_support.patch |   43 ++++++++++----------
 1 files changed, 21 insertions(+), 22 deletions(-)

diff --git a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
index 14444c9..5c1ea39 100644
--- a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
+++ b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
@@ -45,7 +45,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 ===================================================================
 --- /dev/null
 +++ linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
-@@ -0,0 +1,756 @@
+@@ -0,0 +1,755 @@
 +/*
 + * Copyright (C) 2012 Armadeus systems
 + *
@@ -273,7 +273,6 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.voltage = PAD_3_3V,
 +		.drive = 1,
 +	},
-+/*
 +	{
 +	 .name = "LCD_CONTRAST",
 +	 .id = PINID_PWM3,
@@ -282,7 +281,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +	 .voltage = PAD_3_3V,
 +	 .drive	= 1,
 +	 },
-+*/
++
 +#endif
 +	/* SSP0 SD/MMC port pins */
 +	{
@@ -1043,9 +1042,9 @@ Index: linux-2.6.35.3/drivers/video/mxs/lcd_tm035.c
 +	__raw_writel(BF_PWM_PERIODn_CDIV(6) |	/* divide by 64 */
 +		     BF_PWM_PERIODn_INACTIVE_STATE(2) |	/* low */
 +		     BF_PWM_PERIODn_ACTIVE_STATE(3) |	/* high */
-+		     BF_PWM_PERIODn_PERIOD(599),
++		     BF_PWM_PERIODn_PERIOD(99),
 +		     REGS_PWM_BASE + HW_PWM_PERIODn(3));
-+	__raw_writel(BM_PWM_CTRL_PWM2_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL_SET);
++	__raw_writel(BM_PWM_CTRL_PWM3_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL_SET);
 +
 +	return 0;
 +}
@@ -1058,9 +1057,9 @@ Index: linux-2.6.35.3/drivers/video/mxs/lcd_tm035.c
 +	__raw_writel(BF_PWM_PERIODn_CDIV(6) |	/* divide by 64 */
 +		     BF_PWM_PERIODn_INACTIVE_STATE(2) |	/* low */
 +		     BF_PWM_PERIODn_ACTIVE_STATE(3) |	/* high */
-+		     BF_PWM_PERIODn_PERIOD(599),
++		     BF_PWM_PERIODn_PERIOD(99),
 +		     REGS_PWM_BASE + HW_PWM_PERIODn(3));
-+	__raw_writel(BM_PWM_CTRL_PWM2_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL_CLR);
++	__raw_writel(BM_PWM_CTRL_PWM3_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL_CLR);
 +
 +	clk_disable(pwm_clk);
 +	clk_put(pwm_clk);
@@ -1122,7 +1121,7 @@ Index: linux-2.6.35.3/drivers/video/mxs/lcd_tm035.c
 +	__raw_writel(BF_PWM_PERIODn_CDIV(6) |	/* divide by 64 */
 +		     BF_PWM_PERIODn_INACTIVE_STATE(2) |	/* low */
 +		     BF_PWM_PERIODn_ACTIVE_STATE(3) |	/* high */
-+		     BF_PWM_PERIODn_PERIOD(399),
++		     BF_PWM_PERIODn_PERIOD(99),
 +		     REGS_PWM_BASE + HW_PWM_PERIODn(3));
 +	return 0;
 +}
@@ -1341,13 +1340,13 @@ Index: linux-2.6.35.3/drivers/video/mxs/lcd_lw700.c
 +
 +	__raw_writel(BF_PWM_ACTIVEn_INACTIVE(0) |
 +		     BF_PWM_ACTIVEn_ACTIVE(0),
-+		     REGS_PWM_BASE + HW_PWM_ACTIVEn(2));
-+	__raw_writel(BF_PWM_PERIODn_CDIV(6) |	/* divide by 64 */
++		     REGS_PWM_BASE + HW_PWM_ACTIVEn(3));
++	__raw_writel(BF_PWM_PERIODn_CDIV(3) |	/* divide by 8 */
 +		     BF_PWM_PERIODn_INACTIVE_STATE(2) |	/* low */
 +		     BF_PWM_PERIODn_ACTIVE_STATE(3) |	/* high */
-+		     BF_PWM_PERIODn_PERIOD(599),
-+		     REGS_PWM_BASE + HW_PWM_PERIODn(2));
-+	__raw_writel(BM_PWM_CTRL_PWM2_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL_SET);
++		     BF_PWM_PERIODn_PERIOD(99),
++		     REGS_PWM_BASE + HW_PWM_PERIODn(3));
++	__raw_writel(BM_PWM_CTRL_PWM3_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL_SET);
 +
 +	return 0;
 +}
@@ -1356,13 +1355,13 @@ Index: linux-2.6.35.3/drivers/video/mxs/lcd_lw700.c
 +{
 +	__raw_writel(BF_PWM_ACTIVEn_INACTIVE(0) |
 +		     BF_PWM_ACTIVEn_ACTIVE(0),
-+		     REGS_PWM_BASE + HW_PWM_ACTIVEn(2));
-+	__raw_writel(BF_PWM_PERIODn_CDIV(6) |	/* divide by 64 */
++		     REGS_PWM_BASE + HW_PWM_ACTIVEn(3));
++	__raw_writel(BF_PWM_PERIODn_CDIV(3) |	/* divide by 8 */
 +		     BF_PWM_PERIODn_INACTIVE_STATE(2) |	/* low */
 +		     BF_PWM_PERIODn_ACTIVE_STATE(3) |	/* high */
-+		     BF_PWM_PERIODn_PERIOD(599),
-+		     REGS_PWM_BASE + HW_PWM_PERIODn(2));
-+	__raw_writel(BM_PWM_CTRL_PWM2_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL_CLR);
++		     BF_PWM_PERIODn_PERIOD(99),
++		     REGS_PWM_BASE + HW_PWM_PERIODn(3));
++	__raw_writel(BM_PWM_CTRL_PWM3_ENABLE, REGS_PWM_BASE + HW_PWM_CTRL_CLR);
 +
 +	clk_disable(pwm_clk);
 +	clk_put(pwm_clk);
@@ -1420,12 +1419,12 @@ Index: linux-2.6.35.3/drivers/video/mxs/lcd_lw700.c
 +	}
 +	__raw_writel(BF_PWM_ACTIVEn_INACTIVE(scaled_int) |
 +		     BF_PWM_ACTIVEn_ACTIVE(0),
-+		     REGS_PWM_BASE + HW_PWM_ACTIVEn(2));
-+	__raw_writel(BF_PWM_PERIODn_CDIV(6) |	/* divide by 64 */
++		     REGS_PWM_BASE + HW_PWM_ACTIVEn(3));
++	__raw_writel(BF_PWM_PERIODn_CDIV(3) |	/* divide by 8 */
 +		     BF_PWM_PERIODn_INACTIVE_STATE(2) |	/* low */
 +		     BF_PWM_PERIODn_ACTIVE_STATE(3) |	/* high */
-+		     BF_PWM_PERIODn_PERIOD(399),
-+		     REGS_PWM_BASE + HW_PWM_PERIODn(2));
++		     BF_PWM_PERIODn_PERIOD(99),
++		     REGS_PWM_BASE + HW_PWM_PERIODn(3));
 +	return 0;
 +}
 +


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-349-g6e18882

From: jorasse <jo...@us...> - 2012-06-06 10:27:58

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  6e188825b32f3908ba701b653888ba03d6002751 (commit)
       via  0ff79f604578a6cba96f6dd4f40bb7cbb267942d (commit)
      from  36fb390e8668a19db8b0812d8bb9ee1728fb90ca (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 6e188825b32f3908ba701b653888ba03d6002751
Author: Eric Jarrige <eri...@ar...>
Date:   Wed Jun 6 12:28:58 2012 +0200

    [LINUX] apf28: Fix board signal strengh to 4mA - TODO: LCD bus signal optimization

commit 0ff79f604578a6cba96f6dd4f40bb7cbb267942d
Author: Eric Jarrige <eri...@ar...>
Date:   Wed Jun 6 12:21:13 2012 +0200

    [UBOOT] apf28: Fix board signal level and strengh issue with NAND flash and DDR2 RAM

-----------------------------------------------------------------------

Summary of changes:
 .../device/armadeus/apf28/apf28-u-boot-2012.04.h   |    2 +-
 .../450-armadeus-add_apf28_module_support.patch    |   24 ++++++------
 ...1-armadeus-add_apf28dev_baseboard_support.patch |   42 ++++++++++----------
 patches/u-boot/2012.04/502-add-apf28.patch         |   21 +++++-----
 4 files changed, 44 insertions(+), 45 deletions(-)

diff --git a/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h b/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h
index a864a16..3e503f7 100644
--- a/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h
+++ b/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h
@@ -26,7 +26,7 @@
 
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_ENV_VERSION 	"1.0"
-#define CONFIG_IDENT_STRING	" apf28 patch 1.1"
+#define CONFIG_IDENT_STRING	" apf28 patch 1.2"
 #define CONFIG_BOARD_NAME	apf28
 
 /*
diff --git a/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch b/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch
index 2985a03..e9ac7ca 100644
--- a/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch
+++ b/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch
@@ -192,7 +192,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +		.name		= "GPMI RD-",
 +		.id		= PINID_GPMI_RDN,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_12MA,
++		.strength	= PAD_4MA,
 +		.voltage	= PAD_3_3V,
 +		.pullup		= 0,
 +		.drive		= !0
@@ -201,7 +201,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +		.name		= "GPMI WR-",
 +		.id		= PINID_GPMI_WRN,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_12MA,
++		.strength	= PAD_4MA,
 +		.voltage	= PAD_3_3V,
 +		.pullup		= 0,
 +		.drive		= !0
@@ -228,7 +228,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +		.name		= "GPMI RST-",
 +		.id		= PINID_GPMI_RESETN,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_12MA,
++		.strength	= PAD_4MA,
 +		.voltage	= PAD_3_3V,
 +		.pullup		= 0,
 +		.drive		= !0
@@ -240,7 +240,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +		.name		= "ENET0_MDC",
 +		.id		= PINID_ENET0_MDC,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_8MA,
++		.strength	= PAD_4MA,
 +		.pull		= 1,
 +		.pullup		= 1,
 +		.voltage	= PAD_3_3V,
@@ -250,7 +250,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +		.name		= "ENET0_MDIO",
 +		.id		= PINID_ENET0_MDIO,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_8MA,
++		.strength	= PAD_4MA,
 +		.pull		= 1,
 +		.pullup		= 1,
 +		.voltage	= PAD_3_3V,
@@ -260,7 +260,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +		.name		= "ENET0_RX_EN",
 +		.id		= PINID_ENET0_RX_EN,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_8MA,
++		.strength	= PAD_4MA,
 +		.pull		= 1,
 +		.pullup		= 1,
 +		.voltage	= PAD_3_3V,
@@ -270,7 +270,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +		.name		= "ENET0_RXD0",
 +		.id		= PINID_ENET0_RXD0,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_8MA,
++		.strength	= PAD_4MA,
 +		.pull		= 1,
 +		.pullup		= 1,
 +		.voltage	= PAD_3_3V,
@@ -280,7 +280,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +		.name		= "ENET0_RXD1",
 +		.id		= PINID_ENET0_RXD1,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_8MA,
++		.strength	= PAD_4MA,
 +		.pull		= 1,
 +		.pullup		= 1,
 +		.voltage	= PAD_3_3V,
@@ -290,7 +290,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +		.name		= "ENET0_TX_EN",
 +		.id		= PINID_ENET0_TX_EN,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_8MA,
++		.strength	= PAD_4MA,
 +		.pull		= 1,
 +		.pullup		= 1,
 +		.voltage	= PAD_3_3V,
@@ -300,7 +300,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +		.name		= "ENET0_TXD0",
 +		.id		= PINID_ENET0_TXD0,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_8MA,
++		.strength	= PAD_4MA,
 +		.pull		= 1,
 +		.pullup		= 1,
 +		.voltage	= PAD_3_3V,
@@ -310,7 +310,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +		.name		= "ENET0_TXD1",
 +		.id		= PINID_ENET0_TXD1,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_8MA,
++		.strength	= PAD_4MA,
 +		.pull		= 1,
 +		.pullup		= 1,
 +		.voltage	= PAD_3_3V,
@@ -320,7 +320,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +		.name		= "ENET_CLK",
 +		.id		= PINID_ENET_CLK,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_8MA,
++		.strength	= PAD_4MA,
 +		.pull		= 1,
 +		.pullup		= 1,
 +		.voltage	= PAD_3_3V,
diff --git a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
index f37e549..14444c9 100644
--- a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
+++ b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
@@ -289,7 +289,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name = "SSP0_DATA0",
 +		.id = PINID_SSP0_DATA0,
 +		.fun = PIN_FUN1,
-+		.strength = PAD_8MA,
++		.strength = PAD_4MA,
 +		.voltage = PAD_3_3V,
 +		.pullup	= 1,
 +		.drive = 1,
@@ -299,7 +299,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name = "SSP0_DATA1",
 +		.id = PINID_SSP0_DATA1,
 +		.fun = PIN_FUN1,
-+		.strength = PAD_8MA,
++		.strength = PAD_4MA,
 +		.voltage = PAD_3_3V,
 +		.pullup	= 1,
 +		.drive = 1,
@@ -309,7 +309,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name = "SSP0_DATA2",
 +		.id = PINID_SSP0_DATA2,
 +		.fun = PIN_FUN1,
-+		.strength = PAD_8MA,
++		.strength = PAD_4MA,
 +		.voltage = PAD_3_3V,
 +		.pullup	= 1,
 +		.drive = 1,
@@ -319,7 +319,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name = "SSP0_DATA3",
 +		.id = PINID_SSP0_DATA3,
 +		.fun = PIN_FUN1,
-+		.strength = PAD_8MA,
++		.strength = PAD_4MA,
 +		.voltage = PAD_3_3V,
 +		.pullup	= 1,
 +		.drive = 1,
@@ -329,7 +329,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name = "SSP0_CMD",
 +		.id = PINID_SSP0_CMD,
 +		.fun = PIN_FUN1,
-+		.strength = PAD_8MA,
++		.strength = PAD_4MA,
 +		.voltage = PAD_3_3V,
 +		.pullup	= 1,
 +		.drive = 1,
@@ -339,7 +339,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name = "SSP0_SCK",
 +		.id = PINID_SSP0_SCK,
 +		.fun = PIN_FUN1,
-+		.strength = PAD_12MA,
++		.strength = PAD_4MA,
 +		.voltage = PAD_3_3V,
 +		.pullup	= 0,
 +		.drive = 1,
@@ -349,7 +349,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name = "SSP0_DETECT",
 +		.id = PINID_SSP0_DETECT,
 +		.fun = PIN_FUN1,
-+		.strength = PAD_8MA,
++		.strength = PAD_4MA,
 +		.voltage = PAD_3_3V,
 +		.pullup	= 0,
 +		.drive = 1,
@@ -469,7 +469,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name		= "I2C0_SCL",
 +		.id		= PINID_I2C0_SCL,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_8MA,
++		.strength	= PAD_4MA,
 +		.voltage	= PAD_3_3V,
 +		.drive		= 1,
 +	},
@@ -477,7 +477,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name		= "I2C0_SDA",
 +		.id		= PINID_I2C0_SDA,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_8MA,
++		.strength	= PAD_4MA,
 +		.voltage	= PAD_3_3V,
 +		.drive		= 1,
 +	},
@@ -488,7 +488,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name		= "SAIF0_MCLK",
 +		.id		= PINID_SAIF0_MCLK,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_12MA,
++		.strength	= PAD_4MA,
 +		.voltage	= PAD_3_3V,
 +		.pullup		= 1,
 +		.drive		= 1,
@@ -498,7 +498,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name		= "SAIF0_LRCLK",
 +		.id		= PINID_SAIF0_LRCLK,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_12MA,
++		.strength	= PAD_4MA,
 +		.voltage	= PAD_3_3V,
 +		.pullup		= 1,
 +		.drive		= 1,
@@ -508,7 +508,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name		= "SAIF0_BITCLK",
 +		.id		= PINID_SAIF0_BITCLK,
 +		.fun		= PIN_FUN3,
-+		.strength	= PAD_12MA,
++		.strength	= PAD_4MA,
 +		.voltage	= PAD_3_3V,
 +		.pullup		= 1,
 +		.drive		= 1,
@@ -518,7 +518,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name		= "SAIF0_SDATA0",
 +		.id		= PINID_SAIF0_SDATA0,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_12MA,
++		.strength	= PAD_4MA,
 +		.voltage	= PAD_3_3V,
 +		.pullup		= 1,
 +		.drive		= 1,
@@ -528,7 +528,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name		= "SAIF1_SDATA0",
 +		.id		= PINID_SAIF1_SDATA0,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_12MA,
++		.strength	= PAD_4MA,
 +		.voltage	= PAD_3_3V,
 +		.pullup		= 1,
 +		.drive		= 1,
@@ -541,7 +541,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name		= "SPDIF",
 +		.id		= PINID_SPDIF,
 +		.fun		= PIN_FUN1,
-+		.strength	= PAD_12MA,
++		.strength	= PAD_4MA,
 +		.voltage	= PAD_3_3V,
 +		.pullup		= 1,
 +		.drive		= 1,
@@ -554,7 +554,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name		= "ENET1_RX_EN",
 +		.id		= PINID_ENET0_CRS,
 +		.fun		= PIN_FUN2,
-+		.strength	= PAD_8MA,
++		.strength	= PAD_4MA,
 +		.pull		= 1,
 +		.pullup		= 1,
 +		.voltage	= PAD_3_3V,
@@ -564,7 +564,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name		= "ENET1_RXD0",
 +		.id		= PINID_ENET0_RXD2,
 +		.fun		= PIN_FUN2,
-+		.strength	= PAD_8MA,
++		.strength	= PAD_4MA,
 +		.pull		= 1,
 +		.pullup		= 1,
 +		.voltage	= PAD_3_3V,
@@ -574,7 +574,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name		= "ENET1_RXD1",
 +		.id		= PINID_ENET0_RXD3,
 +		.fun		= PIN_FUN2,
-+		.strength	= PAD_8MA,
++		.strength	= PAD_4MA,
 +		.pull		= 1,
 +		.pullup		= 1,
 +		.voltage	= PAD_3_3V,
@@ -584,7 +584,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name		= "ENET1_TX_EN",
 +		.id		= PINID_ENET0_COL,
 +		.fun		= PIN_FUN2,
-+		.strength	= PAD_8MA,
++		.strength	= PAD_4MA,
 +		.pull		= 1,
 +		.pullup		= 1,
 +		.voltage	= PAD_3_3V,
@@ -594,7 +594,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name		= "ENET1_TXD0",
 +		.id		= PINID_ENET0_TXD2,
 +		.fun		= PIN_FUN2,
-+		.strength	= PAD_8MA,
++		.strength	= PAD_4MA,
 +		.pull		= 1,
 +		.pullup		= 1,
 +		.voltage	= PAD_3_3V,
@@ -604,7 +604,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.name		= "ENET1_TXD1",
 +		.id		= PINID_ENET0_TXD3,
 +		.fun		= PIN_FUN2,
-+		.strength	= PAD_8MA,
++		.strength	= PAD_4MA,
 +		.pull		= 1,
 +		.pullup		= 1,
 +		.voltage	= PAD_3_3V,
diff --git a/patches/u-boot/2012.04/502-add-apf28.patch b/patches/u-boot/2012.04/502-add-apf28.patch
index 474fe2a..abd0e09 100644
--- a/patches/u-boot/2012.04/502-add-apf28.patch
+++ b/patches/u-boot/2012.04/502-add-apf28.patch
@@ -135,7 +135,7 @@ index 0000000..c00b55c
 +
 +#ifdef	CONFIG_CMD_USB
 +	mxs_iomux_setup_pad(MX28_PAD_LCD_D23__GPIO_1_23 |
-+			MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
++			MXS_PAD_4MA | MXS_PAD_3V3 | MXS_PAD_NOPULL);
 +	gpio_direction_output(MX28_PAD_LCD_D23__GPIO_1_23, 0);
 +#endif
 +
@@ -1115,7 +1115,7 @@ new file mode 100644
 index 0000000..3769d44
 --- /dev/null
 +++ b/board/armadeus/apf28/spl_boot.c
-@@ -0,0 +1,203 @@
+@@ -0,0 +1,202 @@
 +/*
 + * Freescale i.MX28 Boot setup for the APF28 board
 + *
@@ -1150,18 +1150,18 @@ index 0000000..3769d44
 +#include <asm/arch/sys_proto.h>
 +
 +#define	MUX_CONFIG_LED	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
-+#define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP)
-+#define	MUX_CONFIG_GPMI	(MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
++#define	MUX_CONFIG_SSP0	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
++#define	MUX_CONFIG_GPMI	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
 +#define	MUX_CONFIG_ENET	(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
-+#define	MUX_CONFIG_EMI	(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL)
++#define	MUX_CONFIG_EMI	(MXS_PAD_1V8 | MXS_PAD_4MA | MXS_PAD_NOPULL)
 +
 +const iomux_cfg_t iomux_setup[] = {
 +	/* LED */
 +	MX28_PAD_GPMI_RDY1__GPIO_0_21 | MUX_CONFIG_LED,
 +
 +	/* DEBUG UART (console) */
-+	MX28_PAD_PWM0__DUART_RX,
-+	MX28_PAD_PWM1__DUART_TX,
++	MX28_PAD_PWM0__DUART_RX | (MXS_PAD_3V3 | MXS_PAD_4MA),
++	MX28_PAD_PWM1__DUART_TX | (MXS_PAD_3V3 | MXS_PAD_4MA),
 +
 +	/* MMC0 */
 +	MX28_PAD_SSP0_DATA0__SSP0_D0 | MUX_CONFIG_SSP0,
@@ -1170,9 +1170,9 @@ index 0000000..3769d44
 +	MX28_PAD_SSP0_DATA3__SSP0_D3 | MUX_CONFIG_SSP0,
 +	MX28_PAD_SSP0_CMD__SSP0_CMD | MUX_CONFIG_SSP0,
 +	MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT |
-+		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
++		(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL),
 +	MX28_PAD_SSP0_SCK__SSP0_SCK |
-+		(MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL),
++		(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL),
 +
 +	/* GPMI NAND */
 +	MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI,
@@ -1185,8 +1185,7 @@ index 0000000..3769d44
 +	MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI,
 +	MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI,
 +	MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI,
-+	MX28_PAD_GPMI_RDN__GPMI_RDN |
-+		(MXS_PAD_1V8 | MXS_PAD_8MA | MXS_PAD_PULLUP),
++	MX28_PAD_GPMI_RDN__GPMI_RDN | MUX_CONFIG_GPMI,
 +	MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI,
 +	MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI,
 +	MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI,


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-347-g36fb390

From: jorasse <jo...@us...> - 2012-06-05 22:37:09

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  36fb390e8668a19db8b0812d8bb9ee1728fb90ca (commit)
      from  f01d0e03f016c25082423e9e36e2f0cc02f0c908 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 36fb390e8668a19db8b0812d8bb9ee1728fb90ca
Author: Eric Jarrige <eri...@ar...>
Date:   Wed Jun 6 00:37:53 2012 +0200

    [LINUX] apf28dev config: set UART ports to DMA mode

-----------------------------------------------------------------------

Summary of changes:
 .../armadeus/apf28/apf28-linux-2.6.35.config       |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config b/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
index 8a7389e..fc9bb0b 100644
--- a/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
+++ b/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
@@ -274,13 +274,13 @@ CONFIG_MXS_PWM_CHANNELS=8
 CONFIG_MXS_AUART_DMA_SUPPORT=y
 CONFIG_MXS_AUART_PORTS=5
 CONFIG_MXS_AUART0_DEVICE_ENABLE=y
-# CONFIG_MXS_AUART0_DMA_ENABLE is not set
+CONFIG_MXS_AUART0_DMA_ENABLE=y
 # CONFIG_MXS_AUART1_DEVICE_ENABLE is not set
 # CONFIG_MXS_AUART1_DMA_ENABLE is not set
 CONFIG_MXS_AUART2_DEVICE_ENABLE=y
-# CONFIG_MXS_AUART2_DMA_ENABLE is not set
+CONFIG_MXS_AUART2_DMA_ENABLE=y
 CONFIG_MXS_AUART3_DEVICE_ENABLE=y
-# CONFIG_MXS_AUART3_DMA_ENABLE is not set
+CONFIG_MXS_AUART3_DMA_ENABLE=y
 # CONFIG_MXS_AUART4_DEVICE_ENABLE is not set
 # CONFIG_MXS_AUART4_DMA_ENABLE is not set
 CONFIG_MXS_RAM_FREQ_SCALING=y


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-346-gf01d0e0

From: jorasse <jo...@us...> - 2012-06-05 15:01:24

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  f01d0e03f016c25082423e9e36e2f0cc02f0c908 (commit)
      from  c76fbbb105f050f9db8d94fc5521c88b63193da8 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit f01d0e03f016c25082423e9e36e2f0cc02f0c908
Author: Eric Jarrige <eri...@ar...>
Date:   Tue Jun 5 17:01:26 2012 +0200

    [LINUX] apf28: Enable GPIO LED and LED triggers - This activates the board LED and Heartbeat trigger by default

-----------------------------------------------------------------------

Summary of changes:
 .../armadeus/apf28/apf28-linux-2.6.35.config       |   19 +++++++++++++++++--
 1 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config b/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
index 850108f..8a7389e 100644
--- a/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
+++ b/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
@@ -555,6 +555,7 @@ CONFIG_MAC80211_RC_DEFAULT="minstrel"
 # CONFIG_MAC80211_DEBUG_MENU is not set
 # CONFIG_WIMAX is not set
 CONFIG_RFKILL=y
+CONFIG_RFKILL_LEDS=y
 CONFIG_RFKILL_INPUT=y
 # CONFIG_NET_9P is not set
 # CONFIG_CAIF is not set
@@ -1707,14 +1708,28 @@ CONFIG_LEDS_CLASS=y
 #
 CONFIG_LEDS_MXS=y
 # CONFIG_LEDS_PCA9532 is not set
-# CONFIG_LEDS_GPIO is not set
+CONFIG_LEDS_GPIO=y
+CONFIG_LEDS_GPIO_PLATFORM=y
 # CONFIG_LEDS_LP3944 is not set
 # CONFIG_LEDS_PCA955X is not set
 # CONFIG_LEDS_DAC124S085 is not set
 # CONFIG_LEDS_REGULATOR is not set
 # CONFIG_LEDS_BD2802 is not set
 # CONFIG_LEDS_LT3593 is not set
-# CONFIG_LEDS_TRIGGERS is not set
+CONFIG_LEDS_TRIGGERS=y
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGER_TIMER=y
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+CONFIG_LEDS_TRIGGER_BACKLIGHT=y
+CONFIG_LEDS_TRIGGER_GPIO=y
+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
+
+#
+# iptables trigger is under Netfilter config (LED target)
+#
 # CONFIG_ACCESSIBILITY is not set
 CONFIG_RTC_LIB=y
 CONFIG_RTC_CLASS=y


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-345-gc76fbbb

From: jorasse <jo...@us...> - 2012-06-05 14:54:43

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  c76fbbb105f050f9db8d94fc5521c88b63193da8 (commit)
      from  0ced2f35807aa8fb334c4b17e2b332208a62d582 (commit)

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not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit c76fbbb105f050f9db8d94fc5521c88b63193da8
Author: Eric Jarrige <eri...@ar...>
Date:   Tue Jun 5 16:55:14 2012 +0200

    [LINUX] apf28: update power management gorvernances and set conservative mode the default for this board

-----------------------------------------------------------------------

Summary of changes:
 .../armadeus/apf28/apf28-linux-2.6.35.config       |   12 +++++++-----
 1 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config b/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
index 275ad2f..850108f 100644
--- a/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
+++ b/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
@@ -374,15 +374,17 @@ CONFIG_CPU_FREQ_STAT=y
 # CONFIG_CPU_FREQ_STAT_DETAILS is not set
 # CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE is not set
 # CONFIG_CPU_FREQ_DEFAULT_GOV_POWERSAVE is not set
-CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE=y
+# CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set
 # CONFIG_CPU_FREQ_DEFAULT_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE is not set
+CONFIG_CPU_FREQ_DEFAULT_GOV_CONSERVATIVE=y
 CONFIG_CPU_FREQ_GOV_PERFORMANCE=y
 CONFIG_CPU_FREQ_GOV_POWERSAVE=y
 CONFIG_CPU_FREQ_GOV_USERSPACE=y
-# CONFIG_CPU_FREQ_GOV_ONDEMAND is not set
-# CONFIG_CPU_FREQ_GOV_CONSERVATIVE is not set
-# CONFIG_CPU_IDLE is not set
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
+CONFIG_CPU_IDLE_GOV_LADDER=y
+CONFIG_CPU_IDLE_GOV_MENU=y
 
 #
 # Floating point emulation


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-344-g0ced2f3

From: jorasse <jo...@us...> - 2012-06-05 14:43:16

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  0ced2f35807aa8fb334c4b17e2b332208a62d582 (commit)
      from  e2c89f4e9c03fc5854e822c292093e8f3a859b63 (commit)

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not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 0ced2f35807aa8fb334c4b17e2b332208a62d582
Author: Eric Jarrige <eri...@ar...>
Date:   Tue Jun 5 16:44:09 2012 +0200

    [UBOOT] apf28: bump to U-Boot 2012.04.01

-----------------------------------------------------------------------

Summary of changes:
 buildroot/configs/apf28_defconfig                  |    2 +-
 .../device/armadeus/apf28/apf28-u-boot-2012.04.h   |    1 +
 2 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/buildroot/configs/apf28_defconfig b/buildroot/configs/apf28_defconfig
index 38a08bb..63a4cfe 100644
--- a/buildroot/configs/apf28_defconfig
+++ b/buildroot/configs/apf28_defconfig
@@ -63,7 +63,7 @@ BR2_TARGET_UBOOT=y
 BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
 BR2_TARGET_UBOOT_CONFIG_HEADER_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2012.04.h"
 BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2012.04.tar.bz2"
+BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2012.04.01.tar.bz2"
 BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2012.04"
 BR2_TARGET_UBOOT_FORMAT_SB=y
 BR2_TARGET_UBOOT_NETWORK=y
diff --git a/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h b/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h
index b1ed6fa..a864a16 100644
--- a/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h
+++ b/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h
@@ -44,6 +44,7 @@
 #define CONFIG_BOARD_LATE_INIT
 #define	CONFIG_ARCH_CPU_INIT
 #define	CONFIG_ARCH_MISC_INIT
+#define CONFIG_APBH_DMA
 
 /*
  * Board display option


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-343-ge2c89f4

From: jorasse <jo...@us...> - 2012-06-04 14:57:09

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  e2c89f4e9c03fc5854e822c292093e8f3a859b63 (commit)
      from  bd953cb9415fe1ed333fb7b57f2fd826f0ed79f3 (commit)

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- Log -----------------------------------------------------------------
commit e2c89f4e9c03fc5854e822c292093e8f3a859b63
Author: Eric Jarrige <eri...@ar...>
Date:   Mon Jun 4 16:57:19 2012 +0200

    [LINUX] mx28: Fix mx28 pin init transition

-----------------------------------------------------------------------

Summary of changes:
 ...456-armadeus-mx28_fix_pin_init_transition.patch |   17 +++++++++++++++++
 1 files changed, 17 insertions(+), 0 deletions(-)
 create mode 100644 patches/linux/2.6.35/456-armadeus-mx28_fix_pin_init_transition.patch

diff --git a/patches/linux/2.6.35/456-armadeus-mx28_fix_pin_init_transition.patch b/patches/linux/2.6.35/456-armadeus-mx28_fix_pin_init_transition.patch
new file mode 100644
index 0000000..7387fff
--- /dev/null
+++ b/patches/linux/2.6.35/456-armadeus-mx28_fix_pin_init_transition.patch
@@ -0,0 +1,17 @@
+Fix mx28 pin init transition.
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+Index: linux-2.6.35.3/arch/arm/mach-mx28/pinctrl.c
+===================================================================
+--- linux-2.6.35.3/arch/arm/mach-mx28/pinctrl.c
++++ linux-2.6.35.3/arch/arm/mach-mx28/pinctrl.c
+@@ -92,7 +92,7 @@ static void mx28_set_type(struct pin_ban
+ 	addr += 0x20 * bank->id + 0x10 * (id >> 4);
+ 	id &= 0xF;
+ 	id *= 2;
+-	__raw_writel(0x3 << id, addr + CLR_REGISTER);
++	__raw_writel(((~cfg)&0x3) << id, addr + CLR_REGISTER);
+ 	__raw_writel(cfg << id, addr + SET_REGISTER);
+ }
+ 


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-342-gbd953cb

From: jorasse <jo...@us...> - 2012-06-04 14:45:01

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  bd953cb9415fe1ed333fb7b57f2fd826f0ed79f3 (commit)
      from  5a88f24ae2075de21746407f41d7064a5e409282 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit bd953cb9415fe1ed333fb7b57f2fd826f0ed79f3
Author: Eric Jarrige <eri...@ar...>
Date:   Mon Jun 4 16:45:39 2012 +0200

    [LINUX] apf28: refactor NAND flash integration

-----------------------------------------------------------------------

Summary of changes:
 .../450-armadeus-add_apf28_module_support.patch    |  252 +++++++++++++++++++-
 .../453-armadeus-disable-nand-boot-area.patch      |   19 --
 2 files changed, 240 insertions(+), 31 deletions(-)
 delete mode 100644 patches/linux/2.6.35/453-armadeus-disable-nand-boot-area.patch

diff --git a/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch b/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch
index 91d6d70..2985a03 100644
--- a/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch
+++ b/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch
@@ -37,7 +37,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
 +++ linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c	2012-02-03 17:39:56.000000000 +0100
-@@ -0,0 +1,401 @@
+@@ -0,0 +1,629 @@
 +/*
 + * Copyright (C) 2012 Armadeus systems
 + *
@@ -60,30 +60,31 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 + */
 +
 +#include <linux/kernel.h>
-+#include <linux/init.h>
-+#include <linux/io.h>
-+#include <linux/err.h>
 +#include <linux/clk.h>
-+#include <linux/platform_device.h>
 +#include <linux/delay.h>
++#include <linux/err.h>
 +#include <linux/fec.h>
++#include <linux/gpmi-nfc.h>
++#include <linux/io.h>
++#include <linux/init.h>
++#include <linux/mtd/mtd.h>
++#include <linux/mtd/partitions.h>
++#include <linux/mtd/physmap.h>
++#include <linux/platform_device.h>
 +
 +#include <asm/setup.h>
 +#include <asm/mach-types.h>
 +#include <asm/mach/arch.h>
 +
 +#include <mach/apf28.h>
-+#include <mach/hardware.h>
 +#include <mach/device.h>
++#include <mach/dma.h>
++#include <mach/hardware.h>
 +#include <mach/pinctrl.h>
 +#include <mach/regs-ocotp.h>
 +
-+#include <linux/mtd/mtd.h>
-+#include <linux/mtd/partitions.h>
-+#include <linux/mtd/physmap.h>
-+
-+#include "mx28_pins.h"
 +#include "device.h"
++#include "mx28_pins.h"
 +
 +static struct pin_desc apf28_fixed_pins[] = {
 +	{
@@ -96,6 +97,143 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +		.id		= PINID_PWM1,
 +		.fun		= PIN_FUN3,
 +	},
++#if defined(CONFIG_MTD_NAND_GPMI_NFC)
++	{
++		.name		= "GPMI D0",
++		.id		= PINID_GPMI_D00,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= !0
++	},
++	{
++		.name		= "GPMI D1",
++		.id		= PINID_GPMI_D01,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= !0
++	},
++	{
++		.name		= "GPMI D2",
++		.id		= PINID_GPMI_D02,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= !0
++	},
++	{
++		.name		= "GPMI D3",
++		.id		= PINID_GPMI_D03,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= !0
++	},
++	{
++		.name		= "GPMI D4",
++		.id		= PINID_GPMI_D04,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= !0
++	},
++	{
++		.name		= "GPMI D5",
++		.id		= PINID_GPMI_D05,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= !0
++	},
++	{
++		.name		= "GPMI D6",
++		.id		= PINID_GPMI_D06,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= !0
++	},
++	{
++		.name		= "GPMI D7",
++		.id		= PINID_GPMI_D07,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= !0
++	},
++	{
++		.name		= "GPMI CE0-",
++		.id		= PINID_GPMI_CE0N,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= !0
++	},
++	{
++		.name		= "GPMI RDY0",
++		.id		= PINID_GPMI_RDY0,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= !0
++	},
++	{
++		.name		= "GPMI RD-",
++		.id		= PINID_GPMI_RDN,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_12MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= !0
++	},
++	{
++		.name		= "GPMI WR-",
++		.id		= PINID_GPMI_WRN,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_12MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= !0
++	},
++	{
++		.name		= "GPMI ALE",
++		.id		= PINID_GPMI_ALE,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= !0
++	},
++	{
++		.name		= "GPMI CLE",
++		.id		= PINID_GPMI_CLE,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= !0
++	},
++	{
++		.name		= "GPMI RST-",
++		.id		= PINID_GPMI_RESETN,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_12MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= !0
++	},
++#endif /* defined(CONFIG_MTD_NAND_GPMI_NFC) */
 +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\
 +	|| defined(CONFIG_FEC_L2SWITCH)
 +	{
@@ -214,11 +352,100 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +#endif /* defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) */
 +};
 +
++#if defined(CONFIG_MTD_NAND_GPMI_NFC)
++
++static int apf28_gpmi_nfc_platform_init(unsigned int max_chip_count)
++{
++	return 0;
++}
++
++static void apf28_gpmi_nfc_platform_exit(unsigned int max_chip_count)
++{
++}
++
++static const char *apf28_gpmi_nfc_partition_source_types[] =
++	{ "cmdlinepart", 0 };
++
++static struct gpmi_nfc_platform_data  apf28_gpmi_nfc_platform_data = {
++	.nfc_version             = 1,
++	.boot_rom_version        = 1,
++	.clock_name              = "gpmi",
++	.platform_init           = apf28_gpmi_nfc_platform_init,
++	.platform_exit           = apf28_gpmi_nfc_platform_exit,
++	.min_prop_delay_in_ns    = 5,
++	.max_prop_delay_in_ns    = 9,
++	.max_chip_count          = 1,
++	.boot_area_size_in_bytes = 0 * SZ_1M,
++	.partition_source_types  = apf28_gpmi_nfc_partition_source_types,
++	.partitions              = 0,
++	.partition_count         = 0,
++};
++
++static struct resource gpmi_nfc_resources[] = {
++	{
++	 .name  = GPMI_NFC_GPMI_REGS_ADDR_RES_NAME,
++	 .flags = IORESOURCE_MEM,
++	 .start = GPMI_PHYS_ADDR,
++	 .end   = GPMI_PHYS_ADDR + SZ_8K - 1,
++	 },
++	{
++	 .name  = GPMI_NFC_GPMI_INTERRUPT_RES_NAME,
++	 .flags = IORESOURCE_IRQ,
++	 .start = IRQ_GPMI,
++	 .end   = IRQ_GPMI,
++	},
++	{
++	 .name  = GPMI_NFC_BCH_REGS_ADDR_RES_NAME,
++	 .flags = IORESOURCE_MEM,
++	 .start = BCH_PHYS_ADDR,
++	 .end   = BCH_PHYS_ADDR + SZ_8K - 1,
++	 },
++	{
++	 .name  = GPMI_NFC_BCH_INTERRUPT_RES_NAME,
++	 .flags = IORESOURCE_IRQ,
++	 .start = IRQ_BCH,
++	 .end   = IRQ_BCH,
++	 },
++	{
++	 .name  = GPMI_NFC_DMA_CHANNELS_RES_NAME,
++	 .flags = IORESOURCE_DMA,
++	 .start	= MXS_DMA_CHANNEL_AHB_APBH_GPMI0,
++	 .end	= MXS_DMA_CHANNEL_AHB_APBH_GPMI7,
++	 },
++	{
++	 .name  = GPMI_NFC_DMA_INTERRUPT_RES_NAME,
++	 .flags = IORESOURCE_IRQ,
++	 .start = IRQ_GPMI_DMA,
++	 .end   = IRQ_GPMI_DMA,
++	},
++};
++
++static void __init apf28_init_gpmi_nfc(void)
++{
++	struct platform_device  *pdev;
++
++	pdev = mxs_get_device(GPMI_NFC_DRIVER_NAME, 0);
++	if (pdev == NULL || IS_ERR(pdev))
++		return;
++	pdev->dev.platform_data = &apf28_gpmi_nfc_platform_data;
++	pdev->resource =  gpmi_nfc_resources;
++	pdev->num_resources = ARRAY_SIZE(gpmi_nfc_resources);
++	mxs_add_device(pdev, 1);
++	mxs_get_devices(GPMI_NFC_DRIVER_NAME);	/* to lock the ressource */
++}
++#else
++static void apf28_init_gpmi_nfc(void)
++{
++}
++#endif
++
++
 +/*
 + * Stub implementations for mx287 FEC1 init to be overloaded in the baseboard
 + * source code.
 + */
-+int __mx287_fec1_gpio_init(void) {
++int __mx287_fec1_gpio_init(void)
++{
 +	return 0;
 +}
 +
@@ -419,6 +646,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +#endif
 +
 +	apf28_init_fec();
++	apf28_init_gpmi_nfc();
 +
 +	mx28_device_init();
 +	apf28_device_init();
diff --git a/patches/linux/2.6.35/453-armadeus-disable-nand-boot-area.patch b/patches/linux/2.6.35/453-armadeus-disable-nand-boot-area.patch
deleted file mode 100644
index 1f2c55a..0000000
--- a/patches/linux/2.6.35/453-armadeus-disable-nand-boot-area.patch
+++ /dev/null
@@ -1,19 +0,0 @@
-Quick fix to fully support NAND address space for board memory partitions -
-therefore this add support for any commandline partition.
-
-Signed-off-by: Eric Jarrige <eri...@ar...>
----
-Index: linux-2.6.35.3/arch/arm/mach-mx28/device.c
-===================================================================
---- linux-2.6.35.3/arch/arm/mach-mx28/device.c	2012-03-12 12:29:25.000000000 +0100
-+++ linux-2.6.35.3/arch/arm/mach-mx28/device.c	2012-03-13 23:28:56.000000000 +0100
-@@ -357,7 +357,9 @@ static struct gpmi_nfc_platform_data  gp
- 	.min_prop_delay_in_ns    = 5,
- 	.max_prop_delay_in_ns    = 9,
- 	.max_chip_count          = 2,
-+#if defined(CONFIG_MACH_MX28EVK)
- 	.boot_area_size_in_bytes = 20 * SZ_1M,
-+#endif
- 	.partition_source_types  = gpmi_nfc_partition_source_types,
- 	.partitions              = 0,
- 	.partition_count         = 0,


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armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-341-g5a88f24

From: jorasse <jo...@us...> - 2012-06-03 23:37:58

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  5a88f24ae2075de21746407f41d7064a5e409282 (commit)
      from  554078a05867c6badbb8d8df3d6c68677e51cfc9 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 5a88f24ae2075de21746407f41d7064a5e409282
Author: Eric Jarrige <eri...@ar...>
Date:   Mon Jun 4 01:38:35 2012 +0200

    [LINUX] APF28: update armadeus patches

-----------------------------------------------------------------------

Summary of changes:
 .../452-armadeus-mxs-fixes_USB_freescale_bsp.patch |   99 ++++++++++++++++++++
 .../452-armadeus-mxs-fixes_freescale_bsp.patch     |   93 ------------------
 2 files changed, 99 insertions(+), 93 deletions(-)
 create mode 100644 patches/linux/2.6.35/452-armadeus-mxs-fixes_USB_freescale_bsp.patch

diff --git a/patches/linux/2.6.35/452-armadeus-mxs-fixes_USB_freescale_bsp.patch b/patches/linux/2.6.35/452-armadeus-mxs-fixes_USB_freescale_bsp.patch
new file mode 100644
index 0000000..752bb41
--- /dev/null
+++ b/patches/linux/2.6.35/452-armadeus-mxs-fixes_USB_freescale_bsp.patch
@@ -0,0 +1,99 @@
+USB (i.MX28) fixes to Freescale's 2.6.35 BSP + USB OTG option to enforce mode
+
+Signed-off-by: Julien Boibessot <jul...@ar...>
+
+Index: linux-2.6.35.3/arch/arm/mach-mx28/usb_dr.c
+===================================================================
+--- linux-2.6.35.3.orig/arch/arm/mach-mx28/usb_dr.c	2012-02-03 12:57:41.000000000 +0100
++++ linux-2.6.35.3/arch/arm/mach-mx28/usb_dr.c	2012-02-03 12:57:55.000000000 +0100
+@@ -29,7 +29,13 @@
+ #include <mach/arc_otg.h>
+ #include "usb.h"
+ #include "mx28_pins.h"
++#if defined(CONFIG_MACH_MX28EVK)
+ #define USB_POWER_ENABLE MXS_PIN_TO_GPIO(PINID_AUART2_TX)
++#define USB_OTG_ID MXS_PIN_TO_GPIO(PINID_AUART2_TX)
++#else
++#define USB_POWER_ENABLE MXS_PIN_TO_GPIO(PINID_LCD_D23)
++#define USB_OTG_ID MXS_PIN_TO_GPIO(PINID_PWM2)
++#endif
+ 
+ #ifdef CONFIG_WORKAROUND_ARCUSB_REG_RW
+ static void fsl_safe_writel(u32 val32, volatile u32 *addr)
+@@ -40,6 +46,7 @@ static void fsl_safe_writel(u32 val32, v
+ extern int clk_get_usecount(struct clk *clk);
+ static struct clk *usb_clk;
+ static struct clk *usb_phy_clk;
++static int otg_mode_host = -1;
+ 
+ void fsl_phy_usb_utmi_init(struct fsl_xcvr_ops *this)
+ {
+@@ -58,14 +65,20 @@ void fsl_phy_usb_utmi_uninit(struct fsl_
+ void fsl_phy_set_power(struct fsl_xcvr_ops *this,
+ 			struct fsl_usb2_platform_data *pdata, int on)
+ {
+-#if defined(CONFIG_MACH_MX28EVK)
+-	/* USB_POWER_ENABLE_PIN have request at pin init*/
+-	if (pdata->phy_regs != USBPHY1_PHYS_ADDR) {
+-		pr_debug("%s: on is %d\n", __func__, on);
+-		gpio_direction_output(USB_POWER_ENABLE, on);
+-		gpio_set_value(USB_POWER_ENABLE, on);
++	if (otg_mode_host == 1){
++		gpio_direction_output(USB_POWER_ENABLE, 1);
++		gpio_set_value(USB_POWER_ENABLE, 1);
++	} else if (otg_mode_host == 0){
++		gpio_direction_output(USB_POWER_ENABLE, 0);
++		gpio_set_value(USB_POWER_ENABLE, 0);
++	} else {		
++		/* USB_POWER_ENABLE_PIN have request at pin init*/
++		if (pdata->phy_regs != USBPHY1_PHYS_ADDR) {
++			pr_debug("%s: on is %d\n", __func__, on);
++			gpio_direction_output(USB_POWER_ENABLE, on);
++			gpio_set_value(USB_POWER_ENABLE, on);
++		}
+ 	}
+-#endif
+ }
+ 
+ static void usb_host_phy_resume(struct fsl_usb2_platform_data *plat)
+@@ -365,6 +378,7 @@ static struct fsl_usb2_platform_data __m
+ 	.platform_resume = usb_host_phy_resume,
+ 	.transceiver       = "utmi",
+ 	.phy_regs          = USBPHY0_PHYS_ADDR,
++	.id_gpio 	   = USB_OTG_ID,
+ };
+ 
+ /*
+@@ -459,6 +473,18 @@ static struct fsl_usb2_wakeup_platform_d
+ 	.usb_clock_for_pm  = usbotg_clock_gate,
+ };
+ 
++static int __init apf28_otg_mode(char *options)
++{
++	if (!strcmp(options, "host"))
++		otg_mode_host = 1;
++	else if (!strcmp(options, "device"))
++		otg_mode_host = 0;
++
++	return 0;
++}
++__setup("otg_mode=", apf28_otg_mode);
++
++
+ static int __init usb_dr_init(void)
+ {
+ 	struct platform_device *pdev;
+@@ -474,6 +500,13 @@ static int __init usb_dr_init(void)
+ 	dr_utmi_config.irq_delay = 0;
+ 	dr_utmi_config.wakeup_pdata = &usbdr_wakeup_config;
+ 
++	if (otg_mode_host == 1) { /*mode defined by bootloader options*/
++		printk("OTG mode forced to HOST\n");
++		dr_utmi_config.id_gpio = 0;  /* do not manage the ID pin */
++		gpio_direction_output(USB_POWER_ENABLE, 1);
++		gpio_set_value(USB_POWER_ENABLE, 1);		
++	}
++
+ 	if (platform_device_register(&dr_otg_device))
+ 		printk(KERN_ERR "usb DR: can't register otg device\n");
+ 	else {
diff --git a/patches/linux/2.6.35/452-armadeus-mxs-fixes_freescale_bsp.patch b/patches/linux/2.6.35/452-armadeus-mxs-fixes_freescale_bsp.patch
index d286f8f..9be0eb6 100644
--- a/patches/linux/2.6.35/452-armadeus-mxs-fixes_freescale_bsp.patch
+++ b/patches/linux/2.6.35/452-armadeus-mxs-fixes_freescale_bsp.patch
@@ -76,96 +76,3 @@ Index: linux-2.6.35.3/drivers/input/touchscreen/mxs-ts.c
 +MODULE_DESCRIPTION("MXS input touchscreen driver");
 +MODULE_AUTHOR("Vitaly Wool <vi...@em...>");
 +MODULE_LICENSE("GPL v2");
-Index: linux-2.6.35.3/arch/arm/mach-mx28/usb_dr.c
-===================================================================
---- linux-2.6.35.3.orig/arch/arm/mach-mx28/usb_dr.c	2012-02-03 12:57:41.000000000 +0100
-+++ linux-2.6.35.3/arch/arm/mach-mx28/usb_dr.c	2012-02-03 12:57:55.000000000 +0100
-@@ -29,11 +29,19 @@
- #include <mach/arc_otg.h>
- #include "usb.h"
- #include "mx28_pins.h"
-+
-+#if defined(CONFIG_MACH_MX28EVK)
- #define USB_POWER_ENABLE MXS_PIN_TO_GPIO(PINID_AUART2_TX)
-+#define USB_OTG_ID MXS_PIN_TO_GPIO(PINID_AUART2_TX)
-+#else
-+#define USB_POWER_ENABLE MXS_PIN_TO_GPIO(PINID_LCD_D23)
-+#define USB_OTG_ID MXS_PIN_TO_GPIO(PINID_PWM2)
-+#endif
- 
- extern int clk_get_usecount(struct clk *clk);
- static struct clk *usb_clk;
- static struct clk *usb_phy_clk;
-+static int otg_mode_host = -1;
- 
- void fsl_phy_usb_utmi_init(struct fsl_xcvr_ops *this)
- {
-@@ -52,14 +60,20 @@ void fsl_phy_usb_utmi_uninit(struct fsl_
- void fsl_phy_set_power(struct fsl_xcvr_ops *this,
- 			struct fsl_usb2_platform_data *pdata, int on)
- {
--#if defined(CONFIG_MACH_MX28EVK)
--	/* USB_POWER_ENABLE_PIN have request at pin init*/
--	if (pdata->phy_regs != USBPHY1_PHYS_ADDR) {
--		pr_debug("%s: on is %d\n", __func__, on);
--		gpio_direction_output(USB_POWER_ENABLE, on);
--		gpio_set_value(USB_POWER_ENABLE, on);
-+	if (otg_mode_host == 1){
-+		gpio_direction_output(USB_POWER_ENABLE, 1);
-+		gpio_set_value(USB_POWER_ENABLE, 1);
-+	} else if (otg_mode_host == 0){
-+		gpio_direction_output(USB_POWER_ENABLE, 0);
-+		gpio_set_value(USB_POWER_ENABLE, 0);
-+	} else {		
-+		/* USB_POWER_ENABLE_PIN have request at pin init*/
-+		if (pdata->phy_regs != USBPHY1_PHYS_ADDR) {
-+			pr_debug("%s: on is %d\n", __func__, on);
-+			gpio_direction_output(USB_POWER_ENABLE, on);
-+			gpio_set_value(USB_POWER_ENABLE, on);
-+		}
- 	}
--#endif
- }
- 
- static void usb_host_phy_resume(struct fsl_usb2_platform_data *plat)
-@@ -359,6 +373,7 @@ static struct fsl_usb2_platform_data __m
- 	.platform_resume = usb_host_phy_resume,
- 	.transceiver       = "utmi",
- 	.phy_regs          = USBPHY0_PHYS_ADDR,
-+	.id_gpio 	   = USB_OTG_ID,
- };
- 
- /*
-@@ -453,6 +468,18 @@ static struct fsl_usb2_wakeup_platform_d
- 	.usb_clock_for_pm  = usbotg_clock_gate,
- };
- 
-+static int __init apf28_otg_mode(char *options)
-+{
-+	if (!strcmp(options, "host"))
-+		otg_mode_host = 1;
-+	else if (!strcmp(options, "device"))
-+		otg_mode_host = 0;
-+
-+	return 0;
-+}
-+__setup("otg_mode=", apf28_otg_mode);
-+
-+
- static int __init usb_dr_init(void)
- {
- 	struct platform_device *pdev;
-@@ -468,6 +495,13 @@ static int __init usb_dr_init(void)
- 	dr_utmi_config.irq_delay = 0;
- 	dr_utmi_config.wakeup_pdata = &usbdr_wakeup_config;
- 
-+	if (otg_mode_host == 1) { /*mode defined by bootloader options*/
-+		printk("OTG mode forced to HOST\n");
-+		dr_utmi_config.id_gpio = 0;  /* do not manage the ID pin */
-+		gpio_direction_output(USB_POWER_ENABLE, 1);
-+		gpio_set_value(USB_POWER_ENABLE, 1);		
-+	}
-+
- 	if (platform_device_register(&dr_otg_device))
- 		printk(KERN_ERR "usb DR: can't register otg device\n");
- 	else {


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-340-g554078a

From: jorasse <jo...@us...> - 2012-06-03 23:00:45

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  554078a05867c6badbb8d8df3d6c68677e51cfc9 (commit)
      from  2683f8b966834c1e2a632de99b1c138ebd1f853a (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 554078a05867c6badbb8d8df3d6c68677e51cfc9
Author: Eric Jarrige <eri...@ar...>
Date:   Mon Jun 4 01:01:18 2012 +0200

    [UBOOT] update apf9328 config file for U-Boot 2012.04

-----------------------------------------------------------------------

Summary of changes:
 ...8-u-boot-2011.12.h => apf9328-u-boot-2012.04.h} |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)
 copy buildroot/target/device/armadeus/apf9328/{apf9328-u-boot-2011.12.h => apf9328-u-boot-2012.04.h} (99%)

diff --git a/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2011.12.h b/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2012.04.h
similarity index 99%
copy from buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2011.12.h
copy to buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2012.04.h
index f0c6def..12ab4bd 100644
--- a/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2011.12.h
+++ b/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2012.04.h
@@ -24,7 +24,7 @@
 
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_ENV_VERSION 	"5.1"
-#define CONFIG_IDENT_STRING	" apf9328 patch 5.2"
+#define CONFIG_IDENT_STRING	" apf9328 patch 5.3"
 #define CONFIG_BOARD_NAME	apf9328
 
 /*


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-339-g2683f8b

From: jorasse <jo...@us...> - 2012-06-03 18:33:46

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  2683f8b966834c1e2a632de99b1c138ebd1f853a (commit)
      from  009939f74d84757013559aa1f21d9e164179538d (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 2683f8b966834c1e2a632de99b1c138ebd1f853a
Author: Eric Jarrige <eri...@ar...>
Date:   Sun Jun 3 20:34:12 2012 +0200

    [LINUX] apf28: add missing Freescale patches - These patches aim to fix many mx28 issues

-----------------------------------------------------------------------

Summary of changes:
 buildroot/configs/apf28_defconfig                  |    2 +-
 .../187-apply-patches.sh_update_to_BR2012.05.patch |  151 ++++++++++++
 ...y-configuration-bug-fixes-and-improvement.patch |  247 ++++++++++++++++++++
 3 files changed, 399 insertions(+), 1 deletions(-)
 create mode 100644 patches/buildroot/2012.02/187-apply-patches.sh_update_to_BR2012.05.patch
 create mode 100755 patches/linux/2.6.35/455-freescale-0004-MX28-kernel-5V-only-configuration-bug-fixes-and-improvement.patch

diff --git a/buildroot/configs/apf28_defconfig b/buildroot/configs/apf28_defconfig
index cbb36f3..38a08bb 100644
--- a/buildroot/configs/apf28_defconfig
+++ b/buildroot/configs/apf28_defconfig
@@ -74,6 +74,6 @@ BR2_TARGET_UBOOT_ETHADDR=""
 BR2_LINUX_KERNEL=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION=y
 BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="2.6.35.3"
-BR2_LINUX_KERNEL_PATCH="ftp://ftp2.armadeus.com/armadeusw/linux-2.6.35.3-imx_10.12.01.patch.tar.gz ../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
+BR2_LINUX_KERNEL_PATCH="ftp://ftp2.armadeus.com/armadeusw/linux-2.6.35.3-imx_10.12.01.patch.tar.gz ftp://ftp2.armadeus.com/armadeusw/patches_for_L2.6.35_MX28_SDK_10.12_SOURCE.tar.gz ftp://ftp2.armadeus.com/armadeusw/L2.6.35_10.12_EMI_FREQ_PATCH_UP.tar.gz ftp://ftp2.armadeus.com/armadeusw/MX28-FEC-PROBLEM-PATCH.tar.gz ../patches/linux/$(BR2_LINUX_KERNEL_VERSION)"
 BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y
 BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-linux-$(BR2_LINUX_KERNEL_VERSION).config"
diff --git a/patches/buildroot/2012.02/187-apply-patches.sh_update_to_BR2012.05.patch b/patches/buildroot/2012.02/187-apply-patches.sh_update_to_BR2012.05.patch
new file mode 100644
index 0000000..57c6936
--- /dev/null
+++ b/patches/buildroot/2012.02/187-apply-patches.sh_update_to_BR2012.05.patch
@@ -0,0 +1,151 @@
+[apply-patches.sh] update to BR 2012.05 
+
+Fix open issues of BR 2012.02.
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+--- buildroot/support/scripts/apply-patches.sh
++++ buildroot/support/scripts/apply-patches.sh
+@@ -4,31 +4,55 @@
+ # -Erik
+ #
+ # (c) 2002 Erik Andersen <and...@co...>
++#
++# Parameters:
++# - the build directory, optional, default value is '.'. The place where are
++# the package sources.
++# - the patch directory, optional, default '../kernel-patches'. The place
++# where are the scripts you want to apply.
++# - other parameters are the patch name patterns, optional, default value is
++# '*'. Pattern(s) describing the patch names you want to apply.
++#
++# The script will look recursively for patches from the patch directory. If a
++# file is named 'series' then only patches mentionned into it will be applied.
++# If not, the script will look for file names matching pattern(s). If the name
++# ends with '.tar.*', '.tbz2' or '.tgz', the file is considered as an archive
++# and will be uncompressed into a directory named
++# '.patches-name_of_the_archive-unpacked'. It's the turn of this directory to
++# be scanned with '*' as pattern. Remember that scanning is recursive. Other
++# files than series file and archives are considered as a patch.
++#
++# Once a patch is found, the script will try to apply it. If its name doesn't
++# end with '.gz', '.bz', '.bz2', '.zip', '.Z', '.diff*' or '.patch*', it will
++# be skipped. If necessary, the patch will be uncompressed before being
++# applied. The list of the patches applied is stored in '.applied_patches_list'
++# file in the build directory.
+ 
+ # Set directories from arguments, or use defaults.
+-targetdir=${1-.}
++builddir=${1-.}
+ patchdir=${2-../kernel-patches}
+ shift 2
+ patchpattern=${@-*}
+ 
+-if [ ! -d "${targetdir}" ] ; then
+-    echo "Aborting.  '${targetdir}' is not a directory."
++if [ ! -d "${builddir}" ] ; then
++    echo "Aborting.  '${builddir}' is not a directory."
+     exit 1
+ fi
+ if [ ! -d "${patchdir}" ] ; then
+     echo "Aborting.  '${patchdir}' is not a directory."
+     exit 1
+ fi
+-    
+-for i in `cd ${patchdir}; ls -d ${patchpattern} 2> /dev/null` ; do 
+-    apply="patch -g0 -p1 -E -d"
+-    uncomp_parm=""
+-    if [ -d "${patchdir}/$i" ] ; then
+-	type="directory overlay"
+-	uncomp="tar cf - --exclude=.svn --no-anchored -C"
+-	uncomp_parm="."
+-	apply="tar xvf - -C"
+-    else case "$i" in
++
++# Remove any rejects present BEFORE patching - Because if there are
++# any, even if patches are well applied, at the end it will complain
++# about rejects in builddir.
++find ${builddir}/ '(' -name '*.rej' -o -name '.*.rej' ')' -print0 | \
++    xargs -0 -r rm -f
++
++function apply_patch {
++    path=$1
++    patch=$2
++    case "$patch" in
+ 	*.gz)
+ 	type="gzip"; uncomp="gunzip -dc"; ;; 
+ 	*.bz)
+@@ -39,28 +63,60 @@ for i in `cd ${patchdir}; ls -d ${patchp
+ 	type="zip"; uncomp="unzip -d"; ;; 
+ 	*.Z)
+ 	type="compress"; uncomp="uncompress -c"; ;; 
+-	*.tgz)
+-	type="tar gzip"; uncomp="gunzip -dc"; apply="tar xvf - -C"; ;; 
+-	*.tar)
+-	type="tar"; uncomp="cat"; apply="tar xvf - -C"; ;; 
++	*.diff*)
++	type="diff"; uncomp="cat"; ;;
++	*.patch*)
++	type="patch"; uncomp="cat"; ;;
+ 	*)
+-	type="plaintext"; uncomp="cat"; ;; 
+-    esac fi
++	echo "Unsupported format file for ${patch}, skip it";
++	return 0;
++	;;
++    esac
+     echo ""
+-    echo "Applying ${i} using ${type}: " 
+-	echo ${i} | cat >> ${targetdir}/.applied_patches_list
+-    ${uncomp} ${patchdir}/${i} ${uncomp_parm} | ${apply} ${targetdir} 
++    echo "Applying $patch using ${type}: "
++	echo $patch >> ${builddir}/.applied_patches_list
++    ${uncomp} "${path}/$patch" | patch -g0 -p1 -E -d "${builddir}"
+     if [ $? != 0 ] ; then
+-        echo "Patch failed!  Please fix $i!"
++        echo "Patch failed!  Please fix ${patch}!"
+ 	exit 1
+     fi
+-done
++}
++
++function scan_patchdir {
++    path=$1
++    shift 1
++    patches=${@-*}
++
++    # If there is a series file, use it instead of using ls sort order
++    # to apply patches. Skip line starting with a dash.
++    if [ -e "${path}/series" ] ; then
++        for i in `grep -Ev "^#" ${path}/series 2> /dev/null` ; do
++            apply_patch "$path" "$i" || exit 1
++        done
++    else
++        for i in `cd $path; ls -d $patches 2> /dev/null` ; do
++            if [ -d "${path}/$i" ] ; then
++                scan_patchdir "${path}/$i"
++            elif echo "$i" | grep -q -E "\.tar(\..*)?$|\.tbz2?$|\.tgz$" ; then
++                unpackedarchivedir="$builddir/.patches-$(basename $i)-unpacked"
++                rm -rf "$unpackedarchivedir" 2> /dev/null
++                mkdir "$unpackedarchivedir"
++                tar -C "$unpackedarchivedir" -xaf "${path}/$i"
++                scan_patchdir "$unpackedarchivedir"
++            else
++                apply_patch "$path" "$i" || exit 1
++            fi
++        done
++    fi
++}
++
++scan_patchdir "$patchdir" "$patchpattern"
+ 
+ # Check for rejects...
+-if [ "`find $targetdir/ '(' -name '*.rej' -o -name '.*.rej' ')' -print`" ] ; then
++if [ "`find $builddir/ '(' -name '*.rej' -o -name '.*.rej' ')' -print`" ] ; then
+     echo "Aborting.  Reject files found."
+     exit 1
+ fi
+ 
+ # Remove backup files
+-find $targetdir/ '(' -name '*.orig' -o -name '.*.orig' ')' -exec rm -f {} \;
++find $builddir/ '(' -name '*.orig' -o -name '.*.orig' ')' -exec rm -f {} \;
diff --git a/patches/linux/2.6.35/455-freescale-0004-MX28-kernel-5V-only-configuration-bug-fixes-and-improvement.patch b/patches/linux/2.6.35/455-freescale-0004-MX28-kernel-5V-only-configuration-bug-fixes-and-improvement.patch
new file mode 100755
index 0000000..37a6be2
--- /dev/null
+++ b/patches/linux/2.6.35/455-freescale-0004-MX28-kernel-5V-only-configuration-bug-fixes-and-improvement.patch
@@ -0,0 +1,247 @@
+From b7787120f90b46e351e74aa71ffbcbb220c8750c Mon Sep 17 00:00:00 2001
+From: Grace Si <gra...@fr...>
+Date: Tue, 13 Mar 2012 16:03:29 +0800
+Subject: [PATCH] MX28 kernel 5V only configuration bug fixes and improvement
+ 1. Change VDDA voltage from 1.75V to 1.8V which is the typical figure on datasheet.
+ 2. Add 5V only handling in kernel, add persistent bit to check whether it is 5V only
+    configuration in kernel and then enable correct FIQs and IRQs and handle FIQ.
+ 3. Add VDDD, VDDIO and VDDA debouncing check in FIQ handler.
+
+---
+ arch/arm/mach-mx28/bus_freq.c |   16 ++++++------
+ drivers/power/mxs/fiq.S       |   50 ++++++++++++++++++++++++++++++++--------
+ drivers/power/mxs/linux.c     |   39 +++++++++++++++++++++++++++++++-
+ 3 files changed, 86 insertions(+), 19 deletions(-)
+
+diff --git a/arch/arm/mach-mx28/bus_freq.c b/arch/arm/mach-mx28/bus_freq.c
+index 920c630..b13025a 100644
+--- a/arch/arm/mach-mx28/bus_freq.c
++++ b/arch/arm/mach-mx28/bus_freq.c
+@@ -51,26 +51,26 @@
+ #ifdef CONFIG_MEM_mDDR
+ struct profile profiles[] = {
+ 	{ 454736, 151570, 205710, 0, 1550000,
+-	1450000, 355000, 3300000, 1750000, 24000, 0 },
++	1450000, 355000, 3300000, 1800000, 24000, 0 },
+ 	{ 360000, 120000, 130910, 0, 1350000,
+-	1250000, 200000, 3300000, 1750000, 24000, 0 },
++	1250000, 200000, 3300000, 1800000, 24000, 0 },
+ 	{ 261818, 130910, 130910, 0, 1350000,
+-	1250000, 173000, 3300000, 1750000, 24000, 0 },
++	1250000, 173000, 3300000, 1800000, 24000, 0 },
+ 	{  64000,  64000, 240000, 3, 1350000,
+-	1250000, 150000, 3300000, 1750000, 24000, 0 },
++	1250000, 150000, 3300000, 1800000, 24000, 0 },
+ 	{  0,  0,  0, 0, 0,
+ 	0, 0, 0, 0, 0, 0 },
+ };
+ #else
+ struct profile profiles[] = {
+ 	{ 454736, 151570, 205710, 0, 1550000,
+-	1450000, 355000, 3300000, 1750000, 24000, 0 },
++	1450000, 355000, 3300000, 1800000, 24000, 0 },
+ 	{ 360000, 120000, 130910, 0, 1350000,
+-	1250000, 200000, 3300000, 1750000, 24000, 0 },
++	1250000, 200000, 3300000, 1800000, 24000, 0 },
+ 	{ 261818, 130910, 130910, 0, 1350000,
+-	1250000, 173000, 3300000, 1750000, 24000, 0 },
++	1250000, 173000, 3300000, 1800000, 24000, 0 },
+ 	{  64000,  64000, 130910, 3, 1350000,
+-	1250000, 150000, 3300000, 1750000, 24000, 0 },
++	1250000, 150000, 3300000, 1800000, 24000, 0 },
+ 	{  0,  0,  0, 0, 0,
+ 	0, 0, 0, 0, 0, 0 },
+ };
+diff --git a/drivers/power/mxs/fiq.S b/drivers/power/mxs/fiq.S
+index 1ad380d..932c31b 100644
+--- a/drivers/power/mxs/fiq.S
++++ b/drivers/power/mxs/fiq.S
+@@ -23,6 +23,7 @@
+ #include <asm/pgtable-hwdef.h>
+ #include <mach/regs-power.h>
+ #include <mach/../../regs-clkctrl.h>
++#include <mach/../../regs-digctl.h>
+ #include <mach/regs-timrot.h>
+ 
+ 	.align 5
+@@ -32,20 +33,46 @@
+ 	.globl lock_vector_tlb
+ 
+ power_fiq_start:
+-	ldr 	r8,power_reg
++	ldr r8,power_reg
+ 	ldr	r9,[r8,#HW_POWER_CTRL ]
+ 	ldr	r10,power_off
+ 
+-	@ when VDDIO_BO_IRQ,
+-	@ disabled, handled in IRQ for now
+-	@tst 	r9, #BM_POWER_CTRL_VDDIO_BO_IRQ
+ 
++    @ If battery Brownout, power off chip
++	tst     r9, #BM_POWER_CTRL_BATT_BO_IRQ
++	strne 	r10,[r8,#HW_POWER_RESET]
++
++
++	@ For 5V only configration, VDDIO_BO is set as FIQ,
++	@ For other cases, VDDIO_BO is handled in IRQ
+ 
+-	@ when BATT_BO_IRQ,  VDDD_BO_IRQ, VDDA_BO_IRQ, power off chip
+-	ldr     r11,power_bo
++	@ check whether it is VDDD_BO_IRQ, VDDA_BO_IRQ, VDDIO_BO_IRQ
++	ldr r11,power_bo
+ 	tst	r9, r11
+-	strne 	r10,[r8,#HW_POWER_RESET]
++	beq	check_vdd5v
++
++	ldr r9, power_digctl
++	ldr r12, [r9, #HW_DIGCTL_MICROSECONDS];
++	add	r12, #11  @ debouce time is 11 microseconds.
++
++    @ Loop for specified time to debounce the brownout status bits. 
+ 
++loop_check:
++	ldr	r10,  [r8, #HW_POWER_STS]
++    ldr r11, sts_bo
++	tst	r10, r11
++    beq     done      @ false brownout go to done.
++
++	ldr r9, power_digctl
++	ldr	r11, [r9, #HW_DIGCTL_MICROSECONDS];
++	cmp	r11, r12
++	blt	loop_check
++
++    @ true brownout, power off chip.
++	ldr	r10,power_off
++	str	r10, [r8, #HW_POWER_RESET]
++
++check_vdd5v:
+ 	@VDD5V_DROOP_IRQ
+ 	tst     r9, #BM_POWER_CTRL_VDD5V_DROOP_IRQ
+ 	beq	    check_dcdc4p2
+@@ -93,18 +120,21 @@ check_dcdc4p2:
+ 	mov	r11, #BM_POWER_CTRL_ENIRQ_DCDC4P2_BO
+ 	strne	r11, [r8, #HW_POWER_CTRL_CLR]
+ 
+-
++done:
+ 
+ 	@return from fiq
+ 	subs    pc,lr, #4
+ 
+ power_reg:
+ 	.long IO_ADDRESS(POWER_PHYS_ADDR)
++power_digctl:
++	.long IO_ADDRESS(DIGCTL_PHYS_ADDR)
+ power_off:
+ 	.long 0x3e770001
+ power_bo:
+-	.long BM_POWER_CTRL_BATT_BO_IRQ | \
+-	      BM_POWER_CTRL_VDDA_BO_IRQ | BM_POWER_CTRL_VDDD_BO_IRQ
++	.long BM_POWER_CTRL_VDDA_BO_IRQ | BM_POWER_CTRL_VDDD_BO_IRQ | BM_POWER_CTRL_VDDIO_BO_IRQ
++sts_bo:
++    .long BM_POWER_STS_VDDIO_BO | BM_POWER_STS_VDDA_BO	| BM_POWER_STS_VDDD_BO
+ power_fiq_count:
+ 	.long 0
+ power_fiq_end:
+diff --git a/drivers/power/mxs/linux.c b/drivers/power/mxs/linux.c
+index 3388307..5ec2a29 100644
+--- a/drivers/power/mxs/linux.c
++++ b/drivers/power/mxs/linux.c
+@@ -28,6 +28,7 @@
+ #include <mach/hardware.h>
+ #include <mach/irqs.h>
+ #include <mach/clock.h>
++#include <mach/regs-rtc.h>
+ #include <linux/delay.h>
+ #include <linux/proc_fs.h>
+ #include <linux/interrupt.h>
+@@ -775,11 +776,26 @@ static int mxs_bat_probe(struct platform_device *pdev)
+ {
+ 	struct mxs_info *info;
+ 	int ret = 0;
++	void *base = IO_ADDRESS(RTC_PHYS_ADDR);
+ 
+ 
+ 	/* enable usb device presence detection */
+ 	fsl_enable_usb_plugindetect();
+ 
++
++
++    /* check bit 11, bit 11 is set in power_prep.c if it is 5V only build.
++       we don't need initialize battery for 5V only build
++    */
++	if((__raw_readl(base + HW_RTC_PERSISTENT1) & 0x800))
++    {
++	    __raw_writel(0x800, base + HW_RTC_PERSISTENT1_CLR);
++
++        /* InitializeFiqSystem(); */
++	    ddi_power_InitOutputBrownouts();
++        return 0;
++    }
++
+ 	ret = ddi_power_init_battery();
+ 	if (ret) {
+ 		printk(KERN_ERR "Aborting power driver initialization\n");
+@@ -975,6 +991,7 @@ static int mxs_bat_probe(struct platform_device *pdev)
+ 		pr_debug("No onboard vbus 5v reg provided\n");
+ 		info->onboard_vbus5v = NULL;
+ 	}
++
+ 	return 0;
+ 
+ unregister_ac:
+@@ -1127,9 +1144,20 @@ static struct proc_dir_entry *power_fiq_proc;
+ static int __init mxs_bat_init(void)
+ {
+ 	struct clk *cpu, *pll0;
++	int ret;
++    int no_battery = false;
+ 
+ #ifdef POWER_FIQ
+-	int ret;
++
++    /* check bit 11, bit 11 is set in power_prep.c if it is 5V only build.
++    */
++
++	if((__raw_readl(IO_ADDRESS(RTC_PHYS_ADDR) + HW_RTC_PERSISTENT1) & 0x800))
++    {
++        no_battery = true;
++        printk(KERN_NOTICE "This is 5V only build. \r\n");
++    }
++
+ 	ret = claim_fiq(&power_fiq);
+ 	if (ret) {
+ 		pr_err("Can't claim fiq");
+@@ -1143,6 +1171,9 @@ static int __init mxs_bat_init(void)
+ 		disable_irq(IRQ_DCDC4P2_BRNOUT);
+ 		disable_irq(IRQ_BATT_BRNOUT);
+ 		disable_irq(IRQ_VDDD_BRNOUT);
++		disable_irq(IRQ_VDDA_BRNOUT);
++		if(no_battery)
++			disable_irq(IRQ_VDDIO_BRNOUT);
+ #ifndef CONFIG_ARCH_MX28
+ 		disable_irq(IRQ_VDD18_BRNOUT);
+ #endif
+@@ -1153,6 +1184,9 @@ static int __init mxs_bat_init(void)
+ 		mxs_set_irq_fiq(IRQ_DCDC4P2_BRNOUT, 1);
+ 		mxs_set_irq_fiq(IRQ_BATT_BRNOUT, 1);
+ 		mxs_set_irq_fiq(IRQ_VDDD_BRNOUT, 1);
++		mxs_set_irq_fiq(IRQ_VDDA_BRNOUT, 1);
++		if(no_battery)
++			mxs_set_irq_fiq(IRQ_VDDIO_BRNOUT, 1);
+ #ifndef CONFIG_ARCH_MX28
+ 		mxs_set_irq_fiq(IRQ_VDD18_BRNOUT, 1);
+ #endif
+@@ -1165,6 +1199,9 @@ static int __init mxs_bat_init(void)
+ 		enable_irq(IRQ_DCDC4P2_BRNOUT);
+ 		enable_irq(IRQ_BATT_BRNOUT);
+ 		enable_irq(IRQ_VDDD_BRNOUT);
++		enable_irq(IRQ_VDDA_BRNOUT);
++		if(no_battery)
++			enable_irq(IRQ_VDDIO_BRNOUT);
+ #ifndef CONFIG_ARCH_MX28
+ 		enable_irq(IRQ_VDD18_BRNOUT);
+ #endif
+-- 
+1.7.0.4
+


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-338-g009939f

From: jorasse <jo...@us...> - 2012-06-03 13:09:56

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  009939f74d84757013559aa1f21d9e164179538d (commit)
      from  994cb0a0465e3c91f87074b5dfaf5f834a6240f7 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 009939f74d84757013559aa1f21d9e164179538d
Author: Eric Jarrige <eri...@ar...>
Date:   Sun Jun 3 15:10:23 2012 +0200

    [UBOOT] apf28: bump to U-Boot 2012.04 - support battery as power supply

-----------------------------------------------------------------------

Summary of changes:
 buildroot/configs/apf28_defconfig                  |    6 ++--
 ...f28-u-boot-2011.12.h => apf28-u-boot-2012.04.h} |   31 ++++++++++++++++++-
 2 files changed, 32 insertions(+), 5 deletions(-)
 copy buildroot/target/device/armadeus/apf28/{apf28-u-boot-2011.12.h => apf28-u-boot-2012.04.h} (90%)

diff --git a/buildroot/configs/apf28_defconfig b/buildroot/configs/apf28_defconfig
index 2e80169..cbb36f3 100644
--- a/buildroot/configs/apf28_defconfig
+++ b/buildroot/configs/apf28_defconfig
@@ -61,10 +61,10 @@ BR2_TARGET_ROOTFS_UBI=y
 BR2_TARGET_ROOTFS_UBI_SUBSIZE=0
 BR2_TARGET_UBOOT=y
 BR2_TARGET_UBOOT_BOARDNAME="$(BR2_BOARD_NAME)"
-BR2_TARGET_UBOOT_CONFIG_HEADER_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2011.12.h"
+BR2_TARGET_UBOOT_CONFIG_HEADER_FILE="$(BR2_BOARD_PATH)/$(BR2_BOARD_NAME)-u-boot-2012.04.h"
 BR2_TARGET_UBOOT_CUSTOM_TARBALL=y
-BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2011.12.tar.bz2"
-BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2011.12"
+BR2_TARGET_UBOOT_CUSTOM_TARBALL_LOCATION="ftp://ftp.denx.de/pub/u-boot/u-boot-2012.04.tar.bz2"
+BR2_TARGET_UBOOT_CUSTOM_PATCH_DIR="../patches/u-boot/2012.04"
 BR2_TARGET_UBOOT_FORMAT_SB=y
 BR2_TARGET_UBOOT_NETWORK=y
 BR2_TARGET_UBOOT_SERVERIP="192.168.0.2"
diff --git a/buildroot/target/device/armadeus/apf28/apf28-u-boot-2011.12.h b/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h
similarity index 90%
copy from buildroot/target/device/armadeus/apf28/apf28-u-boot-2011.12.h
copy to buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h
index 5da1a50..b1ed6fa 100644
--- a/buildroot/target/device/armadeus/apf28/apf28-u-boot-2011.12.h
+++ b/buildroot/target/device/armadeus/apf28/apf28-u-boot-2012.04.h
@@ -26,7 +26,7 @@
 
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_ENV_VERSION 	"1.0"
-#define CONFIG_IDENT_STRING	" apf28 patch 1.0"
+#define CONFIG_IDENT_STRING	" apf28 patch 1.1"
 #define CONFIG_BOARD_NAME	apf28
 
 /*
@@ -39,6 +39,7 @@
  * Enable the call to miscellaneous platform dependent initialization.
  */
 #define CONFIG_SYS_NO_FLASH	/* to be define before <config_cmd_default.h> */
+#define CONFIG_SYS_DCACHE_OFF
 #define	CONFIG_BOARD_EARLY_INIT_F
 #define CONFIG_BOARD_LATE_INIT
 #define	CONFIG_ARCH_CPU_INIT
@@ -60,6 +61,32 @@
 #define	CONFIG_SPL_LIBCOMMON_SUPPORT
 #define	CONFIG_SPL_LIBGENERIC_SUPPORT
 
+/* Enable CONFIG_SYS_NO_DCDC_BATT_SOURCE the following if you only have a
+ * VDD5V source only and no DCDC_BATT source. This includes configurations with
+ * and without a supercap on the BATTERY pin as shown in the i.MX28 reference
+ * schematic.
+ *
+ * NOTE: If both a DCDC_BATT and VDD5V source are present, this is not meant to
+ * select which one to use. This is only for hardware configurations without
+ * DCDC_BATT power source.
+ */
+/* #define CONFIG_SYS_NO_DCDC_BATT_SOURCE */
+
+/* Enable CONFIG_SYS_NO_VDD5V_SOURCE the following if you only have a DCDC_BATT
+ * source only and no VDD5V. This includes configurations with and without a
+ * supercap on the BATTERY pin as shown in the i.MX28 reference schematic.
+ *
+ * NOTE: If both a DCDC_BATT and VDD5V source are present, this is not meant to
+ * select which one to use.  This is only for hardware configurations without
+ * VDD5V power source.
+*/
+/* #define CONFIG_SYS_NO_VDD5V_SOURCE */
+
+/* Enable CONFIG_SYS_VBUS_CURRENT_DRAW the following if VDD5V is sourced from
+ * VBUS. Limit the current to 100mA
+ */
+/* #define CONFIG_SYS_VBUS_CURRENT_DRAW */
+
 /*
  * BOOTP options
  */
@@ -320,7 +347,7 @@
 #define	CONFIG_MII
 #define	CONFIG_DISCOVER_PHY
 #define	CONFIG_FEC_XCV_TYPE		RMII
-#define CONFIG_M28_FEC_MAC_IN_OCOTP
+#define CONFIG_MX28_FEC_MAC_IN_OCOTP
 #define CONFIG_NETCONSOLE		1
 #endif
 #define ACFG_OUI	0x001EAC


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-337-g994cb0a

From: jorasse <jo...@us...> - 2012-05-25 23:47:04

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  994cb0a0465e3c91f87074b5dfaf5f834a6240f7 (commit)
       via  4fea75ffc2d68c541c1bcc76315cc4c29ad3ef04 (commit)
      from  6f6973828179e8f77384eb3b8c8c4cbb70d4ce67 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 994cb0a0465e3c91f87074b5dfaf5f834a6240f7
Merge: 4fea75f 6f69738
Author: Eric Jarrige <eri...@ar...>
Date:   Sat May 26 01:47:17 2012 +0200

    Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus

commit 4fea75ffc2d68c541c1bcc76315cc4c29ad3ef04
Author: Eric Jarrige <eri...@ar...>
Date:   Sat May 26 01:46:05 2012 +0200

    [UBOOT] 2012.04: apf27: add automatic memory bank detection/initialisation

-----------------------------------------------------------------------

Summary of changes:
 .../device/armadeus/apf27/apf27-u-boot-2012.04.h   |    2 +-
 ...dule-and-I-O-Multiplexer-constant-for-mx2.patch |    9 +++
 ...-Add-support-for-the-armadeus-apf27-board.patch |   52 ++++++++++++++------
 3 files changed, 46 insertions(+), 17 deletions(-)

diff --git a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.04.h b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.04.h
index 0c06421..d422159 100644
--- a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.04.h
+++ b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.04.h
@@ -25,7 +25,7 @@
 
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_ENV_VERSION 	"3.0"
-#define CONFIG_IDENT_STRING	" apf27 patch 3.2"
+#define CONFIG_IDENT_STRING	" apf27 patch 3.3"
 #define CONFIG_BOARD_NAME	apf27
 
 /*
diff --git a/patches/u-boot/2012.04/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch b/patches/u-boot/2012.04/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
index d962599..c05dfce 100644
--- a/patches/u-boot/2012.04/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
+++ b/patches/u-boot/2012.04/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
@@ -58,6 +58,15 @@ diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/ar
 index ced5b2a..4df67d6 100644
 --- a/arch/arm/include/asm/arch-mx27/imx-regs.h
 +++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
+@@ -206,7 +206,7 @@ struct iim_regs {
+ 	struct fuse_bank {
+ 		u32 fuse_regs[0x20];
+ 		u32 fuse_rsvd[0xe0];
+-	} bank[1];
++	} bank[2];
+ };
+ 
+ struct fuse_bank0_regs {
 @@ -522,4 +522,13 @@ struct fuse_bank0_regs {
  #define IIM_ERR_SNSE	(1 << 2)
  #define IIM_ERR_PARITYE	(1 << 1)
diff --git a/patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch b/patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch
index 10753da..76ed5d0 100644
--- a/patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch
+++ b/patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch
@@ -88,7 +88,7 @@ new file mode 100644
 index 0000000..1f1bd42
 --- /dev/null
 +++ b/board/armadeus/apf27/apf27.c
-@@ -0,0 +1,305 @@
+@@ -0,0 +1,325 @@
 +/*
 + * Copyright (C) 2007 Sascha Hauer, Pengutronix
 + * Copyright (C) 2008,2009 Eric Jarrige <jo...@us...>
@@ -122,6 +122,26 @@ index 0000000..1f1bd42
 +
 +DECLARE_GLOBAL_DATA_PTR;
 +
++u32 get_board_rev(void)
++{
++	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
++
++	return readl(&iim->bank[1].fuse_regs[8]);
++}
++
++int get_num_ram_bank(void)
++{
++	struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
++	int nr_dram_banks = 1;
++
++	if ((get_board_rev() > 0) && (CONFIG_NR_DRAM_BANKS > 1))
++		nr_dram_banks += readl(&iim->bank[1].fuse_regs[9]) & 0x01;
++	else
++		nr_dram_banks = CONFIG_NR_DRAM_POPULATED;
++
++	return nr_dram_banks;
++}
++
 +static void apf27_gpio_init(void)
 +{
 +  	struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
@@ -276,24 +296,24 @@ index 0000000..1f1bd42
 +int
 +dram_init (void)
 +{
-+       /* dram_init must store complete ramsize in gd->ram_size */
-+       gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
-+                                   PHYS_SDRAM_1_SIZE);
-+#if ( CONFIG_NR_DRAM_POPULATED > 1 )
-+       gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2,
-+                                    PHYS_SDRAM_2_SIZE);
-+#endif
-+  return 0;
++	/* dram_init must store complete ramsize in gd->ram_size */
++	gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE);
++	if (get_num_ram_bank() > 1) {
++		gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2,
++						PHYS_SDRAM_2_SIZE);
++	}
++
++	return 0;
 +}
 +
 +void dram_init_banksize(void)
 +{
-+       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-+       gd->bd->bi_dram[0].size = gd->ram_size / CONFIG_NR_DRAM_POPULATED;
-+#if ( CONFIG_NR_DRAM_BANKS > 1 )
-+       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
-+       gd->bd->bi_dram[1].size = gd->ram_size -gd->bd->bi_dram[0].size;
-+#endif
++	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
++	gd->bd->bi_dram[0].size = gd->ram_size / get_num_ram_bank();
++	if (CONFIG_NR_DRAM_BANKS > 1) {
++		gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
++		gd->bd->bi_dram[1].size = gd->ram_size -gd->bd->bi_dram[0].size;
++	}
 +}
 +
 +/*
@@ -357,7 +377,7 @@ index 0000000..1f1bd42
 +
 +int checkboard(void)
 +{
-+	printf("Armadeus APF27\n");
++	printf("Board: Armadeus APF27 revision %d\n", get_board_rev());
 +	return 0;
 +}
 +


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-335-g6f69738

From: Gwenhael Goavec-M. <gwe...@us...> - 2012-05-25 18:42:21

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  6f6973828179e8f77384eb3b8c8c4cbb70d4ce67 (commit)
      from  fec65f233446f1d0b2176dab6fa1229a3bd7fc55 (commit)

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- Log -----------------------------------------------------------------
commit 6f6973828179e8f77384eb3b8c8c4cbb70d4ce67
Author: Gwenhael Goavec-Merou <gw...@tr...>
Date:   Fri May 25 20:41:15 2012 +0200

    [LINUX] 2.6.35: apf28: add support for spidev on apf28dev

-----------------------------------------------------------------------

Summary of changes:
 ...1-armadeus-add_apf28dev_baseboard_support.patch |   68 ++++++++++++--------
 1 files changed, 41 insertions(+), 27 deletions(-)

diff --git a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
index e17e557..f37e549 100644
--- a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
+++ b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
@@ -4,9 +4,9 @@ Signed-off-by: Julien Boibessot <jul...@ar...>
 
 Index: linux-2.6.35.3/arch/arm/mach-mx28/Kconfig
 ===================================================================
---- linux-2.6.35.3.orig/arch/arm/mach-mx28/Kconfig	2012-02-15 14:42:20.000000000 +0100
-+++ linux-2.6.35.3/arch/arm/mach-mx28/Kconfig	2012-02-15 14:43:35.000000000 +0100
-@@ -16,6 +16,22 @@
+--- linux-2.6.35.3.orig/arch/arm/mach-mx28/Kconfig
++++ linux-2.6.35.3/arch/arm/mach-mx28/Kconfig
+@@ -16,6 +16,22 @@ config MACH_APF28
  
  endchoice
  
@@ -31,9 +31,9 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/Kconfig
  	default 0
 Index: linux-2.6.35.3/arch/arm/mach-mx28/Makefile
 ===================================================================
---- linux-2.6.35.3.orig/arch/arm/mach-mx28/Makefile	2012-02-15 14:42:20.000000000 +0100
-+++ linux-2.6.35.3/arch/arm/mach-mx28/Makefile	2012-02-15 14:43:35.000000000 +0100
-@@ -6,6 +6,7 @@
+--- linux-2.6.35.3.orig/arch/arm/mach-mx28/Makefile
++++ linux-2.6.35.3/arch/arm/mach-mx28/Makefile
+@@ -6,6 +6,7 @@ obj-y += pinctrl.o clock.o device.o seri
  # Board select
  obj-$(CONFIG_MACH_MX28EVK) += mx28evk.o mx28evk_pins.o
  obj-$(CONFIG_MACH_APF28)   += mach-apf28.o
@@ -43,9 +43,9 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/Makefile
  
 Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 ===================================================================
---- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c	2012-02-15 15:51:09.000000000 +0100
-@@ -0,0 +1,742 @@
+--- /dev/null
++++ linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
+@@ -0,0 +1,756 @@
 +/*
 + * Copyright (C) 2012 Armadeus systems
 + *
@@ -773,6 +773,16 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +}
 +#endif /* defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) */
 +
++#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE)
++static struct spi_board_info spi_board_info[] __initdata = {
++	{
++		.modalias = "spidev",
++		.max_speed_hz = 120000,
++		.bus_num = 1, /* SSPI2 */
++		.chip_select = 0,
++	},
++};
++#endif /* defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE) */
 +
 +void __init apf28_baseboard_pins_init(void)
 +{
@@ -785,14 +795,18 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +{
 +	/* Add apf28dev special code */
 +	platform_add_devices(apf28dev_platform_devices, ARRAY_SIZE(apf28dev_platform_devices));
++
++#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE)
++	spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
++#endif /* defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE) */
 +}
 +
 +
 Index: linux-2.6.35.3/drivers/video/mxs/Kconfig
 ===================================================================
---- linux-2.6.35.3.orig/drivers/video/mxs/Kconfig	2012-02-15 14:42:20.000000000 +0100
-+++ linux-2.6.35.3/drivers/video/mxs/Kconfig	2012-02-15 14:43:35.000000000 +0100
-@@ -21,6 +21,20 @@
+--- linux-2.6.35.3.orig/drivers/video/mxs/Kconfig
++++ linux-2.6.35.3/drivers/video/mxs/Kconfig
+@@ -21,6 +21,20 @@ config FB_MXS_LCD_LMS430
  	---help---
  	  Use LMS430 dotclock LCD panel for MXS
  
@@ -815,9 +829,9 @@ Index: linux-2.6.35.3/drivers/video/mxs/Kconfig
  	bool "TVENC"
 Index: linux-2.6.35.3/drivers/video/mxs/Makefile
 ===================================================================
---- linux-2.6.35.3.orig/drivers/video/mxs/Makefile	2012-02-15 14:42:20.000000000 +0100
-+++ linux-2.6.35.3/drivers/video/mxs/Makefile	2012-02-15 14:43:35.000000000 +0100
-@@ -2,5 +2,7 @@
+--- linux-2.6.35.3.orig/drivers/video/mxs/Makefile
++++ linux-2.6.35.3/drivers/video/mxs/Makefile
+@@ -2,5 +2,7 @@ obj-$(CONFIG_ARCH_MXS)				+= lcdif.o
  obj-$(CONFIG_FB_MXS)				+= mxsfb.o
  obj-$(CONFIG_FB_MXS_LCD_43WVF1G)		+= lcd_43wvf1g.o
  obj-$(CONFIG_FB_MXS_LCD_LMS430)			+= lcd_lms430.o
@@ -827,8 +841,8 @@ Index: linux-2.6.35.3/drivers/video/mxs/Makefile
  obj-$(CONFIG_FB_MXS_TVENC)			+= tvenc.o
 Index: linux-2.6.35.3/drivers/video/mxs/lcd_tm035.c
 ===================================================================
---- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.35.3/drivers/video/mxs/lcd_tm035.c	2012-02-15 14:43:35.000000000 +0100
+--- /dev/null
++++ linux-2.6.35.3/drivers/video/mxs/lcd_tm035.c
 @@ -0,0 +1,305 @@
 +/*
 + * Tianma TM035 LCD panel initialization for Armadeus APF28Dev
@@ -1137,8 +1151,8 @@ Index: linux-2.6.35.3/drivers/video/mxs/lcd_tm035.c
 +subsys_initcall(register_devices);
 Index: linux-2.6.35.3/drivers/video/mxs/lcd_lw700.c
 ===================================================================
---- /dev/null	1970-01-01 00:00:00.000000000 +0000
-+++ linux-2.6.35.3/drivers/video/mxs/lcd_lw700.c	2012-02-15 14:43:35.000000000 +0100
+--- /dev/null
++++ linux-2.6.35.3/drivers/video/mxs/lcd_lw700.c
 @@ -0,0 +1,297 @@
 +/*
 + * Freescale MX28 Densitron LW700 LCD panel driver
@@ -1439,9 +1453,9 @@ Index: linux-2.6.35.3/drivers/video/mxs/lcd_lw700.c
 +subsys_initcall(register_devices);
 Index: linux-2.6.35.3/arch/arm/mach-mx28/device.c
 ===================================================================
---- linux-2.6.35.3.orig/arch/arm/mach-mx28/device.c	2012-02-15 14:43:59.000000000 +0100
-+++ linux-2.6.35.3/arch/arm/mach-mx28/device.c	2012-02-15 14:52:10.000000000 +0100
-@@ -426,7 +426,6 @@
+--- linux-2.6.35.3.orig/arch/arm/mach-mx28/device.c
++++ linux-2.6.35.3/arch/arm/mach-mx28/device.c
+@@ -426,7 +426,6 @@ static void mx28_init_gpmi_nfc(void)
  #define MMC1_POWER	MXS_PIN_TO_GPIO(PINID_PWM4)
  #define MMC0_WP		MXS_PIN_TO_GPIO(PINID_SSP1_SCK)
  #define MMC1_WP		MXS_PIN_TO_GPIO(PINID_GPMI_RESETN)
@@ -1449,7 +1463,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/device.c
  
  static int mxs_mmc_get_wp_ssp0(void)
  {
-@@ -467,6 +466,7 @@
+@@ -467,6 +466,7 @@ static void mxs_mmc_hw_release_ssp0(void
  	gpio_free(MMC0_WP);
  
  }
@@ -1457,7 +1471,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/device.c
  
  static void mxs_mmc_cmd_pullup_ssp0(int enable)
  {
-@@ -490,6 +490,7 @@
+@@ -490,6 +490,7 @@ static unsigned long mxs_mmc_setclock_ss
  	return hz;
  }
  
@@ -1465,7 +1479,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/device.c
  static int mxs_mmc_get_wp_ssp1(void)
  {
  	return gpio_get_value(MMC1_WP);
-@@ -528,6 +529,7 @@
+@@ -528,6 +529,7 @@ static void mxs_mmc_hw_release_ssp1(void
  	gpio_free(MMC1_POWER);
  	gpio_free(MMC1_WP);
  }
@@ -1473,7 +1487,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/device.c
  
  static void mxs_mmc_cmd_pullup_ssp1(int enable)
  {
-@@ -552,9 +554,11 @@
+@@ -552,9 +554,11 @@ static unsigned long mxs_mmc_setclock_ss
  }
  
  static struct mxs_mmc_platform_data mmc0_data = {
@@ -1485,7 +1499,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/device.c
  	.cmd_pullup	= mxs_mmc_cmd_pullup_ssp0,
  	.setclock	= mxs_mmc_setclock_ssp0,
  	.caps 		= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA
-@@ -591,9 +595,11 @@
+@@ -591,9 +595,11 @@ static struct resource mmc0_resource[] =
  };
  
  static struct mxs_mmc_platform_data mmc1_data = {


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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-334-gfec65f2

From: jorasse <jo...@us...> - 2012-05-25 16:59:51

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- Log -----------------------------------------------------------------
commit fec65f233446f1d0b2176dab6fa1229a3bd7fc55
Author: Eric Jarrige <eri...@ar...>
Date:   Fri May 25 18:57:00 2012 +0200

    [LINUX] 2.6.35: apf28: Enable I2C0 in the default configuration and its user space interface

commit 30502feaf329621da3e47610c04930c688bef683
Author: Eric Jarrige <eri...@ar...>
Date:   Fri May 25 18:51:18 2012 +0200

    [LINUX] 2.6.35: apf28: Add audio support (enable SPDIF)

commit 47376e551cddde05e7985e476cea86389f44b428
Author: Eric Jarrige <eri...@ar...>
Date:   Fri May 25 18:32:49 2012 +0200

    [LINUX] 2.6.35: apf28: Enable CAN and VCAN drivers

commit d5fdd37d071769ccbfeb60f42e3802c98b44b9e1
Author: Eric Jarrige <eri...@ar...>
Date:   Fri May 25 18:15:28 2012 +0200

    [LINUX] 2.6.35: apf28: Enable spi-dev from the default configuration

-----------------------------------------------------------------------

Summary of changes:
 .../armadeus/apf28/apf28-linux-2.6.35.config       |   59 ++++++++++++++++++--
 ...1-armadeus-add_apf28dev_baseboard_support.patch |    2 +-
 2 files changed, 54 insertions(+), 7 deletions(-)

diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config b/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
index f3e3041..275ad2f 100644
--- a/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
+++ b/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
@@ -497,10 +497,10 @@ CONFIG_CAN_RAW=y
 #
 # CAN Device Drivers
 #
-# CONFIG_CAN_VCAN is not set
+CONFIG_CAN_VCAN=y
 # CONFIG_CAN_DEV is not set
 # CONFIG_CAN_DEBUG_DEVICES is not set
-CONFIG_CAN_FLEXCAN=m
+CONFIG_CAN_FLEXCAN=y
 # CONFIG_IRDA is not set
 CONFIG_BT=m
 CONFIG_BT_L2CAP=m
@@ -1035,8 +1035,9 @@ CONFIG_MAX_RAW_DEVS=8192
 CONFIG_I2C=y
 CONFIG_I2C_BOARDINFO=y
 CONFIG_I2C_COMPAT=y
-# CONFIG_I2C_CHARDEV is not set
+CONFIG_I2C_CHARDEV=y
 CONFIG_I2C_HELPER_AUTO=y
+CONFIG_I2C_ALGOBIT=m
 
 #
 # I2C Hardware Bus support
@@ -1046,7 +1047,7 @@ CONFIG_I2C_HELPER_AUTO=y
 # I2C system bus drivers (mostly embedded / system-on-chip)
 #
 # CONFIG_I2C_DESIGNWARE is not set
-# CONFIG_I2C_GPIO is not set
+CONFIG_I2C_GPIO=m
 CONFIG_I2C_MXS=y
 CONFIG_I2C_MXS_SELECT0=y
 # CONFIG_I2C_MXS_SELECT0_PIOQUEUE_MODE is not set
@@ -1085,7 +1086,7 @@ CONFIG_SPI_MXS=y
 #
 # SPI Protocol Masters
 #
-# CONFIG_SPI_SPIDEV is not set
+CONFIG_SPI_SPIDEV=y
 # CONFIG_SPI_TLE62X0 is not set
 
 #
@@ -1401,7 +1402,52 @@ CONFIG_LOGO=y
 # CONFIG_LOGO_LINUX_MONO is not set
 # CONFIG_LOGO_LINUX_VGA16 is not set
 CONFIG_LOGO_LINUX_CLUT224=y
-# CONFIG_SOUND is not set
+CONFIG_SOUND=y
+CONFIG_SOUND_OSS_CORE=y
+CONFIG_SOUND_OSS_CORE_PRECLAIM=y
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_JACK=y
+# CONFIG_SND_SEQUENCER is not set
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=y
+CONFIG_SND_PCM_OSS=y
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_HRTIMER=m
+# CONFIG_SND_DYNAMIC_MINORS is not set
+CONFIG_SND_SUPPORT_OLD_API=y
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+# CONFIG_SND_RAWMIDI_SEQ is not set
+# CONFIG_SND_OPL3_LIB_SEQ is not set
+# CONFIG_SND_OPL4_LIB_SEQ is not set
+# CONFIG_SND_SBAWE_SEQ is not set
+# CONFIG_SND_EMU10K1_SEQ is not set
+CONFIG_SND_DRIVERS=y
+# CONFIG_SND_DUMMY is not set
+# CONFIG_SND_MTPAV is not set
+# CONFIG_SND_SERIAL_U16550 is not set
+# CONFIG_SND_MPU401 is not set
+CONFIG_SND_ARM=y
+# CONFIG_SND_MXC_SPDIF is not set
+CONFIG_SND_SPI=y
+CONFIG_SND_USB=y
+# CONFIG_SND_USB_AUDIO is not set
+# CONFIG_SND_USB_UA101 is not set
+# CONFIG_SND_USB_CAIAQ is not set
+CONFIG_SND_SOC=y
+CONFIG_SND_MXS_SOC=y
+CONFIG_SND_MXS_SOC_SPDIF_DAI=y
+CONFIG_SND_MXS_SOC_EVK_DEVB=m
+CONFIG_SND_MXS_SOC_DAI=m
+CONFIG_SND_MXS_SOC_EVK_DEVB_SPDIF=y
+CONFIG_SND_SOC_I2C_AND_SPI=y
+# CONFIG_SND_SOC_ALL_CODECS is not set
+CONFIG_SND_SOC_SGTL5000=m
+CONFIG_SND_SOC_MXS_SPDIF=y
+# CONFIG_SOUND_PRIME is not set
 CONFIG_HID_SUPPORT=y
 CONFIG_HID=y
 # CONFIG_HIDRAW is not set
@@ -1423,6 +1469,7 @@ CONFIG_HID_BELKIN=y
 # CONFIG_HID_CANDO is not set
 CONFIG_HID_CHERRY=y
 CONFIG_HID_CHICONY=y
+# CONFIG_HID_PRODIKEYS is not set
 CONFIG_HID_CYPRESS=y
 CONFIG_HID_DRAGONRISE=y
 # CONFIG_DRAGONRISE_FF is not set
diff --git a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
index 800e0e8..e17e557 100644
--- a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
+++ b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
@@ -526,7 +526,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +	},
 +	{
 +		.name		= "SAIF1_SDATA0",
-+		.id		= PINID_SAIF1_SDATA0
++		.id		= PINID_SAIF1_SDATA0,
 +		.fun		= PIN_FUN1,
 +		.strength	= PAD_12MA,
 +		.voltage	= PAD_3_3V,


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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-330-g1ce2eb6

From: jorasse <jo...@us...> - 2012-05-25 14:37:45

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  1ce2eb650d10b4f51ed3891cd95b0c4b2a6036aa (commit)
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- Log -----------------------------------------------------------------
commit 1ce2eb650d10b4f51ed3891cd95b0c4b2a6036aa
Author: Eric Jarrige <eri...@ar...>
Date:   Fri May 25 16:34:40 2012 +0200

    [LINUX] 2.6.35: apf28: default config has UART 0, 2 and 3 enabled - also disable UART 1 and 4

commit 89c70cb53fb219c6aff177faaacc44fa178e0a0d
Author: Eric Jarrige <eri...@ar...>
Date:   Fri May 25 16:27:57 2012 +0200

    [LINUX] 2.6.35: apf28: Use SMSC PHY driver instead of a generic MII PHY

-----------------------------------------------------------------------

Summary of changes:
 .../armadeus/apf28/apf28-linux-2.6.35.config       |   11 ++++++-----
 1 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config b/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
index 27ec7e8..f3e3041 100644
--- a/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
+++ b/buildroot/target/device/armadeus/apf28/apf28-linux-2.6.35.config
@@ -1,7 +1,7 @@
 #
 # Automatically generated make config: don't edit
 # Linux kernel version: 2.6.35.3
-# Mon Mar 19 10:50:08 2012
+# Fri May 25 16:25:50 2012
 #
 CONFIG_ARM=y
 CONFIG_SYS_SUPPORTS_APM_EMULATION=y
@@ -275,13 +275,13 @@ CONFIG_MXS_AUART_DMA_SUPPORT=y
 CONFIG_MXS_AUART_PORTS=5
 CONFIG_MXS_AUART0_DEVICE_ENABLE=y
 # CONFIG_MXS_AUART0_DMA_ENABLE is not set
-CONFIG_MXS_AUART1_DEVICE_ENABLE=y
+# CONFIG_MXS_AUART1_DEVICE_ENABLE is not set
 # CONFIG_MXS_AUART1_DMA_ENABLE is not set
 CONFIG_MXS_AUART2_DEVICE_ENABLE=y
 # CONFIG_MXS_AUART2_DMA_ENABLE is not set
 CONFIG_MXS_AUART3_DEVICE_ENABLE=y
 # CONFIG_MXS_AUART3_DMA_ENABLE is not set
-CONFIG_MXS_AUART4_DEVICE_ENABLE=y
+# CONFIG_MXS_AUART4_DEVICE_ENABLE is not set
 # CONFIG_MXS_AUART4_DMA_ENABLE is not set
 CONFIG_MXS_RAM_FREQ_SCALING=y
 # CONFIG_MXS_RAM_MDDR is not set
@@ -702,6 +702,7 @@ CONFIG_MISC_DEVICES=y
 # CONFIG_DS1682 is not set
 # CONFIG_TI_DAC7512 is not set
 CONFIG_MXS_PERSISTENT=y
+CONFIG_MXS_PERFMON=y
 # CONFIG_ANDROID_PMEM is not set
 # CONFIG_UID_STAT is not set
 # CONFIG_C2PORT is not set
@@ -780,7 +781,7 @@ CONFIG_PHYLIB=y
 # CONFIG_LXT_PHY is not set
 # CONFIG_CICADA_PHY is not set
 # CONFIG_VITESSE_PHY is not set
-# CONFIG_SMSC_PHY is not set
+CONFIG_SMSC_PHY=y
 # CONFIG_BROADCOM_PHY is not set
 # CONFIG_ICPLUS_PHY is not set
 # CONFIG_REALTEK_PHY is not set
@@ -791,7 +792,7 @@ CONFIG_PHYLIB=y
 # CONFIG_FIXED_PHY is not set
 # CONFIG_MDIO_BITBANG is not set
 CONFIG_NET_ETHERNET=y
-CONFIG_MII=y
+# CONFIG_MII is not set
 # CONFIG_AX88796 is not set
 # CONFIG_SMC91X is not set
 # CONFIG_DM9000 is not set


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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-328-g5a597e0

From: jorasse <jo...@us...> - 2012-05-25 14:22:09

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  5a597e0b268f9b39a473fe87505a92e57e17bfc4 (commit)
      from  011d922a72c5ace5c70e1318aa52c744eaa242ca (commit)

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- Log -----------------------------------------------------------------
commit 5a597e0b268f9b39a473fe87505a92e57e17bfc4
Author: Eric Jarrige <eri...@ar...>
Date:   Fri May 25 16:21:55 2012 +0200

    [LINUX] apf28: support extension connector buses: I2C, SPI, SPDIF, CAN, UART and SAIF

-----------------------------------------------------------------------

Summary of changes:
 ...1-armadeus-add_apf28dev_baseboard_support.patch |  261 +++++++++++++++++++-
 1 files changed, 260 insertions(+), 1 deletions(-)

diff --git a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
index 59bbf36..800e0e8 100644
--- a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
+++ b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
@@ -45,7 +45,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
 +++ linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c	2012-02-15 15:51:09.000000000 +0100
-@@ -0,0 +1,483 @@
+@@ -0,0 +1,742 @@
 +/*
 + * Copyright (C) 2012 Armadeus systems
 + *
@@ -355,6 +355,199 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.drive = 1,
 +		.pull = 0,
 +	},
++#ifdef CONFIG_MXS_AUART0_DEVICE_ENABLE
++	{
++		.name		= "AUART0.RX",
++		.id		= PINID_AUART0_RX,
++		.fun		= PIN_FUN1,
++		},
++	{
++		.name		= "AUART0.TX",
++		.id		= PINID_AUART0_TX,
++		.fun		= PIN_FUN1,
++	},
++	{
++		.name		= "AUART0.CTS",
++		.id		= PINID_AUART0_CTS,
++		.fun		= PIN_FUN1,
++		},
++	{
++		.name		= "AUART0.RTS",
++		.id		= PINID_AUART0_RTS,
++		.fun		= PIN_FUN1,
++	},
++#endif
++#ifdef CONFIG_MXS_AUART2_DEVICE_ENABLE
++	{
++		.name		= "AUART2.RX",
++		.id		= PINID_AUART2_RX,
++		.fun		= PIN_FUN1,
++	},
++	{
++		.name		= "AUART2.TX",
++		.id		= PINID_AUART2_TX,
++		.fun		= PIN_FUN1,
++	},
++	{
++		.name		= "AUART2.CTS",
++		.id		= PINID_AUART2_CTS,
++		.fun		= PIN_FUN1,
++	},
++	{
++		.name		= "AUART2.RTS",
++		.id		= PINID_AUART2_RTS,
++		.fun		= PIN_FUN1,
++	},
++#endif
++#ifdef CONFIG_MXS_AUART3_DEVICE_ENABLE
++	{
++		.name		= "AUART3.RX",
++		.id		= PINID_AUART3_RX,
++		.fun		= PIN_FUN1,
++	},
++	{
++		.name		= "AUART3.TX",
++		.id		= PINID_AUART3_TX,
++		.fun		= PIN_FUN1,
++	},
++	{
++		.name		= "AUART3.CTS",
++		.id		= PINID_AUART3_CTS,
++		.fun		= PIN_FUN1,
++	},
++	{
++		.name		= "AUART3.RTS",
++		.id		= PINID_AUART3_RTS,
++		.fun		= PIN_FUN1,
++	},
++#endif
++#if defined(CONFIG_CAN_FLEXCAN) || defined(CONFIG_CAN_FLEXCAN_MODULE)
++	{
++		.name		= "CAN0_TX",
++		.id		= PINID_GPMI_RDY2,
++		.fun		= PIN_FUN2,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= 1,
++		.pull		= 0,
++	},
++	{
++		.name		= "CAN0_RX",
++		.id		= PINID_GPMI_RDY3,
++		.fun		= PIN_FUN2,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= 1,
++		.pull		= 0,
++	},
++	{
++		.name		= "CAN1_TX",
++		.id		= PINID_GPMI_CE2N,
++		.fun		= PIN_FUN2,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= 1,
++		.pull		= 0,
++	},
++	{
++		.name		= "CAN1_RX",
++		.id		= PINID_GPMI_CE3N,
++		.fun		= PIN_FUN2,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 0,
++		.drive		= 1,
++		.pull		= 0,
++	},
++#endif
++#if defined(CONFIG_I2C_MXS) || \
++	defined(CONFIG_I2C_MXS_MODULE)
++	{
++		.name		= "I2C0_SCL",
++		.id		= PINID_I2C0_SCL,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_8MA,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
++	},
++	{
++		.name		= "I2C0_SDA",
++		.id		= PINID_I2C0_SDA,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_8MA,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
++	},
++#endif
++#if defined(CONFIG_SND_MXS_SOC_DAI) || defined(CONFIG_SND_MXS_SOC_DAI_MODULE)
++	/* Configurations of SAIF0 port pins */
++	{
++		.name		= "SAIF0_MCLK",
++		.id		= PINID_SAIF0_MCLK,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_12MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 1,
++		.drive		= 1,
++		.pull		= 1,
++	},
++	{
++		.name		= "SAIF0_LRCLK",
++		.id		= PINID_SAIF0_LRCLK,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_12MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 1,
++		.drive		= 1,
++		.pull		= 1,
++	},
++	{
++		.name		= "SAIF0_BITCLK",
++		.id		= PINID_SAIF0_BITCLK,
++		.fun		= PIN_FUN3,
++		.strength	= PAD_12MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 1,
++		.drive		= 1,
++		.pull		= 1,
++	},
++	{
++		.name		= "SAIF0_SDATA0",
++		.id		= PINID_SAIF0_SDATA0,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_12MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 1,
++		.drive		= 1,
++		.pull		= 1,
++	},
++	{
++		.name		= "SAIF1_SDATA0",
++		.id		= PINID_SAIF1_SDATA0
++		.fun		= PIN_FUN1,
++		.strength	= PAD_12MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 1,
++		.drive		= 1,
++		.pull		= 1,
++	},
++#endif
++#if defined(CONFIG_SND_SOC_MXS_SPDIF) || \
++	defined(CONFIG_SND_SOC_MXS_SPDIF_MODULE)
++	{
++		.name		= "SPDIF",
++		.id		= PINID_SPDIF,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_12MA,
++		.voltage	= PAD_3_3V,
++		.pullup		= 1,
++		.drive		= 1,
++		.pull		= 1,
++	},
++#endif
 +#if defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE)\
 +	|| defined(CONFIG_FEC_L2SWITCH)
 +	{
@@ -441,6 +634,72 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.data		= 1,
 +	},
 +#endif /* defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE).. */
++#if defined(CONFIG_SPI_MXS) || defined(CONFIG_SPI_MXS_MODULE)
++	{
++		.name		= "SSP2 MOSI",
++		.id		= PINID_SSP2_MOSI,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
++	},
++	{
++		.name		= "SSP2 MISO",
++		.id		= PINID_SSP2_MISO,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
++	},
++	{
++		.name		= "SSP2 SCK",
++		.id		= PINID_SSP2_SCK,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
++	},
++	{
++		.name		= "SSP2 SS0",
++		.id		= PINID_SSP2_SS0,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
++	},
++	{
++		.name		= "SSP3 MOSI",
++		.id		= PINID_SSP3_MOSI,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
++	},
++	{
++		.name		= "SSP3 MISO",
++		.id		= PINID_SSP3_MISO,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
++	},
++	{
++		.name		= "SSP3 SCK",
++		.id		= PINID_SSP3_SCK,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
++	},
++	{
++		.name		= "SSP3 SS0",
++		.id		= PINID_SSP3_SS0,
++		.fun		= PIN_FUN1,
++		.strength	= PAD_4MA,
++		.voltage	= PAD_3_3V,
++		.drive		= 1,
++	},
++#endif
 +};
 +
 +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-327-g011d922

From: jorasse <jo...@us...> - 2012-05-25 08:36:19

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  011d922a72c5ace5c70e1318aa52c744eaa242ca (commit)
      from  5c77e77f384345fc422f25039d3af59a32c69fd9 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 011d922a72c5ace5c70e1318aa52c744eaa242ca
Author: Eric Jarrige <eri...@ar...>
Date:   Fri May 25 10:35:48 2012 +0200

    [UBOOT] 2012.04: apf27: make SDRAM init code generic for all hardware configuration (1 and 2 memory banks)

-----------------------------------------------------------------------

Summary of changes:
 ...f27-u-boot-2011.12.h => apf27-u-boot-2012.04.h} |    4 +-
 ...-Add-support-for-the-armadeus-apf27-board.patch |   44 +++++++++-----------
 2 files changed, 22 insertions(+), 26 deletions(-)
 copy buildroot/target/device/armadeus/apf27/{apf27-u-boot-2011.12.h => apf27-u-boot-2012.04.h} (99%)

diff --git a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.04.h
similarity index 99%
copy from buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
copy to buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.04.h
index ead5231..0c06421 100644
--- a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
+++ b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.04.h
@@ -25,7 +25,7 @@
 
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_ENV_VERSION 	"3.0"
-#define CONFIG_IDENT_STRING	" apf27 patch 3.1"
+#define CONFIG_IDENT_STRING	" apf27 patch 3.2"
 #define CONFIG_BOARD_NAME	apf27
 
 /*
@@ -100,7 +100,7 @@
  * Memory configurations
  */
 #define CONFIG_NR_DRAM_POPULATED	1
-#define CONFIG_NR_DRAM_BANKS	CONFIG_NR_DRAM_POPULATED
+#define CONFIG_NR_DRAM_BANKS	2
 
 #define CONFIG_SYS_SDRAM_MBYTE_SYZE 64
 
diff --git a/patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch b/patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch
index b3601e5..10753da 100644
--- a/patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch
+++ b/patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch
@@ -279,7 +279,7 @@ index 0000000..1f1bd42
 +       /* dram_init must store complete ramsize in gd->ram_size */
 +       gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
 +                                   PHYS_SDRAM_1_SIZE);
-+#if ( CONFIG_NR_DRAM_BANKS > 1 )
++#if ( CONFIG_NR_DRAM_POPULATED > 1 )
 +       gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2,
 +                                    PHYS_SDRAM_2_SIZE);
 +#endif
@@ -289,7 +289,7 @@ index 0000000..1f1bd42
 +void dram_init_banksize(void)
 +{
 +       gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-+       gd->bd->bi_dram[0].size = gd->ram_size / CONFIG_NR_DRAM_BANKS;
++       gd->bd->bi_dram[0].size = gd->ram_size / CONFIG_NR_DRAM_POPULATED;
 +#if ( CONFIG_NR_DRAM_BANKS > 1 )
 +       gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
 +       gd->bd->bi_dram[1].size = gd->ram_size -gd->bd->bi_dram[0].size;
@@ -738,7 +738,7 @@ new file mode 100644
 index 0000000..a6bbbc1
 --- /dev/null
 +++ b/board/armadeus/apf27/lowlevel_init.S
-@@ -0,0 +1,277 @@
+@@ -0,0 +1,275 @@
 +/*
 + * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
 + * Applications Processor Reference Manual, Rev. 0.2".
@@ -859,7 +859,7 @@ index 0000000..a6bbbc1
 +
 +	/* writeb(0xA0001000, any value) */
 +	ldr		r1, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
-+	ldrb		r2, [r1]
++	strb		r2, [r1]
 +
 +	/* writel(ESDCTL0, CONFIG_SYS_AUTOREFRESH_CMD) */
 +	ldr		r1, =CONFIG_SYS_AUTOREFRESH_CMD
@@ -868,7 +868,7 @@ index 0000000..a6bbbc1
 +	ldr 		r4, =PHYS_SDRAM_1	/* CSD0 base address	*/
 +
 +	ldr 		r6,=0x7			/* load loop counter	*/
-+1:	ldr 		r5,[r4]			/* run auto-refresh cycle to array 0 */
++1:	str 		r5,[r4]			/* run auto-refresh cycle to array 0 */
 +	subs 		r6,r6,#1		/* decrease counter value */
 +	bne 1b
 +
@@ -878,17 +878,16 @@ index 0000000..a6bbbc1
 +
 +	/* set standard mode register */
 +	ldr		r4, = PHYS_SDRAM_1+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
-+	ldrb		r2, [r4]
++	strb		r2, [r4]
 +
 +	/* set extended mode register */
 +	ldr		r4, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
-+	ldrb		r5, [r4]
++	strb		r5, [r4]
 +
 +	/* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_NORMAL_RW_CMD) */
 +	ldr		r1, =CONFIG_SYS_NORMAL_RW_CMD
 +	str		r1, [r0, #ESDCTL0_ROF]
 +
-+#if (CONFIG_NR_DRAM_BANKS > 1)
 +	/* 2nd sdram */
 +	/* write32 ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL */
 +	ldr		r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL
@@ -900,7 +899,7 @@ index 0000000..a6bbbc1
 +
 +	/* writeb(0xB0001000, any value) */
 +	ldr		r1, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
-+	ldrb		r2, [r1]
++	strb		r2, [r1]
 +
 +	/* writel(ESDCTL1, CONFIG_SYS_AUTOREFRESH_CMD) */
 +	ldr		r1, =CONFIG_SYS_AUTOREFRESH_CMD
@@ -909,7 +908,7 @@ index 0000000..a6bbbc1
 +	ldr 		r4, =PHYS_SDRAM_2	/* CSD1 base address */
 +
 +	ldr 		r6,=0x7			/* load loop counter */
-+1:	ldr 		r5,[r4]			/* run auto-refresh cycle to array 0 */
++1:	str 		r5,[r4]			/* run auto-refresh cycle to array 0 */
 +	subs 		r6,r6,#1		/* decrease counter value */
 +	bne 1b
 +
@@ -919,16 +918,15 @@ index 0000000..a6bbbc1
 +
 +	/* set standard mode register */
 +	ldr		r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
-+	ldrb		r2, [r4]
++	strb		r2, [r4]
 +
 +	/* set extended mode register */
 +	ldr		r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
-+	ldrb		r2, [r4]
++	strb		r2, [r4]
 +
 +	/* writel(ESDCTL1, CONFIG_SYS_NORMAL_RW_CMD) */
 +	ldr		r1, =CONFIG_SYS_NORMAL_RW_CMD
 +	str		r1, [r0, #ESDCTL1_ROF]
-+#endif  /* CONFIG_NR_DRAM_BANKS > 1 */
 +.endm /* sdram_init */
 +
 +.globl board_init_lowlevel
@@ -1165,7 +1163,7 @@ new file mode 100644
 index 0000000..c8f158d
 --- /dev/null
 +++ b/nand_spl/board/armadeus/apf27/start.S
-@@ -0,0 +1,552 @@
+@@ -0,0 +1,550 @@
 +/*
 + *  IMX27 NAND Flash SPL (Secondary Program Loader)
 + *
@@ -1643,7 +1641,7 @@ index 0000000..c8f158d
 +
 +	/* writeb(0xA0001000, any value) */
 +	ldr		r1, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
-+	ldrb		r2, [r1]
++	strb		r2, [r1]
 +
 +	/* writel(ESDCTL0, CONFIG_SYS_AUTOREFRESH_CMD) */
 +	ldr		r1, =CONFIG_SYS_AUTOREFRESH_CMD
@@ -1652,7 +1650,7 @@ index 0000000..c8f158d
 +	ldr 		r4, =PHYS_SDRAM_1	/* CSD0 base address	*/
 +
 +	ldr 		r6,=0x7			/* load loop counter	*/
-+1:	ldr 		r5,[r4]			/* run auto-refresh cycle to array 0 */
++1:	str 		r5,[r4]			/* run auto-refresh cycle to array 0 */
 +	subs 		r6,r6,#1		/* decrease counter value */
 +	bne 1b
 +
@@ -1662,17 +1660,16 @@ index 0000000..c8f158d
 +
 +	/* set standard mode register */
 +	ldr		r4, = PHYS_SDRAM_1+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
-+	ldrb		r2, [r4]
++	strb		r2, [r4]
 +
 +	/* set extended mode register */
 +	ldr		r4, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
-+	ldrb		r5, [r4]
++	strb		r5, [r4]
 +
 +	/* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_NORMAL_RW_CMD) */
 +	ldr		r1, =CONFIG_SYS_NORMAL_RW_CMD
 +	str		r1, [r0, #ESDCTL0_ROF]
 +
-+#if (CONFIG_NR_DRAM_BANKS > 1)
 +	/* 2nd sdram */
 +	/* writel(ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL ) */
 +	ldr		r0, =IMX_ESD_BASE
@@ -1686,7 +1683,7 @@ index 0000000..c8f158d
 +
 +	/* writeb(0xB0001000, any value) */
 +	ldr		r1, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
-+	ldrb		r2, [r1]
++	strb		r2, [r1]
 +
 +	/* writel(ESDCTL1, CONFIG_SYS_AUTOREFRESH_CMD) */
 +	ldr		r1, =CONFIG_SYS_AUTOREFRESH_CMD
@@ -1695,7 +1692,7 @@ index 0000000..c8f158d
 +	ldr 		r4, =PHYS_SDRAM_2	/* CSD1 base address */
 +
 +	ldr 		r6,=0x7			/* load loop counter */
-+1:	ldr 		r5,[r4]			/* run auto-refresh cycle to array 0 */
++1:	str 		r5,[r4]			/* run auto-refresh cycle to array 0 */
 +	subs 		r6,r6,#1		/* decrease counter value */
 +	bne 1b
 +
@@ -1705,16 +1702,15 @@ index 0000000..c8f158d
 +
 +	/* set standard mode register */
 +	ldr		r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
-+	ldrb		r2, [r4]
++	strb		r2, [r4]
 +
 +	/* set extended mode register */
 +	ldr		r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
-+	ldrb		r2, [r4]
++	strb		r2, [r4]
 +
 +	/* writel(ESDCTL1, CONFIG_SYS_NORMAL_RW_CMD) */
 +	ldr		r1, =CONFIG_SYS_NORMAL_RW_CMD
 +	str		r1, [r0, #ESDCTL1_ROF]
-+#endif  /* CONFIG_NR_DRAM_BANKS > 1 */
 +
 +	mov	pc, lr
 +


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-326-g5c77e77

From: jorasse <jo...@us...> - 2012-05-24 23:19:51

This is an automated email from the git hooks/post-receive script. It was
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- Log -----------------------------------------------------------------
commit 5c77e77f384345fc422f25039d3af59a32c69fd9
Author: Eric Jarrige <eri...@ar...>
Date:   Fri May 25 01:16:44 2012 +0200

    [UBOOT] apf28: U-Boot 2012.04: add support for battery power supply

commit 3eed9cb86708a625f928befd436f22e902803aac
Author: Eric Jarrige <eri...@ar...>
Date:   Fri May 25 01:10:32 2012 +0200

    [UBOOT] apf28: update U-Boot 2012.04 patchs

-----------------------------------------------------------------------

Summary of changes:
 .../u-boot/2012.04/501-imx28-update-and-fix.patch  |   39 +-
 patches/u-boot/2012.04/502-add-apf28.patch         |   66 +-
 .../503-imx28-fix_spl_power_init_IRQ_bit.patch     |   38 -
 .../503-imx28_suppport_battery_power_supply.patch  | 1362 ++++++++++++++++++++
 4 files changed, 1372 insertions(+), 133 deletions(-)
 delete mode 100644 patches/u-boot/2012.04/503-imx28-fix_spl_power_init_IRQ_bit.patch
 create mode 100644 patches/u-boot/2012.04/503-imx28_suppport_battery_power_supply.patch

diff --git a/patches/u-boot/2012.04/501-imx28-update-and-fix.patch b/patches/u-boot/2012.04/501-imx28-update-and-fix.patch
index d1e1c1c..ecb9f6c 100644
--- a/patches/u-boot/2012.04/501-imx28-update-and-fix.patch
+++ b/patches/u-boot/2012.04/501-imx28-update-and-fix.patch
@@ -1,29 +1,10 @@
 Signed-off-by: Eric Jarrige <eri...@ar...>
 Signed-off-by: Philippe Reynes <tr...@ya...>
 ---
- Makefile                                   |    6 ++++++
  arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c |    5 ++++-
  common/memsize.c                           |    2 ++
- tools/mxsboot.c                            |    4 +++-
- 4 files changed, 15 insertions(+), 2 deletions(-)
+ 2 files changed, 6 insertions(+), 1 deletions(-)
 
-diff --git a/Makefile b/Makefile
-index cdd4294..ab9abab 100644
---- a/Makefile
-+++ b/Makefile
-@@ -453,6 +453,12 @@ $(obj)u-boot.sb:       $(obj)u-boot.bin $(obj)spl/u-boot-spl.bin
- 		elftosb -zdf imx28 -c $(TOPDIR)/board/$(BOARDDIR)/u-boot.bd \
- 			-o $(obj)u-boot.sb
- 
-+$(obj)u-boot.nand:       $(obj)u-boot.sb
-+		$(obj)tools/mxsboot nand u-boot.sb u-boot.nand
-+
-+$(obj)u-boot.sd:       $(obj)u-boot.sb
-+		$(obj)tools/mxsboot sd u-boot.sb u-boot.sd
-+
- ifeq ($(CONFIG_SANDBOX),y)
- GEN_UBOOT = \
- 		cd $(LNDIR) && $(CC) $(SYMS) -T $(obj)u-boot.lds \
 diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
 index 911bbef..7c3f1dd 100644
 --- a/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
@@ -60,21 +41,3 @@ index 963e4f3..112ae6e 100644
  	for (cnt = 1; cnt < maxsize / sizeof (long); cnt <<= 1) {
  		addr = base + cnt;	/* pointer arith! */
  		val = *addr;
-diff --git a/tools/mxsboot.c b/tools/mxsboot.c
-index 6c05aa4..7ace37f 100644
---- a/tools/mxsboot.c
-+++ b/tools/mxsboot.c
-@@ -667,7 +667,9 @@ int main(int argc, char **argv)
- 	}
- 
- 	outfd = open(argv[offset + 2], O_CREAT | O_TRUNC | O_WRONLY,
--					S_IRUSR | S_IWUSR);
-+					S_IRUSR | S_IWUSR 
-+					| S_IRGRP | S_IWGRP 
-+					| S_IROTH | S_IWOTH);
- 	if (outfd < 0) {
- 		printf("Output file can not be created\n");
- 		ret = 3;
--- 
-1.7.4.4
-
diff --git a/patches/u-boot/2012.04/502-add-apf28.patch b/patches/u-boot/2012.04/502-add-apf28.patch
index bb26f16..474fe2a 100644
--- a/patches/u-boot/2012.04/502-add-apf28.patch
+++ b/patches/u-boot/2012.04/502-add-apf28.patch
@@ -77,7 +77,7 @@ new file mode 100644
 index 0000000..c00b55c
 --- /dev/null
 +++ b/board/armadeus/apf28/apf28.c
-@@ -0,0 +1,236 @@
+@@ -0,0 +1,191 @@
 +/*
 + * APF28 motherboard based on DENX M28 module
 + *
@@ -150,25 +150,9 @@ index 0000000..c00b55c
 +	return 0;
 +}
 +
-+#define	HW_DIGCTRL_SCRATCH0	0x8001c280
-+#define	HW_DIGCTRL_SCRATCH1	0x8001c290
 +int dram_init(void)
 +{
-+	uint32_t sz[2];
-+
-+	sz[0] = readl(HW_DIGCTRL_SCRATCH0);
-+	sz[1] = readl(HW_DIGCTRL_SCRATCH1);
-+
-+	if (sz[0] != sz[1]) {
-+		printf("MX28:\n"
-+			"Error, the RAM size in HW_DIGCTRL_SCRATCH0 and\n"
-+			"HW_DIGCTRL_SCRATCH1 is not the same. Please\n"
-+			"verify these two registers contain valid RAM size!\n");
-+		hang();
-+	}
-+
-+	gd->ram_size = sz[0];
-+	return 0;
++	return mx28_dram_init();
 +}
 +
 +#ifdef	CONFIG_CMD_MMC
@@ -241,7 +225,6 @@ index 0000000..c00b55c
 +	}
 +
 +	if (!eth_getenv_enetaddr(STR_ENV_ETHADDR, eth_addr)) {
-+		dev = eth_get_dev_by_index(0);
 +		if (dev) {
 +			eth_setenv_enetaddr(STR_ENV_ETHADDR, dev->enetaddr);
 +		} else {
@@ -269,50 +252,22 @@ index 0000000..c00b55c
 +}
 +#endif
 +
-+#ifdef	CONFIG_M28_FEC_MAC_IN_OCOTP
-+
-+#define	MXS_OCOTP_MAX_TIMEOUT	1000000
-+void imx_get_mac_from_fuse(char *mac)
++#ifdef	CONFIG_MX28_FEC_MAC_IN_OCOTP
++void mx28_adjust_mac(int dev_id, unsigned char *mac)
 +{
 +	struct mx28_ocotp_regs *ocotp_regs =
 +		(struct mx28_ocotp_regs *)MXS_OCOTP_BASE;
-+	uint32_t data;
-+
-+	memset(mac, 0, 6);
-+
-+	writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
-+
-+	if (mx28_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
-+				MXS_OCOTP_MAX_TIMEOUT)) {
-+		printf("MXS FEC: Can't get MAC from OCOTP\n");
-+		return;
-+	}
-+
-+	data = readl(&ocotp_regs->hw_ocotp_cust0);
 +
 +	writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_clr);
 +
 +	mac[0] = (ACFG_OUI>> 16) & 0xff;
 +	mac[1] = (ACFG_OUI>> 8) & 0xff;
-+	mac[2] = (data >> 24) & 0xff;
-+	mac[3] = (data >> 16) & 0xff;
-+	mac[4] = (data >> 8) & 0xff;
-+	mac[5] = data & 0xff;
-+}
-+#else
-+void imx_get_mac_from_fuse(char *mac)
-+{
-+	memset(mac, 0, 6);
-+}
-+#endif
 +
++	if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
++		mac[5] += 1;
++}
 +#endif
 +
-+#ifndef	CONFIG_SYS_DCACHE_OFF
-+void enable_caches(void)
-+{
-+	/* dcache_enable(); */
-+}
 +#endif
 diff --git a/board/armadeus/apf28/cmd_ocotp.c b/board/armadeus/apf28/cmd_ocotp.c
 new file mode 100644
@@ -1394,14 +1349,11 @@ diff --git a/boards.cfg b/boards.cfg
 index fdd0ffb..910b611 100644
 --- a/boards.cfg
 +++ b/boards.cfg
-@@ -162,6 +162,7 @@ tx25                         arm         arm926ejs   tx25                karo
+@@ -159,6 +159,7 @@ tx25                         arm        
  zmx25                        arm         arm926ejs   zmx25               syteco         mx25
  imx27lite                    arm         arm926ejs   imx27lite           logicpd        mx27
  magnesium                    arm         arm926ejs   imx27lite           logicpd        mx27
 +apf28                        arm         arm926ejs   -                   armadeus       mx28
  m28evk                       arm         arm926ejs   -                   denx           mx28
- mx28evk                      arm         arm926ejs   -                   freescale      mx28
  nhk8815                      arm         arm926ejs   nhk8815             st             nomadik
--- 
-1.7.4.4
-
+ nhk8815_onenand              arm         arm926ejs   nhk8815             st             nomadik       nhk8815:BOOT_ONENAND
diff --git a/patches/u-boot/2012.04/503-imx28-fix_spl_power_init_IRQ_bit.patch b/patches/u-boot/2012.04/503-imx28-fix_spl_power_init_IRQ_bit.patch
deleted file mode 100644
index 97cfc40..0000000
--- a/patches/u-boot/2012.04/503-imx28-fix_spl_power_init_IRQ_bit.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-Signed-off-by: Eric Jarrige <eri...@ar...>
-Signed-off-by: Philippe Reynes <tr...@ya...>
----
- arch/arm/cpu/arm926ejs/mx28/spl_power_init.c |   10 +++++-----
- 1 files changed, 5 insertions(+), 5 deletions(-)
-
-diff --git a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
-index aa4117d..51e9131 100644
---- a/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
-+++ b/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
-@@ -187,7 +187,7 @@ void mx28_enable_4p2_dcdc_input(int xfer)
- 	writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
- 		&power_regs->hw_power_reset);
- 
--	clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
-+	writel(POWER_CTRL_ENIRQ_VDD5V_DROOP, &power_regs->hw_power_ctrl_clr);
- 
- 	if (xfer && (readl(&power_regs->hw_power_5vctrl) &
- 			POWER_5VCTRL_ENABLE_DCDC)) {
-@@ -260,11 +260,11 @@ void mx28_enable_4p2_dcdc_input(int xfer)
- 			&power_regs->hw_power_ctrl_clr);
- 
- 	if (prev_5v_droop)
--		clrbits_le32(&power_regs->hw_power_ctrl,
--				POWER_CTRL_ENIRQ_VDD5V_DROOP);
-+		writel(POWER_CTRL_ENIRQ_VDD5V_DROOP, 
-+				&power_regs->hw_power_ctrl_clr);
- 	else
--		setbits_le32(&power_regs->hw_power_ctrl,
--				POWER_CTRL_ENIRQ_VDD5V_DROOP);
-+		writel(POWER_CTRL_ENIRQ_VDD5V_DROOP, 
-+				&power_regs->hw_power_ctrl_clr);
- }
- 
- void mx28_power_init_4p2_regulator(void)
--- 
-1.7.4.4
-
diff --git a/patches/u-boot/2012.04/503-imx28_suppport_battery_power_supply.patch b/patches/u-boot/2012.04/503-imx28_suppport_battery_power_supply.patch
new file mode 100644
index 0000000..f84f9a4
--- /dev/null
+++ b/patches/u-boot/2012.04/503-imx28_suppport_battery_power_supply.patch
@@ -0,0 +1,1362 @@
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+--- uboot-custom/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
++++ uboot-custom/arch/arm/cpu/arm926ejs/mx28/spl_mem_init.c
+@@ -159,10 +159,13 @@ void mx28_mem_setup_vdda(void)
+ 	struct mx28_power_regs *power_regs =
+ 		(struct mx28_power_regs *)MXS_POWER_BASE;
+ 
+-	writel((0xc << POWER_VDDACTRL_TRG_OFFSET) |
+-		(0x7 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
+-		POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW,
+-		&power_regs->hw_power_vddactrl);
++	clrsetbits_le32(&power_regs->hw_power_vddactrl,
++		POWER_VDDACTRL_LINREG_OFFSET_MASK |
++		POWER_VDDACTRL_BO_OFFSET_MASK |
++		POWER_VDDACTRL_TRG_MASK,
++		(0xc << POWER_VDDACTRL_TRG_OFFSET) |
++		(0x6 << POWER_VDDACTRL_BO_OFFSET_OFFSET) |
++		POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
+ }
+ 
+ void mx28_mem_setup_vddd(void)
+@@ -170,10 +173,13 @@ void mx28_mem_setup_vddd(void)
+ 	struct mx28_power_regs *power_regs =
+ 		(struct mx28_power_regs *)MXS_POWER_BASE;
+ 
+-	writel((0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
++	clrsetbits_le32(&power_regs->hw_power_vdddctrl,
++		POWER_VDDDCTRL_LINREG_OFFSET_MASK |
++		POWER_VDDDCTRL_BO_OFFSET_MASK |
++		POWER_VDDDCTRL_TRG_MASK,
++		(0x1c << POWER_VDDDCTRL_TRG_OFFSET) |
+ 		(0x7 << POWER_VDDDCTRL_BO_OFFSET_OFFSET) |
+-		POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW,
+-		&power_regs->hw_power_vdddctrl);
++		POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
+ }
+ 
+ void mx28_mem_get_size(void)
+--- uboot-custom/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
++++ uboot-custom/arch/arm/cpu/arm926ejs/mx28/spl_power_init.c
+@@ -30,6 +30,12 @@
+ 
+ #include "mx28_init.h"
+ 
++/* if you accidentally define both, don't allow a successful compile. */
++#if defined(CONFIG_SYS_NO_DCDC_BATT_SOURCE) \
++	&& defined(CONFIG_SYS_NO_VDD5V_SOURCE)
++#error Invalid power source configuration.
++#endif
++
+ void mx28_power_clock2xtal(void)
+ {
+ 	struct mx28_clkctrl_regs *clkctrl_regs =
+@@ -64,25 +70,6 @@ void mx28_power_clear_auto_restart(void)
+ 	writel(RTC_CTRL_CLKGATE, &rtc_regs->hw_rtc_ctrl_clr);
+ 	while (readl(&rtc_regs->hw_rtc_ctrl) & RTC_CTRL_CLKGATE)
+ 		;
+-
+-	/*
+-	 * Due to the hardware design bug of mx28 EVK-A
+-	 * we need to set the AUTO_RESTART bit.
+-	 */
+-	if (readl(&rtc_regs->hw_rtc_persistent0) & RTC_PERSISTENT0_AUTO_RESTART)
+-		return;
+-
+-	while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
+-		;
+-
+-	setbits_le32(&rtc_regs->hw_rtc_persistent0,
+-			RTC_PERSISTENT0_AUTO_RESTART);
+-	writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_set);
+-	writel(RTC_CTRL_FORCE_UPDATE, &rtc_regs->hw_rtc_ctrl_clr);
+-	while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_NEW_REGS_MASK)
+-		;
+-	while (readl(&rtc_regs->hw_rtc_stat) & RTC_STAT_STALE_REGS_MASK)
+-		;
+ }
+ 
+ void mx28_power_set_linreg(void)
+@@ -147,6 +134,15 @@ void mx28_src_power_init(void)
+ 	clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER);
+ }
+ 
++void mx28_powerdown(void)
++{
++	struct mx28_power_regs *power_regs =
++		(struct mx28_power_regs *)MXS_POWER_BASE;
++	writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
++	writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
++		&power_regs->hw_power_reset);
++}
++
+ void mx28_power_init_4p2_params(void)
+ {
+ 	struct mx28_power_regs *power_regs =
+@@ -161,10 +157,17 @@ void mx28_power_init_4p2_params(void)
+ 		POWER_5VCTRL_HEADROOM_ADJ_MASK,
+ 		0x4 << POWER_5VCTRL_HEADROOM_ADJ_OFFSET);
+ 
++#if defined(CONFIG_SYS_NO_DCDC_BATT_SOURCE)
++/* don't use the DCDC_BATT source if configured not to */
++	clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
++		POWER_DCDC4P2_DROPOUT_CTRL_MASK,
++		POWER_DCDC4P2_DROPOUT_CTRL_100MV);
++#else
+ 	clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
+ 		POWER_DCDC4P2_DROPOUT_CTRL_MASK,
+ 		POWER_DCDC4P2_DROPOUT_CTRL_100MV |
+ 		POWER_DCDC4P2_DROPOUT_CTRL_SRC_SEL);
++#endif
+ 
+ 	clrsetbits_le32(&power_regs->hw_power_5vctrl,
+ 		POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
+@@ -175,20 +178,9 @@ void mx28_enable_4p2_dcdc_input(int xfer
+ {
+ 	struct mx28_power_regs *power_regs =
+ 		(struct mx28_power_regs *)MXS_POWER_BASE;
+-	uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo;
++	uint32_t tmp, vbus_thresh;
+ 	uint32_t prev_5v_brnout, prev_5v_droop;
+ 
+-	prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
+-				POWER_5VCTRL_PWDN_5VBRNOUT;
+-	prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
+-				POWER_CTRL_ENIRQ_VDD5V_DROOP;
+-
+-	clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
+-	writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
+-		&power_regs->hw_power_reset);
+-
+-	clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
+-
+ 	if (xfer && (readl(&power_regs->hw_power_5vctrl) &
+ 			POWER_5VCTRL_ENABLE_DCDC)) {
+ 		return;
+@@ -200,19 +192,24 @@ void mx28_enable_4p2_dcdc_input(int xfer
+ 	 */
+ 	tmp = readl(&power_regs->hw_power_5vctrl);
+ 	vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK;
+-	vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT;
+-
+-	pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO;
+ 
+ 	/*
+ 	 * Disable mechanisms that get erroneously tripped by when setting
+ 	 * the DCDC4P2 EN_DCDC
+ 	 */
+ 	clrbits_le32(&power_regs->hw_power_5vctrl,
+-		POWER_5VCTRL_VBUSVALID_5VDETECT |
+ 		POWER_5VCTRL_VBUSVALID_TRSH_MASK);
+ 
+-	writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set);
++	prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) &
++				POWER_5VCTRL_PWDN_5VBRNOUT;
++	prev_5v_droop = readl(&power_regs->hw_power_ctrl) &
++				POWER_CTRL_ENIRQ_VDD5V_DROOP;
++
++	clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT);
++	writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
++		&power_regs->hw_power_reset);
++
++	clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP);
+ 
+ 	if (xfer) {
+ 		setbits_le32(&power_regs->hw_power_5vctrl,
+@@ -230,19 +227,25 @@ void mx28_enable_4p2_dcdc_input(int xfer
+ 
+ 	early_delay(25);
+ 
+-	clrsetbits_le32(&power_regs->hw_power_5vctrl,
+-			POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
+-
+-	if (vbus_5vdetect)
+-		writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set);
+-
+-	if (!pwd_bo)
+-		clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO);
++	if(readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
++	{
++		writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
++			&power_regs->hw_power_5vctrl_set);
++		writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
++			&power_regs->hw_power_5vctrl_clr);
++	}
+ 
+ 	while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ)
+ 		writel(POWER_CTRL_VBUS_VALID_IRQ,
+ 			&power_regs->hw_power_ctrl_clr);
+ 
++	while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
++		writel(POWER_CTRL_VDD5V_DROOP_IRQ,
++			&power_regs->hw_power_ctrl_clr);
++
++	clrsetbits_le32(&power_regs->hw_power_5vctrl,
++			POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh);
++
+ 	if (prev_5v_brnout) {
+ 		writel(POWER_5VCTRL_PWDN_5VBRNOUT,
+ 			&power_regs->hw_power_5vctrl_set);
+@@ -255,10 +258,6 @@ void mx28_enable_4p2_dcdc_input(int xfer
+ 			&power_regs->hw_power_reset);
+ 	}
+ 
+-	while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ)
+-		writel(POWER_CTRL_VDD5V_DROOP_IRQ,
+-			&power_regs->hw_power_ctrl_clr);
+-
+ 	if (prev_5v_droop)
+ 		clrbits_le32(&power_regs->hw_power_ctrl,
+ 				POWER_CTRL_ENIRQ_VDD5V_DROOP);
+@@ -299,55 +298,38 @@ void mx28_power_init_4p2_regulator(void)
+ 		 * not present. Exiting to not enable DCDC power during 5V
+ 		 * connected state.
+ 		 */
+-		clrbits_le32(&power_regs->hw_power_dcdc4p2,
+-			POWER_DCDC4P2_ENABLE_DCDC);
+-		writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+-			&power_regs->hw_power_5vctrl_set);
+-		hang();
++		early_delay(100);
++		mx28_powerdown();
+ 	}
+ 
+ 	/*
+-	 * Here we set the 4p2 brownout level to something very close to 4.2V.
+-	 * We then check the brownout status. If the brownout status is false,
+-	 * the voltage is already close to the target voltage of 4.2V so we
+-	 * can go ahead and set the 4P2 current limit to our max target limit.
+-	 * If the brownout status is true, we need to ramp us the current limit
+-	 * so that we don't cause large inrush current issues. We step up the
+-	 * current limit until the brownout status is false or until we've
+-	 * reached our maximum defined 4p2 current limit.
++	 * Ramp up the current limit to avoid large inrush current.
+ 	 */
+-	clrsetbits_le32(&power_regs->hw_power_dcdc4p2,
+-			POWER_DCDC4P2_BO_MASK,
+-			22 << POWER_DCDC4P2_BO_OFFSET);	/* 4.15V */
+-
+-	if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) {
+-		setbits_le32(&power_regs->hw_power_5vctrl,
+-			0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
+-	} else {
+-		tmp = (readl(&power_regs->hw_power_5vctrl) &
+-			POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
+-			POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
+-		while (tmp < 0x3f) {
+-			if (!(readl(&power_regs->hw_power_sts) &
+-					POWER_STS_DCDC_4P2_BO)) {
+-				tmp = readl(&power_regs->hw_power_5vctrl);
+-				tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
+-				early_delay(100);
+-				writel(tmp, &power_regs->hw_power_5vctrl);
+-				break;
+-			} else {
+-				tmp++;
+-				tmp2 = readl(&power_regs->hw_power_5vctrl);
+-				tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
+-				tmp2 |= tmp <<
+-					POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
+-				writel(tmp2, &power_regs->hw_power_5vctrl);
+-				early_delay(100);
+-			}
+-		}
++	tmp = (readl(&power_regs->hw_power_5vctrl) &
++		POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >>
++		POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
++	while (tmp < 0x3f) {
++		tmp++;
++		tmp2 = readl(&power_regs->hw_power_5vctrl) &
++			~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
++		tmp2 |= tmp << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
++		writel(tmp2, &power_regs->hw_power_5vctrl);
++		early_delay(100);
+ 	}
+ 
++#ifdef CONFIG_SYS_VBUS_CURRENT_DRAW
++		/* VDD5V is sourced from VBUS,limit the current to 100mA */
++		tmp2 = readl(&power_regs->hw_power_5vctrl) &
++			~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK;
++		tmp2 |= 0x08 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET;
++		writel(tmp2, &power_regs->hw_power_5vctrl);
++
++		early_delay(10000);
++#endif
++
+ 	clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK);
++	early_delay(100000);
++
+ 	writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+ }
+ 
+@@ -356,20 +338,14 @@ void mx28_power_init_dcdc_4p2_source(voi
+ 	struct mx28_power_regs *power_regs =
+ 		(struct mx28_power_regs *)MXS_POWER_BASE;
+ 
+-	if (!(readl(&power_regs->hw_power_dcdc4p2) &
+-		POWER_DCDC4P2_ENABLE_DCDC)) {
+-		hang();
+-	}
+-
+ 	mx28_enable_4p2_dcdc_input(1);
+ 
+ 	if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) {
+-		clrbits_le32(&power_regs->hw_power_dcdc4p2,
+-			POWER_DCDC4P2_ENABLE_DCDC);
+-		writel(POWER_5VCTRL_ENABLE_DCDC,
+-			&power_regs->hw_power_5vctrl_clr);
+-		writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
+-			&power_regs->hw_power_5vctrl_set);
++		/* Enabling of DCDC failed at setting of 5VCTRL ENABLE_DCDC.
++		 * We need power down device.
++		 */
++		early_delay(100);
++		mx28_powerdown();
+ 	}
+ }
+ 
+@@ -450,15 +426,6 @@ void mx28_boot_valid_5v(void)
+ 	mx28_power_enable_4p2();
+ }
+ 
+-void mx28_powerdown(void)
+-{
+-	struct mx28_power_regs *power_regs =
+-		(struct mx28_power_regs *)MXS_POWER_BASE;
+-	writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset);
+-	writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF,
+-		&power_regs->hw_power_reset);
+-}
+-
+ void mx28_handle_5v_conflict(void)
+ {
+ 	struct mx28_power_regs *power_regs =
+@@ -530,10 +497,10 @@ void mx28_init_batt_bo(void)
+ 	struct mx28_power_regs *power_regs =
+ 		(struct mx28_power_regs *)MXS_POWER_BASE;
+ 
+-	/* Brownout at 3V */
++	/* Brownout at 3.2V */
+ 	clrsetbits_le32(&power_regs->hw_power_battmonitor,
+ 		POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
+-		15 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
++		20 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
+ 
+ 	writel(POWER_CTRL_BATT_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+ 	writel(POWER_CTRL_ENIRQ_BATT_BO, &power_regs->hw_power_ctrl_clr);
+@@ -601,15 +568,418 @@ int mx28_is_batt_good(void)
+ 	return 0;
+ }
+ 
+-void mx28_power_configure_power_source(void)
++void mx28_lradc_init(int bEnableOnChipGroundRef, int eFreq)
++{
++	static int lradcInitialized = 0;
++	struct mx28_lradc_regs *lradc_regs =
++		(struct mx28_lradc_regs *)MXS_LRADC_BASE;
++
++	if( lradcInitialized )
++	{
++		return;
++	}
++
++	/* Clear the Soft Reset for normal operation */
++	clrbits_le32(&lradc_regs->hw_lradc_ctrl0, LRADC_CTRL0_SFTRST);
++
++	/* Clear the Clock Gate for normal operation */
++	clrbits_le32(&lradc_regs->hw_lradc_ctrl0, LRADC_CTRL0_CLKGATE);
++
++	/* Set on-chip ground ref */
++	if(bEnableOnChipGroundRef) {
++		/* Enable the onchip ground ref of LRADC conversions */
++		setbits_le32(&lradc_regs->hw_lradc_ctrl0,
++			LRADC_CTRL0_ONCHIP_GROUNDREF);
++	} else {
++		/* Disable the onchip ground ref of LRADC conversions */
++		clrbits_le32(&lradc_regs->hw_lradc_ctrl0,
++			LRADC_CTRL0_ONCHIP_GROUNDREF);
++	}
++
++	/* Set LRADC conversion clock frequency */
++	clrsetbits_le32(&lradc_regs->hw_lradc_ctrl3,
++			LRADC_CTRL3_CYCLE_TIME_MASK,
++			LRADC_CTRL3_CYCLE_TIME(eFreq));
++
++	/* Make sure the LRADC channel-6 selected for VDDIO */
++	clrsetbits_le32(&lradc_regs->hw_lradc_ctrl4,
++			LRADC_CTRL4_LRADC6SELECT_MASK,
++			LRADC_CTRL4_LRADC6SELECT(
++				LRADC_CTRL4_LRADC6SELECT__CHANNEL6)
++			);
++
++	/* Make sure the LRADC channel-7 selected for Battery */
++	clrsetbits_le32(&lradc_regs->hw_lradc_ctrl4,
++			LRADC_CTRL4_LRADC7SELECT_MASK,
++			LRADC_CTRL4_LRADC7SELECT(
++				LRADC_CTRL4_LRADC7SELECT__CHANNEL7)
++			);
++
++	lradcInitialized = 1;
++}
++
++void mx28_lradc_configure_channel( int eChannel,
++				int bEnableDivideByTwo,
++				int bEnableAccum,
++				uint8_t u8NumSamples)
++{
++	struct mx28_lradc_regs *lradc_regs =
++		(struct mx28_lradc_regs *)MXS_LRADC_BASE;
++
++	/* Set the analog divide-by two function */
++	if(bEnableDivideByTwo) {
++		/* Enable the divide-by-two of a LRADC channel */
++		setbits_le32(&lradc_regs->hw_lradc_ctrl2,
++			LRADC_CTRL2_DIVIDE_BY_TWO(1 << eChannel));
++	} else {
++		/* Disable the divide-by-two of a LRADC channel */
++		clrbits_le32(&lradc_regs->hw_lradc_ctrl2,
++			LRADC_CTRL2_DIVIDE_BY_TWO(1 << eChannel));
++	}
++
++	/* Clear the accumulator & NUM_SAMPLES */
++	clrbits_le32(&lradc_regs->hw_lradc_ch0 + (eChannel * 4),
++			0xFFFFFFFF);
++
++	/* Sets NUM_SAMPLES bitfield of HW_LRADC_CHn register. */
++	clrsetbits_le32(&lradc_regs->hw_lradc_ch0 + (eChannel * 4),
++			LRADC_CHn_NUM_SAMPLES_MASK,
++			LRADC_CHn_NUM_SAMPLES(u8NumSamples));
++
++	/* Set ACCUMULATE bit of HW_LRADC_CHn register */
++	if(bEnableAccum) {
++		/* Enable the accumulation of a LRADC channel */
++		setbits_le32(&lradc_regs->hw_lradc_ch0 + (eChannel * 4),
++			LRADC_CHn_ACCUMULATE);
++	} else {
++		/* Disable the accumulation of a LRADC channel */
++		clrbits_le32(&lradc_regs->hw_lradc_ch0 + (eChannel * 4),
++			LRADC_CHn_ACCUMULATE);
++	}
++}
++
++void mx28_lradc_set_delay_trigger(int eDelayTrigger,
++				uint32_t u32TriggerLradcs,
++				uint32_t u32DelayTriggers,
++				uint32_t u32LoopCount,
++				uint32_t u32DelayCount)
++{
++	struct mx28_lradc_regs *lradc_regs =
++		(struct mx28_lradc_regs *)MXS_LRADC_BASE;
++
++	/* Set the TRIGGER_LRADCS bitfield of HW_LRADC_DELAYn register */
++	setbits_le32(&lradc_regs->hw_lradc_delay0 + (eDelayTrigger * 4),
++			LRADC_DELAYn_TRIGGER_LRADCS(u32TriggerLradcs));
++
++	/* Set the TRIGGER_DELAYS bitfield of HW_LRADC_DELAYn register */
++	setbits_le32(&lradc_regs->hw_lradc_delay0 + (eDelayTrigger * 4),
++			LRADC_DELAYn_TRIGGER_DELAYS(u32DelayTriggers));
++
++	/* Write the LOOP_COUNT bitfield of HW_LRADC_DELAYn register */
++	clrsetbits_le32(&lradc_regs->hw_lradc_delay0 + (eDelayTrigger * 4),
++			LRADC_DELAYn_LOOP_COUNT_MASK,
++			LRADC_DELAYn_LOOP_COUNT(u32LoopCount));
++
++	/* Write the DEALY bitfield of HW_LRADC_DELAYn register */
++	clrsetbits_le32(&lradc_regs->hw_lradc_delay0 + (eDelayTrigger * 4),
++			LRADC_DELAYn_DELAY_MASK,
++			LRADC_DELAYn_DELAY(u32DelayCount));
++}
++
++int mx28_lradc_enable_battery_measurement( int eTrigger,
++					uint16_t u16SamplingInterval)
++{
++	struct mx28_lradc_regs *lradc_regs =
++		(struct mx28_lradc_regs *)MXS_LRADC_BASE;
++
++	/*
++	 * Check if the lradc battery voltage channel
++	 * is present in this product
++	 */
++	if ( (readl(&lradc_regs->hw_lradc_status)
++		& LRADC_STATUS_CHANNEL7_PRESENT) == 0 ) return 0;
++
++	/* Disable the channel interrupt */
++	clrbits_le32(&lradc_regs->hw_lradc_ctrl1, LRADC_CTRL1_LRADC7_IRQ_EN);
++	clrbits_le32(&lradc_regs->hw_lradc_ctrl1, LRADC_CTRL1_LRADC7_IRQ);
++
++	/* Configure the battery conversion register */
++	clrsetbits_le32(&lradc_regs->hw_lradc_conversion,
++			LRADC_CONVERSION_SCALE_FACTOR_MASK,
++			LRADC_CONVERSION_SCALE_FACTOR(2)
++			);
++
++
++	/*
++	 * Enable the automatic update mode of BATT_VALUE field
++	 * in HW_POWER_MONITOR
++	 */
++	setbits_le32(&lradc_regs->hw_lradc_conversion,
++		LRADC_CONVERSION_AUTOMATIC);
++
++	mx28_lradc_configure_channel( 7, /* Lradc battery voltage channel */
++				0, /* DIVIDE_BY_TWO */
++				0, /* ACCUMULATE */
++				0); /* NUM_SAMPLES */
++
++	/* schedule a conversion before the setting up of the delay channel */
++	/* so the user can have a good value right after the function returns */
++	setbits_le32(&lradc_regs->hw_lradc_ctrl0, LRADC_CTRL0_SCHEDULE(1<<7));
++
++	/* Setup the trigger loop forever, */
++	mx28_lradc_set_delay_trigger( eTrigger, /* Trigger Index */
++				(1 << 7), /* Lradc channels */
++				(1 << eTrigger), /* Restart the triggers */
++				0, /* No loop count */
++				u16SamplingInterval); /* 0.5*N msec on 2khz */
++
++	/* Clear the accumulator & NUM_SAMPLES */
++	clrbits_le32(&lradc_regs->hw_lradc_ch7, 0xFFFFFFFF);
++
++	/* Kick off the LRADC battery measurement */
++	setbits_le32(&lradc_regs->hw_lradc_delay0 + (eTrigger * 4),
++			LRADC_DELAYn_KICK);
++
++
++	/* Wait for first measurement of battery.  Should occur in 13 LRADC clock
++	 * cycles from the time of channel kickoff.  Also add some wait time for
++	 * copy to the power supply BATT_VAL field to occur.
++	 */
++	early_delay(10);
++
++	return 1;
++}
++
++void mx28_power_setup_batt_detect(void)
++{
++#define BATTERY_MONITOR_LRADC_TRIGGER	3
++
++	/* Initialize LRADC for battery monitoring. */
++	mx28_lradc_init(0, LRADC_CTRL3_CYCLE_TIME__6MHZ);
++
++	mx28_lradc_enable_battery_measurement(
++		BATTERY_MONITOR_LRADC_TRIGGER,
++		100);
++}
++
++void mx28_power_setup_batt_boot(void)
+ {
++	struct mx28_power_regs *power_regs =
++		(struct mx28_power_regs *)MXS_POWER_BASE;
++
++	/* disable automatic hardware powerdown as the system is configured */
++	/* for 5v removal */
++	writel(POWER_5VCTRL_PWDN_5VBRNOUT,
++		&power_regs->hw_power_5vctrl_clr);
++	/* now that protection is enabled, we can startup the DCDC converter */
++	/*HW_POWER_5VCTRL_SET(BM_POWER_5VCTRL_ENABLE_DCDC);*/
++	/* For maximum stability on the Vddd rail, we will leave the
++	* Vddd linreg forced on (even under battery power).  The linreg
++	* will only regulate if the target voltage get 25mV below the
++	* DCDC target
++	*/
++	/*Disable DCDC*/
++	writel(POWER_5VCTRL_ENABLE_DCDC,
++		&power_regs->hw_power_5vctrl_clr);
++
++	clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_DCDC);
++	clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2);
++	writel(POWER_CHARGE_ENABLE_LOAD,
++		&power_regs->hw_power_charge_clr);
++
++	/* Set DCDC_XFER to init DCDC for 100us*/
++	writel(POWER_5VCTRL_DCDC_XFER,
++		&power_regs->hw_power_5vctrl_set);
++	early_delay(1000);
++	writel(POWER_5VCTRL_DCDC_XFER,
++		&power_regs->hw_power_5vctrl_clr);
++
++	writel(POWER_CTRL_ENIRQ_DCDC4P2_BO,
++		&power_regs->hw_power_ctrl_clr);
++
++	/*Enable double FETs to make DCDC more powerful*/
++	writel(POWER_MINPWR_HALFFETS,
++		&power_regs->hw_power_minpwr_clr);
++	writel(POWER_MINPWR_DOUBLE_FETS,
++		&power_regs->hw_power_minpwr_set);
++
++	/* This should have already been done, but just in case */
++	clrsetbits_le32(&power_regs->hw_power_vdddctrl,
++			POWER_VDDDCTRL_LINREG_OFFSET_MASK,
++			POWER_VDDDCTRL_LINREG_OFFSET_1STEPS_BELOW);
++
++	clrsetbits_le32(&power_regs->hw_power_vddactrl,
++			POWER_VDDACTRL_LINREG_OFFSET_MASK,
++			POWER_VDDACTRL_LINREG_OFFSET_1STEPS_BELOW);
++
++	clrsetbits_le32(&power_regs->hw_power_vddioctrl,
++			POWER_VDDIOCTRL_LINREG_OFFSET_MASK,
++			POWER_VDDIOCTRL_LINREG_OFFSET_1STEPS_BELOW);
++
++	/* Enabe DCDC output to Vddd rail */
++	clrbits_le32(&power_regs->hw_power_vdddctrl,
++			POWER_VDDDCTRL_DISABLE_FET);
++	clrbits_le32(&power_regs->hw_power_vddioctrl,
++			POWER_VDDIOCTRL_DISABLE_FET);
++	clrbits_le32(&power_regs->hw_power_vddactrl,
++			POWER_VDDACTRL_DISABLE_FET);
++
++	clrbits_le32(&power_regs->hw_power_vdddctrl,
++			POWER_VDDDCTRL_ENABLE_LINREG);
++	clrbits_le32(&power_regs->hw_power_vddactrl,
++			POWER_VDDACTRL_ENABLE_LINREG);
++
++	writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK,
++		&power_regs->hw_power_5vctrl_set);
++	/* Enable DCDC*/
++	writel(POWER_5VCTRL_ENABLE_DCDC,
++		&power_regs->hw_power_5vctrl_set);
++
++	clrsetbits_le32(&power_regs->hw_power_5vctrl_set,
++			POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK,
++			0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET);
++	/* Set current limit of Linear regulator to 0mA.*/
++/*	HW_POWER_5VCTRL_SET(BM_POWER_5VCTRL_ILIMIT_EQ_ZERO); */
++}
++
++int mx28_power_configure_power_source(void)
++{
++	struct mx28_power_regs *power_regs =
++		(struct mx28_power_regs *)MXS_POWER_BASE;
++#if defined(CONFIG_SYS_NO_DCDC_BATT_SOURCE) \
++	|| defined(CONFIG_SYS_NO_VDD5V_SOURCE)
++	struct mx28_rtc_regs *rtc_regs =
++		(struct mx28_rtc_regs *)MXS_RTC_BASE;
++#endif
++
++	int battery_ready = 0;
++
+ 	mx28_src_power_init();
+ 
++#if defined(CONFIG_SYS_NO_DCDC_BATT_SOURCE)
++
++	/* Device configured for no source to DCDC_BATT input (5V only power
++	 * source). This boot option doesn't waste time looking for a good
++	 * battery.  Battery powered operation and automatic voltage
++	 * measurements are disabled.
++	 */
++
++	/* bit 11 of PERSISTENT1 */
++	writel(0x800, &rtc_regs->hw_rtc_persistent1_set);
++	
++
++	battery_ready = 0;
++
++	/* Disable automatic battery voltage measurements which seem unnecessary
++	 * for this configuration.
++	 */
++	setbits_le32(&power_regs->hw_power_battmonitor,
++		POWER_BATTMONITOR_EN_BATADJ);
++	writel(LRADC_CONVERSION_AUTOMATIC,
++		&lradc_regs->hw_lradc_conversion_clr);
++	clrsetbits_le32(&power_regs->hw_power_battmonitor,
++		POWER_BATTMONITOR_BATT_VAL_MASK,
++		525 << POWER_BATTMONITOR_BATT_VAL_OFFSE);
++	/* Brownout at 3.2V */
++	clrsetbits_le32(&power_regs->hw_power_battmonitor,
++		POWER_BATTMONITOR_BRWNOUT_LVL_MASK,
++		20 << POWER_BATTMONITOR_BRWNOUT_LVL_OFFSET);
++
+ 	mx28_5v_boot();
++
++#if !defined(CONFIG_SYS_VBUS_CURRENT_DRAW)
++	mx28_power_clock2pll();
++#endif
++
++#elif defined(CONFIG_SYS_NO_VDD5V_SOURCE)
++	/* Device Configured for DCDC_BATT only power source.
++	 * We only care about the DCDC_BATT source in this configuration.
++	 */
++	setbits_le32(&power_regs->hw_power_battmonitor,
++		POWER_BATTMONITOR_PWDN_BATTBRNOUT_5VDETECT_EN);
++
++	writel(0x800, &rtc_regs->hw_rtc_persistent1_set);
++
++	/* since the DCDC_BATT input is our only source, we'll assume
++	 * it is good and attempt to boot.  If your device has uses
++	 * this configuration but has a external DCDC_BATT source
++	 * that takes time to ramp, you could add a voltage check
++	 * and wait here until voltage reaches near the final level to
++	 * avoid trigger a battery brownout when the voltage is too
++	 * low.
++	 */
++	battery_ready = 1;
++
++	/*Boot from DCDC_BATT source*/
++	mx28_power_setup_batt_boot();
+ 	mx28_power_clock2pll();
+ 
++	/* raise battery brownout level to programmed value. */
+ 	mx28_init_batt_bo();
++
++	/* Configured to not use a VDD5V source */
++	writel(POWER_5VCTRL_ILIMIT_EQ_ZERO, &power_regs->hw_power_5vctrl_set);
++
++#else
++
++	/* check if Battery Voltage is high enough for full
++	 * power operation.
++	 */
++	battery_ready = mx28_is_batt_ready();
++
++	if (!(readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO)) {
++		/* this option allows for fast booting without
++		 * the unecessary delay required for proper
++		 * battery detection when booting from 5v.
++		 */
++
++		/* battery voltage is present and 5v is not connected,
++		 * assume valid battery voltage source is present.  Battery
++		 * brownout protection will take care of supply protection
++		 * if battery becomes invalid in the future
++		 */
++		/*Boot from battery*/
++		mx28_power_setup_batt_boot();
++		mx28_power_clock2pll();
++	} else {
++		/* 5v input detected.  Now we need to determine if a
++		 * valid battery source is present to decide which
++		 * power source to use during bootup.
++		 */
++		int battery_good = mx28_is_batt_good();
++		if(!battery_ready) {
++			if(!battery_good) {
++				struct mx28_lradc_regs *lradc_regs =
++				(struct mx28_lradc_regs *)MXS_LRADC_BASE;
++
++				/* No battery or bad battery detected!!!
++				 * Disabling battery voltage measurements.
++				 */
++				writel(LRADC_CONVERSION_AUTOMATIC,
++					&lradc_regs->hw_lradc_conversion_clr);
++				clrbits_le32(&power_regs->hw_power_battmonitor,
++					POWER_BATTMONITOR_BATT_VAL_MASK);
++			}
++			mx28_5v_boot();
++#if !defined(CONFIG_SYS_VBUS_CURRENT_DRAW)
++			mx28_power_clock2pll();
++#endif
++		} else {
++			/* 5v source detected. Valid battery voltage detected.
++			 * Booting from battery.
++			 */
++			mx28_power_setup_batt_boot();
++			mx28_power_clock2pll();
++		}
++	}
++
++	mx28_init_batt_bo();
++
++#endif /* CONFIG_SYS_NO_DCDC_BATT_SOURCE */
++
+ 	mx28_switch_vddd_to_dcdc_source();
++
++	return battery_ready;
+ }
+ 
+ void mx28_enable_output_rail_protection(void)
+@@ -640,7 +1010,7 @@ int mx28_get_vddio_power_source_off(void
+ 		tmp = readl(&power_regs->hw_power_vddioctrl);
+ 		if (tmp & POWER_VDDIOCTRL_DISABLE_FET) {
+ 			if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
+-				POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
++				POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
+ 				return 1;
+ 			}
+ 		}
+@@ -648,7 +1018,7 @@ int mx28_get_vddio_power_source_off(void
+ 		if (!(readl(&power_regs->hw_power_5vctrl) &
+ 			POWER_5VCTRL_ENABLE_DCDC)) {
+ 			if ((tmp & POWER_VDDIOCTRL_LINREG_OFFSET_MASK) ==
+-				POWER_VDDDCTRL_LINREG_OFFSET_0STEPS) {
++				POWER_VDDIOCTRL_LINREG_OFFSET_0STEPS) {
+ 				return 1;
+ 			}
+ 		}
+@@ -887,12 +1257,14 @@ void mx28_power_init(void)
+ {
+ 	struct mx28_power_regs *power_regs =
+ 		(struct mx28_power_regs *)MXS_POWER_BASE;
++	int is_battery_ready;
+ 
+ 	mx28_power_clock2xtal();
+ 	mx28_power_clear_auto_restart();
+ 	mx28_power_set_linreg();
+ 	mx28_power_setup_5v_detect();
+-	mx28_power_configure_power_source();
++	mx28_power_setup_batt_detect();
++	is_battery_ready = mx28_power_configure_power_source();
+ 	mx28_enable_output_rail_protection();
+ 
+ 	mx28_power_set_vddio(3300, 3150);
+@@ -904,8 +1276,23 @@ void mx28_power_init(void)
+ 		POWER_CTRL_VBUS_VALID_IRQ | POWER_CTRL_BATT_BO_IRQ |
+ 		POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr);
+ 
+-	writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set);
++	if (!is_battery_ready) {
++		writel(POWER_5VCTRL_PWDN_5VBRNOUT,
++			&power_regs->hw_power_5vctrl_set);
++
++#if defined(CONFIG_SYS_NO_DCDC_BATT_SOURCE)
++	/* On i.MX28, a new bit has been added to allow automatic hardware
++	 * shutdown if VDD4P2 browns out.  If we permanently only have a VDD5V
++	 * source, we want to enable this bit.  For devices with dead batteries,
++	 * we could also temporarily set this bit until the kernel battery
++	 * charger sufficiently charges the battery but we won't do this for
++	 * now as the latest release kernel versions aren't aware of  it
++	 * and thus don't handle the proper setting/clearing of this bit.
++	 */
++		writel( 1<<7, &power_regs->hw_power_refctrl_set);
++#endif /* CONFIG_SYS_NO_DCDC_BATT_SOURCE */
+ 
++	}
+ 	early_delay(1000);
+ }
+ 
+--- uboot-custom/arch/arm/include/asm/arch-mx28/imx-regs.h
++++ uboot-custom/arch/arm/include/asm/arch-mx28/imx-regs.h
+@@ -30,6 +30,7 @@
+ #include <asm/arch/regs-digctl.h>
+ #include <asm/arch/regs-gpmi.h>
+ #include <asm/arch/regs-i2c.h>
++#include <asm/arch/regs-lradc.h>
+ #include <asm/arch/regs-ocotp.h>
+ #include <asm/arch/regs-pinctrl.h>
+ #include <asm/arch/regs-power.h>
+--- uboot-custom/arch/arm/include/asm/arch-mx28/regs-lradc.h
++++ uboot-custom/arch/arm/include/asm/arch-mx28/regs-lradc.h
+@@ -0,0 +1,523 @@
++/*
++ * Freescale i.MX28 LRADC Register Definitions
++ *
++ * Copyright (C) 2012 Armadeus Project / ej <eri...@ar...>
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
++ *
++ */
++
++#ifndef __MX28_REGS_LRADC_H__
++#define __MX28_REGS_LRADC_H__
++
++#include <asm/arch/regs-common.h>
++
++#ifndef	__ASSEMBLY__
++struct mx28_lradc_regs {
++	mx28_reg_32(hw_lradc_ctrl0)
++	mx28_reg_32(hw_lradc_ctrl1)
++	mx28_reg_32(hw_lradc_ctrl2)
++	mx28_reg_32(hw_lradc_ctrl3)
++	mx28_reg_32(hw_lradc_status)
++	mx28_reg_32(hw_lradc_ch0)
++	mx28_reg_32(hw_lradc_ch1)
++	mx28_reg_32(hw_lradc_ch2)
++	mx28_reg_32(hw_lradc_ch3)
++	mx28_reg_32(hw_lradc_ch4)
++	mx28_reg_32(hw_lradc_ch5)
++	mx28_reg_32(hw_lradc_ch6)
++	mx28_reg_32(hw_lradc_ch7)
++	mx28_reg_32(hw_lradc_delay0)
++	mx28_reg_32(hw_lradc_delay1)
++	mx28_reg_32(hw_lradc_delay2)
++	mx28_reg_32(hw_lradc_delay3)
++	mx28_reg_32(hw_lradc_debug0)
++	mx28_reg_32(hw_lradc_debug1)
++	mx28_reg_32(hw_lradc_conversion)
++	mx28_reg_32(hw_lradc_ctrl4)
++	mx28_reg_32(hw_lradc_threshold0)
++	mx28_reg_32(hw_lradc_threshold1)
++	mx28_reg_32(hw_lradc_version)
++};
++#endif
++
++#define	LRADC_CTRL0_SFTRST			0x80000000
++#define	LRADC_CTRL0_CLKGATE			0x40000000
++#define	LRADC_CTRL0_ONCHIP_GROUNDREF		0x00200000
++#define	LRADC_CTRL0_TOUCH_DETECT_ENABLE		0x00100000
++#define	LRADC_CTRL0_YMINUS_ENABLE		0x00080000
++#define	LRADC_CTRL0_XMINUS_ENABLE		0x00040000
++#define	LRADC_CTRL0_YPLUS_ENABLE		0x00020000
++#define	LRADC_CTRL0_XPLUS_ENABLE		0x00010000
++#define	LRADC_CTRL0_SCHEDULE_OFFSET		0
++#define	LRADC_CTRL0_SCHEDULE_MASK		0x000000FF
++#define	LRADC_CTRL0_SCHEDULE(v) \
++	(((v) << 0) &	LRADC_CTRL0_SCHEDULE_MASK)
++
++#define	LRADC_CTRL1_TOUCH_DETECT_IRQ_EN_MASK	0x01000000
++#define	LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__DISABLE 0x0
++#define	LRADC_CTRL1_TOUCH_DETECT_IRQ_EN__ENABLE	0x1
++#define	LRADC_CTRL1_LRADC7_IRQ_EN		0x00800000
++#define	LRADC_CTRL1_LRADC7_IRQ_EN__DISABLE	0x0
++#define	LRADC_CTRL1_LRADC7_IRQ_EN__ENABLE	0x1
++#define	LRADC_CTRL1_LRADC6_IRQ_EN		0x00400000
++#define	LRADC_CTRL1_LRADC6_IRQ_EN__DISABLE	0x0
++#define	LRADC_CTRL1_LRADC6_IRQ_EN__ENABLE	0x1
++#define	LRADC_CTRL1_LRADC5_IRQ_EN		0x00200000
++#define	LRADC_CTRL1_LRADC5_IRQ_EN__DISABLE	0x0
++#define	LRADC_CTRL1_LRADC5_IRQ_EN__ENABLE	0x1
++#define	LRADC_CTRL1_LRADC4_IRQ_EN		0x00100000
++#define	LRADC_CTRL1_LRADC4_IRQ_EN__DISABLE	0x0
++#define	LRADC_CTRL1_LRADC4_IRQ_EN__ENABLE	0x1
++#define	LRADC_CTRL1_LRADC3_IRQ_EN		0x00080000
++#define	LRADC_CTRL1_LRADC3_IRQ_EN__DISABLE	0x0
++#define	LRADC_CTRL1_LRADC3_IRQ_EN__ENABLE	0x1
++#define	LRADC_CTRL1_LRADC2_IRQ_EN		0x00040000
++#define	LRADC_CTRL1_LRADC2_IRQ_EN__DISABLE	0x0
++#define	LRADC_CTRL1_LRADC2_IRQ_EN__ENABLE	0x1
++#define	LRADC_CTRL1_LRADC1_IRQ_EN		0x00020000
++#define	LRADC_CTRL1_LRADC1_IRQ_EN__DISABLE	0x0
++#define	LRADC_CTRL1_LRADC1_IRQ_EN__ENABLE	0x1
++#define	LRADC_CTRL1_LRADC0_IRQ_EN		0x00010000
++#define	LRADC_CTRL1_LRADC0_IRQ_EN__DISABLE	0x0
++#define	LRADC_CTRL1_LRADC0_IRQ_EN__ENABLE	0x1
++#define	LRADC_CTRL1_TOUCH_DETECT_IRQ		0x00000100
++#define	LRADC_CTRL1_TOUCH_DETECT_IRQ__CLEAR	0x0
++#define	LRADC_CTRL1_TOUCH_DETECT_IRQ__PENDING	0x1
++#define	LRADC_CTRL1_LRADC7_IRQ			0x00000080
++#define	LRADC_CTRL1_LRADC7_IRQ__CLEAR		0x0
++#define	LRADC_CTRL1_LRADC7_IRQ__PENDING		0x1
++#define	LRADC_CTRL1_LRADC6_IRQ			0x00000040
++#define	LRADC_CTRL1_LRADC6_IRQ__CLEAR		0x0
++#define	LRADC_CTRL1_LRADC6_IRQ__PENDING		0x1
++#define	LRADC_CTRL1_LRADC5_IRQ			0x00000020
++#define	LRADC_CTRL1_LRADC5_IRQ__CLEAR		0x0
++#define	LRADC_CTRL1_LRADC5_IRQ__PENDING		0x1
++#define	LRADC_CTRL1_LRADC4_IRQ			0x00000010
++#define	LRADC_CTRL1_LRADC4_IRQ__CLEAR		0x0
++#define	LRADC_CTRL1_LRADC4_IRQ__PENDING		0x1
++#define	LRADC_CTRL1_LRADC3_IRQ			0x00000008
++#define	LRADC_CTRL1_LRADC3_IRQ__CLEAR		0x0
++#define	LRADC_CTRL1_LRADC3_IRQ__PENDING		0x1
++#define	LRADC_CTRL1_LRADC2_IRQ			0x00000004
++#define	LRADC_CTRL1_LRADC2_IRQ__CLEAR		0x0
++#define	LRADC_CTRL1_LRADC2_IRQ__PENDING		0x1
++#define	LRADC_CTRL1_LRADC1_IRQ			0x00000002
++#define	LRADC_CTRL1_LRADC1_IRQ__CLEAR		0x0
++#define	LRADC_CTRL1_LRADC1_IRQ__PENDING		0x1
++#define	LRADC_CTRL1_LRADC0_IRQ			0x00000001
++#define	LRADC_CTRL1_LRADC0_IRQ__CLEAR		0x0
++#define	LRADC_CTRL1_LRADC0_IRQ__PENDING		0x1
++
++#define	LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET	24
++#define	LRADC_CTRL2_DIVIDE_BY_TWO_MASK		0xFF000000
++#define	LRADC_CTRL2_DIVIDE_BY_TWO(v) \
++	(((v) << 24) &	LRADC_CTRL2_DIVIDE_BY_TWO_MASK)
++#define	LRADC_CTRL2_BL_AMP_BYPASS		0x00800000
++#define	LRADC_CTRL2_BL_AMP_BYPASS__DISABLE	0x0
++#define	LRADC_CTRL2_BL_AMP_BYPASS__ENABLE	0x1
++#define	LRADC_CTRL2_BL_ENABLE			0x00400000
++#define	LRADC_CTRL2_BL_MUX_SELECT		0x00200000
++#define	LRADC_CTRL2_BL_BRIGHTNESS_OFFSET	16
++#define	LRADC_CTRL2_BL_BRIGHTNESS_MASK		0x001F0000
++#define	LRADC_CTRL2_BL_BRIGHTNESS(v) \
++	(((v) << 16) &	LRADC_CTRL2_BL_BRIGHTNESS_MASK)
++#define	LRADC_CTRL2_TEMPSENSE_PWD		0x00008000
++#define	LRADC_CTRL2_TEMPSENSE_PWD__ENABLE	0x0
++#define	LRADC_CTRL2_TEMPSENSE_PWD__DISABLE	0x1
++#define	LRADC_CTRL2_EXT_EN1			0x00002000
++#define	LRADC_CTRL2_EXT_EN1__DISABLE		0x0
++#define	LRADC_CTRL2_EXT_EN1__ENABLE		0x1
++#define	LRADC_CTRL2_EXT_EN0			0x00001000
++#define	LRADC_CTRL2_TEMP_SENSOR_IENABLE1	0x00000200
++#define	LRADC_CTRL2_TEMP_SENSOR_IENABLE1__DISABLE 0x0
++#define	LRADC_CTRL2_TEMP_SENSOR_IENABLE1__ENABLE 0x1
++#define	LRADC_CTRL2_TEMP_SENSOR_IENABLE0	0x00000100
++#define	LRADC_CTRL2_TEMP_SENSOR_IENABLE0__DISABLE 0x0
++#define	LRADC_CTRL2_TEMP_SENSOR_IENABLE0__ENABLE 0x1
++#define	LRADC_CTRL2_TEMP_ISRC1_OFFSET		4
++#define	LRADC_CTRL2_TEMP_ISRC1_MASK		0x000000F0
++#define	LRADC_CTRL2_TEMP_ISRC1(v) \
++	(((v) << 4) &	LRADC_CTRL2_TEMP_ISRC1_MASK)
++#define	LRADC_CTRL2_TEMP_ISRC1__300		0xF
++#define	LRADC_CTRL2_TEMP_ISRC1__280		0xE
++#define	LRADC_CTRL2_TEMP_ISRC1__260		0xD
++#define	LRADC_CTRL2_TEMP_ISRC1__240		0xC
++#define	LRADC_CTRL2_TEMP_ISRC1__220		0xB
++#define	LRADC_CTRL2_TEMP_ISRC1__200		0xA
++#define	LRADC_CTRL2_TEMP_ISRC1__180		0x9
++#define	LRADC_CTRL2_TEMP_ISRC1__160		0x8
++#define	LRADC_CTRL2_TEMP_ISRC1__140		0x7
++#define	LRADC_CTRL2_TEMP_ISRC1__120		0x6
++#define	LRADC_CTRL2_TEMP_ISRC1__100		0x5
++#define	LRADC_CTRL2_TEMP_ISRC1__80		0x4
++#define	LRADC_CTRL2_TEMP_ISRC1__60		0x3
++#define	LRADC_CTRL2_TEMP_ISRC1__40		0x2
++#define	LRADC_CTRL2_TEMP_ISRC1__20		0x1
++#define	LRADC_CTRL2_TEMP_ISRC1__ZERO		0x0
++#define	LRADC_CTRL2_TEMP_ISRC0_OFFSET		0
++#define	LRADC_CTRL2_TEMP_ISRC0_MASK		0x0000000F
++#define	LRADC_CTRL2_TEMP_ISRC0(v) \
++	(((v) << 0) &	LRADC_CTRL2_TEMP_ISRC0_MASK)
++#define	LRADC_CTRL2_TEMP_ISRC0__300		0xF
++#define	LRADC_CTRL2_TEMP_ISRC0__280		0xE
++#define	LRADC_CTRL2_TEMP_ISRC0__260		0xD
++#define	LRADC_CTRL2_TEMP_ISRC0__240		0xC
++#define	LRADC_CTRL2_TEMP_ISRC0__220		0xB
++#define	LRADC_CTRL2_TEMP_ISRC0__200		0xA
++#define	LRADC_CTRL2_TEMP_ISRC0__180		0x9
++#define	LRADC_CTRL2_TEMP_ISRC0__160		0x8
++#define	LRADC_CTRL2_TEMP_ISRC0__140		0x7
++#define	LRADC_CTRL2_TEMP_ISRC0__120		0x6
++#define	LRADC_CTRL2_TEMP_ISRC0__100		0x5
++#define	LRADC_CTRL2_TEMP_ISRC0__80		0x4
++#define	LRADC_CTRL2_TEMP_ISRC0__60		0x3
++#define	LRADC_CTRL2_TEMP_ISRC0__40		0x2
++#define	LRADC_CTRL2_TEMP_ISRC0__20		0x1
++#define	LRADC_CTRL2_TEMP_ISRC0__ZERO		0x0
++
++#define	LRADC_CTRL3_DISCARD_OFFSET		24
++#define	LRADC_CTRL3_DISCARD_MASK		0x03000000
++#define	LRADC_CTRL3_DISCARD(v) \
++	(((v) << 24) &	LRADC_CTRL3_DISCARD_MASK)
++#define	LRADC_CTRL3_DISCARD__1_SAMPLE		0x1
++#define	LRADC_CTRL3_DISCARD__2_SAMPLES		0x2
++#define	LRADC_CTRL3_DISCARD__3_SAMPLES		0x3
++#define	LRADC_CTRL3_FORCE_ANALOG_PWUP		0x00800000
++#define	LRADC_CTRL3_FORCE_ANALOG_PWUP__OFF	0x0
++#define	LRADC_CTRL3_FORCE_ANALOG_PWUP__ON	0x1
++#define	LRADC_CTRL3_FORCE_ANALOG_PWDN		0x00400000
++#define	LRADC_CTRL3_FORCE_ANALOG_PWDN__ON	0x0
++#define	LRADC_CTRL3_FORCE_ANALOG_PWDN__OFF	0x1
++#define	LRADC_CTRL3_CYCLE_TIME_OFFSET		8
++#define	LRADC_CTRL3_CYCLE_TIME_MASK		0x00000300
++#define	LRADC_CTRL3_CYCLE_TIME(v) \
++	(((v) << 8) &	LRADC_CTRL3_CYCLE_TIME_MASK)
++#define	LRADC_CTRL3_CYCLE_TIME__6MHZ		0x0
++#define	LRADC_CTRL3_CYCLE_TIME__4MHZ		0x1
++#define	LRADC_CTRL3_CYCLE_TIME__3MHZ		0x2
++#define	LRADC_CTRL3_CYCLE_TIME__2MHZ		0x3
++#define	LRADC_CTRL3_HIGH_TIME_OFFSET		4
++#define	LRADC_CTRL3_HIGH_TIME_MASK		0x00000030
++#define	LRADC_CTRL3_HIGH_TIME(v) \
++	(((v) << 4) &	LRADC_CTRL3_HIGH_TIME_MASK)
++#define	LRADC_CTRL3_HIGH_TIME__42NS		0x0
++#define	LRADC_CTRL3_HIGH_TIME__83NS		0x1
++#define	LRADC_CTRL3_HIGH_TIME__125NS		0x2
++#define	LRADC_CTRL3_HIGH_TIME__250NS		0x3
++#define	LRADC_CTRL3_DELAY_CLOCK			0x00000002
++#define	LRADC_CTRL3_DELAY_CLOCK__NORMAL		0x0
++#define	LRADC_CTRL3_DELAY_CLOCK__DELAYED	0x1
++#define	LRADC_CTRL3_INVERT_CLOCK		0x00000001
++#define	LRADC_CTRL3_INVERT_CLOCK__NORMAL	0x0
++#define	LRADC_CTRL3_INVERT_CLOCK__INVERT	0x1
++
++#define	LRADC_STATUS_TEMP1_PRESENT		0x04000000
++#define	LRADC_STATUS_TEMP0_PRESENT		0x02000000
++#define	LRADC_STATUS_TOUCH_PANEL_PRESENT	0x01000000
++#define	LRADC_STATUS_CHANNEL7_PRESENT		0x00800000
++#define	LRADC_STATUS_CHANNEL6_PRESENT		0x00400000
++#define	LRADC_STATUS_CHANNEL5_PRESENT		0x00200000
++#define	LRADC_STATUS_CHANNEL4_PRESENT		0x00100000
++#define	LRADC_STATUS_CHANNEL3_PRESENT		0x00080000
++#define	LRADC_STATUS_CHANNEL2_PRESENT		0x00040000
++#define	LRADC_STATUS_CHANNEL1_PRESENT		0x00020000
++#define	LRADC_STATUS_CHANNEL0_PRESENT		0x00010000
++#define	LRADC_STATUS_TOUCH_DETECT_RAW		0x00000001
++#define	LRADC_STATUS_TOUCH_DETECT_RAW__OPEN	0x0
++#define	LRADC_STATUS_TOUCH_DETECT_RAW__HIT	0x1
++
++/*
++ * multi-register-define name HW_LRADC_CHn
++ * base 0x00000050
++ * count 6
++ * offset 0x10
++ */
++#define	LRADC_CHn_TOGGLE			0x80000000
++#define	LRADC_CHn_ACCUMULATE			0x20000000
++#define	LRADC_CHn_NUM_SAMPLES_OFFSET		24
++#define	LRADC_CHn_NUM_SAMPLES_MASK		0x1F000000
++#define	LRADC_CHn_NUM_SAMPLES(v) \
++	(((v) << 24) &	LRADC_CHn_NUM_SAMPLES_MASK)
++#define	LRADC_CHn_VALUE_OFFSET			0
++#define	LRADC_CHn_VALUE_MASK			0x0003FFFF
++#define	LRADC_CHn_VALUE(v) \
++	(((v) << 0) &	LRADC_CHn_VALUE_MASK)
++
++#define	LRADC_CH6_TOGGLE			0x80000000
++#define	LRADC_CH6_ACCUMULATE			0x20000000
++#define	LRADC_CH6_NUM_SAMPLES_OFFSET		24
++#define	LRADC_CH6_NUM_SAMPLES_MASK		0x1F000000
++#define	LRADC_CH6_NUM_SAMPLES(v) \
++	(((v) << 24) &	LRADC_CH6_NUM_SAMPLES_MASK)
++#define	LRADC_CH6_VALUE_OFFSET			0
++#define	LRADC_CH6_VALUE_MASK			0x0003FFFF
++#define	LRADC_CH6_VALUE(v) \
++	(((v) << 0) &	LRADC_CH6_VALUE_MASK)
++
++#define	LRADC_CH7_TOGGLE			0x80000000
++#define	LRADC_CH7_TESTMODE_TOGGLE		0x40000000
++#define	LRADC_CH7_ACCUMULATE			0x20000000
++#define	LRADC_CH7_NUM_SAMPLES_OFFSET		24
++#define	LRADC_CH7_NUM_SAMPLES_MASK		0x1F000000
++#define	LRADC_CH7_NUM_SAMPLES(v) \
++	(((v) << 24) &	LRADC_CH7_NUM_SAMPLES_MASK)
++#define	LRADC_CH7_VALUE_OFFSET			0
++#define	LRADC_CH7_VALUE_MASK			0x0003FFFF
++#define	LRADC_CH7_VALUE(v) \
++	(((v) << 0) &	LRADC_CH7_VALUE_MASK)
++
++/*
++ * multi-register-define name HW_LRADC_DELAYn
++ * base 0x000000D0
++ * count 4
++ * offset 0x10
++ */
++#define	LRADC_DELAYn_TRIGGER_LRADCS_OFFSET	24
++#define	LRADC_DELAYn_TRIGGER_LRADCS_MASK	0xFF000000
++#define	LRADC_DELAYn_TRIGGER_LRADCS(v) \
++	(((v) << 24) &	LRADC_DELAYn_TRIGGER_LRADCS_MASK)
++#define	LRADC_DELAYn_KICK			0x00100000
++#define	LRADC_DELAYn_TRIGGER_DELAYS_OFFSET	16
++#define	LRADC_DELAYn_TRIGGER_DELAYS_MASK	0x000F0000
++#define	LRADC_DELAYn_TRIGGER_DELAYS(v) \
++	(((v) << 16) &	LRADC_DELAYn_TRIGGER_DELAYS_MASK)
++#define	LRADC_DELAYn_LOOP_COUNT_OFFSET		11
++#define	LRADC_DELAYn_LOOP_COUNT_MASK		0x0000F800
++#define	LRADC_DELAYn_LOOP_COUNT(v) \
++	(((v) << 11) &	LRADC_DELAYn_LOOP_COUNT_MASK)
++#define	LRADC_DELAYn_DELAY_OFFSET		0
++#define	LRADC_DELAYn_DELAY_MASK			0x000007FF
++#define	LRADC_DELAYn_DELAY(v) \
++	(((v) << 0) &	LRADC_DELAYn_DELAY_MASK)
++
++#define	LRADC_DEBUG0_READONLY_OFFSET		16
++#define	LRADC_DEBUG0_READONLY_MASK		0xFFFF0000
++#define	LRADC_DEBUG0_READONLY(v) \
++	(((v) << 16) &	LRADC_DEBUG0_READONLY_MASK)
++#define	LRADC_DEBUG0_STATE_OFFSET		0
++#define	LRADC_DEBUG0_STATE_MASK			0x00000FFF
++#define	LRADC_DEBUG0_STATE(v) \
++	(((v) << 0) &	LRADC_DEBUG0_STATE_MASK)
++
++#define	LRADC_DEBUG1_REQUEST_OFFSET		16
++#define	LRADC_DEBUG1_REQUEST_MASK		0x00FF0000
++#define	LRADC_DEBUG1_REQUEST(v) \
++	(((v) << 16) &	LRADC_DEBUG1_REQUEST_MASK)
++#define	LRADC_DEBUG1_TESTMODE_COUNT_OFFSET	8
++#define	LRADC_DEBUG1_TESTMODE_COUNT_MASK	0x00001F00
++#define	LRADC_DEBUG1_TESTMODE_COUNT(v) \
++	(((v) << 8) &	LRADC_DEBUG1_TESTMODE_COUNT_MASK)
++#define	LRADC_DEBUG1_TESTMODE6			0x00000004
++#define	LRADC_DEBUG1_TESTMODE6__NORMAL		0x0
++#define	LRADC_DEBUG1_TESTMODE6__TEST		0x1
++#define	LRADC_DEBUG1_TESTMODE5			0x00000002
++#define	LRADC_DEBUG1_TESTMODE5__NORMAL		0x0
++#define	LRADC_DEBUG1_TESTMODE5__TEST		0x1
++#define	LRADC_DEBUG1_TESTMODE			0x00000001
++#define	LRADC_DEBUG1_TESTMODE__NORMAL		0x0
++#define	LRADC_DEBUG1_TESTMODE__TEST		0x1
++
++#define	LRADC_CONVERSION_AUTOMATIC		0x00100000
++#define	LRADC_CONVERSION_AUTOMATIC__DISABLE	0x0
++#define	LRADC_CONVERSION_AUTOMATIC__ENABLE	0x1
++#define	LRADC_CONVERSION_SCALE_FACTOR_OFFSET	16
++#define	LRADC_CONVERSION_SCALE_FACTOR_MASK	0x00030000
++#define	LRADC_CONVERSION_SCALE_FACTOR(v) \
++	(((v) << 16) &	LRADC_CONVERSION_SCALE_FACTOR_MASK)
++#define	LRADC_CONVERSION_SCALE_FACTOR__NIMH	0x0
++#define	LRADC_CONVERSION_SCALE_FACTOR__DUAL_NIMH 0x1
++#define	LRADC_CONVERSION_SCALE_FACTOR__LI_ION	0x2
++#define	LRADC_CONVERSION_SCALE_FACTOR__ALT_LI_ION 0x3
++#define	LRADC_CONVERSION_SCALED_BATT_VOLTAGE_OFFSET 0
++#define	LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK 0x000003FF
++#define	LRADC_CONVERSION_SCALED_BATT_VOLTAGE(v) \
++	(((v) << 0) &	LRADC_CONVERSION_SCALED_BATT_VOLTAGE_MASK)
++
++#define	LRADC_CTRL4_LRADC7SELECT_OFFSET		28
++#define	LRADC_CTRL4_LRADC7SELECT_MASK		0xF0000000
++#define	LRADC_CTRL4_LRADC7SELECT(v) \
++	(((v) << 28) &	LRADC_CTRL4_LRADC7SELECT_MASK)
++#define	LRADC_CTRL4_LRADC7SELECT__CHANNEL0	0x0
++#define	LRADC_CTRL4_LRADC7SELECT__CHANNEL1	0x1
++#define	LRADC_CTRL4_LRADC7SELECT__CHANNEL2	0x2
++#define	LRADC_CTRL4_LRADC7SELECT__CHANNEL3	0x3
++#define	LRADC_CTRL4_LRADC7SELECT__CHANNEL4	0x4
++#define	LRADC_CTRL4_LRADC7SELECT__CHANNEL5	0x5
++#define	LRADC_CTRL4_LRADC7SELECT__CHANNEL6	0x6
++#define	LRADC_CTRL4_LRADC7SELECT__CHANNEL7	0x7
++#define	LRADC_CTRL4_LRADC7SELECT__CHANNEL8	0x8
++#define	LRADC_CTRL4_LRADC7SELECT__CHANNEL9	0x9
++#define	LRADC_CTRL4_LRADC7SELECT__CHANNEL10	0xA
++#define	LRADC_CTRL4_LRADC7SELECT__CHANNEL11	0xB
++#define	LRADC_CTRL4_LRADC7SELECT__CHANNEL12	0xC
++#define	LRADC_CTRL4_LRADC7SELECT__CHANNEL13	0xD
++#define	LRADC_CTRL4_LRADC7SELECT__CHANNEL14	0xE
++#define	LRADC_CTRL4_LRADC7SELECT__CHANNEL15	0xF
++#define	LRADC_CTRL4_LRADC6SELECT_OFFSET		24
++#define	LRADC_CTRL4_LRADC6SELECT_MASK		0x0F000000
++#define	LRADC_CTRL4_LRADC6SELECT(v) \
++	(((v) << 24) &	LRADC_CTRL4_LRADC6SELECT_MASK)
++#define	LRADC_CTRL4_LRADC6SELECT__CHANNEL0	0x0
++#define	LRADC_CTRL4_LRADC6SELECT__CHANNEL1	0x1
++#define	LRADC_CTRL4_LRADC6SELECT__CHANNEL2	0x2
++#define	LRADC_CTRL4_LRADC6SELECT__CHANNEL3	0x3
++#define	LRADC_CTRL4_LRADC6SELECT__CHANNEL4	0x4
++#define	LRADC_CTRL4_LRADC6SELECT__CHANNEL5	0x5
++#define	LRADC_CTRL4_LRADC6SELECT__CHANNEL6	0x6
++#define	LRADC_CTRL4_LRADC6SELECT__CHANNEL7	0x7
++#define	LRADC_CTRL4_LRADC6SELECT__CHANNEL8	0x8
++#define	LRADC_CTRL4_LRADC6SELECT__CHANNEL9	0x9
++#define	LRADC_CTRL4_LRADC6SELECT__CHANNEL10	0xA
++#define	LRADC_CTRL4_LRADC6SELECT__CHANNEL11	0xB
++#define	LRADC_CTRL4_LRADC6SELECT__CHANNEL12	0xC
++#define	LRADC_CTRL4_LRADC6SELECT__CHANNEL13	0xD
++#define	LRADC_CTRL4_LRADC6SELECT__CHANNEL14	0xE
++#define	LRADC_CTRL4_LRADC6SELECT__CHANNEL15	0xF
++#define	LRADC_CTRL4_LRADC5SELECT_OFFSET		20
++#define	LRADC_CTRL4_LRADC5SELECT_MASK		0x00F00000
++#define	LRADC_CTRL4_LRADC5SELECT(v) \
++	(((v) << 20) &	LRADC_CTRL4_LRADC5SELECT_MASK)
++#define	LRADC_CTRL4_LRADC5SELECT__CHANNEL0	0x0
++#define	LRADC_CTRL4_LRADC5SELECT__CHANNEL1	0x1
++#define	LRADC_CTRL4_LRADC5SELECT__CHANNEL2	0x2
++#define	LRADC_CTRL4_LRADC5SELECT__CHANNEL3	0x3
++#define	LRADC_CTRL4_LRADC5SELECT__CHANNEL4	0x4
++#define	LRADC_CTRL4_LRADC5SELECT__CHANNEL5	0x5
++#define	LRADC_CTRL4_LRADC5SELECT__CHANNEL6	0x6
++#define	LRADC_CTRL4_LRADC5SELECT__CHANNEL7	0x7
++#define	LRADC_CTRL4_LRADC5SELECT__CHANNEL8	0x8
++#define	LRADC_CTRL4_LRADC5SELECT__CHANNEL9	0x9
++#define	LRADC_CTRL4_LRADC5SELECT__CHANNEL10	0xA
++#define	LRADC_CTRL4_LRADC5SELECT__CHANNEL11	0xB
++#define	LRADC_CTRL4_LRADC5SELECT__CHANNEL12	0xC
++#define	LRADC_CTRL4_LRADC5SELECT__CHANNEL13	0xD
++#define	LRADC_CTRL4_LRADC5SELECT__CHANNEL14	0xE
++#define	LRADC_CTRL4_LRADC5SELECT__CHANNEL15	0xF
++#define	LRADC_CTRL4_LRADC4SELECT_OFFSET		16
++#define	LRADC_CTRL4_LRADC4SELECT_MASK		0x000F0000
++#define	LRADC_CTRL4_LRADC4SELECT(v) \
++	(((v) << 16) &	LRADC_CTRL4_LRADC4SELECT_MASK)
++#define	LRADC_CTRL4_LRADC4SELECT__CHANNEL0	0x0
++#define	LRADC_CTRL4_LRADC4SELECT__CHANNEL1	0x1
++#define	LRADC_CTRL4_LRADC4SELECT__CHANNEL2	0x2
++#define	LRADC_CTRL4_LRADC4SELECT__CHANNEL3	0x3
++#define	LRADC_CTRL4_LRADC4SELECT__CHANNEL4	0x4
++#define	LRADC_CTRL4_LRADC4SELECT__CHANNEL5	0x5
++#define	LRADC_CTRL4_LRADC4SELECT__CHANNEL6	0x6
++#define	LRADC_CTRL4_LRADC4SELECT__CHANNEL7	0x7
++#define	LRADC_CTRL4_LRADC4SELECT__CHANNEL8	0x8
++#define	LRADC_CTRL4_LRADC4SELECT__CHANNEL9	0x9
++#define	LRADC_CTRL4_LRADC4SELECT__CHANNEL10	0xA
++#define	LRADC_CTRL4_LRADC4SELECT__CHANNEL11	0xB
++#define	LRADC_CTRL4_LRADC4SELECT__CHANNEL12	0xC
++#define	LRADC_CTRL4_LRADC4SELECT__CHANNEL13	0xD
++#define	LRADC_CTRL4_LRADC4SELECT__CHANNEL14	0xE
++#define	LRADC_CTRL4_LRADC4SELECT__CHANNEL15	0xF
++#define	LRADC_CTRL4_LRADC3SELECT_OFFSET		12
++#define	LRADC_CTRL4_LRADC3SELECT_MASK		0x0000F000
++#define	LRADC_CTRL4_LRADC3SELECT(v) \
++	(((v) << 12) &	LRADC_CTRL4_LRADC3SELECT_MASK)
++#define	LRADC_CTRL4_LRADC3SELECT__CHANNEL0	0x0
++#define	LRADC_CTRL4_LRADC3SELECT__CHANNEL1	0x1
++#define	LRADC_CTRL4_LRADC3SELECT__CHANNEL2	0x2
++#define	LRADC_CTRL4_LRADC3SELECT__CHANNEL3	0x3
++#define	LRADC_CTRL4_LRADC3SELECT__CHANNEL4	0x4
++#define	LRADC_CTRL4_LRADC3SELECT__CHANNEL5	0x5
++#define	LRADC_CTRL4_LRADC3SELECT__CHANNEL6	0x6
++#define	LRADC_CTRL4_LRADC3SELECT__CHANNEL7	0x7
++#define	LRADC_CTRL4_LRADC3SELECT__CHANNEL8	0x8
++#define	LRADC_CTRL4_LRADC3SELECT__CHANNEL9	0x9
++#define	LRADC_CTRL4_LRADC3SELECT__CHANNEL10	0xA
++#define	LRADC_CTRL4_LRADC3SELECT__CHANNEL11	0xB
++#define	LRADC_CTRL4_LRADC3SELECT__CHANNEL12	0xC
++#define	LRADC_CTRL4_LRADC3SELECT__CHANNEL13	0xD
++#define	LRADC_CTRL4_LRADC3SELECT__CHANNEL14	0xE
++#define	LRADC_CTRL4_LRADC3SELECT__CHANNEL15	0xF
++#define	LRADC_CTRL4_LRADC2SELECT_OFFSET		8
++#define	LRADC_CTRL4_LRADC2SELECT_MASK		0x00000F00
++#define	LRADC_CTRL4_LRADC2SELECT(v) \
++	(((v) << 8) &	LRADC_CTRL4_LRADC2SELECT_MASK)
++#define	LRADC_CTRL4_LRADC2SELECT__CHANNEL0	0x0
++#define	LRADC_CTRL4_LRADC2SELECT__CHANNEL1	0x1
++#define	LRADC_CTRL4_LRADC2SELECT__CHANNEL2	0x2
++#define	LRADC_CTRL4_LRADC2SELECT__CHANNEL3	0x3
++#define	LRADC_CTRL4_LRADC2SELECT__CHANNEL4	0x4
++#define	LRADC_CTRL4_LRADC2SELECT__CHANNEL5	0x5
++#define	LRADC_CTRL4_LRADC2SELECT__CHANNEL6	0x6
++#define	LRADC_CTRL4_LRADC2SELECT__CHANNEL7	0x7
++#define	LRADC_CTRL4_LRADC2SELECT__CHANNEL8	0x8
++#define	LRADC_CTRL4_LRADC2SELECT__CHANNEL9	0x9
++#define	LRADC_CTRL4_LRADC2SELECT__CHANNEL10	0xA
++#define	LRADC_CTRL4_LRADC2SELECT__CHANNEL11	0xB
++#define	LRADC_CTRL4_LRADC2SELECT__CHANNEL12	0xC
++#define	LRADC_CTRL4_LRADC2SELECT__CHANNEL13	0xD
++#define	LRADC_CTRL4_LRADC2SELECT__CHANNEL14	0xE
++#define	LRADC_CTRL4_LRADC2SELECT__CHANNEL15	0xF
++#define	LRADC_CTRL4_LRADC1SELECT_OFFSET		4
++#define	LRADC_CTRL4_LRADC1SELECT_MASK		0x000000F0
++#define	LRADC_CTRL4_LRADC1SELECT(v) \
++	(((v) << 4) &	LRADC_CTRL4_LRADC1SELECT_MASK)
++#define	LRADC_CTRL4_LRADC1SELECT__CHANNEL0	0x0
++#define	LRADC_CTRL4_LRADC1SELECT__CHANNEL1	0x1
++#define	LRADC_CTRL4_LRADC1SELECT__CHANNEL2	0x2
++#define	LRADC_CTRL4_LRADC1SELECT__CHANNEL3	0x3
++#define	LRADC_CTRL4_LRADC1SELECT__CHANNEL4	0x4
++#define	LRADC_CTRL4_LRADC1SELECT__CHANNEL5	0x5
++#define	LRADC_CTRL4_LRADC1SELECT__CHANNEL6	0x6
++#define	LRADC_CTRL4_LRADC1SELECT__CHANNEL7	0x7
++#define	LRADC_CTRL4_LRADC1SELECT__CHANNEL8	0x8
++#define	LRADC_CTRL4_LRADC1SELECT__CHANNEL9	0x9
++#define	LRADC_CTRL4_LRADC1SELECT__CHANNEL10	0xA
++#define	LRADC_CTRL4_LRADC1SELECT__CHANNEL11	0xB
++#define	LRADC_CTRL4_LRADC1SELECT__CHANNEL12	0xC
++#define	LRADC_CTRL4_LRADC1SELECT__CHANNEL13	0xD
++#define	LRADC_CTRL4_LRADC1SELECT__CHANNEL14	0xE
++#define	LRADC_CTRL4_LRADC1SELECT__CHANNEL15	0xF
++#define	LRADC_CTRL4_LRADC0SELECT_OFFSET		0
++#define	LRADC_CTRL4_LRADC0SELECT_MASK		0x0000000F
++#define	LRADC_CTRL4_LRADC0SELECT(v) \
++	(((v) << 0) &	LRADC_CTRL4_LRADC0SELECT_MASK)
++#define	LRADC_CTRL4_LRADC0SELECT__CHANNEL0	0x0
++#define	LRADC_CTRL4_LRADC0SELECT__CHANNEL1	0x1
++#define	LRADC_CTRL4_LRADC0SELECT__CHANNEL2	0x2
++#define	LRADC_CTRL4_LRADC0SELECT__CHANNEL3	0x3
++#define	LRADC_CTRL4_LRADC0SELECT__CHANNEL4	0x4
++#define	LRADC_CTRL4_LRADC0SELECT__CHANNEL5	0x5
++#define	LRADC_CTRL4_LRADC0SELECT__CHANNEL6	0x6
++#define	LRADC_CTRL4_LRADC0SELECT__CHANNEL7	0x7
++#define	LRADC_CTRL4_LRADC0SELECT__CHANNEL8	0x8
++#define	LRADC_CTRL4_LRADC0SELECT__CHANNEL9	0x9
++#define	LRADC_CTRL4_LRADC0SELECT__CHANNEL10	0xA
++#define	LRADC_CTRL4_LRADC0SELECT__CHANNEL11	0xB
++#define	LRADC_CTRL4_LRADC0SELECT__CHANNEL12	0xC
++#define	LRADC_CTRL4_LRADC0SELECT__CHANNEL13	0xD
++#define	LRADC_CTRL4_LRADC0SELECT__CHANNEL14	0xE
++#define	LRADC_CTRL4_LRADC0SELECT__CHANNEL15	0xF
++
++#define	LRADC_VERSION_MAJOR_OFFSET		24
++#define	LRADC_VERSION_MAJOR_MASK		0xFF000000
++#define	LRADC_VERSION_MAJOR(v) \
++	(((v) << 24) &	LRADC_VERSION_MAJOR_MASK)
++#define	LRADC_VERSION_MINOR_OFFSET		16
++#define	LRADC_VERSION_MINOR_MASK		0x00FF0000
++#define	LRADC_VERSION_MINOR(v) \
++	(((v) << 16) &	LRADC_VERSION_MINOR_MASK)
++#define	LRADC_VERSION_STEP_OFFSET		0
++#define	LRADC_VERSION_STEP_MASK			0x0000FFFF
++#define	LRADC_VERSION_STEP(v) \
++	(((v) << 0) ...
 
[truncated message content]

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-324-gfca486f

From: jorasse <jo...@us...> - 2012-05-24 22:28:23

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  fca486ff69b21ad09f4bfa754da289da03cdb444 (commit)
      from  fc8e6ec67b11887a524097e29c50b90460fe25f4 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit fca486ff69b21ad09f4bfa754da289da03cdb444
Author: Eric Jarrige <eri...@ar...>
Date:   Fri May 25 00:28:08 2012 +0200

    [UBOOT] (Preliminary) Update U-Boot patch to U-Boot 2012.04 - Thx Trem

-----------------------------------------------------------------------

Summary of changes:
 patches/u-boot/2012.04/101-mx1-gpio-mode.patch     |   31 +
 patches/u-boot/2012.04/102-mx1-i2c.patch           |   46 +
 patches/u-boot/2012.04/103-apf9328.patch           | 1359 +++++++++++++++
 patches/u-boot/2012.04/104-apf9328-makefile.patch  |   41 +
 patches/u-boot/2012.04/106-mx1-pllclk.patch        |   63 +
 patches/u-boot/2012.04/107-mx1-pllclk-debug.patch  |   26 +
 patches/u-boot/2012.04/108-DM9000.patch            |   48 +
 patches/u-boot/2012.04/109-mx1-relocation.patch    |   33 +
 patches/u-boot/2012.04/111-mx1-timer.patch         |   25 +
 ...dule-and-I-O-Multiplexer-constant-for-mx2.patch |  156 ++
 ...-Add-support-for-the-armadeus-apf27-board.patch | 1766 ++++++++++++++++++++
 .../u-boot/2012.04/311-imx-nand-lock-unlock.patch  |   93 +
 patches/u-boot/2012.04/320-spartan.patch           |   45 +
 patches/u-boot/2012.04/321-add_spartan6.patch      |  761 +++++++++
 patches/u-boot/2012.04/330-arm926-relocation.patch |   32 +
 .../u-boot/2012.04/340-apf27-misc-commands.patch   |  379 +++++
 .../2012.04/350-nand_large_file_download.patch     |  235 +++
 patches/u-boot/2012.04/400-imx51.patch             |  510 ++++++
 patches/u-boot/2012.04/401-apf51.patch             | 1624 ++++++++++++++++++
 patches/u-boot/2012.04/403-apf51-wdog.patch        |   29 +
 .../u-boot/2012.04/405-remove_extra_printk.patch   |   36 +
 patches/u-boot/2012.04/407-imx51-nand.patch        | 1390 +++++++++++++++
 patches/u-boot/2012.04/409-apf51-nand-spl.patch    |  407 +++++
 patches/u-boot/2012.04/410-imx-iim.patch           |  547 ++++++
 .../2012.04/411-Fix-high-voltage-nand-sd.patch     |   24 +
 ...c_i2c-add_support_for_the_iMX51_processor.patch |   26 +
 patches/u-boot/2012.04/425-cortex-relocation.patch |   32 +
 .../u-boot/2012.04/501-imx28-update-and-fix.patch  |   80 +
 patches/u-boot/2012.04/502-add-apf28.patch         | 1407 ++++++++++++++++
 .../503-imx28-fix_spl_power_init_IRQ_bit.patch     |   38 +
 30 files changed, 11289 insertions(+), 0 deletions(-)
 create mode 100644 patches/u-boot/2012.04/101-mx1-gpio-mode.patch
 create mode 100644 patches/u-boot/2012.04/102-mx1-i2c.patch
 create mode 100644 patches/u-boot/2012.04/103-apf9328.patch
 create mode 100644 patches/u-boot/2012.04/104-apf9328-makefile.patch
 create mode 100644 patches/u-boot/2012.04/106-mx1-pllclk.patch
 create mode 100644 patches/u-boot/2012.04/107-mx1-pllclk-debug.patch
 create mode 100644 patches/u-boot/2012.04/108-DM9000.patch
 create mode 100644 patches/u-boot/2012.04/109-mx1-relocation.patch
 create mode 100644 patches/u-boot/2012.04/111-mx1-timer.patch
 create mode 100644 patches/u-boot/2012.04/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
 create mode 100644 patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch
 create mode 100644 patches/u-boot/2012.04/311-imx-nand-lock-unlock.patch
 create mode 100644 patches/u-boot/2012.04/320-spartan.patch
 create mode 100644 patches/u-boot/2012.04/321-add_spartan6.patch
 create mode 100644 patches/u-boot/2012.04/330-arm926-relocation.patch
 create mode 100644 patches/u-boot/2012.04/340-apf27-misc-commands.patch
 create mode 100644 patches/u-boot/2012.04/350-nand_large_file_download.patch
 create mode 100644 patches/u-boot/2012.04/400-imx51.patch
 create mode 100644 patches/u-boot/2012.04/401-apf51.patch
 create mode 100644 patches/u-boot/2012.04/403-apf51-wdog.patch
 create mode 100644 patches/u-boot/2012.04/405-remove_extra_printk.patch
 create mode 100644 patches/u-boot/2012.04/407-imx51-nand.patch
 create mode 100644 patches/u-boot/2012.04/409-apf51-nand-spl.patch
 create mode 100644 patches/u-boot/2012.04/410-imx-iim.patch
 create mode 100644 patches/u-boot/2012.04/411-Fix-high-voltage-nand-sd.patch
 create mode 100644 patches/u-boot/2012.04/424-armadeus-mxc_i2c-add_support_for_the_iMX51_processor.patch
 create mode 100644 patches/u-boot/2012.04/425-cortex-relocation.patch
 create mode 100644 patches/u-boot/2012.04/501-imx28-update-and-fix.patch
 create mode 100644 patches/u-boot/2012.04/502-add-apf28.patch
 create mode 100644 patches/u-boot/2012.04/503-imx28-fix_spl_power_init_IRQ_bit.patch

diff --git a/patches/u-boot/2012.04/101-mx1-gpio-mode.patch b/patches/u-boot/2012.04/101-mx1-gpio-mode.patch
new file mode 100644
index 0000000..29af133
--- /dev/null
+++ b/patches/u-boot/2012.04/101-mx1-gpio-mode.patch
@@ -0,0 +1,31 @@
+mx1: export imx_gpio_mode() function
+
+Add imx_gpio_mode() to Freescale imx1/L/S public functions
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Stefano Babic <sb...@de...>
+---
+ arch/arm/include/asm/arch-imx/imx-regs.h |    7 +++++++
+ 1 files changed, 7 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch-imx/imx-regs.h b/arch/arm/include/asm/arch-imx/imx-regs.h
+index ec94ba9..0c26a36 100644
+--- a/arch/arm/include/asm/arch-imx/imx-regs.h
++++ b/arch/arm/include/asm/arch-imx/imx-regs.h
+@@ -1,5 +1,12 @@
+ #ifndef _IMX_REGS_H
+ #define _IMX_REGS_H
++
++#ifndef __ASSEMBLY__
++
++extern void imx_gpio_mode(int gpio_mode);
++
++#endif /* __ASSEMBLY__ */
++
+ /* ------------------------------------------------------------------------
+  *  Motorola IMX system registers
+  * ------------------------------------------------------------------------
+-- 
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/102-mx1-i2c.patch b/patches/u-boot/2012.04/102-mx1-i2c.patch
new file mode 100644
index 0000000..6919c81
--- /dev/null
+++ b/patches/u-boot/2012.04/102-mx1-i2c.patch
@@ -0,0 +1,46 @@
+mx1: add i2c registers
+
+Add i2c registers for Freescale imx1/L/S
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Stefano Babic <sb...@de...>
+---
+ arch/arm/include/asm/arch-imx/imx-regs.h |   23 +++++++++++++++++++++++
+ 1 files changed, 23 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch-imx/imx-regs.h b/arch/arm/include/asm/arch-imx/imx-regs.h
+index 0c26a36..a7b3404 100644
+--- a/arch/arm/include/asm/arch-imx/imx-regs.h
++++ b/arch/arm/include/asm/arch-imx/imx-regs.h
+@@ -638,4 +638,27 @@ extern void imx_gpio_mode(int gpio_mode);
+ #define TSTAT_CAPT     (1<<1)  /* Capture event */
+ #define TSTAT_COMP     (1)     /* Compare event */
+ 
++/*
++ * I2C module
++ */
++#define IADR   __REG(IMX_I2C_BASE + 0x000) /* I2C Address Register */
++#define IFDR   __REG(IMX_I2C_BASE + 0x004) /* I2C Frequency Divider Register*/
++#define I2CR   __REG(IMX_I2C_BASE + 0x008) /* I2C Control Register */
++#define I2SR   __REG(IMX_I2C_BASE + 0x00C) /* I2C Status Register */
++#define I2DR   __REG(IMX_I2C_BASE + 0x010) /* I2C Data I/O Register */
++/* I2C Control Register Bit Fields */
++#define I2CR_IEN 	(1<<7)		/* I2C Enable */
++#define I2CR_IIEN 	(1<<6)		/* I2C Interrupt Enable */
++#define I2CR_MSTA 	(1<<5)		/* I2C Master/Slave Mode Select */
++#define I2CR_MTX 	(1<<4)		/* I2C Transmit/Receive Mode Select */
++#define I2CR_TXAK 	(1<<3)		/* I2C Transmit Acknowledge Enable */
++#define I2CR_RSTA 	(1<<2)		/* I2C Repeated START */
++#define I2SR_ICF 	(1<<7)		/* I2C Data Transfer */
++#define I2SR_IAAS 	(1<<6)		/* I2C Addressed As a Slave */
++#define I2SR_IBB 	(1<<5)		/* I2C Bus Busy */
++#define I2SR_IAL 	(1<<4)		/* I2C Arbitration Lost */
++#define I2SR_SRW 	(1<<2)		/* I2C Slave Read/Write	*/
++#define I2SR_IIF 	(1<<1)		/* I2C interrupt */
++#define I2SR_RXAK 	(1<<0)		/* I2C Received Acknowledge */
++
+ #endif				/* _IMX_REGS_H */
+-- 
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/103-apf9328.patch b/patches/u-boot/2012.04/103-apf9328.patch
new file mode 100644
index 0000000..6897dab
--- /dev/null
+++ b/patches/u-boot/2012.04/103-apf9328.patch
@@ -0,0 +1,1359 @@
+apf9328: Add Armadeus Project board APF9328
+
+Add Armadeus Project board APF9328
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Nicolas Colombain <nic...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Nicolas Colombain <nic...@ar...>
+---
+ board/armadeus/apf9328/Makefile        |   51 ++++
+ board/armadeus/apf9328/apf9328.c       |  106 +++++++
+ board/armadeus/apf9328/apf9328fpga.c   |  101 +++++++
+ board/armadeus/apf9328/apf9328fpga.h   |   31 ++
+ board/armadeus/apf9328/eeprom.c        |   88 ++++++
+ board/armadeus/apf9328/fpga.c          |  121 ++++++++
+ board/armadeus/apf9328/fpga.h          |   30 ++
+ board/armadeus/apf9328/i2c.c           |  276 +++++++++++++++++++
+ board/armadeus/apf9328/lowlevel_init.S |  469 ++++++++++++++++++++++++++++++++
+ 9 files changed, 1273 insertions(+), 0 deletions(-)
+ create mode 100644 board/armadeus/apf9328/Makefile
+ create mode 100644 board/armadeus/apf9328/apf9328.c
+ create mode 100644 board/armadeus/apf9328/apf9328fpga.c
+ create mode 100644 board/armadeus/apf9328/apf9328fpga.h
+ create mode 100644 board/armadeus/apf9328/eeprom.c
+ create mode 100644 board/armadeus/apf9328/fpga.c
+ create mode 100644 board/armadeus/apf9328/fpga.h
+ create mode 100644 board/armadeus/apf9328/i2c.c
+ create mode 100644 board/armadeus/apf9328/lowlevel_init.S
+
+diff --git a/board/armadeus/apf9328/Makefile b/board/armadeus/apf9328/Makefile
+new file mode 100644
+index 0000000..0f097cd
+--- /dev/null
++++ b/board/armadeus/apf9328/Makefile
+@@ -0,0 +1,51 @@
++#
++# (C) Copyright 2000-2004
++# Wolfgang Denk, DENX Software Engineering, wd...@de....
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB	= $(obj)lib$(BOARD).o
++
++COBJS	:= apf9328.o i2c.o apf9328fpga.o fpga.o eeprom.o
++SOBJS	:= lowlevel_init.o
++
++SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS	:= $(addprefix $(obj),$(COBJS))
++SOBJS	:= $(addprefix $(obj),$(SOBJS))
++
++$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
++	$(call cmd_link_o_target, $(OBJS) $(SOBJS))
++
++clean:
++	rm -f $(SOBJS) $(OBJS)
++
++distclean:	clean
++	rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/armadeus/apf9328/apf9328.c b/board/armadeus/apf9328/apf9328.c
+new file mode 100644
+index 0000000..b72491d
+--- /dev/null
++++ b/board/armadeus/apf9328/apf9328.c
+@@ -0,0 +1,106 @@
++/*
++ * (C) Copyright 2005-2011
++ * Nicolas Colombin <th...@us...>
++ * Eric Jarrige <eri...@ar...>
++ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++
++#include <common.h>
++#include <asm/arch/imx-regs.h>
++#include <flash.h>
++#include <netdev.h>
++#include "apf9328fpga.h"
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int board_init(void)
++{
++
++	gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
++
++	return 0;
++}
++
++int dram_init(void)
++{
++	/* dram_init must store complete ramsize in gd->ram_size */
++	gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
++				    PHYS_SDRAM_1_SIZE);
++	return 0;
++}
++
++#ifndef CONFIG_SYS_DCACHE_OFF
++void enable_caches(void)
++{
++	/* Enable D-cache. I-cache is already enabled in start.S */
++	/*dcache_enable();  fix kernel 2.6.29 boot crash first*/
++}
++#endif
++
++/*
++ * Miscellaneous intialization
++ */
++int misc_init_r(void)
++{
++	char *s;
++
++#ifdef CONFIG_FPGA
++	apf9328_init_fpga();
++#endif
++
++#ifdef CONFIG_DRIVER_DM9000
++	imx_gpio_mode(GPIO_PORTB | GPIO_DR | GPIO_IN | 14);
++#endif
++
++	/* detect compatibility issue of environment version */
++	s = getenv("env_version");
++	if ((NULL == s) || (0 != strcmp(s, CONFIG_ENV_VERSION))) {
++		printf("*** Warning - Environment version change suggests: "
++		       "run flash_reset_env; reset\n");
++	}
++
++	return 0;
++}
++
++void show_boot_progress(int status)
++{
++	return;
++}
++
++#ifdef CONFIG_DRIVER_DM9000
++int board_eth_init(bd_t *bis)
++{
++	struct eth_device *dev;
++	unsigned char env_enetaddr[6];
++
++	if (dm9000_initialize(bis) != 0)
++		return -1;
++	if (!eth_getenv_enetaddr("ethaddr", env_enetaddr)) {
++		dev = eth_get_dev_by_index(0);
++		if (dev) {
++			eth_setenv_enetaddr("ethaddr", dev->enetaddr);
++		} else {
++			printf("DM9000 APF9328: Couldn't get eth device\n");
++			return -1;
++		}
++	}
++
++	return 0;
++}
++#endif
+diff --git a/board/armadeus/apf9328/apf9328fpga.c b/board/armadeus/apf9328/apf9328fpga.c
+new file mode 100644
+index 0000000..4c63c4e
+--- /dev/null
++++ b/board/armadeus/apf9328/apf9328fpga.c
+@@ -0,0 +1,101 @@
++/*
++ * (C) Copyright 2005-2011
++ * Nicolas Colombin <th...@us...>
++ * Eric Jarrige <eri...@ar...>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++
++/*
++ * Spartan 3 FPGA configuration support for the APF9328 daughter board
++ */
++
++#include <common.h>
++#include <spartan3.h>
++#include <command.h>
++#include <jffs2/jffs2.h>
++#include <asm/arch/imx-regs.h>
++#include <asm/io.h>
++#include "apf9328fpga.h"
++
++#ifdef CONFIG_FPGA
++DECLARE_GLOBAL_DATA_PTR;
++/* Note that these are pointers to code that is in Flash.  They will be
++ * relocated at runtime.
++ * Spartan3 code is used to download our Spartan 3 :) code is compatible.
++ * Just take care about the file size
++*/
++Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
++	fpga_pre_fn,
++	fpga_pgm_fn,
++	fpga_clk_fn,
++	fpga_init_fn,
++	fpga_done_fn,
++	fpga_wr_fn,
++};
++
++Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
++	{Xilinx_Spartan3,
++	 slave_serial,
++	 XILINX_XC3S400_SIZE,
++	 (void *)&fpga_fns,
++	 0}
++};
++
++/*
++ * Initialize the fpga.  Return 1 on success, 0 on failure.
++ */
++int apf9328_init_fpga(void)
++{
++	char *autoload = getenv("firmware_autoload");
++	int i, lout = 1;
++	u8 pnum;
++	struct mtd_device *dev;
++	struct part_info *part;
++
++	debug("%s:%d: Initialize FPGA interface (relocation offset= 0x%.8lx)\n",
++		__func__, __LINE__, gd->reloc_off);
++
++	fpga_init();
++
++	for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
++		debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
++		fpga_add(fpga_xilinx, &fpga[i]);
++	}
++
++	if ((autoload) && (0 == strcmp(autoload, "1"))) {
++		if (mtdparts_init() == 0)
++		if (find_dev_and_part("firmware", &dev, &pnum, &part) == 0)
++		{
++			if (ctrlc()) {
++				printf("Firmware download stopped!\n");
++				lout = 0;
++			} else if (FPGA_SUCCESS != fpga_load(0,
++							(void *)part->offset,
++							(size_t)part->size)) {
++				lout = 0;
++				printf("Firmware not loaded!\n");
++			}
++		}
++	}
++	return lout;
++}
++
++#endif /* CONFIG_FPGA */
+diff --git a/board/armadeus/apf9328/apf9328fpga.h b/board/armadeus/apf9328/apf9328fpga.h
+new file mode 100644
+index 0000000..2a15443
+--- /dev/null
++++ b/board/armadeus/apf9328/apf9328fpga.h
+@@ -0,0 +1,31 @@
++/*
++ * (C) Copyright 2002
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++
++/*
++ * Spartan 3 FPGA configuration support for the APF9328 daughter board
++ */
++
++#include "fpga.h"
++extern int apf9328_init_fpga(void);
+diff --git a/board/armadeus/apf9328/eeprom.c b/board/armadeus/apf9328/eeprom.c
+new file mode 100644
+index 0000000..8f2ad9a
+--- /dev/null
++++ b/board/armadeus/apf9328/eeprom.c
+@@ -0,0 +1,88 @@
++/*
++ * (C) Copyright 2008-2011 Armadeus Project
++ * (C) Copyright 2007
++ * Stefano Babic, DENX Software Engineering, sb...@de....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <command.h>
++#include <dm9000.h>
++
++static int do_read_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc,
++				 char * const argv[])
++{
++	unsigned int i;
++	u8 data[2];
++
++	for (i = 0; i < 0x40; i++) {
++		if (!(i % 0x10))
++			printf("\n%08x:", i);
++		dm9000_read_srom_word(i, data);
++		printf(" %02x%02x", data[1], data[0]);
++	}
++	printf("\n");
++	return 0;
++}
++
++static int do_write_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc,
++				  char * const argv[])
++{
++	unsigned long offset, value;
++
++	if (argc < 4) {
++		cmd_usage(cmdtp);
++		return 1;
++	}
++
++	strict_strtoul(argv[2], 16, &offset);
++	strict_strtoul(argv[3], 16, &value);
++	if (offset > 0x40) {
++		printf("Wrong offset : 0x%lx\n", offset);
++		cmd_usage(cmdtp);
++		return 1;
++	}
++	dm9000_write_srom_word(offset, value);
++	return 0;
++}
++
++int do_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
++{
++	if (argc < 2) {
++		cmd_usage(cmdtp);
++		return 1;
++	}
++
++	if (strcmp(argv[1], "read") == 0) {
++		return do_read_dm9000_eeprom(cmdtp, flag, argc, argv);
++	} else if (strcmp(argv[1], "write") == 0) {
++		return do_write_dm9000_eeprom(cmdtp, flag, argc, argv);
++	} else {
++		cmd_usage(cmdtp);
++		return 1;
++	}
++}
++
++U_BOOT_CMD(dm9000ee, 4, 1, do_dm9000_eeprom,
++	   "Read/Write eeprom connected to Ethernet Controller",
++	   "\ndm9000ee write <word offset> <value> \n"
++	   "\tdm9000ee read \n"
++	   "\tword:\t\t00-02 : MAC Address\n"
++	   "\t\t\t03-07 : DM9000 Configuration\n" "\t\t\t08-63 : User data");
+diff --git a/board/armadeus/apf9328/fpga.c b/board/armadeus/apf9328/fpga.c
+new file mode 100644
+index 0000000..f3d4f03
+--- /dev/null
++++ b/board/armadeus/apf9328/fpga.c
+@@ -0,0 +1,121 @@
++/*
++ * (C) Copyright 2002
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++#include <common.h>
++
++#ifdef CONFIG_FPGA
++
++#include <asm/arch/imx-regs.h>
++#include <asm/io.h>
++#include <config.h>
++
++#define GPIO_PORT(x)  ((x >> 5) & 3)
++#define GPIO_SET(x)   (DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK)))
++#define GPIO_CLEAR(x) (DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK)))
++#define GPIO_WRITE(x, y) (y ? GPIO_SET(x) : GPIO_CLEAR(x))
++#define GPIO_READ(x)  ((SSR(GPIO_PORT(x)) & (1<<(x & GPIO_PIN_MASK))))
++
++/*
++ * Port bit numbers for the serial slave controls
++ */
++#define FPGA_INIT	CONFIG_SYS_FPGA_INIT
++#define FPGA_DONE	CONFIG_SYS_FPGA_DONE
++#define FPGA_DIN	CONFIG_SYS_FPGA_DATA
++#define FPGA_PROGRAM	CONFIG_SYS_FPGA_PRG
++#define FPGA_CLOCK	CONFIG_SYS_FPGA_CLK
++
++/* Note that these are pointers to code that is in Flash.  They will be
++ * relocated at runtime.
++ * Spartan2 code is used to download our Spartan 3 :) code is compatible.
++ * Just take care about the file size
++*/
++
++/*
++ * nitialize GPIO port B before download
++ */
++int fpga_pre_fn(int cookie)
++{
++	debug("%s:%d: FPGA PRE ", __func__, __LINE__);
++
++	/* Initialize GPIO pins */
++	imx_gpio_mode(FPGA_INIT | GPIO_DR | GPIO_IN);
++	imx_gpio_mode(FPGA_DONE | GPIO_DR | GPIO_IN);
++	imx_gpio_mode(FPGA_DIN | GPIO_DR | GPIO_OUT);
++	imx_gpio_mode(FPGA_PROGRAM | GPIO_DR | GPIO_OUT);
++	imx_gpio_mode(FPGA_CLOCK | GPIO_DR | GPIO_OUT);
++	return cookie;
++}
++
++/*
++ * Set the FPGA's active-low program line to the specified level
++ */
++int fpga_pgm_fn(int assert, int flush, int cookie)
++{
++	debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__,
++	       assert ? "high" : "low");
++	GPIO_WRITE(FPGA_PROGRAM, !assert);
++	return assert;
++}
++
++/*
++ * Set the FPGA's active-high clock line to the specified level
++ */
++int fpga_clk_fn(int assert_clk, int flush, int cookie)
++{
++	debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__,
++	       assert_clk ? "high" : "low");
++	GPIO_WRITE(FPGA_CLOCK, assert_clk);
++	return assert_clk;
++}
++
++/*
++ * Test the state of the active-low FPGA INIT line.  Return 1 on INIT
++ * asserted (low).
++ */
++int fpga_init_fn(int cookie)
++{
++	debug("%s:%d: INIT check... ", __func__, __LINE__);
++	return !GPIO_READ(FPGA_INIT);
++}
++
++/*
++ * Test the state of the active-high FPGA DONE pin
++ */
++int fpga_done_fn(int cookie)
++{
++	debug("%s:%d: DONE check... ", __func__, __LINE__);
++	return GPIO_READ(FPGA_DONE);
++}
++
++/*
++ * Set the FPGA's data line to the specified level
++ */
++int fpga_wr_fn(int assert_write, int flush, int cookie)
++{
++	debug("%s:%d: DATA write... ", __func__, __LINE__);
++	GPIO_WRITE(FPGA_DIN, assert_write);
++	return assert_write;
++}
++
++#endif /* CONFIG_FPGA */
+diff --git a/board/armadeus/apf9328/fpga.h b/board/armadeus/apf9328/fpga.h
+new file mode 100644
+index 0000000..3b226d7
+--- /dev/null
++++ b/board/armadeus/apf9328/fpga.h
+@@ -0,0 +1,30 @@
++/*
++ * (C) Copyright 2002
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++extern int fpga_pre_fn(int cookie);
++extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
++extern int fpga_init_fn(int cookie);
++extern int fpga_done_fn(int cookie);
++extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
++extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+diff --git a/board/armadeus/apf9328/i2c.c b/board/armadeus/apf9328/i2c.c
+new file mode 100644
+index 0000000..0ba0a8d
+--- /dev/null
++++ b/board/armadeus/apf9328/i2c.c
+@@ -0,0 +1,276 @@
++/*
++ * (C) Copyright 2005-2011 ej Armadeus Project <eri...@ar...>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ *
++ */
++
++#include <common.h>
++
++#ifdef CONFIG_HARD_I2C
++
++#include <asm/io.h>
++#include <asm/arch/imx-regs.h>
++#include <i2c.h>
++
++/*-----------------------------------------------------------------------
++ * Definitions
++ */
++
++#define I2C_ACK		0	/* level to ack a byte */
++#define I2C_NOACK	1	/* level to noack a byte */
++
++/*-----------------------------------------------------------------------
++ * Local functions
++ */
++
++/*-----------------------------------------------------------------------
++ * START: High -> Low on SDA while SCL is High
++ * after check for a bus free
++ */
++static void imxi2c_send_start(void)
++{
++	while (I2SR & I2SR_IBB)
++		udelay(1);
++
++	I2CR |= I2CR_MSTA;
++	I2SR &= ~I2SR_IIF;
++}
++
++/*-----------------------------------------------------------------------
++ * STOP: Low -> High on SDA while SCL is High
++ * after the end of previous transfer
++ */
++static void imxi2c_send_stop(void)
++{
++	while (!(I2SR & I2SR_ICF))
++		udelay(1);
++
++	I2CR &= ~I2CR_MSTA;
++}
++
++/*-----------------------------------------------------------------------
++ * Send 8 bits and look for an acknowledgement.
++ */
++static int imxi2c_write_byte(uchar data)
++{
++	while (!(I2SR & I2SR_ICF))	/* Wait end of transfer */
++		udelay(1);
++
++	I2CR |= I2CR_MTX;
++	I2SR &= ~I2SR_IIF;
++	I2DR = data;
++
++	while (!(I2SR & I2SR_IIF))	/* checking IIF before ICF: FIXME */
++		udelay(1);
++
++	I2SR &= ~I2SR_IIF;
++
++	while (!(I2SR & I2SR_ICF))	/* Wait end of transfer */
++		udelay(1);
++
++	return I2SR & I2SR_RXAK;	/* not a nack is an ack */
++}
++
++/*-----------------------------------------------------------------------
++ * if ack == I2C_ACK, ACK the byte so can continue reading, else
++ * send I2C_NOACK to end the read.
++ */
++static uchar imxi2c_read_byte(int ack)
++{
++	int data;
++
++	while (!(I2SR & I2SR_ICF))
++		udelay(1);
++
++	I2CR &= ~I2CR_MTX;
++
++	if (ack)
++		I2CR |= I2CR_TXAK;
++	else
++		I2CR &= ~I2CR_TXAK;
++
++	data = I2DR;
++	return data;
++}
++
++/* ------------------------------------------------------------------------
++ * API Functions
++ * ------------------------------------------------------------------------
++ */
++
++/*-----------------------------------------------------------------------
++ * i2c_init compute the i2c divider to reach the requested speed
++ * see mxl reference manual
++ */
++void i2c_init(int speed, int slaveaddr)
++{
++	int hclk_dividers[] = {
++		30, 32, 36, 42, 48, 52, 60, 72,
++		80, 88, 104, 128, 144, 160, 192, 240,
++		288, 320, 384, 480, 576, 640, 768, 960,
++		1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840,
++		22, 24, 26, 26, 32, 36, 40, 44,
++		48, 56, 64, 72, 80, 96, 112, 128,
++		160, 192, 224, 256, 320, 384, 448, 512,
++		640, 768, 896, 1024, 1280, 1536, 1792, 2048
++	};
++	int refDiv = get_HCLK() / speed;
++	int i, tmpIC;
++
++	imx_gpio_mode(PA15_PF_I2C_SDA);
++	imx_gpio_mode(PA16_PF_I2C_SCL);
++
++	tmpIC = (sizeof(hclk_dividers) / sizeof(int)) - 1;
++	for (i = tmpIC; i >= 0; i--) {
++		if ((hclk_dividers[i] >= refDiv)
++		    && (hclk_dividers[i] < hclk_dividers[tmpIC])) {
++			tmpIC = i;
++		}
++	}
++
++	IFDR = tmpIC;
++	IADR = slaveaddr << 1;
++
++	if (I2SR & I2SR_IBB)
++		imxi2c_send_stop();
++
++	I2CR |= I2CR_IEN;
++}
++
++/*-----------------------------------------------------------------------
++ * Probe to see if a chip is present. Also good for checking for the
++ * completion of EEPROM writes since the chip stops responding until
++ * the write completes (typically 10mSec).
++ * probe sends a read command to probe a an address
++ */
++int i2c_probe(uchar addr)
++{
++	int rc;
++
++	imxi2c_send_start();
++	rc = imxi2c_write_byte((addr << 1) | 0);
++	imxi2c_send_stop();
++
++	return rc ? 1 : 0;
++}
++
++/*-----------------------------------------------------------------------
++ * Read bytes
++ */
++int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
++{
++	int shift;
++	debug("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
++	       chip, addr, alen, buffer, len);
++
++#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
++	/*
++	 * EEPROM chips that implement "address overflow" are ones
++	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
++	 * address and the extra bits end up in the "chip address"
++	 * bit slots. This makes a 24WC08 (1Kbyte) chip look like
++	 * four 256 byte chips.
++	 *
++	 * Note that we consider the length of the address field to
++	 * still be one byte because the extra address bits are
++	 * hidden in the chip address.
++	 */
++	chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
++
++	debug("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
++	       chip, addr);
++#endif
++
++	/*
++	 * Do the addressing portion of a write cycle to set the
++	 * chip's address pointer. If the address length is zero,
++	 * don't do the normal write cycle to set the address pointer,
++	 * there is no address pointer in this chip.
++	 */
++	imxi2c_send_start();
++	if (alen > 0) {
++		if (imxi2c_write_byte(chip << 1)) {	/* write cycle */
++			imxi2c_send_stop();
++			debug("i2c_read, no chip responded %02X\n", chip);
++			return 1;
++		}
++		shift = (alen - 1) * 8;
++		while (alen-- > 0) {
++			if (imxi2c_write_byte(addr >> shift)) {
++				debug("i2c_read, address not <ACK>ed\n");
++				return 1;
++			}
++			shift -= 8;
++		}
++
++		/* reportedly some chips need a full stop */
++		imxi2c_send_stop();
++		imxi2c_send_start();
++	}
++	/*
++	 * Send the chip address again, this time for a read cycle.
++	 * Then read the data. On the last byte, we do a NACK instead
++	 * of an ACK(len == 0) to terminate the read.
++	 */
++	imxi2c_write_byte((chip << 1) | 1);	/* read cycle */
++	imxi2c_read_byte(len <= 2);
++	while (len-- > 1)
++		*buffer++ = imxi2c_read_byte(len == 1);
++
++	imxi2c_send_stop();
++	*buffer++ = imxi2c_read_byte(0);
++	return 0;
++}
++
++/*-----------------------------------------------------------------------
++ * Write bytes
++ */
++int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
++{
++	int shift, failures = 0;
++
++	debug("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
++	       chip, addr, alen, buffer, len);
++
++	imxi2c_send_start();
++	if (imxi2c_write_byte(chip << 1)) {	/* write cycle */
++		imxi2c_send_stop();
++		debug("i2c_write, no chip responded %02X\n", chip);
++		return 1;
++	}
++	shift = (alen - 1) * 8;
++	while (alen-- > 0) {
++		if (imxi2c_write_byte(addr >> shift)) {
++			debug("i2c_write, address not <ACK>ed\n");
++			return 1;
++		}
++		shift -= 8;
++	}
++
++	while (len-- > 0) {
++		if (imxi2c_write_byte(*buffer++))
++			failures++;
++	}
++	imxi2c_send_stop();
++	return failures;
++}
++
++#endif /* CONFIG_HARD_I2C */
+diff --git a/board/armadeus/apf9328/lowlevel_init.S b/board/armadeus/apf9328/lowlevel_init.S
+new file mode 100644
+index 0000000..f080423
+--- /dev/null
++++ b/board/armadeus/apf9328/lowlevel_init.S
+@@ -0,0 +1,469 @@
++/*
++ * (C) Copyright 2005-2011 ej Armadeus Project <eri...@ar...>
++ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
++ * 02111-1307, USA.
++ *
++ */
++
++#include <config.h>
++#include <version.h>
++#include <asm/arch/imx-regs.h>
++
++.globl lowlevel_init
++lowlevel_init:
++/* Change PERCLK1DIV to 14 ie 14+1 */
++	ldr		r0,	=PCDR
++	ldr		r1,	=CONFIG_SYS_PCDR_VAL
++	str		r1,	[r0]
++
++/* set MCU PLL Control Register 0 */
++
++	ldr		r0,	=MPCTL0
++	ldr		r1,	=CONFIG_SYS_MPCTL0_VAL
++	str		r1,	[r0]
++
++/* set MCU PLL Control Register 1 */
++
++	ldr		r0,	=MPCTL1
++	ldr		r1,	=CONFIG_SYS_MPCTL1_VAL
++	str		r1,	[r0]
++
++/* set mpll restart bit */
++	ldr		r0, =CSCR
++	ldr		r1, [r0]
++	orr		r1,r1,#(1<<21)
++	str		r1, [r0]
++
++	mov		r2,#0x10
++1:
++	mov		r3,#0x2000
++2:
++	subs	r3,r3,#1
++	bne		2b
++
++	subs	r2,r2,#1
++	bne		1b
++
++/* set System PLL Control Register 0 */
++
++	ldr		r0,	=SPCTL0
++	ldr		r1,	=CONFIG_SYS_SPCTL0_VAL
++	str		r1,	[r0]
++
++/* set System PLL Control Register 1 */
++
++	ldr		r0,	=SPCTL1
++	ldr		r1,	=CONFIG_SYS_SPCTL1_VAL
++	str		r1,	[r0]
++
++/* set spll restart bit */
++	ldr		r0, =CSCR
++	ldr		r1, [r0]
++	orr		r1,r1,#(1<<22)
++	str		r1, [r0]
++
++	mov		r2,#0x10
++1:
++	mov		r3,#0x2000
++2:
++	subs	r3,r3,#1
++	bne		2b
++
++	subs	r2,r2,#1
++	bne		1b
++
++	ldr		r0,	=CSCR
++	ldr		r1,	=CONFIG_SYS_CSCR_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GPCR
++	ldr		r1,	=CONFIG_SYS_GPCR_VAL
++	str		r1,	[r0]
++
++/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
++ *this.....
++ *
++ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
++ * register 1, this stops it using the output of the PLL and thus runs at the
++ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
++ * use the value set in the CM_OSC registers...regardless of what you set it
++ * too!  Thus, although i thought i was running at 140MHz, i'm actually running
++ * at 40!..
++
++ * Slapping this into my bootloader does the trick...
++
++ * MRC p15,0,r0,c1,c0,0	 ; read core configuration register
++ * ORR r0,r0,#0xC0000000	; set asynchronous clocks and not fastbus mode
++ * MCR p15,0,r0,c1,c0,0	 ; write modified value to core configuration
++ * register
++ */
++	MRC p15,0,r0,c1,c0,0
++	ORR r0,r0,#0xC0000000
++	MCR p15,0,r0,c1,c0,0
++
++/*	ldr		r0,	=GPR(0)
++	ldr		r1,	=CONFIG_SYS_GPR_A_VAL
++	str		r1,	[r0]
++*/
++
++	ldr		r0,	=DR(0)
++	ldr		r1,	=CONFIG_SYS_DR_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=OCR1(0)
++	ldr		r1,	=CONFIG_SYS_OCR1_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=OCR2(0)
++	ldr		r1,	=CONFIG_SYS_OCR2_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFA1(0)
++	ldr		r1,	=CONFIG_SYS_ICFA1_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFA2(0)
++	ldr		r1,	=CONFIG_SYS_ICFA2_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFB1(0)
++	ldr		r1,	=CONFIG_SYS_ICFB1_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFB2(0)
++	ldr		r1,	=CONFIG_SYS_ICFB2_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICR1(0)
++	ldr		r1,	=CONFIG_SYS_ICR1_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICR2(0)
++	ldr		r1,	=CONFIG_SYS_ICR2_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=IMR(0)
++	ldr		r1,	=CONFIG_SYS_IMR_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=DDIR(0)
++	ldr		r1,	=CONFIG_SYS_DDIR_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GPR(0)
++	ldr		r1,	=CONFIG_SYS_GPR_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=PUEN(0)
++	ldr		r1,	=CONFIG_SYS_PUEN_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GIUS(0)
++	ldr		r1,	=CONFIG_SYS_GIUS_A_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=DR(1)
++	ldr		r1,	=CONFIG_SYS_DR_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=OCR1(1)
++	ldr		r1,	=CONFIG_SYS_OCR1_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=OCR2(1)
++	ldr		r1,	=CONFIG_SYS_OCR2_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFA1(1)
++	ldr		r1,	=CONFIG_SYS_ICFA1_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFA2(1)
++	ldr		r1,	=CONFIG_SYS_ICFA2_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFB1(1)
++	ldr		r1,	=CONFIG_SYS_ICFB1_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFB2(1)
++	ldr		r1,	=CONFIG_SYS_ICFB2_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICR1(1)
++	ldr		r1,	=CONFIG_SYS_ICR1_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICR2(1)
++	ldr		r1,	=CONFIG_SYS_ICR2_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=IMR(1)
++	ldr		r1,	=CONFIG_SYS_IMR_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=DDIR(1)
++	ldr		r1,	=CONFIG_SYS_DDIR_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GPR(1)
++	ldr		r1,	=CONFIG_SYS_GPR_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=PUEN(1)
++	ldr		r1,	=CONFIG_SYS_PUEN_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GIUS(1)
++	ldr		r1,	=CONFIG_SYS_GIUS_B_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=DR(2)
++	ldr		r1,	=CONFIG_SYS_DR_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=OCR1(2)
++	ldr		r1,	=CONFIG_SYS_OCR1_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=OCR2(2)
++	ldr		r1,	=CONFIG_SYS_OCR2_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFA1(2)
++	ldr		r1,	=CONFIG_SYS_ICFA1_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFA2(2)
++	ldr		r1,	=CONFIG_SYS_ICFA2_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFB1(2)
++	ldr		r1,	=CONFIG_SYS_ICFB1_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFB2(2)
++	ldr		r1,	=CONFIG_SYS_ICFB2_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICR1(2)
++	ldr		r1,	=CONFIG_SYS_ICR1_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICR2(2)
++	ldr		r1,	=CONFIG_SYS_ICR2_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=IMR(2)
++	ldr		r1,	=CONFIG_SYS_IMR_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=DDIR(2)
++	ldr		r1,	=CONFIG_SYS_DDIR_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GPR(2)
++	ldr		r1,	=CONFIG_SYS_GPR_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=PUEN(2)
++	ldr		r1,	=CONFIG_SYS_PUEN_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GIUS(2)
++	ldr		r1,	=CONFIG_SYS_GIUS_C_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=DR(3)
++	ldr		r1,	=CONFIG_SYS_DR_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=OCR1(3)
++	ldr		r1,	=CONFIG_SYS_OCR1_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=OCR2(3)
++	ldr		r1,	=CONFIG_SYS_OCR2_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFA1(3)
++	ldr		r1,	=CONFIG_SYS_ICFA1_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFA2(3)
++	ldr		r1,	=CONFIG_SYS_ICFA2_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFB1(3)
++	ldr		r1,	=CONFIG_SYS_ICFB1_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICONFB2(3)
++	ldr		r1,	=CONFIG_SYS_ICFB2_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICR1(3)
++	ldr		r1,	=CONFIG_SYS_ICR1_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=ICR2(3)
++	ldr		r1,	=CONFIG_SYS_ICR2_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=IMR(3)
++	ldr		r1,	=CONFIG_SYS_IMR_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=DDIR(3)
++	ldr		r1,	=CONFIG_SYS_DDIR_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GPR(3)
++	ldr		r1,	=CONFIG_SYS_GPR_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=PUEN(3)
++	ldr		r1,	=CONFIG_SYS_PUEN_D_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=GIUS(3)
++	ldr		r1,	=CONFIG_SYS_GIUS_D_VAL
++	str		r1,	[r0]
++
++/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
++
++	ldr		r0,	=FMCR
++	ldr		r1,	=CONFIG_SYS_FMCR_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS0U
++	ldr		r1,	=CONFIG_SYS_CS0U_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS0L
++	ldr		r1,	=CONFIG_SYS_CS0L_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS1U
++	ldr		r1,	=CONFIG_SYS_CS1U_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS1L
++	ldr		r1,	=CONFIG_SYS_CS1L_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS2U
++	ldr		r1,	=CONFIG_SYS_CS2U_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS2L
++	ldr		r1,	=CONFIG_SYS_CS2L_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS3U
++	ldr		r1,	=CONFIG_SYS_CS3U_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS3L
++	ldr		r1,	=CONFIG_SYS_CS3L_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS4U
++	ldr		r1,	=CONFIG_SYS_CS4U_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS4L
++	ldr		r1,	=CONFIG_SYS_CS4L_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS5U
++	ldr		r1,	=CONFIG_SYS_CS5U_VAL
++	str		r1,	[r0]
++
++	ldr		r0,	=CS5L
++	ldr		r1,	=CONFIG_SYS_CS5L_VAL
++	str		r1,	[r0]
++
++	adr	r0, sdramsetup	/* r0 <- current position of code */
++	/* test if we run from flash or RAM */
++	ldr	r1, =PHYS_SDRAM_1
++	cmp	r1, r0		/* don't reloc during debug*/
++	bhi		sdramsetup
++	/* test if we run from flash or RAM */
++	ldr	r1, =CONFIG_SYS_FLASH_BASE
++	cmp	r0, r1		/* don't reloc during debug */
++	bmi		copy2ram
++
++/* SDRAM Setup */
++sdramsetup:
++	ldr		r0, =SDCTL0
++	ldr		r1, =CONFIG_SYS_PRECHARGE_CMD
++	str		r1,	[r0]
++
++	ldr		r1, =PHYS_SDRAM_1			\
++				+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
++	ldr		r2,	[r1]
++
++	ldr		r1, =CONFIG_SYS_AUTOREFRESH_CMD
++	str		r1,	[r0]
++
++	ldr		r1, =PHYS_SDRAM_1
++	ldr		r2,	[r1] /* Issue AutoRefresh Command */
++	ldr		r2,	[r1]
++	ldr		r2,	[r1]
++	ldr		r2,	[r1]
++	ldr		r2,	[r1]
++	ldr		r2,	[r1]
++	ldr		r2,	[r1]
++	ldr		r2,	[r1]
++
++	ldr		r1, =CONFIG_SYS_SET_MODE_REG_CMD
++	str		r1,	[r0]
++
++	ldr		r1, =PHYS_SDRAM_1			\
++				+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
++	str		r2,	[r1]
++
++	ldr		r1, =CONFIG_SYS_NORMAL_RW_CMD
++	str		r1,	[r0]
++/* make U-Boot runnable form "almost" anywhere */
++/* but SYS_TEXT_BASE should be in RAM */
++copy2ram:		/* populate _TEXT_BASE with U-Boot from load addr */
++	ldr	r0, _start_adr
++	ldr	r1, _copy2ram
++	sub	r1, r1, r0
++	adr	r0, copy2ram
++	sub	r0, r0, r1
++	ldr	r1, =CONFIG_SYS_TEXT_BASE
++	cmp	r0, r1
++	beq	end_of_copy2ram		/* skip U-Boot copy */
++	ldr	r2, =CONFIG_SYS_MONITOR_LEN
++	add	r2, r2, r0		/* r2 <- source end address	    */
++
++copy_loop:
++	ldmia	r0!, {r9-r10}		/* copy from source address [r0]    */
++	stmia	r1!, {r9-r10}		/* copy to   target address [r1]    */
++	cmp	r0, r2			/* until source end address [r2]    */
++	blo	copy_loop
++
++end_of_copy2ram:
++	mov	pc,lr
++
++_copy2ram:
++	.word copy2ram
++_start_adr:
++	.word _start
+-- 
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/104-apf9328-makefile.patch b/patches/u-boot/2012.04/104-apf9328-makefile.patch
new file mode 100644
index 0000000..b325d1d
--- /dev/null
+++ b/patches/u-boot/2012.04/104-apf9328-makefile.patch
@@ -0,0 +1,41 @@
+apf9328: add apf9328 board in Makefile
+
+add apf9328 board definition in makefile, MAKEALL and MAINTAINERS list
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+---
+ MAINTAINERS |    4 ++++
+ boards.cfg  |    1 +
+ 2 files changed, 5 insertions(+), 0 deletions(-)
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 708ded7..183cf0e 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -240,6 +240,10 @@ Ilko Iliev <il...@ro...>
+ 	PM9263		AT91SAM9263
+ 	PM9G45		ARM926EJS (AT91SAM9G45 SoC)
+ 
++Eric Jarrige <eri...@ar...>
++
++	apf9328		ARM920T (iMX1)
++
+ Gary Jennejohn <ga...@de...>
+ 
+ 	quad100hd	PPC405EP
+diff --git a/boards.cfg b/boards.cfg
+index 3cf75c3..c8bc589 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -52,6 +52,7 @@ integratorap_cm720t          arm         arm720t     integrator          armltd
+ integratorap_cm920t          arm         arm920t     integrator          armltd         -           integratorap:CM920T
+ integratorcp_cm920t          arm         arm920t     integrator          armltd         -           integratorcp:CM920T
+ a320evb                      arm         arm920t     -                   faraday        a320
++apf9328                      arm         arm920t     apf9328             armadeus       imx
+ at91rm9200ek                 arm         arm920t     at91rm9200ek        atmel          at91        at91rm9200ek
+ at91rm9200ek_ram             arm         arm920t     at91rm9200ek        atmel          at91        at91rm9200ek:RAMBOOT
+ eb_cpux9k2                   arm         arm920t     -                   BuS            at91
+-- 
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/106-mx1-pllclk.patch b/patches/u-boot/2012.04/106-mx1-pllclk.patch
new file mode 100644
index 0000000..40cb77c
--- /dev/null
+++ b/patches/u-boot/2012.04/106-mx1-pllclk.patch
@@ -0,0 +1,63 @@
+mx1: improve PLL freq computation
+
+Improve PLL freq computation by using the full resolution of the PLL registers
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Stefano Babic <sb...@de...>
+---
+ arch/arm/cpu/arm920t/imx/speed.c |   29 +++++++++++------------------
+ 1 files changed, 11 insertions(+), 18 deletions(-)
+
+diff --git a/arch/arm/cpu/arm920t/imx/speed.c b/arch/arm/cpu/arm920t/imx/speed.c
+index 1e29698..b1c2bd6 100644
+--- a/arch/arm/cpu/arm920t/imx/speed.c
++++ b/arch/arm/cpu/arm920t/imx/speed.c
+@@ -36,33 +36,26 @@
+  * the specified bus in HZ.
+  */
+ /* ------------------------------------------------------------------------- */
+-
+-ulong get_systemPLLCLK(void)
++static ulong get_PLLCLK(u32 sys_clk_freq, u32 pllctl0)
+ {
+ 	/* FIXME: We assume System_SEL = 0 here */
+-	u32 spctl0 = SPCTL0;
+-	u32 mfi = (spctl0 >> 10) & 0xf;
+-	u32 mfn = spctl0 & 0x3f;
+-	u32 mfd = (spctl0 >> 16) & 0x3f;
+-	u32 pd =  (spctl0 >> 26) & 0xf;
++	u32 mfi = (pllctl0 >> 10) & 0xf;
++	u32 mfn = pllctl0 & 0x3ff;
++	u32 mfd = (pllctl0 >> 16) & 0x3ff;
++	u32 pd =  (pllctl0 >> 26) & 0xf;
+ 
+ 	mfi = mfi<=5 ? 5 : mfi;
++	return (2*(u64)sys_clk_freq * (mfi*(mfd+1) + mfn))/((mfd+1)*(pd+1));
++}
+ 
+-	return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
++ulong get_systemPLLCLK(void)
++{
++	return get_PLLCLK(CONFIG_SYSPLL_CLK_FREQ, SPCTL0);
+ }
+ 
+ ulong get_mcuPLLCLK(void)
+ {
+-	/* FIXME: We assume System_SEL = 0 here */
+-	u32 mpctl0 = MPCTL0;
+-	u32 mfi = (mpctl0 >> 10) & 0xf;
+-	u32 mfn = mpctl0 & 0x3f;
+-	u32 mfd = (mpctl0 >> 16) & 0x3f;
+-	u32 pd =  (mpctl0 >> 26) & 0xf;
+-
+-	mfi = mfi<=5 ? 5 : mfi;
+-
+-	return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
++	return get_PLLCLK(CONFIG_SYS_CLK_FREQ, MPCTL0);
+ }
+ 
+ ulong get_FCLK(void)
+-- 
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/107-mx1-pllclk-debug.patch b/patches/u-boot/2012.04/107-mx1-pllclk-debug.patch
new file mode 100644
index 0000000..9621b0a
--- /dev/null
+++ b/patches/u-boot/2012.04/107-mx1-pllclk-debug.patch
@@ -0,0 +1,26 @@
+mx1: change a printf in speed.c to use debug instead
+
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Stefano Babic <sb...@de...>
+---
+ arch/arm/cpu/arm920t/imx/speed.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/cpu/arm920t/imx/speed.c b/arch/arm/cpu/arm920t/imx/speed.c
+index b1c2bd6..b8e42bf 100644
+--- a/arch/arm/cpu/arm920t/imx/speed.c
++++ b/arch/arm/cpu/arm920t/imx/speed.c
+@@ -67,7 +67,7 @@ ulong get_FCLK(void)
+ ulong get_HCLK(void)
+ {
+ 	u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
+-	printf("bclkdiv: %d\n", bclkdiv);
++	debug("bclkdiv: %d\n", bclkdiv);
+ 	return get_systemPLLCLK() / bclkdiv;
+ }
+ 
+-- 
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/108-DM9000.patch b/patches/u-boot/2012.04/108-DM9000.patch
new file mode 100644
index 0000000..e6a18d7
--- /dev/null
+++ b/patches/u-boot/2012.04/108-DM9000.patch
@@ -0,0 +1,48 @@
+DM9000: change some printf to use debug instead
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Ben Warren <big...@gm...>
+---
+ drivers/net/dm9000x.c |    8 ++++----
+ 1 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c
+index 0424110..3e56db5 100644
+--- a/drivers/net/dm9000x.c
++++ b/drivers/net/dm9000x.c
+@@ -240,7 +240,7 @@ dm9000_probe(void)
+ 	id_val |= DM9000_ior(DM9000_PIDL) << 16;
+ 	id_val |= DM9000_ior(DM9000_PIDH) << 24;
+ 	if (id_val == DM9000_ID) {
+-		printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
++		DM9000_DBG("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
+ 		       id_val);
+ 		return 0;
+ 	} else {
+@@ -306,19 +306,19 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd)
+ 
+ 	switch (io_mode) {
+ 	case 0x0:  /* 16-bit mode */
+-		printf("DM9000: running in 16 bit mode\n");
++		DM9000_DBG("DM9000: running in 16 bit mode\n");
+ 		db->outblk    = dm9000_outblk_16bit;
+ 		db->inblk     = dm9000_inblk_16bit;
+ 		db->rx_status = dm9000_rx_status_16bit;
+ 		break;
+ 	case 0x01:  /* 32-bit mode */
+-		printf("DM9000: running in 32 bit mode\n");
++		DM9000_DBG("DM9000: running in 32 bit mode\n");
+ 		db->outblk    = dm9000_outblk_32bit;
+ 		db->inblk     = dm9000_inblk_32bit;
+ 		db->rx_status = dm9000_rx_status_32bit;
+ 		break;
+ 	case 0x02: /* 8 bit mode */
+-		printf("DM9000: running in 8 bit mode\n");
++		DM9000_DBG("DM9000: running in 8 bit mode\n");
+ 		db->outblk    = dm9000_outblk_8bit;
+ 		db->inblk     = dm9000_inblk_8bit;
+ 		db->rx_status = dm9000_rx_status_8bit;
+-- 
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/109-mx1-relocation.patch b/patches/u-boot/2012.04/109-mx1-relocation.patch
new file mode 100644
index 0000000..65ee7b6
--- /dev/null
+++ b/patches/u-boot/2012.04/109-mx1-relocation.patch
@@ -0,0 +1,33 @@
+mx1: Fix jump to the relocated board_init_r
+
+Jump to the relocated board_init_r according to the initial computation
+and remove computation against current PC addr as relocated address is
+already known and fixed.
+This helps to support CPU that miroor flash to different address at
+power on boot such as iMX1/L
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Stefano Babic <sb...@de...>
+---
+ arch/arm/cpu/arm920t/start.S |    4 +---
+ 1 files changed, 1 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
+index 8c5612c..25cd4a2 100644
+--- a/arch/arm/cpu/arm920t/start.S
++++ b/arch/arm/cpu/arm920t/start.S
+@@ -292,9 +292,7 @@ _nand_boot_ofs:
+ 	.word nand_boot
+ #else
+ 	ldr	r0, _board_init_r_ofs
+-	adr	r1, _start
+-	add	lr, r0, r1
+-	add	lr, lr, r9
++	add	lr, r0, r6
+ 	/* setup parameters for board_init_r */
+ 	mov	r0, r5		/* gd_t */
+ 	mov	r1, r6		/* dest_addr */
+-- 
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/111-mx1-timer.patch b/patches/u-boot/2012.04/111-mx1-timer.patch
new file mode 100644
index 0000000..74fb28b
--- /dev/null
+++ b/patches/u-boot/2012.04/111-mx1-timer.patch
@@ -0,0 +1,25 @@
+mx1: Fix function get_timer() to adjust frequency according to CONFIG_SYS_HZ
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Stefano Babic <sb...@de...>
+---
+ arch/arm/cpu/arm920t/imx/timer.c |    2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/cpu/arm920t/imx/timer.c b/arch/arm/cpu/arm920t/imx/timer.c
+index 6141bd4..d6d1968 100644
+--- a/arch/arm/cpu/arm920t/imx/timer.c
++++ b/arch/arm/cpu/arm920t/imx/timer.c
+@@ -55,7 +55,7 @@ int timer_init (void)
+  */
+ ulong get_timer (ulong base)
+ {
+-	return get_timer_masked() - base;
++	return get_timer_masked() / (1000000 / CONFIG_SYS_HZ) - base;
+ }
+ 
+ ulong get_timer_masked (void)
+-- 
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch b/patches/u-boot/2012.04/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
new file mode 100644
index 0000000..d962599
--- /dev/null
+++ b/patches/u-boot/2012.04/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
@@ -0,0 +1,156 @@
+Add WEIM, NFC SYSTEM_CTLconstants to the mx27 CPU
+
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+ arch/arm/cpu/arm926ejs/mx27/asm-offsets.c |   28 +++++++++++
+ arch/arm/include/asm/arch-mx27/imx-regs.h |    9 ++++
+ arch/arm/include/asm/arch-mx27/mxc_nand.h |   73 +++++++++++++++++++++++++++++
+ 3 files changed, 110 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/include/asm/arch-mx27/mxc_nand.h
+
+diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
+index f3a8d7b..7dad00f 100644
+--- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
++++ b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
+@@ -34,6 +34,7 @@ int main(void)
+ 	DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
+ 	DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
+ 	DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
++	DEFINE(CCSR, IMX_PLL_BASE + offsetof(struct pll_regs, ccsr));
+ 
+ 	DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
+ 	DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
+@@ -41,5 +42,32 @@ int main(void)
+ 	DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
+ 	DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
+ 
++	DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, gpcr));
++	DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, fmcr));
++	DEFINE(DSCR2, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr2));
++	DEFINE(DSCR3, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr3));
++	DEFINE(DSCR7, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr7));
++	DEFINE(DSCR10, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr10));
++
++	DEFINE(CS0U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0u));
++	DEFINE(CS0L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0l));
++	DEFINE(CS0A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0a));
++	DEFINE(CS1U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1u));
++	DEFINE(CS1L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1l));
++	DEFINE(CS1A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1a));
++	DEFINE(CS2U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2u));
++	DEFINE(CS2L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2l));
++	DEFINE(CS2A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2a));
++	DEFINE(CS3U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3u));
++	DEFINE(CS3L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3l));
++	DEFINE(CS3A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3a));
++	DEFINE(CS4U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4u));
++	DEFINE(CS4L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4l));
++	DEFINE(CS4A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4a));
++	DEFINE(CS5U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5u));
++	DEFINE(CS5L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5l));
++	DEFINE(CS5A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5a));
++	DEFINE(EIM,  IMX_WEIM_BASE + offsetof(struct weim_regs, eim));
++
+ 	return 0;
+ }
+diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
+index ced5b2a..4df67d6 100644
+--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
++++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
+@@ -522,4 +522,13 @@ struct fuse_bank0_regs {
+ #define IIM_ERR_SNSE	(1 << 2)
+ #define IIM_ERR_PARITYE	(1 << 1)
+ 
++/*
++ * Memory areas of the NFC
++ */
++#define IMX_NFC_BASE                    (0xD8000000)
++#define IMX_NFC_MAIN_AREA0              (0xD8000000)
++#define IMX_NFC_MAIN_AREA1              (0xD8000200)
++#define IMX_NFC_SPARE_AREA0             (0xD8000800)
++#define IMX_NFC_REGS                    (0xD8000E00)
++
+ #endif				/* _IMX_REGS_H */
+diff --git a/arch/arm/include/asm/arch-mx27/mxc_nand.h b/arch/arm/include/asm/arch-mx27/mxc_nand.h
+new file mode 100644
+index 0000000..99af18b
+--- /dev/null
++++ b/arch/arm/include/asm/arch-mx27/mxc_nand.h
+@@ -0,0 +1,73 @@
++/*
++ * (c) 2012 Philippe Reynes <tr...@ya...>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __MXC_NAND_H
++#define __MXC_NAND_H
++
++/*
++ * NFC registers address offest
++ */
++#define NFC_OFFSET_BUFSIZE             (0x00) /* Internal SRAM Size */
++#define NFC_OFFSET_BLCK_ADD_LOCK       (0x02) /* NAND Flash Block Address for Lock Check */
++#define NFC_OFFSET_BUF_ADDR            (0x04) /* Buffer Number for Page Data Transfer To/
++                                                 From Flash Memory */
++#define NFC_OFFSET_FLASH_ADDR          (0x06) /* NAND Flash Address */
++#define NFC_OFFSET_FLASH_CMD           (0x08) /* NAND Flash Command */
++#define NFC_OFFSET_CONFIG              (0x0A) /* NFC Internal Buffer Lock Control */
++#define NFC_OFFSET_ECC_STATUS_RESULT   (0x0C) /* Controller Status/Result of Flash Operation */
++#define NFC_OFFSET_ECC_RSLT_MAIN_AREA  (0x0E) /* ECC ...
 
[truncated message content]

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-323-gfc8e6ec

From: jorasse <jo...@us...> - 2012-05-23 22:11:28

This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
       via  fc8e6ec67b11887a524097e29c50b90460fe25f4 (commit)
       via  7845d55787986d26d168d6af3294b5f75b5e3f4a (commit)
      from  61c43fbb986e9eadc10e11f56de77532456cc0de (commit)

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- Log -----------------------------------------------------------------
commit fc8e6ec67b11887a524097e29c50b90460fe25f4
Merge: 7845d55 61c43fb
Author: Eric Jarrige <eri...@ar...>
Date:   Thu May 24 00:11:24 2012 +0200

    Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus

commit 7845d55787986d26d168d6af3294b5f75b5e3f4a
Author: Eric Jarrige <eri...@ar...>
Date:   Thu May 24 00:09:59 2012 +0200

    [LINUX] apf28: clean and rework mx28 ethernet FEC devices to improve reliability and power comsumption in low power modes

-----------------------------------------------------------------------

Summary of changes:
 .../450-armadeus-add_apf28_module_support.patch    |  284 +++++++++++++++-----
 ...1-armadeus-add_apf28dev_baseboard_support.patch |   92 ++-----
 2 files changed, 233 insertions(+), 143 deletions(-)

diff --git a/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch b/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch
index 1940bea..91d6d70 100644
--- a/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch
+++ b/patches/linux/2.6.35/450-armadeus-add_apf28_module_support.patch
@@ -37,7 +37,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
 +++ linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c	2012-02-03 17:39:56.000000000 +0100
-@@ -0,0 +1,323 @@
+@@ -0,0 +1,401 @@
 +/*
 + * Copyright (C) 2012 Armadeus systems
 + *
@@ -66,14 +66,17 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +#include <linux/clk.h>
 +#include <linux/platform_device.h>
 +#include <linux/delay.h>
++#include <linux/fec.h>
 +
 +#include <asm/setup.h>
 +#include <asm/mach-types.h>
 +#include <asm/mach/arch.h>
 +
++#include <mach/apf28.h>
 +#include <mach/hardware.h>
 +#include <mach/device.h>
 +#include <mach/pinctrl.h>
++#include <mach/regs-ocotp.h>
 +
 +#include <linux/mtd/mtd.h>
 +#include <linux/mtd/partitions.h>
@@ -82,8 +85,6 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +#include "mx28_pins.h"
 +#include "device.h"
 +
-+extern void apf28_baseboard_init(void);
-+
 +static struct pin_desc apf28_fixed_pins[] = {
 +	{
 +		.name		= "DUART.RX",
@@ -95,9 +96,6 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +		.id		= PINID_PWM1,
 +		.fun		= PIN_FUN3,
 +	},
-+};
-+
-+static struct pin_desc apf28_eth_pins[] = {
 +#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\
 +	|| defined(CONFIG_FEC_L2SWITCH)
 +	{
@@ -191,110 +189,190 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +		.drive		= 1,
 +	},
 +	{
-+		.name		= "PHY0_RESET",
-+		.id		= PINID_ENET0_RX_CLK,
++		.name		= "ETH0_INT",
++		.id		= PINID_ENET0_TX_CLK,
 +		.fun		= PIN_GPIO,
 +		.strength	= PAD_4MA,
 +		.voltage	= PAD_3_3V,
 +		.pullup		= 0,
 +		.drive		= 1,
 +		.pull		= 0,
-+		.output		= 1,
-+		.data		= 1,
++		.output		= 0,
 +	},
 +	{
-+		.name		= "ETH0_INT",
-+		.id		= PINID_ENET0_TX_CLK,
++		.name		= "PHY0_RESET",
++		.id		= PINID_ENET0_RX_CLK,
 +		.fun		= PIN_GPIO,
 +		.strength	= PAD_4MA,
 +		.voltage	= PAD_3_3V,
 +		.pullup		= 0,
 +		.drive		= 1,
 +		.pull		= 0,
-+		.output		= 0,
++		.output		= 1,
++		.data		= 1,
 +	},
 +#endif /* defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) */
 +};
 +
-+int __inline__ apf28_enet0_gpio_init(void)
++/*
++ * Stub implementations for mx287 FEC1 init to be overloaded in the baseboard
++ * source code.
++ */
++int __mx287_fec1_gpio_init(void) {
++	return 0;
++}
++
++int mx287_fec1_gpio_init(void)
++	__attribute__((weak, alias("__mx287_fec1_gpio_init")));
++
++/* Stub implementation used in FEC l2switch mode*/
++int mx28evk_enet_gpio_init(void)
 +{
-+	/* reset phy */
 +	gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 0);
-+
 +	udelay(100);
 +	gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 1);
++	mx287_fec1_gpio_init();
 +
 +	return 0;
 +}
 +
-+void __inline__ apf28_enet0_io_lowerpower_enter(void)
++/*
++ * Power management calls these function when entering and leaving sleep modes.
++ * They can be overloaded in the baseboard source code.
++ */
++void __mx28evk_enet_io_lowerpower_enter(void) {; }
++void mx28evk_enet_io_lowerpower_enter(void)
++	__attribute__((weak, alias("__mx28evk_enet_io_lowerpower_enter")));
++
++void __mx28evk_enet_io_lowerpower_exit(void) { ; }
++void mx28evk_enet_io_lowerpower_exit(void)
++	__attribute__((weak, alias("__mx28evk_enet_io_lowerpower_exit")));
++
++
++#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\
++	|| defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE)
++int apf28_fec0_gpio_init(void)
 +{
-+	int i;
-+	for (i = 0; i < ARRAY_SIZE(apf28_eth_pins); i++) {
-+		mxs_release_pin(apf28_eth_pins[i].id,
-+			apf28_eth_pins[i].name);
-+		gpio_request(MXS_PIN_TO_GPIO(apf28_eth_pins[i].id),
-+			apf28_eth_pins[i].name);
-+		gpio_direction_output(
-+			MXS_PIN_TO_GPIO(apf28_eth_pins[i].id), 0);
-+	}
++	gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 0);
++	udelay(100);
++	gpio_direction_output(MXS_PIN_TO_GPIO(PINID_ENET0_RX_CLK), 1);
++
++	return 0;
 +}
 +
-+void __inline__ apf28_enet0_io_lowerpower_exit(void)
++#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)
++static struct resource fec0_resource[] = {
++	{
++		.start	= ENET_PHYS_ADDR,
++		.end	= ENET_PHYS_ADDR + 0x3fff,
++		.flags	= IORESOURCE_MEM
++	},
++	{
++		.start	= IRQ_ENET_MAC0,
++		.end	= IRQ_ENET_MAC0,
++		.flags	= IORESOURCE_IRQ
++	},
++};
++
++static struct fec_platform_data fec_pdata0 = {
++	.phy = PHY_INTERFACE_MODE_RMII,
++	.init = apf28_fec0_gpio_init,
++};
++#endif
++
++#if defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE)
++static struct resource fec1_resource[] = {
++	{
++		.start	= ENET_PHYS_ADDR + 0x4000,
++		.end	= ENET_PHYS_ADDR + 0x7fff,
++		.flags	= IORESOURCE_MEM
++	},
++	{
++		.start	= IRQ_ENET_MAC1,
++		.end	= IRQ_ENET_MAC1,
++		.flags	= IORESOURCE_IRQ
++	},
++};
++
++static struct fec_platform_data fec_pdata1 = {
++	.phy	= PHY_INTERFACE_MODE_RMII,
++	.init	= mx287_fec1_gpio_init,
++};
++#endif
++
++
++static void __init apf28_init_fec(void)
 +{
++	struct platform_device *pdev;
++	struct mxs_dev_lookup *lookup;
++	struct fec_platform_data *pfec;
 +	int i;
-+	for (i = 0; i < ARRAY_SIZE(apf28_eth_pins); i++) {
-+		gpio_free(MXS_PIN_TO_GPIO(apf28_eth_pins[i].id));
-+		if (apf28_eth_pins[i].fun != PIN_GPIO)
-+			mxs_request_pin(apf28_eth_pins[i].id,
-+				apf28_eth_pins[i].fun,
-+				apf28_eth_pins[i].name);
-+		else {
-+			gpio_request(MXS_PIN_TO_GPIO(apf28_eth_pins[i].id),
-+				apf28_eth_pins[i].name);
-+			if (apf28_eth_pins[i].output)
-+				gpio_direction_output(
-+					MXS_PIN_TO_GPIO(apf28_eth_pins[i].id),
-+					apf28_eth_pins[i].data);
-+			else
-+				gpio_direction_input(
-+					MXS_PIN_TO_GPIO(apf28_eth_pins[i].id));
++	u32 val;
++
++	__raw_writel(BM_OCOTP_CTRL_RD_BANK_OPEN,
++			IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL_SET);
++
++	while (BM_OCOTP_CTRL_BUSY &
++		__raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) + HW_OCOTP_CTRL))
++		udelay(10);
++
++	lookup = mxs_get_devices("mxs-fec");
++	if (lookup == NULL || IS_ERR(lookup))
++		return;
++
++	for (i = 0; i < lookup->size; i++) {
++		pdev = lookup->pdev + i;
++		val =  __raw_readl(IO_ADDRESS(OCOTP_PHYS_ADDR) +
++						HW_OCOTP_CUSTn(pdev->id));
++		switch (pdev->id) {
++		case 0:
++#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)
++			pdev->resource = fec0_resource;
++			pdev->num_resources = ARRAY_SIZE(fec0_resource);
++			pdev->dev.platform_data = &fec_pdata0;
++			break;
++		case 1:
++#endif
++#if defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE)
++			pdev->resource = fec1_resource;
++			pdev->num_resources = ARRAY_SIZE(fec1_resource);
++			pdev->dev.platform_data = &fec_pdata1;
++			break;
++#endif
++		default:
++			return;
 +		}
-+	}
-+}
 +
-+#if !defined(CONFIG_FEC2) && !defined(CONFIG_FEC2_MODULE)\
-+	&& !defined(CONFIG_FEC_L2SWITCH)
-+int mx28evk_enet_gpio_init(void)
-+{
-+	apf28_enet0_gpio_init();
-+	return 0;
-+}
++		pfec = (struct fec_platform_data *)pdev->dev.platform_data;
++		pfec->mac[0] = 0x00;
++		pfec->mac[1] = 0x1e;
++		pfec->mac[2] = (val >> 24) & 0xFF;
++		pfec->mac[3] = (val >> 16) & 0xFF;
++		pfec->mac[4] = (val >> 8) & 0xFF;
++		pfec->mac[5] = (val >> 0) & 0xFF;
 +
-+void mx28evk_enet_io_lowerpower_enter(void)
-+{
-+	apf28_enet0_io_lowerpower_enter();
++		mxs_add_device(pdev, 2);
++	}
 +}
 +
-+void mx28evk_enet_io_lowerpower_exit(void)
-+{
-+	apf28_enet0_io_lowerpower_exit();
-+}
-+#endif
++#else
++static void __init apf28_init_fec(void) { ; }
++#endif /* defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) 
++	|| defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE) */
 +
 +/* used by device.c (mx28evk makes it a bootcmd option) */
 +int enable_gpmi = 1;
 +
 +
 +static void __init fixup_board(struct machine_desc *desc, struct tag *tags,
-+			       char **cmdline, struct meminfo *mi)
++				char **cmdline, struct meminfo *mi)
 +{
 +	mx28_set_input_clk(24000000, 24000000, 32000, 50000000);
 +}
 +
 +static void __init apf28_device_init(void)
 +{
-+	/* Add apf28 special code */
++	/* Add apf28 special device init code */
 +	;
 +}
 +
@@ -334,21 +412,21 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +#else
 +	iram_init(MX28_OCRAM_PHBASE, MX28_OCRAM_SIZE);
 +#endif
-+
 +	mx28_gpio_init();
 +	apf28_init_pin_group(apf28_fixed_pins, ARRAY_SIZE(apf28_fixed_pins));
++#ifdef CONFIG_MACH_APF28_HAS_BASEBOARD
++	apf28_baseboard_pins_init();
++#endif
 +
-+#if defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE)\
-+	|| defined(CONFIG_FEC_L2SWITCH)
-+	apf28_init_pin_group(apf28_eth_pins, ARRAY_SIZE(apf28_eth_pins));
-+#endif /* defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) */
++	apf28_init_fec();
 +
 +	mx28_device_init();
 +	apf28_device_init();
-+
 +#ifdef CONFIG_MACH_APF28_HAS_BASEBOARD
-+	apf28_baseboard_init();
++	apf28_baseboard_devices_init();
 +#endif
++
++
 +}
 +
 +MACHINE_START(APF28, "Armadeus APF28")
@@ -361,6 +439,74 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/mach-apf28.c
 +	.init_machine	= apf28_init_machine,
 +	.timer		= &mx28_timer.timer,
 +MACHINE_END
+Index: linux-2.6.35.3.ref/arch/arm/mach-mx28/include/mach/apf28.h
+===================================================================
+--- linux-2.6.35.3.ref/arch/arm/mach-mx28/include/mach/apf28.h
++++ linux-2.6.35.3.ref/arch/arm/mach-mx28/include/mach/apf28.h
+@@ -0,0 +1,63 @@
++/*
++ * Copyright (C) 2012 Armadeus systems
++ *
++ * This program is free software; you can redistribute it and/or modify
++ * it under the terms of the GNU General Public License as published by
++ * the Free Software Foundation; either version 2 of the License, or
++ * (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License along
++ * with this program; if not, write to the Free Software Foundation, Inc.,
++ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
++ */
++
++#ifndef __ASM_ARM_MACH_APF28_H
++#define __ASM_ARM_MACH_APF28_H
++
++#include <mach/pinctrl.h>
++
++/*
++ * This function initialize the CPU pins used on the base board and shall
++ * be implemented in the base board file (ex. apf28dev.c)
++ * It will be called at startup from mach-apf28.c.
++ */
++extern void __init apf28_baseboard_pins_init(void);
++
++/*
++ * This function initialize the base board specific devices connected to
++ * the board and shall be implemented in the base board file (ex. apf28dev.c)
++ * It will be called at startup from mach-apf28.c.
++ */
++extern void __init apf28_baseboard_devices_init(void);
++
++/*
++ * Base board function to initialize the ethernet FEC1 interface if needed.
++ * This function may be implemented in the base board file if a specific
++ * is required to initialize the FEC1
++ * It will be called at startup from mach-apf28.c.
++ * This function may not be implemented
++ */
++extern int mx287_fec1_gpio_init(void);
++
++/*
++ * Base board can use apf28_init_pin_group() to initialize a set of CPU pins
++ * from a description table.
++ */
++extern void __init apf28_init_pin_group(struct pin_desc *pins, unsigned count);
++
++/*
++ * Base board can implement these 2 functions to add any specific code to put
++ * the ethernet external hardware in low power mode and to wake up the
++ * interface on resume.
++ * These function may not be implemented
++ */
++extern void mx28evk_enet_io_lowerpower_enter(void);
++extern void mx28evk_enet_io_lowerpower_exit(void);
++
++
++#endif /* __ASM_ARM_MACH_APF28_H */
 Index: linux-2.6.35.3/arch/arm/tools/mach-types
 ===================================================================
 --- linux-2.6.35.3.orig/arch/arm/tools/mach-types	2012-01-31 14:28:17.000000000 +0100
diff --git a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
index 233ac93..59bbf36 100644
--- a/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
+++ b/patches/linux/2.6.35/451-armadeus-add_apf28dev_baseboard_support.patch
@@ -45,7 +45,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 ===================================================================
 --- /dev/null	1970-01-01 00:00:00.000000000 +0000
 +++ linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c	2012-02-15 15:51:09.000000000 +0100
-@@ -0,0 +1,539 @@
+@@ -0,0 +1,483 @@
 +/*
 + * Copyright (C) 2012 Armadeus systems
 + *
@@ -73,6 +73,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +#include <linux/err.h>
 +#include <linux/clk.h>
 +#include <linux/delay.h>
++#include <linux/fec.h>
 +#include <linux/gpio_keys.h>
 +#include <linux/input.h>
 +#include <linux/leds.h>
@@ -83,6 +84,7 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +#include <asm/mach-types.h>
 +#include <asm/mach/arch.h>
 +
++#include <mach/apf28.h>
 +#include <mach/hardware.h>
 +#include <mach/device.h>
 +#include <mach/pinctrl.h>
@@ -353,11 +355,8 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.drive = 1,
 +		.pull = 0,
 +	},
-+};
-+
 +#if defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE)\
 +	|| defined(CONFIG_FEC_L2SWITCH)
-+static struct pin_desc apf28dev_eth_pins[] = {
 +	{
 +		.name		= "ENET1_RX_EN",
 +		.id		= PINID_ENET0_CRS,
@@ -419,30 +418,30 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +		.drive		= 1,
 +	},
 +	{
-+		.name		= "PHY1_RESET",
-+		.id		= PINID_LCD_HSYNC,
++		.name		= "ETH1_INT",
++		.id		= PINID_LCD_VSYNC,
 +		.fun		= PIN_GPIO,
 +		.strength	= PAD_4MA,
 +		.voltage	= PAD_3_3V,
 +		.pullup		= 0,
 +		.drive		= 1,
 +		.pull		= 0,
-+		.output		= 1,
-+		.data		= 1,
++		.output		= 0,
 +	},
 +	{
-+		.name		= "ETH1_INT",
-+		.id		= PINID_LCD_VSYNC,
++		.name		= "PHY1_RESET",
++		.id		= PINID_LCD_HSYNC,
 +		.fun		= PIN_GPIO,
 +		.strength	= PAD_4MA,
 +		.voltage	= PAD_3_3V,
 +		.pullup		= 0,
 +		.drive		= 1,
 +		.pull		= 0,
-+		.output		= 0,
++		.output		= 1,
++		.data		= 1,
 +	},
-+};
 +#endif /* defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE).. */
++};
 +
 +#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
 +static struct gpio_keys_button apf28dev_gpio_keys[] = {
@@ -504,87 +503,32 @@ Index: linux-2.6.35.3/arch/arm/mach-mx28/apf28dev.c
 +
 +#if defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE)\
 +	|| defined(CONFIG_FEC_L2SWITCH)
-+extern int apf28_enet0_gpio_init(void);
-+extern void apf28_enet0_io_lowerpower_enter(void);
-+extern void apf28_enet0_io_lowerpower_exit(void);
-+
-+int mx28evk_enet_gpio_init(void)
++int mx287_fec1_gpio_init(void)
 +{
-+	/* reset phy */
-+	apf28_enet0_gpio_init();
-+
++	/* reset 2nd phy */
 +	gpio_direction_output(MXS_PIN_TO_GPIO(PINID_LCD_HSYNC), 0);
-+
 +	udelay(100);
 +	gpio_direction_output(MXS_PIN_TO_GPIO(PINID_LCD_HSYNC), 1);
 +
 +	return 0;
 +}
++#endif /* defined(CONFIG_FEC) || defined(CONFIG_FEC_MODULE) */
 +
-+void mx28evk_enet_io_lowerpower_enter(void)
-+{
-+	int i;
-+
-+	apf28_enet0_io_lowerpower_enter();
-+
-+	for (i = 0; i < ARRAY_SIZE(apf28dev_eth_pins); i++) {
-+		mxs_release_pin(apf28dev_eth_pins[i].id,
-+			apf28dev_eth_pins[i].name);
-+		gpio_request(MXS_PIN_TO_GPIO(apf28dev_eth_pins[i].id),
-+			apf28dev_eth_pins[i].name);
-+		gpio_direction_output(
-+			MXS_PIN_TO_GPIO(apf28dev_eth_pins[i].id), 0);
-+	}
-+}
 +
-+void mx28evk_enet_io_lowerpower_exit(void)
++void __init apf28_baseboard_pins_init(void)
 +{
-+	int i;
-+
-+	apf28_enet0_io_lowerpower_exit();
-+
-+	for (i = 0; i < ARRAY_SIZE(apf28dev_eth_pins); i++) {
-+		gpio_free(MXS_PIN_TO_GPIO(apf28dev_eth_pins[i].id));
-+		if (apf28dev_eth_pins[i].fun != PIN_GPIO)
-+			mxs_request_pin(apf28dev_eth_pins[i].id,
-+				apf28dev_eth_pins[i].fun,
-+				apf28dev_eth_pins[i].name);
-+		else {
-+			gpio_request(MXS_PIN_TO_GPIO(apf28dev_eth_pins[i].id),
-+				apf28dev_eth_pins[i].name);
-+			if (apf28dev_eth_pins[i].output)
-+				gpio_direction_output(
-+					MXS_PIN_TO_GPIO(apf28dev_eth_pins[i].id),
-+					apf28dev_eth_pins[i].data);
-+			else
-+				gpio_direction_input(
-+					MXS_PIN_TO_GPIO(apf28dev_eth_pins[i].id));
-+		}
-+	}
++	printk("--- apf28_baseboard_init %d\n", MXS_PIN_TO_GPIO(PINID_PWM3));
++
++	apf28_init_pin_group(apf28dev_fixed_pins, ARRAY_SIZE(apf28dev_fixed_pins));
 +}
-+#endif /* defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE).. */
 +
-+static void __init apf28dev_device_init(void)
++void __init apf28_baseboard_devices_init(void)
 +{
 +	/* Add apf28dev special code */
 +	platform_add_devices(apf28dev_platform_devices, ARRAY_SIZE(apf28dev_platform_devices));
 +}
 +
-+extern void __init apf28_init_pin_group(struct pin_desc *pins, unsigned count);
 +
-+void __init apf28_baseboard_init(void)
-+{
-+	printk("--- apf28_baseboard_init %d\n", MXS_PIN_TO_GPIO(PINID_PWM3));
-+
-+	apf28_init_pin_group(apf28dev_fixed_pins, ARRAY_SIZE(apf28dev_fixed_pins));
-+
-+#if defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE)\
-+	|| defined(CONFIG_FEC_L2SWITCH)
-+	apf28_init_pin_group(apf28dev_eth_pins, ARRAY_SIZE(apf28dev_eth_pins));
-+#endif /* defined(CONFIG_FEC2) || defined(CONFIG_FEC2_MODULE).. */
-+
-+	apf28dev_device_init();
-+}
 Index: linux-2.6.35.3/drivers/video/mxs/Kconfig
 ===================================================================
 --- linux-2.6.35.3.orig/drivers/video/mxs/Kconfig	2012-02-15 14:42:20.000000000 +0100


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armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-321-g61c43fb

From: jorasse <jo...@us...> - 2012-05-23 20:40:28

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  61c43fbb986e9eadc10e11f56de77532456cc0de (commit)
       via  d9d695754213c163541026d61e850e376641888d (commit)
       via  1d55a43d5126fb835d4fee36d5abe089f2393d5b (commit)
       via  d03bceb458e4fc6eac59e43e5d9f0a08cf1a0953 (commit)
      from  dd32f586e22a4c3659d1327101d2ad6b9bd12f21 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 61c43fbb986e9eadc10e11f56de77532456cc0de
Author: Eric Jarrige <eri...@ar...>
Date:   Wed May 23 22:40:16 2012 +0200

    [UBOOT] apf9328: update patch version to 5.2

commit d9d695754213c163541026d61e850e376641888d
Author: Eric Jarrige <eri...@ar...>
Date:   Wed May 23 22:38:54 2012 +0200

    [UBOOT] apf51: update patch version to 1.1

commit 1d55a43d5126fb835d4fee36d5abe089f2393d5b
Author: Eric Jarrige <eri...@ar...>
Date:   Wed May 23 22:36:34 2012 +0200

    [UBOOT] apf28: update patch version and environment variables to 1.0

commit d03bceb458e4fc6eac59e43e5d9f0a08cf1a0953
Author: Eric Jarrige <eri...@ar...>
Date:   Wed May 23 22:35:15 2012 +0200

    [UBOOT] apf27/PPS: update patch version to 3.1

-----------------------------------------------------------------------

Summary of changes:
 .../device/armadeus/apf27/apf27-u-boot-2011.12.h   |    2 +-
 .../device/armadeus/apf28/apf28-u-boot-2011.12.h   |    4 ++--
 .../device/armadeus/apf51/apf51-u-boot-2011.12.h   |    2 +-
 .../armadeus/apf9328/apf9328-u-boot-2011.12.h      |    2 +-
 .../device/armadeus/pps/pps-u-boot-2011.12.h       |    2 +-
 5 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
index 8428fbb..ead5231 100644
--- a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
+++ b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
@@ -25,7 +25,7 @@
 
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_ENV_VERSION 	"3.0"
-#define CONFIG_IDENT_STRING	" apf27 patch 3.0"
+#define CONFIG_IDENT_STRING	" apf27 patch 3.1"
 #define CONFIG_BOARD_NAME	apf27
 
 /*
diff --git a/buildroot/target/device/armadeus/apf28/apf28-u-boot-2011.12.h b/buildroot/target/device/armadeus/apf28/apf28-u-boot-2011.12.h
index c9e46b1..5da1a50 100644
--- a/buildroot/target/device/armadeus/apf28/apf28-u-boot-2011.12.h
+++ b/buildroot/target/device/armadeus/apf28/apf28-u-boot-2011.12.h
@@ -25,8 +25,8 @@
 #include <asm/arch/regs-base.h>
 
 #define CONFIG_VERSION_VARIABLE
-#define CONFIG_ENV_VERSION 	"0.8"
-#define CONFIG_IDENT_STRING	" apf28 patch 0.8"
+#define CONFIG_ENV_VERSION 	"1.0"
+#define CONFIG_IDENT_STRING	" apf28 patch 1.0"
 #define CONFIG_BOARD_NAME	apf28
 
 /*
diff --git a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2011.12.h b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2011.12.h
index c6f3261..270b910 100644
--- a/buildroot/target/device/armadeus/apf51/apf51-u-boot-2011.12.h
+++ b/buildroot/target/device/armadeus/apf51/apf51-u-boot-2011.12.h
@@ -25,7 +25,7 @@
 
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_ENV_VERSION 	"1.0"
-#define CONFIG_IDENT_STRING	" apf51 patch 1.0"
+#define CONFIG_IDENT_STRING	" apf51 patch 1.1"
 #define CONFIG_BOARD_NAME	apf51
 
 /*
diff --git a/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2011.12.h b/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2011.12.h
index 2f1f0b8..f0c6def 100644
--- a/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2011.12.h
+++ b/buildroot/target/device/armadeus/apf9328/apf9328-u-boot-2011.12.h
@@ -24,7 +24,7 @@
 
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_ENV_VERSION 	"5.1"
-#define CONFIG_IDENT_STRING	" apf9328 patch 5.1"
+#define CONFIG_IDENT_STRING	" apf9328 patch 5.2"
 #define CONFIG_BOARD_NAME	apf9328
 
 /*
diff --git a/buildroot/target/device/armadeus/pps/pps-u-boot-2011.12.h b/buildroot/target/device/armadeus/pps/pps-u-boot-2011.12.h
index 19da50f..a5f399e 100644
--- a/buildroot/target/device/armadeus/pps/pps-u-boot-2011.12.h
+++ b/buildroot/target/device/armadeus/pps/pps-u-boot-2011.12.h
@@ -25,7 +25,7 @@
 
 #define CONFIG_VERSION_VARIABLE
 #define CONFIG_ENV_VERSION 	"3.0"
-#define CONFIG_IDENT_STRING	" pps patch 3.0"
+#define CONFIG_IDENT_STRING	" pps patch 3.1"
 #define CONFIG_BOARD_NAME	pps
 
 /*


hooks/post-receive
-- 
armadeus

[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-317-gdd32f58

From: jscheer <js...@us...> - 2012-05-23 13:11:19

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".

The branch, master has been updated
       via  dd32f586e22a4c3659d1327101d2ad6b9bd12f21 (commit)
      from  6783f97581a28c6e5bdb2efb9b828cba54e2ad5e (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit dd32f586e22a4c3659d1327101d2ad6b9bd12f21
Author: Jeremie Scheer <jer...@ar...>
Date:   Wed May 23 15:10:56 2012 +0200

    [DEMOS] Fix Qt build & mkspecs directory paths in ApfDacClientServer's build.sh.

-----------------------------------------------------------------------

Summary of changes:
 software/demos/ApfDacClientServer/src/build.sh |    6 +++---
 1 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/software/demos/ApfDacClientServer/src/build.sh b/software/demos/ApfDacClientServer/src/build.sh
index 3cde296..642f9cf 100755
--- a/software/demos/ApfDacClientServer/src/build.sh
+++ b/software/demos/ApfDacClientServer/src/build.sh
@@ -2,7 +2,7 @@
 
 export INITIALPATH=$PATH
 . ../../../../armadeus_env.sh
-ARMADEUS_QTE_DIR=$ARMADEUS_BUILD_DIR/qt-embedded-linux-opensource-src-4.4.3
+ARMADEUS_QTE_DIR=$ARMADEUS_QT_DIR
 
 if [ -d "$ARMADEUS_QTE_DIR" ]; then
 	echo "building the demos for 3 targets......"
@@ -88,7 +88,7 @@ export OUTPUT_DIR=../../bin/apf
 #export QTDIR=$ARMADEUS_ROOTFS_DIR/qt/qtopia.4.2.0/
 export QTDIR=$ARMADEUS_QTE_DIR
 ## due to some installation problems.... I use a custom qmake spec
-export QMAKESPEC=../../QtopiaMkspec/linux-arm-g++/
+export QMAKESPEC=$ARMADEUS_BUILDROOT_DIR/output/host/usr/mkspecs/qws/linux-arm-g++
 export PATH=$ARMADEUS_TOOLCHAIN_PATH:$QTDIR/bin:$INITIALPATH
 
 buildForEnvironment "APF board" $1
@@ -98,7 +98,7 @@ buildForEnvironment "APF board" $1
 
 export OUTPUT_DIR=../../bin/qvbf
 #export QTDIR=$ARMADEUS_ROOTFS_DIR/qt/qvfb/
-export QTDIR=/usr/local/Trolltech/QtEmbedded-4.4.1/
+export QTDIR=/usr/local/Trolltech/QtEmbedded-4.7.2/
 export QMAKESPEC=$QTDIR/mkspecs/linux-g++
 export QMAKEPATH=$QTDIR
 export PATH=$QTDIR/bin:$INITIALPATH


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