[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-327-g011d922
Brought to you by:
sszy
Menu
▾
▴
[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-327-g011d922
|
From: jorasse <jo...@us...> - 2012-05-25 08:36:19
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 011d922a72c5ace5c70e1318aa52c744eaa242ca (commit)
from 5c77e77f384345fc422f25039d3af59a32c69fd9 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 011d922a72c5ace5c70e1318aa52c744eaa242ca
Author: Eric Jarrige <eri...@ar...>
Date: Fri May 25 10:35:48 2012 +0200
[UBOOT] 2012.04: apf27: make SDRAM init code generic for all hardware configuration (1 and 2 memory banks)
-----------------------------------------------------------------------
Summary of changes:
...f27-u-boot-2011.12.h => apf27-u-boot-2012.04.h} | 4 +-
...-Add-support-for-the-armadeus-apf27-board.patch | 44 +++++++++-----------
2 files changed, 22 insertions(+), 26 deletions(-)
copy buildroot/target/device/armadeus/apf27/{apf27-u-boot-2011.12.h => apf27-u-boot-2012.04.h} (99%)
diff --git a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.04.h
similarity index 99%
copy from buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
copy to buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.04.h
index ead5231..0c06421 100644
--- a/buildroot/target/device/armadeus/apf27/apf27-u-boot-2011.12.h
+++ b/buildroot/target/device/armadeus/apf27/apf27-u-boot-2012.04.h
@@ -25,7 +25,7 @@
#define CONFIG_VERSION_VARIABLE
#define CONFIG_ENV_VERSION "3.0"
-#define CONFIG_IDENT_STRING " apf27 patch 3.1"
+#define CONFIG_IDENT_STRING " apf27 patch 3.2"
#define CONFIG_BOARD_NAME apf27
/*
@@ -100,7 +100,7 @@
* Memory configurations
*/
#define CONFIG_NR_DRAM_POPULATED 1
-#define CONFIG_NR_DRAM_BANKS CONFIG_NR_DRAM_POPULATED
+#define CONFIG_NR_DRAM_BANKS 2
#define CONFIG_SYS_SDRAM_MBYTE_SYZE 64
diff --git a/patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch b/patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch
index b3601e5..10753da 100644
--- a/patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch
+++ b/patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch
@@ -279,7 +279,7 @@ index 0000000..1f1bd42
+ /* dram_init must store complete ramsize in gd->ram_size */
+ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
+ PHYS_SDRAM_1_SIZE);
-+#if ( CONFIG_NR_DRAM_BANKS > 1 )
++#if ( CONFIG_NR_DRAM_POPULATED > 1 )
+ gd->ram_size += get_ram_size((void *)PHYS_SDRAM_2,
+ PHYS_SDRAM_2_SIZE);
+#endif
@@ -289,7 +289,7 @@ index 0000000..1f1bd42
+void dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
-+ gd->bd->bi_dram[0].size = gd->ram_size / CONFIG_NR_DRAM_BANKS;
++ gd->bd->bi_dram[0].size = gd->ram_size / CONFIG_NR_DRAM_POPULATED;
+#if ( CONFIG_NR_DRAM_BANKS > 1 )
+ gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
+ gd->bd->bi_dram[1].size = gd->ram_size -gd->bd->bi_dram[0].size;
@@ -738,7 +738,7 @@ new file mode 100644
index 0000000..a6bbbc1
--- /dev/null
+++ b/board/armadeus/apf27/lowlevel_init.S
-@@ -0,0 +1,277 @@
+@@ -0,0 +1,275 @@
+/*
+ * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
+ * Applications Processor Reference Manual, Rev. 0.2".
@@ -859,7 +859,7 @@ index 0000000..a6bbbc1
+
+ /* writeb(0xA0001000, any value) */
+ ldr r1, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
-+ ldrb r2, [r1]
++ strb r2, [r1]
+
+ /* writel(ESDCTL0, CONFIG_SYS_AUTOREFRESH_CMD) */
+ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
@@ -868,7 +868,7 @@ index 0000000..a6bbbc1
+ ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
+
+ ldr r6,=0x7 /* load loop counter */
-+1: ldr r5,[r4] /* run auto-refresh cycle to array 0 */
++1: str r5,[r4] /* run auto-refresh cycle to array 0 */
+ subs r6,r6,#1 /* decrease counter value */
+ bne 1b
+
@@ -878,17 +878,16 @@ index 0000000..a6bbbc1
+
+ /* set standard mode register */
+ ldr r4, = PHYS_SDRAM_1+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
-+ ldrb r2, [r4]
++ strb r2, [r4]
+
+ /* set extended mode register */
+ ldr r4, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
-+ ldrb r5, [r4]
++ strb r5, [r4]
+
+ /* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_NORMAL_RW_CMD) */
+ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
+ str r1, [r0, #ESDCTL0_ROF]
+
-+#if (CONFIG_NR_DRAM_BANKS > 1)
+ /* 2nd sdram */
+ /* write32 ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL */
+ ldr r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL
@@ -900,7 +899,7 @@ index 0000000..a6bbbc1
+
+ /* writeb(0xB0001000, any value) */
+ ldr r1, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
-+ ldrb r2, [r1]
++ strb r2, [r1]
+
+ /* writel(ESDCTL1, CONFIG_SYS_AUTOREFRESH_CMD) */
+ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
@@ -909,7 +908,7 @@ index 0000000..a6bbbc1
+ ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
+
+ ldr r6,=0x7 /* load loop counter */
-+1: ldr r5,[r4] /* run auto-refresh cycle to array 0 */
++1: str r5,[r4] /* run auto-refresh cycle to array 0 */
+ subs r6,r6,#1 /* decrease counter value */
+ bne 1b
+
@@ -919,16 +918,15 @@ index 0000000..a6bbbc1
+
+ /* set standard mode register */
+ ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
-+ ldrb r2, [r4]
++ strb r2, [r4]
+
+ /* set extended mode register */
+ ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
-+ ldrb r2, [r4]
++ strb r2, [r4]
+
+ /* writel(ESDCTL1, CONFIG_SYS_NORMAL_RW_CMD) */
+ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
+ str r1, [r0, #ESDCTL1_ROF]
-+#endif /* CONFIG_NR_DRAM_BANKS > 1 */
+.endm /* sdram_init */
+
+.globl board_init_lowlevel
@@ -1165,7 +1163,7 @@ new file mode 100644
index 0000000..c8f158d
--- /dev/null
+++ b/nand_spl/board/armadeus/apf27/start.S
-@@ -0,0 +1,552 @@
+@@ -0,0 +1,550 @@
+/*
+ * IMX27 NAND Flash SPL (Secondary Program Loader)
+ *
@@ -1643,7 +1641,7 @@ index 0000000..c8f158d
+
+ /* writeb(0xA0001000, any value) */
+ ldr r1, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
-+ ldrb r2, [r1]
++ strb r2, [r1]
+
+ /* writel(ESDCTL0, CONFIG_SYS_AUTOREFRESH_CMD) */
+ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
@@ -1652,7 +1650,7 @@ index 0000000..c8f158d
+ ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
+
+ ldr r6,=0x7 /* load loop counter */
-+1: ldr r5,[r4] /* run auto-refresh cycle to array 0 */
++1: str r5,[r4] /* run auto-refresh cycle to array 0 */
+ subs r6,r6,#1 /* decrease counter value */
+ bne 1b
+
@@ -1662,17 +1660,16 @@ index 0000000..c8f158d
+
+ /* set standard mode register */
+ ldr r4, = PHYS_SDRAM_1+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
-+ ldrb r2, [r4]
++ strb r2, [r4]
+
+ /* set extended mode register */
+ ldr r4, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
-+ ldrb r5, [r4]
++ strb r5, [r4]
+
+ /* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_NORMAL_RW_CMD) */
+ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
+ str r1, [r0, #ESDCTL0_ROF]
+
-+#if (CONFIG_NR_DRAM_BANKS > 1)
+ /* 2nd sdram */
+ /* writel(ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL ) */
+ ldr r0, =IMX_ESD_BASE
@@ -1686,7 +1683,7 @@ index 0000000..c8f158d
+
+ /* writeb(0xB0001000, any value) */
+ ldr r1, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
-+ ldrb r2, [r1]
++ strb r2, [r1]
+
+ /* writel(ESDCTL1, CONFIG_SYS_AUTOREFRESH_CMD) */
+ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
@@ -1695,7 +1692,7 @@ index 0000000..c8f158d
+ ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
+
+ ldr r6,=0x7 /* load loop counter */
-+1: ldr r5,[r4] /* run auto-refresh cycle to array 0 */
++1: str r5,[r4] /* run auto-refresh cycle to array 0 */
+ subs r6,r6,#1 /* decrease counter value */
+ bne 1b
+
@@ -1705,16 +1702,15 @@ index 0000000..c8f158d
+
+ /* set standard mode register */
+ ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
-+ ldrb r2, [r4]
++ strb r2, [r4]
+
+ /* set extended mode register */
+ ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
-+ ldrb r2, [r4]
++ strb r2, [r4]
+
+ /* writel(ESDCTL1, CONFIG_SYS_NORMAL_RW_CMD) */
+ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
+ str r1, [r0, #ESDCTL1_ROF]
-+#endif /* CONFIG_NR_DRAM_BANKS > 1 */
+
+ mov pc, lr
+
hooks/post-receive
--
armadeus
|
