[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-324-gfca486f
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-324-gfca486f
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From: jorasse <jo...@us...> - 2012-05-24 22:28:23
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via fca486ff69b21ad09f4bfa754da289da03cdb444 (commit)
from fc8e6ec67b11887a524097e29c50b90460fe25f4 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit fca486ff69b21ad09f4bfa754da289da03cdb444
Author: Eric Jarrige <eri...@ar...>
Date: Fri May 25 00:28:08 2012 +0200
[UBOOT] (Preliminary) Update U-Boot patch to U-Boot 2012.04 - Thx Trem
-----------------------------------------------------------------------
Summary of changes:
patches/u-boot/2012.04/101-mx1-gpio-mode.patch | 31 +
patches/u-boot/2012.04/102-mx1-i2c.patch | 46 +
patches/u-boot/2012.04/103-apf9328.patch | 1359 +++++++++++++++
patches/u-boot/2012.04/104-apf9328-makefile.patch | 41 +
patches/u-boot/2012.04/106-mx1-pllclk.patch | 63 +
patches/u-boot/2012.04/107-mx1-pllclk-debug.patch | 26 +
patches/u-boot/2012.04/108-DM9000.patch | 48 +
patches/u-boot/2012.04/109-mx1-relocation.patch | 33 +
patches/u-boot/2012.04/111-mx1-timer.patch | 25 +
...dule-and-I-O-Multiplexer-constant-for-mx2.patch | 156 ++
...-Add-support-for-the-armadeus-apf27-board.patch | 1766 ++++++++++++++++++++
.../u-boot/2012.04/311-imx-nand-lock-unlock.patch | 93 +
patches/u-boot/2012.04/320-spartan.patch | 45 +
patches/u-boot/2012.04/321-add_spartan6.patch | 761 +++++++++
patches/u-boot/2012.04/330-arm926-relocation.patch | 32 +
.../u-boot/2012.04/340-apf27-misc-commands.patch | 379 +++++
.../2012.04/350-nand_large_file_download.patch | 235 +++
patches/u-boot/2012.04/400-imx51.patch | 510 ++++++
patches/u-boot/2012.04/401-apf51.patch | 1624 ++++++++++++++++++
patches/u-boot/2012.04/403-apf51-wdog.patch | 29 +
.../u-boot/2012.04/405-remove_extra_printk.patch | 36 +
patches/u-boot/2012.04/407-imx51-nand.patch | 1390 +++++++++++++++
patches/u-boot/2012.04/409-apf51-nand-spl.patch | 407 +++++
patches/u-boot/2012.04/410-imx-iim.patch | 547 ++++++
.../2012.04/411-Fix-high-voltage-nand-sd.patch | 24 +
...c_i2c-add_support_for_the_iMX51_processor.patch | 26 +
patches/u-boot/2012.04/425-cortex-relocation.patch | 32 +
.../u-boot/2012.04/501-imx28-update-and-fix.patch | 80 +
patches/u-boot/2012.04/502-add-apf28.patch | 1407 ++++++++++++++++
.../503-imx28-fix_spl_power_init_IRQ_bit.patch | 38 +
30 files changed, 11289 insertions(+), 0 deletions(-)
create mode 100644 patches/u-boot/2012.04/101-mx1-gpio-mode.patch
create mode 100644 patches/u-boot/2012.04/102-mx1-i2c.patch
create mode 100644 patches/u-boot/2012.04/103-apf9328.patch
create mode 100644 patches/u-boot/2012.04/104-apf9328-makefile.patch
create mode 100644 patches/u-boot/2012.04/106-mx1-pllclk.patch
create mode 100644 patches/u-boot/2012.04/107-mx1-pllclk-debug.patch
create mode 100644 patches/u-boot/2012.04/108-DM9000.patch
create mode 100644 patches/u-boot/2012.04/109-mx1-relocation.patch
create mode 100644 patches/u-boot/2012.04/111-mx1-timer.patch
create mode 100644 patches/u-boot/2012.04/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
create mode 100644 patches/u-boot/2012.04/302-Add-support-for-the-armadeus-apf27-board.patch
create mode 100644 patches/u-boot/2012.04/311-imx-nand-lock-unlock.patch
create mode 100644 patches/u-boot/2012.04/320-spartan.patch
create mode 100644 patches/u-boot/2012.04/321-add_spartan6.patch
create mode 100644 patches/u-boot/2012.04/330-arm926-relocation.patch
create mode 100644 patches/u-boot/2012.04/340-apf27-misc-commands.patch
create mode 100644 patches/u-boot/2012.04/350-nand_large_file_download.patch
create mode 100644 patches/u-boot/2012.04/400-imx51.patch
create mode 100644 patches/u-boot/2012.04/401-apf51.patch
create mode 100644 patches/u-boot/2012.04/403-apf51-wdog.patch
create mode 100644 patches/u-boot/2012.04/405-remove_extra_printk.patch
create mode 100644 patches/u-boot/2012.04/407-imx51-nand.patch
create mode 100644 patches/u-boot/2012.04/409-apf51-nand-spl.patch
create mode 100644 patches/u-boot/2012.04/410-imx-iim.patch
create mode 100644 patches/u-boot/2012.04/411-Fix-high-voltage-nand-sd.patch
create mode 100644 patches/u-boot/2012.04/424-armadeus-mxc_i2c-add_support_for_the_iMX51_processor.patch
create mode 100644 patches/u-boot/2012.04/425-cortex-relocation.patch
create mode 100644 patches/u-boot/2012.04/501-imx28-update-and-fix.patch
create mode 100644 patches/u-boot/2012.04/502-add-apf28.patch
create mode 100644 patches/u-boot/2012.04/503-imx28-fix_spl_power_init_IRQ_bit.patch
diff --git a/patches/u-boot/2012.04/101-mx1-gpio-mode.patch b/patches/u-boot/2012.04/101-mx1-gpio-mode.patch
new file mode 100644
index 0000000..29af133
--- /dev/null
+++ b/patches/u-boot/2012.04/101-mx1-gpio-mode.patch
@@ -0,0 +1,31 @@
+mx1: export imx_gpio_mode() function
+
+Add imx_gpio_mode() to Freescale imx1/L/S public functions
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Stefano Babic <sb...@de...>
+---
+ arch/arm/include/asm/arch-imx/imx-regs.h | 7 +++++++
+ 1 files changed, 7 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch-imx/imx-regs.h b/arch/arm/include/asm/arch-imx/imx-regs.h
+index ec94ba9..0c26a36 100644
+--- a/arch/arm/include/asm/arch-imx/imx-regs.h
++++ b/arch/arm/include/asm/arch-imx/imx-regs.h
+@@ -1,5 +1,12 @@
+ #ifndef _IMX_REGS_H
+ #define _IMX_REGS_H
++
++#ifndef __ASSEMBLY__
++
++extern void imx_gpio_mode(int gpio_mode);
++
++#endif /* __ASSEMBLY__ */
++
+ /* ------------------------------------------------------------------------
+ * Motorola IMX system registers
+ * ------------------------------------------------------------------------
+--
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/102-mx1-i2c.patch b/patches/u-boot/2012.04/102-mx1-i2c.patch
new file mode 100644
index 0000000..6919c81
--- /dev/null
+++ b/patches/u-boot/2012.04/102-mx1-i2c.patch
@@ -0,0 +1,46 @@
+mx1: add i2c registers
+
+Add i2c registers for Freescale imx1/L/S
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Stefano Babic <sb...@de...>
+---
+ arch/arm/include/asm/arch-imx/imx-regs.h | 23 +++++++++++++++++++++++
+ 1 files changed, 23 insertions(+), 0 deletions(-)
+
+diff --git a/arch/arm/include/asm/arch-imx/imx-regs.h b/arch/arm/include/asm/arch-imx/imx-regs.h
+index 0c26a36..a7b3404 100644
+--- a/arch/arm/include/asm/arch-imx/imx-regs.h
++++ b/arch/arm/include/asm/arch-imx/imx-regs.h
+@@ -638,4 +638,27 @@ extern void imx_gpio_mode(int gpio_mode);
+ #define TSTAT_CAPT (1<<1) /* Capture event */
+ #define TSTAT_COMP (1) /* Compare event */
+
++/*
++ * I2C module
++ */
++#define IADR __REG(IMX_I2C_BASE + 0x000) /* I2C Address Register */
++#define IFDR __REG(IMX_I2C_BASE + 0x004) /* I2C Frequency Divider Register*/
++#define I2CR __REG(IMX_I2C_BASE + 0x008) /* I2C Control Register */
++#define I2SR __REG(IMX_I2C_BASE + 0x00C) /* I2C Status Register */
++#define I2DR __REG(IMX_I2C_BASE + 0x010) /* I2C Data I/O Register */
++/* I2C Control Register Bit Fields */
++#define I2CR_IEN (1<<7) /* I2C Enable */
++#define I2CR_IIEN (1<<6) /* I2C Interrupt Enable */
++#define I2CR_MSTA (1<<5) /* I2C Master/Slave Mode Select */
++#define I2CR_MTX (1<<4) /* I2C Transmit/Receive Mode Select */
++#define I2CR_TXAK (1<<3) /* I2C Transmit Acknowledge Enable */
++#define I2CR_RSTA (1<<2) /* I2C Repeated START */
++#define I2SR_ICF (1<<7) /* I2C Data Transfer */
++#define I2SR_IAAS (1<<6) /* I2C Addressed As a Slave */
++#define I2SR_IBB (1<<5) /* I2C Bus Busy */
++#define I2SR_IAL (1<<4) /* I2C Arbitration Lost */
++#define I2SR_SRW (1<<2) /* I2C Slave Read/Write */
++#define I2SR_IIF (1<<1) /* I2C interrupt */
++#define I2SR_RXAK (1<<0) /* I2C Received Acknowledge */
++
+ #endif /* _IMX_REGS_H */
+--
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/103-apf9328.patch b/patches/u-boot/2012.04/103-apf9328.patch
new file mode 100644
index 0000000..6897dab
--- /dev/null
+++ b/patches/u-boot/2012.04/103-apf9328.patch
@@ -0,0 +1,1359 @@
+apf9328: Add Armadeus Project board APF9328
+
+Add Armadeus Project board APF9328
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Nicolas Colombain <nic...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Nicolas Colombain <nic...@ar...>
+---
+ board/armadeus/apf9328/Makefile | 51 ++++
+ board/armadeus/apf9328/apf9328.c | 106 +++++++
+ board/armadeus/apf9328/apf9328fpga.c | 101 +++++++
+ board/armadeus/apf9328/apf9328fpga.h | 31 ++
+ board/armadeus/apf9328/eeprom.c | 88 ++++++
+ board/armadeus/apf9328/fpga.c | 121 ++++++++
+ board/armadeus/apf9328/fpga.h | 30 ++
+ board/armadeus/apf9328/i2c.c | 276 +++++++++++++++++++
+ board/armadeus/apf9328/lowlevel_init.S | 469 ++++++++++++++++++++++++++++++++
+ 9 files changed, 1273 insertions(+), 0 deletions(-)
+ create mode 100644 board/armadeus/apf9328/Makefile
+ create mode 100644 board/armadeus/apf9328/apf9328.c
+ create mode 100644 board/armadeus/apf9328/apf9328fpga.c
+ create mode 100644 board/armadeus/apf9328/apf9328fpga.h
+ create mode 100644 board/armadeus/apf9328/eeprom.c
+ create mode 100644 board/armadeus/apf9328/fpga.c
+ create mode 100644 board/armadeus/apf9328/fpga.h
+ create mode 100644 board/armadeus/apf9328/i2c.c
+ create mode 100644 board/armadeus/apf9328/lowlevel_init.S
+
+diff --git a/board/armadeus/apf9328/Makefile b/board/armadeus/apf9328/Makefile
+new file mode 100644
+index 0000000..0f097cd
+--- /dev/null
++++ b/board/armadeus/apf9328/Makefile
+@@ -0,0 +1,51 @@
++#
++# (C) Copyright 2000-2004
++# Wolfgang Denk, DENX Software Engineering, wd...@de....
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++
++LIB = $(obj)lib$(BOARD).o
++
++COBJS := apf9328.o i2c.o apf9328fpga.o fpga.o eeprom.o
++SOBJS := lowlevel_init.o
++
++SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
++OBJS := $(addprefix $(obj),$(COBJS))
++SOBJS := $(addprefix $(obj),$(SOBJS))
++
++$(LIB): $(obj).depend $(OBJS) $(SOBJS)
++ $(call cmd_link_o_target, $(OBJS) $(SOBJS))
++
++clean:
++ rm -f $(SOBJS) $(OBJS)
++
++distclean: clean
++ rm -f $(LIB) core *.bak .depend
++
++#########################################################################
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+diff --git a/board/armadeus/apf9328/apf9328.c b/board/armadeus/apf9328/apf9328.c
+new file mode 100644
+index 0000000..b72491d
+--- /dev/null
++++ b/board/armadeus/apf9328/apf9328.c
+@@ -0,0 +1,106 @@
++/*
++ * (C) Copyright 2005-2011
++ * Nicolas Colombin <th...@us...>
++ * Eric Jarrige <eri...@ar...>
++ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++
++#include <common.h>
++#include <asm/arch/imx-regs.h>
++#include <flash.h>
++#include <netdev.h>
++#include "apf9328fpga.h"
++
++DECLARE_GLOBAL_DATA_PTR;
++
++int board_init(void)
++{
++
++ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
++
++ return 0;
++}
++
++int dram_init(void)
++{
++ /* dram_init must store complete ramsize in gd->ram_size */
++ gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
++ PHYS_SDRAM_1_SIZE);
++ return 0;
++}
++
++#ifndef CONFIG_SYS_DCACHE_OFF
++void enable_caches(void)
++{
++ /* Enable D-cache. I-cache is already enabled in start.S */
++ /*dcache_enable(); fix kernel 2.6.29 boot crash first*/
++}
++#endif
++
++/*
++ * Miscellaneous intialization
++ */
++int misc_init_r(void)
++{
++ char *s;
++
++#ifdef CONFIG_FPGA
++ apf9328_init_fpga();
++#endif
++
++#ifdef CONFIG_DRIVER_DM9000
++ imx_gpio_mode(GPIO_PORTB | GPIO_DR | GPIO_IN | 14);
++#endif
++
++ /* detect compatibility issue of environment version */
++ s = getenv("env_version");
++ if ((NULL == s) || (0 != strcmp(s, CONFIG_ENV_VERSION))) {
++ printf("*** Warning - Environment version change suggests: "
++ "run flash_reset_env; reset\n");
++ }
++
++ return 0;
++}
++
++void show_boot_progress(int status)
++{
++ return;
++}
++
++#ifdef CONFIG_DRIVER_DM9000
++int board_eth_init(bd_t *bis)
++{
++ struct eth_device *dev;
++ unsigned char env_enetaddr[6];
++
++ if (dm9000_initialize(bis) != 0)
++ return -1;
++ if (!eth_getenv_enetaddr("ethaddr", env_enetaddr)) {
++ dev = eth_get_dev_by_index(0);
++ if (dev) {
++ eth_setenv_enetaddr("ethaddr", dev->enetaddr);
++ } else {
++ printf("DM9000 APF9328: Couldn't get eth device\n");
++ return -1;
++ }
++ }
++
++ return 0;
++}
++#endif
+diff --git a/board/armadeus/apf9328/apf9328fpga.c b/board/armadeus/apf9328/apf9328fpga.c
+new file mode 100644
+index 0000000..4c63c4e
+--- /dev/null
++++ b/board/armadeus/apf9328/apf9328fpga.c
+@@ -0,0 +1,101 @@
++/*
++ * (C) Copyright 2005-2011
++ * Nicolas Colombin <th...@us...>
++ * Eric Jarrige <eri...@ar...>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++
++/*
++ * Spartan 3 FPGA configuration support for the APF9328 daughter board
++ */
++
++#include <common.h>
++#include <spartan3.h>
++#include <command.h>
++#include <jffs2/jffs2.h>
++#include <asm/arch/imx-regs.h>
++#include <asm/io.h>
++#include "apf9328fpga.h"
++
++#ifdef CONFIG_FPGA
++DECLARE_GLOBAL_DATA_PTR;
++/* Note that these are pointers to code that is in Flash. They will be
++ * relocated at runtime.
++ * Spartan3 code is used to download our Spartan 3 :) code is compatible.
++ * Just take care about the file size
++*/
++Xilinx_Spartan3_Slave_Serial_fns fpga_fns = {
++ fpga_pre_fn,
++ fpga_pgm_fn,
++ fpga_clk_fn,
++ fpga_init_fn,
++ fpga_done_fn,
++ fpga_wr_fn,
++};
++
++Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
++ {Xilinx_Spartan3,
++ slave_serial,
++ XILINX_XC3S400_SIZE,
++ (void *)&fpga_fns,
++ 0}
++};
++
++/*
++ * Initialize the fpga. Return 1 on success, 0 on failure.
++ */
++int apf9328_init_fpga(void)
++{
++ char *autoload = getenv("firmware_autoload");
++ int i, lout = 1;
++ u8 pnum;
++ struct mtd_device *dev;
++ struct part_info *part;
++
++ debug("%s:%d: Initialize FPGA interface (relocation offset= 0x%.8lx)\n",
++ __func__, __LINE__, gd->reloc_off);
++
++ fpga_init();
++
++ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
++ debug("%s:%d: Adding fpga %d\n", __func__, __LINE__, i);
++ fpga_add(fpga_xilinx, &fpga[i]);
++ }
++
++ if ((autoload) && (0 == strcmp(autoload, "1"))) {
++ if (mtdparts_init() == 0)
++ if (find_dev_and_part("firmware", &dev, &pnum, &part) == 0)
++ {
++ if (ctrlc()) {
++ printf("Firmware download stopped!\n");
++ lout = 0;
++ } else if (FPGA_SUCCESS != fpga_load(0,
++ (void *)part->offset,
++ (size_t)part->size)) {
++ lout = 0;
++ printf("Firmware not loaded!\n");
++ }
++ }
++ }
++ return lout;
++}
++
++#endif /* CONFIG_FPGA */
+diff --git a/board/armadeus/apf9328/apf9328fpga.h b/board/armadeus/apf9328/apf9328fpga.h
+new file mode 100644
+index 0000000..2a15443
+--- /dev/null
++++ b/board/armadeus/apf9328/apf9328fpga.h
+@@ -0,0 +1,31 @@
++/*
++ * (C) Copyright 2002
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++
++/*
++ * Spartan 3 FPGA configuration support for the APF9328 daughter board
++ */
++
++#include "fpga.h"
++extern int apf9328_init_fpga(void);
+diff --git a/board/armadeus/apf9328/eeprom.c b/board/armadeus/apf9328/eeprom.c
+new file mode 100644
+index 0000000..8f2ad9a
+--- /dev/null
++++ b/board/armadeus/apf9328/eeprom.c
+@@ -0,0 +1,88 @@
++/*
++ * (C) Copyright 2008-2011 Armadeus Project
++ * (C) Copyright 2007
++ * Stefano Babic, DENX Software Engineering, sb...@de....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#include <common.h>
++#include <command.h>
++#include <dm9000.h>
++
++static int do_read_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc,
++ char * const argv[])
++{
++ unsigned int i;
++ u8 data[2];
++
++ for (i = 0; i < 0x40; i++) {
++ if (!(i % 0x10))
++ printf("\n%08x:", i);
++ dm9000_read_srom_word(i, data);
++ printf(" %02x%02x", data[1], data[0]);
++ }
++ printf("\n");
++ return 0;
++}
++
++static int do_write_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc,
++ char * const argv[])
++{
++ unsigned long offset, value;
++
++ if (argc < 4) {
++ cmd_usage(cmdtp);
++ return 1;
++ }
++
++ strict_strtoul(argv[2], 16, &offset);
++ strict_strtoul(argv[3], 16, &value);
++ if (offset > 0x40) {
++ printf("Wrong offset : 0x%lx\n", offset);
++ cmd_usage(cmdtp);
++ return 1;
++ }
++ dm9000_write_srom_word(offset, value);
++ return 0;
++}
++
++int do_dm9000_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
++{
++ if (argc < 2) {
++ cmd_usage(cmdtp);
++ return 1;
++ }
++
++ if (strcmp(argv[1], "read") == 0) {
++ return do_read_dm9000_eeprom(cmdtp, flag, argc, argv);
++ } else if (strcmp(argv[1], "write") == 0) {
++ return do_write_dm9000_eeprom(cmdtp, flag, argc, argv);
++ } else {
++ cmd_usage(cmdtp);
++ return 1;
++ }
++}
++
++U_BOOT_CMD(dm9000ee, 4, 1, do_dm9000_eeprom,
++ "Read/Write eeprom connected to Ethernet Controller",
++ "\ndm9000ee write <word offset> <value> \n"
++ "\tdm9000ee read \n"
++ "\tword:\t\t00-02 : MAC Address\n"
++ "\t\t\t03-07 : DM9000 Configuration\n" "\t\t\t08-63 : User data");
+diff --git a/board/armadeus/apf9328/fpga.c b/board/armadeus/apf9328/fpga.c
+new file mode 100644
+index 0000000..f3d4f03
+--- /dev/null
++++ b/board/armadeus/apf9328/fpga.c
+@@ -0,0 +1,121 @@
++/*
++ * (C) Copyright 2002
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++#include <common.h>
++
++#ifdef CONFIG_FPGA
++
++#include <asm/arch/imx-regs.h>
++#include <asm/io.h>
++#include <config.h>
++
++#define GPIO_PORT(x) ((x >> 5) & 3)
++#define GPIO_SET(x) (DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK)))
++#define GPIO_CLEAR(x) (DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK)))
++#define GPIO_WRITE(x, y) (y ? GPIO_SET(x) : GPIO_CLEAR(x))
++#define GPIO_READ(x) ((SSR(GPIO_PORT(x)) & (1<<(x & GPIO_PIN_MASK))))
++
++/*
++ * Port bit numbers for the serial slave controls
++ */
++#define FPGA_INIT CONFIG_SYS_FPGA_INIT
++#define FPGA_DONE CONFIG_SYS_FPGA_DONE
++#define FPGA_DIN CONFIG_SYS_FPGA_DATA
++#define FPGA_PROGRAM CONFIG_SYS_FPGA_PRG
++#define FPGA_CLOCK CONFIG_SYS_FPGA_CLK
++
++/* Note that these are pointers to code that is in Flash. They will be
++ * relocated at runtime.
++ * Spartan2 code is used to download our Spartan 3 :) code is compatible.
++ * Just take care about the file size
++*/
++
++/*
++ * nitialize GPIO port B before download
++ */
++int fpga_pre_fn(int cookie)
++{
++ debug("%s:%d: FPGA PRE ", __func__, __LINE__);
++
++ /* Initialize GPIO pins */
++ imx_gpio_mode(FPGA_INIT | GPIO_DR | GPIO_IN);
++ imx_gpio_mode(FPGA_DONE | GPIO_DR | GPIO_IN);
++ imx_gpio_mode(FPGA_DIN | GPIO_DR | GPIO_OUT);
++ imx_gpio_mode(FPGA_PROGRAM | GPIO_DR | GPIO_OUT);
++ imx_gpio_mode(FPGA_CLOCK | GPIO_DR | GPIO_OUT);
++ return cookie;
++}
++
++/*
++ * Set the FPGA's active-low program line to the specified level
++ */
++int fpga_pgm_fn(int assert, int flush, int cookie)
++{
++ debug("%s:%d: FPGA PROGRAM %s", __func__, __LINE__,
++ assert ? "high" : "low");
++ GPIO_WRITE(FPGA_PROGRAM, !assert);
++ return assert;
++}
++
++/*
++ * Set the FPGA's active-high clock line to the specified level
++ */
++int fpga_clk_fn(int assert_clk, int flush, int cookie)
++{
++ debug("%s:%d: FPGA CLOCK %s", __func__, __LINE__,
++ assert_clk ? "high" : "low");
++ GPIO_WRITE(FPGA_CLOCK, assert_clk);
++ return assert_clk;
++}
++
++/*
++ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
++ * asserted (low).
++ */
++int fpga_init_fn(int cookie)
++{
++ debug("%s:%d: INIT check... ", __func__, __LINE__);
++ return !GPIO_READ(FPGA_INIT);
++}
++
++/*
++ * Test the state of the active-high FPGA DONE pin
++ */
++int fpga_done_fn(int cookie)
++{
++ debug("%s:%d: DONE check... ", __func__, __LINE__);
++ return GPIO_READ(FPGA_DONE);
++}
++
++/*
++ * Set the FPGA's data line to the specified level
++ */
++int fpga_wr_fn(int assert_write, int flush, int cookie)
++{
++ debug("%s:%d: DATA write... ", __func__, __LINE__);
++ GPIO_WRITE(FPGA_DIN, assert_write);
++ return assert_write;
++}
++
++#endif /* CONFIG_FPGA */
+diff --git a/board/armadeus/apf9328/fpga.h b/board/armadeus/apf9328/fpga.h
+new file mode 100644
+index 0000000..3b226d7
+--- /dev/null
++++ b/board/armadeus/apf9328/fpga.h
+@@ -0,0 +1,30 @@
++/*
++ * (C) Copyright 2002
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++extern int fpga_pre_fn(int cookie);
++extern int fpga_pgm_fn(int assert_pgm, int flush, int cookie);
++extern int fpga_init_fn(int cookie);
++extern int fpga_done_fn(int cookie);
++extern int fpga_clk_fn(int assert_clk, int flush, int cookie);
++extern int fpga_wr_fn(int assert_write, int flush, int cookie);
+diff --git a/board/armadeus/apf9328/i2c.c b/board/armadeus/apf9328/i2c.c
+new file mode 100644
+index 0000000..0ba0a8d
+--- /dev/null
++++ b/board/armadeus/apf9328/i2c.c
+@@ -0,0 +1,276 @@
++/*
++ * (C) Copyright 2005-2011 ej Armadeus Project <eri...@ar...>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ *
++ */
++
++#include <common.h>
++
++#ifdef CONFIG_HARD_I2C
++
++#include <asm/io.h>
++#include <asm/arch/imx-regs.h>
++#include <i2c.h>
++
++/*-----------------------------------------------------------------------
++ * Definitions
++ */
++
++#define I2C_ACK 0 /* level to ack a byte */
++#define I2C_NOACK 1 /* level to noack a byte */
++
++/*-----------------------------------------------------------------------
++ * Local functions
++ */
++
++/*-----------------------------------------------------------------------
++ * START: High -> Low on SDA while SCL is High
++ * after check for a bus free
++ */
++static void imxi2c_send_start(void)
++{
++ while (I2SR & I2SR_IBB)
++ udelay(1);
++
++ I2CR |= I2CR_MSTA;
++ I2SR &= ~I2SR_IIF;
++}
++
++/*-----------------------------------------------------------------------
++ * STOP: Low -> High on SDA while SCL is High
++ * after the end of previous transfer
++ */
++static void imxi2c_send_stop(void)
++{
++ while (!(I2SR & I2SR_ICF))
++ udelay(1);
++
++ I2CR &= ~I2CR_MSTA;
++}
++
++/*-----------------------------------------------------------------------
++ * Send 8 bits and look for an acknowledgement.
++ */
++static int imxi2c_write_byte(uchar data)
++{
++ while (!(I2SR & I2SR_ICF)) /* Wait end of transfer */
++ udelay(1);
++
++ I2CR |= I2CR_MTX;
++ I2SR &= ~I2SR_IIF;
++ I2DR = data;
++
++ while (!(I2SR & I2SR_IIF)) /* checking IIF before ICF: FIXME */
++ udelay(1);
++
++ I2SR &= ~I2SR_IIF;
++
++ while (!(I2SR & I2SR_ICF)) /* Wait end of transfer */
++ udelay(1);
++
++ return I2SR & I2SR_RXAK; /* not a nack is an ack */
++}
++
++/*-----------------------------------------------------------------------
++ * if ack == I2C_ACK, ACK the byte so can continue reading, else
++ * send I2C_NOACK to end the read.
++ */
++static uchar imxi2c_read_byte(int ack)
++{
++ int data;
++
++ while (!(I2SR & I2SR_ICF))
++ udelay(1);
++
++ I2CR &= ~I2CR_MTX;
++
++ if (ack)
++ I2CR |= I2CR_TXAK;
++ else
++ I2CR &= ~I2CR_TXAK;
++
++ data = I2DR;
++ return data;
++}
++
++/* ------------------------------------------------------------------------
++ * API Functions
++ * ------------------------------------------------------------------------
++ */
++
++/*-----------------------------------------------------------------------
++ * i2c_init compute the i2c divider to reach the requested speed
++ * see mxl reference manual
++ */
++void i2c_init(int speed, int slaveaddr)
++{
++ int hclk_dividers[] = {
++ 30, 32, 36, 42, 48, 52, 60, 72,
++ 80, 88, 104, 128, 144, 160, 192, 240,
++ 288, 320, 384, 480, 576, 640, 768, 960,
++ 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840,
++ 22, 24, 26, 26, 32, 36, 40, 44,
++ 48, 56, 64, 72, 80, 96, 112, 128,
++ 160, 192, 224, 256, 320, 384, 448, 512,
++ 640, 768, 896, 1024, 1280, 1536, 1792, 2048
++ };
++ int refDiv = get_HCLK() / speed;
++ int i, tmpIC;
++
++ imx_gpio_mode(PA15_PF_I2C_SDA);
++ imx_gpio_mode(PA16_PF_I2C_SCL);
++
++ tmpIC = (sizeof(hclk_dividers) / sizeof(int)) - 1;
++ for (i = tmpIC; i >= 0; i--) {
++ if ((hclk_dividers[i] >= refDiv)
++ && (hclk_dividers[i] < hclk_dividers[tmpIC])) {
++ tmpIC = i;
++ }
++ }
++
++ IFDR = tmpIC;
++ IADR = slaveaddr << 1;
++
++ if (I2SR & I2SR_IBB)
++ imxi2c_send_stop();
++
++ I2CR |= I2CR_IEN;
++}
++
++/*-----------------------------------------------------------------------
++ * Probe to see if a chip is present. Also good for checking for the
++ * completion of EEPROM writes since the chip stops responding until
++ * the write completes (typically 10mSec).
++ * probe sends a read command to probe a an address
++ */
++int i2c_probe(uchar addr)
++{
++ int rc;
++
++ imxi2c_send_start();
++ rc = imxi2c_write_byte((addr << 1) | 0);
++ imxi2c_send_stop();
++
++ return rc ? 1 : 0;
++}
++
++/*-----------------------------------------------------------------------
++ * Read bytes
++ */
++int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len)
++{
++ int shift;
++ debug("i2c_read: chip %02X addr %02X alen %d buffer %p len %d\n",
++ chip, addr, alen, buffer, len);
++
++#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
++ /*
++ * EEPROM chips that implement "address overflow" are ones
++ * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
++ * address and the extra bits end up in the "chip address"
++ * bit slots. This makes a 24WC08 (1Kbyte) chip look like
++ * four 256 byte chips.
++ *
++ * Note that we consider the length of the address field to
++ * still be one byte because the extra address bits are
++ * hidden in the chip address.
++ */
++ chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
++
++ debug("i2c_read: fix addr_overflow: chip %02X addr %02X\n",
++ chip, addr);
++#endif
++
++ /*
++ * Do the addressing portion of a write cycle to set the
++ * chip's address pointer. If the address length is zero,
++ * don't do the normal write cycle to set the address pointer,
++ * there is no address pointer in this chip.
++ */
++ imxi2c_send_start();
++ if (alen > 0) {
++ if (imxi2c_write_byte(chip << 1)) { /* write cycle */
++ imxi2c_send_stop();
++ debug("i2c_read, no chip responded %02X\n", chip);
++ return 1;
++ }
++ shift = (alen - 1) * 8;
++ while (alen-- > 0) {
++ if (imxi2c_write_byte(addr >> shift)) {
++ debug("i2c_read, address not <ACK>ed\n");
++ return 1;
++ }
++ shift -= 8;
++ }
++
++ /* reportedly some chips need a full stop */
++ imxi2c_send_stop();
++ imxi2c_send_start();
++ }
++ /*
++ * Send the chip address again, this time for a read cycle.
++ * Then read the data. On the last byte, we do a NACK instead
++ * of an ACK(len == 0) to terminate the read.
++ */
++ imxi2c_write_byte((chip << 1) | 1); /* read cycle */
++ imxi2c_read_byte(len <= 2);
++ while (len-- > 1)
++ *buffer++ = imxi2c_read_byte(len == 1);
++
++ imxi2c_send_stop();
++ *buffer++ = imxi2c_read_byte(0);
++ return 0;
++}
++
++/*-----------------------------------------------------------------------
++ * Write bytes
++ */
++int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len)
++{
++ int shift, failures = 0;
++
++ debug("i2c_write: chip %02X addr %02X alen %d buffer %p len %d\n",
++ chip, addr, alen, buffer, len);
++
++ imxi2c_send_start();
++ if (imxi2c_write_byte(chip << 1)) { /* write cycle */
++ imxi2c_send_stop();
++ debug("i2c_write, no chip responded %02X\n", chip);
++ return 1;
++ }
++ shift = (alen - 1) * 8;
++ while (alen-- > 0) {
++ if (imxi2c_write_byte(addr >> shift)) {
++ debug("i2c_write, address not <ACK>ed\n");
++ return 1;
++ }
++ shift -= 8;
++ }
++
++ while (len-- > 0) {
++ if (imxi2c_write_byte(*buffer++))
++ failures++;
++ }
++ imxi2c_send_stop();
++ return failures;
++}
++
++#endif /* CONFIG_HARD_I2C */
+diff --git a/board/armadeus/apf9328/lowlevel_init.S b/board/armadeus/apf9328/lowlevel_init.S
+new file mode 100644
+index 0000000..f080423
+--- /dev/null
++++ b/board/armadeus/apf9328/lowlevel_init.S
+@@ -0,0 +1,469 @@
++/*
++ * (C) Copyright 2005-2011 ej Armadeus Project <eri...@ar...>
++ * Copyright (C) 2004 Sascha Hauer, Synertronixx GmbH
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License
++ * as published by the Free Software Foundation; either version 2
++ * of the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
++ * 02111-1307, USA.
++ *
++ */
++
++#include <config.h>
++#include <version.h>
++#include <asm/arch/imx-regs.h>
++
++.globl lowlevel_init
++lowlevel_init:
++/* Change PERCLK1DIV to 14 ie 14+1 */
++ ldr r0, =PCDR
++ ldr r1, =CONFIG_SYS_PCDR_VAL
++ str r1, [r0]
++
++/* set MCU PLL Control Register 0 */
++
++ ldr r0, =MPCTL0
++ ldr r1, =CONFIG_SYS_MPCTL0_VAL
++ str r1, [r0]
++
++/* set MCU PLL Control Register 1 */
++
++ ldr r0, =MPCTL1
++ ldr r1, =CONFIG_SYS_MPCTL1_VAL
++ str r1, [r0]
++
++/* set mpll restart bit */
++ ldr r0, =CSCR
++ ldr r1, [r0]
++ orr r1,r1,#(1<<21)
++ str r1, [r0]
++
++ mov r2,#0x10
++1:
++ mov r3,#0x2000
++2:
++ subs r3,r3,#1
++ bne 2b
++
++ subs r2,r2,#1
++ bne 1b
++
++/* set System PLL Control Register 0 */
++
++ ldr r0, =SPCTL0
++ ldr r1, =CONFIG_SYS_SPCTL0_VAL
++ str r1, [r0]
++
++/* set System PLL Control Register 1 */
++
++ ldr r0, =SPCTL1
++ ldr r1, =CONFIG_SYS_SPCTL1_VAL
++ str r1, [r0]
++
++/* set spll restart bit */
++ ldr r0, =CSCR
++ ldr r1, [r0]
++ orr r1,r1,#(1<<22)
++ str r1, [r0]
++
++ mov r2,#0x10
++1:
++ mov r3,#0x2000
++2:
++ subs r3,r3,#1
++ bne 2b
++
++ subs r2,r2,#1
++ bne 1b
++
++ ldr r0, =CSCR
++ ldr r1, =CONFIG_SYS_CSCR_VAL
++ str r1, [r0]
++
++ ldr r0, =GPCR
++ ldr r1, =CONFIG_SYS_GPCR_VAL
++ str r1, [r0]
++
++/* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
++ *this.....
++ *
++ * It would appear that from a Cold-Boot the ARM920T enters "FastBus" mode CP15
++ * register 1, this stops it using the output of the PLL and thus runs at the
++ * slow rate. Unless you place the Core into "Asynch" mode, the CPU will never
++ * use the value set in the CM_OSC registers...regardless of what you set it
++ * too! Thus, although i thought i was running at 140MHz, i'm actually running
++ * at 40!..
++
++ * Slapping this into my bootloader does the trick...
++
++ * MRC p15,0,r0,c1,c0,0 ; read core configuration register
++ * ORR r0,r0,#0xC0000000 ; set asynchronous clocks and not fastbus mode
++ * MCR p15,0,r0,c1,c0,0 ; write modified value to core configuration
++ * register
++ */
++ MRC p15,0,r0,c1,c0,0
++ ORR r0,r0,#0xC0000000
++ MCR p15,0,r0,c1,c0,0
++
++/* ldr r0, =GPR(0)
++ ldr r1, =CONFIG_SYS_GPR_A_VAL
++ str r1, [r0]
++*/
++
++ ldr r0, =DR(0)
++ ldr r1, =CONFIG_SYS_DR_A_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR1(0)
++ ldr r1, =CONFIG_SYS_OCR1_A_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR2(0)
++ ldr r1, =CONFIG_SYS_OCR2_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA1(0)
++ ldr r1, =CONFIG_SYS_ICFA1_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA2(0)
++ ldr r1, =CONFIG_SYS_ICFA2_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB1(0)
++ ldr r1, =CONFIG_SYS_ICFB1_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB2(0)
++ ldr r1, =CONFIG_SYS_ICFB2_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR1(0)
++ ldr r1, =CONFIG_SYS_ICR1_A_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR2(0)
++ ldr r1, =CONFIG_SYS_ICR2_A_VAL
++ str r1, [r0]
++
++ ldr r0, =IMR(0)
++ ldr r1, =CONFIG_SYS_IMR_A_VAL
++ str r1, [r0]
++
++ ldr r0, =DDIR(0)
++ ldr r1, =CONFIG_SYS_DDIR_A_VAL
++ str r1, [r0]
++
++ ldr r0, =GPR(0)
++ ldr r1, =CONFIG_SYS_GPR_A_VAL
++ str r1, [r0]
++
++ ldr r0, =PUEN(0)
++ ldr r1, =CONFIG_SYS_PUEN_A_VAL
++ str r1, [r0]
++
++ ldr r0, =GIUS(0)
++ ldr r1, =CONFIG_SYS_GIUS_A_VAL
++ str r1, [r0]
++
++ ldr r0, =DR(1)
++ ldr r1, =CONFIG_SYS_DR_B_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR1(1)
++ ldr r1, =CONFIG_SYS_OCR1_B_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR2(1)
++ ldr r1, =CONFIG_SYS_OCR2_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA1(1)
++ ldr r1, =CONFIG_SYS_ICFA1_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA2(1)
++ ldr r1, =CONFIG_SYS_ICFA2_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB1(1)
++ ldr r1, =CONFIG_SYS_ICFB1_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB2(1)
++ ldr r1, =CONFIG_SYS_ICFB2_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR1(1)
++ ldr r1, =CONFIG_SYS_ICR1_B_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR2(1)
++ ldr r1, =CONFIG_SYS_ICR2_B_VAL
++ str r1, [r0]
++
++ ldr r0, =IMR(1)
++ ldr r1, =CONFIG_SYS_IMR_B_VAL
++ str r1, [r0]
++
++ ldr r0, =DDIR(1)
++ ldr r1, =CONFIG_SYS_DDIR_B_VAL
++ str r1, [r0]
++
++ ldr r0, =GPR(1)
++ ldr r1, =CONFIG_SYS_GPR_B_VAL
++ str r1, [r0]
++
++ ldr r0, =PUEN(1)
++ ldr r1, =CONFIG_SYS_PUEN_B_VAL
++ str r1, [r0]
++
++ ldr r0, =GIUS(1)
++ ldr r1, =CONFIG_SYS_GIUS_B_VAL
++ str r1, [r0]
++
++ ldr r0, =DR(2)
++ ldr r1, =CONFIG_SYS_DR_C_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR1(2)
++ ldr r1, =CONFIG_SYS_OCR1_C_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR2(2)
++ ldr r1, =CONFIG_SYS_OCR2_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA1(2)
++ ldr r1, =CONFIG_SYS_ICFA1_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA2(2)
++ ldr r1, =CONFIG_SYS_ICFA2_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB1(2)
++ ldr r1, =CONFIG_SYS_ICFB1_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB2(2)
++ ldr r1, =CONFIG_SYS_ICFB2_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR1(2)
++ ldr r1, =CONFIG_SYS_ICR1_C_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR2(2)
++ ldr r1, =CONFIG_SYS_ICR2_C_VAL
++ str r1, [r0]
++
++ ldr r0, =IMR(2)
++ ldr r1, =CONFIG_SYS_IMR_C_VAL
++ str r1, [r0]
++
++ ldr r0, =DDIR(2)
++ ldr r1, =CONFIG_SYS_DDIR_C_VAL
++ str r1, [r0]
++
++ ldr r0, =GPR(2)
++ ldr r1, =CONFIG_SYS_GPR_C_VAL
++ str r1, [r0]
++
++ ldr r0, =PUEN(2)
++ ldr r1, =CONFIG_SYS_PUEN_C_VAL
++ str r1, [r0]
++
++ ldr r0, =GIUS(2)
++ ldr r1, =CONFIG_SYS_GIUS_C_VAL
++ str r1, [r0]
++
++ ldr r0, =DR(3)
++ ldr r1, =CONFIG_SYS_DR_D_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR1(3)
++ ldr r1, =CONFIG_SYS_OCR1_D_VAL
++ str r1, [r0]
++
++ ldr r0, =OCR2(3)
++ ldr r1, =CONFIG_SYS_OCR2_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA1(3)
++ ldr r1, =CONFIG_SYS_ICFA1_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFA2(3)
++ ldr r1, =CONFIG_SYS_ICFA2_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB1(3)
++ ldr r1, =CONFIG_SYS_ICFB1_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICONFB2(3)
++ ldr r1, =CONFIG_SYS_ICFB2_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR1(3)
++ ldr r1, =CONFIG_SYS_ICR1_D_VAL
++ str r1, [r0]
++
++ ldr r0, =ICR2(3)
++ ldr r1, =CONFIG_SYS_ICR2_D_VAL
++ str r1, [r0]
++
++ ldr r0, =IMR(3)
++ ldr r1, =CONFIG_SYS_IMR_D_VAL
++ str r1, [r0]
++
++ ldr r0, =DDIR(3)
++ ldr r1, =CONFIG_SYS_DDIR_D_VAL
++ str r1, [r0]
++
++ ldr r0, =GPR(3)
++ ldr r1, =CONFIG_SYS_GPR_D_VAL
++ str r1, [r0]
++
++ ldr r0, =PUEN(3)
++ ldr r1, =CONFIG_SYS_PUEN_D_VAL
++ str r1, [r0]
++
++ ldr r0, =GIUS(3)
++ ldr r1, =CONFIG_SYS_GIUS_D_VAL
++ str r1, [r0]
++
++/* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
++
++ ldr r0, =FMCR
++ ldr r1, =CONFIG_SYS_FMCR_VAL
++ str r1, [r0]
++
++ ldr r0, =CS0U
++ ldr r1, =CONFIG_SYS_CS0U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS0L
++ ldr r1, =CONFIG_SYS_CS0L_VAL
++ str r1, [r0]
++
++ ldr r0, =CS1U
++ ldr r1, =CONFIG_SYS_CS1U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS1L
++ ldr r1, =CONFIG_SYS_CS1L_VAL
++ str r1, [r0]
++
++ ldr r0, =CS2U
++ ldr r1, =CONFIG_SYS_CS2U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS2L
++ ldr r1, =CONFIG_SYS_CS2L_VAL
++ str r1, [r0]
++
++ ldr r0, =CS3U
++ ldr r1, =CONFIG_SYS_CS3U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS3L
++ ldr r1, =CONFIG_SYS_CS3L_VAL
++ str r1, [r0]
++
++ ldr r0, =CS4U
++ ldr r1, =CONFIG_SYS_CS4U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS4L
++ ldr r1, =CONFIG_SYS_CS4L_VAL
++ str r1, [r0]
++
++ ldr r0, =CS5U
++ ldr r1, =CONFIG_SYS_CS5U_VAL
++ str r1, [r0]
++
++ ldr r0, =CS5L
++ ldr r1, =CONFIG_SYS_CS5L_VAL
++ str r1, [r0]
++
++ adr r0, sdramsetup /* r0 <- current position of code */
++ /* test if we run from flash or RAM */
++ ldr r1, =PHYS_SDRAM_1
++ cmp r1, r0 /* don't reloc during debug*/
++ bhi sdramsetup
++ /* test if we run from flash or RAM */
++ ldr r1, =CONFIG_SYS_FLASH_BASE
++ cmp r0, r1 /* don't reloc during debug */
++ bmi copy2ram
++
++/* SDRAM Setup */
++sdramsetup:
++ ldr r0, =SDCTL0
++ ldr r1, =CONFIG_SYS_PRECHARGE_CMD
++ str r1, [r0]
++
++ ldr r1, =PHYS_SDRAM_1 \
++ +CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
++ ldr r2, [r1]
++
++ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
++ str r1, [r0]
++
++ ldr r1, =PHYS_SDRAM_1
++ ldr r2, [r1] /* Issue AutoRefresh Command */
++ ldr r2, [r1]
++ ldr r2, [r1]
++ ldr r2, [r1]
++ ldr r2, [r1]
++ ldr r2, [r1]
++ ldr r2, [r1]
++ ldr r2, [r1]
++
++ ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD
++ str r1, [r0]
++
++ ldr r1, =PHYS_SDRAM_1 \
++ +CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
++ str r2, [r1]
++
++ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
++ str r1, [r0]
++/* make U-Boot runnable form "almost" anywhere */
++/* but SYS_TEXT_BASE should be in RAM */
++copy2ram: /* populate _TEXT_BASE with U-Boot from load addr */
++ ldr r0, _start_adr
++ ldr r1, _copy2ram
++ sub r1, r1, r0
++ adr r0, copy2ram
++ sub r0, r0, r1
++ ldr r1, =CONFIG_SYS_TEXT_BASE
++ cmp r0, r1
++ beq end_of_copy2ram /* skip U-Boot copy */
++ ldr r2, =CONFIG_SYS_MONITOR_LEN
++ add r2, r2, r0 /* r2 <- source end address */
++
++copy_loop:
++ ldmia r0!, {r9-r10} /* copy from source address [r0] */
++ stmia r1!, {r9-r10} /* copy to target address [r1] */
++ cmp r0, r2 /* until source end address [r2] */
++ blo copy_loop
++
++end_of_copy2ram:
++ mov pc,lr
++
++_copy2ram:
++ .word copy2ram
++_start_adr:
++ .word _start
+--
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/104-apf9328-makefile.patch b/patches/u-boot/2012.04/104-apf9328-makefile.patch
new file mode 100644
index 0000000..b325d1d
--- /dev/null
+++ b/patches/u-boot/2012.04/104-apf9328-makefile.patch
@@ -0,0 +1,41 @@
+apf9328: add apf9328 board in Makefile
+
+add apf9328 board definition in makefile, MAKEALL and MAINTAINERS list
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+---
+ MAINTAINERS | 4 ++++
+ boards.cfg | 1 +
+ 2 files changed, 5 insertions(+), 0 deletions(-)
+
+diff --git a/MAINTAINERS b/MAINTAINERS
+index 708ded7..183cf0e 100644
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -240,6 +240,10 @@ Ilko Iliev <il...@ro...>
+ PM9263 AT91SAM9263
+ PM9G45 ARM926EJS (AT91SAM9G45 SoC)
+
++Eric Jarrige <eri...@ar...>
++
++ apf9328 ARM920T (iMX1)
++
+ Gary Jennejohn <ga...@de...>
+
+ quad100hd PPC405EP
+diff --git a/boards.cfg b/boards.cfg
+index 3cf75c3..c8bc589 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -52,6 +52,7 @@ integratorap_cm720t arm arm720t integrator armltd
+ integratorap_cm920t arm arm920t integrator armltd - integratorap:CM920T
+ integratorcp_cm920t arm arm920t integrator armltd - integratorcp:CM920T
+ a320evb arm arm920t - faraday a320
++apf9328 arm arm920t apf9328 armadeus imx
+ at91rm9200ek arm arm920t at91rm9200ek atmel at91 at91rm9200ek
+ at91rm9200ek_ram arm arm920t at91rm9200ek atmel at91 at91rm9200ek:RAMBOOT
+ eb_cpux9k2 arm arm920t - BuS at91
+--
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/106-mx1-pllclk.patch b/patches/u-boot/2012.04/106-mx1-pllclk.patch
new file mode 100644
index 0000000..40cb77c
--- /dev/null
+++ b/patches/u-boot/2012.04/106-mx1-pllclk.patch
@@ -0,0 +1,63 @@
+mx1: improve PLL freq computation
+
+Improve PLL freq computation by using the full resolution of the PLL registers
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Stefano Babic <sb...@de...>
+---
+ arch/arm/cpu/arm920t/imx/speed.c | 29 +++++++++++------------------
+ 1 files changed, 11 insertions(+), 18 deletions(-)
+
+diff --git a/arch/arm/cpu/arm920t/imx/speed.c b/arch/arm/cpu/arm920t/imx/speed.c
+index 1e29698..b1c2bd6 100644
+--- a/arch/arm/cpu/arm920t/imx/speed.c
++++ b/arch/arm/cpu/arm920t/imx/speed.c
+@@ -36,33 +36,26 @@
+ * the specified bus in HZ.
+ */
+ /* ------------------------------------------------------------------------- */
+-
+-ulong get_systemPLLCLK(void)
++static ulong get_PLLCLK(u32 sys_clk_freq, u32 pllctl0)
+ {
+ /* FIXME: We assume System_SEL = 0 here */
+- u32 spctl0 = SPCTL0;
+- u32 mfi = (spctl0 >> 10) & 0xf;
+- u32 mfn = spctl0 & 0x3f;
+- u32 mfd = (spctl0 >> 16) & 0x3f;
+- u32 pd = (spctl0 >> 26) & 0xf;
++ u32 mfi = (pllctl0 >> 10) & 0xf;
++ u32 mfn = pllctl0 & 0x3ff;
++ u32 mfd = (pllctl0 >> 16) & 0x3ff;
++ u32 pd = (pllctl0 >> 26) & 0xf;
+
+ mfi = mfi<=5 ? 5 : mfi;
++ return (2*(u64)sys_clk_freq * (mfi*(mfd+1) + mfn))/((mfd+1)*(pd+1));
++}
+
+- return (2*(CONFIG_SYSPLL_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
++ulong get_systemPLLCLK(void)
++{
++ return get_PLLCLK(CONFIG_SYSPLL_CLK_FREQ, SPCTL0);
+ }
+
+ ulong get_mcuPLLCLK(void)
+ {
+- /* FIXME: We assume System_SEL = 0 here */
+- u32 mpctl0 = MPCTL0;
+- u32 mfi = (mpctl0 >> 10) & 0xf;
+- u32 mfn = mpctl0 & 0x3f;
+- u32 mfd = (mpctl0 >> 16) & 0x3f;
+- u32 pd = (mpctl0 >> 26) & 0xf;
+-
+- mfi = mfi<=5 ? 5 : mfi;
+-
+- return (2*(CONFIG_SYS_CLK_FREQ>>10)*( (mfi<<10) + (mfn<<10)/(mfd+1)))/(pd+1);
++ return get_PLLCLK(CONFIG_SYS_CLK_FREQ, MPCTL0);
+ }
+
+ ulong get_FCLK(void)
+--
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/107-mx1-pllclk-debug.patch b/patches/u-boot/2012.04/107-mx1-pllclk-debug.patch
new file mode 100644
index 0000000..9621b0a
--- /dev/null
+++ b/patches/u-boot/2012.04/107-mx1-pllclk-debug.patch
@@ -0,0 +1,26 @@
+mx1: change a printf in speed.c to use debug instead
+
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Stefano Babic <sb...@de...>
+---
+ arch/arm/cpu/arm920t/imx/speed.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/cpu/arm920t/imx/speed.c b/arch/arm/cpu/arm920t/imx/speed.c
+index b1c2bd6..b8e42bf 100644
+--- a/arch/arm/cpu/arm920t/imx/speed.c
++++ b/arch/arm/cpu/arm920t/imx/speed.c
+@@ -67,7 +67,7 @@ ulong get_FCLK(void)
+ ulong get_HCLK(void)
+ {
+ u32 bclkdiv = (( CSCR >> 10 ) & 0xf) + 1;
+- printf("bclkdiv: %d\n", bclkdiv);
++ debug("bclkdiv: %d\n", bclkdiv);
+ return get_systemPLLCLK() / bclkdiv;
+ }
+
+--
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/108-DM9000.patch b/patches/u-boot/2012.04/108-DM9000.patch
new file mode 100644
index 0000000..e6a18d7
--- /dev/null
+++ b/patches/u-boot/2012.04/108-DM9000.patch
@@ -0,0 +1,48 @@
+DM9000: change some printf to use debug instead
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Ben Warren <big...@gm...>
+---
+ drivers/net/dm9000x.c | 8 ++++----
+ 1 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/drivers/net/dm9000x.c b/drivers/net/dm9000x.c
+index 0424110..3e56db5 100644
+--- a/drivers/net/dm9000x.c
++++ b/drivers/net/dm9000x.c
+@@ -240,7 +240,7 @@ dm9000_probe(void)
+ id_val |= DM9000_ior(DM9000_PIDL) << 16;
+ id_val |= DM9000_ior(DM9000_PIDH) << 24;
+ if (id_val == DM9000_ID) {
+- printf("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
++ DM9000_DBG("dm9000 i/o: 0x%x, id: 0x%x \n", CONFIG_DM9000_BASE,
+ id_val);
+ return 0;
+ } else {
+@@ -306,19 +306,19 @@ static int dm9000_init(struct eth_device *dev, bd_t *bd)
+
+ switch (io_mode) {
+ case 0x0: /* 16-bit mode */
+- printf("DM9000: running in 16 bit mode\n");
++ DM9000_DBG("DM9000: running in 16 bit mode\n");
+ db->outblk = dm9000_outblk_16bit;
+ db->inblk = dm9000_inblk_16bit;
+ db->rx_status = dm9000_rx_status_16bit;
+ break;
+ case 0x01: /* 32-bit mode */
+- printf("DM9000: running in 32 bit mode\n");
++ DM9000_DBG("DM9000: running in 32 bit mode\n");
+ db->outblk = dm9000_outblk_32bit;
+ db->inblk = dm9000_inblk_32bit;
+ db->rx_status = dm9000_rx_status_32bit;
+ break;
+ case 0x02: /* 8 bit mode */
+- printf("DM9000: running in 8 bit mode\n");
++ DM9000_DBG("DM9000: running in 8 bit mode\n");
+ db->outblk = dm9000_outblk_8bit;
+ db->inblk = dm9000_inblk_8bit;
+ db->rx_status = dm9000_rx_status_8bit;
+--
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/109-mx1-relocation.patch b/patches/u-boot/2012.04/109-mx1-relocation.patch
new file mode 100644
index 0000000..65ee7b6
--- /dev/null
+++ b/patches/u-boot/2012.04/109-mx1-relocation.patch
@@ -0,0 +1,33 @@
+mx1: Fix jump to the relocated board_init_r
+
+Jump to the relocated board_init_r according to the initial computation
+and remove computation against current PC addr as relocated address is
+already known and fixed.
+This helps to support CPU that miroor flash to different address at
+power on boot such as iMX1/L
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Stefano Babic <sb...@de...>
+---
+ arch/arm/cpu/arm920t/start.S | 4 +---
+ 1 files changed, 1 insertions(+), 3 deletions(-)
+
+diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S
+index 8c5612c..25cd4a2 100644
+--- a/arch/arm/cpu/arm920t/start.S
++++ b/arch/arm/cpu/arm920t/start.S
+@@ -292,9 +292,7 @@ _nand_boot_ofs:
+ .word nand_boot
+ #else
+ ldr r0, _board_init_r_ofs
+- adr r1, _start
+- add lr, r0, r1
+- add lr, lr, r9
++ add lr, r0, r6
+ /* setup parameters for board_init_r */
+ mov r0, r5 /* gd_t */
+ mov r1, r6 /* dest_addr */
+--
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/111-mx1-timer.patch b/patches/u-boot/2012.04/111-mx1-timer.patch
new file mode 100644
index 0000000..74fb28b
--- /dev/null
+++ b/patches/u-boot/2012.04/111-mx1-timer.patch
@@ -0,0 +1,25 @@
+mx1: Fix function get_timer() to adjust frequency according to CONFIG_SYS_HZ
+
+Signed-off-by: Eric Jarrige <eri...@ar...>
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Cc: Stefano Babic <sb...@de...>
+---
+ arch/arm/cpu/arm920t/imx/timer.c | 2 +-
+ 1 files changed, 1 insertions(+), 1 deletions(-)
+
+diff --git a/arch/arm/cpu/arm920t/imx/timer.c b/arch/arm/cpu/arm920t/imx/timer.c
+index 6141bd4..d6d1968 100644
+--- a/arch/arm/cpu/arm920t/imx/timer.c
++++ b/arch/arm/cpu/arm920t/imx/timer.c
+@@ -55,7 +55,7 @@ int timer_init (void)
+ */
+ ulong get_timer (ulong base)
+ {
+- return get_timer_masked() - base;
++ return get_timer_masked() / (1000000 / CONFIG_SYS_HZ) - base;
+ }
+
+ ulong get_timer_masked (void)
+--
+1.7.4.4
+
diff --git a/patches/u-boot/2012.04/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch b/patches/u-boot/2012.04/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
new file mode 100644
index 0000000..d962599
--- /dev/null
+++ b/patches/u-boot/2012.04/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
@@ -0,0 +1,156 @@
+Add WEIM, NFC SYSTEM_CTLconstants to the mx27 CPU
+
+Signed-off-by: Philippe Reynes <tr...@ya...>
+Signed-off-by: Eric Jarrige <eri...@ar...>
+---
+ arch/arm/cpu/arm926ejs/mx27/asm-offsets.c | 28 +++++++++++
+ arch/arm/include/asm/arch-mx27/imx-regs.h | 9 ++++
+ arch/arm/include/asm/arch-mx27/mxc_nand.h | 73 +++++++++++++++++++++++++++++
+ 3 files changed, 110 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/include/asm/arch-mx27/mxc_nand.h
+
+diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
+index f3a8d7b..7dad00f 100644
+--- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
++++ b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
+@@ -34,6 +34,7 @@ int main(void)
+ DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
+ DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
+ DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
++ DEFINE(CCSR, IMX_PLL_BASE + offsetof(struct pll_regs, ccsr));
+
+ DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
+ DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
+@@ -41,5 +42,32 @@ int main(void)
+ DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
+ DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
+
++ DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, gpcr));
++ DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, fmcr));
++ DEFINE(DSCR2, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr2));
++ DEFINE(DSCR3, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr3));
++ DEFINE(DSCR7, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr7));
++ DEFINE(DSCR10, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr10));
++
++ DEFINE(CS0U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0u));
++ DEFINE(CS0L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0l));
++ DEFINE(CS0A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0a));
++ DEFINE(CS1U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1u));
++ DEFINE(CS1L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1l));
++ DEFINE(CS1A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1a));
++ DEFINE(CS2U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2u));
++ DEFINE(CS2L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2l));
++ DEFINE(CS2A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2a));
++ DEFINE(CS3U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3u));
++ DEFINE(CS3L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3l));
++ DEFINE(CS3A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3a));
++ DEFINE(CS4U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4u));
++ DEFINE(CS4L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4l));
++ DEFINE(CS4A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4a));
++ DEFINE(CS5U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5u));
++ DEFINE(CS5L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5l));
++ DEFINE(CS5A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5a));
++ DEFINE(EIM, IMX_WEIM_BASE + offsetof(struct weim_regs, eim));
++
+ return 0;
+ }
+diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
+index ced5b2a..4df67d6 100644
+--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
++++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
+@@ -522,4 +522,13 @@ struct fuse_bank0_regs {
+ #define IIM_ERR_SNSE (1 << 2)
+ #define IIM_ERR_PARITYE (1 << 1)
+
++/*
++ * Memory areas of the NFC
++ */
++#define IMX_NFC_BASE (0xD8000000)
++#define IMX_NFC_MAIN_AREA0 (0xD8000000)
++#define IMX_NFC_MAIN_AREA1 (0xD8000200)
++#define IMX_NFC_SPARE_AREA0 (0xD8000800)
++#define IMX_NFC_REGS (0xD8000E00)
++
+ #endif /* _IMX_REGS_H */
+diff --git a/arch/arm/include/asm/arch-mx27/mxc_nand.h b/arch/arm/include/asm/arch-mx27/mxc_nand.h
+new file mode 100644
+index 0000000..99af18b
+--- /dev/null
++++ b/arch/arm/include/asm/arch-mx27/mxc_nand.h
+@@ -0,0 +1,73 @@
++/*
++ * (c) 2012 Philippe Reynes <tr...@ya...>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __MXC_NAND_H
++#define __MXC_NAND_H
++
++/*
++ * NFC registers address offest
++ */
++#define NFC_OFFSET_BUFSIZE (0x00) /* Internal SRAM Size */
++#define NFC_OFFSET_BLCK_ADD_LOCK (0x02) /* NAND Flash Block Address for Lock Check */
++#define NFC_OFFSET_BUF_ADDR (0x04) /* Buffer Number for Page Data Transfer To/
++ From Flash Memory */
++#define NFC_OFFSET_FLASH_ADDR (0x06) /* NAND Flash Address */
++#define NFC_OFFSET_FLASH_CMD (0x08) /* NAND Flash Command */
++#define NFC_OFFSET_CONFIG (0x0A) /* NFC Internal Buffer Lock Control */
++#define NFC_OFFSET_ECC_STATUS_RESULT (0x0C) /* Controller Status/Result of Flash Operation */
++#define NFC_OFFSET_ECC_RSLT_MAIN_AREA (0x0E) /* ECC ...
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