[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-315-g0da920b
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-315-g0da920b
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From: jorasse <jo...@us...> - 2012-05-22 23:10:52
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 0da920b941b3c8c8144d0181c4ffec7f9ad5767c (commit)
from 016e87336b375cd7657a7ccf040d50296577b672 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 0da920b941b3c8c8144d0181c4ffec7f9ad5767c
Author: Eric Jarrige <eri...@ar...>
Date: Wed May 23 01:10:16 2012 +0200
[UBOOT] apf27: cleanup and reorganize patchwork
-----------------------------------------------------------------------
Summary of changes:
...-Add-support-for-the-armadeus-apf27-board.patch | 1243 ++++++++++++++++----
.../u-boot/2011.12/304-Add-type-for-apf27.patch | 24 -
patches/u-boot/2011.12/310-apf27-nand-spl.patch | 721 ------------
3 files changed, 982 insertions(+), 1006 deletions(-)
delete mode 100644 patches/u-boot/2011.12/304-Add-type-for-apf27.patch
delete mode 100644 patches/u-boot/2011.12/310-apf27-nand-spl.patch
diff --git a/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch b/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
index a8cde15..b3e53eb 100644
--- a/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
+++ b/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
@@ -301,6 +301,324 @@ index 0000000..3354ba0
+TEXT_BASE = 0xAFF00000
+endif
+# CONFIG_NAND_U_BOOT = y
+Index: u-boot-2010.03/board/armadeus/apf27/fpga.c
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2010.03/board/armadeus/apf27/fpga.c 2011-01-05 18:09:44.000000000 +0100
+@@ -0,0 +1,269 @@
++/*
++ * (C) Copyright 2002-2008
++ * Eric Jarrige <eri...@ar...>
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++#include <common.h>
++
++#if defined(CONFIG_FPGA)
++
++#include <asm/arch/imx-regs.h>
++#include <asm/io.h>
++#include <command.h>
++#include <config.h>
++#include "fpga.h"
++#include <spartan3.h>
++
++#define GPIO_PORT(x) ((x & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT)
++#define GPIO_SET(x) writel(readl(&gpregs->port[GPIO_PORT(x)].dr) | (1 << (x & GPIO_PIN_MASK)), \
++ &gpregs->port[GPIO_PORT(x)].dr)
++//(DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK)))
++#define GPIO_CLEAR(x) writel(readl(&gpregs->port[GPIO_PORT(x)].dr) & ~(1 << (x & GPIO_PIN_MASK)), \
++ &gpregs->port[GPIO_PORT(x)].dr)
++//(DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK)))
++#define GPIO_WRITE(x,y) ( y ? GPIO_SET(x) : GPIO_CLEAR(x) )
++#define GPIO_READ(x) ((readl(&gpregs->port[GPIO_PORT(x)].ssr) & (1 << (x & GPIO_PIN_MASK))) \
++ >> (x & GPIO_PIN_MASK))
++//((SSR (GPIO_PORT(x)) & (1<<(x & GPIO_PIN_MASK)))>> (x & GPIO_PIN_MASK))
++#ifdef FPGA_DEBUG
++#define PRINTF(fmt,args...) printf (fmt ,##args)
++#else
++#define PRINTF(fmt,args...)
++#endif
++
++/* Note that these are pointers to code that is in Flash. They will be
++ * relocated at runtime.
++ * Spartan2 code is used to download our Spartan 3 :) code is compatible.
++ * Just take care about the file size
++*/
++Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
++ fpga_pre_fn,
++ fpga_pgm_fn,
++ fpga_init_fn,
++ NULL,
++ fpga_done_fn,
++ fpga_clk_fn,
++ fpga_cs_fn,
++ fpga_wr_fn,
++ fpga_rdata_fn,
++ fpga_wdata_fn,
++ fpga_busy_fn,
++ fpga_abort_fn,
++ fpga_post_fn,
++};
++
++Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
++ {Xilinx_Spartan3,
++ slave_parallel,
++ 1196128l/8,
++ (void *) &fpga_fns,
++ 0}
++};
++
++/*
++ * nitialize GPIO port B before download
++ */
++int
++fpga_pre_fn (int cookie)
++{
++ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++ // Initialize GPIO pins
++ GPIO_SET(CONFIG_SYS_FPGA_PWR);
++ imx_gpio_mode (CONFIG_SYS_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
++ imx_gpio_mode (CONFIG_SYS_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
++ imx_gpio_mode (CONFIG_SYS_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++ imx_gpio_mode (CONFIG_SYS_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++ imx_gpio_mode (CONFIG_SYS_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++ imx_gpio_mode (CONFIG_SYS_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++ imx_gpio_mode (CONFIG_SYS_FPGA_SUSPEND | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++ GPIO_SET(CONFIG_SYS_FPGA_RESET);
++ imx_gpio_mode (CONFIG_SYS_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++ imx_gpio_mode (CONFIG_SYS_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++ GPIO_SET(CONFIG_SYS_FPGA_PRG);
++ GPIO_SET(CONFIG_SYS_FPGA_CLK);
++ GPIO_SET(CONFIG_SYS_FPGA_RW);
++ GPIO_SET(CONFIG_SYS_FPGA_CS);
++ GPIO_CLEAR(CONFIG_SYS_FPGA_SUSPEND);
++// GPIO_CLEAR(CONFIG_SYS_FPGA_RESET);
++ GPIO_CLEAR(CONFIG_SYS_FPGA_PWR);
++
++ return cookie;
++}
++
++/*
++ * Set the FPGA's active-low program line to the specified level
++ */
++int
++fpga_pgm_fn (int assert, int flush, int cookie)
++{
++ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++ PRINTF ("%s:%d: FPGA PROGRAM %s", __FUNCTION__, __LINE__,
++ assert?"high":"low");
++ GPIO_WRITE( CONFIG_SYS_FPGA_PRG, !assert);
++ return assert;
++}
++
++/*
++ * Set the FPGA's active-high clock line to the specified level
++ */
++int
++fpga_clk_fn (int assert_clk, int flush, int cookie)
++{
++ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++ PRINTF ("%s:%d: FPGA CLOCK %s", __FUNCTION__, __LINE__,
++ assert_clk?"high":"low");
++ GPIO_WRITE( CONFIG_SYS_FPGA_CLK, !assert_clk);
++ return assert_clk;
++}
++
++/*
++ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
++ * asserted (low).
++ */
++int
++fpga_init_fn (int cookie)
++{
++ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++ int value;
++ PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
++ value = GPIO_READ(CONFIG_SYS_FPGA_INIT);
++ //printf("init value read %x",value);
++#ifdef CONFIG_SYS_FPGA_IS_PROTO
++ return value;
++#else
++ return !value;
++#endif
++}
++
++/*
++ * Test the state of the active-high FPGA DONE pin
++ */
++int
++fpga_done_fn (int cookie)
++{
++ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++ PRINTF ("%s:%d: DONE check... %s", __FUNCTION__, __LINE__,
++ GPIO_READ(CONFIG_SYS_FPGA_DONE)?"high":"low");
++ return(GPIO_READ(CONFIG_SYS_FPGA_DONE)?FPGA_SUCCESS:FPGA_FAIL);
++}
++
++/*
++ * Set the FPGA's wr line to the specified level
++ */
++int
++fpga_wr_fn (int assert_write, int flush, int cookie)
++{
++ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++ PRINTF ("%s:%d: FPGA RW... %s ", __FUNCTION__, __LINE__,
++ assert_write?"high":"low");
++ GPIO_WRITE( CONFIG_SYS_FPGA_RW, !assert_write);
++ return assert_write;
++}
++
++int
++fpga_cs_fn (int assert_cs, int flush, int cookie)
++{
++ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++ PRINTF ("%s:%d: FPGA CS %s ", __FUNCTION__, __LINE__,
++ assert_cs?"high":"low");
++ GPIO_WRITE( CONFIG_SYS_FPGA_CS, !assert_cs);
++ return assert_cs;
++}
++
++int
++fpga_rdata_fn ( unsigned char *data, int cookie )
++{
++ PRINTF ("%s:%d: FPGA READ DATA %02X ", __FUNCTION__, __LINE__,
++ *((char*)CONFIG_SYS_FPGA_RDATA));
++ *data = (unsigned char)((*((unsigned short*)CONFIG_SYS_FPGA_RDATA))&0x00FF);
++ return *data;
++}
++
++int
++fpga_wdata_fn ( unsigned char data, int cookie )
++{
++ PRINTF ("%s:%d: FPGA WRITE DATA %02X ", __FUNCTION__, __LINE__,
++ data);
++ *((unsigned short*)CONFIG_SYS_FPGA_WDATA) = data;
++ return data;
++}
++
++int
++fpga_abort_fn ( int cookie )
++{
++ return cookie;
++}
++
++
++int
++fpga_busy_fn ( int cookie )
++{
++ return 1;
++}
++
++int
++fpga_post_fn (int cookie)
++{
++ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
++ PRINTF ("%s:%d: FPGA POST ", __FUNCTION__, __LINE__);
++
++ imx_gpio_mode (CONFIG_SYS_FPGA_RW | GPIO_PF | GPIO_PUEN);
++ imx_gpio_mode (CONFIG_SYS_FPGA_CS | GPIO_PF | GPIO_PUEN);
++ imx_gpio_mode (CONFIG_SYS_FPGA_CLK | GPIO_PF | GPIO_PUEN);
++ GPIO_SET(CONFIG_SYS_FPGA_PRG);
++ GPIO_CLEAR(CONFIG_SYS_FPGA_RESET);
++ imx_gpio_mode (CONFIG_SYS_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
++ return cookie;
++}
++
++/*
++ * Initialize the fpga. Return 1 on success, 0 on failure.
++ */
++int
++APF27_init_fpga (u_char * buffer, size_t size)
++{
++ char *autoload = getenv ("firmware_autoload");
++
++ int i,lout=0;
++
++ fpga_init();
++
++ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
++ PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
++ fpga_add (fpga_xilinx, &fpga[i]);
++ }
++
++ if ((size >= fpga[0].size) && ( autoload ) && (0 == strcmp(autoload, "1"))) {
++ if (ctrlc()) {
++ printf("Firmware download stopped!\n");
++ } else if (FPGA_SUCCESS != fpga_load( 0,(void *)buffer, size )) {
++ printf("Firmware download failed!\n");
++ } else {
++ printf("Firmware successfully programmed\n");
++ lout = 1;
++ }
++ }
++ return lout;
++}
++
++#endif /* CONFIG_FPGA */
+Index: u-boot-2010.03/board/armadeus/apf27/fpga.h
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2010.03/board/armadeus/apf27/fpga.h 2011-01-05 18:09:44.000000000 +0100
+@@ -0,0 +1,39 @@
++/*
++ * (C) Copyright 2002-2008
++ * Eric Jarrige <eri...@ar...>
++ * Rich Ireland, Enterasys Networks, rir...@en....
++ * Keith Outwater, kei...@mv....
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ *
++ */
++extern int APF27_init_fpga (u_char * buffer, size_t size);
++
++extern int fpga_pre_fn (int cookie);
++extern int fpga_pgm_fn (int assert_pgm, int flush, int cookie);
++extern int fpga_cs_fn (int assert_cs, int flush, int cookie);
++extern int fpga_init_fn (int cookie);
++extern int fpga_done_fn (int cookie);
++extern int fpga_clk_fn (int assert_clk, int flush, int cookie);
++extern int fpga_wr_fn (int assert_write, int flush, int cookie);
++extern int fpga_rdata_fn ( unsigned char *data, int cookie );
++extern int fpga_wdata_fn ( unsigned char data, int cookie );
++extern int fpga_abort_fn (int cookie);
++extern int fpga_post_fn (int cookie);
++extern int fpga_busy_fn (int cookie);
diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S
new file mode 100644
index 0000000..4d72d8c
@@ -721,42 +1039,175 @@ index 0000000..f66f20e
+ . = ALIGN(4);
+ .data : { *(.data) }
+
-+ . = ALIGN(4);
-+ .got : { *(.got) }
++ . = ALIGN(4);
++ .got : { *(.got) }
++
++ __u_boot_cmd_start = .;
++ .u_boot_cmd : { *(.u_boot_cmd) }
++ __u_boot_cmd_end = .;
++
++ . = ALIGN(4);
++ __bss_start = .;
++ .bss : { *(.bss) }
++ _end = .;
++}
++
+diff --git a/boards.cfg b/boards.cfg
+index 66c27a4..f68c3a7 100644
+--- a/boards.cfg
++++ b/boards.cfg
+@@ -69,6 +69,7 @@ integratorcp_cm926ejs arm arm926ejs integrator armltd
+ aspenite arm arm926ejs - Marvell armada100
+ gplugd arm arm926ejs - Marvell armada100
+ afeb9260 arm arm926ejs - - at91
++apf27 arm arm926ejs apf27 armadeus mx27
+ at91sam9260ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0
+ at91sam9260ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1
+ at91sam9260ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH
+Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/Makefile
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2010.03/nand_spl/board/armadeus/apf27/Makefile 2011-01-05 18:09:44.000000000 +0100
+@@ -0,0 +1,77 @@
++#
++# (C) Copyright 2007
++# Stefan Roese, DENX Software Engineering, sr...@de....
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++
++include $(TOPDIR)/config.mk
++include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
++
++LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
++LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
++AFLAGS += -DCONFIG_NAND_SPL
++CFLAGS += -DCONFIG_NAND_SPL
++
++SOBJS = start.o
++COBJS =
++
++SRCS := $(addprefix $(src),$(SOBJS:.o=.S) $(COBJS:.o=.c))
++OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
++__OBJS := $(SOBJS) $(COBJS)
++LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
++
++nandobj := $(OBJTREE)/nand_spl/
++
++ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
++ $(nandobj)System.map
++
++all: $(obj).depend $(ALL)
++
++$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
++ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
++
++$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
++ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
++
++$(nandobj)u-boot-spl: $(OBJS)
++ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
++ -Map $(nandobj)u-boot-spl.map \
++ -o $(nandobj)u-boot-spl
++
++$(nandobj)System.map: $(nandobj)u-boot-spl
++ @$(NM) $< | \
++ grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
++ sort > $(nandobj)System.map
++
++
++#########################################################################
++
++$(obj)%.o: %.S
++ $(CC) $(AFLAGS) -c -o $@ $<
++
++$(obj)%.o: %.c
++ $(CC) $(CFLAGS) -c -o $@ $<
++
++# defines $(obj).depend target
++include $(SRCTREE)/rules.mk
++
++sinclude $(obj).depend
++
++#########################################################################
+Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/config.mk
+===================================================================
+--- /dev/null 1970-01-01 00:00:00.000000000 +0000
++++ u-boot-2010.03/nand_spl/board/armadeus/apf27/config.mk 2011-01-05 18:09:44.000000000 +0100
+@@ -0,0 +1,43 @@
++#
++# (C) Copyright 2007
++# Stefan Roese, DENX Software Engineering, sr...@de....
++#
++# See file CREDITS for list of people who contributed to this
++# project.
++#
++# This program is free software; you can redistribute it and/or
++# modify it under the terms of the GNU General Public License as
++# published by the Free Software Foundation; either version 2 of
++# the License, or (at your option) any later version.
++#
++# This program is distributed in the hope that it will be useful,
++# but WITHOUT ANY WARRANTY; without even the implied warranty of
++# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++# GNU General Public License for more details.
++#
++# You should have received a copy of the GNU General Public License
++# along with this program; if not, write to the Free Software
++# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++# MA 02111-1307 USA
++#
++#
++# This config file is used for compilation of armadeus apf27 board
++#
+
-+ __u_boot_cmd_start = .;
-+ .u_boot_cmd : { *(.u_boot_cmd) }
-+ __u_boot_cmd_end = .;
++#
++# TEXT_BASE for SPL:
++#
++#
++# This config file is used for compilation of armadeus sources
++#
++# You might change location of U-Boot in memory by setting right TEXT_BASE.
++# This allows for example having one copy located at the end of ram and stored
++# in flash device and later on while developing use other location to test
++# the code in RAM device only.
++#
+
-+ . = ALIGN(4);
-+ __bss_start = .;
-+ .bss : { *(.bss) }
-+ _end = .;
-+}
++TEXT_BASE = 0xa0000000
+
-diff --git a/boards.cfg b/boards.cfg
-index 66c27a4..f68c3a7 100644
---- a/boards.cfg
-+++ b/boards.cfg
-@@ -69,6 +69,7 @@ integratorcp_cm926ejs arm arm926ejs integrator armltd
- aspenite arm arm926ejs - Marvell armada100
- gplugd arm arm926ejs - Marvell armada100
- afeb9260 arm arm926ejs - - at91
-+apf27 arm arm926ejs apf27 armadeus mx27
- at91sam9260ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0
- at91sam9260ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1
- at91sam9260ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH
-1.7.4.4
-Index: u-boot-2010.03/board/armadeus/apf27/fpga.c
++# PAD_TO used to generate a 2kByte binary needed for the combined image
++# -> PAD_TO = TEXT_BASE + 0x0800
++PAD_TO = 0xa0000800
+Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/board/armadeus/apf27/fpga.c 2011-01-05 18:09:44.000000000 +0100
-@@ -0,0 +1,269 @@
++++ u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S 2011-01-05 18:09:44.000000000 +0100
+@@ -0,0 +1,544 @@
+/*
-+ * (C) Copyright 2002-2008
-+ * Eric Jarrige <eri...@ar...>
-+ * Rich Ireland, Enterasys Networks, rir...@en....
-+ * Keith Outwater, kei...@mv....
++ * IMX27 NAND Flash SPL (Secondary Program Loader)
++ *
++ * Copyright (c) 2008 Armadeus Project / eja
++ *
++ * Based on Freescale NAND SPL
++ *
++ * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
++ * Copyright (c) 2008 Eric Jarrige <eri...@ar...>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
@@ -775,262 +1226,531 @@ Index: u-boot-2010.03/board/armadeus/apf27/fpga.c
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
-+ *
+ */
-+#include <common.h>
+
-+#if defined(CONFIG_FPGA)
+
-+#include <asm/arch/imx-regs.h>
-+#include <asm/io.h>
-+#include <command.h>
+#include <config.h>
-+#include "fpga.h"
-+#include <spartan3.h>
++#include <version.h>
++#include <asm/arch/imx-regs.h>
+
-+#define GPIO_PORT(x) ((x & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT)
-+#define GPIO_SET(x) writel(readl(&gpregs->port[GPIO_PORT(x)].dr) | (1 << (x & GPIO_PIN_MASK)), \
-+ &gpregs->port[GPIO_PORT(x)].dr)
-+//(DR(GPIO_PORT(x)) |= (1<<(x & GPIO_PIN_MASK)))
-+#define GPIO_CLEAR(x) writel(readl(&gpregs->port[GPIO_PORT(x)].dr) & ~(1 << (x & GPIO_PIN_MASK)), \
-+ &gpregs->port[GPIO_PORT(x)].dr)
-+//(DR(GPIO_PORT(x)) &= ~(1<<(x & GPIO_PIN_MASK)))
-+#define GPIO_WRITE(x,y) ( y ? GPIO_SET(x) : GPIO_CLEAR(x) )
-+#define GPIO_READ(x) ((readl(&gpregs->port[GPIO_PORT(x)].ssr) & (1 << (x & GPIO_PIN_MASK))) \
-+ >> (x & GPIO_PIN_MASK))
-+//((SSR (GPIO_PORT(x)) & (1<<(x & GPIO_PIN_MASK)))>> (x & GPIO_PIN_MASK))
-+#ifdef FPGA_DEBUG
-+#define PRINTF(fmt,args...) printf (fmt ,##args)
++/*
++ * Standard NAND flash commands
++ */
++#define NAND_CMD_READ0 0
++#define NAND_CMD_READ1 1
++#define NAND_CMD_PAGEPROG 0x10
++#define NAND_CMD_READOOB 0x50
++#define NAND_CMD_ERASE1 0x60
++#define NAND_CMD_STATUS 0x70
++#define NAND_CMD_STATUS_MULTI 0x71
++#define NAND_CMD_SEQIN 0x80
++#define NAND_CMD_READID 0x90
++#define NAND_CMD_ERASE2 0xd0
++#define NAND_CMD_RESET 0xff
++
++/* Extended commands for large page devices */
++#define NAND_CMD_READSTART 0x30
++#define NAND_CMD_CACHEDPROG 0x15
++
++/* Status bits */
++#define NAND_STATUS_FAIL 0x01
++#define NAND_STATUS_FAIL_N1 0x02
++#define NAND_STATUS_TRUE_READY 0x20
++#define NAND_STATUS_READY 0x40
++#define NAND_STATUS_WP 0x80
++
++#define writel(reg, val) \
++ ldr r0, =reg; \
++ ldr r1, =val; \
++ str r1, [r0];
++
++ .macro nand_boot
++
++#ifdef CONFIG_BOOT_TRACE_REG
++/*
++ * If CONFIG_BOOT_TRACE_REG is a SDRAM address then be sure to use the following
++ * 2 command after SDRAM init
++ */
++
++/* Backup state of previous boot to CONFIG_BOOT_TRACE_REG+4*/
++#define BACKUP_TRACE() \
++ ldr r4, =CONFIG_BOOT_TRACE_REG; \
++ ldr r3, [r4]; \
++ str r3, [r4, #0x04];
++
++/* Save a state of boot at CONFIG_BOOT_TRACE_REG */
++#define BOOT_TRACE(val) \
++ ldr r4, =CONFIG_BOOT_TRACE_REG; \
++ ldr r3, =val; \
++ str r3, [r4];
+#else
-+#define PRINTF(fmt,args...)
++#define BACKUP_TRACE()
++#define BOOT_TRACE(val)
+#endif
+
-+/* Note that these are pointers to code that is in Flash. They will be
-+ * relocated at runtime.
-+ * Spartan2 code is used to download our Spartan 3 :) code is compatible.
-+ * Just take care about the file size
-+*/
-+Xilinx_Spartan3_Slave_Parallel_fns fpga_fns = {
-+ fpga_pre_fn,
-+ fpga_pgm_fn,
-+ fpga_init_fn,
-+ NULL,
-+ fpga_done_fn,
-+ fpga_clk_fn,
-+ fpga_cs_fn,
-+ fpga_wr_fn,
-+ fpga_rdata_fn,
-+ fpga_wdata_fn,
-+ fpga_busy_fn,
-+ fpga_abort_fn,
-+ fpga_post_fn,
-+};
++nand_boot_setup:
+
-+Xilinx_desc fpga[CONFIG_FPGA_COUNT] = {
-+ {Xilinx_Spartan3,
-+ slave_parallel,
-+ 1196128l/8,
-+ (void *) &fpga_fns,
-+ 0}
-+};
++ /* Copy SPL image from flash to SDRAM first */
++ BOOT_TRACE(1)
++ ldr r0, =IMX_NFC_MAIN_AREA0
++ add r2, r0, #(IMX_NFC_SPARE_AREA0-IMX_NFC_MAIN_AREA0) //2KB NFC Buff
++ ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST
+
-+/*
-+ * nitialize GPIO port B before download
-+ */
-+int
-+fpga_pre_fn (int cookie)
-+{
-+ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+ // Initialize GPIO pins
-+ GPIO_SET(CONFIG_SYS_FPGA_PWR);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_INIT | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_DONE | GPIO_IN | GPIO_PUEN | GPIO_GPIO);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_PRG | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_CLK | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_RW | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_CS | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_SUSPEND | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+ GPIO_SET(CONFIG_SYS_FPGA_RESET);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_PWR | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+ GPIO_SET(CONFIG_SYS_FPGA_PRG);
-+ GPIO_SET(CONFIG_SYS_FPGA_CLK);
-+ GPIO_SET(CONFIG_SYS_FPGA_RW);
-+ GPIO_SET(CONFIG_SYS_FPGA_CS);
-+ GPIO_CLEAR(CONFIG_SYS_FPGA_SUSPEND);
-+// GPIO_CLEAR(CONFIG_SYS_FPGA_RESET);
-+ GPIO_CLEAR(CONFIG_SYS_FPGA_PWR);
++ BOOT_TRACE(2)
++1: ldmia r0!, {r3-r10}
++ stmia r1!, {r3-r10}
++ cmp r0, r2
++ blo 1b
+
-+ return cookie;
-+}
+
-+/*
-+ * Set the FPGA's active-low program line to the specified level
-+ */
-+int
-+fpga_pgm_fn (int assert, int flush, int cookie)
-+{
-+ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+ PRINTF ("%s:%d: FPGA PROGRAM %s", __FUNCTION__, __LINE__,
-+ assert?"high":"low");
-+ GPIO_WRITE( CONFIG_SYS_FPGA_PRG, !assert);
-+ return assert;
-+}
+
-+/*
-+ * Set the FPGA's active-high clock line to the specified level
-+ */
-+int
-+fpga_clk_fn (int assert_clk, int flush, int cookie)
-+{
-+ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+ PRINTF ("%s:%d: FPGA CLOCK %s", __FUNCTION__, __LINE__,
-+ assert_clk?"high":"low");
-+ GPIO_WRITE( CONFIG_SYS_FPGA_CLK, !assert_clk);
-+ return assert_clk;
-+}
++ /* Jump to SDRAM */
++ BOOT_TRACE(3)
++ ldr r1, =0xFFF
++ and r0, pc, r1 /* offset of pc */
++ ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST
++ add r1, r1, #0x10
++ add pc, r0, r1
++ nop
++ nop
++ nop
++ nop
++
++NAND_Copy_Main:
++ BOOT_TRACE(4)
++ /* r0: nfc base. Reloaded after each page copying */
++ ldr r0, =IMX_NFC_MAIN_AREA0
++
++ /* r1: starting flash addr to be copied. Updated constantly */
++ /* bypass the first preloaded pages */
++ ldr r1, =(IMX_NFC_SPARE_AREA0-IMX_NFC_MAIN_AREA0)
++
++ /* r2: end of 1st RAM buf. Doesn't change */
++ ldr r2, =IMX_NFC_MAIN_AREA1
++
++ /* r12: NFC register base. Doesn't change */
++ ldr r12, =IMX_NFC_REGS
++
++ ldr r11, =CONFIG_SYS_NAND_U_BOOT_DST
++
++ /* r13: end of SDRAM address for copying. Doesn't change */
++ add r13, r11, #CONFIG_SYS_NAND_U_BOOT_SIZE
++
++ /* r11: starting SDRAM address for copying. Updated constantly */
++ add r11, r11, r1
++
++ /* unlock internal buffer */
++ ldr r3, =NFC_CONFIG_UNLOCKED
++ strh r3, [r12, #NFC_OFFSET_CONFIG]
++
++ /* enable ECC and mask interrupts */
++ ldr r3, =(NFC_CONFIG1_ECC_EN | NFC_CONFIG1_INT_MSK)
++ strh r3, [r12, #NFC_OFFSET_CONFIG1]
++
++Nfc_Read_Page:
++ BOOT_TRACE(5)
++ /* send NAND_CMD_READ0 command */
++ ldr r3, =NAND_CMD_READ0;
++ strh r3, [r12, #NFC_OFFSET_FLASH_CMD]
++
++ ldr r3, =NFC_CONFIG2_FCMD
++ strh r3, [r12, #NFC_OFFSET_CONFIG2]
++ bl do_wait_op_done
++
++ /* send NAND address to read. TODO small page support */
++ BOOT_TRACE(6)
++ mov r3, r1, lsr #1
++ bl do_addr_input /* 1st addr cycle */
++
++ mov r3, r1, lsr #9
++ and r3, r3, #0x03
++ bl do_addr_input /* 2nd addr cycle */
++
++ mov r3, r1, lsr #11
++ bl do_addr_input /* 3rd addr cycle */
++
++ mov r3, r1, lsr #19
++ bl do_addr_input /* 4th addr cycle */
++
++ /* Small NAND flashs (== 1Gb) support 5 addr cycles */
++ mov r3, r1, lsr #27
++ bl do_addr_input /* 5th addr cycle */
++
++ /* send NAND_CMD_READSTART command. TODO small page support */
++ BOOT_TRACE(7)
++ mov r3, #NAND_CMD_READSTART;
++ strh r3, [r12, #NFC_OFFSET_FLASH_CMD]
++ mov r3, #NFC_CONFIG2_FCMD
++ strh r3, [r12, #NFC_OFFSET_CONFIG2]
++ bl do_wait_op_done
++
++ /* read and copy buf 0 */
++ BOOT_TRACE(8)
++ mov r3, #0
++ strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
++
++ mov r3, #NFC_CONFIG2_FDO_PAGE
++ strh r3, [r12, #NFC_OFFSET_CONFIG2]
++ bl do_wait_op_done
++
++ bl Test_And_Copy_Buffer
++
++ /* read and copy buf 1 */
++ mov r3, #1
++ strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
++
++ mov r3, #NFC_CONFIG2_FDO_PAGE
++ strh r3, [r12, #NFC_OFFSET_CONFIG2]
++ bl do_wait_op_done
++
++ bl Test_And_Copy_Buffer
++
++ /* here we should test if 512B page flash and bypass next buffers */
++ /* read and copy buf 2. TODO small page support */
++ mov r3, #2
++ strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
++
++ mov r3, #NFC_CONFIG2_FDO_PAGE
++ strh r3, [r12, #NFC_OFFSET_CONFIG2]
++ bl do_wait_op_done
++
++ bl Test_And_Copy_Buffer
++
++ /* read and copy buf 3 */
++ mov r3, #3
++ strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
++
++ mov r3, #NFC_CONFIG2_FDO_PAGE
++ strh r3, [r12, #NFC_OFFSET_CONFIG2]
++ bl do_wait_op_done
++
++ bl Test_And_Copy_Buffer
++
++ /* is the last page ? */
++ BOOT_TRACE(12)
++ cmp r11, r13
++ bge NAND_Copy_Main_done
++
++ /* r0: nfc base. Reloaded after each page copying */
++ ldr r0, =IMX_NFC_MAIN_AREA0
++ /* r2: end of 1st RAM buf. Doesn't change */
++ ldr r2, =IMX_NFC_MAIN_AREA1
++ b Nfc_Read_Page
++
++NAND_Copy_Main_done:
++ BOOT_TRACE(13)
++ .endm /* nand_boot */
++
++ .macro init_aipi
++ /*
++ * setup AIPI1 and AIPI2
++ */
++ writel(AIPI1_PSR0, CONFIG_SYS_AIPI1_PSR0_VAL)
++ writel(AIPI1_PSR1, CONFIG_SYS_AIPI1_PSR1_VAL)
++ writel(AIPI2_PSR0, CONFIG_SYS_AIPI2_PSR0_VAL)
++ writel(AIPI2_PSR1, CONFIG_SYS_AIPI2_PSR1_VAL)
++
++ /* Change SDRAM signal strengh */
++ ldr r0, =GPCR
++ ldr r1, =CONFIG_SYS_GPCR_VAL
++ ldr r5, [r0]
++ orr r5, r5, r1
++ str r5, [r0]
++
++ .endm /* init_aipi */
++
++ .macro init_clock
++ ldr r0, =CSCR
++ /* disable MPLL/SPLL first */
++ ldr r1, [r0]
++ bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
++ str r1, [r0]
++
++ /*
++ * pll clock initialization predefined in apf27.h
++ */
++ writel(MPCTL0, CONFIG_SYS_MPCTL0_VAL)
++ writel(SPCTL0, CONFIG_SYS_SPCTL0_VAL)
++
++ writel(CSCR, CONFIG_SYS_CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART)
++
++ /*
++ * add some delay here
++ */
++ mov r1, #0x1000
++ 1: subs r1, r1, #0x1
++ bne 1b
++
++ /* peripheral clock divider */
++ writel(PCDR0, CONFIG_SYS_PCDR0_VAL)
++ writel(PCDR1, CONFIG_SYS_PCDR1_VAL)
++
++ /* Configure PCCR0 and PCCR1 */
++ writel(PCCR0, CONFIG_SYS_PCCR0_VAL)
++ writel(PCCR1, CONFIG_SYS_PCCR1_VAL)
++
++ .endm /* init_clock */
+
+/*
-+ * Test the state of the active-low FPGA INIT line. Return 1 on INIT
-+ * asserted (low).
++ *************************************************************************
++ *
++ * No jump vector table. Use reset vector as direct entry point.
++ * Do not support any interrupt event within SPL
++ *
++ *************************************************************************
+ */
-+int
-+fpga_init_fn (int cookie)
-+{
-+ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+ int value;
-+ PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
-+ value = GPIO_READ(CONFIG_SYS_FPGA_INIT);
-+ //printf("init value read %x",value);
-+#ifdef CONFIG_SYS_FPGA_IS_PROTO
-+ return value;
-+#else
-+ return !value;
-+#endif
-+}
++
++
++.globl _start
++_start:
+
+/*
-+ * Test the state of the active-high FPGA DONE pin
++ *************************************************************************
++ *
++ * Startup Code (reset vector)
++ *
++ * do important init only if we don't start from memory!
++ * setup Memory and board specific bits prior to relocation.
++ * relocate armboot to ram
++ * setup stack
++ *
++ *************************************************************************
+ */
-+int
-+fpga_done_fn (int cookie)
-+{
-+ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+ PRINTF ("%s:%d: DONE check... %s", __FUNCTION__, __LINE__,
-+ GPIO_READ(CONFIG_SYS_FPGA_DONE)?"high":"low");
-+ return(GPIO_READ(CONFIG_SYS_FPGA_DONE)?FPGA_SUCCESS:FPGA_FAIL);
-+}
++
+
+/*
-+ * Set the FPGA's wr line to the specified level
++ * the actual reset code
+ */
-+int
-+fpga_wr_fn (int assert_write, int flush, int cookie)
-+{
-+ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+ PRINTF ("%s:%d: FPGA RW... %s ", __FUNCTION__, __LINE__,
-+ assert_write?"high":"low");
-+ GPIO_WRITE( CONFIG_SYS_FPGA_RW, !assert_write);
-+ return assert_write;
-+}
+
-+int
-+fpga_cs_fn (int assert_cs, int flush, int cookie)
-+{
-+ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+ PRINTF ("%s:%d: FPGA CS %s ", __FUNCTION__, __LINE__,
-+ assert_cs?"high":"low");
-+ GPIO_WRITE( CONFIG_SYS_FPGA_CS, !assert_cs);
-+ return assert_cs;
-+}
++reset:
++ /*
++ * set the cpu to SVC32 mode
++ */
++ mrs r0,cpsr
++ bic r0,r0,#0x1f
++ orr r0,r0,#0xd3
++ msr cpsr,r0
+
-+int
-+fpga_rdata_fn ( unsigned char *data, int cookie )
-+{
-+ PRINTF ("%s:%d: FPGA READ DATA %02X ", __FUNCTION__, __LINE__,
-+ *((char*)CONFIG_SYS_FPGA_RDATA));
-+ *data = (unsigned char)((*((unsigned short*)CONFIG_SYS_FPGA_RDATA))&0x00FF);
-+ return *data;
-+}
++ /*
++ * invalidate I/D cache/TLB and drain write buffer
++ */
++ mov r0, #0
++ mcr p15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
++ mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
++ mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */
+
-+int
-+fpga_wdata_fn ( unsigned char data, int cookie )
-+{
-+ PRINTF ("%s:%d: FPGA WRITE DATA %02X ", __FUNCTION__, __LINE__,
-+ data);
-+ *((unsigned short*)CONFIG_SYS_FPGA_WDATA) = data;
-+ return data;
-+}
++ /*
++ * disable MMU stuff and caches
++ */
++ mrc p15, 0, r0, c1, c0, 0
++ bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
++ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
++ orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
++ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
++ mcr p15, 0, r0, c1, c0, 0
++
++init_aipi_start:
++ init_aipi
+
-+int
-+fpga_abort_fn ( int cookie )
-+{
-+ return cookie;
-+}
++ /* check if sdram has been setup (running within sdram) */
++ cmp pc, #0xa0000000 /* start of first sdram memory space */
++ blo init_clock_start
++ cmp pc, #0xc0000000 /* end of second sdram memory space */
++ blo regular_boot
+
++ /* running from sdram with full code present -> regular_boot */
++init_clock_start:
++ init_clock
+
-+int
-+fpga_busy_fn ( int cookie )
-+{
-+ return 1;
-+}
++init_sdram_start:
++ bl setup_sdram_ddr
++
++ /* save state of previous boot (SDRAM is configured)*/
++ BACKUP_TRACE()
++
++ /* nand_boot BOOT_TRACE(1..13) */
++
++ nand_boot
++
++ BOOT_TRACE(14) /* start regular U-Boot */
++
++regular_boot: /* jump to start of next 2kiB block (U-Boot) */
++ ldr r0, =0xfffff800
++ and r0, r0, pc
++ add pc, r0, #0x800
++
++do_wait_op_done:
++ 1:
++ ldrh r3, [r12, #NFC_OFFSET_CONFIG2]
++ ands r3, r3, #NFC_CONFIG2_INT
++ beq 1b
++ mov r3, #0x0
++ strh r3, [r12, #NFC_OFFSET_CONFIG2]
++ mov pc, lr
++
++do_addr_input:
++ mov r9, lr
++ and r3, r3, #0xFF
++ strh r3, [r12, #NFC_OFFSET_FLASH_ADDR]
++ mov r3, #NFC_CONFIG2_FADD
++ strh r3, [r12, #NFC_OFFSET_CONFIG2]
++ bl do_wait_op_done
++ mov pc, r9
++
++Test_And_Copy_Buffer:
++ /* check for bad block (2 bits error in main or spare are)*/
++ BOOT_TRACE(9)
++ ldrh r4, [r12, #NFC_OFFSET_ECC_STATUS_RESULT]
++ ands r4, r4, #(NFC_ECC_STAT_ERROR2|(NFC_ECC_STAT_ERROR2<<NFC_ECC_STAT_ERM_SHFT))
++ bne Skip_Bad_Buffer
++
++ /* check BI byte of the current spare buffer */
++ ldr r4, =IMX_NFC_SPARE_AREA0
++ ldrh r3, [r12, #NFC_OFFSET_BUF_ADDR] /* for the current buffer */
++ orr r4, r3, lsl #0x04
++
++ /* at bi word offset 4. Fixme position change betwwen 8 and 16 bits bus */
++ ldrh r4, [r4, #0x04]
++ and r4, r4, #0x0FF00 /* has to be 0xFFxx */
++ cmp r4, #0x0FF00
++ bne Skip_Bad_Buffer
++
++Copy_Good_Buffer:
++ /* copying 512 bytes buffer */
++ BOOT_TRACE(10)
++1: ldmia r0!, {r3-r10}
++ stmia r11!, {r3-r10}
++ cmp r0, r2
++ blo 1b
++ b End_Of_Copy
++
++Skip_Bad_Buffer:
++ BOOT_TRACE(11)
++ /* bad pages do not contain valid data and have to be skip */
++ add r0, r0, #0x200
++
++ /* rewind ram addr to start of buffer */
++ ldr r3, =(~0x1FF)
++ and r11, r11, r3
++
++End_Of_Copy:
++ add r2, r2, #0x200
++ add r1, r1, #0x200
++
++ mov pc, lr
++
++
++setup_sdram_ddr:
+
-+int
-+fpga_post_fn (int cookie)
-+{
-+ struct gpio_regs *gpregs = (struct gpio_regs *)IMX_GPIO_BASE;
-+ PRINTF ("%s:%d: FPGA POST ", __FUNCTION__, __LINE__);
++ /* wait for SDRAM/LPDDR ready (SDRAMRDY) */
++ ldr r0, =ESDMISC
++ ldr r4, =ESDMISC_SDRAM_RDY
++2: ldr r1, [r0]
++ ands r1, r1, r4
++ bpl 2b
+
-+ imx_gpio_mode (CONFIG_SYS_FPGA_RW | GPIO_PF | GPIO_PUEN);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_CS | GPIO_PF | GPIO_PUEN);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_CLK | GPIO_PF | GPIO_PUEN);
-+ GPIO_SET(CONFIG_SYS_FPGA_PRG);
-+ GPIO_CLEAR(CONFIG_SYS_FPGA_RESET);
-+ imx_gpio_mode (CONFIG_SYS_FPGA_RESET | GPIO_OUT | GPIO_PUEN | GPIO_GPIO);
-+ return cookie;
-+}
++ /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
++ ldr r0, =ESDMISC
++ ldr r4, =CONFIG_SYS_ESDMISC_VAL
++ orr r1, r4, #ESDMISC_MDDR_DL_RST
++ str r1, [r0]
+
-+/*
-+ * Initialize the fpga. Return 1 on success, 0 on failure.
-+ */
-+int
-+APF27_init_fpga (u_char * buffer, size_t size)
-+{
-+ char *autoload = getenv ("firmware_autoload");
++ /* Hold for more than 200ns */
++ ldr r1, =0x10000
++ 1: subs r1, r1, #0x1
++ bne 1b
+
-+ int i,lout=0;
++ str r4, [r0]
+
-+ fpga_init();
++ writel(ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL)
+
-+ for (i = 0; i < CONFIG_FPGA_COUNT; i++) {
-+ PRINTF ("%s:%d: Adding fpga %d\n", __FUNCTION__, __LINE__, i);
-+ fpga_add (fpga_xilinx, &fpga[i]);
-+ }
++ /* writel(ESDCTL0, CONFIG_SYS_PRECHARGE_CMD) */
++ ldr r0, =ESDCTL0
++ ldr r1, =CONFIG_SYS_PRECHARGE_CMD
++ str r1, [r0]
+
-+ if ((size >= fpga[0].size) && ( autoload ) && (0 == strcmp(autoload, "1"))) {
-+ if (ctrlc()) {
-+ printf("Firmware download stopped!\n");
-+ } else if (FPGA_SUCCESS != fpga_load( 0,(void *)buffer, size )) {
-+ printf("Firmware download failed!\n");
-+ } else {
-+ printf("Firmware successfully programmed\n");
-+ lout = 1;
-+ }
-+ }
-+ return lout;
-+}
++ /* writeb(0xA0001000, any value) */
++ ldr r1, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
++ ldrb r2, [r1]
+
-+#endif /* CONFIG_FPGA */
-Index: u-boot-2010.03/board/armadeus/apf27/fpga.h
++ /* writel(ESDCTL0, CONFIG_SYS_AUTOREFRESH_CMD) */
++ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
++ str r1, [r0]
++
++ ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
++
++ ldr r6,=0x7 /* load loop counter */
++1: ldr r5,[r4] /* run auto-refresh cycle to array 0 */
++ subs r6,r6,#1 /* decrease counter value */
++ bne 1b
++
++ /* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_SET_MODE_REG_CMD) */
++ ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD
++ str r1, [r0]
++
++ /* set standard mode register */
++ ldr r4, = PHYS_SDRAM_1+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
++ ldrb r2, [r4]
++
++ /* set extended mode register */
++ ldr r4, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
++ ldrb r5, [r4]
++
++ /* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_NORMAL_RW_CMD) */
++ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
++ str r1, [r0]
++
++#if (CONFIG_NR_DRAM_BANKS > 1)
++ /* 2nd sdram */
++ writel(ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL )
++
++ /* writel(ESDCTL1, CONFIG_SYS_PRECHARGE_CMD) */
++ ldr r0, =ESDCTL1
++ ldr r1, =CONFIG_SYS_PRECHARGE_CMD
++ str r1, [r0]
++
++ /* writeb(0xB0001000, any value) */
++ ldr r1, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
++ ldrb r2, [r1]
++
++ /* writel(ESDCTL1, CONFIG_SYS_AUTOREFRESH_CMD) */
++ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
++ str r1, [r0]
++
++ ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
++
++ ldr r6,=0x7 /* load loop counter */
++1: ldr r5,[r4] /* run auto-refresh cycle to array 0 */
++ subs r6,r6,#1 /* decrease counter value */
++ bne 1b
++
++ /* writel(ESDCTL1, CONFIG_SYS_SET_MODE_REG_CMD) */
++ ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD
++ str r1, [r0]
++
++ /* set standard mode register */
++ ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
++ ldrb r2, [r4]
++
++ /* set extended mode register */
++ ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_EXT_MODE_REGISTER_VAL
++ ldrb r2, [r4]
++
++ /* writel(ESDCTL1, CONFIG_SYS_NORMAL_RW_CMD) */
++ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
++ str r1, [r0]
++#endif /* CONFIG_NR_DRAM_BANKS > 1 */
++
++ mov pc, lr
++
+Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/u-boot.lds
===================================================================
--- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/board/armadeus/apf27/fpga.h 2011-01-05 18:09:44.000000000 +0100
-@@ -0,0 +1,39 @@
++++ u-boot-2010.03/nand_spl/board/armadeus/apf27/u-boot.lds 2011-01-05 18:09:44.000000000 +0100
+@@ -0,0 +1,37 @@
+/*
-+ * (C) Copyright 2002-2008
-+ * Eric Jarrige <eri...@ar...>
-+ * Rich Ireland, Enterasys Networks, rir...@en....
-+ * Keith Outwater, kei...@mv....
++ * (C) Copyright 2007
++ * Stefan Roese, DENX Software Engineering, sr...@de....
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
@@ -1049,20 +1769,21 @@ Index: u-boot-2010.03/board/armadeus/apf27/fpga.h
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
-+ *
+ */
-+extern int APF27_init_fpga (u_char * buffer, size_t size);
+
-+extern int fpga_pre_fn (int cookie);
-+extern int fpga_pgm_fn (int assert_pgm, int flush, int cookie);
-+extern int fpga_cs_fn (int assert_cs, int flush, int cookie);
-+extern int fpga_init_fn (int cookie);
-+extern int fpga_done_fn (int cookie);
-+extern int fpga_clk_fn (int assert_clk, int flush, int cookie);
-+extern int fpga_wr_fn (int assert_write, int flush, int cookie);
-+extern int fpga_rdata_fn ( unsigned char *data, int cookie );
-+extern int fpga_wdata_fn ( unsigned char data, int cookie );
-+extern int fpga_abort_fn (int cookie);
-+extern int fpga_post_fn (int cookie);
-+extern int fpga_busy_fn (int cookie);
++OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
++OUTPUT_ARCH(arm)
++ENTRY(_start)
++SECTIONS
++{
++ . = 0x00000000;
++
++ . = ALIGN(4);
++ .text :
++ {
++ start.o (.text)
++ *(.text)
++ }
++}
+1.7.4.4
diff --git a/patches/u-boot/2011.12/304-Add-type-for-apf27.patch b/patches/u-boot/2011.12/304-Add-type-for-apf27.patch
deleted file mode 100644
index 29628c7..0000000
--- a/patches/u-boot/2011.12/304-Add-type-for-apf27.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-From bfedc74f6beae4f7bbb5f2ccf0c651a489fe7675 Mon Sep 17 00:00:00 2001
-From: Philippe Reynes <tr...@ya...>
-Date: Wed, 28 Dec 2011 14:26:52 +0100
-Subject: [PATCH 4/6] Add type for apf27
-
----
- arch/arm/include/asm/mach-types.h | 1 +
- 1 files changed, 1 insertions(+), 0 deletions(-)
-
-diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
-index 2d5c3bc..c38a816 100644
---- a/arch/arm/include/asm/mach-types.h
-+++ b/arch/arm/include/asm/mach-types.h
-@@ -286,6 +286,7 @@ extern unsigned int __machine_arch_type;
- #define MACH_TYPE_WBD111 1690
- #define MACH_TYPE_MV2120 1693
- #define MACH_TYPE_MX51_3DS 1696
-+#define MACH_TYPE_APF27 1698
- #define MACH_TYPE_IMX27LITE 1701
- #define MACH_TYPE_USB_A9260 1709
- #define MACH_TYPE_USB_A9263 1710
---
-1.7.4.4
-
diff --git a/patches/u-boot/2011.12/310-apf27-nand-spl.patch b/patches/u-boot/2011.12/310-apf27-nand-spl.patch
deleted file mode 100644
index daa8554..0000000
--- a/patches/u-boot/2011.12/310-apf27-nand-spl.patch
+++ /dev/null
@@ -1,721 +0,0 @@
-Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/config.mk
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/nand_spl/board/armadeus/apf27/config.mk 2011-01-05 18:09:44.000000000 +0100
-@@ -0,0 +1,43 @@
-+#
-+# (C) Copyright 2007
-+# Stefan Roese, DENX Software Engineering, sr...@de....
-+#
-+# See file CREDITS for list of people who contributed to this
-+# project.
-+#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; either version 2 of
-+# the License, or (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+# MA 02111-1307 USA
-+#
-+#
-+# This config file is used for compilation of armadeus apf27 board
-+#
-+
-+#
-+# TEXT_BASE for SPL:
-+#
-+#
-+# This config file is used for compilation of armadeus sources
-+#
-+# You might change location of U-Boot in memory by setting right TEXT_BASE.
-+# This allows for example having one copy located at the end of ram and stored
-+# in flash device and later on while developing use other location to test
-+# the code in RAM device only.
-+#
-+
-+TEXT_BASE = 0xa0000000
-+
-+# PAD_TO used to generate a 2kByte binary needed for the combined image
-+# -> PAD_TO = TEXT_BASE + 0x0800
-+PAD_TO = 0xa0000800
-Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/Makefile
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/nand_spl/board/armadeus/apf27/Makefile 2011-01-05 18:09:44.000000000 +0100
-@@ -0,0 +1,77 @@
-+#
-+# (C) Copyright 2007
-+# Stefan Roese, DENX Software Engineering, sr...@de....
-+#
-+# See file CREDITS for list of people who contributed to this
-+# project.
-+#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; either version 2 of
-+# the License, or (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+# MA 02111-1307 USA
-+#
-+
-+include $(TOPDIR)/config.mk
-+include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk
-+
-+LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds
-+LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS)
-+AFLAGS += -DCONFIG_NAND_SPL
-+CFLAGS += -DCONFIG_NAND_SPL
-+
-+SOBJS = start.o
-+COBJS =
-+
-+SRCS := $(addprefix $(src),$(SOBJS:.o=.S) $(COBJS:.o=.c))
-+OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS))
-+__OBJS := $(SOBJS) $(COBJS)
-+LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR)
-+
-+nandobj := $(OBJTREE)/nand_spl/
-+
-+ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-16k.bin \
-+ $(nandobj)System.map
-+
-+all: $(obj).depend $(ALL)
-+
-+$(nandobj)u-boot-spl-16k.bin: $(nandobj)u-boot-spl
-+ $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@
-+
-+$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl
-+ $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@
-+
-+$(nandobj)u-boot-spl: $(OBJS)
-+ cd $(LNDIR) && $(LD) $(LDFLAGS) $$UNDEF_SYM $(__OBJS) \
-+ -Map $(nandobj)u-boot-spl.map \
-+ -o $(nandobj)u-boot-spl
-+
-+$(nandobj)System.map: $(nandobj)u-boot-spl
-+ @$(NM) $< | \
-+ grep -v '\(compiled\)\|\(\.o$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \
-+ sort > $(nandobj)System.map
-+
-+
-+#########################################################################
-+
-+$(obj)%.o: %.S
-+ $(CC) $(AFLAGS) -c -o $@ $<
-+
-+$(obj)%.o: %.c
-+ $(CC) $(CFLAGS) -c -o $@ $<
-+
-+# defines $(obj).depend target
-+include $(SRCTREE)/rules.mk
-+
-+sinclude $(obj).depend
-+
-+#########################################################################
-Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S 2011-01-05 18:09:44.000000000 +0100
-@@ -0,0 +1,544 @@
-+/*
-+ * IMX27 NAND Flash SPL (Secondary Program Loader)
-+ *
-+ * Copyright (c) 2008 Armadeus Project / eja
-+ *
-+ * Based on Freescale NAND SPL
-+ *
-+ * Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-+ * Copyright (c) 2008 Eric Jarrige <eri...@ar...>
-+ *
-+ * See file CREDITS for list of people who contributed to this
-+ * project.
-+ *
-+ * This program is free software; you can redistribute it and/or
-+ * modify it under the terms of the GNU General Public License as
-+ * published by the Free Software Foundation; either version 2 of
-+ * the License, or (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+ * MA 02111-1307 USA
-+ */
-+
-+
-+#include <config.h>
-+#include <version.h>
-+#include <asm/arch/imx-regs.h>
-+
-+/*
-+ * Standard NAND flash commands
-+ */
-+#define NAND_CMD_READ0 0
-+#define NAND_CMD_READ1 1
-+#define NAND_CMD_PAGEPROG 0x10
-+#define NAND_CMD_READOOB 0x50
-+#define NAND_CMD_ERASE1 0x60
-+#define NAND_CMD_STATUS 0x70
-+#define NAND_CMD_STATUS_MULTI 0x71
-+#define NAND_CMD_SEQIN 0x80
-+#define NAND_CMD_READID 0x90
-+#define NAND_CMD_ERASE2 0xd0
-+#define NAND_CMD_RESET 0xff
-+
-+/* Extended commands for large page devices */
-+#define NAND_CMD_READSTART 0x30
-+#define NAND_CMD_CACHEDPROG 0x15
-+
-+/* Status bits */
-+#define NAND_STATUS_FAIL 0x01
-+#define NAND_STATUS_FAIL_N1 0x02
-+#define NAND_STATUS_TRUE_READY 0x20
-+#define NAND_STATUS_READY 0x40
-+#define NAND_STATUS_WP 0x80
-+
-+#define writel(reg, val) \
-+ ldr r0, =reg; \
-+ ldr r1, =val; \
-+ str r1, [r0];
-+
-+ .macro nand_boot
-+
-+#ifdef CONFIG_BOOT_TRACE_REG
-+/*
-+ * If CONFIG_BOOT_TRACE_REG is a SDRAM address then be sure to use the following
-+ * 2 command after SDRAM init
-+ */
-+
-+/* Backup state of previous boot to CONFIG_BOOT_TRACE_REG+4*/
-+#define BACKUP_TRACE() \
-+ ldr r4, =CONFIG_BOOT_TRACE_REG; \
-+ ldr r3, [r4]; \
-+ str r3, [r4, #0x04];
-+
-+/* Save a state of boot at CONFIG_BOOT_TRACE_REG */
-+#define BOOT_TRACE(val) \
-+ ldr r4, =CONFIG_BOOT_TRACE_REG; \
-+ ldr r3, =val; \
-+ str r3, [r4];
-+#else
-+#define BACKUP_TRACE()
-+#define BOOT_TRACE(val)
-+#endif
-+
-+nand_boot_setup:
-+
-+ /* Copy SPL image from flash to SDRAM first */
-+ BOOT_TRACE(1)
-+ ldr r0, =IMX_NFC_MAIN_AREA0
-+ add r2, r0, #(IMX_NFC_SPARE_AREA0-IMX_NFC_MAIN_AREA0) //2KB NFC Buff
-+ ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST
-+
-+ BOOT_TRACE(2)
-+1: ldmia r0!, {r3-r10}
-+ stmia r1!, {r3-r10}
-+ cmp r0, r2
-+ blo 1b
-+
-+
-+
-+ /* Jump to SDRAM */
-+ BOOT_TRACE(3)
-+ ldr r1, =0xFFF
-+ and r0, pc, r1 /* offset of pc */
-+ ldr r1, =CONFIG_SYS_NAND_U_BOOT_DST
-+ add r1, r1, #0x10
-+ add pc, r0, r1
-+ nop
-+ nop
-+ nop
-+ nop
-+
-+NAND_Copy_Main:
-+ BOOT_TRACE(4)
-+ /* r0: nfc base. Reloaded after each page copying */
-+ ldr r0, =IMX_NFC_MAIN_AREA0
-+
-+ /* r1: starting flash addr to be copied. Updated constantly */
-+ /* bypass the first preloaded pages */
-+ ldr r1, =(IMX_NFC_SPARE_AREA0-IMX_NFC_MAIN_AREA0)
-+
-+ /* r2: end of 1st RAM buf. Doesn't change */
-+ ldr r2, =IMX_NFC_MAIN_AREA1
-+
-+ /* r12: NFC register base. Doesn't change */
-+ ldr r12, =IMX_NFC_REGS
-+
-+ ldr r11, =CONFIG_SYS_NAND_U_BOOT_DST
-+
-+ /* r13: end of SDRAM address for copying. Doesn't change */
-+ add r13, r11, #CONFIG_SYS_NAND_U_BOOT_SIZE
-+
-+ /* r11: starting SDRAM address for copying. Updated constantly */
-+ add r11, r11, r1
-+
-+ /* unlock internal buffer */
-+ ldr r3, =NFC_CONFIG_UNLOCKED
-+ strh r3, [r12, #NFC_OFFSET_CONFIG]
-+
-+ /* enable ECC and mask interrupts */
-+ ldr r3, =(NFC_CONFIG1_ECC_EN | NFC_CONFIG1_INT_MSK)
-+ strh r3, [r12, #NFC_OFFSET_CONFIG1]
-+
-+Nfc_Read_Page:
-+ BOOT_TRACE(5)
-+ /* send NAND_CMD_READ0 command */
-+ ldr r3, =NAND_CMD_READ0;
-+ strh r3, [r12, #NFC_OFFSET_FLASH_CMD]
-+
-+ ldr r3, =NFC_CONFIG2_FCMD
-+ strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ bl do_wait_op_done
-+
-+ /* send NAND address to read. TODO small page support */
-+ BOOT_TRACE(6)
-+ mov r3, r1, lsr #1
-+ bl do_addr_input /* 1st addr cycle */
-+
-+ mov r3, r1, lsr #9
-+ and r3, r3, #0x03
-+ bl do_addr_input /* 2nd addr cycle */
-+
-+ mov r3, r1, lsr #11
-+ bl do_addr_input /* 3rd addr cycle */
-+
-+ mov r3, r1, lsr #19
-+ bl do_addr_input /* 4th addr cycle */
-+
-+ /* Small NAND flashs (== 1Gb) support 5 addr cycles */
-+ mov r3, r1, lsr #27
-+ bl do_addr_input /* 5th addr cycle */
-+
-+ /* send NAND_CMD_READSTART command. TODO small page support */
-+ BOOT_TRACE(7)
-+ mov r3, #NAND_CMD_READSTART;
-+ strh r3, [r12, #NFC_OFFSET_FLASH_CMD]
-+ mov r3, #NFC_CONFIG2_FCMD
-+ strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ bl do_wait_op_done
-+
-+ /* read and copy buf 0 */
-+ BOOT_TRACE(8)
-+ mov r3, #0
-+ strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
-+
-+ mov r3, #NFC_CONFIG2_FDO_PAGE
-+ strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ bl do_wait_op_done
-+
-+ bl Test_And_Copy_Buffer
-+
-+ /* read and copy buf 1 */
-+ mov r3, #1
-+ strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
-+
-+ mov r3, #NFC_CONFIG2_FDO_PAGE
-+ strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ bl do_wait_op_done
-+
-+ bl Test_And_Copy_Buffer
-+
-+ /* here we should test if 512B page flash and bypass next buffers */
-+ /* read and copy buf 2. TODO small page support */
-+ mov r3, #2
-+ strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
-+
-+ mov r3, #NFC_CONFIG2_FDO_PAGE
-+ strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ bl do_wait_op_done
-+
-+ bl Test_And_Copy_Buffer
-+
-+ /* read and copy buf 3 */
-+ mov r3, #3
-+ strh r3, [r12, #NFC_OFFSET_BUF_ADDR]
-+
-+ mov r3, #NFC_CONFIG2_FDO_PAGE
-+ strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ bl do_wait_op_done
-+
-+ bl Test_And_Copy_Buffer
-+
-+ /* is the last page ? */
-+ BOOT_TRACE(12)
-+ cmp r11, r13
-+ bge NAND_Copy_Main_done
-+
-+ /* r0: nfc base. Reloaded after each page copying */
-+ ldr r0, =IMX_NFC_MAIN_AREA0
-+ /* r2: end of 1st RAM buf. Doesn't change */
-+ ldr r2, =IMX_NFC_MAIN_AREA1
-+ b Nfc_Read_Page
-+
-+NAND_Copy_Main_done:
-+ BOOT_TRACE(13)
-+ .endm /* nand_boot */
-+
-+ .macro init_aipi
-+ /*
-+ * setup AIPI1 and AIPI2
-+ */
-+ writel(AIPI1_PSR0, CONFIG_SYS_AIPI1_PSR0_VAL)
-+ writel(AIPI1_PSR1, CONFIG_SYS_AIPI1_PSR1_VAL)
-+ writel(AIPI2_PSR0, CONFIG_SYS_AIPI2_PSR0_VAL)
-+ writel(AIPI2_PSR1, CONFIG_SYS_AIPI2_PSR1_VAL)
-+
-+ /* Change SDRAM signal strengh */
-+ ldr r0, =GPCR
-+ ldr r1, =CONFIG_SYS_GPCR_VAL
-+ ldr r5, [r0]
-+ orr r5, r5, r1
-+ str r5, [r0]
-+
-+ .endm /* init_aipi */
-+
-+ .macro init_clock
-+ ldr r0, =CSCR
-+ /* disable MPLL/SPLL first */
-+ ldr r1, [r0]
-+ bic r1, r1, #(CSCR_MPEN|CSCR_SPEN)
-+ str r1, [r0]
-+
-+ /*
-+ * pll clock initialization predefined in apf27.h
-+ */
-+ writel(MPCTL0, CONFIG_SYS_MPCTL0_VAL)
-+ writel(SPCTL0, CONFIG_SYS_SPCTL0_VAL)
-+
-+ writel(CSCR, CONFIG_SYS_CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART)
-+
-+ /*
-+ * add some delay here
-+ */
-+ mov r1, #0x1000
-+ 1: subs r1, r1, #0x1
-+ bne 1b
-+
-+ /* peripheral clock divider */
-+ writel(PCDR0, CONFIG_SYS_PCDR0_VAL)
-+ writel(PCDR1, CONFIG_SYS_PCDR1_VAL)
-+
-+ /* Configure PCCR0 and PCCR1 */
-+ writel(PCCR0, CONFIG_SYS_PCCR0_VAL)
-+ writel(PCCR1, CONFIG_SYS_PCCR1_VAL)
-+
-+ .endm /* init_clock */
-+
-+/*
-+ *************************************************************************
-+ *
-+ * No jump vector table. Use reset vector as direct entry point.
-+ * Do not support any interrupt event within SPL
-+ *
-+ *************************************************************************
-+ */
-+
-+
-+.globl _start
-+_start:
-+
-+/*
-+ *************************************************************************
-+ *
-+ * Startup Code (reset vector)
-+ *
-+ * do important init only if we don't start from memory!
-+ * setup Memory and board specific bits prior to relocation.
-+ * relocate armboot to ram
-+ * setup stack
-+ *
-+ *************************************************************************
-+ */
-+
-+
-+/*
-+ * the actual reset code
-+ */
-+
-+reset:
-+ /*
-+ * set the cpu to SVC32 mode
-+ */
-+ mrs r0,cpsr
-+ bic r0,r0,#0x1f
-+ orr r0,r0,#0xd3
-+ msr cpsr,r0
-+
-+ /*
-+ * invalidate I/D cache/TLB and drain write buffer
-+ */
-+ mov r0, #0
-+ mcr p15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
-+ mcr p15, 0, r0, c8, c7, 0 /* invalidate TLBs */
-+ mcr p15, 0, r0, c7, c10, 4 /* Drain the write buffer */
-+
-+ /*
-+ * disable MMU stuff and caches
-+ */
-+ mrc p15, 0, r0, c1, c0, 0
-+ bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */
-+ bic r0, r0, #0x00000087 /* clear bits 7, 2:0 (B--- -CAM) */
-+ orr r0, r0, #0x00000002 /* set bit 2 (A) Align */
-+ orr r0, r0, #0x00001000 /* set bit 12 (I) I-Cache */
-+ mcr p15, 0, r0, c1, c0, 0
-+
-+init_aipi_start:
-+ init_aipi
-+
-+ /* check if sdram has been setup (running within sdram) */
-+ cmp pc, #0xa0000000 /* start of first sdram memory space */
-+ blo init_clock_start
-+ cmp pc, #0xc0000000 /* end of second sdram memory space */
-+ blo regular_boot
-+
-+ /* running from sdram with full code present -> regular_boot */
-+init_clock_start:
-+ init_clock
-+
-+init_sdram_start:
-+ bl setup_sdram_ddr
-+
-+ /* save state of previous boot (SDRAM is configured)*/
-+ BACKUP_TRACE()
-+
-+ /* nand_boot BOOT_TRACE(1..13) */
-+
-+ nand_boot
-+
-+ BOOT_TRACE(14) /* start regular U-Boot */
-+
-+regular_boot: /* jump to start of next 2kiB block (U-Boot) */
-+ ldr r0, =0xfffff800
-+ and r0, r0, pc
-+ add pc, r0, #0x800
-+
-+do_wait_op_done:
-+ 1:
-+ ldrh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ ands r3, r3, #NFC_CONFIG2_INT
-+ beq 1b
-+ mov r3, #0x0
-+ strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ mov pc, lr
-+
-+do_addr_input:
-+ mov r9, lr
-+ and r3, r3, #0xFF
-+ strh r3, [r12, #NFC_OFFSET_FLASH_ADDR]
-+ mov r3, #NFC_CONFIG2_FADD
-+ strh r3, [r12, #NFC_OFFSET_CONFIG2]
-+ bl do_wait_op_done
-+ mov pc, r9
-+
-+Test_And_Copy_Buffer:
-+ /* check for bad block (2 bits error in main or spare are)*/
-+ BOOT_TRACE(9)
-+ ldrh r4, [r12, #NFC_OFFSET_ECC_STATUS_RESULT]
-+ ands r4, r4, #(NFC_ECC_STAT_ERROR2|(NFC_ECC_STAT_ERROR2<<NFC_ECC_STAT_ERM_SHFT))
-+ bne Skip_Bad_Buffer
-+
-+ /* check BI byte of the current spare buffer */
-+ ldr r4, =IMX_NFC_SPARE_AREA0
-+ ldrh r3, [r12, #NFC_OFFSET_BUF_ADDR] /* for the current buffer */
-+ orr r4, r3, lsl #0x04
-+
-+ /* at bi word offset 4. Fixme position change betwwen 8 and 16 bits bus */
-+ ldrh r4, [r4, #0x04]
-+ and r4, r4, #0x0FF00 /* has to be 0xFFxx */
-+ cmp r4, #0x0FF00
-+ bne Skip_Bad_Buffer
-+
-+Copy_Good_Buffer:
-+ /* copying 512 bytes buffer */
-+ BOOT_TRACE(10)
-+1: ldmia r0!, {r3-r10}
-+ stmia r11!, {r3-r10}
-+ cmp r0, r2
-+ blo 1b
-+ b End_Of_Copy
-+
-+Skip_Bad_Buffer:
-+ BOOT_TRACE(11)
-+ /* bad pages do not contain valid data and have to be skip */
-+ add r0, r0, #0x200
-+
-+ /* rewind ram addr to start of buffer */
-+ ldr r3, =(~0x1FF)
-+ and r11, r11, r3
-+
-+End_Of_Copy:
-+ add r2, r2, #0x200
-+ add r1, r1, #0x200
-+
-+ mov pc, lr
-+
-+
-+setup_sdram_ddr:
-+
-+ /* wait for SDRAM/LPDDR ready (SDRAMRDY) */
-+ ldr r0, =ESDMISC
-+ ldr r4, =ESDMISC_SDRAM_RDY
-+2: ldr r1, [r0]
-+ ands r1, r1, r4
-+ bpl 2b
-+
-+ /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
-+ ldr r0, =ESDMISC
-+ ldr r4, =CONFIG_SYS_ESDMISC_VAL
-+ orr r1, r4, #ESDMISC_MDDR_DL_RST
-+ str r1, [r0]
-+
-+ /* Hold for more than 200ns */
-+ ldr r1, =0x10000
-+ 1: subs r1, r1, #0x1
-+ bne 1b
-+
-+ str r4, [r0]
-+
-+ writel(ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL)
-+
-+ /* writel(ESDCTL0, CONFIG_SYS_PRECHARGE_CMD) */
-+ ldr r0, =ESDCTL0
-+ ldr r1, =CONFIG_SYS_P...
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