[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-316-g6783f97
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[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-316-g6783f97
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From: jorasse <jo...@us...> - 2012-05-22 23:19:41
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The branch, master has been updated
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from 0da920b941b3c8c8144d0181c4ffec7f9ad5767c (commit)
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- Log -----------------------------------------------------------------
commit 6783f97581a28c6e5bdb2efb9b828cba54e2ad5e
Author: Philippe Reynes <tr...@ya...>
Date: Wed May 23 01:18:56 2012 +0200
[UBOOT] apf27: refactoring to be aligned with U-Boot 2011.12 coding conventions
-----------------------------------------------------------------------
Summary of changes:
...dule-and-I-O-Multiplexer-constant-for-mx2.patch | 295 +++++--------
...-Add-support-for-the-armadeus-apf27-board.patch | 449 +++++++++++---------
.../u-boot/2011.12/340-apf27-misc-commands.patch | 63 ++-
3 files changed, 396 insertions(+), 411 deletions(-)
diff --git a/patches/u-boot/2011.12/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch b/patches/u-boot/2011.12/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
index c60fcba..8e80e02 100644
--- a/patches/u-boot/2011.12/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
+++ b/patches/u-boot/2011.12/301-Add-GPIO-Module-and-I-O-Multiplexer-constant-for-mx2.patch
@@ -1,134 +1,67 @@
-From c454b2c2ed3a4be1a0809c0f0fa49f46559e1fa6 Mon Sep 17 00:00:00 2001
-From: Philippe Reynes <tr...@ya...>
-Date: Sun, 25 Sep 2011 11:22:00 +0200
-Subject: [PATCH 1/6] Add GPIO Module and I/O Multiplexer constant for mx27
+Add WEIM, NFC SYSTEM_CTLconstants to the mx27 CPU
Signed-off-by: Philippe Reynes <tr...@ya...>
---
- arch/arm/include/asm/arch-mx27/imx-regs.h | 216 +++++++++++++++++++++++++++++
- 1 files changed, 216 insertions(+), 0 deletions(-)
+ arch/arm/cpu/arm926ejs/mx27/asm-offsets.c | 28 +++++++++++
+ arch/arm/include/asm/arch-mx27/imx-regs.h | 9 ++++
+ arch/arm/include/asm/arch-mx27/mxc_nand.h | 73 +++++++++++++++++++++++++++++
+ 3 files changed, 110 insertions(+), 0 deletions(-)
+ create mode 100644 arch/arm/include/asm/arch-mx27/mxc_nand.h
+diff --git a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
+index f3a8d7b..7dad00f 100644
+--- a/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
++++ b/arch/arm/cpu/arm926ejs/mx27/asm-offsets.c
+@@ -34,6 +34,7 @@ int main(void)
+ DEFINE(PCDR1, IMX_PLL_BASE + offsetof(struct pll_regs, pcdr1));
+ DEFINE(PCCR0, IMX_PLL_BASE + offsetof(struct pll_regs, pccr0));
+ DEFINE(PCCR1, IMX_PLL_BASE + offsetof(struct pll_regs, pccr1));
++ DEFINE(CCSR, IMX_PLL_BASE + offsetof(struct pll_regs, ccsr));
+
+ DEFINE(ESDCTL0_ROF, offsetof(struct esdramc_regs, esdctl0));
+ DEFINE(ESDCFG0_ROF, offsetof(struct esdramc_regs, esdcfg0));
+@@ -41,5 +42,32 @@ int main(void)
+ DEFINE(ESDCFG1_ROF, offsetof(struct esdramc_regs, esdcfg1));
+ DEFINE(ESDMISC_ROF, offsetof(struct esdramc_regs, esdmisc));
+
++ DEFINE(GPCR, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, gpcr));
++ DEFINE(FMCR, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, fmcr));
++ DEFINE(DSCR2, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr2));
++ DEFINE(DSCR3, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr3));
++ DEFINE(DSCR7, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr7));
++ DEFINE(DSCR10, IMX_SYSTEM_CTL_BASE + offsetof(struct system_control_regs, dscr10));
++
++ DEFINE(CS0U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0u));
++ DEFINE(CS0L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0l));
++ DEFINE(CS0A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs0a));
++ DEFINE(CS1U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1u));
++ DEFINE(CS1L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1l));
++ DEFINE(CS1A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs1a));
++ DEFINE(CS2U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2u));
++ DEFINE(CS2L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2l));
++ DEFINE(CS2A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs2a));
++ DEFINE(CS3U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3u));
++ DEFINE(CS3L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3l));
++ DEFINE(CS3A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs3a));
++ DEFINE(CS4U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4u));
++ DEFINE(CS4L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4l));
++ DEFINE(CS4A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs4a));
++ DEFINE(CS5U, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5u));
++ DEFINE(CS5L, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5l));
++ DEFINE(CS5A, IMX_WEIM_BASE + offsetof(struct weim_regs, cs5a));
++ DEFINE(EIM, IMX_WEIM_BASE + offsetof(struct weim_regs, eim));
++
+ return 0;
+ }
diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
-index ced5b2a..f1c0ce7 100644
+index ced5b2a..4df67d6 100644
--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
-@@ -522,4 +522,220 @@ struct fuse_bank0_regs {
+@@ -522,4 +522,13 @@ struct fuse_bank0_regs {
#define IIM_ERR_SNSE (1 << 2)
#define IIM_ERR_PARITYE (1 << 1)
-+/* IIM Control Registers */
-+#define IIM_BANK_AREA IMX_IIM_BASE + 0x800
-+#define IIM_BANK_REG(x,y) (IIM_BANK_AREA + 0x400 * x + (y<<2))
-+
-+# ifdef __ASSEMBLY__
-+# define __REG(x) (x)
-+# define __REG16(x) (x)
-+# define __REG2(x,y) ((x)+(y))
-+
+/*
-+ * GPIO Module and I/O Multiplexer
-+ */
-+#define PORTA 0
-+#define PORTB 1
-+#define PORTC 2
-+#define PORTD 3
-+#define PORTE 4
-+#define PORTF 5
-+
-+#define AIPI1_PSR0 __REG(IMX_AIPI1_BASE + 0x00)
-+#define AIPI1_PSR1 __REG(IMX_AIPI1_BASE + 0x04)
-+#define AIPI2_PSR0 __REG(IMX_AIPI2_BASE + 0x00)
-+#define AIPI2_PSR1 __REG(IMX_AIPI2_BASE + 0x04)
-+
-+/* System Control */
-+#define FMCR __REG(IMX_SYSTEM_CTL_BASE + 0x14)
-+#define GPCR __REG(IMX_SYSTEM_CTL_BASE + 0x18)
-+#define WBCR __REG(IMX_SYSTEM_CTL_BASE + 0x1C)
-+#define DSCR1 __REG(IMX_SYSTEM_CTL_BASE + 0x20)
-+#define DSCR2 __REG(IMX_SYSTEM_CTL_BASE + 0x24)
-+#define DSCR3 __REG(IMX_SYSTEM_CTL_BASE + 0x28)
-+#define DSCR4 __REG(IMX_SYSTEM_CTL_BASE + 0x2C)
-+#define DSCR5 __REG(IMX_SYSTEM_CTL_BASE + 0x30)
-+#define DSCR6 __REG(IMX_SYSTEM_CTL_BASE + 0x34)
-+#define DSCR7 __REG(IMX_SYSTEM_CTL_BASE + 0x38)
-+#define DSCR8 __REG(IMX_SYSTEM_CTL_BASE + 0x3C)
-+#define DSCR9 __REG(IMX_SYSTEM_CTL_BASE + 0x40)
-+#define DSCR10 __REG(IMX_SYSTEM_CTL_BASE + 0x44)
-+#define DSCR11 __REG(IMX_SYSTEM_CTL_BASE + 0x48)
-+#define DSCR12 __REG(IMX_SYSTEM_CTL_BASE + 0x4C)
-+#define DSCR13 __REG(IMX_SYSTEM_CTL_BASE + 0x50)
-+#define PSCR __REG(IMX_SYSTEM_CTL_BASE + 0x54)
-+#define PMCR __REG(IMX_SYSTEM_CTL_BASE + 0x58)
-+#define DCVR0 __REG(IMX_SYSTEM_CTL_BASE + 0x60)
-+#define DCVR1 __REG(IMX_SYSTEM_CTL_BASE + 0x64)
-+#define DCVR2 __REG(IMX_SYSTEM_CTL_BASE + 0x68)
-+#define DCVR3 __REG(IMX_SYSTEM_CTL_BASE + 0x6C)
-+
-+/* Chip Select Registers */
-+#define CS0U __REG(IMX_WEIM_BASE + 0x00) /* Chip Select 0 Upper Register */
-+#define CS0L __REG(IMX_WEIM_BASE + 0x04) /* Chip Select 0 Lower Register */
-+#define CS0A __REG(IMX_WEIM_BASE + 0x08) /* Chip Select 0 Addition Register */
-+#define CS1U __REG(IMX_WEIM_BASE + 0x10) /* Chip Select 1 Upper Register */
-+#define CS1L __REG(IMX_WEIM_BASE + 0x14) /* Chip Select 1 Lower Register */
-+#define CS1A __REG(IMX_WEIM_BASE + 0x18) /* Chip Select 1 Addition Register */
-+#define CS2U __REG(IMX_WEIM_BASE + 0x20) /* Chip Select 2 Upper Register */
-+#define CS2L __REG(IMX_WEIM_BASE + 0x24) /* Chip Select 2 Lower Register */
-+#define CS2A __REG(IMX_WEIM_BASE + 0x28) /* Chip Select 2 Addition Register */
-+#define CS3U __REG(IMX_WEIM_BASE + 0x30) /* Chip Select 3 Upper Register */
-+#define CS3L __REG(IMX_WEIM_BASE + 0x34) /* Chip Select 3 Lower Register */
-+#define CS3A __REG(IMX_WEIM_BASE + 0x38) /* Chip Select 3 Addition Register */
-+#define CS4U __REG(IMX_WEIM_BASE + 0x40) /* Chip Select 4 Upper Register */
-+#define CS4L __REG(IMX_WEIM_BASE + 0x44) /* Chip Select 4 Lower Register */
-+#define CS4A __REG(IMX_WEIM_BASE + 0x48) /* Chip Select 4 Addition Register */
-+#define CS5U __REG(IMX_WEIM_BASE + 0x50) /* Chip Select 5 Upper Register */
-+#define CS5L __REG(IMX_WEIM_BASE + 0x54) /* Chip Select 5 Lower Register */
-+#define CS5A __REG(IMX_WEIM_BASE + 0x58) /* Chip Select 5 Addition Register */
-+#define EIM __REG(IMX_WEIM_BASE + 0x60) /* WEIM Configuration Register */
-+
-+/* SDRAM Controller registers */
-+#define ESDCTL0 __REG(IMX_ESD_BASE + 0x00) /* Enhanced SDRAM Control Register 0 */
-+#define ESDCFG0 __REG(IMX_ESD_BASE + 0x04) /* Enhanced SDRAM Configuration Register 0 */
-+#define ESDCTL1 __REG(IMX_ESD_BASE + 0x08) /* Enhanced SDRAM Control Register 1 */
-+#define ESDCFG1 __REG(IMX_ESD_BASE + 0x0C) /* Enhanced SDRAM Configuration Register 1 */
-+#define ESDMISC __REG(IMX_ESD_BASE + 0x10) /* Enhanced SDRAM Miscellanious Register */
-+
-+/* PLL registers */
-+#define CSCR __REG(IMX_PLL_BASE + 0x00) /* Clock Source Control Register */
-+#define MPCTL0 __REG(IMX_PLL_BASE + 0x04) /* MCU PLL Control Register 0 */
-+#define MPCTL1 __REG(IMX_PLL_BASE + 0x08) /* MCU PLL Control Register 1 */
-+#define SPCTL0 __REG(IMX_PLL_BASE + 0x0c) /* System PLL Control Register 0 */
-+#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
-+#define OSC26MCTL __REG(IMX_PLL_BASE + 0x14) /* Oscillator 26M Register */
-+#define PCDR0 __REG(IMX_PLL_BASE + 0x18) /* Peripheral Clock Divider Register 0 */
-+#define PCDR1 __REG(IMX_PLL_BASE + 0x1c) /* Peripheral Clock Divider Register 1 */
-+#define PCCR0 __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Control Register 0 */
-+#define PCCR1 __REG(IMX_PLL_BASE + 0x24) /* Peripheral Clock Control Register 1 */
-+#define CCSR __REG(IMX_PLL_BASE + 0x28) /* Clock Control Status Register */
-+
-+#define DDIR(x) __REG2(IMX_GPIO_BASE + 0x00, ((x) & 7) << 8)
-+#define OCR1(x) __REG2(IMX_GPIO_BASE + 0x04, ((x) & 7) << 8)
-+#define OCR2(x) __REG2(IMX_GPIO_BASE + 0x08, ((x) & 7) << 8)
-+#define ICONFA1(x) __REG2(IMX_GPIO_BASE + 0x0c, ((x) & 7) << 8)
-+#define ICONFA2(x) __REG2(IMX_GPIO_BASE + 0x10, ((x) & 7) << 8)
-+#define ICONFB1(x) __REG2(IMX_GPIO_BASE + 0x14, ((x) & 7) << 8)
-+#define ICONFB2(x) __REG2(IMX_GPIO_BASE + 0x18, ((x) & 7) << 8)
-+#define DR(x) __REG2(IMX_GPIO_BASE + 0x1c, ((x) & 7) << 8)
-+#define GIUS(x) __REG2(IMX_GPIO_BASE + 0x20, ((x) & 7) << 8)
-+#define SSR(x) __REG2(IMX_GPIO_BASE + 0x24, ((x) & 7) << 8)
-+#define ICR1(x) __REG2(IMX_GPIO_BASE + 0x28, ((x) & 7) << 8)
-+#define ICR2(x) __REG2(IMX_GPIO_BASE + 0x2c, ((x) & 7) << 8)
-+#define IMR(x) __REG2(IMX_GPIO_BASE + 0x30, ((x) & 7) << 8)
-+#define ISR(x) __REG2(IMX_GPIO_BASE + 0x34, ((x) & 7) << 8)
-+#define GPR(x) __REG2(IMX_GPIO_BASE + 0x38, ((x) & 7) << 8)
-+#define SWR(x) __REG2(IMX_GPIO_BASE + 0x3c, ((x) & 7) << 8)
-+#define PUEN(x) __REG2(IMX_GPIO_BASE + 0x40, ((x) & 7) << 8)
-+
-+ /* Macros to get byte and bit positions of ECC
-+ */
-+#define COLPOS(x) ((x) >> 4)
-+#define BITPOS(x) ((x)& 0xf)
-+
-+/**
+ * Memory areas of the NFC
+ */
+#define IMX_NFC_BASE (0xD8000000)
@@ -137,6 +70,38 @@ index ced5b2a..f1c0ce7 100644
+#define IMX_NFC_SPARE_AREA0 (0xD8000800)
+#define IMX_NFC_REGS (0xD8000E00)
+
+ #endif /* _IMX_REGS_H */
+diff --git a/arch/arm/include/asm/arch-mx27/mxc_nand.h b/arch/arm/include/asm/arch-mx27/mxc_nand.h
+new file mode 100644
+index 0000000..99af18b
+--- /dev/null
++++ b/arch/arm/include/asm/arch-mx27/mxc_nand.h
+@@ -0,0 +1,73 @@
++/*
++ * (c) 2012 Philippe Reynes <tr...@ya...>
++ *
++ * See file CREDITS for list of people who contributed to this
++ * project.
++ *
++ * This program is free software; you can redistribute it and/or
++ * modify it under the terms of the GNU General Public License as
++ * published by the Free Software Foundation; either version 2 of
++ * the License, or (at your option) any later version.
++ *
++ * This program is distributed in the hope that it will be useful,
++ * but WITHOUT ANY WARRANTY; without even the implied warranty of
++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
++ * GNU General Public License for more details.
++ *
++ * You should have received a copy of the GNU General Public License
++ * along with this program; if not, write to the Free Software
++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
++ * MA 02111-1307 USA
++ */
++
++#ifndef __MXC_NAND_H
++#define __MXC_NAND_H
++
+/*
+ * NFC registers address offest
+ */
@@ -157,82 +122,34 @@ index ced5b2a..f1c0ce7 100644
+#define NFC_OFFSET_CONFIG1 (0x1A) /* Nand Flash Operation Configuration 1 */
+#define NFC_OFFSET_CONFIG2 (0x1C) /* Nand Flash Operation Configuration 2 */
+
-+/*
-+ * NFC registers
-+ */
-+ /* Internal SRAM Size */
-+#define NFC_BUFSIZE __REG16(IMX_NFC_REGS + NFC_OFFSET_BUFSIZE)
-+ /* NAND Flash Block Address for Lock Check */
-+#define NFC_BLCK_ADD_LOCK __REG16(IMX_NFC_REGS + NFC_OFFSET_BLCK_ADD_LOCK)
-+ /* Buffer Number for Page Data Transfer To From Flash Memory */
-+#define NFC_BUF_ADDR __REG16(IMX_NFC_REGS + NFC_OFFSET_BUF_ADDR)
-+ /* NAND Flash Address */
-+#define NFC_FLASH_ADDR __REG16(IMX_NFC_REGS + NFC_OFFSET_FLASH_ADDR)
-+ /* NAND Flash Command */
-+#define NFC_FLASH_CMD __REG16(IMX_NFC_REGS + NFC_OFFSET_FLASH_CMD)
-+ /* NFC Internal Buffer Lock Control */
-+#define NFC_CONFIG __REG16(IMX_NFC_REGS + NFC_OFFSET_CONFIG)
-+ /* Controller Status/Result of Flash Operation */
-+#define NFC_ECC_STATUS_RESULT __REG16(IMX_NFC_REGS + NFC_OFFSET_ECC_STATUS_RESULT)
-+ /* ECC Error Position of Main Area Data Error */
-+#define NFC_ECC_RSLT_MAIN_AREA __REG16(IMX_NFC_REGS + NFC_OFFSET_ECC_RSLT_MAIN_AREA)
-+ /* ECC Error Position of Spare Area Data Error */
-+#define NFC_ECC_RSLT_SPARE_AREA __REG16(IMX_NFC_REGS + NFC_OFFSET_ECC_RSLT_SPARE_AREA)
-+ /* Nand Flash Write Protection */
-+#define NFC_WRPROT __REG16(IMX_NFC_REGS + NFC_OFFSET_WRPROT)
-+ /* Start Address for Write Protection Unlock */
-+#define NFC_UNLOCKSTART_BLKADDR __REG16(IMX_NFC_REGS + NFC_OFFSET_UNLOCKSTART_BLKADDR)
-+ /* End Address for Write Protection Unlock */
-+#define NFC_UNLOCKEND_BLKADDR __REG16(IMX_NFC_REGS + NFC_OFFSET_UNLOCKEND_BLKADDR)
-+ /* Current Nand Flash Write Protection Status */
-+#define NFC_WRPR_STAT __REG16(IMX_NFC_REGS + NFC_OFFSET_WRPR_STAT)
-+ /* Nand Flash Operation Configuration 1 */
-+#define NFC_CONFIG1 __REG16(IMX_NFC_REGS + NFC_OFFSET_CONFIG1)
-+ /* Nand Flash Operation Configuration 2 */
-+#define NFC_CONFIG2 __REG16(IMX_NFC_REGS + NFC_OFFSET_CONFIG2)
-+
+/* NFC_ECC_STATUS_RESULT Status Register Bit Fields */
-+#define NFC_ECC_STAT_ERM_SHFT (2) /* ERM shift */
-+#define NFC_ECC_STAT_ERS_MASK (0x03) /* ERS mask */
-+#define NFC_ECC_STAT_ERROR1 (1<<0) /* correctable error */
-+#define NFC_ECC_STAT_ERROR2 (1<<1) /* non correctable error */
++#define NFC_ECC_STAT_ERM_SHFT (2) /* ERM shift */
++#define NFC_ECC_STAT_ERS_MASK (0x03) /* ERS mask */
++#define NFC_ECC_STAT_ERROR1 (1<<0) /* correctable error */
++#define NFC_ECC_STAT_ERROR2 (1<<1) /* non correctable error */
+
+/* NFC_CONFIG Control Register Bit Fields */
-+#define NFC_CONFIG_UNLOCKED (1<<1) /* unlocked */
-+#define NFC_CONFIG_LOCKED (1<<0) /* locked */
-+/* NFC_WRPROT Control Register Bit Fields */
-+#define NFC_WRPROT_UNLOCKBLK (4<<0) /* unlock block according to given address range */
-+#define NFC_WRPROT_LOCKALL (2<<0) /* lock all */
-+#define NFC_WRPROT_LOCKTIGHT (1<<0) /* lock-tight locked blocks */
-+/* NFC_WRPR_STAT Status Register Bit Fields */
-+#define NFC_WRPR_US (1<<2) /* Unlocked status */
-+#define NFC_WRPR_LS (1<<1) /* Locked status */
-+#define NFC_WRPR_LTS (1<<0) /* Lock-tight Status */
++#define NFC_CONFIG_UNLOCKED (1<<1) /* unlocked */
++#define NFC_CONFIG_LOCKED (1<<0) /* locked */
++
+/* NFC_CONFIG1 Control Register Bit Fields */
-+#define NFC_CONFIG1_CEn (1<<7) /* Flash force CE */
-+#define NFC_CONFIG1_RST (1<<6) /* Reset */
-+#define NFC_CONFIG1_BIG (1<<5) /* Big Endian Mode */
-+#define NFC_CONFIG1_INT_MSK (1<<4) /* Mask Interrupt Bit */
-+#define NFC_CONFIG1_ECC_EN (1<<3) /* ECC operation enable */
-+#define NFC_CONFIG1_SP_EN (1<<2) /* Flash spare enable */
-+/* NFC_CONFIG2 Control Register Bit Fields */
-+#define NFC_CONFIG2_INT (1<<15) /* Interrupt */
-+#define NFC_CONFIG2_FDO_STATUS (4<<3) /* Flash status output */
-+#define NFC_CONFIG2_FDO_ID (2<<3) /* Flash ID output */
-+#define NFC_CONFIG2_FDO_PAGE (1<<3) /* Flash data output */
-+#define NFC_CONFIG2_FDI (1<<2) /* Flash data input */
-+#define NFC_CONFIG2_FADD (1<<1) /* Flash address input */
-+#define NFC_CONFIG2_FCMD (1<<0) /* Flash command input */
++#define NFC_CONFIG1_CEn (1<<7) /* Flash force CE */
++#define NFC_CONFIG1_RST (1<<6) /* Reset */
++#define NFC_CONFIG1_BIG (1<<5) /* Big Endian Mode */
++#define NFC_CONFIG1_INT_MSK (1<<4) /* Mask Interrupt Bit */
++#define NFC_CONFIG1_ECC_EN (1<<3) /* ECC operation enable */
++#define NFC_CONFIG1_SP_EN (1<<2) /* Flash spare enable */
+
-+#define NAND_CMD_LOCK 0x2a
-+#define NAND_CMD_LOCK_TIGHT 0x2c
-+#define NAND_CMD_UNLOCK1 0x23
-+#define NAND_CMD_UNLOCK2 0x24
-+#define NAND_CMD_LOCK_STATUS 0x7a
++/* NFC_CONFIG2 Control Register Bit Fields */
++#define NFC_CONFIG2_INT (1<<15) /* Interrupt */
++#define NFC_CONFIG2_FDO_STATUS (4<<3) /* Flash status output */
++#define NFC_CONFIG2_FDO_ID (2<<3) /* Flash ID output */
++#define NFC_CONFIG2_FDO_PAGE (1<<3) /* Flash data output */
++#define NFC_CONFIG2_FDI (1<<2) /* Flash data input */
++#define NFC_CONFIG2_FADD (1<<1) /* Flash address input */
++#define NFC_CONFIG2_FCMD (1<<0) /* Flash command input */
+
+#endif
-+
- #endif /* _IMX_REGS_H */
--
1.7.4.4
diff --git a/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch b/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
index b3e53eb..6a4bf28 100644
--- a/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
+++ b/patches/u-boot/2011.12/302-Add-support-for-the-armadeus-apf27-board.patch
@@ -1,26 +1,35 @@
-From fe25e4695b704742eee8ff6e0d01cf0c3413dbd3 Mon Sep 17 00:00:00 2001
-From: Philippe Reynes <tr...@ya...>
-Date: Sun, 25 Sep 2011 11:25:10 +0200
-Subject: [PATCH 2/6] Add support for the armadeus apf27 board
+Add support for the armadeus APF27 board
Signed-off-by: Philippe Reynes <tr...@ya...>
---
- board/armadeus/apf27/Makefile | 50 ++
- board/armadeus/apf27/apf27.c | 200 +++++++
- board/armadeus/apf27/config.mk | 13 +
- board/armadeus/apf27/lowlevel_init.S | 343 ++++++++++++
- board/armadeus/apf27/u-boot-nand.lds | 56 ++
- boards.cfg | 1 +
- 6 files changed, 1649 insertions(+), 0 deletions(-)
+ board/armadeus/apf27/Makefile | 50 +++
+ board/armadeus/apf27/apf27.c | 305 +++++++++++++++++
+ board/armadeus/apf27/config.mk | 13 +
+ board/armadeus/apf27/fpga.c | 269 +++++++++++++++
+ board/armadeus/apf27/fpga.h | 39 +++
+ board/armadeus/apf27/lowlevel_init.S | 277 +++++++++++++++
+ board/armadeus/apf27/u-boot-nand.lds | 56 +++
+ boards.cfg | 1 +
+ nand_spl/board/armadeus/apf27/Makefile | 77 +++++
+ nand_spl/board/armadeus/apf27/config.mk | 43 +++
+ nand_spl/board/armadeus/apf27/start.S | 552 ++++++++++++++++++++++++++++++
+ nand_spl/board/armadeus/apf27/u-boot.lds | 37 ++
+ 12 files changed, 1719 insertions(+), 0 deletions(-)
create mode 100644 board/armadeus/apf27/Makefile
create mode 100644 board/armadeus/apf27/apf27.c
create mode 100644 board/armadeus/apf27/config.mk
+ create mode 100644 board/armadeus/apf27/fpga.c
+ create mode 100644 board/armadeus/apf27/fpga.h
create mode 100644 board/armadeus/apf27/lowlevel_init.S
create mode 100644 board/armadeus/apf27/u-boot-nand.lds
+ create mode 100644 nand_spl/board/armadeus/apf27/Makefile
+ create mode 100644 nand_spl/board/armadeus/apf27/config.mk
+ create mode 100644 nand_spl/board/armadeus/apf27/start.S
+ create mode 100644 nand_spl/board/armadeus/apf27/u-boot.lds
diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile
new file mode 100644
-index 0000000..2a0f7d8
+index 0000000..b67334c
--- /dev/null
+++ b/board/armadeus/apf27/Makefile
@@ -0,0 +1,50 @@
@@ -76,10 +85,10 @@ index 0000000..2a0f7d8
+#########################################################################
diff --git a/board/armadeus/apf27/apf27.c b/board/armadeus/apf27/apf27.c
new file mode 100644
-index 0000000..e08b7a2
+index 0000000..1f1bd42
--- /dev/null
+++ b/board/armadeus/apf27/apf27.c
-@@ -0,0 +1,202 @@
+@@ -0,0 +1,305 @@
+/*
+ * Copyright (C) 2007 Sascha Hauer, Pengutronix
+ * Copyright (C) 2008,2009 Eric Jarrige <jo...@us...>
@@ -107,11 +116,113 @@ index 0000000..e08b7a2
+#include <jffs2/jffs2.h>
+#include <nand.h>
+#include <netdev.h>
++#include <asm/io.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/errno.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
++static void apf27_gpio_init(void)
++{
++ struct gpio_regs *regs = (struct gpio_regs *)IMX_GPIO_BASE;
++
++ /* PORT A */
++ writel(CONFIG_SYS_DR_A_VAL, ®s->port[PORTA].dr);
++ writel(CONFIG_SYS_OCR1_A_VAL, ®s->port[PORTA].ocr1);
++ writel(CONFIG_SYS_OCR2_A_VAL, ®s->port[PORTA].ocr2);
++ writel(CONFIG_SYS_ICFA1_A_VAL, ®s->port[PORTA].iconfa1);
++ writel(CONFIG_SYS_ICFA2_A_VAL, ®s->port[PORTA].iconfa2);
++ writel(CONFIG_SYS_ICFB1_A_VAL, ®s->port[PORTA].iconfb1);
++ writel(CONFIG_SYS_ICFB2_A_VAL, ®s->port[PORTA].iconfb2);
++ writel(CONFIG_SYS_ICR1_A_VAL, ®s->port[PORTA].icr1);
++ writel(CONFIG_SYS_ICR2_A_VAL, ®s->port[PORTA].icr2);
++ writel(CONFIG_SYS_IMR_A_VAL, ®s->port[PORTA].imr);
++ writel(CONFIG_SYS_DDIR_A_VAL, ®s->port[PORTA].ddir);
++ writel(CONFIG_SYS_GPR_A_VAL, ®s->port[PORTA].gpr);
++ writel(CONFIG_SYS_PUEN_A_VAL, ®s->port[PORTA].puen);
++ writel(CONFIG_SYS_GIUS_A_VAL, ®s->port[PORTA].gius);
++
++ /* PORT B */
++ writel(CONFIG_SYS_DR_B_VAL, ®s->port[PORTB].dr);
++ writel(CONFIG_SYS_OCR1_B_VAL, ®s->port[PORTB].ocr1);
++ writel(CONFIG_SYS_OCR2_B_VAL, ®s->port[PORTB].ocr2);
++ writel(CONFIG_SYS_ICFA1_B_VAL, ®s->port[PORTB].iconfa1);
++ writel(CONFIG_SYS_ICFA2_B_VAL, ®s->port[PORTB].iconfa2);
++ writel(CONFIG_SYS_ICFB1_B_VAL, ®s->port[PORTB].iconfb1);
++ writel(CONFIG_SYS_ICFB2_B_VAL, ®s->port[PORTB].iconfb2);
++ writel(CONFIG_SYS_ICR1_B_VAL, ®s->port[PORTB].icr1);
++ writel(CONFIG_SYS_ICR2_B_VAL, ®s->port[PORTB].icr2);
++ writel(CONFIG_SYS_IMR_B_VAL, ®s->port[PORTB].imr);
++ writel(CONFIG_SYS_DDIR_B_VAL, ®s->port[PORTB].ddir);
++ writel(CONFIG_SYS_GPR_B_VAL, ®s->port[PORTB].gpr);
++ writel(CONFIG_SYS_PUEN_B_VAL, ®s->port[PORTB].puen);
++ writel(CONFIG_SYS_GIUS_B_VAL, ®s->port[PORTB].gius);
++
++ /* PORT C */
++ writel(CONFIG_SYS_DR_C_VAL, ®s->port[PORTC].dr);
++ writel(CONFIG_SYS_OCR1_C_VAL, ®s->port[PORTC].ocr1);
++ writel(CONFIG_SYS_OCR2_C_VAL, ®s->port[PORTC].ocr2);
++ writel(CONFIG_SYS_ICFA1_C_VAL, ®s->port[PORTC].iconfa1);
++ writel(CONFIG_SYS_ICFA2_C_VAL, ®s->port[PORTC].iconfa2);
++ writel(CONFIG_SYS_ICFB1_C_VAL, ®s->port[PORTC].iconfb1);
++ writel(CONFIG_SYS_ICFB2_C_VAL, ®s->port[PORTC].iconfb2);
++ writel(CONFIG_SYS_ICR1_C_VAL, ®s->port[PORTC].icr1);
++ writel(CONFIG_SYS_ICR2_C_VAL, ®s->port[PORTC].icr2);
++ writel(CONFIG_SYS_IMR_C_VAL, ®s->port[PORTC].imr);
++ writel(CONFIG_SYS_DDIR_C_VAL, ®s->port[PORTC].ddir);
++ writel(CONFIG_SYS_GPR_C_VAL, ®s->port[PORTC].gpr);
++ writel(CONFIG_SYS_PUEN_C_VAL, ®s->port[PORTC].puen);
++ writel(CONFIG_SYS_GIUS_C_VAL, ®s->port[PORTC].gius);
++
++ /* PORT D */
++ writel(CONFIG_SYS_DR_D_VAL, ®s->port[PORTD].dr);
++ writel(CONFIG_SYS_OCR1_D_VAL, ®s->port[PORTD].ocr1);
++ writel(CONFIG_SYS_OCR2_D_VAL, ®s->port[PORTD].ocr2);
++ writel(CONFIG_SYS_ICFA1_D_VAL, ®s->port[PORTD].iconfa1);
++ writel(CONFIG_SYS_ICFA2_D_VAL, ®s->port[PORTD].iconfa2);
++ writel(CONFIG_SYS_ICFB1_D_VAL, ®s->port[PORTD].iconfb1);
++ writel(CONFIG_SYS_ICFB2_D_VAL, ®s->port[PORTD].iconfb2);
++ writel(CONFIG_SYS_ICR1_D_VAL, ®s->port[PORTD].icr1);
++ writel(CONFIG_SYS_ICR2_D_VAL, ®s->port[PORTD].icr2);
++ writel(CONFIG_SYS_IMR_D_VAL, ®s->port[PORTD].imr);
++ writel(CONFIG_SYS_DDIR_D_VAL, ®s->port[PORTD].ddir);
++ writel(CONFIG_SYS_GPR_D_VAL, ®s->port[PORTD].gpr);
++ writel(CONFIG_SYS_PUEN_D_VAL, ®s->port[PORTD].puen);
++ writel(CONFIG_SYS_GIUS_D_VAL, ®s->port[PORTD].gius);
++
++ /* PORT E */
++ writel(CONFIG_SYS_DR_E_VAL, ®s->port[PORTE].dr);
++ writel(CONFIG_SYS_OCR1_E_VAL, ®s->port[PORTE].ocr1);
++ writel(CONFIG_SYS_OCR2_E_VAL, ®s->port[PORTE].ocr2);
++ writel(CONFIG_SYS_ICFA1_E_VAL, ®s->port[PORTE].iconfa1);
++ writel(CONFIG_SYS_ICFA2_E_VAL, ®s->port[PORTE].iconfa2);
++ writel(CONFIG_SYS_ICFB1_E_VAL, ®s->port[PORTE].iconfb1);
++ writel(CONFIG_SYS_ICFB2_E_VAL, ®s->port[PORTE].iconfb2);
++ writel(CONFIG_SYS_ICR1_E_VAL, ®s->port[PORTE].icr1);
++ writel(CONFIG_SYS_ICR2_E_VAL, ®s->port[PORTE].icr2);
++ writel(CONFIG_SYS_IMR_E_VAL, ®s->port[PORTE].imr);
++ writel(CONFIG_SYS_DDIR_E_VAL, ®s->port[PORTE].ddir);
++ writel(CONFIG_SYS_GPR_E_VAL, ®s->port[PORTE].gpr);
++ writel(CONFIG_SYS_PUEN_E_VAL, ®s->port[PORTE].puen);
++ writel(CONFIG_SYS_GIUS_E_VAL, ®s->port[PORTE].gius);
++
++ /* PORT F */
++ writel(CONFIG_SYS_DR_F_VAL, ®s->port[PORTF].dr);
++ writel(CONFIG_SYS_OCR1_F_VAL, ®s->port[PORTF].ocr1);
++ writel(CONFIG_SYS_OCR2_F_VAL, ®s->port[PORTF].ocr2);
++ writel(CONFIG_SYS_ICFA1_F_VAL, ®s->port[PORTF].iconfa1);
++ writel(CONFIG_SYS_ICFA2_F_VAL, ®s->port[PORTF].iconfa2);
++ writel(CONFIG_SYS_ICFB1_F_VAL, ®s->port[PORTF].iconfb1);
++ writel(CONFIG_SYS_ICFB2_F_VAL, ®s->port[PORTF].iconfb2);
++ writel(CONFIG_SYS_ICR1_F_VAL, ®s->port[PORTF].icr1);
++ writel(CONFIG_SYS_ICR2_F_VAL, ®s->port[PORTF].icr2);
++ writel(CONFIG_SYS_IMR_F_VAL, ®s->port[PORTF].imr);
++ writel(CONFIG_SYS_DDIR_F_VAL, ®s->port[PORTF].ddir);
++ writel(CONFIG_SYS_GPR_F_VAL, ®s->port[PORTF].gpr);
++ writel(CONFIG_SYS_PUEN_F_VAL, ®s->port[PORTF].puen);
++ writel(CONFIG_SYS_GIUS_F_VAL, ®s->port[PORTF].gius);
++}
++
+static int apf27_devices_init(void)
+{
+ int i;
@@ -156,6 +267,7 @@ index 0000000..e08b7a2
+{
+ gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
+
++ apf27_gpio_init();
+ apf27_devices_init();
+
+ return 0;
@@ -301,10 +413,11 @@ index 0000000..3354ba0
+TEXT_BASE = 0xAFF00000
+endif
+# CONFIG_NAND_U_BOOT = y
-Index: u-boot-2010.03/board/armadeus/apf27/fpga.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/board/armadeus/apf27/fpga.c 2011-01-05 18:09:44.000000000 +0100
+diff --git a/board/armadeus/apf27/fpga.c b/board/armadeus/apf27/fpga.c
+new file mode 100644
+index 0000000..1d2c168
+--- /dev/null
++++ b/board/armadeus/apf27/fpga.c
@@ -0,0 +1,269 @@
+/*
+ * (C) Copyright 2002-2008
@@ -575,10 +688,11 @@ Index: u-boot-2010.03/board/armadeus/apf27/fpga.c
+}
+
+#endif /* CONFIG_FPGA */
-Index: u-boot-2010.03/board/armadeus/apf27/fpga.h
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/board/armadeus/apf27/fpga.h 2011-01-05 18:09:44.000000000 +0100
+diff --git a/board/armadeus/apf27/fpga.h b/board/armadeus/apf27/fpga.h
+new file mode 100644
+index 0000000..ca569e0
+--- /dev/null
++++ b/board/armadeus/apf27/fpga.h
@@ -0,0 +1,39 @@
+/*
+ * (C) Copyright 2002-2008
@@ -621,10 +735,10 @@ Index: u-boot-2010.03/board/armadeus/apf27/fpga.h
+extern int fpga_busy_fn (int cookie);
diff --git a/board/armadeus/apf27/lowlevel_init.S b/board/armadeus/apf27/lowlevel_init.S
new file mode 100644
-index 0000000..4d72d8c
+index 0000000..dab8d78
--- /dev/null
+++ b/board/armadeus/apf27/lowlevel_init.S
-@@ -0,0 +1,365 @@
+@@ -0,0 +1,277 @@
+/*
+ * For clock initialization, see chapter 3 of the "MCIMX27 Multimedia
+ * Applications Processor Reference Manual, Rev. 0.2".
@@ -650,117 +764,25 @@ index 0000000..4d72d8c
+
+#include <config.h>
+#include <version.h>
++#include <asm/macro.h>
+#include <asm/arch/imx-regs.h>
++#include <generated/asm-offsets.h>
+
+
+
-+#define writel(reg, val) \
-+ ldr r0, =reg; \
-+ ldr r1, =val; \
-+ str r1, [r0];
+
+.macro port_init
-+ writel( FMCR, CONFIG_SYS_FMCR_VAL)
-+/* PORTA */
-+ writel( DR(PORTA), CONFIG_SYS_DR_A_VAL)
-+ writel( OCR1(PORTA), CONFIG_SYS_OCR1_A_VAL)
-+ writel( OCR2(PORTA), CONFIG_SYS_OCR2_A_VAL)
-+ writel( ICONFA1(PORTA), CONFIG_SYS_ICFA1_A_VAL)
-+ writel( ICONFA2(PORTA), CONFIG_SYS_ICFA2_A_VAL)
-+ writel( ICONFB1(PORTA), CONFIG_SYS_ICFB1_A_VAL)
-+ writel( ICONFB2(PORTA), CONFIG_SYS_ICFB2_A_VAL)
-+ writel( ICR1(PORTA), CONFIG_SYS_ICR1_A_VAL)
-+ writel( ICR2(PORTA), CONFIG_SYS_ICR2_A_VAL)
-+ writel( IMR(PORTA), CONFIG_SYS_IMR_A_VAL)
-+ writel( DDIR(PORTA), CONFIG_SYS_DDIR_A_VAL)
-+ writel( GPR(PORTA), CONFIG_SYS_GPR_A_VAL)
-+ writel( PUEN(PORTA), CONFIG_SYS_PUEN_A_VAL)
-+ writel( GIUS(PORTA), CONFIG_SYS_GIUS_A_VAL)
-+/* PORTB */
-+ writel( DR(PORTB), CONFIG_SYS_DR_B_VAL)
-+ writel( OCR1(PORTB), CONFIG_SYS_OCR1_B_VAL)
-+ writel( OCR2(PORTB), CONFIG_SYS_OCR2_B_VAL)
-+ writel( ICONFA1(PORTB), CONFIG_SYS_ICFA1_B_VAL)
-+ writel( ICONFA2(PORTB), CONFIG_SYS_ICFA2_B_VAL)
-+ writel( ICONFB1(PORTB), CONFIG_SYS_ICFB1_B_VAL)
-+ writel( ICONFB2(PORTB), CONFIG_SYS_ICFB2_B_VAL)
-+ writel( ICR1(PORTB), CONFIG_SYS_ICR1_B_VAL)
-+ writel( ICR2(PORTB), CONFIG_SYS_ICR2_B_VAL)
-+ writel( IMR(PORTB), CONFIG_SYS_IMR_B_VAL)
-+ writel( DDIR(PORTB), CONFIG_SYS_DDIR_B_VAL)
-+ writel( GPR(PORTB), CONFIG_SYS_GPR_B_VAL)
-+ writel( PUEN(PORTB), CONFIG_SYS_PUEN_B_VAL)
-+ writel( GIUS(PORTB), CONFIG_SYS_GIUS_B_VAL)
-+/* PORTC */
-+ writel( DR(PORTC), CONFIG_SYS_DR_C_VAL)
-+ writel( OCR1(PORTC), CONFIG_SYS_OCR1_C_VAL)
-+ writel( OCR2(PORTC), CONFIG_SYS_OCR2_C_VAL)
-+ writel( ICONFA1(PORTC), CONFIG_SYS_ICFA1_C_VAL)
-+ writel( ICONFA2(PORTC), CONFIG_SYS_ICFA2_C_VAL)
-+ writel( ICONFB1(PORTC), CONFIG_SYS_ICFB1_C_VAL)
-+ writel( ICONFB2(PORTC), CONFIG_SYS_ICFB2_C_VAL)
-+ writel( ICR1(PORTC), CONFIG_SYS_ICR1_C_VAL)
-+ writel( ICR2(PORTC), CONFIG_SYS_ICR2_C_VAL)
-+ writel( IMR(PORTC), CONFIG_SYS_IMR_C_VAL)
-+ writel( DDIR(PORTC), CONFIG_SYS_DDIR_C_VAL)
-+ writel( GPR(PORTC), CONFIG_SYS_GPR_C_VAL)
-+ writel( PUEN(PORTC), CONFIG_SYS_PUEN_C_VAL)
-+ writel( GIUS(PORTC), CONFIG_SYS_GIUS_C_VAL)
-+/* PORTD */
-+ writel( DR(PORTD), CONFIG_SYS_DR_D_VAL)
-+ writel( OCR1(PORTD), CONFIG_SYS_OCR1_D_VAL)
-+ writel( OCR2(PORTD), CONFIG_SYS_OCR2_D_VAL)
-+ writel( ICONFA1(PORTD), CONFIG_SYS_ICFA1_D_VAL)
-+ writel( ICONFA2(PORTD), CONFIG_SYS_ICFA2_D_VAL)
-+ writel( ICONFB1(PORTD), CONFIG_SYS_ICFB1_D_VAL)
-+ writel( ICONFB2(PORTD), CONFIG_SYS_ICFB2_D_VAL)
-+ writel( ICR1(PORTD), CONFIG_SYS_ICR1_D_VAL)
-+ writel( ICR2(PORTD), CONFIG_SYS_ICR2_D_VAL)
-+ writel( IMR(PORTD), CONFIG_SYS_IMR_D_VAL)
-+ writel( DDIR(PORTD), CONFIG_SYS_DDIR_D_VAL)
-+ writel( GPR(PORTD), CONFIG_SYS_GPR_D_VAL)
-+ writel( PUEN(PORTD), CONFIG_SYS_PUEN_D_VAL)
-+ writel( GIUS(PORTD), CONFIG_SYS_GIUS_D_VAL)
-+/* PORTE */
-+ writel( DR(PORTE), CONFIG_SYS_DR_E_VAL)
-+ writel( OCR1(PORTE), CONFIG_SYS_OCR1_E_VAL)
-+ writel( OCR2(PORTE), CONFIG_SYS_OCR2_E_VAL)
-+ writel( ICONFA1(PORTE), CONFIG_SYS_ICFA1_E_VAL)
-+ writel( ICONFA2(PORTE), CONFIG_SYS_ICFA2_E_VAL)
-+ writel( ICONFB1(PORTE), CONFIG_SYS_ICFB1_E_VAL)
-+ writel( ICONFB2(PORTE), CONFIG_SYS_ICFB2_E_VAL)
-+ writel( ICR1(PORTE), CONFIG_SYS_ICR1_E_VAL)
-+ writel( ICR2(PORTE), CONFIG_SYS_ICR2_E_VAL)
-+ writel( IMR(PORTE), CONFIG_SYS_IMR_E_VAL)
-+ writel( DDIR(PORTE), CONFIG_SYS_DDIR_E_VAL)
-+ writel( GPR(PORTE), CONFIG_SYS_GPR_E_VAL)
-+ writel( PUEN(PORTE), CONFIG_SYS_PUEN_E_VAL)
-+ writel( GIUS(PORTE), CONFIG_SYS_GIUS_E_VAL)
-+/* PORTF */
-+ writel( DR(PORTF), CONFIG_SYS_DR_F_VAL)
-+ writel( OCR1(PORTF), CONFIG_SYS_OCR1_F_VAL)
-+ writel( OCR2(PORTF), CONFIG_SYS_OCR2_F_VAL)
-+ writel( ICONFA1(PORTF), CONFIG_SYS_ICFA1_F_VAL)
-+ writel( ICONFA2(PORTF), CONFIG_SYS_ICFA2_F_VAL)
-+ writel( ICONFB1(PORTF), CONFIG_SYS_ICFB1_F_VAL)
-+ writel( ICONFB2(PORTF), CONFIG_SYS_ICFB2_F_VAL)
-+ writel( ICR1(PORTF), CONFIG_SYS_ICR1_F_VAL)
-+ writel( ICR2(PORTF), CONFIG_SYS_ICR2_F_VAL)
-+ writel( IMR(PORTF), CONFIG_SYS_IMR_F_VAL)
-+ writel( DDIR(PORTF), CONFIG_SYS_DDIR_F_VAL)
-+ writel( GPR(PORTF), CONFIG_SYS_GPR_F_VAL)
-+ writel( PUEN(PORTF), CONFIG_SYS_PUEN_F_VAL)
-+ writel( GIUS(PORTF), CONFIG_SYS_GIUS_F_VAL)
++ write32 FMCR, CONFIG_SYS_FMCR_VAL
+.endm /* port_init */
+
+.macro init_aipi
+ /*
+ * setup AIPI1 and AIPI2
+ */
-+ writel(AIPI1_PSR0, CONFIG_SYS_AIPI1_PSR0_VAL)
-+ writel(AIPI1_PSR1, CONFIG_SYS_AIPI1_PSR1_VAL)
-+ writel(AIPI2_PSR0, CONFIG_SYS_AIPI2_PSR0_VAL)
-+ writel(AIPI2_PSR1, CONFIG_SYS_AIPI2_PSR1_VAL)
++ write32 AIPI1_PSR0, CONFIG_SYS_AIPI1_PSR0_VAL
++ write32 AIPI1_PSR1, CONFIG_SYS_AIPI1_PSR1_VAL
++ write32 AIPI2_PSR0, CONFIG_SYS_AIPI2_PSR0_VAL
++ write32 AIPI2_PSR1, CONFIG_SYS_AIPI2_PSR1_VAL
+
+ /* Change SDRAM signal strengh */
+ ldr r0, =GPCR
@@ -781,10 +803,10 @@ index 0000000..4d72d8c
+ /*
+ * pll clock initialization predefined in apf27.h
+ */
-+ writel(MPCTL0, CONFIG_SYS_MPCTL0_VAL)
-+ writel(SPCTL0, CONFIG_SYS_SPCTL0_VAL)
++ write32 MPCTL0, CONFIG_SYS_MPCTL0_VAL
++ write32 SPCTL0, CONFIG_SYS_SPCTL0_VAL
+
-+ writel(CSCR, CONFIG_SYS_CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART)
++ write32 CSCR, CONFIG_SYS_CSCR_VAL | CSCR_MPLL_RESTART | CSCR_SPLL_RESTART
+
+ /*
+ * add some delay here
@@ -794,29 +816,29 @@ index 0000000..4d72d8c
+ bne 1b
+
+ /* peripheral clock divider */
-+ writel(PCDR0, CONFIG_SYS_PCDR0_VAL)
-+ writel(PCDR1, CONFIG_SYS_PCDR1_VAL)
++ write32 PCDR0, CONFIG_SYS_PCDR0_VAL
++ write32 PCDR1, CONFIG_SYS_PCDR1_VAL
+
+ /* Configure PCCR0 and PCCR1 */
-+ writel(PCCR0, CONFIG_SYS_PCCR0_VAL)
-+ writel(PCCR1, CONFIG_SYS_PCCR1_VAL)
++ write32 PCCR0, CONFIG_SYS_PCCR0_VAL
++ write32 PCCR1, CONFIG_SYS_PCCR1_VAL
+
+
+.endm /* init_clock */
+
+.macro sdram_init
+ /* wait for SDRAM/LPDDR ready (SDRAMRDY) */
-+ ldr r0, =ESDMISC
++ ldr r0, =IMX_ESD_BASE
+ ldr r4, =ESDMISC_SDRAM_RDY
-+2: ldr r1, [r0]
++2: ldr r1, [r0, #ESDMISC_ROF]
+ ands r1, r1, r4
+ bpl 2b
+
+ /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
-+ ldr r0, =ESDMISC
++ ldr r0, =IMX_ESD_BASE
+ ldr r4, =CONFIG_SYS_ESDMISC_VAL
+ orr r1, r4, #ESDMISC_MDDR_DL_RST
-+ str r1, [r0]
++ str r1, [r0, #ESDMISC_ROF]
+
+ /* Hold for more than 200ns */
+ ldr r1, =0x10000
@@ -825,12 +847,15 @@ index 0000000..4d72d8c
+
+ str r4, [r0]
+
-+ writel(ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL)
++ /* write32 ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL */
++ ldr r0, =IMX_ESD_BASE
++ ldr r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL
++ str r1, [r0, #ESDCFG0_ROF]
+
+ /* writel(ESDCTL0, CONFIG_SYS_PRECHARGE_CMD) */
-+ ldr r0, =ESDCTL0
++ ldr r0, =IMX_ESD_BASE
+ ldr r1, =CONFIG_SYS_PRECHARGE_CMD
-+ str r1, [r0]
++ str r1, [r0, #ESDCTL0_ROF]
+
+ /* writeb(0xA0001000, any value) */
+ ldr r1, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
@@ -838,7 +863,7 @@ index 0000000..4d72d8c
+
+ /* writel(ESDCTL0, CONFIG_SYS_AUTOREFRESH_CMD) */
+ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
-+ str r1, [r0]
++ str r1, [r0, #ESDCTL0_ROF]
+
+ ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
+
@@ -849,7 +874,7 @@ index 0000000..4d72d8c
+
+ /* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_SET_MODE_REG_CMD) */
+ ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD
-+ str r1, [r0]
++ str r1, [r0, #ESDCTL0_ROF]
+
+ /* set standard mode register */
+ ldr r4, = PHYS_SDRAM_1+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
@@ -861,16 +886,17 @@ index 0000000..4d72d8c
+
+ /* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_NORMAL_RW_CMD) */
+ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
-+ str r1, [r0]
++ str r1, [r0, #ESDCTL0_ROF]
+
+#if (CONFIG_NR_DRAM_BANKS > 1)
+ /* 2nd sdram */
-+ writel(ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL )
++ /* write32 ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL */
++ ldr r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL
++ str r1, [r0, #ESDCFG1_ROF]
+
+ /* writel(ESDCTL1, CONFIG_SYS_PRECHARGE_CMD) */
-+ ldr r0, =ESDCTL1
+ ldr r1, =CONFIG_SYS_PRECHARGE_CMD
-+ str r1, [r0]
++ str r1, [r0, #ESDCTL1_ROF]
+
+ /* writeb(0xB0001000, any value) */
+ ldr r1, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
@@ -878,7 +904,7 @@ index 0000000..4d72d8c
+
+ /* writel(ESDCTL1, CONFIG_SYS_AUTOREFRESH_CMD) */
+ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
-+ str r1, [r0]
++ str r1, [r0, #ESDCTL1_ROF]
+
+ ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
+
@@ -889,7 +915,7 @@ index 0000000..4d72d8c
+
+ /* writel(ESDCTL1, CONFIG_SYS_SET_MODE_REG_CMD) */
+ ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD
-+ str r1, [r0]
++ str r1, [r0, #ESDCTL1_ROF]
+
+ /* set standard mode register */
+ ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
@@ -901,7 +927,7 @@ index 0000000..4d72d8c
+
+ /* writel(ESDCTL1, CONFIG_SYS_NORMAL_RW_CMD) */
+ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
-+ str r1, [r0]
++ str r1, [r0, #ESDCTL1_ROF]
+#endif /* CONFIG_NR_DRAM_BANKS > 1 */
+.endm /* sdram_init */
+
@@ -913,42 +939,42 @@ index 0000000..4d72d8c
+ init_aipi
+
+ /* configure csx */
-+ writel(CS0U, CONFIG_SYS_CS0U_VAL)
-+ writel(CS0L, CONFIG_SYS_CS0L_VAL)
-+ writel(CS0A, CONFIG_SYS_CS0A_VAL)
++ write32 CS0U, CONFIG_SYS_CS0U_VAL
++ write32 CS0L, CONFIG_SYS_CS0L_VAL
++ write32 CS0A, CONFIG_SYS_CS0A_VAL
+
-+ writel(CS1U, CONFIG_SYS_CS1U_VAL)
-+ writel(CS1L, CONFIG_SYS_CS1L_VAL)
-+ writel(CS1A, CONFIG_SYS_CS1A_VAL)
++ write32 CS1U, CONFIG_SYS_CS1U_VAL
++ write32 CS1L, CONFIG_SYS_CS1L_VAL
++ write32 CS1A, CONFIG_SYS_CS1A_VAL
+
-+ writel(CS2U, CONFIG_SYS_CS2U_VAL)
-+ writel(CS2L, CONFIG_SYS_CS2L_VAL)
-+ writel(CS2A, CONFIG_SYS_CS2A_VAL)
++ write32 CS2U, CONFIG_SYS_CS2U_VAL
++ write32 CS2L, CONFIG_SYS_CS2L_VAL
++ write32 CS2A, CONFIG_SYS_CS2A_VAL
+
-+ writel(CS3U, CONFIG_SYS_CS3U_VAL)
-+ writel(CS3L, CONFIG_SYS_CS3L_VAL)
-+ writel(CS3A, CONFIG_SYS_CS3A_VAL)
++ write32 CS3U, CONFIG_SYS_CS3U_VAL
++ write32 CS3L, CONFIG_SYS_CS3L_VAL
++ write32 CS3A, CONFIG_SYS_CS3A_VAL
+
-+ writel(CS4U, CONFIG_SYS_CS4U_VAL)
-+ writel(CS4L, CONFIG_SYS_CS4L_VAL)
-+ writel(CS4A, CONFIG_SYS_CS4A_VAL)
++ write32 CS4U, CONFIG_SYS_CS4U_VAL
++ write32 CS4L, CONFIG_SYS_CS4L_VAL
++ write32 CS4A, CONFIG_SYS_CS4A_VAL
+
-+ writel(CS5U, CONFIG_SYS_CS5U_VAL)
-+ writel(CS5L, CONFIG_SYS_CS5L_VAL)
-+ writel(CS5A, CONFIG_SYS_CS5A_VAL)
++ write32 CS5U, CONFIG_SYS_CS5U_VAL
++ write32 CS5L, CONFIG_SYS_CS5L_VAL
++ write32 CS5A, CONFIG_SYS_CS5A_VAL
+
-+ writel(EIM, CONFIG_SYS_EIM_VAL)
++ write32 EIM, CONFIG_SYS_EIM_VAL
+
+ port_init
+
+ /* Configure FPGA CLKO */
-+ writel(CCSR, CONFIG_SYS_CCSR_VAL)
++ write32 CCSR, CONFIG_SYS_CCSR_VAL
+
+ /* Configure strentgh for FPGA */
-+ writel(DSCR10, CONFIG_SYS_DSCR10_VAL)
-+ writel(DSCR3, CONFIG_SYS_DSCR3_VAL)
-+ writel(DSCR7, CONFIG_SYS_DSCR7_VAL)
-+ writel(DSCR2, CONFIG_SYS_DSCR2_VAL)
++ write32 DSCR10, CONFIG_SYS_DSCR10_VAL
++ write32 DSCR3, CONFIG_SYS_DSCR3_VAL
++ write32 DSCR7, CONFIG_SYS_DSCR7_VAL
++ write32 DSCR2, CONFIG_SYS_DSCR2_VAL
+
+ init_clock
+
@@ -1053,10 +1079,10 @@ index 0000000..f66f20e
+}
+
diff --git a/boards.cfg b/boards.cfg
-index 66c27a4..f68c3a7 100644
+index 30eb74f..95d713a 100644
--- a/boards.cfg
+++ b/boards.cfg
-@@ -69,6 +69,7 @@ integratorcp_cm926ejs arm arm926ejs integrator armltd
+@@ -70,6 +70,7 @@ integratorcp_cm926ejs arm arm926ejs integrator armltd
aspenite arm arm926ejs - Marvell armada100
gplugd arm arm926ejs - Marvell armada100
afeb9260 arm arm926ejs - - at91
@@ -1064,10 +1090,11 @@ index 66c27a4..f68c3a7 100644
at91sam9260ek_dataflash_cs0 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS0
at91sam9260ek_dataflash_cs1 arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_DATAFLASH_CS1
at91sam9260ek_nandflash arm arm926ejs at91sam9260ek atmel at91 at91sam9260ek:AT91SAM9260,SYS_USE_NANDFLASH
-Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/Makefile
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/nand_spl/board/armadeus/apf27/Makefile 2011-01-05 18:09:44.000000000 +0100
+diff --git a/nand_spl/board/armadeus/apf27/Makefile b/nand_spl/board/armadeus/apf27/Makefile
+new file mode 100644
+index 0000000..79a250e
+--- /dev/null
++++ b/nand_spl/board/armadeus/apf27/Makefile
@@ -0,0 +1,77 @@
+#
+# (C) Copyright 2007
@@ -1146,10 +1173,11 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/Makefile
+sinclude $(obj).depend
+
+#########################################################################
-Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/config.mk
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/nand_spl/board/armadeus/apf27/config.mk 2011-01-05 18:09:44.000000000 +0100
+diff --git a/nand_spl/board/armadeus/apf27/config.mk b/nand_spl/board/armadeus/apf27/config.mk
+new file mode 100644
+index 0000000..46802e3
+--- /dev/null
++++ b/nand_spl/board/armadeus/apf27/config.mk
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2007
@@ -1194,11 +1222,12 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/config.mk
+# PAD_TO used to generate a 2kByte binary needed for the combined image
+# -> PAD_TO = TEXT_BASE + 0x0800
+PAD_TO = 0xa0000800
-Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S 2011-01-05 18:09:44.000000000 +0100
-@@ -0,0 +1,544 @@
+diff --git a/nand_spl/board/armadeus/apf27/start.S b/nand_spl/board/armadeus/apf27/start.S
+new file mode 100644
+index 0000000..25dd7ad
+--- /dev/null
++++ b/nand_spl/board/armadeus/apf27/start.S
+@@ -0,0 +1,552 @@
+/*
+ * IMX27 NAND Flash SPL (Secondary Program Loader)
+ *
@@ -1231,7 +1260,9 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
+
+#include <config.h>
+#include <version.h>
++#include <asm/arch/mxc_nand.h>
+#include <asm/arch/imx-regs.h>
++#include <generated/asm-offsets.h>
+
+/*
+ * Standard NAND flash commands
@@ -1643,17 +1674,17 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
+setup_sdram_ddr:
+
+ /* wait for SDRAM/LPDDR ready (SDRAMRDY) */
-+ ldr r0, =ESDMISC
++ ldr r0, =IMX_ESD_BASE
+ ldr r4, =ESDMISC_SDRAM_RDY
-+2: ldr r1, [r0]
++2: ldr r1, [r0, #ESDMISC_ROF]
+ ands r1, r1, r4
+ bpl 2b
+
+ /* LPDDR Soft Reset Mobile/Low Power DDR SDRAM. */
-+ ldr r0, =ESDMISC
++ ldr r0, =IMX_ESD_BASE
+ ldr r4, =CONFIG_SYS_ESDMISC_VAL
+ orr r1, r4, #ESDMISC_MDDR_DL_RST
-+ str r1, [r0]
++ str r1, [r0, #ESDMISC_ROF]
+
+ /* Hold for more than 200ns */
+ ldr r1, =0x10000
@@ -1662,12 +1693,15 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
+
+ str r4, [r0]
+
-+ writel(ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL)
++ /* writel(ESDCFG0, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL) */
++ ldr r0, =IMX_ESD_BASE
++ ldr r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL
++ str r1, [r0, #ESDCFG0_ROF]
+
+ /* writel(ESDCTL0, CONFIG_SYS_PRECHARGE_CMD) */
-+ ldr r0, =ESDCTL0
++ ldr r0, =IMX_ESD_BASE
+ ldr r1, =CONFIG_SYS_PRECHARGE_CMD
-+ str r1, [r0]
++ str r1, [r0, #ESDCTL0_ROF]
+
+ /* writeb(0xA0001000, any value) */
+ ldr r1, =PHYS_SDRAM_1+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
@@ -1675,7 +1709,7 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
+
+ /* writel(ESDCTL0, CONFIG_SYS_AUTOREFRESH_CMD) */
+ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
-+ str r1, [r0]
++ str r1, [r0, #ESDCTL0_ROF]
+
+ ldr r4, =PHYS_SDRAM_1 /* CSD0 base address */
+
@@ -1686,7 +1720,7 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
+
+ /* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_SET_MODE_REG_CMD) */
+ ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD
-+ str r1, [r0]
++ str r1, [r0, #ESDCTL0_ROF]
+
+ /* set standard mode register */
+ ldr r4, = PHYS_SDRAM_1+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
@@ -1698,16 +1732,19 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
+
+ /* writel(CONFIG_SYS_PRECHARGE_CMD, CONFIG_SYS_NORMAL_RW_CMD) */
+ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
-+ str r1, [r0]
++ str r1, [r0, #ESDCTL0_ROF]
+
+#if (CONFIG_NR_DRAM_BANKS > 1)
+ /* 2nd sdram */
-+ writel(ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL )
++ /* writel(ESDCFG1, CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL ) */
++ ldr r0, =IMX_ESD_BASE
++ ldr r1, =CONFIG_SYS_SDRAM_ESDCFG_REGISTER_VAL
++ str r1, [r0, #ESDCFG1_ROF]
+
+ /* writel(ESDCTL1, CONFIG_SYS_PRECHARGE_CMD) */
-+ ldr r0, =ESDCTL1
++ ldr r0, =IMX_ESD_BASE
+ ldr r1, =CONFIG_SYS_PRECHARGE_CMD
-+ str r1, [r0]
++ str r1, [r0, #ESDCTL1_ROF]
+
+ /* writeb(0xB0001000, any value) */
+ ldr r1, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_PRECHARGE_ALL_VAL
@@ -1715,7 +1752,7 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
+
+ /* writel(ESDCTL1, CONFIG_SYS_AUTOREFRESH_CMD) */
+ ldr r1, =CONFIG_SYS_AUTOREFRESH_CMD
-+ str r1, [r0]
++ str r1, [r0, #ESDCTL1_ROF]
+
+ ldr r4, =PHYS_SDRAM_2 /* CSD1 base address */
+
@@ -1726,7 +1763,7 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
+
+ /* writel(ESDCTL1, CONFIG_SYS_SET_MODE_REG_CMD) */
+ ldr r1, =CONFIG_SYS_SET_MODE_REG_CMD
-+ str r1, [r0]
++ str r1, [r0, #ESDCTL1_ROF]
+
+ /* set standard mode register */
+ ldr r4, =PHYS_SDRAM_2+CONFIG_SYS_SDRAM_MODE_REGISTER_VAL
@@ -1738,15 +1775,16 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/start.S
+
+ /* writel(ESDCTL1, CONFIG_SYS_NORMAL_RW_CMD) */
+ ldr r1, =CONFIG_SYS_NORMAL_RW_CMD
-+ str r1, [r0]
++ str r1, [r0, #ESDCTL1_ROF]
+#endif /* CONFIG_NR_DRAM_BANKS > 1 */
+
+ mov pc, lr
+
-Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/u-boot.lds
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ u-boot-2010.03/nand_spl/board/armadeus/apf27/u-boot.lds 2011-01-05 18:09:44.000000000 +0100
+diff --git a/nand_spl/board/armadeus/apf27/u-boot.lds b/nand_spl/board/armadeus/apf27/u-boot.lds
+new file mode 100644
+index 0000000..aff356f
+--- /dev/null
++++ b/nand_spl/board/armadeus/apf27/u-boot.lds
@@ -0,0 +1,37 @@
+/*
+ * (C) Copyright 2007
@@ -1785,5 +1823,6 @@ Index: u-boot-2010.03/nand_spl/board/armadeus/apf27/u-boot.lds
+ *(.text)
+ }
+}
+--
1.7.4.4
diff --git a/patches/u-boot/2011.12/340-apf27-misc-commands.patch b/patches/u-boot/2011.12/340-apf27-misc-commands.patch
index c231719..23ade88 100644
--- a/patches/u-boot/2011.12/340-apf27-misc-commands.patch
+++ b/patches/u-boot/2011.12/340-apf27-misc-commands.patch
@@ -1,7 +1,46 @@
-Index: /board/armadeus/apf27/cmd_imxfuse.c
-===================================================================
---- /dev/null 1970-01-01 00:00:00.000000000 +0000
-+++ /board/armadeus/apf27/cmd_imxfuse.c 2011-01-05 18:08:44.000000000 +0100
+Add apf27 imxfuse command
+
+Signed-off-by: Philippe Reynes <tr...@ya...>
+---
+ arch/arm/include/asm/arch-mx27/imx-regs.h | 4 +
+ board/armadeus/apf27/Makefile | 2 +-
+ board/armadeus/apf27/cmd_imxfuse.c | 331 +++++++++++++++++++++++++++++
+ 3 files changed, 336 insertions(+), 1 deletions(-)
+ create mode 100644 board/armadeus/apf27/cmd_imxfuse.c
+
+diff --git a/arch/arm/include/asm/arch-mx27/imx-regs.h b/arch/arm/include/asm/arch-mx27/imx-regs.h
+index 4df67d6..be2bf41 100644
+--- a/arch/arm/include/asm/arch-mx27/imx-regs.h
++++ b/arch/arm/include/asm/arch-mx27/imx-regs.h
+@@ -522,6 +522,10 @@ struct fuse_bank0_regs {
+ #define IIM_ERR_SNSE (1 << 2)
+ #define IIM_ERR_PARITYE (1 << 1)
+
++/* IIM Control Registers */
++#define IIM_BANK_AREA IMX_IIM_BASE + 0x800
++#define IIM_BANK_REG(x,y) (IIM_BANK_AREA + 0x400 * x + (y<<2))
++
+ /*
+ * Memory areas of the NFC
+ */
+diff --git a/board/armadeus/apf27/Makefile b/board/armadeus/apf27/Makefile
+index b67334c..e87df1d 100644
+--- a/board/armadeus/apf27/Makefile
++++ b/board/armadeus/apf27/Makefile
+@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
+
+ LIB = $(obj)lib$(BOARD).o
+
+-COBJS := apf27.o fpga.o
++COBJS := apf27.o fpga.o cmd_imxfuse.o
+ SOBJS := lowlevel_init.o
+
+ SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+diff --git a/board/armadeus/apf27/cmd_imxfuse.c b/board/armadeus/apf27/cmd_imxfuse.c
+new file mode 100644
+index 0000000..cd2078a
+--- /dev/null
++++ b/board/armadeus/apf27/cmd_imxfuse.c
@@ -0,0 +1,331 @@
+/*
+ * cmd_imxfuse-c Interface to iMX IC Identification Module
@@ -334,16 +373,6 @@ Index: /board/armadeus/apf27/cmd_imxfuse.c
+ "imxfuse scc_key - read iMX SCC_KEY\n");
+
+#endif /* CONFIG_CMD_IMX_FUSE */
-Index: /board/armadeus/apf27/mx27/Makefile
-===================================================================
---- /board/armadeus/apf27/Makefile 2011-01-05 18:05:13.000000000 +0100
-+++ /board/armadeus/apf27/Makefile 2011-01-05 18:08:44.000000000 +0100
-@@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
-
- LIB = $(obj)lib$(BOARD).o
-
--COBJS := apf27.o fpga.o
-+COBJS := apf27.o fpga.o cmd_imxfuse.o
- SOBJS := lowlevel_init.o
-
- SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+--
+1.7.4.4
+
hooks/post-receive
--
armadeus
|
