[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-303-g4b4be02
Brought to you by:
sszy
Menu
▾
▴
[Armadeus-commitlog] armadeus branch, master, updated. armadeus-4.1-303-g4b4be02
|
From: Julien B a. A. <ar...@us...> - 2012-05-11 15:18:44
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "armadeus".
The branch, master has been updated
via 4b4be023227a1322d0db618d4983177bedd9c04c (commit)
via cec905e3738c164df223a87fee99290e10c3ccef (commit)
via af8c92e476c5faea728619181437050dd4e34a21 (commit)
via 61ea8a61754a4186ec1aed30649c9a8b3dd7b301 (commit)
from fd18e0d5ef2517e6208997666d137786ab7c7533 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 4b4be023227a1322d0db618d4983177bedd9c04c
Merge: cec905e fd18e0d
Author: Julien Boibessot <jul...@ar...>
Date: Fri May 11 17:17:54 2012 +0200
Merge branch 'master' of ssh://armadeus.git.sourceforge.net/gitroot/armadeus/armadeus
commit cec905e3738c164df223a87fee99290e10c3ccef
Author: Julien Boibessot <jul...@ar...>
Date: Fri May 11 17:17:06 2012 +0200
[BUILD] quiltify: support big custom patch only for apf28 & 2.6.35.3 kernel
commit af8c92e476c5faea728619181437050dd4e34a21
Author: Julien Boibessot <jul...@ar...>
Date: Fri May 11 17:16:00 2012 +0200
[TOOLS] Add possibility to build imxregs for i.MX53
commit 61ea8a61754a4186ec1aed30649c9a8b3dd7b301
Author: Julien Boibessot <jul...@ar...>
Date: Fri May 11 17:13:04 2012 +0200
[TOOLS] Add (partial) IPU support to imxregs
-----------------------------------------------------------------------
Summary of changes:
scripts/quiltify.sh | 2 +-
target/linux/debug/imxregs/Makefile | 5 +++-
target/linux/debug/imxregs/imx5regs.h | 36 +++++++++++++++++++++++++++++++++
target/linux/debug/imxregs/imxregs.c | 2 +-
4 files changed, 42 insertions(+), 3 deletions(-)
diff --git a/scripts/quiltify.sh b/scripts/quiltify.sh
index 42d0ed0..da1264c 100755
--- a/scripts/quiltify.sh
+++ b/scripts/quiltify.sh
@@ -51,7 +51,7 @@ fi
make shell_env
. armadeus_env.sh
-if [ "$ARMADEUS_BOARD_NAME" == "apf28" ]; then
+if [ "$ARMADEUS_BOARD_NAME" == "apf28" ] && [ "$ARMADEUS_LINUX_VERSION" == "2.6.35.3" ]; then
FREESCALE_PATCH=linux-2.6.35.3-imx_10.12.01.patch.tar.gz
else
FREESCALE_PATCH=""
diff --git a/target/linux/debug/imxregs/Makefile b/target/linux/debug/imxregs/Makefile
index 5ef8944..1ffa7e7 100644
--- a/target/linux/debug/imxregs/Makefile
+++ b/target/linux/debug/imxregs/Makefile
@@ -1,5 +1,5 @@
CC = arm-linux-gcc
-EXECS = imxlregs imx27regs imx28regs imx51regs
+EXECS = imxlregs imx27regs imx28regs imx51regs imx53regs
all: $(EXECS)
@@ -15,6 +15,9 @@ imx28regs: imxregs.c imx28regs.h definitions.h
imx51regs: imxregs.c imx5regs.h definitions.h
$(CC) -DIMX51 imxregs.c -o $@
+imx53regs: imxregs.c imx5regs.h definitions.h
+ $(CC) -DIMX53 imxregs.c -o $@
+
clean:
rm -f *.o
rm -f $(EXECS)
diff --git a/target/linux/debug/imxregs/imx5regs.h b/target/linux/debug/imxregs/imx5regs.h
index b658853..543133d 100644
--- a/target/linux/debug/imxregs/imx5regs.h
+++ b/target/linux/debug/imxregs/imx5regs.h
@@ -25,17 +25,50 @@
#ifdef IMX51
#define IMX_TYPE "i.MX51"
+#define IPU_BASE(x) (0x5e000000 + x)
#define CSI0_BASE(x) (0x5e030000 + x)
#define CSI1_BASE(x) (0x5e038000 + x)
+#define VDI_BASE(x) (0x5e068000 + x)
#else
#define IMX_TYPE "i.MX53"
+#define IPU_BASE(x) (0x1e000000 + x)
#define CSI0_BASE(x) (0x1e030000 + x)
#define CSI1_BASE(x) (0x1e038000 + x)
+#define VDI_BASE(x) (0x1e068000 + x)
#endif
static struct reg_info regs[] =
{
/* IPU */
+{ "IPU_CONF", IPU_BASE(0x00), 0, 0xffffffff, 'x', "Configuration Register" },
+{ "IPU_FS_PROC_FLOW1", IPU_BASE(0xa8), 0, 0xffffffff, 'x', "FSU Processing Flow 1 Register" },
+{ "IPU_FS_PROC_FLOW2", IPU_BASE(0xac), 0, 0xffffffff, 'x', "FSU Processing Flow 1 Register" },
+{ "IPU_FS_PROC_FLOW3", IPU_BASE(0xb0), 0, 0xffffffff, 'x', "FSU Processing Flow 1 Register" },
+{ "IPU_SKIP", IPU_BASE(0xbc), 0, 0xffffffff, 'x', "Skip Register" },
+{ "IPU_CH_DB_MODE_SEL0",IPU_BASE(0x150), 0, 0xffffffff, 'x', "Channel Double Buffer Mode Select 0 Register" },
+{ "IPU_CH_DB_MODE_SEL1",IPU_BASE(0x154), 0, 0xffffffff, 'x', "Channel Double Buffer Mode Select 0 Register" },
+{ "IPU_INT_STAT_1", IPU_BASE(0x200), 0, 0xffffffff, 'x', "Interrupt Status Register 1" },
+{ "IPU_INT_STAT_2", IPU_BASE(0x204), 0, 0xffffffff, 'x', "Interrupt Status Register 2" },
+{ "IPU_INT_STAT_3", IPU_BASE(0x208), 0, 0xffffffff, 'x', "Interrupt Status Register 3" },
+{ "IPU_INT_STAT_5", IPU_BASE(0x210), 0, 0xffffffff, 'x', "Interrupt Status Register 5" },
+{ "IPU_INT_STAT_6", IPU_BASE(0x214), 0, 0xffffffff, 'x', "Interrupt Status Register 6" },
+{ "IPU_INT_STAT_7", IPU_BASE(0x218), 0, 0xffffffff, 'x', "Interrupt Status Register 7" },
+{ "IPU_INT_STAT_8", IPU_BASE(0x21c), 0, 0xffffffff, 'x', "Interrupt Status Register 8" },
+{ "IPU_INT_STAT_9", IPU_BASE(0x220), 0, 0xffffffff, 'x', "Interrupt Status Register 9" },
+{ "IPU_INT_STAT_10", IPU_BASE(0x224), 0, 0xffffffff, 'x', "Interrupt Status Register 10" },
+{ "IPU_INT_STAT_11", IPU_BASE(0x228), 0, 0xffffffff, 'x', "Interrupt Status Register 11" },
+{ "IPU_INT_STAT_12", IPU_BASE(0x22c), 0, 0xffffffff, 'x', "Interrupt Status Register 12" },
+{ "IPU_INT_STAT_13", IPU_BASE(0x230), 0, 0xffffffff, 'x', "Interrupt Status Register 13" },
+{ "IPU_INT_STAT_14", IPU_BASE(0x234), 0, 0xffffffff, 'x', "Interrupt Status Register 14" },
+{ "IPU_INT_STAT_15", IPU_BASE(0x238), 0, 0xffffffff, 'x', "Interrupt Status Register 15" },
+{ "IPU_CUR_BUF_0", IPU_BASE(0x23c), 0, 0xffffffff, 'x', "Current Buffer Register 0" },
+{ "IPU_CUR_BUF_1", IPU_BASE(0x240), 0, 0xffffffff, 'x', "Current Buffer Register 1" },
+{ "IPU_ALT_CUR_0", IPU_BASE(0x244), 0, 0xffffffff, 'x', "Alternate Current Buffer Register 0" },
+{ "IPU_ALT_CUR_1", IPU_BASE(0x248), 0, 0xffffffff, 'x', "Alternate Current Buffer Register 1" },
+{ "IPU_CH_BUF0_RDY0", IPU_BASE(0x268), 0, 0xffffffff, 'x', "Channels Buffer 0 Ready Register 0" },
+{ "IPU_CH_BUF0_RDY1", IPU_BASE(0x26c), 0, 0xffffffff, 'x', "Channels Buffer 0 Ready Register 1" },
+{ "IPU_CH_BUF1_RDY0", IPU_BASE(0x270), 0, 0xffffffff, 'x', "Channels Buffer 1 Ready Register 0" },
+{ "IPU_CH_BUF1_RDY1", IPU_BASE(0x274), 0, 0xffffffff, 'x', "Channels Buffer 1 Ready Register 1" },
{ "CSI0_SENS_CONF", CSI0_BASE(0x00), 0, 0xffffffff, 'x', "CSI0 Sensor Configuration Register" },
{ "CSI0_SENS_FRM_SIZE", CSI0_BASE(0x04), 0, 0xffffffff, 'x', "CSI0 Sensor Frame Size Register" },
{ "CSI0_ACT_FRM_SIZE", CSI0_BASE(0x08), 0, 0xffffffff, 'x', "CSI0 Actual Frame Size Register" },
@@ -58,6 +91,9 @@ static struct reg_info regs[] =
{ "CSI1_DI", CSI1_BASE(0x20), 0, 0xffffffff, 'x', "CSI1 Data Identifier Register" },
{ "CSI1_SKIP", CSI1_BASE(0x24), 0, 0xffffffff, 'x', "CSI1 Skip Register" },
{ "CSI1_CPD_CTRL", CSI1_BASE(0x28), 0, 0xffffffff, 'x', "CSI1 Compander Control Register" },
+{ "IPU_VDI_SIZE", VDI_BASE(0x00), 0, 0xffffffff, 'x', "VDI Field Size Register" },
+{ "IPU_VDI_C", VDI_BASE(0x04), 0, 0xffffffff, 'x', "VDI Control Register" },
+{ "IPU_VDI_C2", VDI_BASE(0x08), 0, 0xffffffff, 'x', "VDI Control Register 2" },
/* CCM */
{ "CCR", 0x73fd4000, 0, 0xffffffff, 'x', "CCM Control Register" },
{ "CCDR", 0x73fd4004, 0, 0xffffffff, 'x', "CCM Control Divider Register" },
diff --git a/target/linux/debug/imxregs/imxregs.c b/target/linux/debug/imxregs/imxregs.c
index 90ad295..84c5885 100644
--- a/target/linux/debug/imxregs/imxregs.c
+++ b/target/linux/debug/imxregs/imxregs.c
@@ -35,7 +35,7 @@
#include "imx27regs.h"
#elif defined(IMX28)
#include "imx28regs.h"
-#elif defined(IMX51)
+#elif defined(IMX51) || defined(IMX53)
#include "imx5regs.h"
#else
#include "imxregs.h"
hooks/post-receive
--
armadeus
|
