Search Results for "hdl" - Page 2
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Showing 40 open source projects for "hdl"
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This is a Viterbi HDL Code Generator (VHCG). It can generate the Verilog HDL codes of some kind of Viterbi Decoder which is scalable and parameterized. In-place-state-metric-storage is used in these decoders. I purpose that it can reduce repeated works i
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s2vhdl extracts structural information from SystemC HDL programs. The output is in VHDL code and graphical diagrams. GCC compiler is used as a C++ frontend.
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OpenVGA is an free and open FPGA-based implementation of a VGA compatible graphics adapter, and utilising low-cost hardware. The project includes the PCB schematic and artwork, Verilog HDL, firmware assembly code, and driver source code.
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Scicos-HDL is a tool to design digital circuit system; it integrates the hardware circuit, algorithm and Scilab/Scicos environment as a plat for digital circuit design, simulation and Hardware Description Language generation. ZhangDong & KangCai
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Sister is high-level synthesizer for SoC design . It analyzes SystemC(based on C++ language) source code and creates Verilog HDL source code.
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HDLObf is intended to be a HDL Obfuscator and identifier name change utility. Primarily designed for Verilog/SystemVerilog support will be added for VHDL/SystemC in future.
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F- is an ANSish Forth that uses a VM generator to compile Forth into C-based VM suitable for living in a C-based (or assembly or HDL) microcontroller project. The VM supplies 32-bit math, I/O, multitasking and debugger in a ROM footprint as small as 4kB.
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Parallelsimu provides interfaces for parallel simulation of RTL descriptions of complex hardware designs(SoCs, CPUs and etc.) written in Verilog HDL.
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libLCS is a hardware description library in C++ aiming to be as powerfull and easy as the Verilog HDL. It currently supports logic gates, flipflops, clock, and facilitates delays, continuous assignments and variable value dumping into VCD files.
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Desktop and Mobile Device Management SoftwareDesktop Central is a unified endpoint management (UEM) solution that helps in managing servers, laptops, desktops, smartphones, and tablets from a central location.
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The Register Description Language (RDL) is an object modeling language used to specify and implement software accessible hardware registers and memories. A RDL compiler can create synthesizable HDL, documentation, driver code, system-c models, and more.
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IVI is a graphical, interactive user-interface to various Open-Source HDL simulators. IVI is transitioning to using the Eclipse application framework.
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C++ template classes for Multi-Value Logic support arbitrary precision and user defined Multi-Value Logic types. This library comes with pre-defined data types: integer, boolean, bit, logic, std_logic, bit_vector, logic_vector and std_logic_vector.
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RSTK is a C language program that generates Reed-Solomon HDL source code modules that can be compiled and synthesized using standard VHDL or Verilog compilers and synthesis tools.
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Verilator converts synthesizable Verilog HDL modules into SystemC modules. This enables users with Verilog code to have a publicly available co-simulation environment. For all information, see http://www.veripool.com/verilator.html.
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A behavioral synthesis tool infrastructure and software framework, translating sequential algorithms into hardware descriptions expressed in a hardware description language (HDL).