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Logic Circuit Simulation in C++ Icon

Logic Circuit Simulation in C++

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Description

libLCS is a hardware description library in C++ aiming to be as powerfull and easy as the Verilog HDL. It currently supports logic gates, flipflops, clock, and facilitates delays, continuous assignments and variable value dumping into VCD files.

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Additional Project Details

Languages

English

Intended Audience

Education, Science/Research, Telecommunications Industry

Programming Language

C++

Registered

2006-09-18

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