Showing 25 open source projects for "exe-generator"

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    HRSoft Compensation - Human Resources Software

    HRSoft is the only unified, purpose-built SaaS platform designed to transform your complex HR processes into seamless digital ones

    Manage your enterprise’s compensation lifecycle and accurately recognize top performers with a digitized, integrated system. Keep employees invested and your HR team in control while preventing compensation chaos.
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    Eptura Workplace Software

    From desk booking and visitor management, to space planning and office utilization data, Eptura Workplace helps your entire organization work smarter.

    With the world of work changed forever, it’s essential to manage your workplace and assets together to effectively create a high-performing environment. The Eptura experience combines the power of workplace management software with asset management, enabling you to effectively operate your building and facilitate hybrid work.
  • 1
    CircuiTikZ Generator

    CircuiTikZ Generator

    This software is a tool for designing electronic circuits using LaTeX.

    This software is a tool for designing electronic circuits using LaTeX. With an intuitive graphical interface, you can create complex circuits quickly and easily, while the LaTeX code generator translates your designs into code compatible with the LaTeX circuitikz library.
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    Downloads: 19 This Week
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  • 2

    AUDio MEasurement System

    PC based Oscilloscope and Spectrum analyzer using sound card

    AUDio MEasurement System - a multi-platfrom system for audio measurement through sound card in the PC. It contains: generator, oscilloscope, audio spectrum analyzer (FFT) and frequency sweep plot. Compiles and works under Linux, Windows and MacOS. Source code is available in "git" and as ZIP snapshot. For more information see README.md
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    Downloads: 78 This Week
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  • 3
    Kactus2

    Kactus2

    Kactus2 is a graphical EDA tool based on the IP-XACT standard.

    Kactus2 is a toolset for IP-XACT based SoC design and provides packaging, integration and configuration of HW and SW components, plus register design and HDL import and generation. The source code is hosted at https://github.com/kactus2/kactus2dev. An example IP library is available at https://github.com/kactus2/ipxactexamplelib Video tutorials are available at https://www.youtube.com/user/Kactus2Tutorial Issue tracker is available at https://github.com/kactus2/kactus2dev/issues For...
    Downloads: 30 This Week
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  • 4
    ... in the higher leve 5. removehierarchy : Verilog Hierarchy Removal Tool to ungroup all the instances in a given module 6. comparemoduleinterfaces - Diff module ports and parameter. Tool to compare the interfaces ( ports, parameters, SV interfaces ) between two versions of a Verilog module or two similar modules 7. Verilog Testbench Generator 8. VHDL Testbench Generator 9. Verilog Remove Assignments 10. Verilog Find Instances or Nets 11. Clock And Reset Tree Analyzer( Alpha)
    Downloads: 0 This Week
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  • RMM Software | Remote Monitoring Platform and Tools Icon
    RMM Software | Remote Monitoring Platform and Tools

    Best-in-class automation, scalability, and single-pane IT management.

    Don’t settle when it comes to managing your clients’ IT infrastructure. Exceed their expectations with ConnectWise RMM, our MSP RMM software that provides proactive tools and NOC services—regardless of device environment. With the number of new vulnerabilities rising each year, smart patching procedures have never been more important. We automatically test and deploy patches when they are viable and restrict patches that are harmful. Get better protection for clients while you spend less time managing endpoints and more time growing your business. It’s tough to locate, afford, and retain quality talent. In fact, 81% of IT leaders say it’s hard to find the recruits they need. Add ConnectWise RMM, NOC services and get the expertise and problem resolution you need to become the advisor your clients demand—without adding headcount.
  • 5
    XOR Tree Generator
    Program for creating Verilog synthesizable XOR trees for high performance designs. Supports creation of Hamming Code (ECC) generators, checkers, and GF2 Multipliers.
    Downloads: 1 This Week
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  • 6

    SmGen

    Verilog Finite State Machine (FSM) Code Generator

    SmGen is a finite state machine (FSM) generator for Verilog. On the other hand, it is not an FSM entry tool. The input is behavioral Verilog with clock boundaries specifically set by the designer. SmGen unrolls this behavioral code and generates an FSM from it in synthesizable Verilog. Clock boundaries are explicitly provided by the designer so there is good control on the expected timing
    Downloads: 0 This Week
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  • 7

    TimingDrawer

    Text based timing diagram generator

    This tool generates timing diagrams for documenting hardware design. It reads the description from a text file with a simple syntax. It generates vector graphic (EPS, SVG or EMF format). It can be used in command line mode or with a GUI. It is written in Python and works on any platform.
    Downloads: 0 This Week
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  • 8
    adms
    ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. Repository migrated to: https://github.com/Qucs/ADMS For checkout do: git clone https://github.com/Qucs/ADMS.git
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    Downloads: 6 This Week
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  • 9
    DraftCable
    Current work at: https://github.com/jcampos73/DraftCable WARNING: version 1.0.94 previous to 2016-01-22 has a BUG! Download again! Min. Req: Win XP SP3 If you get missing mfc120.dll install vcredist_x86.exe at prog folder CAD design tool for electrical and block diagrams with net list compilation. Tool for creating new parts included. DO NOT lose time copy and pasting cable datasheet. This program, unlike MS Visio or other generic tools, has specific business funcionalities like: 1.- You...
    Downloads: 0 This Week
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  • Total Network Visibility for Network Engineers and IT Managers Icon
    Total Network Visibility for Network Engineers and IT Managers

    Network monitoring and troubleshooting is hard. TotalView makes it easy.

    This means every device on your network, and every interface on every device is automatically analyzed for performance, errors, QoS, and configuration.
  • 10
    W warsztacie każdego elektronika prędzej czy później pojawi się potrzeba użycia generatora funkcyjnego. Jednak profesjonalne urządzenia tego typu są przeważnie drogie. Z pomocą przychodzi nam karta dźwiękowa komputera. Może nie jest w stanie generować sygnałów o bardzo dużej częstotliwości, ale jej zakres (20Hz – 20kHz) może się okazać przydatny, nie tylko przy testowaniu układów audio, ale też przy układach mikroprocesorowych. W ostatnim czasie pojawiła się u mnie taka potrzeba, więc...
    Downloads: 8 This Week
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  • 11

    KiCadSymGenerator

    KiCad Symbol Generator (Schematic Lib)

    This tool can generate the KiCad schematic symbol from a plain text file. Please check the example.txt for the usage.
    Downloads: 0 This Week
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  • 12
    "kdiv" is a generator of routines for optimized division by an integer constant based on the work presented in H.S. Warren's "Hacker's Delight". "kdiv" can be used to emit a generic assembly or C implementation of (signed/unsigned) division.
    Downloads: 1 This Week
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  • 13
    A IC/MEMS layout editor. Features: all angle, font generator, macros, boolean operations, design rule checker, supported formats:Calma GDSII, OASIS (Open Artwork System Interchange Standard), OpenAccess, DXF, CIF (Caltech Intermediate Form), ...
    Downloads: 3 This Week
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  • 14
    "mprfgen" is a multi-port memory generator that can be used for VHDL designs. It can generate either generic or Xilinx-specific (through component instantiation) multi-port memories.
    Downloads: 0 This Week
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  • 15
    PikLoops is a simple KDE program used to generate assembly time delays for Microchip microcontrolers using Microchip instructions.
    Downloads: 0 This Week
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  • 16
    openGL tool librarian/schematic netlist generator for PCB
    Downloads: 0 This Week
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  • 17
    F- is an ANSish Forth that uses a VM generator to compile Forth into C-based VM suitable for living in a C-based (or assembly or HDL) microcontroller project. The VM supplies 32-bit math, I/O, multitasking and debugger in a ROM footprint as small as 4kB.
    Downloads: 0 This Week
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  • 18
    A GTK+/Gnome2 graphical front end for the IW3HEV Vector Network Analyzer, also has a signal generator, and It displays graphicaly SWR, Phase, Return Loss, X impedance, Serial resistance, |Z| Impedanze, and Inductance, and capacitance.
    Downloads: 1 This Week
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  • 19
    This software generate a complete project for ARM LPC 2119,2129,2292,2294,2194. It generate the main file, Makefile, and a initialisation file with a graphical interface. It's very useful because it calculate all value for the peripherals.
    Downloads: 4 This Week
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  • 20
    An automatic 2D Delaunay mesh generator and solver for Finite Element Analysis. Can solve 2D field problems (Poisson and Helmholtz Equations). Can use LAPACK/ARPACK solvers producing OpenGL/Postscript output. Uses C/GTK/GTKGLExt/MFC. Runs on Win32/Unix.
    Downloads: 2 This Week
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  • 21
    The main target of this project is to create a Open Source System on Chip generator for FPGA. This generator will use following technologies: Python, Wishbone SoC bus specifications and VHDL.
    Downloads: 0 This Week
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  • 22
    System on Chip design generator.
    Downloads: 0 This Week
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  • 23
    Tool-independent Makefile generator for VHDL models.
    Downloads: 0 This Week
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  • 24
    UVE

    UVE

    Unified Verification Environment

    The aim of the UVE project is to create software that automatically generates a verification testbench (TB) written in SystemVerilog (SV) and integrating the UVM methodology. UVE makes the rapid development of a verification environment a simple process. The generated TB is directly able to perform random actions on the DUV (design under verification). For this UVE provides a graphical user interface, a code generator, compilation scripts and a library of verification IPs (VIP). One...
    Downloads: 0 This Week
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  • 25

    bldc

    BLDC ESC

    ... have used neodymium magnets BLDC, CD drive BLDC and car generator as BLDC motor without any modification in software, hardware - it just works. Schematic is done using EAGLE PCB software Software is witten in spin langue. If You want to improve this project then put your thoughts into discussion section. Or if You have some burning information - drop me an email "htamme@ut.ee" enjoy,
    Downloads: 0 This Week
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