13-12-2016 Kactus2 code has been relocated to https://github.com/kactus2/kactus2dev.
Kactus2 is the first graphical open source IP-XACT tool aiming at superior usability among EDA tools. It started as a simple IP-XACT editor but currently has tools for complete IP-XACT design flow, e.g. Verilog/VHDL import, component, design and configuration editors and code generators. The user input is validated in real-time, which helps to locate potential design problems immediately. Visualization is included for e.g. Memory maps and file dependencies. Kactus2 is based on IEEE 1685-2014 from version 3.0 onward. The older releases are based on IP-XACT 1.4. A conversion tool is available upon request.
Issue tracker is available at https://kactus2.cs.tut.fi Sample libraries and plugins at https://github.com/kactus2 Please help us make Kactus2 even better http://funbase.cs.tut.fi/feedback
- Create "electronic datasheets" of your existing IPs to simplify integration
- Import IP-XACT libraries by other vendors, check their integrity, export your IP library
- Create HW designs with hierarchy
- Create quick draft block diagram blueprints for IP, system-on-chip, printed circuit board (PCB), and product. All these are stored in IP-XACT format
- Create system designs that map SW to HW
- Create SW architecture in MCAPI communication abstraction (MCAPI endpoints and channels)
- Configure all designs: set parameters, active views
- Generate structural top-level VHDL and Verilog
- Generate code templates for a new IP (VHDL entities, Verilog modules, C headers) based on their IP-XACT component description
- Generate synthesis and simulation scripts, perform SW build for all processors
- Generate combined documentation from all blocks, through all hierarchy levels