Activity for Eclipse Verilog editor
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D. Nitecki modified a comment on discussion Open Discussion
I have found that the coloring behavior is different in Verilog and VHDL. In Verilog in/out/inout port coloring is propagating through the whole file, but in VHDL the port coloring is limited only to the entity. (for Verilog and VHDL) I think adding coloring also to component/module and it's instantiation would speed up making connections.
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I have found that the coloring behavior is different in Verilog and VHDL. In Verilog in/out/inout port coloring is propagating through the whole file, but in VHDL the port coloring is limited only to the entity. (for Verilog and VHDL) I think adding coloring also to component/module and it's instantiation would speed up making connections.
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I have found that the coloring behavior is different in Verilog and VHDL. In Verilog in/out/inout port coloring is propagating through the whole file, but in VHDL the port coloring is limited only to the entity. (for Verilog and VHDL) I think adding coloring also to component/module and it's instantiation would speed up making connections.
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This plugin is great! I like ports coloring in entity and I think adding coloring also to component/module and it's instantiation would speed up making connections. Making connections inside one entity when having a lot of modules is a pain - you always need to check ports directions (e.g. to make open ports for outputs and zeros for inputs).
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Pavlo Skliar created ticket #95
Error highlighting
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aghoras modified a blog post
Version 1.5 Released
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Version 1.5 Released
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Eclipse Verilog editor released /veditor runtime/VEditor 1.5/net.sourceforge.veditor_1.5.0.jar
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Added support for Interface declarations updates in VHDL-2008. Generics can now include types, packages, procedures, and packages
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Added VHDL-2008 Test file
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Added test syntax for VHDL-2008
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Added support for VHDL-2008 context definition and context reference
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Andi modified a comment on discussion Open Discussion
Hi Folks, I really like the Eclipse Verilog editor. But I wonder if some SystemVerilog features could be supproted as well. To be precise the following code snippets are causing problems. packed arrays: wire [10:0][31:0] my_packed_array; or nested `defines: define FACTOR *10 define VALUE 1234 `FACTOR parameter val = `VALUE; `` What annoys most: Whenever the parser stumbles over such an issue, it stops processing. So when this occurs at the top of a file, all signals below that line are not parsed...
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Hi Folks, I really like the Eclipse Verilog editor. But I wonder if some SystemVerilog features could be supproted as well. To be precise the following code snippets are causing problems. packed arrays: wire [10:0][31:0] my_packed_array; or nested `defines: define FACTOR *10 define VALUE 1234 FACTOR parameter val =VALUE; `` What annoys most: Whenever the parser stumbles over such an issue, it stops processing. So when this occurs at the top of a file, all signals below that line are not parsed anymore...
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Added support for "force" and "release" VHDL-20...
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KOBAYASHI Tadashi posted a comment on discussion Help
Hi HyungKi, You can add "File Association" in Eclipse Preferences. Can you open Preferences...
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HyungKi Jeong modified a comment on discussion Help
Hi, I'm HyungKi Jeong. It's good to use. Thanks. But supported verilog file type...
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Hi, I'm HyungKi Jeong. It's good to use. Thanks. But supported verilog file type...
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Hi, I'm HyungKi Jeong. It's good to use. Thanks. But supported verilog file type...
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Support Verilog-AMS keyword.
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Hi, I update the site right now. You can install version 1.2.2.a which is latest...
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Change version to 1.2.2.a
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Add syntax coloring of port, signal and constant.
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Hi, Thank you for your information. I didn't know ISO-8859-1. Now I can see ISO-8859-1...
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Vesion 1.2.2 Released
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HorstWe posted a comment on ticket #3
Hi Tadashi, thank you for applying the patch. Those characters are from the ISO/IEC...
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Hi, I applied the VHDL-2008-Features.patch and commited to SVN, except two lines....
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Applied patch to support some VHDL 2008 Feature...
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Applied patch to support some VHDL 2008 Feature...
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Hi Ruben, unfortunately I haven't had time yet, but i it is planned to do it in the...
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Ruben Scheja posted a comment on ticket #3
Any updates here on integrating this patch?
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Done
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Yes, you can add me as a developer. I will integrate those changes and very lickely...
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Sorry about the delayed response. I'm swamped with work and Tadashi, (the other developer)...
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Hi, just wondering why you do not integrate this patch in your releases... I'm considering...
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Brian Trotter posted a comment on discussion Help
It now works. Thank you.
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There must be something wrong with the project's permissions. I'll look into it.
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The Create Ticket button is grayed out and reads "To create a new ticket, you must...
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Yamada Taro created ticket #5
The available version is not the latest V1.2.1, only V1.2.0 is proposed.
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Alina Yakovleva posted a comment on discussion Help
I've downloaded the latest jar file and I am trying to install it in Eclipse Kepler....
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Change version to 1.2.1.c
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Do you mean "wreal" should be treated as reserved word for syntax highlight? How...
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Thomas A created ticket #4
wreal support
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sounansu posted a comment on discussion Open Discussion
Veditor indicates warnings. "Compare bit width mismatch: 2 and 32" But I don't think...
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sqrt123 posted a comment on discussion Open Discussion
Please provide a link where the "tarred up content" can be downloaded.
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Fix insert new line bug
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Fix one character length selection occurrence
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Sourceforge unceremoniously delete the project's wiki which contained all the documentation....
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It's not a matter of money, it's a matter of time :)
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Change version to 1.2.1.b
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Update outline database when selection is chang...
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Fixed spelling
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Fixed Auto Edit Strategy by Windows new line (\...
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Change version to 1.2.1.a for development build
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Exactly matching for occurrence marker in Verilog.
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N. Coesel posted a comment on discussion Open Discussion
Would donations help to speed up the development of Veditor? If yes, please setup...
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Add AutoEditStrategy for Verilog multi-line com...
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ILLICO posted a comment on a blog post
Thanks for this new version. Now Altera encrypted files are supported, then scan...
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Very good job with the new 1.2.1 version. Now Altera encrypted files are supported....
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Vesion 1.2.1 Released
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Evaluate signal reference in Verilog condition ...
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Exclude Verilog signals from the full source co...
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Limit selection occurrence as whole word
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Fix unresolved variable problem start with "pr"
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Merge from Sjors Hettinga's repository
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Merge from Sjors Hettinga's repository
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update multi-line comment scanner in Verilog
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You are correct. We'll change that on a future release. For now, the new file template...
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GenGumby posted a comment on discussion Open Discussion
Recently downloaded VEditor, and immediately noticed that the default VHDL template...
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pirotz posted a comment on discussion Open Discussion
Sorry, this is actually a feature request but it is my first time here and I am possibly...
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Sourceforge has ungraciously deleted our project's wiki and dumped the data in some...
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It appears that the entire wiki is missing. I'm going to look into it.
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dp118m posted a comment on discussion Help
Hello! I'm trying to compile VEditor, but I get several errors (see images at https://www.evernote.com/shard/s35/sh/8203ee1c-f23e-4225-9fa8-2412a2e57a17/c1b16ffc3c06a82df0fe35fbf199a687...
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Hello, http://sourceforge.net/apps/mediawiki/veditor/index.php?title=For_Developers...
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Larry Cameron posted a comment on discussion Help
Has anyone successfully got this to run on the latest release of Eclipse (Kepler)?...
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Not it VEditor but there may be a generic eclipse plugin to do that. Here's one I...
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kairue modified a comment on discussion Help
Is it somehow possible to enable that all occurences of a text (e.g. a variable name)...
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Is it somehow possible to enable that all occurences of a text (e.g. a variable name)...
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Is it somehow possible to enabled that all occurences of a text (e.g. a variable...
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Patch to support some VHDL 2008 Features
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problem occurred
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No sorry, I still cannot find the "Create Tickets" in the "Patches" category. But...
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No sorry, I still cannot find the "Create Tickets" in the "Patches" category. But...
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Patch to support VHDL 2008 Generate statements
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The ticket permissions are set so that authenticated users can create tickets. I...
