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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-24 21:35:04
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via a708b6d25ec72c6de57ff42bdc6c0b4d52a69388 (commit)
from 85dc63011378c0a8112f99e3a02fa971f96bbc05 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit a708b6d25ec72c6de57ff42bdc6c0b4d52a69388
Author: Lars Poeschel <poe...@ma...>
Date: Tue Nov 5 16:37:43 2019 +0100
avrf.c: Use extended addressing for flash > 0x20000
The current method used for flash addressing uses 16 bit. Every access
to flash is 16 bit wide. With 16 address bits one can address 0x10000
unique locations á 16 bits thats 0x20000 bytes.
For flashes bigger than that avrs have an extended addressing with more
than 16 address bits. This is now implemented and used for flashs larger
than 0x20000 bytes.
Change-Id: Id8b6337dde3830fb3c56b9042872e040bb67c12d
Signed-off-by: Lars Pöschel <poe...@ma...>
Reviewed-on: http://openocd.zylin.com/5502
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/flash/nor/avrf.c b/src/flash/nor/avrf.c
index 178567e6b..aa8645909 100644
--- a/src/flash/nor/avrf.c
+++ b/src/flash/nor/avrf.c
@@ -142,6 +142,7 @@ static int avr_jtagprg_chiperase(struct avr_common *avr)
}
static int avr_jtagprg_writeflashpage(struct avr_common *avr,
+ const bool ext_addressing,
const uint8_t *page_buf,
uint32_t buf_size,
uint32_t addr,
@@ -152,6 +153,13 @@ static int avr_jtagprg_writeflashpage(struct avr_common *avr,
avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2310, AVR_JTAG_REG_ProgrammingCommand_Len);
+ /* load extended high byte */
+ if (ext_addressing)
+ avr_jtag_senddat(avr->jtag_info.tap,
+ NULL,
+ 0x0b00 | ((addr >> 17) & 0xFF),
+ AVR_JTAG_REG_ProgrammingCommand_Len);
+
/* load addr high byte */
avr_jtag_senddat(avr->jtag_info.tap,
NULL,
@@ -238,6 +246,7 @@ static int avrf_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t o
struct target *target = bank->target;
struct avr_common *avr = target->arch_info;
uint32_t cur_size, cur_buffer_size, page_size;
+ bool ext_addressing;
if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
@@ -258,6 +267,11 @@ static int avrf_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t o
if (ERROR_OK != avr_jtagprg_enterprogmode(avr))
return ERROR_FAIL;
+ if (bank->size > 0x20000)
+ ext_addressing = true;
+ else
+ ext_addressing = false;
+
cur_size = 0;
while (count > 0) {
if (count > page_size)
@@ -265,6 +279,7 @@ static int avrf_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t o
else
cur_buffer_size = count;
avr_jtagprg_writeflashpage(avr,
+ ext_addressing,
buffer + cur_size,
cur_buffer_size,
offset + cur_size,
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/avrf.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-24 17:28:36
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 85dc63011378c0a8112f99e3a02fa971f96bbc05 (commit)
from b7c13323e702c7aa1d05d952708d1e408c47fae1 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 85dc63011378c0a8112f99e3a02fa971f96bbc05
Author: Antonio Borneo <bor...@gm...>
Date: Fri Mar 6 10:30:25 2020 +0100
jtag: fix command "adapter [de]assert" with dap direct
The commit fafe6dfc9cd8 ("adapter: add command "adapter [de]assert
srst|trst [[de]assert srst|trst]"") was proposed in gerrit well
before commit a61ec3c1d73d ("adi_v5_dapdirect: add support for
adapter drivers that provide DAP API") get merged, so it didn't
include a complete support for dap direct.
The merge upstream of the two commits lacks the support by command
"adapter [de]assert" for dap direct
Let command command "adapter [de]assert" handle dap direct.
Change-Id: I1a69f8ee877c8fd57598ed4ad9d71da61d15457c
Fixes: commit fafe6dfc9cd8 ("adapter: add command "adapter [de]assert srst|trst [[de]assert srst|trst]"")
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5515
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/jtag/core.c b/src/jtag/core.c
index c5011e522..001523365 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -2021,7 +2021,8 @@ int adapter_resets(int trst, int srst)
/* adapters without trst signal will eventually use tlr sequence */
jtag_add_reset(trst, srst);
return ERROR_OK;
- } else if (transport_is_swd() || transport_is_hla()) {
+ } else if (transport_is_swd() || transport_is_hla() ||
+ transport_is_dapdirect_swd() || transport_is_dapdirect_jtag()) {
if (trst == TRST_ASSERT) {
LOG_ERROR("transport %s has no trst signal",
get_current_transport()->name);
-----------------------------------------------------------------------
Summary of changes:
src/jtag/core.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-24 17:21:15
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via b7c13323e702c7aa1d05d952708d1e408c47fae1 (commit)
from 4d7c48fb80cb65d53ad3bcd57182ffb79b61e5f3 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit b7c13323e702c7aa1d05d952708d1e408c47fae1
Author: Antonio Borneo <bor...@gm...>
Date: Sun Mar 8 16:40:05 2020 +0100
doc: fix texinfo files attributes on Windows
While installing git on Windows, the user is prompted by a dialog
"Configuring the line ending conversions" to select the value for
the git property "core.autocrlf". The default choice proposed by
the installer is "Checkout Windows-style, commit Unix-style line
endings", that corresponds to "core.autocrlf=true".
Even if the dialog provides technical explanation of the different
choices, most users will blindly accept the default proposal.
With "core.autocrlf=true" git will convert to DOS mode all the
text files during "clone" (so can be edited by any crap Windows
tool) and convert back to UNIX mode during "push" operation.
While this is safe enough for C and TCL files, it breaks the
texinfo files.
The trailing '@' character used for command continuation in
https://www.gnu.org/software/texinfo/manual/texinfo/html_node/Def-Cmd-Continuation-Lines.html
does not accept being followed by CR+LF (DOS mode), generating a
build error. Same error can be replicated on Linux by passing the
file doc/openocd.texi through "unix2dos" command.
Tentative to fix this has already been proposed in
http://openocd.zylin.com/5294
http://openocd.zylin.com/5413
by breaking the command continuation syntax, which is a no go.
The correct fix would require to force/suggest all the Windows
users to get rid of the crap DOS mode, but this could have side
effects.
To workaround the issue, add a .gitattributes file in the doc
folder, specifying a local conversion attribute for the files .txt
and .texi in the doc folder and overriding the eventual incorrect
global value of "core.autocrlf" selected during installation.
The local attribute "text eol=lf" is equivalent to the global one
"core.autocrlf=input".
Change-Id: I468a8f8125b6bc4628fce6c66eb082824ba3413f
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5499
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/doc/.gitattributes b/doc/.gitattributes
new file mode 100644
index 000000000..dcf6d037c
--- /dev/null
+++ b/doc/.gitattributes
@@ -0,0 +1,3 @@
+# Avoid DOS conversion of texinfo files during git clone
+*.texi text eol=lf
+*.txt text eol=lf
-----------------------------------------------------------------------
Summary of changes:
doc/.gitattributes | 3 +++
1 file changed, 3 insertions(+)
create mode 100644 doc/.gitattributes
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-24 17:19:44
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 4d7c48fb80cb65d53ad3bcd57182ffb79b61e5f3 (commit)
from d35c44c743d6f471697ed1d204fe5447fd47cefd (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 4d7c48fb80cb65d53ad3bcd57182ffb79b61e5f3
Author: Edward Fewell <ef...@ti...>
Date: Mon Mar 2 14:04:24 2020 -0600
tcl/target: Enable using vectreset for CC3320SF targets
On CC32xx family of devices, sysrequest is disabled, and
vectreset is blocked by the boot loader (stops in a while(1)
statement). srst reset can leave the target in a state
that prevents debug.
This change enables using vectreset on SF variants by
moving the PC to the start of the user application in
internal flash. This allows for a more reliable reset,
but with two caveats:
1) This only works for the SF variant with internal
flash.
2) This only resets the CPU and not any peripherals.
Tested on CC3220SF rev B Launchpad in both SWD and
JTAG modes. Confirmed proper behavior of reset,
reset init, reset halt, and reset run commands.
Update: reworked per comment in code review. Re-tested
with CC3220SF Launchpad as both CC3220SF and as
CC32xx board to confirm reset behavior as expected.
Update: Added adapter srst delay 1100 line to the
CC3200 LaunchXL configuration file.
Change-Id: Ibc042d785c846c2223ae55b8f2410b75ed2df354
Signed-off-by: Edward Fewell <ef...@ti...>
Reviewed-on: http://openocd.zylin.com/5489
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/board/ti_cc3200_launchxl.cfg b/tcl/board/ti_cc3200_launchxl.cfg
index 34f9bffb8..b37b406ad 100644
--- a/tcl/board/ti_cc3200_launchxl.cfg
+++ b/tcl/board/ti_cc3200_launchxl.cfg
@@ -18,3 +18,4 @@ set WORKAREASIZE 0x40000
source [find target/ti_cc32xx.cfg]
reset_config srst_only
+adapter srst delay 1100
diff --git a/tcl/board/ti_cc32xx_launchpad.cfg b/tcl/board/ti_cc32xx_launchpad.cfg
index 1df461a93..d0f2a831c 100644
--- a/tcl/board/ti_cc32xx_launchpad.cfg
+++ b/tcl/board/ti_cc32xx_launchpad.cfg
@@ -5,3 +5,6 @@ source [find interface/xds110.cfg]
adapter speed 8500
transport select swd
source [find target/ti_cc32xx.cfg]
+
+reset_config srst_only
+adapter srst delay 1100
diff --git a/tcl/target/ti_cc3220sf.cfg b/tcl/target/ti_cc3220sf.cfg
index f7d9bfe17..3e758e6ab 100644
--- a/tcl/target/ti_cc3220sf.cfg
+++ b/tcl/target/ti_cc3220sf.cfg
@@ -10,3 +10,31 @@ source [find target/ti_cc32xx.cfg]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
+
+#
+# On CC32xx family of devices, sysreqreset is disabled, and vectreset is
+# blocked by the boot loader (stops in a while(1) statement). srst reset can
+# leave the target in a state that prevents debug. The following uses the
+# soft_reset_halt command to reset and halt the target. Then the PC and stack
+# are initialized from internal flash. This allows for a more reliable reset,
+# but with two caveats: it only works for the SF variant that has internal
+# flash, and it only resets the CPU and not any peripherals.
+#
+
+proc ocd_process_reset_inner { MODE } {
+
+ soft_reset_halt
+
+ # Intialize MSP, PSP, and PC from vector table at flash 0x01000800
+ mem2array boot 32 0x01000800 2
+
+ reg msp $boot(0)
+ reg psp $boot(0)
+ reg pc $boot(1)
+
+ if { 0 == [string compare $MODE run ] } {
+ resume
+ }
+
+ cc32xx.cpu invoke-event reset-end
+}
diff --git a/tcl/target/ti_cc32xx.cfg b/tcl/target/ti_cc32xx.cfg
index 6f91d3fd3..e3e3ebc92 100644
--- a/tcl/target/ti_cc32xx.cfg
+++ b/tcl/target/ti_cc32xx.cfg
@@ -59,6 +59,3 @@ if { [info exists WORKAREASIZE] } {
}
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-reset_config srst_only
-adapter srst delay 1100
-----------------------------------------------------------------------
Summary of changes:
tcl/board/ti_cc3200_launchxl.cfg | 1 +
tcl/board/ti_cc32xx_launchpad.cfg | 3 +++
tcl/target/ti_cc3220sf.cfg | 28 ++++++++++++++++++++++++++++
tcl/target/ti_cc32xx.cfg | 3 ---
4 files changed, 32 insertions(+), 3 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-24 17:19:13
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via d35c44c743d6f471697ed1d204fe5447fd47cefd (commit)
from 87a4158acf56863d4e5e70afc33791f631b6c693 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit d35c44c743d6f471697ed1d204fe5447fd47cefd
Author: Edward Fewell <ef...@ti...>
Date: Wed Mar 4 15:14:48 2020 -0600
drivers: xds110: Add support of alternate XDS110 configurations
The XDS110 supports alternate configurations, each of which has
a unique vid/pid:
0451/bef3 -- Standard (legacy) configuration
0451/bef4 -- Drag-n-Drop configuration
1cbe/02a5 -- CMSIS-DAP 2.0 on BULK interface configuration
It's not important to OpenOCD what the differences are except
that OpenOCD needs to know how to connect using the different
vid/pids and, in the case of the last one, use a different
interface for the debug connection.
Updated the XDS110 source to search for all possible
configurations, and updated the udev rules file to enable
user access to the alternate configuraitons.
For the curious, you can download the latest XDS emupack from
software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds_software_package_download.html
Install to an empty directory, and documentation for the
XDS110 is located in the .../ccs_base/common/uscif/xds110
of the installation.
Updated for comments in code review. Changed const variable
names to lower case. Reworked interface/endpoint setting
to use arrays suggestion.
Change-Id: Icc9d11c6618f43d87ae8171c78ebf238800d3ac2
Signed-off-by: Edward Fewell <ef...@ti...>
Reviewed-on: http://openocd.zylin.com/5494
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/contrib/60-openocd.rules b/contrib/60-openocd.rules
index ac574bb14..990412752 100644
--- a/contrib/60-openocd.rules
+++ b/contrib/60-openocd.rules
@@ -139,6 +139,8 @@ ATTRS{idVendor}=="1cbe", ATTRS{idProduct}=="00fd", MODE="660", GROUP="plugdev",
# TI XDS110 Debug Probe (Launchpads and Standalone)
ATTRS{idVendor}=="0451", ATTRS{idProduct}=="bef3", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0451", ATTRS{idProduct}=="bef4", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1cbe", ATTRS{idProduct}=="02a5", MODE="660", GROUP="plugdev", TAG+="uaccess"
# TI Tiva-based ICDI and XDS110 probes in DFU mode
ATTRS{idVendor}=="1cbe", ATTRS{idProduct}=="00ff", MODE="660", GROUP="plugdev", TAG+="uaccess"
diff --git a/src/jtag/drivers/xds110.c b/src/jtag/drivers/xds110.c
index 9ca200e79..8a832adf0 100644
--- a/src/jtag/drivers/xds110.c
+++ b/src/jtag/drivers/xds110.c
@@ -66,15 +66,6 @@
#endif
#define MAX_RESULT_QUEUE (MAX_DATA_BLOCK / 4)
-/***************************************************************************
- * USB Connection Endpoints *
- ***************************************************************************/
-
-/* Bulk endpoints used by the XDS110 debug interface */
-#define INTERFACE_DEBUG (2)
-#define ENDPOINT_DEBUG_IN (3 | LIBUSB_ENDPOINT_IN)
-#define ENDPOINT_DEBUG_OUT (2 | LIBUSB_ENDPOINT_OUT)
-
/***************************************************************************
* XDS110 Firmware API Definitions *
***************************************************************************/
@@ -227,6 +218,13 @@ struct xds110_info {
unsigned char read_payload[USB_PAYLOAD_SIZE];
unsigned char write_packet[3];
unsigned char write_payload[USB_PAYLOAD_SIZE];
+ /* Device vid/pid */
+ uint16_t vid;
+ uint16_t pid;
+ /* Debug interface */
+ uint8_t interface;
+ uint8_t endpoint_in;
+ uint8_t endpoint_out;
/* Status flags */
bool is_connected;
bool is_cmapi_connected;
@@ -259,6 +257,11 @@ struct xds110_info {
static struct xds110_info xds110 = {
.ctx = NULL,
.dev = NULL,
+ .vid = 0,
+ .pid = 0,
+ .interface = 0,
+ .endpoint_in = 0,
+ .endpoint_out = 0,
.is_connected = false,
.is_cmapi_connected = false,
.is_cmapi_acquired = false,
@@ -320,12 +323,20 @@ static bool usb_connect(void)
struct libusb_device_descriptor desc;
- uint16_t vid = 0x0451;
- uint16_t pid = 0xbef3;
+ /* The vid/pids of possible XDS110 configurations */
+ uint16_t vids[] = { 0x0451, 0x0451, 0x1cbe };
+ uint16_t pids[] = { 0xbef3, 0xbef4, 0x02a5 };
+ /* Corresponding interface and endpoint numbers for configurations */
+ uint8_t interfaces[] = { 2, 2, 0 };
+ uint8_t endpoints_in[] = { 3, 3, 1 };
+ uint8_t endpoints_out[] = { 2, 2, 1 };
+
ssize_t count = 0;
ssize_t i = 0;
int result = 0;
bool found = false;
+ uint32_t device = 0;
+ bool match = false;
/* Initialize libusb context */
result = libusb_init(&ctx);
@@ -342,13 +353,21 @@ static bool usb_connect(void)
if (0 == result) {
/* Scan through list of devices for any XDS110s */
for (i = 0; i < count; i++) {
- /* Check for device VID/PID match */
+ /* Check for device vid/pid match */
libusb_get_device_descriptor(list[i], &desc);
- if (desc.idVendor == vid && desc.idProduct == pid) {
+ match = false;
+ for (device = 0; device < sizeof(vids)/sizeof(vids[0]); device++) {
+ if (desc.idVendor == vids[device] &&
+ desc.idProduct == pids[device]) {
+ match = true;
+ break;
+ }
+ }
+ if (match) {
result = libusb_open(list[i], &dev);
if (0 == result) {
- const int MAX_DATA = 256;
- unsigned char data[MAX_DATA + 1];
+ const int max_data = 256;
+ unsigned char data[max_data + 1];
*data = '\0';
/* May be the requested device if serial number matches */
@@ -359,7 +378,7 @@ static bool usb_connect(void)
} else {
/* Get the device's serial number string */
result = libusb_get_string_descriptor_ascii(dev,
- desc.iSerialNumber, data, MAX_DATA);
+ desc.iSerialNumber, data, max_data);
if (0 < result &&
0 == strcmp((char *)data, (char *)xds110.serial)) {
found = true;
@@ -387,6 +406,15 @@ static bool usb_connect(void)
}
if (found) {
+ /* Save the vid/pid of the device we're using */
+ xds110.vid = vids[device];
+ xds110.pid = pids[device];
+
+ /* Save the debug interface and endpoints for the device */
+ xds110.interface = interfaces[device];
+ xds110.endpoint_in = endpoints_in[device] | LIBUSB_ENDPOINT_IN;
+ xds110.endpoint_out = endpoints_out[device] | LIBUSB_ENDPOINT_OUT;
+
/* Save the context and device handles */
xds110.ctx = ctx;
xds110.dev = dev;
@@ -395,7 +423,7 @@ static bool usb_connect(void)
(void)libusb_set_auto_detach_kernel_driver(dev, 1);
/* Claim the debug interface on the XDS110 */
- result = libusb_claim_interface(dev, INTERFACE_DEBUG);
+ result = libusb_claim_interface(dev, xds110.interface);
} else {
/* Couldn't find an XDS110, flag the error */
result = -1;
@@ -405,7 +433,7 @@ static bool usb_connect(void)
if (0 != result) {
if (NULL != dev) {
/* Release the debug and data interface on the XDS110 */
- (void)libusb_release_interface(dev, INTERFACE_DEBUG);
+ (void)libusb_release_interface(dev, xds110.interface);
libusb_close(dev);
}
if (NULL != ctx)
@@ -427,7 +455,7 @@ static void usb_disconnect(void)
{
if (NULL != xds110.dev) {
/* Release the debug and data interface on the XDS110 */
- (void)libusb_release_interface(xds110.dev, INTERFACE_DEBUG);
+ (void)libusb_release_interface(xds110.dev, xds110.interface);
libusb_close(xds110.dev);
xds110.dev = NULL;
}
@@ -451,7 +479,7 @@ static bool usb_read(unsigned char *buffer, int size, int *bytes_read,
if (0 == timeout)
timeout = DEFAULT_TIMEOUT;
- result = libusb_bulk_transfer(xds110.dev, ENDPOINT_DEBUG_IN, buffer, size,
+ result = libusb_bulk_transfer(xds110.dev, xds110.endpoint_in, buffer, size,
bytes_read, timeout);
return (0 == result) ? true : false;
@@ -466,13 +494,13 @@ static bool usb_write(unsigned char *buffer, int size, int *written)
if (NULL == xds110.dev || NULL == buffer)
return false;
- result = libusb_bulk_transfer(xds110.dev, ENDPOINT_DEBUG_OUT, buffer,
+ result = libusb_bulk_transfer(xds110.dev, xds110.endpoint_out, buffer,
size, &bytes_written, 0);
while (LIBUSB_ERROR_PIPE == result && retries < 3) {
/* Try clearing the pipe stall and retry transfer */
- libusb_clear_halt(xds110.dev, ENDPOINT_DEBUG_OUT);
- result = libusb_bulk_transfer(xds110.dev, ENDPOINT_DEBUG_OUT, buffer,
+ libusb_clear_halt(xds110.dev, xds110.endpoint_out);
+ result = libusb_bulk_transfer(xds110.dev, xds110.endpoint_out, buffer,
size, &bytes_written, 0);
retries++;
}
@@ -1360,6 +1388,7 @@ static void xds110_show_info(void)
{
uint32_t firmware = xds110.firmware;
+ LOG_INFO("XDS110: vid/pid = %04x/%04x", xds110.vid, xds110.pid);
LOG_INFO("XDS110: firmware version = %d.%d.%d.%d",
(((firmware >> 28) & 0xf) * 10) + ((firmware >> 24) & 0xf),
(((firmware >> 20) & 0xf) * 10) + ((firmware >> 16) & 0xf),
-----------------------------------------------------------------------
Summary of changes:
contrib/60-openocd.rules | 2 ++
src/jtag/drivers/xds110.c | 75 ++++++++++++++++++++++++++++++++---------------
2 files changed, 54 insertions(+), 23 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-24 17:18:18
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 87a4158acf56863d4e5e70afc33791f631b6c693 (commit)
via 76ba9bd0b373e0bddfe944e411550b0a0304b238 (commit)
from c9ebd488eadfaec6154db5747f376323f587766d (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 87a4158acf56863d4e5e70afc33791f631b6c693
Author: Edward Fewell <ef...@ti...>
Date: Wed Mar 4 17:24:33 2020 -0600
drivers: xds110: Clean up command syntax and documentation
Arrange all commands under a top level xds110 command. Fix
documentation to properly reflect the current functionality.
Also updated the links in the document to the new permanent
links for the XDS110 only support.
Patch updated for comments from code review. Return
ERROR_COMMAND_SYNTAX_ERROR for wrong number of args in
commands. Added deprecated commands to src/jtag/startup.tcl.
Change-Id: Ica45f65e1fdf7fa72866f4e28c4f6bce428d8ac9
Signed-off-by: Edward Fewell <ef...@ti...>
Reviewed-on: http://openocd.zylin.com/5495
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 25554f87a..4665092d1 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -537,15 +537,25 @@ debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/
@item @b{TI XDS110 Debug Probe}
@* The XDS110 is included as the embedded debug probe on many Texas Instruments
-LaunchPad evaluation boards.
-@* The XDS110 is also available as a stand-alone USB debug probe. The XDS110
-stand-alone probe has the additional ability to supply voltage to the target
-board via its AUX FUNCTIONS port. Use the
-@command{xds110_supply_voltage <millivolts>} command to set the voltage. 0 turns
-off the supply. Otherwise, the supply can be set to any value in the range 1800
-to 3600 millivolts.
-@* Link: @url{http://processors.wiki.ti.com/index.php/XDS110}
-@* Link: @url{http://processors.wiki.ti.com/index.php/XDS_Emulation_Software_Package#XDS110_Support_Utilities}
+LaunchPad evaluation boards. The XDS110 is also available as a stand-alone USB
+debug probe with the added capability to supply power to the target board. The
+following commands are supported by the XDS110 driver:
+@*@deffn {Config Command} {xds110 serial} serial_string
+Specifies the serial number of which XDS110 probe to use. Otherwise, the first
+XDS110 found will be used.
+@end deffn
+@*@deffn {Config Command} {xds110 supply} voltage_in_millivolts
+Available only on the XDS110 stand-alone probe. Sets the voltage level of the
+XDS110 power supply. A value of 0 leaves the supply off. Otherwise, the supply
+can be set to any value in the range 1800 to 3600 millivolts.
+@end deffn
+@*@deffn {Command} {xds110 info}
+Displays information about the connected XDS110 debug probe (e.g. firmware
+version).
+@end deffn
+@* Further information can be found at the following sites:
+@* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds110.html}
+@* Link: @url{https://software-dl.ti.com/ccs/esd/documents/xdsdebugprobes/emu_xds_software_package_download.html#xds110-support-utilities}
@end itemize
@section IBM PC Parallel Printer Port Based
diff --git a/src/jtag/drivers/xds110.c b/src/jtag/drivers/xds110.c
index 085d85f4c..9ca200e79 100644
--- a/src/jtag/drivers/xds110.c
+++ b/src/jtag/drivers/xds110.c
@@ -2028,11 +2028,8 @@ COMMAND_HANDLER(xds110_handle_serial_command)
xds110.serial[i] = (char)serial[i];
xds110.serial[len] = 0;
- } else {
- LOG_ERROR("XDS110: expected exactly one argument to xds110_serial "
- "<serial-number>");
- return ERROR_FAIL;
- }
+ } else
+ return ERROR_COMMAND_SYNTAX_ERROR;
return ERROR_OK;
}
@@ -2053,11 +2050,8 @@ COMMAND_HANDLER(xds110_handle_supply_voltage_command)
return ERROR_FAIL;
}
xds110.voltage = voltage;
- } else {
- LOG_ERROR("XDS110: expected one argument to xds110_supply_voltage "
- "<millivolts>");
- return ERROR_FAIL;
- }
+ } else
+ return ERROR_COMMAND_SYNTAX_ERROR;
return ERROR_OK;
}
@@ -2067,33 +2061,33 @@ static const struct command_registration xds110_subcommand_handlers[] = {
.name = "info",
.handler = &xds110_handle_info_command,
.mode = COMMAND_EXEC,
- .usage = "",
.help = "show XDS110 info",
- },
- COMMAND_REGISTRATION_DONE
-};
-
-static const struct command_registration xds110_command_handlers[] = {
- {
- .name = "xds110",
- .mode = COMMAND_ANY,
- .help = "perform XDS110 management",
- .usage = "<cmd>",
- .chain = xds110_subcommand_handlers,
+ .usage = "",
},
{
- .name = "xds110_serial",
+ .name = "serial",
.handler = &xds110_handle_serial_command,
.mode = COMMAND_CONFIG,
.help = "set the XDS110 probe serial number",
.usage = "serial_string",
},
{
- .name = "xds110_supply_voltage",
+ .name = "supply",
.handler = &xds110_handle_supply_voltage_command,
.mode = COMMAND_CONFIG,
.help = "set the XDS110 probe supply voltage",
- .usage = "supply_voltage (millivolts)",
+ .usage = "voltage_in_millivolts",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration xds110_command_handlers[] = {
+ {
+ .name = "xds110",
+ .mode = COMMAND_ANY,
+ .help = "perform XDS110 management",
+ .usage = "",
+ .chain = xds110_subcommand_handlers,
},
COMMAND_REGISTRATION_DONE
};
diff --git a/src/jtag/startup.tcl b/src/jtag/startup.tcl
index 8fc3ad5ef..f8c4ca0bf 100644
--- a/src/jtag/startup.tcl
+++ b/src/jtag/startup.tcl
@@ -216,4 +216,14 @@ proc ftdi_location args {
eval adapter usb location $args
}
+proc xds110_serial args {
+ echo "DEPRECATED! use 'xds110 serial' not 'xds110_serial'"
+ eval xds110 serial $args
+}
+
+proc xds110_supply_voltage args {
+ echo "DEPRECATED! use 'xds110 supply' not 'xds110_supply_voltage'"
+ eval xds110 supply $args
+}
+
# END MIGRATION AIDS
commit 76ba9bd0b373e0bddfe944e411550b0a0304b238
Author: Edward Fewell <ef...@ti...>
Date: Mon Mar 2 12:22:12 2020 -0600
tcl/target: Use sysresetreq for MSP432 targets
Confirmed that sysresetreq is supported and works better
for MSP432P4 and MSP432E4 targets than srst that was
previously being used.
Tested on MSP432P4111, MSP432P401R, and MSP432E401Y
Launchpads.
Change-Id: I1454c3379b9300bc133f82a766daeaefb98dbaac
Signed-off-by: Edward Fewell <ef...@ti...>
Reviewed-on: http://openocd.zylin.com/5488
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/ti_msp432.cfg b/tcl/target/ti_msp432.cfg
index 146e7ee21..77f81da69 100644
--- a/tcl/target/ti_msp432.cfg
+++ b/tcl/target/ti_msp432.cfg
@@ -42,10 +42,10 @@ if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE 0x4000
}
+
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
-reset_config srst_only
-adapter srst delay 100
+cortex_m reset_config sysresetreq
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 28 +++++++++++++++++++---------
src/jtag/drivers/xds110.c | 44 +++++++++++++++++++-------------------------
src/jtag/startup.tcl | 10 ++++++++++
tcl/target/ti_msp432.cfg | 4 ++--
4 files changed, 50 insertions(+), 36 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-24 17:17:50
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via c9ebd488eadfaec6154db5747f376323f587766d (commit)
from bff1b6f05a56eed8e150c25d925bd51ca2840daf (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit c9ebd488eadfaec6154db5747f376323f587766d
Author: Edward Fewell <ef...@ti...>
Date: Wed Mar 4 13:07:13 2020 -0600
drivers: xds110: Add support TCK changes in firmware update
Starting with XDS110 firmware version 3.0.0.0, the peak TCK
frequency became 14,000 kHz. So the delay count calculation
in the current driver has been updated to use the new
formula for setting the TCK speed depending on which version
of the firmware is detected. And because of the changes, the
default TCK settings for the XDS110 based Launchpads can be
adjusted to take advantage of the higher TCK performance.
Note that the values used have been determined through
testing in the automated test labs to be the highest TCK
frequency with the XDS110 that are still reliable.
Different boards have a different peak TCK setting that
should be safe.
Change-Id: I4d66e90d8fac8272641ba4db4a3a510e3b444d86
Signed-off-by: Edward Fewell <ef...@ti...>
Reviewed-on: http://openocd.zylin.com/5493
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/xds110.c b/src/jtag/drivers/xds110.c
index 69d989520..085d85f4c 100644
--- a/src/jtag/drivers/xds110.c
+++ b/src/jtag/drivers/xds110.c
@@ -41,6 +41,12 @@
#define OCD_FIRMWARE_UPGRADE \
"XDS110: upgrade to version 2.3.0.11+ for improved support"
+/* Firmware version that introduced improved TCK performance */
+#define FAST_TCK_FIRMWARE_VERSION 0x03000000
+
+/* Firmware version that introduced 10 MHz and 12 MHz TCK support */
+#define FAST_TCK_PLUS_FIRMWARE_VERSION 0x03000003
+
/***************************************************************************
* USB Connection Buffer Definitions *
***************************************************************************/
@@ -91,8 +97,17 @@
/* TCK frequency limits */
#define XDS110_MIN_TCK_SPEED 100 /* kHz */
-#define XDS110_MAX_TCK_SPEED 2500 /* kHz */
-#define XDS110_TCK_PULSE_INCREMENT 66.0
+#define XDS110_MAX_SLOW_TCK_SPEED 2500 /* kHz */
+#define XDS110_MAX_FAST_TCK_SPEED 14000 /* kHz */
+#define XDS110_DEFAULT_TCK_SPEED 2500 /* kHz */
+
+/* Fixed TCK delay values for "Fast" TCK frequencies */
+#define FAST_TCK_DELAY_14000_KHZ 0
+#define FAST_TCK_DELAY_10000_KHZ 0xfffffffd
+#define FAST_TCK_DELAY_12000_KHZ 0xfffffffe
+#define FAST_TCK_DELAY_8500_KHZ 1
+#define FAST_TCK_DELAY_5500_KHZ 2
+/* For TCK frequencies below 5500 kHz, use calculated delay */
/* Scan mode on connect */
#define MODE_JTAG 1
@@ -249,7 +264,7 @@ static struct xds110_info xds110 = {
.is_cmapi_acquired = false,
.is_swd_mode = false,
.is_ap_dirty = false,
- .speed = XDS110_MAX_TCK_SPEED,
+ .speed = XDS110_DEFAULT_TCK_SPEED,
.delay_count = 0,
.serial = {0},
.voltage = 0,
@@ -1846,6 +1861,8 @@ static int xds110_execute_queue(void)
static int xds110_speed(int speed)
{
+ double freq_to_use;
+ uint32_t delay_count;
bool success;
if (speed == 0) {
@@ -1853,61 +1870,110 @@ static int xds110_speed(int speed)
return ERROR_JTAG_NOT_IMPLEMENTED;
}
- if (speed > XDS110_MAX_TCK_SPEED) {
- LOG_INFO("XDS110: reduce speed request: %dkHz to %dkHz maximum",
- speed, XDS110_MAX_TCK_SPEED);
- speed = XDS110_MAX_TCK_SPEED;
- }
-
if (speed < XDS110_MIN_TCK_SPEED) {
- LOG_INFO("XDS110: increase speed request: %dkHz to %dkHz minimum",
+ LOG_INFO("XDS110: increase speed request: %d kHz to %d kHz minimum",
speed, XDS110_MIN_TCK_SPEED);
speed = XDS110_MIN_TCK_SPEED;
}
- /* The default is the maximum frequency the XDS110 can support */
- uint32_t freq_to_use = XDS110_MAX_TCK_SPEED * 1000; /* Hz */
- uint32_t delay_count = 0;
+ /* Older XDS110 firmware had inefficient scan routines and could only */
+ /* achieve a peak TCK frequency of about 2500 kHz */
+ if (xds110.firmware < FAST_TCK_FIRMWARE_VERSION) {
- if (XDS110_MAX_TCK_SPEED != speed) {
- freq_to_use = speed * 1000; /* Hz */
+ /* Check for request for top speed or higher */
+ if (speed >= XDS110_MAX_SLOW_TCK_SPEED) {
- /* Calculate the delay count value */
- double one_giga = 1000000000;
- /* Get the pulse duration for the maximum frequency supported in ns */
- double max_freq_pulse_duration = one_giga /
- (XDS110_MAX_TCK_SPEED * 1000);
+ /* Inform user that speed was adjusted down to max possible */
+ if (speed > XDS110_MAX_SLOW_TCK_SPEED) {
+ LOG_INFO(
+ "XDS110: reduce speed request: %d kHz to %d kHz maximum",
+ speed, XDS110_MAX_SLOW_TCK_SPEED);
+ speed = XDS110_MAX_SLOW_TCK_SPEED;
+ }
+ delay_count = 0;
- /* Convert frequency to pulse duration */
- double freq_to_pulse_width_in_ns = one_giga / freq_to_use;
+ } else {
- /*
- * Start with the pulse duration for the maximum frequency. Keep
- * decrementing the time added by each count value till the requested
- * frequency pulse is less than the calculated value.
- */
- double current_value = max_freq_pulse_duration;
+ const double XDS110_TCK_PULSE_INCREMENT = 66.0;
+ freq_to_use = speed * 1000; /* Hz */
+ delay_count = 0;
+
+ /* Calculate the delay count value */
+ double one_giga = 1000000000;
+ /* Get the pulse duration for the max frequency supported in ns */
+ double max_freq_pulse_duration = one_giga /
+ (XDS110_MAX_SLOW_TCK_SPEED * 1000);
+
+ /* Convert frequency to pulse duration */
+ double freq_to_pulse_width_in_ns = one_giga / freq_to_use;
- while (current_value < freq_to_pulse_width_in_ns) {
- current_value += XDS110_TCK_PULSE_INCREMENT;
- ++delay_count;
+ /*
+ * Start with the pulse duration for the maximum frequency. Keep
+ * decrementing time added by each count value till the requested
+ * frequency pulse is less than the calculated value.
+ */
+ double current_value = max_freq_pulse_duration;
+
+ while (current_value < freq_to_pulse_width_in_ns) {
+ current_value += XDS110_TCK_PULSE_INCREMENT;
+ ++delay_count;
+ }
+
+ /*
+ * Determine which delay count yields the best match.
+ * The one obtained above or one less.
+ */
+ if (delay_count) {
+ double diff_freq_1 = freq_to_use -
+ (one_giga / (max_freq_pulse_duration +
+ (XDS110_TCK_PULSE_INCREMENT * delay_count)));
+ double diff_freq_2 = (one_giga / (max_freq_pulse_duration +
+ (XDS110_TCK_PULSE_INCREMENT * (delay_count - 1)))) -
+ freq_to_use;
+
+ /* One less count value yields a better match */
+ if (diff_freq_1 > diff_freq_2)
+ --delay_count;
+ }
}
- /*
- * Determine which delay count yields the best match.
- * The one obtained above or one less.
- */
- if (delay_count) {
- double diff_freq_1 = freq_to_use -
- (one_giga / (max_freq_pulse_duration +
- (XDS110_TCK_PULSE_INCREMENT * delay_count)));
- double diff_freq_2 = (one_giga / (max_freq_pulse_duration +
- (XDS110_TCK_PULSE_INCREMENT * (delay_count - 1)))) -
- freq_to_use;
-
- /* One less count value yields a better match */
- if (diff_freq_1 > diff_freq_2)
- --delay_count;
+ /* Newer firmware has reworked TCK routines that are much more efficient */
+ /* and can now achieve a peak TCK frequency of 14000 kHz */
+ } else {
+
+ if (speed >= XDS110_MAX_FAST_TCK_SPEED) {
+ if (speed > XDS110_MAX_FAST_TCK_SPEED) {
+ LOG_INFO(
+ "XDS110: reduce speed request: %d kHz to %d kHz maximum",
+ speed, XDS110_MAX_FAST_TCK_SPEED);
+ speed = XDS110_MAX_FAST_TCK_SPEED;
+ }
+ delay_count = 0;
+ } else if (speed >= 12000 && xds110.firmware >=
+ FAST_TCK_PLUS_FIRMWARE_VERSION) {
+ delay_count = FAST_TCK_DELAY_12000_KHZ;
+ } else if (speed >= 10000 && xds110.firmware >=
+ FAST_TCK_PLUS_FIRMWARE_VERSION) {
+ delay_count = FAST_TCK_DELAY_10000_KHZ;
+ } else if (speed >= 8500) {
+ delay_count = FAST_TCK_DELAY_8500_KHZ;
+ } else if (speed >= 5500) {
+ delay_count = FAST_TCK_DELAY_5500_KHZ;
+ } else {
+ /* Calculate the delay count to set the frequency */
+ /* Formula determined by measuring the waveform on Saeleae logic */
+ /* analyzer using known values for delay count */
+ const double m = 17100000.0; /* slope */
+ const double b = -1.02; /* y-intercept */
+
+ freq_to_use = speed * 1000; /* Hz */
+ double period = 1.0/freq_to_use;
+ double delay = m * period + b;
+
+ if (delay < 1.0)
+ delay_count = 1;
+ else
+ delay_count = (uint32_t)delay;
}
}
diff --git a/tcl/board/ti_cc13x0_launchpad.cfg b/tcl/board/ti_cc13x0_launchpad.cfg
index d2d0c68fe..4fbce4120 100644
--- a/tcl/board/ti_cc13x0_launchpad.cfg
+++ b/tcl/board/ti_cc13x0_launchpad.cfg
@@ -3,5 +3,5 @@
#
source [find interface/xds110.cfg]
transport select jtag
-adapter speed 2500
+adapter speed 5500
source [find target/ti_cc13x0.cfg]
diff --git a/tcl/board/ti_cc13x2_launchpad.cfg b/tcl/board/ti_cc13x2_launchpad.cfg
index 706bb728a..dc0c18230 100644
--- a/tcl/board/ti_cc13x2_launchpad.cfg
+++ b/tcl/board/ti_cc13x2_launchpad.cfg
@@ -2,6 +2,6 @@
# TI CC13x2 LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter speed 2500
+adapter speed 5500
transport select jtag
source [find target/ti_cc13x2.cfg]
diff --git a/tcl/board/ti_cc26x0_launchpad.cfg b/tcl/board/ti_cc26x0_launchpad.cfg
index c16fa4c56..372e57ceb 100644
--- a/tcl/board/ti_cc26x0_launchpad.cfg
+++ b/tcl/board/ti_cc26x0_launchpad.cfg
@@ -2,6 +2,6 @@
# TI CC26x0 LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter speed 2500
+adapter speed 5500
transport select jtag
source [find target/ti_cc26x0.cfg]
diff --git a/tcl/board/ti_cc26x2_launchpad.cfg b/tcl/board/ti_cc26x2_launchpad.cfg
index e7941914c..c8057ad3d 100644
--- a/tcl/board/ti_cc26x2_launchpad.cfg
+++ b/tcl/board/ti_cc26x2_launchpad.cfg
@@ -2,6 +2,6 @@
# TI CC26x2 LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter speed 2500
+adapter speed 5500
transport select jtag
source [find target/ti_cc26x2.cfg]
diff --git a/tcl/board/ti_cc3220sf_launchpad.cfg b/tcl/board/ti_cc3220sf_launchpad.cfg
index 30255c793..7c8310af0 100644
--- a/tcl/board/ti_cc3220sf_launchpad.cfg
+++ b/tcl/board/ti_cc3220sf_launchpad.cfg
@@ -2,6 +2,6 @@
# TI CC3220SF-LaunchXL LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter speed 2500
+adapter speed 8500
transport select swd
source [find target/ti_cc3220sf.cfg]
diff --git a/tcl/board/ti_cc32xx_launchpad.cfg b/tcl/board/ti_cc32xx_launchpad.cfg
index 6676e5d6e..1df461a93 100644
--- a/tcl/board/ti_cc32xx_launchpad.cfg
+++ b/tcl/board/ti_cc32xx_launchpad.cfg
@@ -2,6 +2,6 @@
# TI CC32xx-LaunchXL LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter speed 2500
+adapter speed 8500
transport select swd
source [find target/ti_cc32xx.cfg]
diff --git a/tcl/board/ti_msp432_launchpad.cfg b/tcl/board/ti_msp432_launchpad.cfg
index f7c96eed1..6d2b15dd4 100644
--- a/tcl/board/ti_msp432_launchpad.cfg
+++ b/tcl/board/ti_msp432_launchpad.cfg
@@ -2,6 +2,6 @@
# TI MSP432 LaunchPad Evaluation Kit
#
source [find interface/xds110.cfg]
-adapter speed 2500
+adapter speed 10000
transport select swd
source [find target/ti_msp432.cfg]
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/xds110.c | 158 +++++++++++++++++++++++++-----------
tcl/board/ti_cc13x0_launchpad.cfg | 2 +-
tcl/board/ti_cc13x2_launchpad.cfg | 2 +-
tcl/board/ti_cc26x0_launchpad.cfg | 2 +-
tcl/board/ti_cc26x2_launchpad.cfg | 2 +-
tcl/board/ti_cc3220sf_launchpad.cfg | 2 +-
tcl/board/ti_cc32xx_launchpad.cfg | 2 +-
tcl/board/ti_msp432_launchpad.cfg | 2 +-
8 files changed, 119 insertions(+), 53 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-23 22:10:50
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit bff1b6f05a56eed8e150c25d925bd51ca2840daf
Author: Tarek BOCHKATI <tar...@gm...>
Date: Mon Mar 9 13:33:08 2020 +0100
flash/stm32l4x: add support of STM32WB3x devices
STM32WB3x devices' flash are quite similar to STM32WB5x,
except the maximum flash size, which is 512K for WB3x and 1M for WB5x
Change-Id: I3098d7153a7429e0e72c75cec962c05768b0b018
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/5475
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index 42f3394ec..2cc378a90 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -188,6 +188,10 @@ static const struct stm32l4_rev stm32_495_revs[] = {
{ 0x2001, "2.1" },
};
+static const struct stm32l4_rev stm32_496_revs[] = {
+ { 0x1000, "A" },
+};
+
static const struct stm32l4_rev stm32_497_revs[] = {
{ 0x1000, "1.0" },
};
@@ -313,6 +317,16 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.flash_regs_base = 0x58004000,
.fsize_addr = 0x1FFF75E0,
},
+ {
+ .id = 0x496,
+ .revs = stm32_496_revs,
+ .num_revs = ARRAY_SIZE(stm32_496_revs),
+ .device_str = "STM32WB3x",
+ .max_flash_size_kb = 512,
+ .has_dual_bank = false,
+ .flash_regs_base = 0x58004000,
+ .fsize_addr = 0x1FFF75E0,
+ },
{
.id = 0x497,
.revs = stm32_497_revs,
@@ -985,6 +999,7 @@ static int stm32l4_probe(struct flash_bank *bank)
}
break;
case 0x495: /* STM32WB5x */
+ case 0x496: /* STM32WB3x */
/* single bank flash */
page_size_kb = 4;
num_pages = flash_size_kb / page_size_kb;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32l4x.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-23 21:53:14
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via c999fcef3e96fbdb5226b0913bddf29365566ce8 (commit)
from 4b4389a2d69d96e08d2b417e47c24cad6b50a5c5 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit c999fcef3e96fbdb5226b0913bddf29365566ce8
Author: Tarek BOCHKATI <tar...@gm...>
Date: Mon Mar 9 15:10:17 2020 +0100
flash/stm32l4x: add support of STM32WLEx devices
STM32WLEx devices are based on arm Cortex-M4 running at 48MHz,
contains a single bank of maximum 256 Kbytes of flash memory.
there is 3 variants with different Flash/RAM sizes:
STM32WLE5JC : 256K/64K
STM32WLE5JB : 128K/48K
STM32WLE5J8 : 64K/20K
the work-area size is set to 20 kb to fit in STM32WLE5J8
Change-Id: Ie8e186fe4be97cbc25c53ef0ade4b4dbbcee6f66
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/5450
Tested-by: jenkins
Reviewed-by: Andreas Bolsch <hyp...@gm...>
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 97c5a728d..25554f87a 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6892,7 +6892,7 @@ The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@deffn {Flash Driver} stm32l4x
-All members of the STM32L4, STM32L4+, STM32WB and STM32G4
+All members of the STM32L4, STM32L4+, STM32WB, STM32WL and STM32G4
microcontroller families from STMicroelectronics include internal flash
and use ARM Cortex-M4 cores.
Additionally this driver supports STM32G0 family with ARM Cortex-M0+ core.
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index b6f0d714d..42f3394ec 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -75,6 +75,12 @@
* http://www.st.com/resource/en/reference_manual/dm00622834.pdf
*/
+/* STM32WLxxx series for reference.
+ *
+ * RM0461 (STM32WLEx)
+ * http://www.st.com/resource/en/reference_manual/dm00530369.pdf
+ */
+
/*
* STM32G0xxx series for reference.
*
@@ -132,7 +138,7 @@ struct stm32l4_flash_bank {
};
/* human readable list of families this drivers supports */
-static const char *device_families = "STM32L4/L4+/WB/G4/G0";
+static const char *device_families = "STM32L4/L4+/WB/WL/G4/G0";
static const struct stm32l4_rev stm32_415_revs[] = {
{ 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
@@ -182,6 +188,10 @@ static const struct stm32l4_rev stm32_495_revs[] = {
{ 0x2001, "2.1" },
};
+static const struct stm32l4_rev stm32_497_revs[] = {
+ { 0x1000, "1.0" },
+};
+
static const struct stm32l4_part_info stm32l4_parts[] = {
{
.id = 0x415,
@@ -303,6 +313,16 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.flash_regs_base = 0x58004000,
.fsize_addr = 0x1FFF75E0,
},
+ {
+ .id = 0x497,
+ .revs = stm32_497_revs,
+ .num_revs = ARRAY_SIZE(stm32_497_revs),
+ .device_str = "STM32WLEx",
+ .max_flash_size_kb = 256,
+ .has_dual_bank = false,
+ .flash_regs_base = 0x58004000,
+ .fsize_addr = 0x1FFF75E0,
+ },
};
/* flash bank stm32l4x <base> <size> 0 0 <target#> */
@@ -918,6 +938,7 @@ static int stm32l4_probe(struct flash_bank *bank)
case 0x464: /* STM32L41/L42xx */
case 0x466: /* STM32G03/G04xx */
case 0x468: /* STM32G43/G44xx */
+ case 0x497: /* STM32WLEx */
/* single bank flash */
page_size_kb = 2;
num_pages = flash_size_kb / page_size_kb;
diff --git a/src/flash/startup.tcl b/src/flash/startup.tcl
index 9d8e91014..aafb939cd 100644
--- a/src/flash/startup.tcl
+++ b/src/flash/startup.tcl
@@ -113,10 +113,11 @@ proc stm32f7x args { eval stm32f2x $args }
proc stm32l0x args { eval stm32lx $args }
proc stm32l1x args { eval stm32lx $args }
-# stm32[g0|g4|wb] uses the same flash driver as the stm32l4x
+# stm32[g0|g4|wb|wl] uses the same flash driver as the stm32l4x
proc stm32g0x args { eval stm32l4x $args }
proc stm32g4x args { eval stm32l4x $args }
proc stm32wbx args { eval stm32l4x $args }
+proc stm32wlx args { eval stm32l4x $args }
# ease migration to updated flash driver
proc stm32x args {
diff --git a/tcl/target/stm32wlx.cfg b/tcl/target/stm32wlx.cfg
new file mode 100644
index 000000000..98c9a7ee9
--- /dev/null
+++ b/tcl/target/stm32wlx.cfg
@@ -0,0 +1,100 @@
+# script for stm32wlx family
+
+#
+# stm32wl devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32wlx
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# By default use 20kB
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x5000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ if { [using_jtag] } {
+ set _CPUTAPID 0x6ba00477
+ } else {
+ # SWD IDCODE (single drop, arm)
+ set _CPUTAPID 0x6ba02477
+ }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+ swj_newdap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
+# the safe side.
+#
+# Note that there is a pretty wide band where things are
+# more or less stable, see http://openocd.zylin.com/#/c/3366/
+adapter speed 500
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+ # if srst is not fitted use SYSRESETREQ to
+ # perform a soft reset
+ cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+ # CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
+ # Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
+ # 2 WS compliant with VOS=Range1 and 24 MHz.
+ mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTEN | 2(Latency)
+ mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
+ # Boost JTAG frequency
+ adapter speed 4000
+}
+
+$_TARGETNAME configure -event reset-start {
+ # Reset clock is MSI (4 MHz)
+ adapter speed 500
+}
+
+$_TARGETNAME configure -event examine-end {
+ # Enable debug during low power modes (uses more power)
+ # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+ mmw 0xE0042004 0x00000007 0
+
+ # Stop watchdog counters during halt
+ # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
+ mmw 0xE004203C 0x00001800 0
+}
+
+$_TARGETNAME configure -event trace-config {
+ # nothing to do
+}
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 2 +-
src/flash/nor/stm32l4x.c | 23 +++++++++++-
src/flash/startup.tcl | 3 +-
tcl/target/{stm32l4x.cfg => stm32wlx.cfg} | 59 +++++++++++++++----------------
4 files changed, 53 insertions(+), 34 deletions(-)
copy tcl/target/{stm32l4x.cfg => stm32wlx.cfg} (55%)
hooks/post-receive
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Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-22 08:17:59
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 4b4389a2d69d96e08d2b417e47c24cad6b50a5c5 (commit)
via 6ecccc88955ead6283bfa9da123e120a73d4cab8 (commit)
from 1891c2d26e240a76b2a5a1761ff0da7693d89901 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 4b4389a2d69d96e08d2b417e47c24cad6b50a5c5
Author: Tarek BOCHKATI <tar...@gm...>
Date: Sat Mar 7 17:20:24 2020 +0100
stlink: workaround serial bug with old ST-Link DFU
Old ST-LINK DFU returns an incorrect serial in the USB descriptor
example for the following serial "57FF72067265575742132067"
- the correct descriptor serial is:
0x32, 0x03, 0x35, 0x00, 0x37, 0x00, 0x46, 0x00, 0x46, 0x00 ...
this contains the length (0x32 = 50), the type (0x3 = DT_STRING)
and the serial in unicode format.
the serial part is: 0x0035, 0x0037, 0x0046, 0x0046 ... >> 57FF ...
this format could be read correctly by 'libusb_get_string_descriptor_ascii'
so this case is managed by libusb_helper::string_descriptor_equal
- the buggy DFU is not doing any unicode conversion and returns a raw
serial data in the descriptor:
0x1a, 0x03, 0x57, 0x00, 0xFF, 0x00, 0x72, 0x00 ...
>> 57 FF 72 ...
based on the length (0x1a = 26) we could easily decide if we have to fixup the serial
and then we have just to convert the raw data into printable characters using sprintf
example for an old ST-LINK/V2 standalone:
before : 'W?rreWWB g'
after : '57FF72067265575742132067'
=> same as the displayed value in STM32CubeProgrammer
tested using these commands
using the buggy serial
-c "hla_serial \x57\x3f\x72\x06\x72\x65\x57\x57\x42\x13\x20\x67"
using the computed serial
-c "hla_serial 57FF72067265575742132067"
Change-Id: I1213818257663eeb8e76f419087d3127d0524842
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/5396
Reviewed-by: Oleksij Rempel <li...@re...>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c
index d8d8d67e3..6ab979f1c 100644
--- a/src/jtag/drivers/stlink_usb.c
+++ b/src/jtag/drivers/stlink_usb.c
@@ -47,6 +47,8 @@
#define USE_LIBUSB_ASYNCIO
#endif
+#define STLINK_SERIAL_LEN 24
+
#define ENDPOINT_IN 0x80
#define ENDPOINT_OUT 0x00
@@ -2745,6 +2747,85 @@ static int stlink_usb_close(void *handle)
return ERROR_OK;
}
+/* Compute ST-Link serial number from the device descriptor
+ * this function will help to work-around a bug in old ST-Link/V2 DFU
+ * the buggy DFU returns an incorrect serial in the USB descriptor
+ * example for the following serial "57FF72067265575742132067"
+ * - the correct descriptor serial is:
+ * 0x32, 0x03, 0x35, 0x00, 0x37, 0x00, 0x46, 0x00, 0x46, 0x00, 0x37, 0x00, 0x32, 0x00 ...
+ * this contains the length (0x32 = 50), the type (0x3 = DT_STRING) and the serial in unicode format
+ * the serial part is: 0x0035, 0x0037, 0x0046, 0x0046, 0x0037, 0x0032 ... >> 57FF72 ...
+ * this format could be read correctly by 'libusb_get_string_descriptor_ascii'
+ * so this case is managed by libusb_helper::string_descriptor_equal
+ * - the buggy DFU is not doing any unicode conversion and returns a raw serial data in the descriptor
+ * 0x1a, 0x03, 0x57, 0x00, 0xFF, 0x00, 0x72, 0x00 ...
+ * >> 57 FF 72 ...
+ * based on the length (0x1a = 26) we could easily decide if we have to fixup the serial
+ * and then we have just to convert the raw data into printable characters using sprintf
+ */
+char *stlink_usb_get_alternate_serial(libusb_device_handle *device,
+ struct libusb_device_descriptor *dev_desc)
+{
+ int usb_retval;
+ unsigned char desc_serial[(STLINK_SERIAL_LEN + 1) * 2];
+
+ if (dev_desc->iSerialNumber == 0)
+ return NULL;
+
+ /* get the LANGID from String Descriptor Zero */
+ usb_retval = libusb_get_string_descriptor(device, 0, 0, desc_serial,
+ sizeof(desc_serial));
+
+ if (usb_retval < LIBUSB_SUCCESS) {
+ LOG_ERROR("libusb_get_string_descriptor() failed: %s(%d)",
+ libusb_error_name(usb_retval), usb_retval);
+ return NULL;
+ } else if (usb_retval < 4) {
+ /* the size should be least 4 bytes to contain a minimum of 1 supported LANGID */
+ LOG_ERROR("could not get the LANGID");
+ return NULL;
+ }
+
+ uint32_t langid = desc_serial[2] | (desc_serial[3] << 8);
+
+ /* get the serial */
+ usb_retval = libusb_get_string_descriptor(device, dev_desc->iSerialNumber,
+ langid, desc_serial, sizeof(desc_serial));
+
+ unsigned char len = desc_serial[0];
+
+ if (usb_retval < LIBUSB_SUCCESS) {
+ LOG_ERROR("libusb_get_string_descriptor() failed: %s(%d)",
+ libusb_error_name(usb_retval), usb_retval);
+ return NULL;
+ } else if (desc_serial[1] != LIBUSB_DT_STRING || len > usb_retval) {
+ LOG_ERROR("invalid string in ST-LINK USB serial descriptor");
+ return NULL;
+ }
+
+ if (len == ((STLINK_SERIAL_LEN + 1) * 2)) {
+ /* good ST-Link adapter, this case is managed by
+ * libusb::libusb_get_string_descriptor_ascii */
+ return NULL;
+ } else if (len != ((STLINK_SERIAL_LEN / 2 + 1) * 2)) {
+ LOG_ERROR("unexpected serial length (%d) in descriptor", len);
+ return NULL;
+ }
+
+ /* else (len == 26) => buggy ST-Link */
+
+ char *alternate_serial = malloc((STLINK_SERIAL_LEN + 1) * sizeof(char));
+ if (alternate_serial == NULL)
+ return NULL;
+
+ for (unsigned int i = 0; i < STLINK_SERIAL_LEN; i += 2)
+ sprintf(alternate_serial + i, "%02X", desc_serial[i + 2]);
+
+ alternate_serial[STLINK_SERIAL_LEN] = '\0';
+
+ return alternate_serial;
+}
+
/** */
static int stlink_usb_open(struct hl_interface_param_s *param, void **fd)
{
@@ -2779,7 +2860,7 @@ static int stlink_usb_open(struct hl_interface_param_s *param, void **fd)
*/
do {
if (jtag_libusb_open(param->vid, param->pid, param->serial,
- &h->fd, NULL) != ERROR_OK) {
+ &h->fd, stlink_usb_get_alternate_serial) != ERROR_OK) {
LOG_ERROR("open failed");
goto error_open;
}
commit 6ecccc88955ead6283bfa9da123e120a73d4cab8
Author: Tarek BOCHKATI <tar...@gm...>
Date: Fri Mar 6 13:52:23 2020 +0100
jtag/libusb_helper: permit adapters to compute their custom serials
introduce a callback function that could be passed to jtag_libusb_open
to permit adapters to compute their custom/exotic serials.
the callback should return a non NULL value only when the serial could not
be retrieved by the standard 'libusb_get_string_descriptor_ascii'
Change-Id: Ib95d6bdfc4ee655eda538fba8becfa183c3b0059
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/5496
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/src/jtag/aice/aice_usb.c b/src/jtag/aice/aice_usb.c
index a5cccfef4..442754209 100644
--- a/src/jtag/aice/aice_usb.c
+++ b/src/jtag/aice/aice_usb.c
@@ -2111,7 +2111,7 @@ static int aice_usb_open(struct aice_port_param_s *param)
const uint16_t pids[] = { param->pid, 0 };
struct libusb_device_handle *devh;
- if (jtag_libusb_open(vids, pids, NULL, &devh) != ERROR_OK)
+ if (jtag_libusb_open(vids, pids, NULL, &devh, NULL) != ERROR_OK)
return ERROR_FAIL;
/* BE ***VERY CAREFUL*** ABOUT MAKING CHANGES IN THIS
@@ -2135,7 +2135,7 @@ static int aice_usb_open(struct aice_port_param_s *param)
/* reopen jlink after usb_reset
* on win32 this may take a second or two to re-enumerate */
int retval;
- while ((retval = jtag_libusb_open(vids, pids, NULL, &devh)) != ERROR_OK) {
+ while ((retval = jtag_libusb_open(vids, pids, NULL, &devh, NULL)) != ERROR_OK) {
usleep(1000);
timeout--;
if (!timeout)
diff --git a/src/jtag/drivers/ft232r.c b/src/jtag/drivers/ft232r.c
index 4812362a3..c9ed304a8 100644
--- a/src/jtag/drivers/ft232r.c
+++ b/src/jtag/drivers/ft232r.c
@@ -257,7 +257,7 @@ static int ft232r_init(void)
{
uint16_t avids[] = {ft232r_vid, 0};
uint16_t apids[] = {ft232r_pid, 0};
- if (jtag_libusb_open(avids, apids, ft232r_serial_desc, &adapter)) {
+ if (jtag_libusb_open(avids, apids, ft232r_serial_desc, &adapter, NULL)) {
LOG_ERROR("ft232r not found: vid=%04x, pid=%04x, serial=%s\n",
ft232r_vid, ft232r_pid, (ft232r_serial_desc == NULL) ? "[any]" : ft232r_serial_desc);
return ERROR_JTAG_INIT_FAILED;
diff --git a/src/jtag/drivers/kitprog.c b/src/jtag/drivers/kitprog.c
index 0c1e74c42..28ed7ac61 100644
--- a/src/jtag/drivers/kitprog.c
+++ b/src/jtag/drivers/kitprog.c
@@ -280,7 +280,7 @@ static int kitprog_usb_open(void)
const uint16_t pids[] = { PID, 0 };
if (jtag_libusb_open(vids, pids, kitprog_serial,
- &kitprog_handle->usb_handle) != ERROR_OK) {
+ &kitprog_handle->usb_handle, NULL) != ERROR_OK) {
LOG_ERROR("Failed to open or find the device");
return ERROR_FAIL;
}
diff --git a/src/jtag/drivers/libusb_helper.c b/src/jtag/drivers/libusb_helper.c
index 5a8129cb9..fbbfb4114 100644
--- a/src/jtag/drivers/libusb_helper.c
+++ b/src/jtag/drivers/libusb_helper.c
@@ -58,7 +58,7 @@ static int jtag_libusb_error(int err)
}
}
-static bool jtag_libusb_match(struct libusb_device_descriptor *dev_desc,
+static bool jtag_libusb_match_ids(struct libusb_device_descriptor *dev_desc,
const uint16_t vids[], const uint16_t pids[])
{
for (unsigned i = 0; vids[i]; i++) {
@@ -123,9 +123,40 @@ static bool string_descriptor_equal(libusb_device_handle *device, uint8_t str_in
return matched;
}
+static bool jtag_libusb_match_serial(libusb_device_handle *device,
+ struct libusb_device_descriptor *dev_desc, const char *serial,
+ adapter_get_alternate_serial_fn adapter_get_alternate_serial)
+{
+ if (string_descriptor_equal(device, dev_desc->iSerialNumber, serial))
+ return true;
+
+ /* check the alternate serial helper */
+ if (!adapter_get_alternate_serial)
+ return false;
+
+ /* get the alternate serial */
+ char *alternate_serial = adapter_get_alternate_serial(device, dev_desc);
+
+ /* check possible failures */
+ if (alternate_serial == NULL)
+ return false;
+
+ /* then compare and free the alternate serial */
+ bool match = false;
+ if (strcmp(serial, alternate_serial) == 0)
+ match = true;
+ else
+ LOG_DEBUG("Device alternate serial number '%s' doesn't match requested serial '%s'",
+ alternate_serial, serial);
+
+ free(alternate_serial);
+ return match;
+}
+
int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
const char *serial,
- struct libusb_device_handle **out)
+ struct libusb_device_handle **out,
+ adapter_get_alternate_serial_fn adapter_get_alternate_serial)
{
int cnt, idx, errCode;
int retval = ERROR_FAIL;
@@ -143,7 +174,7 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
if (libusb_get_device_descriptor(devs[idx], &dev_desc) != 0)
continue;
- if (!jtag_libusb_match(&dev_desc, vids, pids))
+ if (!jtag_libusb_match_ids(&dev_desc, vids, pids))
continue;
if (jtag_usb_get_location() && !jtag_libusb_location_equal(devs[idx]))
@@ -159,7 +190,7 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
/* Device must be open to use libusb_get_string_descriptor_ascii. */
if (serial != NULL &&
- !string_descriptor_equal(libusb_handle, dev_desc.iSerialNumber, serial)) {
+ !jtag_libusb_match_serial(libusb_handle, &dev_desc, serial, adapter_get_alternate_serial)) {
serial_mismatch = true;
libusb_close(libusb_handle);
continue;
diff --git a/src/jtag/drivers/libusb_helper.h b/src/jtag/drivers/libusb_helper.h
index 46e4954e7..74bb23c52 100644
--- a/src/jtag/drivers/libusb_helper.h
+++ b/src/jtag/drivers/libusb_helper.h
@@ -22,9 +22,15 @@
#include <libusb.h>
+/* this callback should return a non NULL value only when the serial could not
+ * be retrieved by the standard 'libusb_get_string_descriptor_ascii' */
+typedef char * (*adapter_get_alternate_serial_fn)(libusb_device_handle *device,
+ struct libusb_device_descriptor *dev_desc);
+
int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
const char *serial,
- struct libusb_device_handle **out);
+ struct libusb_device_handle **out,
+ adapter_get_alternate_serial_fn adapter_get_alternate_serial);
void jtag_libusb_close(struct libusb_device_handle *dev);
int jtag_libusb_control_transfer(struct libusb_device_handle *dev,
uint8_t requestType, uint8_t request, uint16_t wValue,
diff --git a/src/jtag/drivers/opendous.c b/src/jtag/drivers/opendous.c
index 7298a2a10..6812ef649 100644
--- a/src/jtag/drivers/opendous.c
+++ b/src/jtag/drivers/opendous.c
@@ -715,7 +715,7 @@ struct opendous_jtag *opendous_usb_open(void)
struct opendous_jtag *result;
struct libusb_device_handle *devh;
- if (jtag_libusb_open(opendous_probe->VID, opendous_probe->PID, NULL, &devh) != ERROR_OK)
+ if (jtag_libusb_open(opendous_probe->VID, opendous_probe->PID, NULL, &devh, NULL) != ERROR_OK)
return NULL;
jtag_libusb_set_configuration(devh, 0);
diff --git a/src/jtag/drivers/openjtag.c b/src/jtag/drivers/openjtag.c
index 6131df914..7eab5c130 100644
--- a/src/jtag/drivers/openjtag.c
+++ b/src/jtag/drivers/openjtag.c
@@ -449,7 +449,7 @@ static int openjtag_init_cy7c65215(void)
int ret;
usbh = NULL;
- ret = jtag_libusb_open(cy7c65215_vids, cy7c65215_pids, NULL, &usbh);
+ ret = jtag_libusb_open(cy7c65215_vids, cy7c65215_pids, NULL, &usbh, NULL);
if (ret != ERROR_OK) {
LOG_ERROR("unable to open cy7c65215 device");
goto err;
diff --git a/src/jtag/drivers/osbdm.c b/src/jtag/drivers/osbdm.c
index aea126d0d..dc236660e 100644
--- a/src/jtag/drivers/osbdm.c
+++ b/src/jtag/drivers/osbdm.c
@@ -374,7 +374,7 @@ static int osbdm_flush(struct osbdm *osbdm, struct queue *queue)
static int osbdm_open(struct osbdm *osbdm)
{
(void)memset(osbdm, 0, sizeof(*osbdm));
- if (jtag_libusb_open(osbdm_vid, osbdm_pid, NULL, &osbdm->devh) != ERROR_OK)
+ if (jtag_libusb_open(osbdm_vid, osbdm_pid, NULL, &osbdm->devh, NULL) != ERROR_OK)
return ERROR_FAIL;
if (libusb_claim_interface(osbdm->devh, 0) != ERROR_OK)
diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c
index ca7a4df4e..d8d8d67e3 100644
--- a/src/jtag/drivers/stlink_usb.c
+++ b/src/jtag/drivers/stlink_usb.c
@@ -2778,7 +2778,8 @@ static int stlink_usb_open(struct hl_interface_param_s *param, void **fd)
in order to become operational.
*/
do {
- if (jtag_libusb_open(param->vid, param->pid, param->serial, &h->fd) != ERROR_OK) {
+ if (jtag_libusb_open(param->vid, param->pid, param->serial,
+ &h->fd, NULL) != ERROR_OK) {
LOG_ERROR("open failed");
goto error_open;
}
diff --git a/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c b/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c
index 4f7ee6300..b406c0321 100644
--- a/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c
+++ b/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c
@@ -195,7 +195,7 @@ static int ublast2_libusb_init(struct ublast_lowlevel *low)
bool renumeration = false;
int ret;
- if (jtag_libusb_open(vids, pids, NULL, &temp) == ERROR_OK) {
+ if (jtag_libusb_open(vids, pids, NULL, &temp, NULL) == ERROR_OK) {
LOG_INFO("Altera USB-Blaster II (uninitialized) found");
LOG_INFO("Loading firmware...");
ret = load_usb_blaster_firmware(temp, low);
@@ -209,13 +209,15 @@ static int ublast2_libusb_init(struct ublast_lowlevel *low)
const uint16_t pids_renum[] = { low->ublast_pid, 0 };
if (renumeration == false) {
- if (jtag_libusb_open(vids_renum, pids_renum, NULL, &low->libusb_dev) != ERROR_OK) {
+ if (jtag_libusb_open(vids_renum, pids_renum, NULL,
+ &low->libusb_dev, NULL) != ERROR_OK) {
LOG_ERROR("Altera USB-Blaster II not found");
return ERROR_FAIL;
}
} else {
int retry = 10;
- while (jtag_libusb_open(vids_renum, pids_renum, NULL, &low->libusb_dev) != ERROR_OK && retry--) {
+ while (jtag_libusb_open(vids_renum, pids_renum, NULL,
+ &low->libusb_dev, NULL) != ERROR_OK && retry--) {
usleep(1000000);
LOG_INFO("Waiting for renumerate...");
}
-----------------------------------------------------------------------
Summary of changes:
src/jtag/aice/aice_usb.c | 4 +-
src/jtag/drivers/ft232r.c | 2 +-
src/jtag/drivers/kitprog.c | 2 +-
src/jtag/drivers/libusb_helper.c | 39 ++++++++--
src/jtag/drivers/libusb_helper.h | 8 ++-
src/jtag/drivers/opendous.c | 2 +-
src/jtag/drivers/openjtag.c | 2 +-
src/jtag/drivers/osbdm.c | 2 +-
src/jtag/drivers/stlink_usb.c | 84 +++++++++++++++++++++-
.../drivers/usb_blaster/ublast2_access_libusb.c | 8 ++-
10 files changed, 137 insertions(+), 16 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-20 07:09:27
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 1891c2d26e240a76b2a5a1761ff0da7693d89901 (commit)
from 140fe7f7145cb1159e9f530067e8acc62a3584b3 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 1891c2d26e240a76b2a5a1761ff0da7693d89901
Author: Tarek BOCHKATI <tar...@gm...>
Date: Tue Mar 17 16:31:51 2020 +0100
flash/stm32h7x: use proper data type (bool) for has_dual_bank
+ minor changes in comments' alignment to please our eyes
Change-Id: Ifa35a1032afc4e9aee524f596c0298a9eea49c37
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/5500
Tested-by: jenkins
Reviewed-by: Christopher Head <ch...@za...>
diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c
index 6edbc00fa..1e2b35159 100644
--- a/src/flash/nor/stm32h7x.c
+++ b/src/flash/nor/stm32h7x.c
@@ -114,13 +114,13 @@ struct stm32h7x_part_info {
const struct stm32h7x_rev *revs;
size_t num_revs;
unsigned int page_size_kb;
- unsigned int block_size; /* flash write word size in bytes */
+ unsigned int block_size; /* flash write word size in bytes */
uint16_t max_flash_size_kb;
- uint8_t has_dual_bank;
- uint16_t max_bank_size_kb; /* Used when has_dual_bank is true */
- uint32_t flash_regs_base; /* Flash controller registers location */
- uint32_t fsize_addr; /* Location of FSIZE register */
- uint32_t wps_group_size; /* write protection group sectors' count */
+ bool has_dual_bank;
+ uint16_t max_bank_size_kb; /* Used when has_dual_bank is true */
+ uint32_t flash_regs_base; /* Flash controller registers location */
+ uint32_t fsize_addr; /* Location of FSIZE register */
+ uint32_t wps_group_size; /* write protection group sectors' count */
uint32_t wps_mask;
/* function to compute flash_cr register values */
uint32_t (*compute_flash_cr)(uint32_t cmd, int snb);
@@ -174,7 +174,7 @@ static const struct stm32h7x_part_info stm32h7x_parts[] = {
.block_size = 32,
.max_flash_size_kb = 2048,
.max_bank_size_kb = 1024,
- .has_dual_bank = 1,
+ .has_dual_bank = true,
.flash_regs_base = FLASH_REG_BASE_B0,
.fsize_addr = 0x1FF1E880,
.wps_group_size = 1,
@@ -190,7 +190,7 @@ static const struct stm32h7x_part_info stm32h7x_parts[] = {
.block_size = 16,
.max_flash_size_kb = 2048,
.max_bank_size_kb = 1024,
- .has_dual_bank = 1,
+ .has_dual_bank = true,
.flash_regs_base = FLASH_REG_BASE_B0,
.fsize_addr = 0x08FFF80C,
.wps_group_size = 4,
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32h7x.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-17 16:41:39
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 140fe7f7145cb1159e9f530067e8acc62a3584b3 (commit)
from aff486b6a05e1413520537d0d257e36e433754fd (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 140fe7f7145cb1159e9f530067e8acc62a3584b3
Author: Christopher Head <ch...@za...>
Date: Tue Mar 3 13:25:50 2020 -0800
flash/nor: check fill pattern fits in word size
Change-Id: Idad527a428ceed2b53f3da41fb0c64bf8e62614a
Signed-off-by: Christopher Head <ch...@za...>
Reviewed-on: http://openocd.zylin.com/5492
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
index 3287dd97f..40105b43f 100644
--- a/src/flash/nor/tcl.c
+++ b/src/flash/nor/tcl.c
@@ -512,6 +512,11 @@ COMMAND_HANDLER(handle_flash_fill_command)
return ERROR_COMMAND_SYNTAX_ERROR;
}
+ if ((wordsize < sizeof(pattern)) && (pattern >> (8 * wordsize) != 0)) {
+ command_print(CMD, "Fill pattern 0x%" PRIx64 " does not fit within %" PRIu32 "-byte word", pattern, wordsize);
+ return ERROR_FAIL;
+ }
+
if (count == 0)
return ERROR_OK;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/tcl.c | 5 +++++
1 file changed, 5 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-17 16:41:04
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via aff486b6a05e1413520537d0d257e36e433754fd (commit)
from dca1c6ca1f78a6a89e4274e409ff822d655add6b (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit aff486b6a05e1413520537d0d257e36e433754fd
Author: Marc Schink <de...@za...>
Date: Thu Feb 27 13:48:15 2020 +0100
rtos: Destroy RTOS and fix memory leak
The memory leak can be reproduced by using an arbitrary RTOS
and valgrind:
$ valgrind --leak-check=full --show-leak-kinds=all
[...]
==9656== 224 (80 direct, 144 indirect) bytes in 1 blocks are definitely lost in loss record 3 of 3
==9656== at 0x483CD99: calloc (in /usr/lib/x86_64-linux-gnu/valgrind/vgpreload_memcheck-amd64-linux.so)
==9656== by 0x1C541A: os_alloc (rtos.c:79)
==9656== by 0x1C569E: os_alloc_create (rtos.c:111)
==9656== by 0x1C569E: rtos_create (rtos.c:153)
==9656== by 0x1AE332: target_configure (target.c:4899)
==9656== by 0x1AF228: jim_target_configure (target.c:4952)
==9656== by 0x1C9EF9: command_unknown (command.c:1066)
==9656== by 0x313284: JimInvokeCommand (jim.c:10364)
==9656== by 0x313FB6: Jim_EvalObj (jim.c:10814)
==9656== by 0x3154A3: Jim_EvalFile (jim.c:11207)
==9656== by 0x316015: Jim_SourceCoreCommand (jim.c:15230)
==9656== by 0x313284: JimInvokeCommand (jim.c:10364)
==9656== by 0x313B8B: JimEvalObjList (jim.c:10605)
[...]
Change-Id: I2cd41a154fb8570842601ff4e3e76502f5908f49
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5479
Tested-by: jenkins
Reviewed-by: Moritz Fischer <mo...@go...>
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c
index 002d7b543..549833f41 100644
--- a/src/rtos/rtos.c
+++ b/src/rtos/rtos.c
@@ -159,6 +159,11 @@ int rtos_create(Jim_GetOptInfo *goi, struct target *target)
return JIM_ERR;
}
+void rtos_destroy(struct target *target)
+{
+ os_free(target);
+}
+
int gdb_thread_packet(struct connection *connection, char const *packet, int packet_size)
{
struct target *target = get_target_from_connection(connection);
diff --git a/src/rtos/rtos.h b/src/rtos/rtos.h
index a649e2449..c755eec29 100644
--- a/src/rtos/rtos.h
+++ b/src/rtos/rtos.h
@@ -111,6 +111,7 @@ struct rtos_register_stacking {
#define GDB_THREAD_PACKET_NOT_CONSUMED (-40)
int rtos_create(Jim_GetOptInfo *goi, struct target *target);
+void rtos_destroy(struct target *target);
int rtos_set_reg(struct connection *connection, int reg_num,
uint8_t *reg_value);
int rtos_generic_stack_read(struct target *target,
diff --git a/src/target/target.c b/src/target/target.c
index ceecaee10..b77400c1f 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -2049,6 +2049,8 @@ static void target_destroy(struct target *target)
target->smp = 0;
}
+ rtos_destroy(target);
+
free(target->gdb_port_override);
free(target->type);
free(target->trace_info);
-----------------------------------------------------------------------
Summary of changes:
src/rtos/rtos.c | 5 +++++
src/rtos/rtos.h | 1 +
src/target/target.c | 2 ++
3 files changed, 8 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-16 15:27:02
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via dca1c6ca1f78a6a89e4274e409ff822d655add6b (commit)
from ba131f30a0798d97729f9517c136d32f58f57571 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit dca1c6ca1f78a6a89e4274e409ff822d655add6b
Author: Tarek BOCHKATI <tar...@gm...>
Date: Sun Mar 1 22:38:50 2020 +0100
flash/startup.tcl: add STM32G0 and G4 aliases
STM32G0 and G4 uses the same flash driver as the stm32l4x
Change-Id: Ic1c4be70aaee809536912e0390f07893efb9a082
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/5482
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/flash/startup.tcl b/src/flash/startup.tcl
index 725953486..9d8e91014 100644
--- a/src/flash/startup.tcl
+++ b/src/flash/startup.tcl
@@ -113,7 +113,9 @@ proc stm32f7x args { eval stm32f2x $args }
proc stm32l0x args { eval stm32lx $args }
proc stm32l1x args { eval stm32lx $args }
-# stm32wb uses the same flash driver as the stm32l4x
+# stm32[g0|g4|wb] uses the same flash driver as the stm32l4x
+proc stm32g0x args { eval stm32l4x $args }
+proc stm32g4x args { eval stm32l4x $args }
proc stm32wbx args { eval stm32l4x $args }
# ease migration to updated flash driver
-----------------------------------------------------------------------
Summary of changes:
src/flash/startup.tcl | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
hooks/post-receive
--
Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-16 15:26:25
|
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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit ba131f30a0798d97729f9517c136d32f58f57571
Author: Andreas Bolsch <hyp...@gm...>
Date: Sun Dec 16 17:30:41 2018 +0100
Flash driver for STM32G0xx and STM32G4xx
Flash module of STM32G0/G4 family is quite similar to the one of
STM32L4, so only minor changes are required, in particular
adaption of flash loader to Cortex-M0. Register addresses
passed to flash loader to simplify integration of L5.
Added re-probe after option byte load.
Added flash size override via cfg file.
WRPxxR mask now based on max. number of pages instead of fixed 0xFF,
as G4 devices fill up unused bits with '1'.
Sizes in stm32l4_probe changed to multiples of 1kB.
Tested with Nucleo-G071RB, G030J6, Nucleo-G431RB and Nucleo-G474RE.
Gap handling in G4 Cat. 3 dual bank mode tested with STM32G473RB.
This handling isn't optimal as the bank size includes the
size of the gap. WB not tested.
Change-Id: I24df7c065afeb71c11c7e96de4aa9fdb91845593
Signed-off-by: Andreas Bolsch <hyp...@gm...>
Reviewed-on: http://openocd.zylin.com/4807
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/contrib/loaders/flash/stm32/stm32l4x.S b/contrib/loaders/flash/stm32/stm32l4x.S
index e0ce3cb34..9e5c41eba 100644
--- a/contrib/loaders/flash/stm32/stm32l4x.S
+++ b/contrib/loaders/flash/stm32/stm32l4x.S
@@ -8,6 +8,9 @@
* Copyright (C) 2015 Uwe Bonnes *
* bo...@el... *
* *
+ * Copyright (C) 2018 Andreas Bolsch *
+ * and...@mn... *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
@@ -25,68 +28,79 @@
.text
.syntax unified
- .cpu cortex-m4
+ .cpu cortex-m0
.thumb
/*
* Params :
* r0 = workarea start, status (out)
- * r1 = workarea end
+ * r1 = workarea end + 1
* r2 = target address
* r3 = count (64bit words)
- * r4 = flash base
+ * r4 = flash status register
+ * r5 = flash control register
*
* Clobbered:
- * r5 - rp
* r6/7 - temp (64-bit)
- * r8 - wp, tmp
*/
-#define STM32_FLASH_CR_OFFSET 0x14 /* offset of CR register in FLASH struct */
-#define STM32_FLASH_SR_OFFSET 0x10 /* offset of SR register in FLASH struct */
-
-#define STM32_PROG 0x1 /* PG */
+#include "../../../../src/flash/nor/stm32l4x.h"
.thumb_func
.global _start
+
_start:
+ mov r8, r3 /* copy dword count */
wait_fifo:
- ldr r8, [r0, #0] /* read wp */
- cmp r8, #0 /* abort if wp == 0 */
- beq exit
- ldr r5, [r0, #4] /* read rp */
- subs r6, r8, r5 /* number of bytes available for read in r6*/
- itt mi /* if wrapped around*/
- addmi r6, r1 /* add size of buffer */
- submi r6, r0
- cmp r6, #8 /* wait until 8 bytes are available */
- bcc wait_fifo
+ ldr r6, [r0, #0] /* read wp */
+ cmp r6, #0 /* if wp == 0, */
+ beq exit /* then abort */
+ ldr r3, [r0, #4] /* read rp */
+ subs r6, r6, r3 /* number of bytes available for read in r6 */
+ bpl fifo_stat /* if not wrapped around, skip */
+ adds r6, r6, r1 /* add end of buffer */
+ subs r6, r6, r0 /* sub start of buffer */
+fifo_stat:
+ cmp r6, #8 /* wait until at least one dword available */
+ bcc wait_fifo
- ldr r6, =STM32_PROG
- str r6, [r4, #STM32_FLASH_CR_OFFSET]
- ldrd r6, [r5], #0x08 /* read one word from src, increment ptr */
- strd r6, [r2], #0x08 /* write one word to dst, increment ptr */
+ movs r6, #FLASH_PG /* flash program enable */
+ str r6, [r5] /* write to FLASH_CR, start operation */
+ ldmia r3!, {r6, r7} /* read one dword from src, increment ptr */
+ stmia r2!, {r6, r7} /* write one dword to dst, increment ptr */
dsb
+ ldr r7, =FLASH_BSY /* FLASH_BSY mask */
busy:
- ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
- tst r6, #0x10000 /* BSY (bit16) == 1 => operation in progress */
- bne busy /* wait more... */
- tst r6, #0xfa /* PGSERR | SIZERR | PGAERR | WRPERR | PROGERR | OPERR */
- bne error /* fail... */
+ ldr r6, [r4] /* get FLASH_SR register */
+ tst r6, r7 /* BSY == 1 => operation in progress */
+ bne busy /* if still set, wait more ... */
+ movs r7, #FLASH_ERROR /* all error bits */
+ tst r6, r7 /* check for any error bit */
+ bne error /* fail ... */
+
+ cmp r3, r1 /* rp at end of buffer? */
+ bcc upd_rp /* if no, then skip */
+ subs r3, r3, r1 /* sub end of buffer */
+ adds r3, r3, r0 /* add start of buffer */
+ adds r3, r3, #8 /* skip wp and rp */
+upd_rp:
+ str r3, [r0, #4] /* store rp */
+ mov r7, r8 /* get dword count */
+ subs r7, r7, #1 /* decrement dword count */
+ mov r8, r7 /* save dword count */
+ beq exit /* exit if done */
+ b wait_fifo
+
+ .pool
- cmp r5, r1 /* wrap rp at end of buffer */
- it cs
- addcs r5, r0, #8 /* skip loader args */
- str r5, [r0, #4] /* store rp */
- subs r3, r3, #1 /* decrement dword count */
- cbz r3, exit /* loop if not done */
- b wait_fifo
error:
- movs r1, #0
- str r1, [r0, #4] /* set rp = 0 on error */
+ movs r3, #0
+ str r3, [r0, #4] /* set rp = 0 on error */
exit:
- mov r0, r6 /* return status in r0 */
+ mov r0, r6 /* return status in r0 */
+ movs r6, #0 /* flash program disable */
+ str r6, [r5] /* write to FLASH_CR */
+ movs r6, #FLASH_ERROR /* all error bits */
+ str r6, [r4] /* write to FLASH_CR to clear errors */
bkpt #0x00
- .pool
-
diff --git a/contrib/loaders/flash/stm32/stm32l4x.inc b/contrib/loaders/flash/stm32/stm32l4x.inc
index 4065d14ef..df5c7edd1 100644
--- a/contrib/loaders/flash/stm32/stm32l4x.inc
+++ b/contrib/loaders/flash/stm32/stm32l4x.inc
@@ -1,7 +1,7 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */
-0xd0,0xf8,0x00,0x80,0xb8,0xf1,0x00,0x0f,0x20,0xd0,0x45,0x68,0xb8,0xeb,0x05,0x06,
-0x44,0xbf,0x76,0x18,0x36,0x1a,0x08,0x2e,0xf2,0xd3,0x0d,0x4e,0x66,0x61,0xf5,0xe8,
-0x02,0x67,0xe2,0xe8,0x02,0x67,0xbf,0xf3,0x4f,0x8f,0x26,0x69,0x16,0xf4,0x80,0x3f,
-0xfb,0xd1,0x16,0xf0,0xfa,0x0f,0x07,0xd1,0x8d,0x42,0x28,0xbf,0x00,0xf1,0x08,0x05,
-0x45,0x60,0x01,0x3b,0x13,0xb1,0xdb,0xe7,0x00,0x21,0x41,0x60,0x30,0x46,0x00,0xbe,
-0x01,0x00,0x00,0x00,
+0x98,0x46,0x06,0x68,0x00,0x2e,0x23,0xd0,0x43,0x68,0xf6,0x1a,0x01,0xd5,0x76,0x18,
+0x36,0x1a,0x08,0x2e,0xf5,0xd3,0x01,0x26,0x2e,0x60,0xc0,0xcb,0xc0,0xc2,0xbf,0xf3,
+0x4f,0x8f,0x09,0x4f,0x26,0x68,0x3e,0x42,0xfc,0xd1,0xfa,0x27,0x3e,0x42,0x0d,0xd1,
+0x8b,0x42,0x02,0xd3,0x5b,0x1a,0x1b,0x18,0x08,0x33,0x43,0x60,0x47,0x46,0x01,0x3f,
+0xb8,0x46,0x05,0xd0,0xdd,0xe7,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x23,0x43,0x60,
+0x30,0x46,0x00,0x26,0x2e,0x60,0xfa,0x26,0x26,0x60,0x00,0xbe,
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 711171a34..97c5a728d 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6892,8 +6892,10 @@ The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@deffn {Flash Driver} stm32l4x
-All members of the STM32L4 and STM32WB microcontroller families from STMicroelectronics
-include internal flash and use ARM Cortex-M4 cores.
+All members of the STM32L4, STM32L4+, STM32WB and STM32G4
+microcontroller families from STMicroelectronics include internal flash
+and use ARM Cortex-M4 cores.
+Additionally this driver supports STM32G0 family with ARM Cortex-M0+ core.
The driver automatically recognizes a number of these chips using
the chip identification register, and autoconfigures itself.
@@ -6903,7 +6905,8 @@ flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
Note that some devices have been found that have a flash size register that contains
an invalid value, to workaround this issue you can override the probed value used by
-the flash driver.
+the flash driver. However, specifying a wrong value might lead to a completely
+wrong flash layout, so this feature must be used carefully.
@example
flash bank $_FLASHNAME stm32l4x 0x08000000 0x40000 0 0 $_TARGETNAME
@@ -6960,7 +6963,7 @@ This will effectively write protect all sectors in flash bank 1.
@end deffn
@deffn Command {stm32l4x option_load} num
-Forces a re-load of the option byte registers. Will cause a reset of the device.
+Forces a re-load of the option byte registers. Will cause a system reset of the device.
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@end deffn
diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am
index 64c4a9079..b95b003df 100644
--- a/src/flash/nor/Makefile.am
+++ b/src/flash/nor/Makefile.am
@@ -84,4 +84,5 @@ NORHEADERS = \
%D%/non_cfi.h \
%D%/ocl.h \
%D%/spi.h \
+ %D%/stm32l4x.h \
%D%/msp432.h
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index abbb75b46..b6f0d714d 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -28,6 +28,7 @@
#include <target/algorithm.h>
#include <target/armv7m.h>
#include "bits.h"
+#include "stm32l4x.h"
/* STM32L4xxx series for reference.
*
@@ -65,65 +66,43 @@
*
*/
-/* Erase time can be as high as 25ms, 10x this and assume it's toast... */
+/* STM32WBxxx series for reference.
+ *
+ * RM0434 (STM32WB55)
+ * http://www.st.com/resource/en/reference_manual/dm00318631.pdf
+ *
+ * RM0471 (STM32WB50)
+ * http://www.st.com/resource/en/reference_manual/dm00622834.pdf
+ */
-#define FLASH_ERASE_TIMEOUT 250
+/*
+ * STM32G0xxx series for reference.
+ *
+ * RM0444 (STM32G0x1)
+ * http://www.st.com/resource/en/reference_manual/dm00371828.pdf
+ *
+ * RM0454 (STM32G0x0)
+ * http://www.st.com/resource/en/reference_manual/dm00463896.pdf
+ */
-/* Flash registers offsets */
-#define STM32_FLASH_ACR 0x00
-#define STM32_FLASH_KEYR 0x08
-#define STM32_FLASH_OPTKEYR 0x0c
-#define STM32_FLASH_SR 0x10
-#define STM32_FLASH_CR 0x14
-#define STM32_FLASH_OPTR 0x20
-#define STM32_FLASH_WRP1AR 0x2c
-#define STM32_FLASH_WRP1BR 0x30
-#define STM32_FLASH_WRP2AR 0x4c
-#define STM32_FLASH_WRP2BR 0x50
-
-/* FLASH_CR register bits */
-#define FLASH_PG (1 << 0)
-#define FLASH_PER (1 << 1)
-#define FLASH_MER1 (1 << 2)
-#define FLASH_PAGE_SHIFT 3
-#define FLASH_CR_BKER (1 << 11)
-#define FLASH_MER2 (1 << 15)
-#define FLASH_STRT (1 << 16)
-#define FLASH_OPTSTRT (1 << 17)
-#define FLASH_EOPIE (1 << 24)
-#define FLASH_ERRIE (1 << 25)
-#define FLASH_OBLLAUNCH (1 << 27)
-#define FLASH_OPTLOCK (1 << 30)
-#define FLASH_LOCK (1 << 31)
-
-/* FLASH_SR register bits */
-#define FLASH_BSY (1 << 16)
-/* Fast programming not used => related errors not used*/
-#define FLASH_PGSERR (1 << 7) /* Programming sequence error */
-#define FLASH_SIZERR (1 << 6) /* Size error */
-#define FLASH_PGAERR (1 << 5) /* Programming alignment error */
-#define FLASH_WRPERR (1 << 4) /* Write protection error */
-#define FLASH_PROGERR (1 << 3) /* Programming error */
-#define FLASH_OPERR (1 << 1) /* Operation error */
-#define FLASH_EOP (1 << 0) /* End of operation */
-#define FLASH_ERROR (FLASH_PGSERR | FLASH_SIZERR | FLASH_PGAERR | FLASH_WRPERR | FLASH_PROGERR | FLASH_OPERR)
-
-/* register unlock keys */
-#define KEY1 0x45670123
-#define KEY2 0xCDEF89AB
-
-/* option register unlock key */
-#define OPTKEY1 0x08192A3B
-#define OPTKEY2 0x4C5D6E7F
-
-#define RDP_LEVEL_0 0xAA
-#define RDP_LEVEL_1 0xBB
-#define RDP_LEVEL_2 0xCC
-
-
-/* other registers */
-#define DBGMCU_IDCODE 0xE0042000
+/*
+ * STM32G4xxx series for reference.
+ *
+ * RM0440 (STM32G43x/44x/47x/48x)
+ * http://www.st.com/resource/en/reference_manual/dm00355726.pdf
+ *
+ * Cat. 2 devices have single bank only, page size is 2kByte.
+ *
+ * Cat. 3 devices have single and dual bank operating modes,
+ * Page size is 2kByte (dual mode) or 4kByte (single mode).
+ *
+ * Bank mode is controlled by bit 22 (DBANK) in option bytes register.
+ * Both banks are treated as a single OpenOCD bank.
+ */
+/* Erase time can be as high as 25ms, 10x this and assume it's toast... */
+
+#define FLASH_ERASE_TIMEOUT 250
struct stm32l4_rev {
const uint16_t rev;
@@ -147,9 +126,14 @@ struct stm32l4_flash_bank {
int bank1_sectors;
bool dual_bank_mode;
int hole_sectors;
+ uint32_t user_bank_size;
+ uint32_t wrpxxr_mask;
const struct stm32l4_part_info *part_info;
};
+/* human readable list of families this drivers supports */
+static const char *device_families = "STM32L4/L4+/WB/G4/G0";
+
static const struct stm32l4_rev stm32_415_revs[] = {
{ 0x1000, "1" }, { 0x1001, "2" }, { 0x1003, "3" }, { 0x1007, "4" }
};
@@ -158,16 +142,32 @@ static const struct stm32l4_rev stm32_435_revs[] = {
{ 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
};
+static const struct stm32l4_rev stm32_460_revs[] = {
+ { 0x1000, "A/Z" } /* A and Z, no typo in RM! */, { 0x2000, "B" },
+};
+
static const struct stm32l4_rev stm32_461_revs[] = {
{ 0x1000, "A" }, { 0x2000, "B" },
};
static const struct stm32l4_rev stm32_462_revs[] = {
- { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
+ { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
};
static const struct stm32l4_rev stm32_464_revs[] = {
- { 0x1000, "A" },
+ { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2001, "Y" },
+};
+
+static const struct stm32l4_rev stm32_466_revs[] = {
+ { 0x1000, "A" }, { 0x1001, "Z" }, { 0x2000, "B" },
+};
+
+static const struct stm32l4_rev stm32_468_revs[] = {
+ { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
+};
+
+static const struct stm32l4_rev stm32_469_revs[] = {
+ { 0x1000, "A" }, { 0x2000, "B" }, { 0x2001, "Z" },
};
static const struct stm32l4_rev stm32_470_revs[] = {
@@ -203,6 +203,16 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.flash_regs_base = 0x40022000,
.fsize_addr = 0x1FFF75E0,
},
+ {
+ .id = 0x460,
+ .revs = stm32_460_revs,
+ .num_revs = ARRAY_SIZE(stm32_460_revs),
+ .device_str = "STM32G07/G08xx",
+ .max_flash_size_kb = 128,
+ .has_dual_bank = false,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x1FFF75E0,
+ },
{
.id = 0x461,
.revs = stm32_461_revs,
@@ -233,6 +243,36 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
.flash_regs_base = 0x40022000,
.fsize_addr = 0x1FFF75E0,
},
+ {
+ .id = 0x466,
+ .revs = stm32_466_revs,
+ .num_revs = ARRAY_SIZE(stm32_466_revs),
+ .device_str = "STM32G03/G04xx",
+ .max_flash_size_kb = 64,
+ .has_dual_bank = false,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x1FFF75E0,
+ },
+ {
+ .id = 0x468,
+ .revs = stm32_468_revs,
+ .num_revs = ARRAY_SIZE(stm32_468_revs),
+ .device_str = "STM32G43/G44xx",
+ .max_flash_size_kb = 128,
+ .has_dual_bank = false,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x1FFF75E0,
+ },
+ {
+ .id = 0x469,
+ .revs = stm32_469_revs,
+ .num_revs = ARRAY_SIZE(stm32_469_revs),
+ .device_str = "STM32G47/G48xx",
+ .max_flash_size_kb = 512,
+ .has_dual_bank = true,
+ .flash_regs_base = 0x40022000,
+ .fsize_addr = 0x1FFF75E0,
+ },
{
.id = 0x470,
.revs = stm32_470_revs,
@@ -283,6 +323,7 @@ FLASH_BANK_COMMAND_HANDLER(stm32l4_flash_bank_command)
bank->write_start_alignment = bank->write_end_alignment = 8;
stm32l4_info->probed = false;
+ stm32l4_info->user_bank_size = bank->size;
return ERROR_OK;
}
@@ -409,7 +450,8 @@ static int stm32l4_unlock_option_reg(struct flash_bank *bank)
return ERROR_OK;
}
-static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset, uint32_t value, uint32_t mask)
+static int stm32l4_write_option(struct flash_bank *bank, uint32_t reg_offset,
+ uint32_t value, uint32_t mask)
{
uint32_t optiondata;
int retval, retval2;
@@ -454,17 +496,23 @@ static int stm32l4_protect_check(struct flash_bank *bank)
uint32_t wrp1ar, wrp1br, wrp2ar, wrp2br;
stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1AR, &wrp1ar);
stm32l4_read_flash_reg(bank, STM32_FLASH_WRP1BR, &wrp1br);
- stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2AR, &wrp2ar);
- stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2BR, &wrp2br);
-
- const uint8_t wrp1a_start = wrp1ar & 0xFF;
- const uint8_t wrp1a_end = (wrp1ar >> 16) & 0xFF;
- const uint8_t wrp1b_start = wrp1br & 0xFF;
- const uint8_t wrp1b_end = (wrp1br >> 16) & 0xFF;
- const uint8_t wrp2a_start = wrp2ar & 0xFF;
- const uint8_t wrp2a_end = (wrp2ar >> 16) & 0xFF;
- const uint8_t wrp2b_start = wrp2br & 0xFF;
- const uint8_t wrp2b_end = (wrp2br >> 16) & 0xFF;
+ if (stm32l4_info->part_info->has_dual_bank) {
+ stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2AR, &wrp2ar);
+ stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2BR, &wrp2br);
+ } else {
+ /* prevent unintialized errors */
+ wrp2ar = 0;
+ wrp2br = 0;
+ }
+
+ const uint8_t wrp1a_start = wrp1ar & stm32l4_info->wrpxxr_mask;
+ const uint8_t wrp1a_end = (wrp1ar >> 16) & stm32l4_info->wrpxxr_mask;
+ const uint8_t wrp1b_start = wrp1br & stm32l4_info->wrpxxr_mask;
+ const uint8_t wrp1b_end = (wrp1br >> 16) & stm32l4_info->wrpxxr_mask;
+ const uint8_t wrp2a_start = wrp2ar & stm32l4_info->wrpxxr_mask;
+ const uint8_t wrp2a_end = (wrp2ar >> 16) & stm32l4_info->wrpxxr_mask;
+ const uint8_t wrp2b_start = wrp2br & stm32l4_info->wrpxxr_mask;
+ const uint8_t wrp2b_end = (wrp2br >> 16) & stm32l4_info->wrpxxr_mask;
for (int i = 0; i < bank->num_sectors; i++) {
if (i < stm32l4_info->bank1_sectors) {
@@ -476,6 +524,7 @@ static int stm32l4_protect_check(struct flash_bank *bank)
else
bank->sectors[i].is_protected = 0;
} else {
+ assert(stm32l4_info->part_info->has_dual_bank == true);
uint8_t snb;
snb = i - stm32l4_info->bank1_sectors;
if (((snb >= wrp2a_start) &&
@@ -496,8 +545,7 @@ static int stm32l4_erase(struct flash_bank *bank, int first, int last)
int i;
int retval, retval2;
- assert(first < bank->num_sectors);
- assert(last < bank->num_sectors);
+ assert((0 <= first) && (first <= last) && (last < bank->num_sectors));
if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
@@ -512,7 +560,7 @@ static int stm32l4_erase(struct flash_bank *bank, int first, int last)
Sector Erase
To erase a sector, follow the procedure below:
1. Check that no Flash memory operation is ongoing by
- checking the BSY bit in the FLASH_SR register
+ checking the BSY bit in the FLASH_SR register
2. Set the PER bit and select the page and bank
you wish to erase in the FLASH_CR register
3. Set the STRT bit in the FLASH_CR register
@@ -586,15 +634,15 @@ static int stm32l4_protect(struct flash_bank *bank, int set, int first, int last
/* Count is in double-words */
static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
- uint32_t offset, uint32_t count)
+ uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
- uint32_t buffer_size = 16384;
+ uint32_t buffer_size;
struct working_area *write_algorithm;
struct working_area *source;
uint32_t address = bank->base + offset;
- struct reg_param reg_params[5];
+ struct reg_param reg_params[6];
struct armv7m_algorithm armv7m_info;
int retval = ERROR_OK;
@@ -616,18 +664,19 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
return retval;
}
- /* memory buffer */
- while (target_alloc_working_area_try(target, buffer_size, &source) !=
- ERROR_OK) {
- buffer_size /= 2;
- if (buffer_size <= 256) {
- /* we already allocated the writing code, but failed to get a
- * buffer, free the algorithm */
- target_free_working_area(target, write_algorithm);
-
- LOG_WARNING("large enough working area not available, can't do block memory writes");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
+ /* memory buffer, size *must* be multiple of dword plus one dword for rp and one for wp */
+ buffer_size = target_get_working_area_avail(target) & ~(2 * sizeof(uint32_t) - 1);
+ if (buffer_size < 256) {
+ LOG_WARNING("large enough working area not available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ } else if (buffer_size > 16384) {
+ /* probably won't benefit from more than 16k ... */
+ buffer_size = 16384;
+ }
+
+ if (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
+ LOG_ERROR("allocating working area failed");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
@@ -637,17 +686,19 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count (double word-64bit) */
- init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* flash regs base */
+ init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* flash status register */
+ init_reg_param(®_params[5], "r5", 32, PARAM_OUT); /* flash control register */
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
buf_set_u32(reg_params[2].value, 0, 32, address);
buf_set_u32(reg_params[3].value, 0, 32, count);
- buf_set_u32(reg_params[4].value, 0, 32, stm32l4_info->part_info->flash_regs_base);
+ buf_set_u32(reg_params[4].value, 0, 32, stm32l4_info->part_info->flash_regs_base + STM32_FLASH_SR);
+ buf_set_u32(reg_params[5].value, 0, 32, stm32l4_info->part_info->flash_regs_base + STM32_FLASH_CR);
retval = target_run_flash_async_algorithm(target, buffer, count, 8,
0, NULL,
- 5, reg_params,
+ ARRAY_SIZE(reg_params), reg_params,
source->address, source->size,
write_algorithm->address, 0,
&armv7m_info);
@@ -676,14 +727,15 @@ static int stm32l4_write_block(struct flash_bank *bank, const uint8_t *buffer,
destroy_reg_param(®_params[2]);
destroy_reg_param(®_params[3]);
destroy_reg_param(®_params[4]);
+ destroy_reg_param(®_params[5]);
return retval;
}
static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
- uint32_t offset, uint32_t count)
+ uint32_t offset, uint32_t count)
{
- int retval, retval2;
+ int retval = ERROR_OK, retval2;
if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
@@ -695,6 +747,43 @@ static int stm32l4_write(struct flash_bank *bank, const uint8_t *buffer,
assert(offset % 8 == 0);
assert(count % 8 == 0);
+ /* STM32G4xxx Cat. 3 devices may have gaps between banks, check whether
+ * data to be written does not go into a gap:
+ * suppose buffer is fully contained in bank from sector 0 to sector
+ * num->sectors - 1 and sectors are ordered according to offset
+ */
+ struct flash_sector *head = &bank->sectors[0];
+ struct flash_sector *tail = &bank->sectors[bank->num_sectors - 1];
+
+ while ((head < tail) && (offset >= (head + 1)->offset)) {
+ /* buffer does not intersect head nor gap behind head */
+ head++;
+ }
+
+ while ((head < tail) && (offset + count <= (tail - 1)->offset + (tail - 1)->size)) {
+ /* buffer does not intersect tail nor gap before tail */
+ --tail;
+ }
+
+ LOG_DEBUG("data: 0x%08" PRIx32 " - 0x%08" PRIx32 ", sectors: 0x%08" PRIx32 " - 0x%08" PRIx32,
+ offset, offset + count - 1, head->offset, tail->offset + tail->size - 1);
+
+ /* Now check that there is no gap from head to tail, this should work
+ * even for multiple or non-symmetric gaps
+ */
+ while (head < tail) {
+ if (head->offset + head->size != (head + 1)->offset) {
+ LOG_ERROR("write into gap from " TARGET_ADDR_FMT " to " TARGET_ADDR_FMT,
+ bank->base + head->offset + head->size,
+ bank->base + (head + 1)->offset - 1);
+ retval = ERROR_FLASH_DST_OUT_OF_BANK;
+ }
+ head++;
+ }
+
+ if (retval != ERROR_OK)
+ return retval;
+
retval = stm32l4_unlock_reg(bank);
if (retval != ERROR_OK)
goto err_lock;
@@ -713,9 +802,17 @@ err_lock:
static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
{
- int retval = target_read_u32(bank->target, DBGMCU_IDCODE, id);
- if (retval != ERROR_OK)
- return retval;
+ int retval;
+
+ /* try stm32l4/l4+/wb/g4 id register first, then stm32g0 id register */
+ retval = target_read_u32(bank->target, DBGMCU_IDCODE_L4_G4, id);
+ if ((retval != ERROR_OK) || ((*id & 0xfff) == 0) || ((*id & 0xfff) == 0xfff)) {
+ retval = target_read_u32(bank->target, DBGMCU_IDCODE_G0, id);
+ if ((retval != ERROR_OK) || ((*id & 0xfff) == 0) || ((*id & 0xfff) == 0xfff)) {
+ LOG_ERROR("can't get device id");
+ return (retval == ERROR_OK) ? ERROR_FAIL : retval;
+ }
+ }
return retval;
}
@@ -725,13 +822,13 @@ static int stm32l4_probe(struct flash_bank *bank)
struct target *target = bank->target;
struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
const struct stm32l4_part_info *part_info;
- uint16_t flash_size_in_kb = 0xffff;
+ uint16_t flash_size_kb = 0xffff;
uint32_t device_id;
uint32_t options;
stm32l4_info->probed = false;
- /* read stm32 device id register */
+ /* read stm32 device id registers */
int retval = stm32l4_read_idcode(bank, &stm32l4_info->idcode);
if (retval != ERROR_OK)
return retval;
@@ -744,7 +841,7 @@ static int stm32l4_probe(struct flash_bank *bank)
}
if (!stm32l4_info->part_info) {
- LOG_WARNING("Cannot identify target as an STM32 L4 or WB family device.");
+ LOG_WARNING("Cannot identify target as an %s family device.", device_families);
return ERROR_FAIL;
}
@@ -758,21 +855,28 @@ static int stm32l4_probe(struct flash_bank *bank)
LOG_INFO("device idcode = 0x%08" PRIx32 " (%s)", stm32l4_info->idcode, device_info);
/* get flash size from target. */
- retval = target_read_u16(target, part_info->fsize_addr, &flash_size_in_kb);
+ retval = target_read_u16(target, part_info->fsize_addr, &flash_size_kb);
/* failed reading flash size or flash size invalid (early silicon),
* default to max target family */
- if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0
- || flash_size_in_kb > part_info->max_flash_size_kb) {
+ if (retval != ERROR_OK || flash_size_kb == 0xffff || flash_size_kb == 0
+ || flash_size_kb > part_info->max_flash_size_kb) {
LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
part_info->max_flash_size_kb);
- flash_size_in_kb = part_info->max_flash_size_kb;
+ flash_size_kb = part_info->max_flash_size_kb;
+ }
+
+ /* if the user sets the size manually then ignore the probed value
+ * this allows us to work around devices that have a invalid flash size register value */
+ if (stm32l4_info->user_bank_size) {
+ LOG_WARNING("overriding size register by configured bank size - MAY CAUSE TROUBLE");
+ flash_size_kb = stm32l4_info->user_bank_size / 1024;
}
- LOG_INFO("flash size = %dkbytes", flash_size_in_kb);
+ LOG_INFO("flash size = %dkbytes", flash_size_kb);
/* did we assign a flash size? */
- assert((flash_size_in_kb != 0xffff) && flash_size_in_kb);
+ assert((flash_size_kb != 0xffff) && flash_size_kb);
/* read flash option register */
retval = stm32l4_read_flash_reg(bank, STM32_FLASH_OPTR, &options);
@@ -783,13 +887,13 @@ static int stm32l4_probe(struct flash_bank *bank)
stm32l4_info->hole_sectors = 0;
int num_pages = 0;
- int page_size = 0;
+ int page_size_kb = 0;
stm32l4_info->dual_bank_mode = false;
switch (device_id) {
- case 0x415:
- case 0x461:
+ case 0x415: /* STM32L47/L48xx */
+ case 0x461: /* STM32L49/L4Axx */
/* if flash size is max (1M) the device is always dual bank
* 0x415: has variants with 512K
* 0x461: has variants with 512 and 256
@@ -798,51 +902,71 @@ static int stm32l4_probe(struct flash_bank *bank)
* else -> dual bank without gap
* note: the page size is invariant
*/
- page_size = 2048;
- num_pages = flash_size_in_kb / 2;
+ page_size_kb = 2;
+ num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages;
/* check DUAL_BANK bit[21] if the flash is less than 1M */
- if (flash_size_in_kb == 1024 || (options & BIT(21))) {
+ if (flash_size_kb == 1024 || (options & BIT(21))) {
stm32l4_info->dual_bank_mode = true;
stm32l4_info->bank1_sectors = num_pages / 2;
}
break;
- case 0x435:
- case 0x462:
- case 0x464:
+ case 0x435: /* STM32L43/L44xx */
+ case 0x460: /* STM32G07/G08xx */
+ case 0x462: /* STM32L45/L46xx */
+ case 0x464: /* STM32L41/L42xx */
+ case 0x466: /* STM32G03/G04xx */
+ case 0x468: /* STM32G43/G44xx */
/* single bank flash */
- page_size = 2048;
- num_pages = flash_size_in_kb / 2;
+ page_size_kb = 2;
+ num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages;
break;
- case 0x470:
- case 0x471:
+ case 0x469: /* STM32G47/G48xx */
+ /* STM32G47/8 can be single/dual bank:
+ * if DUAL_BANK = 0 -> single bank
+ * else -> dual bank WITH gap
+ */
+ page_size_kb = 4;
+ num_pages = flash_size_kb / page_size_kb;
+ stm32l4_info->bank1_sectors = num_pages;
+ if (options & BIT(22)) {
+ stm32l4_info->dual_bank_mode = true;
+ page_size_kb = 2;
+ num_pages = flash_size_kb / page_size_kb;
+ stm32l4_info->bank1_sectors = num_pages / 2;
+
+ /* for devices with trimmed flash, there is a gap between both banks */
+ stm32l4_info->hole_sectors =
+ (part_info->max_flash_size_kb - flash_size_kb) / (2 * page_size_kb);
+ }
+ break;
+ case 0x470: /* STM32L4R/L4Sxx */
+ case 0x471: /* STM32L4P5/L4Q5x */
/* STM32L4R/S can be single/dual bank:
* if size = 2M check DBANK bit(22)
* if size = 1M check DB1M bit(21)
* STM32L4P/Q can be single/dual bank
* if size = 1M check DBANK bit(22)
* if size = 512K check DB512K bit(21)
- * in single bank configuration the page size is 8K
- * else (dual bank) the page size is 4K without gap between banks
*/
- page_size = 8192;
- num_pages = flash_size_in_kb / 8;
+ page_size_kb = 8;
+ num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages;
- const bool use_dbank_bit = flash_size_in_kb == part_info->max_flash_size_kb;
+ const bool use_dbank_bit = flash_size_kb == part_info->max_flash_size_kb;
if ((use_dbank_bit && (options & BIT(22))) ||
(!use_dbank_bit && (options & BIT(21)))) {
stm32l4_info->dual_bank_mode = true;
- page_size = 4096;
- num_pages = flash_size_in_kb / 4;
+ page_size_kb = 4;
+ num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages / 2;
}
break;
- case 0x495:
+ case 0x495: /* STM32WB5x */
/* single bank flash */
- page_size = 4096;
- num_pages = flash_size_in_kb / 4;
+ page_size_kb = 4;
+ num_pages = flash_size_kb / page_size_kb;
stm32l4_info->bank1_sectors = num_pages;
break;
default:
@@ -852,21 +976,41 @@ static int stm32l4_probe(struct flash_bank *bank)
LOG_INFO("flash mode : %s-bank", stm32l4_info->dual_bank_mode ? "dual" : "single");
- const int gap_size = stm32l4_info->hole_sectors * page_size;
+ const int gap_size_kb = stm32l4_info->hole_sectors * page_size_kb;
- if (stm32l4_info->dual_bank_mode & gap_size) {
- LOG_INFO("gap detected starting from %0x08" PRIx32 " to %0x08" PRIx32,
- 0x8000000 + stm32l4_info->bank1_sectors * page_size,
- 0x8000000 + stm32l4_info->bank1_sectors * page_size + gap_size);
+ if (gap_size_kb != 0) {
+ LOG_INFO("gap detected from 0x%08" PRIx32 " to 0x%08" PRIx32,
+ STM32_FLASH_BANK_BASE + stm32l4_info->bank1_sectors
+ * page_size_kb * 1024,
+ STM32_FLASH_BANK_BASE + (stm32l4_info->bank1_sectors
+ * page_size_kb + gap_size_kb) * 1024 - 1);
}
+ /* number of significant bits in WRPxxR differs per device,
+ * always right adjusted, on some devices non-implemented
+ * bits read as '0', on others as '1' ...
+ * notably G4 Cat. 2 implement only 6 bits, contradicting the RM
+ */
+
+ /* use *max_flash_size* instead of actual size as the trimmed versions
+ * certainly use the same number of bits
+ * max_flash_size is always power of two, so max_pages too
+ */
+ uint32_t max_pages = stm32l4_info->part_info->max_flash_size_kb / page_size_kb;
+ assert((max_pages & (max_pages - 1)) == 0);
+
+ /* in dual bank mode number of pages is doubled, but extra bit is bank selection */
+ stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);
+ assert((stm32l4_info->wrpxxr_mask & 0xFFFF0000) == 0);
+ LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, stm32l4_info->wrpxxr_mask);
+
if (bank->sectors) {
free(bank->sectors);
bank->sectors = NULL;
}
- bank->size = flash_size_in_kb * 1024 + gap_size;
- bank->base = 0x08000000;
+ bank->size = (flash_size_kb + gap_size_kb) * 1024;
+ bank->base = STM32_FLASH_BANK_BASE;
bank->num_sectors = num_pages;
bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
if (bank->sectors == NULL) {
@@ -875,12 +1019,12 @@ static int stm32l4_probe(struct flash_bank *bank)
}
for (int i = 0; i < bank->num_sectors; i++) {
- bank->sectors[i].offset = i * page_size;
+ bank->sectors[i].offset = i * page_size_kb * 1024;
/* in dual bank configuration, if there is a gap between banks
* we fix up the sector offset to consider this gap */
if (i >= stm32l4_info->bank1_sectors && stm32l4_info->hole_sectors)
- bank->sectors[i].offset += gap_size;
- bank->sectors[i].size = page_size;
+ bank->sectors[i].offset += gap_size_kb * 1024;
+ bank->sectors[i].size = page_size_kb * 1024;
bank->sectors[i].is_erased = -1;
bank->sectors[i].is_protected = 1;
}
@@ -911,18 +1055,20 @@ static int get_stm32l4_info(struct flash_bank *bank, char *buf, int buf_size)
rev_str = part_info->revs[i].str;
if (rev_str != NULL) {
- snprintf(buf, buf_size, "%s - Rev: %s",
- part_info->device_str, rev_str);
+ snprintf(buf, buf_size, "%s - Rev: %s%s",
+ part_info->device_str, rev_str, stm32l4_info->probed ?
+ (stm32l4_info->dual_bank_mode ? " dual-bank" : " single-bank") : "");
return ERROR_OK;
}
}
}
- snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)",
- part_info->device_str, rev_id);
+ snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)%s",
+ part_info->device_str, rev_id, stm32l4_info->probed ?
+ (stm32l4_info->dual_bank_mode ? " dual-bank" : " single-bank") : "");
return ERROR_OK;
} else {
- snprintf(buf, buf_size, "Cannot identify target as an STM32 L4 or WB device");
+ snprintf(buf, buf_size, "Cannot identify target as an %s device", device_families);
return ERROR_FAIL;
}
@@ -1073,10 +1219,19 @@ COMMAND_HANDLER(stm32l4_handle_option_load_command)
if (ERROR_OK != retval)
return retval;
- /* Write the OBLLAUNCH bit in CR -> Cause device "POR" and option bytes reload */
- retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OBLLAUNCH);
+ /* Set OBL_LAUNCH bit in CR -> system reset and option bytes reload,
+ * but the RMs explicitly do *NOT* list this as power-on reset cause, and:
+ * "Note: If the read protection is set while the debugger is still
+ * connected through JTAG/SWD, apply a POR (power-on reset) instead of a system reset."
+ */
+ retval = stm32l4_write_flash_reg(bank, STM32_FLASH_CR, FLASH_OBL_LAUNCH);
+
+ command_print(CMD, "stm32l4x option load completed. Power-on reset might be required");
+
+ /* Need to re-probe after change */
+ struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
+ stm32l4_info->probed = false;
- command_print(CMD, "stm32l4x option load (POR) completed.");
return retval;
}
diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h
new file mode 100644
index 000000000..abd8010fc
--- /dev/null
+++ b/src/flash/nor/stm32l4x.h
@@ -0,0 +1,82 @@
+/***************************************************************************
+ * Copyright (C) 2015 by Uwe Bonnes *
+ * bo...@el... *
+ *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifndef OPENOCD_FLASH_NOR_STM32L4X
+#define OPENOCD_FLASH_NOR_STM32L4X
+
+/* Flash registers offsets */
+#define STM32_FLASH_ACR 0x00
+#define STM32_FLASH_KEYR 0x08
+#define STM32_FLASH_OPTKEYR 0x0c
+#define STM32_FLASH_SR 0x10
+#define STM32_FLASH_CR 0x14
+#define STM32_FLASH_OPTR 0x20
+#define STM32_FLASH_WRP1AR 0x2c
+#define STM32_FLASH_WRP1BR 0x30
+#define STM32_FLASH_WRP2AR 0x4c
+#define STM32_FLASH_WRP2BR 0x50
+
+/* FLASH_CR register bits */
+#define FLASH_PG (1 << 0)
+#define FLASH_PER (1 << 1)
+#define FLASH_MER1 (1 << 2)
+#define FLASH_PAGE_SHIFT 3
+#define FLASH_CR_BKER (1 << 11)
+#define FLASH_MER2 (1 << 15)
+#define FLASH_STRT (1 << 16)
+#define FLASH_OPTSTRT (1 << 17)
+#define FLASH_EOPIE (1 << 24)
+#define FLASH_ERRIE (1 << 25)
+#define FLASH_OBL_LAUNCH (1 << 27)
+#define FLASH_OPTLOCK (1 << 30)
+#define FLASH_LOCK (1 << 31)
+
+/* FLASH_SR register bits */
+#define FLASH_BSY (1 << 16)
+
+/* Fast programming not used => related errors not used*/
+#define FLASH_PGSERR (1 << 7) /* Programming sequence error */
+#define FLASH_SIZERR (1 << 6) /* Size error */
+#define FLASH_PGAERR (1 << 5) /* Programming alignment error */
+#define FLASH_WRPERR (1 << 4) /* Write protection error */
+#define FLASH_PROGERR (1 << 3) /* Programming error */
+#define FLASH_OPERR (1 << 1) /* Operation error */
+#define FLASH_EOP (1 << 0) /* End of operation */
+#define FLASH_ERROR (FLASH_PGSERR | FLASH_SIZERR | FLASH_PGAERR | \
+ FLASH_WRPERR | FLASH_PROGERR | FLASH_OPERR)
+
+/* register unlock keys */
+#define KEY1 0x45670123
+#define KEY2 0xCDEF89AB
+
+/* option register unlock key */
+#define OPTKEY1 0x08192A3B
+#define OPTKEY2 0x4C5D6E7F
+
+#define RDP_LEVEL_0 0xAA
+#define RDP_LEVEL_1 0xBB
+#define RDP_LEVEL_2 0xCC
+
+/* other registers */
+#define DBGMCU_IDCODE_G0 0x40015800
+#define DBGMCU_IDCODE_L4_G4 0xE0042000
+#define DBGMCU_IDCODE_L5 0xE0044000
+
+#define STM32_FLASH_BANK_BASE 0x08000000
+
+#endif
diff --git a/tcl/target/stm32g0x.cfg b/tcl/target/stm32g0x.cfg
new file mode 100644
index 000000000..50836ea82
--- /dev/null
+++ b/tcl/target/stm32g0x.cfg
@@ -0,0 +1,88 @@
+# script for stm32g0x family
+
+#
+# stm32g0 devices support SWD transports only.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32g0x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# Smallest proposed target has 8kB ram, use 4kB by default to avoid surprises
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x1000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # Section 37.5.5 - corresponds to Cortex-M0+
+ set _CPUTAPID 0x0bc11477
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+# reasonable default
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+ # if srst is not fitted use SYSRESETREQ to
+ # perform a soft reset
+ cortex_m reset_config sysresetreq
+}
+
+proc stm32g0x_default_reset_start {} {
+ # Reset clock is HSI16 (16 MHz)
+ adapter speed 2000
+}
+
+proc stm32g0x_default_examine_end {} {
+ # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
+ mmw 0x40015804 0x00000006 0
+
+ # Stop watchdog counters during halt
+ # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
+ mmw 0x40015808 0x00001800 0
+}
+
+proc stm32g0x_default_reset_init {} {
+ # Increase clock to 64 Mhz
+ mmw 0x40022000 0x00000002 0x00000005 ;# FLASH_ACR: Latency = 2
+ mww 0x4002100C 0x30000802 ;# RCC_PLLCFGR = PLLR=/2, PLLN=8, PLLM=/1, PLLSRC=0x2
+ mmw 0x40021000 0x01000000 0x00000000 ;# RCC_CR |= PLLON
+ mmw 0x40021008 0x00000002 0x00000005 ;# RCC_CFGR: SW=PLLRCLK
+
+ # Boost JTAG frequency
+ adapter speed 4000
+}
+
+# Default hooks
+$_TARGETNAME configure -event examine-end { stm32g0x_default_examine_end }
+$_TARGETNAME configure -event reset-start { stm32g0x_default_reset_start }
+$_TARGETNAME configure -event reset-init { stm32g0x_default_reset_init }
diff --git a/tcl/target/stm32g4x.cfg b/tcl/target/stm32g4x.cfg
new file mode 100644
index 000000000..9f144a07e
--- /dev/null
+++ b/tcl/target/stm32g4x.cfg
@@ -0,0 +1,103 @@
+# script for stm32g4x family
+
+#
+# stm32g4 devices support both JTAG and SWD transports.
+#
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32g4x
+}
+
+set _ENDIAN little
+
+# Work-area is a space in RAM used for flash programming
+# Smallest current target has 32kB ram, use 16kB by default to avoid surprises
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x4000
+}
+
+#jtag scan chain
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ if { [using_jtag] } {
+ # See STM Document RM0440
+ # Section 46.6.3 - corresponds to Cortex-M4 r0p1
+ set _CPUTAPID 0x4ba00477
+ } {
+ set _CPUTAPID 0x2ba01477
+ }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+if {[using_jtag]} {
+ jtag newtap $_CHIPNAME bs -irlen 5
+}
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME stm32l4x 0 0 0 0 $_TARGETNAME
+
+if { [info exists QUADSPI] && $QUADSPI } {
+ set a [llength [flash list]]
+ set _QSPINAME $_CHIPNAME.qspi
+ flash bank $_QSPINAME stmqspi 0x90000000 0 0 0 $_TARGETNAME 0xA0001000
+}
+
+# reasonable default
+adapter speed 2000
+
+adapter srst delay 100
+if {[using_jtag]} {
+ jtag_ntrst_delay 100
+}
+
+reset_config srst_nogate
+
+if {![using_hla]} {
+ # if srst is not fitted use SYSRESETREQ to
+ # perform a soft reset
+ cortex_m reset_config sysresetreq
+}
+
+$_TARGETNAME configure -event reset-init {
+ # CPU comes out of reset with HSION | HSIRDY.
+ # Use HSI 16 MHz clock, compliant even with VOS == 2.
+ # 1 WS compliant with VOS == 2 and 16 MHz.
+ mmw 0x40022000 0x00000001 0x0000000E ;# FLASH_ACR: Latency = 1
+ mmw 0x40021000 0x00000100 0x00000000 ;# RCC_CR |= HSION
+ mmw 0x40021008 0x00000001 0x00000002 ;# RCC_CFGR: SW=HSI16
+}
+
+$_TARGETNAME configure -event reset-start {
+ # Reset clock is HSI (16 MHz)
+ adapter speed 2000
+}
+
+$_TARGETNAME configure -event examine-end {
+ # DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
+ mmw 0xE0042004 0x00000007 0
+
+ # Stop watchdog counters during halt
+ # DBGMCU_APB1_FZR1 |= DBG_IWDG_STOP | DBG_WWDG_STOP
+ mmw 0xE0042008 0x00001800 0
+}
+
+$_TARGETNAME configure -event trace-config {
+ # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
+ # change this value accordingly to configure trace pins
+ # assignment
+ mmw 0xE0042004 0x00000020 0
+}
-----------------------------------------------------------------------
Summary of changes:
contrib/loaders/flash/stm32/stm32l4x.S | 94 ++++---
contrib/loaders/flash/stm32/stm32l4x.inc | 12 +-
doc/openocd.texi | 11 +-
src/flash/nor/Makefile.am | 1 +
src/flash/nor/stm32l4x.c | 447 +++++++++++++++++++++----------
src/flash/nor/stm32l4x.h | 82 ++++++
tcl/target/stm32g0x.cfg | 88 ++++++
tcl/target/{stm32l1.cfg => stm32g4x.cfg} | 88 +++---
8 files changed, 581 insertions(+), 242 deletions(-)
create mode 100644 src/flash/nor/stm32l4x.h
create mode 100644 tcl/target/stm32g0x.cfg
copy tcl/target/{stm32l1.cfg => stm32g4x.cfg} (50%)
hooks/post-receive
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Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-14 20:40:42
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via e03de33c412b366f3dd45c447410dcc1df3b4b82 (commit)
from a34c336cbf7dbe3540cbce59a9b10e81c28fa32a (commit)
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not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit e03de33c412b366f3dd45c447410dcc1df3b4b82
Author: Marek Vasut <mar...@gm...>
Date: Sat Feb 8 07:02:28 2020 +0100
tcl/target: Fix naming of RZ/A1 SoC
The RZ/A1 is not part of the R-Car family, but is rather an RZ family.
Fix the naming.
Change-Id: I5f882b2467e87e534e0f1c827554e664a7d55664
Signed-off-by: Marek Vasut <mar...@gm...>
Reviewed-on: http://openocd.zylin.com/5445
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/tcl/target/renesas_r7s72100.cfg b/tcl/target/renesas_r7s72100.cfg
index f9466fc2f..5220b3ccb 100644
--- a/tcl/target/renesas_r7s72100.cfg
+++ b/tcl/target/renesas_r7s72100.cfg
@@ -1,4 +1,4 @@
-# Renesas R-Car RZ/A1H
+# Renesas RZ/A1H
# https://www.renesas.com/eu/en/products/microcontrollers-microprocessors/rz/rza/rza1h.html
if { [info exists DAP_TAPID] } {
-----------------------------------------------------------------------
Summary of changes:
tcl/target/renesas_r7s72100.cfg | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-14 19:17:25
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit a34c336cbf7dbe3540cbce59a9b10e81c28fa32a
Author: Edward Fewell <ef...@ti...>
Date: Fri Mar 6 14:39:14 2020 -0600
drivers: xds110: Fix errors in routine that toggles
TCK during nSRST assert/deassert code.
To support LPRF targets (CC13xx/CC26xx), TCK must be toggled
for 50 ms while nSRST is asserted and right after it is
released. This allows the core to halt in boot ROM before
code is run that might interfere with debug access.
The current routine has two issues. It shouldn't be run at
all if the target is using SWD. And the delay needs to
be a real-time 50 ms, so the number of TCK periods should
be calculated off the set speed.
Change-Id: If993031b84cf2a505ea67a6633602c4b01cd8e1e
Signed-off-by: Edward Fewell <ef...@ti...>
Reviewed-on: http://openocd.zylin.com/5497
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/jtag/drivers/xds110.c b/src/jtag/drivers/xds110.c
index 14bfe9c75..69d989520 100644
--- a/src/jtag/drivers/xds110.c
+++ b/src/jtag/drivers/xds110.c
@@ -1624,7 +1624,11 @@ static int xds110_reset(int trst, int srst)
retval = ERROR_FAIL;
/* Toggle TCK to trigger HIB on CC13x/CC26x devices */
- success = xds_cycle_tck(60000);
+ if (success && !xds110.is_swd_mode) {
+ /* Toggle TCK for about 50 ms */
+ success = xds_cycle_tck(xds110.speed * 50);
+ }
+
if (!success)
retval = ERROR_FAIL;
}
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/xds110.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
hooks/post-receive
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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-12 10:12:17
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via b5d2b1224fed3909aa3314339611ac5ac7ab0f82 (commit)
from 6900c5af4ec3f6df52227169d7d897eb14a44bca (commit)
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- Log -----------------------------------------------------------------
commit b5d2b1224fed3909aa3314339611ac5ac7ab0f82
Author: Antonio Borneo <bor...@gm...>
Date: Tue Jun 25 16:01:38 2019 +0200
target/cortex_a: add hypervisor mode
Hypervisor mode is present only if the optional virtualization
extensions are available. Moreover, virtualization extensions
require that also security extensions are implemented.
Add the required infrastructure for the shadowed registers in
hypervisor mode.
Make monitor shadowed registers visible in hypervisor mode too.
Make hypervisor shadowed registers visible in hypervisor mode
only.
Check during cortex_a examine if virtualization extensions are
present and then conditionally enable the visibility of both
hypervisor and monitor modes shadowed registers.
Change-Id: I81dbb1ee8baf4c9f1a2226b77c10c8a2a7b34871
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5261
Tested-by: jenkins
diff --git a/src/target/arm.h b/src/target/arm.h
index bf0d9327e..b39957495 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -47,12 +47,16 @@
* on for example ARM7TDMI cores.
* - ARM_CORE_TYPE_SEC_EXT indicates core has security extensions, thus
* three more registers are shadowed for "Secure Monitor" mode.
+ * - ARM_CORE_TYPE_VIRT_EXT indicates core has virtualization extensions
+ * and also security extensions. Additional shadowed registers for
+ * "Secure Monitor" and "Hypervisor" modes.
* - ARM_CORE_TYPE_M_PROFILE indicates a microcontroller profile core,
* which only shadows SP.
*/
enum arm_core_type {
ARM_CORE_TYPE_STD = -1,
ARM_CORE_TYPE_SEC_EXT = 1,
+ ARM_CORE_TYPE_VIRT_EXT,
ARM_CORE_TYPE_M_PROFILE,
};
@@ -76,6 +80,7 @@ enum arm_mode {
ARM_MODE_SVC = 19,
ARM_MODE_MON = 22,
ARM_MODE_ABT = 23,
+ ARM_MODE_HYP = 26,
ARM_MODE_UND = 27,
ARM_MODE_1176_MON = 28,
ARM_MODE_SYS = 31,
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index c27e9537d..a0983cd54 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -48,6 +48,7 @@ enum {
ARMV4_5_SPSR_ABT = 35,
ARMV4_5_SPSR_UND = 36,
ARM_SPSR_MON = 41,
+ ARM_SPSR_HYP = 43,
};
static const uint8_t arm_usr_indices[17] = {
@@ -78,6 +79,10 @@ static const uint8_t arm_mon_indices[3] = {
39, 40, ARM_SPSR_MON,
};
+static const uint8_t arm_hyp_indices[2] = {
+ 42, ARM_SPSR_HYP,
+};
+
static const struct {
const char *name;
unsigned short psr;
@@ -163,6 +168,14 @@ static const struct {
.name = "Handler",
.psr = ARM_MODE_HANDLER,
},
+
+ /* armv7-a with virtualization extension */
+ {
+ .name = "Hypervisor",
+ .psr = ARM_MODE_HYP,
+ .n_indices = ARRAY_SIZE(arm_hyp_indices),
+ .indices = arm_hyp_indices,
+ },
};
/** Map PSR mode bits to the name of an ARM processor operating mode. */
@@ -209,6 +222,8 @@ int arm_mode_to_number(enum arm_mode mode)
case ARM_MODE_MON:
case ARM_MODE_1176_MON:
return 7;
+ case ARM_MODE_HYP:
+ return 8;
default:
LOG_ERROR("invalid mode value encountered %d", mode);
return -1;
@@ -235,6 +250,8 @@ enum arm_mode armv4_5_number_to_mode(int number)
return ARM_MODE_SYS;
case 7:
return ARM_MODE_MON;
+ case 8:
+ return ARM_MODE_HYP;
default:
LOG_ERROR("mode index out of bounds %d", number);
return ARM_MODE_ANY;
@@ -342,6 +359,9 @@ static const struct {
[40] = { .name = "lr_mon", .cookie = 14, .mode = ARM_MODE_MON, .gdb_index = 49, },
[41] = { .name = "spsr_mon", .cookie = 16, .mode = ARM_MODE_MON, .gdb_index = 50, },
+ /* These exist only when the Virtualization Extensions is present */
+ [42] = { .name = "sp_hyp", .cookie = 13, .mode = ARM_MODE_HYP, .gdb_index = 51, },
+ [43] = { .name = "spsr_hyp", .cookie = 16, .mode = ARM_MODE_HYP, .gdb_index = 52, },
};
static const struct {
@@ -391,7 +411,7 @@ static const struct {
/* map core mode (USR, FIQ, ...) and register number to
* indices into the register cache
*/
-const int armv4_5_core_reg_map[8][17] = {
+const int armv4_5_core_reg_map[9][17] = {
{ /* USR */
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
},
@@ -415,6 +435,9 @@ const int armv4_5_core_reg_map[8][17] = {
},
{ /* MON */
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 39, 40, 15, 41,
+ },
+ { /* HYP */
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 42, 14, 15, 43,
}
};
@@ -658,7 +681,11 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
for (i = 0; i < num_core_regs; i++) {
/* Skip registers this core doesn't expose */
if (arm_core_regs[i].mode == ARM_MODE_MON
- && arm->core_type != ARM_CORE_TYPE_SEC_EXT)
+ && arm->core_type != ARM_CORE_TYPE_SEC_EXT
+ && arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
+ continue;
+ if (arm_core_regs[i].mode == ARM_MODE_HYP
+ && arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
continue;
/* REVISIT handle Cortex-M, which only shadows R13/SP */
@@ -816,8 +843,13 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
name = "System and User";
sep = "";
break;
+ case ARM_MODE_HYP:
+ if (arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
+ continue;
+ /* FALLTHROUGH */
case ARM_MODE_MON:
- if (arm->core_type != ARM_CORE_TYPE_SEC_EXT)
+ if (arm->core_type != ARM_CORE_TYPE_SEC_EXT
+ && arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
continue;
/* FALLTHROUGH */
default:
@@ -1194,7 +1226,16 @@ int arm_get_gdb_reg_list(struct target *target,
break;
case REG_CLASS_ALL:
- *reg_list_size = (arm->core_type != ARM_CORE_TYPE_SEC_EXT ? 48 : 51);
+ switch (arm->core_type) {
+ case ARM_CORE_TYPE_SEC_EXT:
+ *reg_list_size = 51;
+ break;
+ case ARM_CORE_TYPE_VIRT_EXT:
+ *reg_list_size = 53;
+ break;
+ default:
+ *reg_list_size = 48;
+ }
unsigned int list_size_core = *reg_list_size;
if (arm->arm_vfp_version == ARM_VFP_V3)
*reg_list_size += 33;
@@ -1206,9 +1247,15 @@ int arm_get_gdb_reg_list(struct target *target,
for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
int reg_index = arm->core_cache->reg_list[i].number;
- if (!(arm_core_regs[i].mode == ARM_MODE_MON
- && arm->core_type != ARM_CORE_TYPE_SEC_EXT))
- (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
+
+ if (arm_core_regs[i].mode == ARM_MODE_MON
+ && arm->core_type != ARM_CORE_TYPE_SEC_EXT
+ && arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
+ continue;
+ if (arm_core_regs[i].mode == ARM_MODE_HYP
+ && arm->core_type != ARM_CORE_TYPE_VIRT_EXT)
+ continue;
+ (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
}
/* When we supply the target description, there is no need for fake FPA */
diff --git a/src/target/armv4_5.h b/src/target/armv4_5.h
index 3ce4ed0e5..bef1cfe32 100644
--- a/src/target/armv4_5.h
+++ b/src/target/armv4_5.h
@@ -38,7 +38,7 @@
int arm_mode_to_number(enum arm_mode mode);
enum arm_mode armv4_5_number_to_mode(int number);
-extern const int armv4_5_core_reg_map[8][17];
+extern const int armv4_5_core_reg_map[9][17];
#define ARMV4_5_CORE_REG_MODE(cache, mode, num) \
(cache->reg_list[armv4_5_core_reg_map[arm_mode_to_number(mode)][num]])
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 22cbc3d06..729a173eb 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2797,6 +2797,15 @@ static int cortex_a_examine_first(struct target *target)
target->coreid);
armv7a->arm.core_type = ARM_CORE_TYPE_SEC_EXT;
}
+ if (dbg_idpfr1 & 0x0000f000) {
+ LOG_DEBUG("target->coreid %" PRId32 " has virtualization extensions",
+ target->coreid);
+ /*
+ * overwrite and simplify the checks.
+ * virtualization extensions require implementation of security extension
+ */
+ armv7a->arm.core_type = ARM_CORE_TYPE_VIRT_EXT;
+ }
/* Avoid recreating the registers cache */
if (!target_was_examined(target)) {
-----------------------------------------------------------------------
Summary of changes:
src/target/arm.h | 5 +++++
src/target/armv4_5.c | 61 +++++++++++++++++++++++++++++++++++++++++++++------
src/target/armv4_5.h | 2 +-
src/target/cortex_a.c | 9 ++++++++
4 files changed, 69 insertions(+), 8 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-12 10:11:16
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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commit 6900c5af4ec3f6df52227169d7d897eb14a44bca
Author: Antonio Borneo <bor...@gm...>
Date: Mon Jun 24 18:28:31 2019 +0200
armv7a: access monitor registers only with security extensions
Accordingly to ARM DDI 0406C at B1.5, the security extensions for
armv7a are optional extensions and can be detected by reading
ID_PFR1.
The monitor mode is part of the security extensions and the shadow
registers "sp_mon", "lr_mon" and "spsr_mon" are only present with
the security extensions.
Read the register ID_PFR1 during cortex_a examine, determine if
security extension is present and then conditionally enable the
visibility of the monitor mode shadow registers.
Change-Id: Ib4834698659046566f6dc5cd35b44de122dc02e5
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5259
Tested-by: jenkins
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 0ef04c162..3d88c8679 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -178,6 +178,9 @@ static inline bool is_armv7a(struct armv7a_common *armv7a)
/* See ARMv7a arch spec section C10.8 */
#define CPUDBG_AUTHSTATUS 0xFB8
+/* See ARMv7a arch spec DDI 0406C C11.10 */
+#define CPUDBG_ID_PFR1 0xD24
+
/* Masks for Vector Catch register */
#define DBG_VCR_FIQ_MASK ((1 << 31) | (1 << 7))
#define DBG_VCR_IRQ_MASK ((1 << 30) | (1 << 6))
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 4f351f04a..22cbc3d06 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2678,7 +2678,7 @@ static int cortex_a_examine_first(struct target *target)
int i;
int retval = ERROR_OK;
- uint32_t didr, cpuid, dbg_osreg;
+ uint32_t didr, cpuid, dbg_osreg, dbg_idpfr1;
/* Search for the APB-AP - it is needed for access to debug registers */
retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv7a->debug_ap);
@@ -2787,7 +2787,16 @@ static int cortex_a_examine_first(struct target *target)
}
}
- armv7a->arm.core_type = ARM_CORE_TYPE_SEC_EXT;
+ retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
+ armv7a->debug_base + CPUDBG_ID_PFR1, &dbg_idpfr1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (dbg_idpfr1 & 0x000000f0) {
+ LOG_DEBUG("target->coreid %" PRId32 " has security extensions",
+ target->coreid);
+ armv7a->arm.core_type = ARM_CORE_TYPE_SEC_EXT;
+ }
/* Avoid recreating the registers cache */
if (!target_was_examined(target)) {
-----------------------------------------------------------------------
Summary of changes:
src/target/armv7a.h | 3 +++
src/target/cortex_a.c | 13 +++++++++++--
2 files changed, 14 insertions(+), 2 deletions(-)
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commit 9626402c5a65423d4e4e9091f710b542522ca125
Author: Antonio Borneo <bor...@gm...>
Date: Mon Jun 24 18:45:11 2019 +0200
target/armv4_5: remove unused macro
The macro ARMV4_5_CORE_REG_MODENUM() is unused.
Remove it!
Change-Id: I183df57bd86c9428710ea3583e43fba88fd26e0a
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5260
Tested-by: jenkins
Reviewed-by: Muhammad Omair Javaid <oma...@li...>
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 266a45869..c27e9537d 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -768,9 +768,6 @@ int arm_arch_state(struct target *target)
return ERROR_OK;
}
-#define ARMV4_5_CORE_REG_MODENUM(cache, mode, num) \
- (cache->reg_list[armv4_5_core_reg_map[mode][num]])
-
COMMAND_HANDLER(handle_armv4_5_reg_command)
{
struct target *target = get_current_target(CMD_CTX);
-----------------------------------------------------------------------
Summary of changes:
src/target/armv4_5.c | 3 ---
1 file changed, 3 deletions(-)
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commit fba438fde7355bcbe5fb4dc0ce712665d3d8a6da
Author: Antonio Borneo <bor...@gm...>
Date: Mon Jun 24 17:15:33 2019 +0200
arm: Use different enum for core_type and core_mode
The fields core_type and core_mode use the same enum arm_mode
but encode different information, making the code less immediate
to read.
Use a different enum arm_core_type for the field core_type.
The code behavior is not changed.
Change-Id: I60f2095ea6801dfe22f6da81ec295ca71ef90466
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5258
Tested-by: jenkins
diff --git a/src/target/arm.h b/src/target/arm.h
index ea83d3867..bf0d9327e 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -40,6 +40,22 @@
* support has not yet been integrated, affecting Cortex-M parts.
*/
+/**
+ * Indicates what registers are in the ARM state core register set.
+ *
+ * - ARM_CORE_TYPE_STD indicates the standard set of 37 registers, seen
+ * on for example ARM7TDMI cores.
+ * - ARM_CORE_TYPE_SEC_EXT indicates core has security extensions, thus
+ * three more registers are shadowed for "Secure Monitor" mode.
+ * - ARM_CORE_TYPE_M_PROFILE indicates a microcontroller profile core,
+ * which only shadows SP.
+ */
+enum arm_core_type {
+ ARM_CORE_TYPE_STD = -1,
+ ARM_CORE_TYPE_SEC_EXT = 1,
+ ARM_CORE_TYPE_M_PROFILE,
+};
+
/**
* Represent state of an ARM core.
*
@@ -161,15 +177,8 @@ struct arm {
/** Support for arm_reg_current() */
const int *map;
- /**
- * Indicates what registers are in the ARM state core register set.
- * ARM_MODE_ANY indicates the standard set of 37 registers,
- * seen on for example ARM7TDMI cores. ARM_MODE_MON indicates three
- * more registers are shadowed, for "Secure Monitor" mode.
- * ARM_MODE_THREAD indicates a microcontroller profile core,
- * which only shadows SP.
- */
- enum arm_mode core_type;
+ /** Indicates what registers are in the ARM state core register set. */
+ enum arm_core_type core_type;
/** Record the current core mode: SVC, USR, or some other mode. */
enum arm_mode core_mode;
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 159c30a85..51f2a337a 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1109,7 +1109,7 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp)
if (!arm11)
return ERROR_FAIL;
- arm11->arm.core_type = ARM_MODE_ANY;
+ arm11->arm.core_type = ARM_CORE_TYPE_STD;
arm_init_arch_info(target, &arm11->arm);
arm11->jtag_info.tap = target->tap;
@@ -1180,7 +1180,7 @@ static int arm11_examine(struct target *target)
type = "ARM1156";
break;
case 0x7B76:
- arm11->arm.core_type = ARM_MODE_MON;
+ arm11->arm.core_type = ARM_CORE_TYPE_SEC_EXT;
/* NOTE: could default arm11->hardware_step to true */
type = "ARM1176";
break;
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index b2962d1c4..6a7bf9da5 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2848,7 +2848,7 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
arm7_9->dcc_downloads = false;
arm->arch_info = arm7_9;
- arm->core_type = ARM_MODE_ANY;
+ arm->core_type = ARM_CORE_TYPE_STD;
arm->read_core_reg = arm7_9_read_core_reg;
arm->write_core_reg = arm7_9_write_core_reg;
arm->full_context = arm7_9_full_context;
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 6d0385715..266a45869 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -658,7 +658,7 @@ struct reg_cache *arm_build_reg_cache(struct target *target, struct arm *arm)
for (i = 0; i < num_core_regs; i++) {
/* Skip registers this core doesn't expose */
if (arm_core_regs[i].mode == ARM_MODE_MON
- && arm->core_type != ARM_MODE_MON)
+ && arm->core_type != ARM_CORE_TYPE_SEC_EXT)
continue;
/* REVISIT handle Cortex-M, which only shadows R13/SP */
@@ -787,7 +787,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
return ERROR_FAIL;
}
- if (arm->core_type != ARM_MODE_ANY) {
+ if (arm->core_type != ARM_CORE_TYPE_STD) {
command_print(CMD,
"Microcontroller Profile not supported - use standard reg cmd");
return ERROR_OK;
@@ -820,7 +820,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
sep = "";
break;
case ARM_MODE_MON:
- if (arm->core_type != ARM_MODE_MON)
+ if (arm->core_type != ARM_CORE_TYPE_SEC_EXT)
continue;
/* FALLTHROUGH */
default:
@@ -872,7 +872,7 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
return ERROR_FAIL;
}
- if (arm->core_type == ARM_MODE_THREAD) {
+ if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) {
/* armv7m not supported */
command_print(CMD, "Unsupported Command");
return ERROR_OK;
@@ -910,7 +910,7 @@ COMMAND_HANDLER(handle_arm_disassemble_command)
return ERROR_FAIL;
}
- if (arm->core_type == ARM_MODE_THREAD) {
+ if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) {
/* armv7m is always thumb mode */
thumb = 1;
}
@@ -1197,7 +1197,7 @@ int arm_get_gdb_reg_list(struct target *target,
break;
case REG_CLASS_ALL:
- *reg_list_size = (arm->core_type != ARM_MODE_MON ? 48 : 51);
+ *reg_list_size = (arm->core_type != ARM_CORE_TYPE_SEC_EXT ? 48 : 51);
unsigned int list_size_core = *reg_list_size;
if (arm->arm_vfp_version == ARM_VFP_V3)
*reg_list_size += 33;
@@ -1210,7 +1210,7 @@ int arm_get_gdb_reg_list(struct target *target,
for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
int reg_index = arm->core_cache->reg_list[i].number;
if (!(arm_core_regs[i].mode == ARM_MODE_MON
- && arm->core_type != ARM_MODE_MON))
+ && arm->core_type != ARM_CORE_TYPE_SEC_EXT))
(*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
}
@@ -1673,8 +1673,8 @@ int arm_init_arch_info(struct target *target, struct arm *arm)
arm->common_magic = ARM_COMMON_MAGIC;
/* core_type may be overridden by subtype logic */
- if (arm->core_type != ARM_MODE_THREAD) {
- arm->core_type = ARM_MODE_ANY;
+ if (arm->core_type != ARM_CORE_TYPE_M_PROFILE) {
+ arm->core_type = ARM_CORE_TYPE_STD;
arm_set_cpsr(arm, ARM_MODE_USR);
}
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 4b37774a5..82d6e6307 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -695,7 +695,7 @@ int armv7m_init_arch_info(struct target *target, struct armv7m_common *armv7m)
/* Enable stimulus port #0 by default */
armv7m->trace_config.itm_ter[0] = 1;
- arm->core_type = ARM_MODE_THREAD;
+ arm->core_type = ARM_CORE_TYPE_M_PROFILE;
arm->arch_info = armv7m;
arm->setup_semihosting = armv7m_setup_semihosting;
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index a79b0b906..4f351f04a 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2787,7 +2787,7 @@ static int cortex_a_examine_first(struct target *target)
}
}
- armv7a->arm.core_type = ARM_MODE_MON;
+ armv7a->arm.core_type = ARM_CORE_TYPE_SEC_EXT;
/* Avoid recreating the registers cache */
if (!target_was_examined(target)) {
diff --git a/src/target/xscale.c b/src/target/xscale.c
index e57996585..f879a9cc9 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -2981,7 +2981,7 @@ static int xscale_init_arch_info(struct target *target,
/* prepare ARMv4/5 specific information */
arm->arch_info = xscale;
- arm->core_type = ARM_MODE_ANY;
+ arm->core_type = ARM_CORE_TYPE_STD;
arm->read_core_reg = xscale_read_core_reg;
arm->write_core_reg = xscale_write_core_reg;
arm->full_context = xscale_full_context;
commit f447c31b30f805725b7a09d51d786c88de4b7a4f
Author: Antonio Borneo <bor...@gm...>
Date: Mon Jun 24 12:17:17 2019 +0200
arm: fix reg num for Monitor mode
Commit 2efb1f14f611 ("Add GDB remote target description support
for ARM4") inserts two additional registers "sp" and "lr" in the
table arm_core_regs[], thus shifting by two the position of the
last three registers already present
"sp_mon" moved from index 37 to 39
"lr_mon" moved from index 38 to 40
"spsr_mon" moved from index 39 to 41
Part of the code is updated (e.g. enum defining ARM_SPSR_MON and
array arm_mon_indices[]), but it's missing the update of mapping
in armv4_5_core_reg_map[].
Fix armv4_5_core_reg_map[].
Change-Id: I0bdf766183392eb738206b876cd9559aacc29fa0
Signed-off-by: Antonio Borneo <bor...@gm...>
Fixes: 2efb1f14f611 ("Add GDB remote target description support for ARM4")
Reviewed-on: http://openocd.zylin.com/5257
Tested-by: jenkins
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 6c487626c..6d0385715 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -414,7 +414,7 @@ const int armv4_5_core_reg_map[8][17] = {
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 31
},
{ /* MON */
- 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 37, 38, 15, 39,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 39, 40, 15, 41,
}
};
-----------------------------------------------------------------------
Summary of changes:
src/target/arm.h | 27 ++++++++++++++++++---------
src/target/arm11.c | 4 ++--
src/target/arm7_9_common.c | 2 +-
src/target/armv4_5.c | 20 ++++++++++----------
src/target/armv7m.c | 2 +-
src/target/cortex_a.c | 2 +-
src/target/xscale.c | 2 +-
7 files changed, 34 insertions(+), 25 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-12 10:06:00
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from 2e1dfebc8e62376e0ae3e55ac776149bed462330 (commit)
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- Log -----------------------------------------------------------------
commit fbbfbb2516a58b2ab866d713ef18c0a210bb647b
Author: Antonio Borneo <bor...@gm...>
Date: Mon Feb 3 16:48:40 2020 +0100
ftdi: flush mpsse queue after a level change on reset pins
The function ftdi_set_signal() does not propagate the pin change
until next call to mpsse_flush(). Current code does not toggles
immediately the reset pins if polling is turned off.
Call mpsse_flush() at the end of ftdi_reset().
While there, remove the duplicated LOG message.
Change-Id: I79eacfe4fc32b5cdf2dc1b78f3660d96988466bc
Fixes: 8850eb8f2c51 ("swd: get rid of jtag queue to assert/deassert srst")
Reported-by: Leonard Crestez <leo...@nx...>
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5431
Tested-by: jenkins
Reviewed-by: Leonard Crestez <leo...@nx...>
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/jtag/drivers/ftdi.c b/src/jtag/drivers/ftdi.c
index a9cdbbe1e..121cb469f 100644
--- a/src/jtag/drivers/ftdi.c
+++ b/src/jtag/drivers/ftdi.c
@@ -550,8 +550,7 @@ static int ftdi_reset(int trst, int srst)
ftdi_set_signal(sig_nsrst, 'z');
}
- LOG_DEBUG_IO("trst: %i, srst: %i", trst, srst);
- return ERROR_OK;
+ return mpsse_flush(mpsse_ctx);
}
static void ftdi_execute_sleep(struct jtag_command *cmd)
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/ftdi.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-12 10:05:20
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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via 939febeccafc885d3869ce94c688aaf724f2eccd (commit)
from 44967a9e07ff01a01a96757f302c053553cff35e (commit)
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- Log -----------------------------------------------------------------
commit 2e1dfebc8e62376e0ae3e55ac776149bed462330
Author: Antonio Borneo <bor...@gm...>
Date: Sat Oct 19 19:46:53 2019 +0200
jimtcl: update to tag 0.79
OpenOCD is stuck at jimtcl tag 0.77 that is 3 years old.
The latest tag 0.79 (2019-11-20) is already used by debian build,
which packs jim library separately, as shown in [1]. Today only
the build for architecture powerpcspe is still not updated to
latest package version.
I have been using jim 0.79 since the day of the release, without
any issue.
Switch jimtcl to latest tag 0.79
[1] https://packages.debian.org/sid/openocd
Change-Id: I3426e68c32f88ecde74d4278303925423db451e0
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5403
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/jimtcl b/jimtcl
index a9bf5975f..0aa0fb4e3 160000
--- a/jimtcl
+++ b/jimtcl
@@ -1 +1 @@
-Subproject commit a9bf5975fd0f89974d689a2d9ebd0873c8d64787
+Subproject commit 0aa0fb4e3a38d38a49de9eb585d93d63a370dcf6
commit 939febeccafc885d3869ce94c688aaf724f2eccd
Author: Antonio Borneo <bor...@gm...>
Date: Fri Feb 14 14:35:51 2020 +0100
target: fix crash with jimtcl 0.78
The jimtcl commit 41c5ff1809f5 ("jim.c: Fix Object leak in zlib
support") https://repo.or.cz/jimtcl.git/commit/41c5ff1809f5
makes Jim_SetResultFormatted() freeing the parameters that have
zero refcount.
OpenOCD commit 559d08c19ed8 ("jim tests: use installed") adds the
only code instance in OpenOCD that first passes a zero refcount
object to Jim_SetResultFormatted() and then frees it.
By switching jimtcl version to 0.78 or newer this causes a crash
of OpenOCD.
To trigger the crash in a telnet session, check that the current
target is running and type:
[target current] arp_waitstate halted 1
Remove the call to Jim_FreeNewObj() after the call to
Jim_SetResultFormatted().
Change-Id: I5f5a8bca96a0e8466ff7b789fe578ea9785fa550
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5453
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/target/target.c b/src/target/target.c
index 61ed9662d..ceecaee10 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -5164,7 +5164,6 @@ static int jim_target_wait_state(Jim_Interp *interp, int argc, Jim_Obj *const *a
"target: %s wait %s fails (%#s) %s",
target_name(target), n->name,
eObj, target_strerror_safe(e));
- Jim_FreeNewObj(interp, eObj);
return JIM_ERR;
}
return JIM_OK;
-----------------------------------------------------------------------
Summary of changes:
jimtcl | 2 +-
src/target/target.c | 1 -
2 files changed, 1 insertion(+), 2 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-12 10:04:42
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generated because a ref change was pushed to the repository containing
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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 44967a9e07ff01a01a96757f302c053553cff35e
Author: Antonio Borneo <bor...@gm...>
Date: Mon Feb 24 12:26:07 2020 +0100
jtag: report API reset as synchronous
The jtag API reset() is synchronous, but this was not highlighted
in the description.
Change-Id: I76ffb7eec97c8608cfbef0b9268ee18a5f50b221
Signed-off-by: Antonio Borneo <bor...@gm...>
Fixes: 8850eb8f2c51 ("swd: get rid of jtag queue to assert/deassert srst")
Reviewed-on: http://openocd.zylin.com/5471
Reviewed-by: Andreas Fritiofson <and...@gm...>
Tested-by: jenkins
diff --git a/src/jtag/interface.h b/src/jtag/interface.h
index f4c6a98ba..39d2d9d88 100644
--- a/src/jtag/interface.h
+++ b/src/jtag/interface.h
@@ -250,6 +250,8 @@ struct adapter_driver {
/**
* Control (assert/deassert) the signals SRST and TRST on the interface.
+ * This function is synchronous and should be called after the adapter
+ * queue has been properly flushed.
* This function is optional.
* Adapters that don't support resets can either not define this function
* or return an error code.
-----------------------------------------------------------------------
Summary of changes:
src/jtag/interface.h | 2 ++
1 file changed, 2 insertions(+)
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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-12 09:50:19
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- Log -----------------------------------------------------------------
commit 221fe49879607096acad42c9db9f68f852a2fbe7
Author: Tarek BOCHKATI <tar...@gm...>
Date: Tue Feb 25 19:44:58 2020 +0100
semihosting: add semihosting handlers to AArch64
note: this works only when the PE is in AArch64 state
Change-Id: Id6a336ca7d201df72bd1aaaeccce4185473fc1bd
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/5474
Tested-by: jenkins
Reviewed-by: Muhammad Omair Javaid <oma...@li...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 3918b1575..87176f638 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -2782,7 +2782,16 @@ static const struct command_registration aarch64_exec_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
+extern const struct command_registration semihosting_common_handlers[];
+
static const struct command_registration aarch64_command_handlers[] = {
+ {
+ .name = "arm",
+ .mode = COMMAND_ANY,
+ .help = "ARM Command Group",
+ .usage = "",
+ .chain = semihosting_common_handlers
+ },
{
.chain = armv8_command_handlers,
},
-----------------------------------------------------------------------
Summary of changes:
src/target/aarch64.c | 9 +++++++++
1 file changed, 9 insertions(+)
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