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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-12 09:49:16
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via afe899f938a8edb3657c9455fc5caefcaef7e65f (commit)
from a8b1bd8376ad30e8ffe7d4d87ed0b041d7adbe76 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit afe899f938a8edb3657c9455fc5caefcaef7e65f
Author: Matthias Welwarsky <mat...@sy...>
Date: Thu Apr 11 10:22:27 2019 +0200
cortex_a: warn on broken debug_base setting
A common problem with target configurations appears to be broken
debug base address configuration. ARM DDI0406C.d specifies in App. D,
1.4.1, that bit 31 of the debug base address serves as identification
of an external debugger, as opposed to an internal access to memory
mapped debug registers by the CPU. External accesses are treated
as privileged and require no debug authentification via the lock
access register.
Sometimes the base address of a debug component is wrong even
in the targets' ROM table. In this case, the correct base address
must be specified using the -dbgbase argument when creating the
target.
This patch adds a warning when bit 31 of the debug base address
is not set, as a hint to the user.
Change-Id: I9c41d85a138123c657ef655e3436a2aa39249dcc
Signed-off-by: Matthias Welwarsky <mat...@sy...>
Reviewed-on: http://openocd.zylin.com/5105
Tested-by: jenkins
Reviewed-by: Tommy Vestermark <to...@ve...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 8773ea160..a79b0b906 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2718,6 +2718,10 @@ static int cortex_a_examine_first(struct target *target)
} else
armv7a->debug_base = target->dbgbase;
+ if ((armv7a->debug_base & (1UL<<31)) == 0)
+ LOG_WARNING("Debug base address for target %s has bit 31 set to 0. Access to debug registers will likely fail!\n"
+ "Please fix the target configuration.", target_name(target));
+
retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
armv7a->debug_base + CPUDBG_DIDR, &didr);
if (retval != ERROR_OK) {
-----------------------------------------------------------------------
Summary of changes:
src/target/cortex_a.c | 4 ++++
1 file changed, 4 insertions(+)
hooks/post-receive
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-12 09:48:23
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via a8b1bd8376ad30e8ffe7d4d87ed0b041d7adbe76 (commit)
from a154973896576ae59952785e7b2137fb17dac7da (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit a8b1bd8376ad30e8ffe7d4d87ed0b041d7adbe76
Author: Tarek BOCHKATI <tar...@gm...>
Date: Mon Dec 9 12:47:07 2019 +0100
target/armv8_opcodes: use T32 instructions when the PE is in AArch32 state
As stated in ARM v8-A Architecture Reference Manual (ARM DDI 0487E.a)
in Chapter H4.3 DCC and ITR access modes:
Writes to EDITR trigger the instruction to be executed if the PE
is in Debug state:
- If the PE is in AArch64 state, this is an A64 instruction.
- If the PE is in AArch32 state, this is a T32 instruction
But in armv8_opcodes specifically in t32_opcodes we were using some
A32 instructions for HLT, LDRx and STRx opcodes.
Using the correct LDRx and STRx opcodes, fixes 16 and 8 bits memory access
when the PE is in AArch32 state.
Change-Id: Ib1acbdd4966297e7b069569bcb8deea3c3993615
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/5346
Tested-by: jenkins
Reviewed-by: Muhammad Omair Javaid <oma...@li...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/armv8_opcodes.c b/src/target/armv8_opcodes.c
index 6887b2953..96db72871 100644
--- a/src/target/armv8_opcodes.c
+++ b/src/target/armv8_opcodes.c
@@ -68,13 +68,13 @@ static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
[ARMV8_OPC_DCCISW] = ARMV4_5_MCR(15, 0, 0, 7, 14, 2),
[ARMV8_OPC_DCCIVAC] = ARMV4_5_MCR(15, 0, 0, 7, 14, 1),
[ARMV8_OPC_ICIVAU] = ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
- [ARMV8_OPC_HLT] = ARMV8_HLT_A1(11),
- [ARMV8_OPC_LDRB_IP] = ARMV4_5_LDRB_IP(1, 0),
- [ARMV8_OPC_LDRH_IP] = ARMV4_5_LDRH_IP(1, 0),
- [ARMV8_OPC_LDRW_IP] = ARMV4_5_LDRW_IP(1, 0),
- [ARMV8_OPC_STRB_IP] = ARMV4_5_STRB_IP(1, 0),
- [ARMV8_OPC_STRH_IP] = ARMV4_5_STRH_IP(1, 0),
- [ARMV8_OPC_STRW_IP] = ARMV4_5_STRW_IP(1, 0),
+ [ARMV8_OPC_HLT] = ARMV8_HLT_T1(11),
+ [ARMV8_OPC_LDRB_IP] = ARMV8_LDRB_IP_T3(1, 0),
+ [ARMV8_OPC_LDRH_IP] = ARMV8_LDRH_IP_T3(1, 0),
+ [ARMV8_OPC_LDRW_IP] = ARMV8_LDRW_IP_T3(1, 0),
+ [ARMV8_OPC_STRB_IP] = ARMV8_STRB_IP_T3(1, 0),
+ [ARMV8_OPC_STRH_IP] = ARMV8_STRH_IP_T3(1, 0),
+ [ARMV8_OPC_STRW_IP] = ARMV8_STRW_IP_T3(1, 0),
};
void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64)
diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h
index 217cc64c6..239c4c5f1 100644
--- a/src/target/armv8_opcodes.h
+++ b/src/target/armv8_opcodes.h
@@ -164,10 +164,18 @@
#define ARMV8_LDRH_IP(Rd, Rn) (0x78402400 | (Rn << 5) | Rd)
#define ARMV8_LDRW_IP(Rd, Rn) (0xb8404400 | (Rn << 5) | Rd)
+#define ARMV8_LDRB_IP_T3(Rd, Rn) (0xf8100b01 | (Rn << 16) | (Rd << 12))
+#define ARMV8_LDRH_IP_T3(Rd, Rn) (0xf8300b02 | (Rn << 16) | (Rd << 12))
+#define ARMV8_LDRW_IP_T3(Rd, Rn) (0xf8500b04 | (Rn << 16) | (Rd << 12))
+
#define ARMV8_STRB_IP(Rd, Rn) (0x38001400 | (Rn << 5) | Rd)
#define ARMV8_STRH_IP(Rd, Rn) (0x78002400 | (Rn << 5) | Rd)
#define ARMV8_STRW_IP(Rd, Rn) (0xb8004400 | (Rn << 5) | Rd)
+#define ARMV8_STRB_IP_T3(Rd, Rn) (0xf8000b01 | (Rn << 16) | (Rd << 12))
+#define ARMV8_STRH_IP_T3(Rd, Rn) (0xf8200b02 | (Rn << 16) | (Rd << 12))
+#define ARMV8_STRW_IP_T3(Rd, Rn) (0xf8400b04 | (Rn << 16) | (Rd << 12))
+
#define ARMV8_MOV_GPR_VFP(Rd, Rn, Index) (0x4e083c00 | (Index << 20) | (Rn << 5) | Rd)
#define ARMV8_MOV_VFP_GPR(Rd, Rn, Index) (0x4e081c00 | (Index << 20) | (Rn << 5) | Rd)
-----------------------------------------------------------------------
Summary of changes:
src/target/armv8_opcodes.c | 14 +++++++-------
src/target/armv8_opcodes.h | 8 ++++++++
2 files changed, 15 insertions(+), 7 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-12 09:47:47
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via a154973896576ae59952785e7b2137fb17dac7da (commit)
from 4845b5437284b964aad40b1cec57324732abb4d5 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit a154973896576ae59952785e7b2137fb17dac7da
Author: Tarek BOCHKATI <tar...@gm...>
Date: Wed Dec 4 15:09:51 2019 +0100
target/aarch64: fix soft breakpoint when PE is in AArch32 state
Before this patch aarch64_set_breakpoint was using either A64, or A32
HLT opcode by relying on armv8_opcode helper.
This behaviors ignores the fact that in AArch32 state the core could
execute Thumb-2 instructions, and gdb could request to insert a soft
bkpt in a Thumb-2 code chunk.
In this change, we check the core_state and bkpt length to know the
correct opcode to use.
Note: based on https://sourceware.org/gdb/current/onlinedocs/gdb/ARM-Breakpoint-Kinds.html
if bkpt length/kind == 3, we should replace a 32-bit Thumb-2 opcode,
then we use twice the 16 bits Thumb-2 bkpt opcode and we fix-up the
length to 4 bytes, in order to set correctly the bpkt.
Change-Id: I8f3551124412c61d155eae87761767e9937f917d
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/5355
Tested-by: jenkins
Reviewed-by: Muhammad Omair Javaid <oma...@li...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 4d3d9819e..3918b1575 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -1263,9 +1263,32 @@ static int aarch64_set_breakpoint(struct target *target,
brp_list[brp_i].value);
} else if (breakpoint->type == BKPT_SOFT) {
+ uint32_t opcode;
uint8_t code[4];
- buf_set_u32(code, 0, 32, armv8_opcode(armv8, ARMV8_OPC_HLT));
+ if (armv8_dpm_get_core_state(&armv8->dpm) == ARM_STATE_AARCH64) {
+ opcode = ARMV8_HLT(11);
+
+ if (breakpoint->length != 4)
+ LOG_ERROR("bug: breakpoint length should be 4 in AArch64 mode");
+ } else {
+ /**
+ * core_state is ARM_STATE_ARM
+ * in that case the opcode depends on breakpoint length:
+ * - if length == 4 => A32 opcode
+ * - if length == 2 => T32 opcode
+ * - if length == 3 => T32 opcode (refer to gdb doc : ARM-Breakpoint-Kinds)
+ * in that case the length should be changed from 3 to 4 bytes
+ **/
+ opcode = (breakpoint->length == 4) ? ARMV8_HLT_A1(11) :
+ (uint32_t) (ARMV8_HLT_T1(11) | ARMV8_HLT_T1(11) << 16);
+
+ if (breakpoint->length == 3)
+ breakpoint->length = 4;
+ }
+
+ buf_set_u32(code, 0, 32, opcode);
+
retval = target_read_memory(target,
breakpoint->address & 0xFFFFFFFFFFFFFFFE,
breakpoint->length, 1,
diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h
index 3fda29668..217cc64c6 100644
--- a/src/target/armv8_opcodes.h
+++ b/src/target/armv8_opcodes.h
@@ -153,6 +153,7 @@
#define ARMV8_BKPT(Im) (0xD4200000 | ((Im & 0xffff) << 5))
#define ARMV8_HLT(Im) (0x0D4400000 | ((Im & 0xffff) << 5))
#define ARMV8_HLT_A1(Im) (0xE1000070 | ((Im & 0xFFF0) << 4) | (Im & 0xF))
+#define ARMV8_HLT_T1(Im) (0xba80 | (Im & 0x3f))
#define ARMV8_MOVFSP_64(Rt) ((1 << 31) | 0x11000000 | (0x1f << 5) | (Rt))
#define ARMV8_MOVTSP_64(Rt) ((1 << 31) | 0x11000000 | (Rt << 5) | (0x1F))
-----------------------------------------------------------------------
Summary of changes:
src/target/aarch64.c | 25 ++++++++++++++++++++++++-
src/target/armv8_opcodes.h | 1 +
2 files changed, 25 insertions(+), 1 deletion(-)
hooks/post-receive
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-12 09:46:31
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 4845b5437284b964aad40b1cec57324732abb4d5 (commit)
from 9f4659ae6b246bcab77d915cee288b2307a926b3 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 4845b5437284b964aad40b1cec57324732abb4d5
Author: Tarek BOCHKATI <tar...@gm...>
Date: Mon Dec 9 12:35:01 2019 +0100
target/aarch64: fix minor stepping issue with gdb
when using step command from gdb the step happens without any issue,
but aarch64_step call explicitly aarch64_poll which consumes the
status change to HALTED, so it does not inform gdb that the step has
finished.
by removing this call, all is back to normal and openocd could inform gdb
that the step has finished.
Change-Id: I9366aecd20f7d52259b050b8653189b67d9299d0
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/5354
Tested-by: jenkins
Reviewed-by: Muhammad Omair Javaid <oma...@li...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 7acb4726a..4d3d9819e 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -1176,7 +1176,7 @@ static int aarch64_step(struct target *target, int current, target_addr_t addres
if (saved_retval != ERROR_OK)
return saved_retval;
- return aarch64_poll(target);
+ return ERROR_OK;
}
static int aarch64_restore_context(struct target *target, bool bpwp)
-----------------------------------------------------------------------
Summary of changes:
src/target/aarch64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
hooks/post-receive
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-12 09:44:49
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 9f4659ae6b246bcab77d915cee288b2307a926b3 (commit)
from 69f0105324f2fdcd0499ae07ada15d340762d061 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 9f4659ae6b246bcab77d915cee288b2307a926b3
Author: Tomas Vanek <va...@fb...>
Date: Sat Nov 4 09:47:02 2017 +0100
target: add examine-fail event
A configuration script may want to check the reason why examine fails
e.g. device has security lock engaged.
tcl/target/kx.cfg and klx.cfg is modified to use the new event
for testing of the security lock of Kinetis MCU
Change-Id: Id1d3a79d24e84b513f4ea35586cd2ab0437ff9b3
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: http://openocd.zylin.com/4289
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 454ae0675..711171a34 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4820,6 +4820,8 @@ The following target events are defined:
@* Before target examine is called.
@item @b{examine-end}
@* After target examine is called with no errors.
+@item @b{examine-fail}
+@* After target examine fails.
@item @b{gdb-attach}
@* When GDB connects. Issued before any GDB communication with the target
starts. GDB expects the target is halted during attachment.
@@ -5991,7 +5993,8 @@ Used in kinetis 'fcf_source protection' mode only.
@end deffn
@deffn Command {kinetis mdm check_security}
-Checks status of device security lock. Used internally in examine-end event.
+Checks status of device security lock. Used internally in examine-end
+and examine-fail event.
@end deffn
@deffn Command {kinetis mdm halt}
diff --git a/src/target/startup.tcl b/src/target/startup.tcl
index cf844e1f6..976cd2af5 100644
--- a/src/target/startup.tcl
+++ b/src/target/startup.tcl
@@ -66,7 +66,9 @@ proc ocd_process_reset_inner { MODE } {
if {![using_jtag] || [jtag tapisenabled [$t cget -chain-position]]} {
$t invoke-event examine-start
set err [catch "$t arp_examine allow-defer"]
- if { $err == 0 } {
+ if { $err } {
+ $t invoke-event examine-fail
+ } else {
$t invoke-event examine-end
}
}
diff --git a/src/target/target.c b/src/target/target.c
index 1ba4e0987..61ed9662d 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -219,6 +219,7 @@ static const Jim_Nvp nvp_target_event[] = {
{ .value = TARGET_EVENT_RESET_END, .name = "reset-end" },
{ .value = TARGET_EVENT_EXAMINE_START, .name = "examine-start" },
+ { .value = TARGET_EVENT_EXAMINE_FAIL, .name = "examine-fail" },
{ .value = TARGET_EVENT_EXAMINE_END, .name = "examine-end" },
{ .value = TARGET_EVENT_DEBUG_HALTED, .name = "debug-halted" },
@@ -708,13 +709,17 @@ static int default_check_reset(struct target *target)
return ERROR_OK;
}
+/* Equvivalent Tcl code arp_examine_one is in src/target/startup.tcl
+ * Keep in sync */
int target_examine_one(struct target *target)
{
target_call_event_callbacks(target, TARGET_EVENT_EXAMINE_START);
int retval = target->type->examine(target);
- if (retval != ERROR_OK)
+ if (retval != ERROR_OK) {
+ target_call_event_callbacks(target, TARGET_EVENT_EXAMINE_FAIL);
return retval;
+ }
target_call_event_callbacks(target, TARGET_EVENT_EXAMINE_END);
diff --git a/src/target/target.h b/src/target/target.h
index 81fd9d23d..b954ec22d 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -275,6 +275,7 @@ enum target_event {
TARGET_EVENT_DEBUG_RESUMED, /* target resumed to execute on behalf of the debugger */
TARGET_EVENT_EXAMINE_START,
+ TARGET_EVENT_EXAMINE_FAIL,
TARGET_EVENT_EXAMINE_END,
TARGET_EVENT_GDB_ATTACH,
diff --git a/tcl/target/klx.cfg b/tcl/target/klx.cfg
index 36b6ed596..84f6535e3 100644
--- a/tcl/target/klx.cfg
+++ b/tcl/target/klx.cfg
@@ -56,9 +56,9 @@ if {[using_hla]} {
echo " it without mass erase. Don't set write protection on the first block."
echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
echo ""
-} {
- # Detect secured MCU or boot lock-up in RESET/WDOG loop
- $_CHIPNAME.cpu configure -event examine-start {
+} else {
+ # Detect secured MCU
+ $_TARGETNAME configure -event examine-fail {
kinetis mdm check_security
}
diff --git a/tcl/target/kx.cfg b/tcl/target/kx.cfg
index 0ff5b0c53..1dd5d316c 100644
--- a/tcl/target/kx.cfg
+++ b/tcl/target/kx.cfg
@@ -58,9 +58,13 @@ if {[using_hla]} {
echo " it without mass erase. Don't set write protection on the first block."
echo "!!!!!!!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!! WARNING !!!!!!!!!!!!!!!!!!!!!!"
echo ""
-} {
+} else {
# Detect secured MCU or boot lock-up in RESET/WDOG loop
- $_CHIPNAME.cpu configure -event examine-start {
+ $_TARGETNAME configure -event examine-fail {
+ kinetis mdm check_security
+ }
+ # During RESET/WDOG loop the target is sometimes falsely examined
+ $_TARGETNAME configure -event examine-end {
kinetis mdm check_security
}
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 5 ++++-
src/target/startup.tcl | 4 +++-
src/target/target.c | 7 ++++++-
src/target/target.h | 1 +
tcl/target/klx.cfg | 6 +++---
tcl/target/kx.cfg | 8 ++++++--
6 files changed, 23 insertions(+), 8 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-12 09:42:38
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 69f0105324f2fdcd0499ae07ada15d340762d061 (commit)
from a99bf2ea9449d0e8120682feb2bedc398adab8b2 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 69f0105324f2fdcd0499ae07ada15d340762d061
Author: Anton V. Kirilchik <kos...@gm...>
Date: Tue Mar 12 23:11:39 2019 +0300
Add target config for STM8S103 chip...
Change-Id: I693e5b7933fc61956010a96be57ee6eb8abd3c31
Signed-off-by: Anton V. Kirilchik <kos...@gm...>
Reviewed-on: http://openocd.zylin.com/5422
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/stm8s103.cfg b/tcl/target/stm8s103.cfg
new file mode 100644
index 000000000..714acf480
--- /dev/null
+++ b/tcl/target/stm8s103.cfg
@@ -0,0 +1,13 @@
+#config script for STM8S103
+
+set FLASHEND 0x9FFF
+set EEPROMEND 0x427F
+set OPTIONEND 0x480A
+set BLOCKSIZE 0x40
+
+proc stm8_reset_rop {} {
+ mwb 0x4800 0x00
+ reset halt
+}
+
+source [find target/stm8s.cfg]
-----------------------------------------------------------------------
Summary of changes:
tcl/target/{stm8s003.cfg => stm8s103.cfg} | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
copy tcl/target/{stm8s003.cfg => stm8s103.cfg} (65%)
hooks/post-receive
--
Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-10 20:21:55
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via a99bf2ea9449d0e8120682feb2bedc398adab8b2 (commit)
from 123e10288df62e6f66426cdab7adb93fd7348d5f (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit a99bf2ea9449d0e8120682feb2bedc398adab8b2
Author: Tarek BOCHKATI <tar...@gm...>
Date: Tue Feb 25 19:35:44 2020 +0100
semihosting: reorganize semihosting commands
the same semihosting handlers chain is declared twice:
1. in src/target/armv4_5.c
2. in src/target/riscv/riscv.c
to make it simpler we moved the declaration into
'src/target/semihosting_common.c' under semihosting_common_handlers[].
then we used this into both of armv4_5.c and riscv.c
Change-Id: If813b3fd5eb2476658f1308f741c4e805141f617
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/5473
Tested-by: jenkins
Reviewed-by: Muhammad Omair Javaid <oma...@li...>
Reviewed-by: Tim Newsome <ti...@si...>
Reviewed-by: Liviu Ionescu <il...@li...>
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 7a72a0bf0..6c487626c 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -1098,10 +1098,7 @@ static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
return JIM_OK;
}
-extern __COMMAND_HANDLER(handle_common_semihosting_command);
-extern __COMMAND_HANDLER(handle_common_semihosting_fileio_command);
-extern __COMMAND_HANDLER(handle_common_semihosting_resumable_exit_command);
-extern __COMMAND_HANDLER(handle_common_semihosting_cmdline);
+extern const struct command_registration semihosting_common_handlers[];
static const struct command_registration arm_exec_command_handlers[] = {
{
@@ -1140,32 +1137,7 @@ static const struct command_registration arm_exec_command_handlers[] = {
.usage = "cpnum op1 CRn CRm op2",
},
{
- .name = "semihosting",
- .handler = handle_common_semihosting_command,
- .mode = COMMAND_EXEC,
- .usage = "['enable'|'disable']",
- .help = "activate support for semihosting operations",
- },
- {
- .name = "semihosting_cmdline",
- .handler = handle_common_semihosting_cmdline,
- .mode = COMMAND_EXEC,
- .usage = "arguments",
- .help = "command line arguments to be passed to program",
- },
- {
- .name = "semihosting_fileio",
- .handler = handle_common_semihosting_fileio_command,
- .mode = COMMAND_EXEC,
- .usage = "['enable'|'disable']",
- .help = "activate support for semihosting fileio operations",
- },
- {
- .name = "semihosting_resexit",
- .handler = handle_common_semihosting_resumable_exit_command,
- .mode = COMMAND_EXEC,
- .usage = "['enable'|'disable']",
- .help = "activate support for semihosting resumable exit",
+ .chain = semihosting_common_handlers,
},
COMMAND_REGISTRATION_DONE
};
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 1d6f66699..7ad1ccde9 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -1887,11 +1887,6 @@ static const struct command_registration riscv_exec_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
-extern __COMMAND_HANDLER(handle_common_semihosting_command);
-extern __COMMAND_HANDLER(handle_common_semihosting_fileio_command);
-extern __COMMAND_HANDLER(handle_common_semihosting_resumable_exit_command);
-extern __COMMAND_HANDLER(handle_common_semihosting_cmdline);
-
/*
* To be noted that RISC-V targets use the same semihosting commands as
* ARM targets.
@@ -1905,37 +1900,7 @@ extern __COMMAND_HANDLER(handle_common_semihosting_cmdline);
* protocol, then a command like `riscv semihosting enable` will make
* sense, but for now all semihosting commands are prefixed with `arm`.
*/
-static const struct command_registration arm_exec_command_handlers[] = {
- {
- .name = "semihosting",
- .handler = handle_common_semihosting_command,
- .mode = COMMAND_EXEC,
- .usage = "['enable'|'disable']",
- .help = "activate support for semihosting operations",
- },
- {
- .name = "semihosting_cmdline",
- .handler = handle_common_semihosting_cmdline,
- .mode = COMMAND_EXEC,
- .usage = "arguments",
- .help = "command line arguments to be passed to program",
- },
- {
- .name = "semihosting_fileio",
- .handler = handle_common_semihosting_fileio_command,
- .mode = COMMAND_EXEC,
- .usage = "['enable'|'disable']",
- .help = "activate support for semihosting fileio operations",
- },
- {
- .name = "semihosting_resexit",
- .handler = handle_common_semihosting_resumable_exit_command,
- .mode = COMMAND_EXEC,
- .usage = "['enable'|'disable']",
- .help = "activate support for semihosting resumable exit",
- },
- COMMAND_REGISTRATION_DONE
-};
+extern const struct command_registration semihosting_common_handlers[];
const struct command_registration riscv_command_handlers[] = {
{
@@ -1950,7 +1915,7 @@ const struct command_registration riscv_command_handlers[] = {
.mode = COMMAND_ANY,
.help = "ARM Command Group",
.usage = "",
- .chain = arm_exec_command_handlers
+ .chain = semihosting_common_handlers
},
COMMAND_REGISTRATION_DONE
};
diff --git a/src/target/semihosting_common.c b/src/target/semihosting_common.c
index a41f8e4c8..a02f2df3f 100644
--- a/src/target/semihosting_common.c
+++ b/src/target/semihosting_common.c
@@ -1461,7 +1461,7 @@ static void semihosting_set_field(struct target *target, uint64_t value,
/* -------------------------------------------------------------------------
* Common semihosting commands handlers. */
-__COMMAND_HANDLER(handle_common_semihosting_command)
+static __COMMAND_HANDLER(handle_common_semihosting_command)
{
struct target *target = get_current_target(CMD_CTX);
@@ -1502,8 +1502,7 @@ __COMMAND_HANDLER(handle_common_semihosting_command)
return ERROR_OK;
}
-
-__COMMAND_HANDLER(handle_common_semihosting_fileio_command)
+static __COMMAND_HANDLER(handle_common_semihosting_fileio_command)
{
struct target *target = get_current_target(CMD_CTX);
@@ -1533,7 +1532,7 @@ __COMMAND_HANDLER(handle_common_semihosting_fileio_command)
return ERROR_OK;
}
-__COMMAND_HANDLER(handle_common_semihosting_cmdline)
+static __COMMAND_HANDLER(handle_common_semihosting_cmdline)
{
struct target *target = get_current_target(CMD_CTX);
unsigned int i;
@@ -1566,7 +1565,7 @@ __COMMAND_HANDLER(handle_common_semihosting_cmdline)
return ERROR_OK;
}
-__COMMAND_HANDLER(handle_common_semihosting_resumable_exit_command)
+static __COMMAND_HANDLER(handle_common_semihosting_resumable_exit_command)
{
struct target *target = get_current_target(CMD_CTX);
@@ -1595,3 +1594,35 @@ __COMMAND_HANDLER(handle_common_semihosting_resumable_exit_command)
return ERROR_OK;
}
+
+const struct command_registration semihosting_common_handlers[] = {
+ {
+ "semihosting",
+ .handler = handle_common_semihosting_command,
+ .mode = COMMAND_EXEC,
+ .usage = "['enable'|'disable']",
+ .help = "activate support for semihosting operations",
+ },
+ {
+ "semihosting_cmdline",
+ .handler = handle_common_semihosting_cmdline,
+ .mode = COMMAND_EXEC,
+ .usage = "arguments",
+ .help = "command line arguments to be passed to program",
+ },
+ {
+ "semihosting_fileio",
+ .handler = handle_common_semihosting_fileio_command,
+ .mode = COMMAND_EXEC,
+ .usage = "['enable'|'disable']",
+ .help = "activate support for semihosting fileio operations",
+ },
+ {
+ "semihosting_resexit",
+ .handler = handle_common_semihosting_resumable_exit_command,
+ .mode = COMMAND_EXEC,
+ .usage = "['enable'|'disable']",
+ .help = "activate support for semihosting resumable exit",
+ },
+ COMMAND_REGISTRATION_DONE
+};
-----------------------------------------------------------------------
Summary of changes:
src/target/armv4_5.c | 32 ++------------------------------
src/target/riscv/riscv.c | 39 ++-------------------------------------
src/target/semihosting_common.c | 41 ++++++++++++++++++++++++++++++++++++-----
3 files changed, 40 insertions(+), 72 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-10 20:19:32
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 123e10288df62e6f66426cdab7adb93fd7348d5f (commit)
from b304971f380d89d5e934859b2c36e81c26df6eee (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 123e10288df62e6f66426cdab7adb93fd7348d5f
Author: Tarek BOCHKATI <tar...@gm...>
Date: Fri Feb 7 12:52:14 2020 +0100
flash/stm32h7x: fix bank sizes for devices with trimmed flash
STM32H7yxxI: dual independent 1 MByte banks
STM32H7yxxG: dual independent 512 Kbyte banks
STM32H7yxxB: single 128 Kbyte bank
where y = [4/5] or [A/B]
references: (documents are available in www.st.com)
- STM32H7[4/5]x[G/I] : DS12110 Rev 7
>> 3.3.1 Embedded Flash memory
- STM32H750xB : RM0433 Rev 6
>> Table 11. Flash memory organization on STM32H750xB devices
- STM32H7[A/B]x[B/G/I] : RM0455 Rev 3
>> 4.3.4 Flash memory architecture and usage
Change-Id: Ic9346964ef2554abf47f5832e25adfdc77bd323e
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/5442
Tested-by: jenkins
Reviewed-by: Christopher Head <ch...@za...>
diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c
index 7882c11a7..6edbc00fa 100644
--- a/src/flash/nor/stm32h7x.c
+++ b/src/flash/nor/stm32h7x.c
@@ -117,7 +117,7 @@ struct stm32h7x_part_info {
unsigned int block_size; /* flash write word size in bytes */
uint16_t max_flash_size_kb;
uint8_t has_dual_bank;
- uint16_t first_bank_size_kb; /* Used when has_dual_bank is true */
+ uint16_t max_bank_size_kb; /* Used when has_dual_bank is true */
uint32_t flash_regs_base; /* Flash controller registers location */
uint32_t fsize_addr; /* Location of FSIZE register */
uint32_t wps_group_size; /* write protection group sectors' count */
@@ -173,7 +173,7 @@ static const struct stm32h7x_part_info stm32h7x_parts[] = {
.page_size_kb = 128,
.block_size = 32,
.max_flash_size_kb = 2048,
- .first_bank_size_kb = 1024,
+ .max_bank_size_kb = 1024,
.has_dual_bank = 1,
.flash_regs_base = FLASH_REG_BASE_B0,
.fsize_addr = 0x1FF1E880,
@@ -189,7 +189,7 @@ static const struct stm32h7x_part_info stm32h7x_parts[] = {
.page_size_kb = 8,
.block_size = 16,
.max_flash_size_kb = 2048,
- .first_bank_size_kb = 1024,
+ .max_bank_size_kb = 1024,
.has_dual_bank = 1,
.flash_regs_base = FLASH_REG_BASE_B0,
.fsize_addr = 0x08FFF80C,
@@ -740,8 +740,6 @@ static int stm32x_probe(struct flash_bank *bank)
struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
uint16_t flash_size_in_kb;
uint32_t device_id;
- uint32_t base_address = FLASH_BANK0_ADDRESS;
- uint32_t second_bank_base;
stm32x_info->probed = false;
stm32x_info->part_info = NULL;
@@ -776,33 +774,58 @@ static int stm32x_probe(struct flash_bank *bank)
} else
LOG_INFO("flash size probed value %d", flash_size_in_kb);
- /* Lower flash size devices are single bank */
- if (stm32x_info->part_info->has_dual_bank && (flash_size_in_kb > stm32x_info->part_info->first_bank_size_kb)) {
- /* Use the configured base address to determine if this is the first or second flash bank.
- * Verify that the base address is reasonably correct and determine the flash bank size
+
+
+
+ /* setup bank size */
+ const uint32_t bank1_base = FLASH_BANK0_ADDRESS;
+ const uint32_t bank2_base = bank1_base + stm32x_info->part_info->max_bank_size_kb * 1024;
+ bool has_dual_bank = stm32x_info->part_info->has_dual_bank;
+
+ switch (device_id) {
+ case 0x450:
+ case 0x480:
+ /* For STM32H74x/75x and STM32H7Ax/Bx
+ * - STM32H7xxxI devices contains dual bank, 1 Mbyte each
+ * - STM32H7xxxG devices contains dual bank, 512 Kbyte each
+ * - STM32H7xxxB devices contains single bank, 128 Kbyte
+ * - the second bank starts always from 0x08100000
*/
- second_bank_base = base_address + stm32x_info->part_info->first_bank_size_kb * 1024;
- if (bank->base == second_bank_base) {
- /* This is the second bank */
- base_address = second_bank_base;
- flash_size_in_kb = flash_size_in_kb - stm32x_info->part_info->first_bank_size_kb;
- /* bank1 also uses a register offset */
- stm32x_info->flash_regs_base = FLASH_REG_BASE_B1;
- } else if (bank->base == base_address) {
- /* This is the first bank */
- flash_size_in_kb = stm32x_info->part_info->first_bank_size_kb;
- } else {
- LOG_WARNING("STM32H flash bank base address config is incorrect. "
- TARGET_ADDR_FMT " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
- bank->base, base_address, second_bank_base);
+ if (flash_size_in_kb == 128)
+ has_dual_bank = false;
+ else
+ /* flash size is 2M or 1M */
+ flash_size_in_kb /= 2;
+ break;
+ default:
+ LOG_ERROR("unsupported device");
+ return ERROR_FAIL;
+ }
+
+ if (has_dual_bank) {
+ LOG_INFO("STM32H7 flash has dual banks");
+ if (bank->base != bank1_base && bank->base != bank2_base) {
+ LOG_ERROR("STM32H7 flash bank base address config is incorrect. "
+ TARGET_ADDR_FMT " but should rather be 0x%" PRIx32 " or 0x%" PRIx32,
+ bank->base, bank1_base, bank2_base);
return ERROR_FAIL;
}
- LOG_INFO("STM32H flash has dual banks. Bank (%d) size is %dkb, base address is 0x%" PRIx32,
- bank->bank_number, flash_size_in_kb, base_address);
} else {
- LOG_INFO("STM32H flash size is %dkb, base address is 0x%" PRIx32, flash_size_in_kb, base_address);
+ LOG_INFO("STM32H7 flash has a single bank");
+ if (bank->base == bank2_base) {
+ LOG_ERROR("this device has a single bank only");
+ return ERROR_FAIL;
+ } else if (bank->base != bank1_base) {
+ LOG_ERROR("STM32H7 flash bank base address config is incorrect. "
+ TARGET_ADDR_FMT " but should be 0x%" PRIx32,
+ bank->base, bank1_base);
+ return ERROR_FAIL;
+ }
}
+ LOG_INFO("Bank (%d) size is %d kb, base address is 0x%" PRIx32,
+ bank->bank_number, flash_size_in_kb, (uint32_t) bank->base);
+
/* if the user sets the size manually then ignore the probed value
* this allows us to work around devices that have an invalid flash size register value */
if (stm32x_info->user_bank_size) {
@@ -815,8 +838,6 @@ static int stm32x_probe(struct flash_bank *bank)
/* did we assign flash size? */
assert(flash_size_in_kb != 0xffff);
-
- bank->base = base_address;
bank->size = flash_size_in_kb * 1024;
bank->write_start_alignment = stm32x_info->part_info->block_size;
bank->write_end_alignment = stm32x_info->part_info->block_size;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32h7x.c | 77 ++++++++++++++++++++++++++++++------------------
1 file changed, 49 insertions(+), 28 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-09 06:00:32
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via b304971f380d89d5e934859b2c36e81c26df6eee (commit)
from 82a5c55dc357b042b6755b343c920baebd410874 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit b304971f380d89d5e934859b2c36e81c26df6eee
Author: Marek Vasut <mar...@gm...>
Date: Wed Jan 15 05:42:03 2020 +0100
tcl/target: Unify Renesas R-Car JTAG reset config
Both Gen2 and Gen3 used the same init_reset{} implementation,
pull it into common file and include it from both generations.
Moreover, this behavior is SoC specific, not board specific,
so move the common init_reset into target/ directory.
Change-Id: I5489a4bff9a786da8cb7fd7a515b0c9ce9dc16e3
Signed-off-by: Marek Vasut <mar...@gm...>
Reviewed-on: http://openocd.zylin.com/5400
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/tcl/board/renesas_salvator-xs.cfg b/tcl/board/renesas_salvator-xs.cfg
index e6f4da337..6d3096ec1 100644
--- a/tcl/board/renesas_salvator-xs.cfg
+++ b/tcl/board/renesas_salvator-xs.cfg
@@ -7,17 +7,3 @@ if { ![info exists SOC] } {
set SOC H3
}
source [find target/renesas_rcar_gen3.cfg]
-
-reset_config trst_and_srst srst_nogate
-
-proc init_reset {mode} {
- # Assert both resets: equivalent to a power-on reset
- adapter assert trst assert srst
-
- # Deassert TRST to begin TAP communication
- adapter deassert trst assert srst
-
- # TAP should now be responsive, validate the scan-chain
- jtag arp_init
-}
-
diff --git a/tcl/target/renesas_rcar_gen2.cfg b/tcl/target/renesas_rcar_gen2.cfg
index 9f7421d91..91baa6c90 100644
--- a/tcl/target/renesas_rcar_gen2.cfg
+++ b/tcl/target/renesas_rcar_gen2.cfg
@@ -120,4 +120,6 @@ if { [string equal $_boot_core CA15] } {
setup_ca a7 $CA7_DBGBASE $_num_ca7 0
}
+source [find target/renesas_rcar_reset_common.cfg]
+
eval "target smp $smp_targets"
diff --git a/tcl/target/renesas_rcar_gen3.cfg b/tcl/target/renesas_rcar_gen3.cfg
index 34c191827..72f185d61 100644
--- a/tcl/target/renesas_rcar_gen3.cfg
+++ b/tcl/target/renesas_rcar_gen3.cfg
@@ -166,4 +166,6 @@ if { [string equal $_boot_core CA57] } {
setup_a5x a53 $CA53_DBGBASE $CA53_CTIBASE $_num_ca53 0
}
+source [find target/renesas_rcar_reset_common.cfg]
+
eval "target smp $smp_targets"
diff --git a/tcl/board/renesas_gen2_common.cfg b/tcl/target/renesas_rcar_reset_common.cfg
similarity index 100%
rename from tcl/board/renesas_gen2_common.cfg
rename to tcl/target/renesas_rcar_reset_common.cfg
-----------------------------------------------------------------------
Summary of changes:
tcl/board/renesas_salvator-xs.cfg | 14 --------------
tcl/target/renesas_rcar_gen2.cfg | 2 ++
tcl/target/renesas_rcar_gen3.cfg | 2 ++
.../renesas_rcar_reset_common.cfg} | 0
4 files changed, 4 insertions(+), 14 deletions(-)
rename tcl/{board/renesas_gen2_common.cfg => target/renesas_rcar_reset_common.cfg} (100%)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-07 15:33:06
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 82a5c55dc357b042b6755b343c920baebd410874 (commit)
from e9932ef23d4af8466e724b7603549778fb93c294 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 82a5c55dc357b042b6755b343c920baebd410874
Author: Edward Fewell <ef...@ti...>
Date: Fri Feb 28 16:56:11 2020 -0600
flash/nor: update support for TI MSP432 devices
Added fixes for issues found in additional code reviews.
Fixed host Endianness issues with using buffer reads
and writes instead of the *_u32 variants.
Changed code that tried to ID banks by hardcode
bank_number values to use instead the bank base
address. This fixes problems using configurations
with multiple devices.
Note that this replaces Change 4786 which has
been abandoned because of extensive changes to
the code to stop IDing banks by name. And I
think I really messed up a rebase/merge on the
document file.
Tested on MSP432P401R, MSP432P4111, and MSP432E401Y
Launchpads.
Change-Id: Id05798b3aa78ae5cbe725ee762a164d673ee5767
Signed-off-by: Edward Fewell <ef...@ti...>
Reviewed-on: http://openocd.zylin.com/5481
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 8aab1ad94..454ae0675 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6299,14 +6299,14 @@ if @{ [info exists IMEMORY] && [string equal $IMEMORY true] @} @{
All versions of the SimpleLink MSP432 microcontrollers from Texas
Instruments include internal flash. The msp432 flash driver automatically
recognizes the specific version's flash parameters and autoconfigures itself.
-Main program flash (starting at address 0) is flash bank 0. Information flash
-region on MSP432P4 versions (starting at address 0x200000) is flash bank 1.
+Main program flash starts at address 0. The information flash region on
+MSP432P4 versions starts at address 0x200000.
@example
flash bank $_FLASHNAME msp432 0 0 0 0 $_TARGETNAME
@end example
-@deffn Command {msp432 mass_erase} [main|all]
+@deffn Command {msp432 mass_erase} bank_id [main|all]
Performs a complete erase of flash. By default, @command{mass_erase} will erase
only the main program flash.
@@ -6315,7 +6315,7 @@ main program and information flash regions. To also erase the BSL in information
flash, the user must first use the @command{bsl} command.
@end deffn
-@deffn Command {msp432 bsl} [unlock|lock]
+@deffn Command {msp432 bsl} bank_id [unlock|lock]
On MSP432P4 versions, @command{bsl} unlocks and locks the bootstrap loader (BSL)
region in information flash so that flash commands can erase or write the BSL.
Leave the BSL locked to prevent accidentally corrupting the bootstrap loader.
diff --git a/src/flash/nor/msp432.c b/src/flash/nor/msp432.c
index e9e4be33a..95c99b970 100644
--- a/src/flash/nor/msp432.c
+++ b/src/flash/nor/msp432.c
@@ -49,7 +49,8 @@ struct msp432_bank {
int family_type;
int device_type;
uint32_t sector_length;
- bool probed[2];
+ bool probed_main;
+ bool probed_info;
bool unlock_bsl;
struct working_area *working_area;
struct armv7m_algorithm armv7m_info;
@@ -194,8 +195,7 @@ static int msp432_exec_cmd(struct target *target, struct msp432_algo_params
return retval;
/* Write out command to target memory */
- retval = target_write_buffer(target, ALGO_FLASH_COMMAND_ADDR,
- sizeof(command), (uint8_t *)&command);
+ retval = target_write_u32(target, ALGO_FLASH_COMMAND_ADDR, command);
return retval;
}
@@ -210,8 +210,7 @@ static int msp432_wait_return_code(struct target *target)
start_ms = timeval_ms();
while ((0 == return_code) || (FLASH_BUSY == return_code)) {
- retval = target_read_buffer(target, ALGO_RETURN_CODE_ADDR,
- sizeof(return_code), (uint8_t *)&return_code);
+ retval = target_read_u32(target, ALGO_RETURN_CODE_ADDR, &return_code);
if (ERROR_OK != retval)
return retval;
@@ -253,8 +252,7 @@ static int msp432_wait_inactive(struct target *target, uint32_t buffer)
start_ms = timeval_ms();
while (BUFFER_INACTIVE != status_code) {
- retval = target_read_buffer(target, status_addr, sizeof(status_code),
- (uint8_t *)&status_code);
+ retval = target_read_u32(target, status_addr, &status_code);
if (ERROR_OK != retval)
return retval;
@@ -477,15 +475,23 @@ COMMAND_HANDLER(msp432_mass_erase_command)
struct flash_bank *bank;
struct msp432_bank *msp432_bank;
bool all;
+
int retval;
- if (0 == CMD_ARGC) {
+ if (1 > CMD_ARGC)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (1 == CMD_ARGC) {
all = false;
- } else if (1 == CMD_ARGC) {
+ } else if (2 == CMD_ARGC) {
/* Check argument for how much to erase */
- if (0 == strcmp(CMD_ARGV[0], "main"))
+ if (0 == strcmp(CMD_ARGV[1], "main"))
all = false;
- else if (0 == strcmp(CMD_ARGV[0], "all"))
+ else if (0 == strcmp(CMD_ARGV[1], "all"))
all = true;
else
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -493,10 +499,6 @@ COMMAND_HANDLER(msp432_mass_erase_command)
return ERROR_COMMAND_SYNTAX_ERROR;
}
- retval = get_flash_bank_by_num(0, &bank);
- if (ERROR_OK != retval)
- return retval;
-
msp432_bank = bank->driver_priv;
if (MSP432E4 == msp432_bank->family_type) {
@@ -513,7 +515,7 @@ COMMAND_HANDLER(msp432_mass_erase_command)
LOG_INFO("msp432: Mass erase of flash is complete");
} else {
LOG_INFO("msp432: Mass erase of %s is complete",
- all ? "main + info flash" : "main flash");
+ all ? "main + information flash" : "main flash");
}
return ERROR_OK;
@@ -523,13 +525,14 @@ COMMAND_HANDLER(msp432_bsl_command)
{
struct flash_bank *bank;
struct msp432_bank *msp432_bank;
+
int retval;
- if (1 < CMD_ARGC)
+ if (1 > CMD_ARGC)
return ERROR_COMMAND_SYNTAX_ERROR;
- retval = get_flash_bank_by_num(0, &bank);
- if (ERROR_OK != retval)
+ retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (retval != ERROR_OK)
return retval;
msp432_bank = bank->driver_priv;
@@ -539,13 +542,16 @@ COMMAND_HANDLER(msp432_bsl_command)
return ERROR_OK;
}
- if (1 == CMD_ARGC) {
- if (0 == strcmp(CMD_ARGV[0], "lock"))
+ if (2 == CMD_ARGC) {
+ if (0 == strcmp(CMD_ARGV[1], "lock"))
msp432_bank->unlock_bsl = false;
- else if (0 == strcmp(CMD_ARGV[0], "unlock"))
+ else if (0 == strcmp(CMD_ARGV[1], "unlock"))
msp432_bank->unlock_bsl = true;
else
return ERROR_COMMAND_SYNTAX_ERROR;
+ } else if (1 != CMD_ARGC) {
+ /* Extra, unknown argument passed in */
+ return ERROR_COMMAND_SYNTAX_ERROR;
}
LOG_INFO("msp432: BSL flash region is currently %slocked",
@@ -561,6 +567,7 @@ FLASH_BANK_COMMAND_HANDLER(msp432_flash_bank_command)
if (CMD_ARGC < 6)
return ERROR_COMMAND_SYNTAX_ERROR;
+ /* Create shared private struct for flash banks */
msp432_bank = malloc(sizeof(struct msp432_bank));
if (NULL == msp432_bank)
return ERROR_FAIL;
@@ -571,14 +578,14 @@ FLASH_BANK_COMMAND_HANDLER(msp432_flash_bank_command)
msp432_bank->family_type = MSP432_NO_FAMILY;
msp432_bank->device_type = MSP432_NO_TYPE;
msp432_bank->sector_length = 0x1000;
- msp432_bank->probed[0] = false;
- msp432_bank->probed[1] = false;
+ msp432_bank->probed_main = false;
+ msp432_bank->probed_info = false;
msp432_bank->unlock_bsl = false;
msp432_bank->working_area = NULL;
- /* Finish initialization of bank 0 (main flash) */
+ /* Finish up initial settings here */
bank->driver_priv = msp432_bank;
- bank->next = NULL;
+ bank->base = FLASH_BASE;
return ERROR_OK;
}
@@ -589,6 +596,9 @@ static int msp432_erase(struct flash_bank *bank, int first, int last)
struct msp432_bank *msp432_bank = bank->driver_priv;
struct msp432_algo_params algo_params;
+ bool is_main = FLASH_BASE == bank->base;
+ bool is_info = P4_FLASH_INFO_BASE == bank->base;
+
int retval;
if (TARGET_HALTED != target->state) {
@@ -597,8 +607,7 @@ static int msp432_erase(struct flash_bank *bank, int first, int last)
}
/* Do a mass erase if user requested all sectors of main flash */
- if ((0 == bank->bank_number) && (first == 0) &&
- (last == (bank->num_sectors - 1))) {
+ if (is_main && (first == 0) && (last == (bank->num_sectors - 1))) {
/* Request mass erase of main flash */
return msp432_mass_erase(bank, false);
}
@@ -611,7 +620,7 @@ static int msp432_erase(struct flash_bank *bank, int first, int last)
msp432_init_params(&algo_params);
/* Adjust params if this is the info bank */
- if (1 == bank->bank_number) {
+ if (is_info) {
buf_set_u32(algo_params.erase_param, 0, 32, FLASH_ERASE_INFO);
/* And flag if BSL is unlocked */
if (msp432_bank->unlock_bsl)
@@ -622,11 +631,11 @@ static int msp432_erase(struct flash_bank *bank, int first, int last)
for (int i = first; i <= last; i++) {
/* Skip TVL (read-only) sector of the info bank */
- if (1 == bank->bank_number && 1 == i)
+ if (is_info && 1 == i)
continue;
/* Skip BSL sectors of info bank if locked */
- if (1 == bank->bank_number && (2 == i || 3 == i) &&
+ if (is_info && (2 == i || 3 == i) &&
!msp432_bank->unlock_bsl)
continue;
@@ -666,6 +675,8 @@ static int msp432_write(struct flash_bank *bank, const uint8_t *buffer,
long long start_ms;
long long elapsed_ms;
+ bool is_info = P4_FLASH_INFO_BASE == bank->base;
+
int retval;
if (TARGET_HALTED != target->state) {
@@ -679,7 +690,7 @@ static int msp432_write(struct flash_bank *bank, const uint8_t *buffer,
* The BSL region in sectors 2 and 3 of the info flash may be unlocked
* The helper algorithm will hang on attempts to write to TVL
*/
- if (1 == bank->bank_number) {
+ if (is_info) {
/* Set read-only start to TVL sector */
uint32_t start = 0x1000;
/* Set read-only end after BSL region if locked */
@@ -722,7 +733,7 @@ static int msp432_write(struct flash_bank *bank, const uint8_t *buffer,
buf_set_u32(algo_params.length, 0, 32, count);
/* Check if this is the info bank */
- if (1 == bank->bank_number) {
+ if (is_info) {
/* And flag if BSL is unlocked */
if (msp432_bank->unlock_bsl)
buf_set_u32(algo_params.unlock_bsl, 0, 32, FLASH_UNLOCK_BSL);
@@ -753,8 +764,8 @@ static int msp432_write(struct flash_bank *bank, const uint8_t *buffer,
}
/* Signal the flash helper algorithm that data is ready to flash */
- retval = target_write_buffer(target, ALGO_BUFFER1_STATUS_ADDR,
- sizeof(data_ready), (uint8_t *)&data_ready);
+ retval = target_write_u32(target, ALGO_BUFFER1_STATUS_ADDR,
+ data_ready);
if (ERROR_OK != retval) {
(void)msp432_quit(bank);
return ERROR_FLASH_OPERATION_FAILED;
@@ -793,20 +804,23 @@ static int msp432_probe(struct flash_bank *bank)
struct target *target = bank->target;
struct msp432_bank *msp432_bank = bank->driver_priv;
- char *name;
-
uint32_t device_id;
uint32_t hardware_rev;
- uint32_t base;
uint32_t sector_length;
uint32_t size;
int num_sectors;
- int bank_id;
+
+ bool is_main = FLASH_BASE == bank->base;
+ bool is_info = P4_FLASH_INFO_BASE == bank->base;
int retval;
- bank_id = bank->bank_number;
+ /* Check if this bank has already been successfully probed */
+ if (is_main && msp432_bank->probed_main)
+ return ERROR_OK;
+ if (is_info && msp432_bank->probed_info)
+ return ERROR_OK;
/* Read the flash size register to determine this is a P4 or not */
/* MSP432P4s will return the size of flash. MSP432E4s will return zero */
@@ -849,63 +863,16 @@ static int msp432_probe(struct flash_bank *bank)
msp432_bank->device_type = msp432_device_type(msp432_bank->family_type,
msp432_bank->device_id, msp432_bank->hardware_rev);
- /* If not already allocated, create the info bank for MSP432P4 */
- /* We could not determine it was needed until device was probed */
- if (MSP432P4 == msp432_bank->family_type) {
- /* If we've been given bank 1, then this was already done */
- if (0 == bank_id) {
- /* And only allocate it if it doesn't exist yet */
- if (NULL == bank->next) {
- struct flash_bank *info_bank;
- info_bank = malloc(sizeof(struct flash_bank));
- if (NULL == info_bank)
- return ERROR_FAIL;
-
- name = malloc(strlen(bank->name)+1);
- if (NULL == name) {
- free(info_bank);
- return ERROR_FAIL;
- }
- strcpy(name, bank->name);
-
- /* Initialize bank 1 (info region) */
- info_bank->name = name;
- info_bank->target = bank->target;
- info_bank->driver = bank->driver;
- info_bank->driver_priv = bank->driver_priv;
- info_bank->bank_number = 1;
- info_bank->base = 0x00200000;
- info_bank->size = 0;
- info_bank->chip_width = 0;
- info_bank->bus_width = 0;
- info_bank->erased_value = 0xff;
- info_bank->default_padded_value = 0xff;
- info_bank->write_start_alignment = 0;
- info_bank->write_end_alignment = 0;
- info_bank->minimal_write_gap = FLASH_WRITE_GAP_SECTOR;
- info_bank->num_sectors = 0;
- info_bank->sectors = NULL;
- info_bank->num_prot_blocks = 0;
- info_bank->prot_blocks = NULL;
- info_bank->next = NULL;
-
- /* Enable the new bank */
- bank->next = info_bank;
- }
- }
- }
-
if (MSP432P4 == msp432_bank->family_type) {
/* Set up MSP432P4 specific flash parameters */
- if (0 == bank_id) {
+ if (is_main) {
retval = target_read_u32(target, P4_FLASH_MAIN_SIZE_REG, &size);
if (ERROR_OK != retval)
return retval;
- base = P4_FLASH_MAIN_BASE;
sector_length = P4_SECTOR_LENGTH;
num_sectors = size / sector_length;
- } else if (1 == bank_id) {
+ } else if (is_info) {
if (msp432_bank->device_type == MSP432P411X ||
msp432_bank->device_type == MSP432P411X_GUESS) {
/* MSP432P411x has an info size register, use that for size */
@@ -916,19 +883,22 @@ static int msp432_probe(struct flash_bank *bank)
/* All other MSP432P401x devices have fixed info region size */
size = 0x4000; /* 16 KB info region */
}
- base = P4_FLASH_INFO_BASE;
sector_length = P4_SECTOR_LENGTH;
num_sectors = size / sector_length;
} else {
- /* Invalid bank number somehow */
+ /* Invalid bank somehow */
return ERROR_FAIL;
}
} else {
/* Set up MSP432E4 specific flash parameters */
- base = E4_FLASH_BASE;
- size = E4_FLASH_SIZE;
- sector_length = E4_SECTOR_LENGTH;
- num_sectors = size / sector_length;
+ if (is_main) {
+ size = E4_FLASH_SIZE;
+ sector_length = E4_SECTOR_LENGTH;
+ num_sectors = size / sector_length;
+ } else {
+ /* Invalid bank somehow */
+ return ERROR_FAIL;
+ }
}
if (NULL != bank->sectors) {
@@ -936,11 +906,12 @@ static int msp432_probe(struct flash_bank *bank)
bank->sectors = NULL;
}
- bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
- if (NULL == bank->sectors)
- return ERROR_FAIL;
+ if (num_sectors > 0) {
+ bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
+ if (NULL == bank->sectors)
+ return ERROR_FAIL;
+ }
- bank->base = base;
bank->size = size;
bank->write_start_alignment = 0;
bank->write_end_alignment = 0;
@@ -955,7 +926,31 @@ static int msp432_probe(struct flash_bank *bank)
}
/* We've successfully determined the stats on this flash bank */
- msp432_bank->probed[bank_id] = true;
+ if (is_main)
+ msp432_bank->probed_main = true;
+ if (is_info)
+ msp432_bank->probed_info = true;
+
+ if (is_main && MSP432P4 == msp432_bank->family_type) {
+ /* Create the info flash bank needed by MSP432P4 variants */
+ struct flash_bank *info = calloc(sizeof(struct flash_bank), 1);
+ if (NULL == info)
+ return ERROR_FAIL;
+
+ /* Create a name for the info bank, append "_1" to main name */
+ char *name = malloc(strlen(bank->name) + 3);
+ strcpy(name, bank->name);
+ strcat(name, "_1");
+
+ /* Initialize info bank */
+ info->name = name;
+ info->target = bank->target;
+ info->driver = bank->driver;
+ info->driver_priv = msp432_bank;
+ info->base = P4_FLASH_INFO_BASE;
+
+ flash_bank_add(info);
+ }
/* If we fall through to here, then all went well */
@@ -966,15 +961,17 @@ static int msp432_auto_probe(struct flash_bank *bank)
{
struct msp432_bank *msp432_bank = bank->driver_priv;
- int retval = ERROR_OK;
+ bool is_main = FLASH_BASE == bank->base;
+ bool is_info = P4_FLASH_INFO_BASE == bank->base;
- if (bank->bank_number < 0 || bank->bank_number > 1) {
- /* Invalid bank number somehow */
- return ERROR_FAIL;
- }
+ int retval = ERROR_OK;
- if (!msp432_bank->probed[bank->bank_number])
- retval = msp432_probe(bank);
+ if (is_main)
+ if (!msp432_bank->probed_main)
+ retval = msp432_probe(bank);
+ if (is_info)
+ if (!msp432_bank->probed_info)
+ retval = msp432_probe(bank);
return retval;
}
@@ -1036,12 +1033,21 @@ static int msp432_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
+static int msp432_protect_check(struct flash_bank *bank)
+{
+ /* Added to suppress warning, not needed for MSP432 flash */
+ return ERROR_OK;
+}
+
static void msp432_flash_free_driver_priv(struct flash_bank *bank)
{
+ bool is_main = FLASH_BASE == bank->base;
+
/* A single private struct is shared between main and info banks */
- /* Only free it on the call for main bank (#0) */
- if ((0 == bank->bank_number) && (NULL != bank->driver_priv))
+ /* Only free it on the call for main bank */
+ if (is_main && (NULL != bank->driver_priv))
free(bank->driver_priv);
+
/* Forget about the private struct on both main and info banks */
bank->driver_priv = NULL;
}
@@ -1052,14 +1058,14 @@ static const struct command_registration msp432_exec_command_handlers[] = {
.handler = msp432_mass_erase_command,
.mode = COMMAND_EXEC,
.help = "Erase entire flash memory on device.",
- .usage = "['main' | 'all']",
+ .usage = "bank_id ['main' | 'all']",
},
{
.name = "bsl",
.handler = msp432_bsl_command,
.mode = COMMAND_EXEC,
.help = "Allow BSL to be erased or written by flash commands.",
- .usage = "['unlock' | 'lock']",
+ .usage = "bank_id ['unlock' | 'lock']",
},
COMMAND_REGISTRATION_DONE
};
@@ -1085,6 +1091,7 @@ const struct flash_driver msp432_flash = {
.probe = msp432_probe,
.auto_probe = msp432_auto_probe,
.erase_check = default_flash_blank_check,
+ .protect_check = msp432_protect_check,
.info = msp432_info,
.free_driver_priv = msp432_flash_free_driver_priv,
};
diff --git a/src/flash/nor/msp432.h b/src/flash/nor/msp432.h
index ffefa8f43..663393b79 100644
--- a/src/flash/nor/msp432.h
+++ b/src/flash/nor/msp432.h
@@ -34,14 +34,17 @@
#define MSP432E411Y 7 /* MSP432E401Y device */
#define MSP432E4X_GUESS 8 /* Assuming it's an MSP432E4x device */
+/* Common MSP432 flash parameters */
+#define FLASH_BASE 0x00000000
+
/* MSP432P4 flash parameters */
-#define P4_FLASH_MAIN_BASE 0x00000000
+#define P4_FLASH_MAIN_BASE FLASH_BASE
#define P4_FLASH_INFO_BASE 0x00200000
#define P4_SECTOR_LENGTH 0x1000
#define P4_ALGO_ENTRY_ADDR 0x01000110
/* MSP432E4 flash paramters */
-#define E4_FLASH_BASE 0x00000000
+#define E4_FLASH_BASE FLASH_BASE
#define E4_FLASH_SIZE 0x100000
#define E4_SECTOR_LENGTH 0x4000
#define E4_ALGO_ENTRY_ADDR 0x20000110
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 8 +-
src/flash/nor/msp432.c | 229 +++++++++++++++++++++++++------------------------
src/flash/nor/msp432.h | 7 +-
3 files changed, 127 insertions(+), 117 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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- Log -----------------------------------------------------------------
commit e9932ef23d4af8466e724b7603549778fb93c294
Author: luca vinci <luc...@st...>
Date: Wed Jan 8 10:15:40 2020 +0100
bluenrg-x: simplyfied the driver
Adopted only fast algorithm for flash programming:
- write_word and write_byte methods have been removed.
- start and end write alignments have been defined.
Moved flash controller registers offsets in a common file
shared with the flash algorithm.
- the flash base address is passed to the flash algorithm
as a parameter.
Removed unused functions
Change-Id: I80aeab3994e477044bbcf02e66d9525dae0cb491
Signed-off-by: luca vinci <luc...@st...>
Reviewed-on: http://openocd.zylin.com/5393
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Michele Sardo <msm...@gm...>
diff --git a/contrib/loaders/flash/bluenrg-x/Makefile b/contrib/loaders/flash/bluenrg-x/Makefile
index ce86e481a..1a5cfc013 100644
--- a/contrib/loaders/flash/bluenrg-x/Makefile
+++ b/contrib/loaders/flash/bluenrg-x/Makefile
@@ -8,18 +8,15 @@ OBJDUMP=$(CROSS_COMPILE)objdump
CFLAGS = -c -mthumb -mcpu=cortex-m0 -O3 -g
-all:bluenrg-2_write.inc bluenrg-lp_write.inc
+all: bluenrg-x_write.inc
.PHONY: clean
.INTERMEDIATE: bluenrg-x_write.o
-bluenrg-2_write.o: bluenrg-x_write.c
+%.o: %.c
$(CC) $(CFLAGS) -Wall -Wextra -Wa,-adhln=$*.lst $< -o $@
-bluenrg-lp_write.o: bluenrg-x_write.c
- $(CC) $(CFLAGS) -D BLUENRG_LP -Wall -Wextra -Wa,-adhln=$*.lst $< -o $@
-
%.bin: %.o
$(OBJCOPY) -Obinary $< $@
diff --git a/contrib/loaders/flash/bluenrg-x/bluenrg-2_write.inc b/contrib/loaders/flash/bluenrg-x/bluenrg-2_write.inc
deleted file mode 100644
index 1ce4c860e..000000000
--- a/contrib/loaders/flash/bluenrg-x/bluenrg-2_write.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Autogenerated with ../../../../src/helper/bin2char.sh */
-0x05,0x93,0x43,0x68,0x06,0x00,0x09,0x93,0x05,0x9b,0x07,0x91,0x06,0x92,0x34,0x4d,
-0x34,0x4c,0x00,0x2b,0x5d,0xd0,0x72,0x68,0x33,0x68,0x9a,0x42,0xfb,0xd0,0x33,0x68,
-0x00,0x2b,0x56,0xd0,0x72,0x68,0x33,0x68,0x9a,0x42,0x53,0xd9,0x73,0x68,0x07,0x9a,
-0xd3,0x1a,0x0f,0x2b,0xef,0xdd,0x00,0x21,0x2b,0x4a,0x03,0x93,0x11,0x60,0x00,0x2b,
-0x37,0xd0,0x2a,0x4a,0x06,0x9b,0x94,0x46,0x63,0x44,0x18,0x00,0x73,0x68,0x08,0x96,
-0x04,0x93,0x1a,0x00,0x26,0x4b,0x99,0x46,0x26,0x4b,0x98,0x46,0x26,0x4b,0x9c,0x46,
-0x26,0x4b,0x9b,0x46,0x26,0x4b,0x9a,0x46,0x01,0x23,0x91,0x68,0x17,0x68,0x01,0x91,
-0xd1,0x68,0x56,0x68,0x02,0x91,0x3f,0x21,0x29,0x60,0x81,0x03,0x09,0x0c,0x21,0x60,
-0x49,0x46,0x0f,0x60,0x47,0x46,0x3e,0x60,0x66,0x46,0x01,0x99,0x31,0x60,0x5e,0x46,
-0x02,0x99,0x31,0x60,0x51,0x46,0xcc,0x26,0x0e,0x60,0x29,0x68,0x0b,0x42,0xfc,0xd0,
-0x04,0x99,0x03,0x9e,0x10,0x32,0x10,0x30,0x51,0x1a,0x8e,0x42,0xdd,0xd8,0x08,0x9e,
-0x72,0x60,0x03,0x9a,0x06,0x9b,0x94,0x46,0x63,0x44,0x06,0x93,0x07,0x9a,0x73,0x68,
-0x9a,0x42,0x01,0xd8,0x09,0x9b,0x73,0x60,0x05,0x9b,0x03,0x9a,0x9b,0x1a,0x05,0x93,
-0xa1,0xd1,0x00,0xbe,0x33,0x68,0x72,0x68,0x9b,0x1a,0xaa,0xd5,0x9b,0xe7,0xc0,0x46,
-0x10,0x00,0x10,0x40,0x18,0x00,0x10,0x40,0x0c,0x00,0x10,0x40,0x00,0x00,0xfc,0xef,
-0x40,0x00,0x10,0x40,0x44,0x00,0x10,0x40,0x48,0x00,0x10,0x40,0x4c,0x00,0x10,0x40,
-0x00,0x00,0x10,0x40,
diff --git a/contrib/loaders/flash/bluenrg-x/bluenrg-lp_write.inc b/contrib/loaders/flash/bluenrg-x/bluenrg-lp_write.inc
deleted file mode 100644
index cc9b2a174..000000000
--- a/contrib/loaders/flash/bluenrg-x/bluenrg-lp_write.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Autogenerated with ../../../../src/helper/bin2char.sh */
-0x05,0x93,0x43,0x68,0x06,0x00,0x09,0x93,0x05,0x9b,0x07,0x91,0x06,0x92,0x34,0x4d,
-0x34,0x4c,0x00,0x2b,0x5d,0xd0,0x72,0x68,0x33,0x68,0x9a,0x42,0xfb,0xd0,0x33,0x68,
-0x00,0x2b,0x56,0xd0,0x72,0x68,0x33,0x68,0x9a,0x42,0x53,0xd9,0x73,0x68,0x07,0x9a,
-0xd3,0x1a,0x0f,0x2b,0xef,0xdd,0x00,0x21,0x2b,0x4a,0x03,0x93,0x11,0x60,0x00,0x2b,
-0x37,0xd0,0x2a,0x4a,0x06,0x9b,0x94,0x46,0x63,0x44,0x18,0x00,0x73,0x68,0x08,0x96,
-0x04,0x93,0x1a,0x00,0x26,0x4b,0x99,0x46,0x26,0x4b,0x98,0x46,0x26,0x4b,0x9c,0x46,
-0x26,0x4b,0x9b,0x46,0x26,0x4b,0x9a,0x46,0x01,0x23,0x91,0x68,0x17,0x68,0x01,0x91,
-0xd1,0x68,0x56,0x68,0x02,0x91,0x3f,0x21,0x29,0x60,0x81,0x03,0x09,0x0c,0x21,0x60,
-0x49,0x46,0x0f,0x60,0x47,0x46,0x3e,0x60,0x66,0x46,0x01,0x99,0x31,0x60,0x5e,0x46,
-0x02,0x99,0x31,0x60,0x51,0x46,0xcc,0x26,0x0e,0x60,0x29,0x68,0x0b,0x42,0xfc,0xd0,
-0x04,0x99,0x03,0x9e,0x10,0x32,0x10,0x30,0x51,0x1a,0x8e,0x42,0xdd,0xd8,0x08,0x9e,
-0x72,0x60,0x03,0x9a,0x06,0x9b,0x94,0x46,0x63,0x44,0x06,0x93,0x07,0x9a,0x73,0x68,
-0x9a,0x42,0x01,0xd8,0x09,0x9b,0x73,0x60,0x05,0x9b,0x03,0x9a,0x9b,0x1a,0x05,0x93,
-0xa1,0xd1,0x00,0xbe,0x33,0x68,0x72,0x68,0x9b,0x1a,0xaa,0xd5,0x9b,0xe7,0xc0,0x46,
-0x10,0x10,0x00,0x40,0x18,0x10,0x00,0x40,0x0c,0x10,0x00,0x40,0x00,0x00,0xfc,0xef,
-0x40,0x10,0x00,0x40,0x44,0x10,0x00,0x40,0x48,0x10,0x00,0x40,0x4c,0x10,0x00,0x40,
-0x00,0x10,0x00,0x40,
diff --git a/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.c b/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.c
index 695f9145a..f09f7f58a 100644
--- a/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.c
+++ b/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.c
@@ -2,6 +2,7 @@
/* Then postprocess output of command "arm-none-eabi-objdump -d bluenrgx.o" to make a C array of bytes */
#include <stdint.h>
+#include "../../../../src/flash/nor/bluenrg-x.h"
/* Status Values ----------------------------------------------------------*/
#define SUCCESS 0
@@ -13,59 +14,22 @@
#define ERR_ERASE_REQUIRED 6
#define ERR_VERIFY_FAILED 7
-/* Flash Controller defines ---------------------------------------------------*/
-#ifdef BLUENRG_LP
-#define FLASH_REG_COMMAND ((volatile uint32_t *)0x40001000)
-#define FLASH_REG_CONFIG ((volatile uint32_t *)0x40001004)
-#define FLASH_REG_IRQSTAT ((volatile uint32_t *)0x40001008)
-#define FLASH_REG_IRQMASK ((volatile uint32_t *)0x4000100C)
-#define FLASH_REG_IRQRAW ((volatile uint32_t *)0x40001010)
-#define FLASH_REG_ADDRESS ((volatile uint32_t *)0x40001018)
-#define FLASH_REG_UNLOCKM ((volatile uint32_t *)0x4000101C)
-#define FLASH_REG_UNLOCKL ((volatile uint32_t *)0x40001020)
-#define FLASH_REG_DATA0 ((volatile uint32_t *)0x40001040)
-#define FLASH_REG_DATA1 ((volatile uint32_t *)0x40001044)
-#define FLASH_REG_DATA2 ((volatile uint32_t *)0x40001048)
-#define FLASH_REG_DATA3 ((volatile uint32_t *)0x4000104C)
-#define FLASH_SIZE_REG 0x40001014
-#else
-#define FLASH_REG_COMMAND ((volatile uint32_t *)0x40100000)
-#define FLASH_REG_CONFIG ((volatile uint32_t *)0x40100004)
-#define FLASH_REG_IRQSTAT ((volatile uint32_t *)0x40100008)
-#define FLASH_REG_IRQMASK ((volatile uint32_t *)0x4010000C)
-#define FLASH_REG_IRQRAW ((volatile uint32_t *)0x40100010)
-#define FLASH_REG_ADDRESS ((volatile uint32_t *)0x40100018)
-#define FLASH_REG_UNLOCKM ((volatile uint32_t *)0x4010001C)
-#define FLASH_REG_UNLOCKL ((volatile uint32_t *)0x40100020)
-#define FLASH_REG_DATA0 ((volatile uint32_t *)0x40100040)
-#define FLASH_REG_DATA1 ((volatile uint32_t *)0x40100044)
-#define FLASH_REG_DATA2 ((volatile uint32_t *)0x40100048)
-#define FLASH_REG_DATA3 ((volatile uint32_t *)0x4010004C)
-#define FLASH_SIZE_REG 0x40100014
-#endif
-
#define MFB_MASS_ERASE 0x01
#define MFB_PAGE_ERASE 0x02
#define DO_ERASE 0x0100
#define DO_VERIFY 0x0200
-#define FLASH_CMD_ERASE_PAGE 0x11
-#define FLASH_CMD_MASSERASE 0x22
-#define FLASH_CMD_WRITE 0x33
-#define FLASH_CMD_BURSTWRITE 0xCC
-#define FLASH_INT_CMDDONE 0x01
-#define MFB_BOTTOM (0x10040000)
-#define MFB_SIZE_B ((16 * (((*(uint32_t *) FLASH_SIZE_REG) + 1) >> 12)) * 1024)
-#define MFB_SIZE_W (MFB_SIZE_B/4)
-#define MFB_TOP (MFB_BOTTOM+MFB_SIZE_B-1)
-#define MFB_PAGE_SIZE_B (2048)
-#define MFB_PAGE_SIZE_W (MFB_PAGE_SIZE_B/4)
+
+#define MFB_BOTTOM (0x10040000)
+#define MFB_SIZE_B(regs_base) ((16 * (((*(volatile uint32_t *)(regs_base + FLASH_SIZE_REG)) + 1) >> 12)) * 1024)
+#define MFB_SIZE_W (MFB_SIZE_B/4)
+#define MFB_TOP (MFB_BOTTOM+MFB_SIZE_B-1)
+#define MFB_PAGE_SIZE_B (2048)
+#define MFB_PAGE_SIZE_W (MFB_PAGE_SIZE_B/4)
#define AREA_ERROR 0x01
#define AREA_MFB 0x04
-#define FLASH_WORD_LEN 4
-
typedef struct {
volatile uint8_t *wp;
uint8_t *rp;
@@ -73,29 +37,29 @@ typedef struct {
/* Flash Commands --------------------------------------------------------*/
static inline __attribute__((always_inline)) uint32_t flashWrite(uint32_t address, uint8_t **data,
- uint32_t writeLength)
+ uint32_t writeLength, uint32_t flash_regs_base)
{
uint32_t index, flash_word[4];
uint8_t i;
- *FLASH_REG_IRQMASK = 0;
+ *((volatile uint32_t *)(flash_regs_base + FLASH_REG_IRQMASK)) = 0;
for (index = 0; index < writeLength; index += (FLASH_WORD_LEN*4)) {
for (i = 0; i < 4; i++)
flash_word[i] = (*(uint32_t *) (*data + i*4));
/* Clear the IRQ flags */
- *FLASH_REG_IRQRAW = 0x0000003F;
+ *((volatile uint32_t *)(flash_regs_base + FLASH_REG_IRQRAW)) = 0x0000003F;
/* Load the flash address to write */
- *FLASH_REG_ADDRESS = (uint16_t)((address + index - MFB_BOTTOM) >> 2);
+ *((volatile uint32_t *)(flash_regs_base + FLASH_REG_ADDRESS)) = (uint16_t)((address + index - MFB_BOTTOM) >> 2);
/* Prepare and load the data to flash */
- *FLASH_REG_DATA0 = flash_word[0];
- *FLASH_REG_DATA1 = flash_word[1];
- *FLASH_REG_DATA2 = flash_word[2];
- *FLASH_REG_DATA3 = flash_word[3];
+ *((volatile uint32_t *)(flash_regs_base + FLASH_REG_DATA0)) = flash_word[0];
+ *((volatile uint32_t *)(flash_regs_base + FLASH_REG_DATA1)) = flash_word[1];
+ *((volatile uint32_t *)(flash_regs_base + FLASH_REG_DATA2)) = flash_word[2];
+ *((volatile uint32_t *)(flash_regs_base + FLASH_REG_DATA3)) = flash_word[3];
/* Flash write command */
- *FLASH_REG_COMMAND = FLASH_CMD_BURSTWRITE;
+ *((volatile uint32_t *)(flash_regs_base + FLASH_REG_COMMAND)) = FLASH_CMD_BURSTWRITE;
/* Wait the end of the flash write command */
- while ((*FLASH_REG_IRQRAW & FLASH_INT_CMDDONE) == 0)
+ while ((*((volatile uint32_t *)(flash_regs_base + FLASH_REG_IRQRAW)) & FLASH_INT_CMDDONE) == 0)
;
*data += (FLASH_WORD_LEN * 4);
}
@@ -106,7 +70,8 @@ static inline __attribute__((always_inline)) uint32_t flashWrite(uint32_t addres
__attribute__((naked)) __attribute__((noreturn)) void write(uint8_t *work_area_p,
uint8_t *fifo_end,
uint8_t *target_address,
- uint32_t count)
+ uint32_t count,
+ uint32_t flash_regs_base)
{
uint32_t retval;
volatile work_area_t *work_area = (work_area_t *) work_area_p;
@@ -134,7 +99,7 @@ __attribute__((naked)) __attribute__((noreturn)) void write(uint8_t *work_area_p
continue;
}
- retval = flashWrite((uint32_t) target_address, (uint8_t **) &work_area->rp, fifo_linear_size);
+ retval = flashWrite((uint32_t) target_address, (uint8_t **) &work_area->rp, fifo_linear_size, flash_regs_base);
if (retval != SUCCESS) {
work_area->rp = (uint8_t *)retval;
break;
diff --git a/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.inc b/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.inc
new file mode 100644
index 000000000..ff05634bb
--- /dev/null
+++ b/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.inc
@@ -0,0 +1,17 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
+0x05,0x93,0x43,0x68,0x14,0x9e,0x09,0x93,0x05,0x9b,0x05,0x00,0x07,0x91,0x06,0x92,
+0x01,0x24,0xb1,0x46,0x00,0x2b,0x68,0xd0,0x6a,0x68,0x2b,0x68,0x9a,0x42,0xfb,0xd0,
+0x2b,0x68,0x00,0x2b,0x61,0xd0,0x6a,0x68,0x2b,0x68,0x9a,0x42,0x5e,0xd9,0x6b,0x68,
+0x07,0x9a,0xd3,0x1a,0x0f,0x2b,0xef,0xdd,0x4a,0x46,0x00,0x21,0x03,0x93,0xd1,0x60,
+0x00,0x2b,0x42,0xd0,0x40,0x22,0x4a,0x44,0x90,0x46,0x44,0x22,0x4a,0x44,0x00,0x92,
+0x48,0x22,0x4a,0x44,0x93,0x46,0x4c,0x22,0x27,0x4f,0x4a,0x44,0xbc,0x46,0x4e,0x46,
+0x92,0x46,0x06,0x99,0x4b,0x46,0x61,0x44,0x08,0x00,0x00,0x99,0x18,0x36,0x6a,0x68,
+0x08,0x95,0x8c,0x46,0x55,0x46,0xda,0x46,0xb3,0x46,0x10,0x33,0x04,0x92,0x11,0x68,
+0x5e,0x46,0x00,0x91,0x51,0x68,0x97,0x68,0x01,0x91,0xd1,0x68,0x02,0x91,0x3f,0x21,
+0x19,0x60,0x81,0x03,0x09,0x0c,0x31,0x60,0x46,0x46,0x00,0x99,0x31,0x60,0x66,0x46,
+0x01,0x99,0x31,0x60,0x56,0x46,0x02,0x99,0x37,0x60,0x29,0x60,0xcc,0x26,0x49,0x46,
+0x0e,0x60,0x19,0x68,0x0c,0x42,0xfc,0xd0,0x04,0x99,0x03,0x9e,0x10,0x32,0x10,0x30,
+0x51,0x1a,0x8e,0x42,0xdb,0xd8,0x08,0x9d,0x6a,0x60,0x03,0x9a,0x06,0x9b,0x94,0x46,
+0x63,0x44,0x06,0x93,0x07,0x9a,0x6b,0x68,0x9a,0x42,0x01,0xd8,0x09,0x9b,0x6b,0x60,
+0x05,0x9b,0x03,0x9a,0x9b,0x1a,0x05,0x93,0x96,0xd1,0x00,0xbe,0x2b,0x68,0x6a,0x68,
+0x9b,0x1a,0x9f,0xd5,0x90,0xe7,0xc0,0x46,0x00,0x00,0xfc,0xef,
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 8bb4df685..8aab1ad94 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5842,15 +5842,7 @@ Note that when users ask to erase all the sectors of the flash, a mass erase com
each single sector one by one.
@example
-flash erase_sector 0 0 79 # It will perform a mass erase on BlueNRG-1
-@end example
-
-@example
-flash erase_sector 0 0 127 # It will perform a mass erase on BlueNRG-2
-@end example
-
-@example
-flash erase_sector 0 0 127 # It will perform a mass erase on BlueNRG-LP
+flash erase_sector 0 0 last # It will perform a mass erase
@end example
Triggering a mass erase is also useful when users want to disable readout protection.
diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am
index 18b3b859b..64c4a9079 100644
--- a/src/flash/nor/Makefile.am
+++ b/src/flash/nor/Makefile.am
@@ -76,6 +76,7 @@ NOR_DRIVERS = \
NORHEADERS = \
%D%/core.h \
%D%/cc3220sf.h \
+ %D%/bluenrg-x.h \
%D%/cc26xx.h \
%D%/cfi.h \
%D%/driver.h \
diff --git a/src/flash/nor/bluenrg-x.c b/src/flash/nor/bluenrg-x.c
index 79821168e..f7f5e6370 100644
--- a/src/flash/nor/bluenrg-x.c
+++ b/src/flash/nor/bluenrg-x.c
@@ -24,119 +24,63 @@
#include <target/armv7m.h>
#include <target/cortex_m.h>
#include "imp.h"
+#include "bluenrg-x.h"
-#define BLUENRG2_IDCODE (0x0200A041)
-#define BLUENRGLP_IDCODE (0x0201E041)
#define BLUENRG2_JTAG_REG (flash_priv_data_2.jtag_idcode_reg)
#define BLUENRGLP_JTAG_REG (flash_priv_data_lp.jtag_idcode_reg)
-#define FLASH_SIZE_REG(bluenrgx_info) (bluenrgx_info->flash_ptr->flash_size_reg)
#define DIE_ID_REG(bluenrgx_info) (bluenrgx_info->flash_ptr->die_id_reg)
#define JTAG_IDCODE_REG(bluenrgx_info) (bluenrgx_info->flash_ptr->jtag_idcode_reg)
-#define FLASH_BASE(bluenrgx_info) (bluenrgx_info->flash_ptr->flash_base)
#define FLASH_PAGE_SIZE(bluenrgx_info) (bluenrgx_info->flash_ptr->flash_page_size)
-#define FLASH_REG_COMMAND(bluenrgx_info) (bluenrgx_info->flash_ptr->flash_reg_command)
-#define FLASH_REG_IRQRAW(bluenrgx_info) (bluenrgx_info->flash_ptr->flash_reg_irqraw)
-#define FLASH_REG_ADDRESS(bluenrgx_info) (bluenrgx_info->flash_ptr->flash_reg_address)
-#define FLASH_REG_DATA(bluenrgx_info) (bluenrgx_info->flash_ptr->flash_reg_data)
-#define FLASH_CMD_ERASE_PAGE 0x11
-#define FLASH_CMD_MASSERASE 0x22
-#define FLASH_CMD_WRITE 0x33
-#define FLASH_CMD_BURSTWRITE 0xCC
-#define FLASH_INT_CMDDONE 0x01
-#define FLASH_WORD_LEN 4
-
-/* See contrib/loaders/flash/bluenrg-x/bluenrg-x_write.c for source and
- * hints how to generate the data!
- */
-static const uint8_t bluenrgx_flash_write_code_2[] = {
-#include "../../../contrib/loaders/flash/bluenrg-x/bluenrg-2_write.inc"
- };
-
-static const uint8_t bluenrgx_flash_write_code_lp[] = {
-#include "../../../contrib/loaders/flash/bluenrg-x/bluenrg-lp_write.inc"
- };
struct flash_ctrl_priv_data {
- uint32_t flash_size_reg;
uint32_t die_id_reg;
uint32_t jtag_idcode_reg;
uint32_t flash_base;
+ uint32_t flash_regs_base;
uint32_t flash_page_size;
- uint32_t flash_reg_command;
- uint32_t flash_reg_irqraw;
- uint32_t flash_reg_address;
- uint32_t flash_reg_data;
uint32_t jtag_idcode;
char *part_name;
- const uint8_t *flash_write_code;
- uint32_t flash_write_code_size;
};
const struct flash_ctrl_priv_data flash_priv_data_1 = {
- .flash_size_reg = 0x40100014,
.die_id_reg = 0x4090001C,
.jtag_idcode_reg = 0x40900028,
.flash_base = 0x10040000,
+ .flash_regs_base = 0x40100000,
.flash_page_size = 2048,
- .flash_reg_command = 0x40100000,
- .flash_reg_irqraw = 0x40100010,
- .flash_reg_address = 0x40100018,
- .flash_reg_data = 0x40100040,
.jtag_idcode = 0x00000000,
.part_name = "BLUENRG-1",
- .flash_write_code = bluenrgx_flash_write_code_2,
- .flash_write_code_size = sizeof(bluenrgx_flash_write_code_2),
};
const struct flash_ctrl_priv_data flash_priv_data_2 = {
- .flash_size_reg = 0x40100014,
.die_id_reg = 0x4090001C,
.jtag_idcode_reg = 0x40900028,
.flash_base = 0x10040000,
+ .flash_regs_base = 0x40100000,
.flash_page_size = 2048,
- .flash_reg_command = 0x40100000,
- .flash_reg_irqraw = 0x40100010,
- .flash_reg_address = 0x40100018,
- .flash_reg_data = 0x40100040,
- .jtag_idcode = BLUENRG2_IDCODE,
+ .jtag_idcode = 0x0200A041,
.part_name = "BLUENRG-2",
- .flash_write_code = bluenrgx_flash_write_code_2,
- .flash_write_code_size = sizeof(bluenrgx_flash_write_code_2),
};
const struct flash_ctrl_priv_data flash_priv_data_lp = {
- .flash_size_reg = 0x40001014,
.die_id_reg = 0x40000000,
.jtag_idcode_reg = 0x40000004,
.flash_base = 0x10040000,
+ .flash_regs_base = 0x40001000,
.flash_page_size = 2048,
- .flash_reg_command = 0x40001000,
- .flash_reg_irqraw = 0x40001010,
- .flash_reg_address = 0x40001018,
- .flash_reg_data = 0x40001040,
- .jtag_idcode = BLUENRGLP_IDCODE,
+ .jtag_idcode = 0x0201E041,
.part_name = "BLUENRG-LP",
- .flash_write_code = bluenrgx_flash_write_code_lp,
- .flash_write_code_size = sizeof(bluenrgx_flash_write_code_lp),
};
struct bluenrgx_flash_bank {
int probed;
uint32_t die_id;
const struct flash_ctrl_priv_data *flash_ptr;
- const uint8_t *flash_write_code;
- uint32_t flash_write_code_size;
};
const struct flash_ctrl_priv_data *flash_ctrl[] = {&flash_priv_data_1, &flash_priv_data_2, &flash_priv_data_lp};
-static int bluenrgx_protect_check(struct flash_bank *bank)
-{
- /* Nothing to do. Protection is only handled in SW. */
- return ERROR_OK;
-}
-
/* flash_bank bluenrg-x 0 0 0 0 <target#> */
FLASH_BANK_COMMAND_HANDLER(bluenrgx_flash_bank_command)
{
@@ -150,6 +94,9 @@ FLASH_BANK_COMMAND_HANDLER(bluenrgx_flash_bank_command)
return ERROR_FAIL;
}
+ bank->write_start_alignment = 16;
+ bank->write_end_alignment = 16;
+
bank->driver_priv = bluenrgx_info;
bluenrgx_info->probed = 0;
@@ -160,6 +107,22 @@ FLASH_BANK_COMMAND_HANDLER(bluenrgx_flash_bank_command)
return ERROR_OK;
}
+static inline uint32_t bluenrgx_get_flash_reg(struct flash_bank *bank, uint32_t reg_offset)
+{
+ struct bluenrgx_flash_bank *bluenrgx_info = bank->driver_priv;
+ return bluenrgx_info->flash_ptr->flash_regs_base + reg_offset;
+}
+
+static inline int bluenrgx_read_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t *value)
+{
+ return target_read_u32(bank->target, bluenrgx_get_flash_reg(bank, reg_offset), value);
+}
+
+static inline int bluenrgx_write_flash_reg(struct flash_bank *bank, uint32_t reg_offset, uint32_t value)
+{
+ return target_write_u32(bank->target, bluenrgx_get_flash_reg(bank, reg_offset), value);
+}
+
static int bluenrgx_erase(struct flash_bank *bank, int first, int last)
{
int retval = ERROR_OK;
@@ -186,25 +149,25 @@ static int bluenrgx_erase(struct flash_bank *bank, int first, int last)
if (mass_erase) {
command = FLASH_CMD_MASSERASE;
address = bank->base;
- if (target_write_u32(target, FLASH_REG_IRQRAW(bluenrgx_info), 0x3f) != ERROR_OK) {
+ if (bluenrgx_write_flash_reg(bank, FLASH_REG_IRQRAW, 0x3f) != ERROR_OK) {
LOG_ERROR("Register write failed");
return ERROR_FAIL;
}
- if (target_write_u32(target, FLASH_REG_ADDRESS(bluenrgx_info),
- (address - FLASH_BASE(bluenrgx_info)) >> 2) != ERROR_OK) {
+ if (bluenrgx_write_flash_reg(bank, FLASH_REG_ADDRESS,
+ (address - bank->base) >> 2) != ERROR_OK) {
LOG_ERROR("Register write failed");
return ERROR_FAIL;
}
- if (target_write_u32(target, FLASH_REG_COMMAND(bluenrgx_info), command) != ERROR_OK) {
+ if (bluenrgx_write_flash_reg(bank, FLASH_REG_COMMAND, command) != ERROR_OK) {
LOG_ERROR("Register write failed");
return ERROR_FAIL;
}
for (int i = 0; i < 100; i++) {
uint32_t value;
- if (target_read_u32(target, FLASH_REG_IRQRAW(bluenrgx_info), &value)) {
+ if (bluenrgx_read_flash_reg(bank, FLASH_REG_IRQRAW, &value)) {
LOG_ERROR("Register write failed");
return ERROR_FAIL;
}
@@ -222,25 +185,25 @@ static int bluenrgx_erase(struct flash_bank *bank, int first, int last)
address = bank->base+i*FLASH_PAGE_SIZE(bluenrgx_info);
LOG_DEBUG("address = %08x, index = %d", address, i);
- if (target_write_u32(target, FLASH_REG_IRQRAW(bluenrgx_info), 0x3f) != ERROR_OK) {
+ if (bluenrgx_write_flash_reg(bank, FLASH_REG_IRQRAW, 0x3f) != ERROR_OK) {
LOG_ERROR("Register write failed");
return ERROR_FAIL;
}
- if (target_write_u32(target, FLASH_REG_ADDRESS(bluenrgx_info),
- (address - FLASH_BASE(bluenrgx_info)) >> 2) != ERROR_OK) {
+ if (bluenrgx_write_flash_reg(bank, FLASH_REG_ADDRESS,
+ (address - bank->base) >> 2) != ERROR_OK) {
LOG_ERROR("Register write failed");
return ERROR_FAIL;
}
- if (target_write_u32(target, FLASH_REG_COMMAND(bluenrgx_info), command) != ERROR_OK) {
+ if (bluenrgx_write_flash_reg(bank, FLASH_REG_COMMAND, command) != ERROR_OK) {
LOG_ERROR("Failed");
return ERROR_FAIL;
}
for (int j = 0; j < 100; j++) {
uint32_t value;
- if (target_read_u32(target, FLASH_REG_IRQRAW(bluenrgx_info), &value)) {
+ if (bluenrgx_read_flash_reg(bank, FLASH_REG_IRQRAW, &value)) {
LOG_ERROR("Register write failed");
return ERROR_FAIL;
}
@@ -258,143 +221,6 @@ static int bluenrgx_erase(struct flash_bank *bank, int first, int last)
}
-static int bluenrgx_protect(struct flash_bank *bank, int set, int first, int last)
-{
- /* Protection is only handled in software: no hardware write protection
- available in BlueNRG-x devices */
- int sector;
-
- for (sector = first; sector <= last; sector++)
- bank->sectors[sector].is_protected = set;
- return ERROR_OK;
-}
-
-static int bluenrgx_write_word(struct flash_bank *bank, uint32_t address_base, uint8_t *values, uint32_t count)
-{
- int retval = ERROR_OK;
- struct target *target = bank->target;
- struct bluenrgx_flash_bank *bluenrgx_info = bank->driver_priv;
-
- retval = target_write_u32(target, FLASH_REG_IRQRAW(bluenrgx_info), 0x3f);
- if (retval != ERROR_OK) {
- LOG_ERROR("Register write failed, error code: %d", retval);
- return retval;
- }
-
- for (uint32_t i = 0; i < count; i++) {
- uint32_t address = address_base + i * FLASH_WORD_LEN;
-
- retval = target_write_u32(target, FLASH_REG_ADDRESS(bluenrgx_info),
- (address - FLASH_BASE(bluenrgx_info)) >> 2);
- if (retval != ERROR_OK) {
- LOG_ERROR("Register write failed, error code: %d", retval);
- return retval;
- }
-
- retval = target_write_buffer(target, FLASH_REG_DATA(bluenrgx_info),
- FLASH_WORD_LEN, values + i * FLASH_WORD_LEN);
- if (retval != ERROR_OK) {
- LOG_ERROR("Register write failed, error code: %d", retval);
- return retval;
- }
-
- retval = target_write_u32(target, FLASH_REG_COMMAND(bluenrgx_info), FLASH_CMD_WRITE);
- if (retval != ERROR_OK) {
- LOG_ERROR("Register write failed, error code: %d", retval);
- return retval;
- }
-
- for (int j = 0; j < 100; j++) {
- uint32_t reg_value;
- retval = target_read_u32(target, FLASH_REG_IRQRAW(bluenrgx_info), ®_value);
-
- if (retval != ERROR_OK) {
- LOG_ERROR("Register read failed, error code: %d", retval);
- return retval;
- }
-
- if (reg_value & FLASH_INT_CMDDONE)
- break;
-
- if (j == 99) {
- LOG_ERROR("Write command failed (timeout)");
- return ERROR_FAIL;
- }
- }
- }
- return retval;
-}
-
-static int bluenrgx_write_bytes(struct flash_bank *bank, uint32_t address_base, uint8_t *buffer, uint32_t count)
-{
- int retval = ERROR_OK;
- struct target *target = bank->target;
- uint8_t *new_buffer = NULL;
- uint32_t pre_bytes = 0, post_bytes = 0, pre_word, post_word, pre_address, post_address;
-
- if (count == 0) {
- /* Just return if there are no bytes to write */
- return retval;
- }
-
- if (address_base & 3) {
- pre_bytes = address_base & 3;
- pre_address = address_base - pre_bytes;
- }
-
- if ((count + pre_bytes) & 3) {
- post_bytes = ((count + pre_bytes + 3) & ~3) - (count + pre_bytes);
- post_address = (address_base + count) & ~3;
- }
-
- if (pre_bytes || post_bytes) {
- uint32_t old_count = count;
-
- count = old_count + pre_bytes + post_bytes;
-
- new_buffer = malloc(count);
-
- if (new_buffer == NULL) {
- LOG_ERROR("odd number of bytes to write and no memory "
- "for padding buffer");
- return ERROR_FAIL;
- }
-
- LOG_INFO("Requested number of bytes to write and/or address not word aligned (%" PRIu32 "), extending to %"
- PRIu32 " ", old_count, count);
-
- if (pre_bytes) {
- if (target_read_u32(target, pre_address, &pre_word)) {
- LOG_ERROR("Memory read failed");
- free(new_buffer);
- return ERROR_FAIL;
- }
-
- }
-
- if (post_bytes) {
- if (target_read_u32(target, post_address, &post_word)) {
- LOG_ERROR("Memory read failed");
- free(new_buffer);
- return ERROR_FAIL;
- }
-
- }
-
- memcpy(new_buffer, &pre_word, pre_bytes);
- memcpy((new_buffer+((pre_bytes+old_count) & ~3)), &post_word, 4);
- memcpy(new_buffer+pre_bytes, buffer, old_count);
- buffer = new_buffer;
- }
-
- retval = bluenrgx_write_word(bank, address_base - pre_bytes, buffer, count/4);
-
- if (new_buffer)
- free(new_buffer);
-
- return retval;
-}
-
static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
@@ -406,10 +232,16 @@ static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer,
struct working_area *source;
uint32_t address = bank->base + offset;
struct reg_param reg_params[5];
+ struct mem_param mem_params[1];
struct armv7m_algorithm armv7m_info;
int retval = ERROR_OK;
- uint32_t pre_size = 0, fast_size = 0, post_size = 0;
- uint32_t pre_offset = 0, fast_offset = 0, post_offset = 0;
+
+ /* See contrib/loaders/flash/bluenrg-x/bluenrg-x_write.c for source and
+ * hints how to generate the data!
+ */
+ static const uint8_t bluenrgx_flash_write_code[] = {
+#include "../../../contrib/loaders/flash/bluenrg-x/bluenrg-x_write.inc"
+ };
/* check preconditions */
if (bluenrgx_info->probed == 0)
@@ -427,133 +259,105 @@ static int bluenrgx_write(struct flash_bank *bank, const uint8_t *buffer,
return ERROR_TARGET_NOT_HALTED;
}
- /* We are good here and we need to compute pre_size, fast_size, post_size */
- pre_size = MIN(count, ((offset+0xF) & ~0xF) - offset);
- pre_offset = offset;
- fast_size = 16*((count - pre_size) / 16);
- fast_offset = offset + pre_size;
- post_size = (count-pre_size-fast_size) % 16;
- post_offset = fast_offset + fast_size;
-
- LOG_DEBUG("pre_size = %08x, pre_offset=%08x", pre_size, pre_offset);
- LOG_DEBUG("fast_size = %08x, fast_offset=%08x", fast_size, fast_offset);
- LOG_DEBUG("post_size = %08x, post_offset=%08x", post_size, post_offset);
-
- /* Program initial chunk not 16 bytes aligned */
- retval = bluenrgx_write_bytes(bank, bank->base+pre_offset, (uint8_t *) buffer, pre_size);
- if (retval) {
- LOG_ERROR("bluenrgx_write_bytes failed %d", retval);
- return ERROR_FAIL;
+ if (target_alloc_working_area(target, sizeof(bluenrgx_flash_write_code),
+ &write_algorithm) != ERROR_OK) {
+ LOG_WARNING("no working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
- /* Program chunk 16 bytes aligned in fast mode */
- if (fast_size) {
-
- if (target_alloc_working_area(target, bluenrgx_info->flash_write_code_size,
- &write_algorithm) != ERROR_OK) {
- LOG_WARNING("no working area available, can't do block memory writes");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
-
- retval = target_write_buffer(target, write_algorithm->address,
- bluenrgx_info->flash_write_code_size,
- bluenrgx_info->flash_write_code);
- if (retval != ERROR_OK)
- return retval;
+ retval = target_write_buffer(target, write_algorithm->address,
+ sizeof(bluenrgx_flash_write_code),
+ bluenrgx_flash_write_code);
+ if (retval != ERROR_OK)
+ return retval;
- /* memory buffer */
- if (target_alloc_working_area(target, buffer_size, &source)) {
- LOG_WARNING("no large enough working area available");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
+ /* memory buffer */
+ if (target_alloc_working_area(target, buffer_size, &source)) {
+ LOG_WARNING("no large enough working area available");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
- /* Stack pointer area */
- if (target_alloc_working_area(target, 64,
- &write_algorithm_sp) != ERROR_OK) {
- LOG_DEBUG("no working area for write code stack pointer");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
+ /* Stack pointer area */
+ if (target_alloc_working_area(target, 128,
+ &write_algorithm_sp) != ERROR_OK) {
+ LOG_DEBUG("no working area for write code stack pointer");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
- armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
- armv7m_info.core_mode = ARM_MODE_THREAD;
-
- init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
- init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
- init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
- init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
- init_reg_param(®_params[4], "sp", 32, PARAM_OUT);
-
- /* FIFO start address (first two words used for write and read pointers) */
- buf_set_u32(reg_params[0].value, 0, 32, source->address);
- /* FIFO end address (first two words used for write and read pointers) */
- buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
- /* Flash memory address */
- buf_set_u32(reg_params[2].value, 0, 32, address+pre_size);
- /* Number of bytes */
- buf_set_u32(reg_params[3].value, 0, 32, fast_size);
- /* Stack pointer for program working area */
- buf_set_u32(reg_params[4].value, 0, 32, write_algorithm_sp->address);
-
- LOG_DEBUG("source->address = " TARGET_ADDR_FMT, source->address);
- LOG_DEBUG("source->address+ source->size = " TARGET_ADDR_FMT, source->address+source->size);
- LOG_DEBUG("write_algorithm_sp->address = " TARGET_ADDR_FMT, write_algorithm_sp->address);
- LOG_DEBUG("address = %08x", address+pre_size);
- LOG_DEBUG("count = %08x", count);
-
- retval = target_run_flash_async_algorithm(target,
- buffer+pre_size,
- fast_size/16,
- 16, /* Block size: we write in block of 16 bytes to enjoy burstwrite speed */
- 0,
- NULL,
- 5,
- reg_params,
- source->address,
- source->size,
- write_algorithm->address,
- 0,
- &armv7m_info);
-
- if (retval == ERROR_FLASH_OPERATION_FAILED) {
- LOG_ERROR("error executing bluenrg-x flash write algorithm");
-
- uint32_t error = buf_get_u32(reg_params[0].value, 0, 32);
-
- if (error != 0)
- LOG_ERROR("flash write failed = %08" PRIx32, error);
- }
+ armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
+ armv7m_info.core_mode = ARM_MODE_THREAD;
+
+ init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT);
+ init_reg_param(®_params[1], "r1", 32, PARAM_OUT);
+ init_reg_param(®_params[2], "r2", 32, PARAM_OUT);
+ init_reg_param(®_params[3], "r3", 32, PARAM_OUT);
+ init_reg_param(®_params[4], "sp", 32, PARAM_OUT);
+ /* Put the parameter at the first available stack location */
+ init_mem_param(&mem_params[0], write_algorithm_sp->address + 80, 32, PARAM_OUT);
+
+ /* FIFO start address (first two words used for write and read pointers) */
+ buf_set_u32(reg_params[0].value, 0, 32, source->address);
+ /* FIFO end address (first two words used for write and read pointers) */
+ buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
+ /* Flash memory address */
+ buf_set_u32(reg_params[2].value, 0, 32, address);
+ /* Number of bytes */
+ buf_set_u32(reg_params[3].value, 0, 32, count);
+ /* Stack pointer for program working area */
+ buf_set_u32(reg_params[4].value, 0, 32, write_algorithm_sp->address);
+ /* Flash register base address */
+ buf_set_u32(mem_params[0].value, 0, 32, bluenrgx_info->flash_ptr->flash_regs_base);
+
+ LOG_DEBUG("source->address = " TARGET_ADDR_FMT, source->address);
+ LOG_DEBUG("source->address+ source->size = " TARGET_ADDR_FMT, source->address+source->size);
+ LOG_DEBUG("write_algorithm_sp->address = " TARGET_ADDR_FMT, write_algorithm_sp->address);
+ LOG_DEBUG("address = %08x", address);
+ LOG_DEBUG("count = %08x", count);
+
+ retval = target_run_flash_async_algorithm(target,
+ buffer,
+ count/16,
+ 16, /* Block size: we write in block of 16 bytes to enjoy burstwrite speed */
+ 1,
+ mem_params,
+ 5,
+ reg_params,
+ source->address,
+ source->size,
+ write_algorithm->address,
+ 0,
+ &armv7m_info);
+
+ if (retval == ERROR_FLASH_OPERATION_FAILED) {
+ LOG_ERROR("error executing bluenrg-x flash write algorithm");
+
+ uint32_t error = buf_get_u32(reg_params[0].value, 0, 32);
+
+ if (error != 0)
+ LOG_ERROR("flash write failed = %08" PRIx32, error);
+ }
+ if (retval == ERROR_OK) {
+ uint32_t rp;
+ /* Read back rp and check that is valid */
+ retval = target_read_u32(target, source->address+4, &rp);
if (retval == ERROR_OK) {
- uint32_t rp;
- /* Read back rp and check that is valid */
- retval = target_read_u32(target, source->address+4, &rp);
- if (retval == ERROR_OK) {
- if ((rp < source->address+8) || (rp > (source->address + source->size))) {
- LOG_ERROR("flash write failed = %08" PRIx32, rp);
- retval = ERROR_FLASH_OPERATION_FAILED;
- }
+ if ((rp < source->address+8) || (rp > (source->address + source->size))) {
+ LOG_ERROR("flash write failed = %08" PRIx32, rp);
+ retval = ERROR_FLASH_OPERATION_FAILED;
}
}
- target_free_working_area(target, source);
- target_free_working_area(target, write_algorithm);
- target_free_working_area(target, write_algorithm_sp);
-
- destroy_reg_param(®_params[0]);
- destroy_reg_param(®_params[1]);
- destroy_reg_param(®_params[2]);
- destroy_reg_param(®_params[3]);
- destroy_reg_param(®_params[4]);
- if (retval != ERROR_OK)
- return retval;
-
}
+ target_free_working_area(target, source);
+ target_free_working_area(target, write_algorithm);
+ target_free_working_area(target, write_algorithm_sp);
+
+ destroy_reg_param(®_params[0]);
+ destroy_reg_param(®_params[1]);
+ destroy_reg_param(®_params[2]);
+ destroy_reg_param(®_params[3]);
+ destroy_reg_param(®_params[4]);
+ destroy_mem_param(&mem_params[0]);
- /* Program chunk at end, not addressable by fast burst write algorithm */
- retval = bluenrgx_write_bytes(bank, bank->base+post_offset,
- (uint8_t *) (buffer+pre_size+fast_size), post_size);
- if (retval) {
- LOG_ERROR("bluenrgx_write_bytes failed %d", retval);
- return ERROR_FAIL;
- }
return retval;
}
@@ -567,7 +371,7 @@ static int bluenrgx_probe(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
- if (idcode != BLUENRGLP_IDCODE) {
+ if (idcode != flash_priv_data_lp.jtag_idcode) {
retval = target_read_u32(bank->target, BLUENRG2_JTAG_REG, &idcode);
if (retval != ERROR_OK)
return retval;
@@ -575,19 +379,16 @@ static int bluenrgx_probe(struct flash_bank *bank)
/* Default device is BlueNRG-1 */
bluenrgx_info->flash_ptr = &flash_priv_data_1;
- bluenrgx_info->flash_write_code = flash_priv_data_1.flash_write_code;
- bluenrgx_info->flash_write_code_size = flash_priv_data_1.flash_write_code_size;
+ bank->base = flash_priv_data_1.flash_base;
for (i = 0; i < (int)(sizeof(flash_ctrl)/sizeof(*flash_ctrl)); i++) {
if (idcode == (*flash_ctrl[i]).jtag_idcode) {
bluenrgx_info->flash_ptr = flash_ctrl[i];
- bluenrgx_info->flash_write_code = (*flash_ctrl[i]).flash_write_code;
- bluenrgx_info->flash_write_code_size = (*flash_ctrl[i]).flash_write_code_size;
+ bank->base = (*flash_ctrl[i]).flash_base;
break;
}
}
-
- retval = target_read_u32(bank->target, FLASH_SIZE_REG(bluenrgx_info), &size_info);
+ retval = bluenrgx_read_flash_reg(bank, FLASH_SIZE_REG, &size_info);
if (retval != ERROR_OK)
return retval;
@@ -596,7 +397,6 @@ static int bluenrgx_probe(struct flash_bank *bank)
return retval;
bank->size = (size_info + 1) * FLASH_WORD_LEN;
- bank->base = FLASH_BASE(bluenrgx_info);
bank->num_sectors = bank->size/FLASH_PAGE_SIZE(bluenrgx_info);
bank->sectors = realloc(bank->sectors, sizeof(struct flash_sector) * bank->num_sectors);
@@ -650,12 +450,12 @@ const struct flash_driver bluenrgx_flash = {
.name = "bluenrg-x",
.flash_bank_command = bluenrgx_flash_bank_command,
.erase = bluenrgx_erase,
- .protect = bluenrgx_protect,
+ .protect = NULL,
.write = bluenrgx_write,
.read = default_flash_read,
.probe = bluenrgx_probe,
.erase_check = default_flash_blank_check,
- .protect_check = bluenrgx_protect_check,
+ .protect_check = NULL,
.auto_probe = bluenrgx_auto_probe,
.info = bluenrgx_get_info,
};
diff --git a/src/flash/nor/bluenrg-x.h b/src/flash/nor/bluenrg-x.h
new file mode 100644
index 000000000..3b84b8b19
--- /dev/null
+++ b/src/flash/nor/bluenrg-x.h
@@ -0,0 +1,45 @@
+/***************************************************************************
+ * Copyright (C) 2019 by STMicroelectronics. *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifndef OPENOCD_FLASH_NOR_BLUENRGX_H
+#define OPENOCD_FLASH_NOR_BLUENRGX_H
+
+/* Flash Controller registers offsets */
+#define FLASH_REG_COMMAND 0x00
+#define FLASH_REG_CONFIG 0x04
+#define FLASH_REG_IRQSTAT 0x08
+#define FLASH_REG_IRQMASK 0x0C
+#define FLASH_REG_IRQRAW 0x10
+#define FLASH_REG_ADDRESS 0x18
+#define FLASH_REG_UNLOCKM 0x1C
+#define FLASH_REG_UNLOCKL 0x20
+#define FLASH_REG_DATA0 0x40
+#define FLASH_REG_DATA1 0x44
+#define FLASH_REG_DATA2 0x48
+#define FLASH_REG_DATA3 0x4C
+#define FLASH_SIZE_REG 0x14
+
+/* Flash Controller commands */
+#define FLASH_CMD_ERASE_PAGE 0x11
+#define FLASH_CMD_MASSERASE 0x22
+#define FLASH_CMD_WRITE 0x33
+#define FLASH_CMD_BURSTWRITE 0xCC
+#define FLASH_INT_CMDDONE 0x01
+
+#define FLASH_WORD_LEN 4
+
+#endif /* OPENOCD_FLASH_NOR_BLUENRGX_H */
diff --git a/tcl/target/bluenrg-x.cfg b/tcl/target/bluenrg-x.cfg
index 691bbbf83..a9d321ee6 100644
--- a/tcl/target/bluenrg-x.cfg
+++ b/tcl/target/bluenrg-x.cfg
@@ -23,13 +23,7 @@ if { [info exists WORKAREASIZE] } {
adapter speed 4000
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x0bb11477
-}
-
-swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+swj_newdap $_CHIPNAME cpu -expected-id 0x0bb11477 -expected-id 0x0bc11477
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
set _TARGETNAME $_CHIPNAME.cpu
commit 6bc0a77a6e1a1146c44785812595250857fc7307
Author: luca vinci <luc...@st...>
Date: Tue Nov 5 08:45:04 2019 +0100
bluenrg-x: added support for BlueNRG-LP device
Extended bluenrg-x flash driver with BlueNRG-LP flash controller.
Changes include:
- register set for the flash controller
- made software structure prone to support more easily future devices
- updated target config file
Change-Id: I2e2dc70db32cf98c62e3a43f2e44a4600a25ac5b
Signed-off-by: luca vinci <luc...@st...>
Reviewed-on: http://openocd.zylin.com/5343
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/contrib/loaders/flash/bluenrg-x/Makefile b/contrib/loaders/flash/bluenrg-x/Makefile
index 1a5cfc013..ce86e481a 100644
--- a/contrib/loaders/flash/bluenrg-x/Makefile
+++ b/contrib/loaders/flash/bluenrg-x/Makefile
@@ -8,15 +8,18 @@ OBJDUMP=$(CROSS_COMPILE)objdump
CFLAGS = -c -mthumb -mcpu=cortex-m0 -O3 -g
-all: bluenrg-x_write.inc
+all:bluenrg-2_write.inc bluenrg-lp_write.inc
.PHONY: clean
.INTERMEDIATE: bluenrg-x_write.o
-%.o: %.c
+bluenrg-2_write.o: bluenrg-x_write.c
$(CC) $(CFLAGS) -Wall -Wextra -Wa,-adhln=$*.lst $< -o $@
+bluenrg-lp_write.o: bluenrg-x_write.c
+ $(CC) $(CFLAGS) -D BLUENRG_LP -Wall -Wextra -Wa,-adhln=$*.lst $< -o $@
+
%.bin: %.o
$(OBJCOPY) -Obinary $< $@
diff --git a/contrib/loaders/flash/bluenrg-x/bluenrg-2_write.inc b/contrib/loaders/flash/bluenrg-x/bluenrg-2_write.inc
new file mode 100644
index 000000000..1ce4c860e
--- /dev/null
+++ b/contrib/loaders/flash/bluenrg-x/bluenrg-2_write.inc
@@ -0,0 +1,18 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
+0x05,0x93,0x43,0x68,0x06,0x00,0x09,0x93,0x05,0x9b,0x07,0x91,0x06,0x92,0x34,0x4d,
+0x34,0x4c,0x00,0x2b,0x5d,0xd0,0x72,0x68,0x33,0x68,0x9a,0x42,0xfb,0xd0,0x33,0x68,
+0x00,0x2b,0x56,0xd0,0x72,0x68,0x33,0x68,0x9a,0x42,0x53,0xd9,0x73,0x68,0x07,0x9a,
+0xd3,0x1a,0x0f,0x2b,0xef,0xdd,0x00,0x21,0x2b,0x4a,0x03,0x93,0x11,0x60,0x00,0x2b,
+0x37,0xd0,0x2a,0x4a,0x06,0x9b,0x94,0x46,0x63,0x44,0x18,0x00,0x73,0x68,0x08,0x96,
+0x04,0x93,0x1a,0x00,0x26,0x4b,0x99,0x46,0x26,0x4b,0x98,0x46,0x26,0x4b,0x9c,0x46,
+0x26,0x4b,0x9b,0x46,0x26,0x4b,0x9a,0x46,0x01,0x23,0x91,0x68,0x17,0x68,0x01,0x91,
+0xd1,0x68,0x56,0x68,0x02,0x91,0x3f,0x21,0x29,0x60,0x81,0x03,0x09,0x0c,0x21,0x60,
+0x49,0x46,0x0f,0x60,0x47,0x46,0x3e,0x60,0x66,0x46,0x01,0x99,0x31,0x60,0x5e,0x46,
+0x02,0x99,0x31,0x60,0x51,0x46,0xcc,0x26,0x0e,0x60,0x29,0x68,0x0b,0x42,0xfc,0xd0,
+0x04,0x99,0x03,0x9e,0x10,0x32,0x10,0x30,0x51,0x1a,0x8e,0x42,0xdd,0xd8,0x08,0x9e,
+0x72,0x60,0x03,0x9a,0x06,0x9b,0x94,0x46,0x63,0x44,0x06,0x93,0x07,0x9a,0x73,0x68,
+0x9a,0x42,0x01,0xd8,0x09,0x9b,0x73,0x60,0x05,0x9b,0x03,0x9a,0x9b,0x1a,0x05,0x93,
+0xa1,0xd1,0x00,0xbe,0x33,0x68,0x72,0x68,0x9b,0x1a,0xaa,0xd5,0x9b,0xe7,0xc0,0x46,
+0x10,0x00,0x10,0x40,0x18,0x00,0x10,0x40,0x0c,0x00,0x10,0x40,0x00,0x00,0xfc,0xef,
+0x40,0x00,0x10,0x40,0x44,0x00,0x10,0x40,0x48,0x00,0x10,0x40,0x4c,0x00,0x10,0x40,
+0x00,0x00,0x10,0x40,
diff --git a/contrib/loaders/flash/bluenrg-x/bluenrg-lp_write.inc b/contrib/loaders/flash/bluenrg-x/bluenrg-lp_write.inc
new file mode 100644
index 000000000..cc9b2a174
--- /dev/null
+++ b/contrib/loaders/flash/bluenrg-x/bluenrg-lp_write.inc
@@ -0,0 +1,18 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
+0x05,0x93,0x43,0x68,0x06,0x00,0x09,0x93,0x05,0x9b,0x07,0x91,0x06,0x92,0x34,0x4d,
+0x34,0x4c,0x00,0x2b,0x5d,0xd0,0x72,0x68,0x33,0x68,0x9a,0x42,0xfb,0xd0,0x33,0x68,
+0x00,0x2b,0x56,0xd0,0x72,0x68,0x33,0x68,0x9a,0x42,0x53,0xd9,0x73,0x68,0x07,0x9a,
+0xd3,0x1a,0x0f,0x2b,0xef,0xdd,0x00,0x21,0x2b,0x4a,0x03,0x93,0x11,0x60,0x00,0x2b,
+0x37,0xd0,0x2a,0x4a,0x06,0x9b,0x94,0x46,0x63,0x44,0x18,0x00,0x73,0x68,0x08,0x96,
+0x04,0x93,0x1a,0x00,0x26,0x4b,0x99,0x46,0x26,0x4b,0x98,0x46,0x26,0x4b,0x9c,0x46,
+0x26,0x4b,0x9b,0x46,0x26,0x4b,0x9a,0x46,0x01,0x23,0x91,0x68,0x17,0x68,0x01,0x91,
+0xd1,0x68,0x56,0x68,0x02,0x91,0x3f,0x21,0x29,0x60,0x81,0x03,0x09,0x0c,0x21,0x60,
+0x49,0x46,0x0f,0x60,0x47,0x46,0x3e,0x60,0x66,0x46,0x01,0x99,0x31,0x60,0x5e,0x46,
+0x02,0x99,0x31,0x60,0x51,0x46,0xcc,0x26,0x0e,0x60,0x29,0x68,0x0b,0x42,0xfc,0xd0,
+0x04,0x99,0x03,0x9e,0x10,0x32,0x10,0x30,0x51,0x1a,0x8e,0x42,0xdd,0xd8,0x08,0x9e,
+0x72,0x60,0x03,0x9a,0x06,0x9b,0x94,0x46,0x63,0x44,0x06,0x93,0x07,0x9a,0x73,0x68,
+0x9a,0x42,0x01,0xd8,0x09,0x9b,0x73,0x60,0x05,0x9b,0x03,0x9a,0x9b,0x1a,0x05,0x93,
+0xa1,0xd1,0x00,0xbe,0x33,0x68,0x72,0x68,0x9b,0x1a,0xaa,0xd5,0x9b,0xe7,0xc0,0x46,
+0x10,0x10,0x00,0x40,0x18,0x10,0x00,0x40,0x0c,0x10,0x00,0x40,0x00,0x00,0xfc,0xef,
+0x40,0x10,0x00,0x40,0x44,0x10,0x00,0x40,0x48,0x10,0x00,0x40,0x4c,0x10,0x00,0x40,
+0x00,0x10,0x00,0x40,
diff --git a/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.c b/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.c
index 3dd17b2fc..695f9145a 100644
--- a/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.c
+++ b/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.c
@@ -14,6 +14,21 @@
#define ERR_VERIFY_FAILED 7
/* Flash Controller defines ---------------------------------------------------*/
+#ifdef BLUENRG_LP
+#define FLASH_REG_COMMAND ((volatile uint32_t *)0x40001000)
+#define FLASH_REG_CONFIG ((volatile uint32_t *)0x40001004)
+#define FLASH_REG_IRQSTAT ((volatile uint32_t *)0x40001008)
+#define FLASH_REG_IRQMASK ((volatile uint32_t *)0x4000100C)
+#define FLASH_REG_IRQRAW ((volatile uint32_t *)0x40001010)
+#define FLASH_REG_ADDRESS ((volatile uint32_t *)0x40001018)
+#define FLASH_REG_UNLOCKM ((volatile uint32_t *)0x4000101C)
+#define FLASH_REG_UNLOCKL ((volatile uint32_t *)0x40001020)
+#define FLASH_REG_DATA0 ((volatile uint32_t *)0x40001040)
+#define FLASH_REG_DATA1 ((volatile uint32_t *)0x40001044)
+#define FLASH_REG_DATA2 ((volatile uint32_t *)0x40001048)
+#define FLASH_REG_DATA3 ((volatile uint32_t *)0x4000104C)
+#define FLASH_SIZE_REG 0x40001014
+#else
#define FLASH_REG_COMMAND ((volatile uint32_t *)0x40100000)
#define FLASH_REG_CONFIG ((volatile uint32_t *)0x40100004)
#define FLASH_REG_IRQSTAT ((volatile uint32_t *)0x40100008)
@@ -22,11 +37,12 @@
#define FLASH_REG_ADDRESS ((volatile uint32_t *)0x40100018)
#define FLASH_REG_UNLOCKM ((volatile uint32_t *)0x4010001C)
#define FLASH_REG_UNLOCKL ((volatile uint32_t *)0x40100020)
-#define FLASH_REG_DATA0 ((volatile uint32_t *)0x40100040)
-#define FLASH_REG_DATA1 ((volatile uint32_t *)0x40100044)
-#define FLASH_REG_DATA2 ((volatile uint32_t *)0x40100048)
-#define FLASH_REG_DATA3 ((volatile uint32_t *)0x4010004C)
+#define FLASH_REG_DATA0 ((volatile uint32_t *)0x40100040)
+#define FLASH_REG_DATA1 ((volatile uint32_t *)0x40100044)
+#define FLASH_REG_DATA2 ((volatile uint32_t *)0x40100048)
+#define FLASH_REG_DATA3 ((volatile uint32_t *)0x4010004C)
#define FLASH_SIZE_REG 0x40100014
+#endif
#define MFB_MASS_ERASE 0x01
#define MFB_PAGE_ERASE 0x02
@@ -70,7 +86,7 @@ static inline __attribute__((always_inline)) uint32_t flashWrite(uint32_t addres
/* Clear the IRQ flags */
*FLASH_REG_IRQRAW = 0x0000003F;
/* Load the flash address to write */
- *FLASH_REG_ADDRESS = (uint16_t)((address + index) >> 2);
+ *FLASH_REG_ADDRESS = (uint16_t)((address + index - MFB_BOTTOM) >> 2);
/* Prepare and load the data to flash */
*FLASH_REG_DATA0 = flash_word[0];
*FLASH_REG_DATA1 = flash_word[1];
diff --git a/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.inc b/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.inc
deleted file mode 100644
index 47f331228..000000000
--- a/contrib/loaders/flash/bluenrg-x/bluenrg-x_write.inc
+++ /dev/null
@@ -1,18 +0,0 @@
-/* Autogenerated with ../../../../src/helper/bin2char.sh */
-0x05,0x93,0x43,0x68,0x05,0x00,0x07,0x93,0x05,0x9b,0x06,0x91,0x03,0x92,0x35,0x4c,
-0x00,0x2b,0x5c,0xd0,0x6a,0x68,0x2b,0x68,0x9a,0x42,0xfb,0xd0,0x2b,0x68,0x00,0x2b,
-0x55,0xd0,0x6a,0x68,0x2b,0x68,0x9a,0x42,0x52,0xd9,0x6b,0x68,0x06,0x9a,0xd3,0x1a,
-0x09,0x93,0x09,0x9b,0x0f,0x2b,0xed,0xdd,0x00,0x21,0x09,0x9b,0x04,0x93,0x1a,0x1e,
-0x29,0x4b,0x19,0x60,0x32,0xd0,0x29,0x4b,0x00,0x20,0x98,0x46,0x28,0x4b,0x6a,0x68,
-0x9c,0x46,0x28,0x4b,0x28,0x4e,0x9b,0x46,0x28,0x4b,0x9a,0x46,0x28,0x4b,0x99,0x46,
-0x01,0x23,0x51,0x68,0x17,0x68,0x00,0x91,0x91,0x68,0x01,0x91,0xd1,0x68,0x02,0x91,
-0x3f,0x21,0x21,0x60,0x03,0x99,0x09,0x18,0x89,0x03,0x09,0x0c,0x31,0x60,0x41,0x46,
-0x0f,0x60,0x67,0x46,0x00,0x99,0x39,0x60,0x5f,0x46,0x01,0x99,0x39,0x60,0x57,0x46,
-0x02,0x99,0x39,0x60,0x49,0x46,0xcc,0x27,0x0f,0x60,0x21,0x68,0x0b,0x42,0xfc,0xd0,
-0x04,0x99,0x10,0x32,0x10,0x30,0x6a,0x60,0x81,0x42,0xda,0xd8,0x03,0x9a,0x09,0x9b,
-0x94,0x46,0x9c,0x44,0x63,0x46,0x06,0x9a,0x03,0x93,0x6b,0x68,0x9a,0x42,0x01,0xd8,
-0x07,0x9b,0x6b,0x60,0x05,0x9a,0x09,0x9b,0xd3,0x1a,0x05,0x93,0xa2,0xd1,0x00,0xbe,
-0x2b,0x68,0x6a,0x68,0x9b,0x1a,0x09,0x93,0x09,0x9b,0x00,0x2b,0xa9,0xda,0x00,0x23,
-0x09,0x93,0xa6,0xe7,0x10,0x00,0x10,0x40,0x0c,0x00,0x10,0x40,0x40,0x00,0x10,0x40,
-0x44,0x00,0x10,0x40,0x48,0x00,0x10,0x40,0x18,0x00,0x10,0x40,0x4c,0x00,0x10,0x40,
-0x00,0x00,0x10,0x40,
diff --git a/doc/openocd.texi b/doc/openocd.texi
index d059cfae2..8bb4df685 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5830,7 +5830,7 @@ The AVR 8-bit microcontrollers from Atmel integrate flash memory.
@end deffn
@deffn {Flash Driver} bluenrg-x
-STMicroelectronics BlueNRG-1 and BlueNRG-2 Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0 core and internal flash memory.
+STMicroelectronics BlueNRG-1, BlueNRG-2 and BlueNRG-LP Bluetooth low energy wireless system-on-chip. They include ARM Cortex-M0/M0+ core and internal flash memory.
The driver automatically recognizes these chips using
the chip identification registers, and autoconfigures itself.
@@ -5849,6 +5849,10 @@ flash erase_sector 0 0 79 # It will perform a mass erase on BlueNRG-1
flash erase_sector 0 0 127 # It will perform a mass erase on BlueNRG-2
@end example
+@example
+flash erase_sector 0 0 127 # It will perform a mass erase on BlueNRG-LP
+@end example
+
Triggering a mass erase is also useful when users want to disable readout protection.
@end deffn
diff --git a/src/flash/nor/bluenrg-x.c b/src/flash/nor/bluenrg-x.c
index f6a249273..79821168e 100644
--- a/src/flash/nor/bluenrg-x.c
+++ b/src/flash/nor/bluenrg-x.c
@@ -25,16 +25,20 @@
#include <target/cortex_m.h>
#include "imp.h"
-#define FLASH_SIZE_REG (0x40100014)
-#define DIE_ID_REG (0x4090001C)
-#define JTAG_IDCODE_REG (0x40900028)
#define BLUENRG2_IDCODE (0x0200A041)
-#define FLASH_BASE (0x10040000)
-#define FLASH_PAGE_SIZE (2048)
-#define FLASH_REG_COMMAND (0x40100000)
-#define FLASH_REG_IRQRAW (0x40100010)
-#define FLASH_REG_ADDRESS (0x40100018)
-#define FLASH_REG_DATA (0x40100040)
+#define BLUENRGLP_IDCODE (0x0201E041)
+#define BLUENRG2_JTAG_REG (flash_priv_data_2.jtag_idcode_reg)
+#define BLUENRGLP_JTAG_REG (flash_priv_data_lp.jtag_idcode_reg)
+
+#define FLASH_SIZE_REG(bluenrgx_info) (bluenrgx_info->flash_ptr->flash_size_reg)
+#define DIE_ID_REG(bluenrgx_info) (bluenrgx_info->flash_ptr->die_id_reg)
+#define JTAG_IDCODE_REG(bluenrgx_info) (bluenrgx_info->flash_ptr->jtag_idcode_reg)
+#define FLASH_BASE(bluenrgx_info) (bluenrgx_info->flash_ptr->flash_base)
+#define FLASH_PAGE_SIZE(bluenrgx_info) (bluenrgx_info->flash_ptr->flash_page_size)
+#define FLASH_REG_COMMAND(bluenrgx_info) (bluenrgx_info->flash_ptr->flash_reg_command)
+#define FLASH_REG_IRQRAW(bluenrgx_info) (bluenrgx_info->flash_ptr->flash_reg_irqraw)
+#define FLASH_REG_ADDRESS(bluenrgx_info) (bluenrgx_info->flash_ptr->flash_reg_address)
+#define FLASH_REG_DATA(bluenrgx_info) (bluenrgx_info->flash_ptr->flash_reg_data)
#define FLASH_CMD_ERASE_PAGE 0x11
#define FLASH_CMD_MASSERASE 0x22
#define FLASH_CMD_WRITE 0x33
@@ -42,12 +46,91 @@
#define FLASH_INT_CMDDONE 0x01
#define FLASH_WORD_LEN 4
+/* See contrib/loaders/flash/bluenrg-x/bluenrg-x_write.c for source and
+ * hints how to generate the data!
+ */
+static const uint8_t bluenrgx_flash_write_code_2[] = {
+#include "../../../contrib/loaders/flash/bluenrg-x/bluenrg-2_write.inc"
+ };
+
+static const uint8_t bluenrgx_flash_write_code_lp[] = {
+#include "../../../contrib/loaders/flash/bluenrg-x/bluenrg-lp_write.inc"
+ };
+
+struct flash_ctrl_priv_data {
+ uint32_t flash_size_reg;
+ uint32_t die_id_reg;
+ uint32_t jtag_idcode_reg;
+ uint32_t flash_base;
+ uint32_t flash_page_size;
+ uint32_t flash_reg_command;
+ uint32_t flash_reg_irqraw;
+ uint32_t flash_reg_address;
+ uint32_t flash_reg_data;
+ uint32_t jtag_idcode;
+ char *part_name;
+ const uint8_t *flash_write_code;
+ uint32_t flash_write_code_size;
+};
+
+const struct flash_ctrl_priv_data flash_priv_data_1 = {
+ .flash_size_reg = 0x40100014,
+ .die_id_reg = 0x4090001C,
+ .jtag_idcode_reg = 0x40900028,
+ .flash_base = 0x10040000,
+ .flash_page_size = 2048,
+ .flash_reg_command = 0x40100000,
+ .flash_reg_irqraw = 0x40100010,
+ .flash_reg_address = 0x40100018,
+ .flash_reg_data = 0x40100040,
+ .jtag_idcode = 0x00000000,
+ .part_name = "BLUENRG-1",
+ .flash_write_code = bluenrgx_flash_write_code_2,
+ .flash_write_code_size = sizeof(bluenrgx_flash_write_code_2),
+};
+
+const struct flash_ctrl_priv_data flash_priv_data_2 = {
+ .flash_size_reg = 0x40100014,
+ .die_id_reg = 0x4090001C,
+ .jtag_idcode_reg = 0x40900028,
+ .flash_base = 0x10040000,
+ .flash_page_size = 2048,
+ .flash_reg_command = 0x40100000,
+ .flash_reg_irqraw = 0x40100010,
+ .flash_reg_address = 0x40100018,
+ .flash_reg_data = 0x40100040,
+ .jtag_idcode = BLUENRG2_IDCODE,
+ .part_name = "BLUENRG-2",
+ .flash_write_code = bluenrgx_flash_write_code_2,
+ .flash_write_code_size = sizeof(bluenrgx_flash_write_code_2),
+};
+
+const struct flash_ctrl_priv_data flash_priv_data_lp = {
+ .flash_size_reg = 0x40001014,
+ .die_id_reg = 0x40000000,
+ .jtag_idcode_reg = 0x40000004,
+ .flash_base = 0x10040000,
+ .flash_page_size = 2048,
+ .flash_reg_command = 0x40001000,
+ .flash_reg_irqraw = 0x40001010,
+ .flash_reg_address = 0x40001018,
+ .flash_reg_data = 0x40001040,
+ .jtag_idcode = BLUENRGLP_IDCODE,
+ .part_name = "BLUENRG-LP",
+ .flash_write_code = bluenrgx_flash_write_code_lp,
+ .flash_write_code_size = sizeof(bluenrgx_flash_write_code_lp),
+};
+
struct bluenrgx_flash_bank {
int probed;
- uint32_t idcode;
uint32_t die_id;
+ const struct flash_ctrl_priv_data *flash_ptr;
+ const uint8_t *flash_write_code;
+ uint32_t flash_write_code_size;
};
+const struct flash_ctrl_priv_data *flash_ctrl[] = {&flash_priv_data_1, &flash_priv_data_2, &flash_priv_data_lp};
+
static int bluenrgx_protect_check(struct flash_bank *bank)
{
/* Nothing to do. Protection is only handled in SW. */
@@ -103,24 +186,25 @@ static int bluenrgx_erase(struct flash_bank *bank, int first, int last)
if (mass_erase) {
command = FLASH_CMD_MASSERASE;
address = bank->base;
- if (target_write_u32(target, FLASH_REG_IRQRAW, 0x3f) != ERROR_OK) {
+ if (target_write_u32(target, FLASH_REG_IRQRAW(bluenrgx_info), 0x3f) != ERROR_OK) {
LOG_ERROR("Register write failed");
return ERROR_FAIL;
}
- if (target_write_u32(target, FLASH_REG_ADDRESS, address >> 2) != ERROR_OK) {
+ if (target_write_u32(target, FLASH_REG_ADDRESS(bluenrgx_info),
+ (address - FLASH_BASE(bluenrgx_info)) >> 2) != ERROR_OK) {
LOG_ERROR("Register write failed");
return ERROR_FAIL;
}
- if (target_write_u32(target, FLASH_REG_COMMAND, command) != ERROR_OK) {
+ if (target_write_u32(target, FLASH_REG_COMMAND(bluenrgx_info), command) != ERROR_OK) {
LOG_ERROR("Register write failed");
return ERROR_FAIL;
}
for (int i = 0; i < 100; i++) {
uint32_t value;
- if (target_read_u32(target, FLASH_REG_IRQRAW, &value)) {
+ if (target_read_u32(target, FLASH_REG_IRQRAW(bluenrgx_info), &value)) {
LOG_ERROR("Register write failed");
return ERROR_FAIL;
}
@@ -135,26 +219,28 @@ static int bluenrgx_erase(struct flash_bank *bank, int first, int last)
} else {
command = FLASH_CMD_ERASE_PAGE;
for (int i = first; i <= last; i++) {
- address = bank->base+i*FLASH_PAGE_SIZE;
+ address = bank->base+i*FLASH_PAGE_SIZE(bluenrgx_info);
+ LOG_DEBUG("address = %08x, index = %d", address, i);
- if (target_write_u32(target, FLASH_REG_IRQRAW, 0x3f) != ERROR_OK) {
+ if (target_write_u32(target, FLASH_REG_IRQRAW(bluenrgx_info), 0x3f) != ERROR_OK) {
LOG_ERROR("Register write failed");
return ERROR_FAIL;
}
- if (target_write_u32(target, FLASH_REG_ADDRESS, address >> 2) != ERROR_OK) {
+ if (target_write_u32(target, FLASH_REG_ADDRESS(bluenrgx_info),
+ (address - FLASH_BASE(bluenrgx_info)) >> 2) != ERROR_OK) {
LOG_ERROR("Register write failed");
return ERROR_FAIL;
}
- if (target_write_u32(target, FLASH_REG_COMMAND, command) != ERROR_OK) {
+ if (target_write_u32(target, FLASH_REG_COMMAND(bluenrgx_info), command) != ERROR_OK) {
LOG_ERROR("Failed");
return ERROR_FAIL;
}
for (int j = 0; j < 100; j++) {
uint32_t value;
- if (target_read_u32(target, FLASH_REG_IRQRAW, &value)) {
+ if (target_read_u32(target, FLASH_REG_IRQRAW(bluenrgx_info), &value)) {
LOG_ERROR("Register write failed");
return ERROR_FAIL;
}
@@ -182,11 +268,14 @@ static int bluenrgx_protect(struct flash_bank *bank, int set, int first, int las
bank->sectors[sector].is_protected = set;
return ERROR_OK;
}
-static int bluenrgx_write_word(struct target *target, uint32_t address_base, uint8_t *values, uint32_t count)
+
+static int bluenrgx_write_word(struct flash_bank *bank, uint32_t address_base, uint8_t *values, uint32_t count)
{
int retval = ERROR_OK;
+ struct target *target = bank->target;
+ struct bluenrgx_flash_bank *bluenrgx_info = bank->driver_priv;
- retval = target_write_u32(target, FLASH_REG_IRQRAW, 0x3f);
+ retval = target_write_u32(target, FLASH_REG_IRQRAW(bluenrgx_info), 0x3f);
if (retval != ERROR_OK) {
LOG_ERROR("Register write failed, error code: %d", retval);
return retval;
@@ -195,19 +284,21 @@ static int bluenrgx_write_word(struct target *target, uint32_t address_base, uin
for (uint32_t i = 0; i < count; i++) {
uint32_t address = address_base + i * FLASH_WORD_LEN;
- retval = target_write_u32(target, FLASH_REG_ADDRESS, address >> 2);
+ retval = target_write_u32(target, FLASH_REG_ADDRESS(bluenrgx_info),
+ (address - FLASH_BASE(bluenrgx_info)) >> 2);
if (retval != ERROR_OK) {
LOG_ERROR("Register write failed, error code: %d", retval);
return retval;
}
- retval = target_write_buffer(target, FLASH_REG_DATA, FLASH_WORD_LEN, values + i * FLASH_WORD_LEN);
+ retval = target_write_buffer(target, FLASH_REG_DATA(bluenrgx_info),
+ FLASH_WORD_LEN, values + i * FLASH_WORD_LEN);
if (retval != ERROR_OK) {
LOG_ERROR("Register write failed, error code: %d", retval);
return retval;
}
- retval = target_write_u32(target, FLASH_REG_COMMAND, FLASH_CMD_WRITE);
+ retval = target_write_u32(target, FLASH_REG_COMMAND(bluenrgx_info), FLASH_CMD_WRITE);
if (retval != ERROR_OK) {
LOG_ERROR("Register write failed, error code: %d", retval);
return retval;
@@ -215,7 +306,7 @@ static int bluenrgx_write_word(struct target *target, uint32_t address_base, uin
for (int j = 0; j < 100; j++) {
uint32_t reg_value;
- retval = target_read_u32(target, FLASH_REG_IRQRAW, ®_value);
+ retval = target_read_u32(target, FLASH_REG_IRQRAW(bluenrgx_info), ®_value);
if (retval != ERROR_OK) {
LOG_ERROR("Register read failed, error code: %d", retval);
@@ -234,9 +325,10 @@ static int bluenrgx_write_word(struct target *target, uint32_t address_base, uin
return retval;
}
-static int bluenrgx_write_bytes(struct target *target, uint32_t address_base, uint8_t *buffer, uint32_t count)
+static int bluenrgx_write_bytes(struct flash_bank *bank, uint32_t ...
[truncated message content] |
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-07 15:31:12
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via a2e822834df52efef5e1bbcb91a6eb1afbf102db (commit)
from 4e981bc27c36e696dc8ace3ab4bab534564770c1 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit a2e822834df52efef5e1bbcb91a6eb1afbf102db
Author: Tomas Vanek <va...@fb...>
Date: Fri Dec 20 23:56:08 2019 +0100
helper/binarybuffer: fix clang static analyzer warnings
Writing bits to an uninitialized buffer generated false warnings.
Zero buffers before setting them by buf_set_u32|64()
(do it only if bit-by-bit copy loop is used,
zeroed buffer is not necessary if a fast path write is used)
Change-Id: I2f7f8ddb45b0cbd08d3e249534fc51f4b5cc6694
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: http://openocd.zylin.com/5383
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <and...@gm...>
diff --git a/src/flash/nor/jtagspi.c b/src/flash/nor/jtagspi.c
index a9f2dd4a4..f6e311ab8 100644
--- a/src/flash/nor/jtagspi.c
+++ b/src/flash/nor/jtagspi.c
@@ -59,7 +59,7 @@ static void jtagspi_set_ir(struct flash_bank *bank)
{
struct jtagspi_flash_bank *info = bank->driver_priv;
struct scan_field field;
- uint8_t buf[4];
+ uint8_t buf[4] = { 0 };
LOG_DEBUG("loading jtagspi ir");
buf_set_u32(buf, 0, info->tap->ir_length, info->ir);
diff --git a/src/helper/binarybuffer.h b/src/helper/binarybuffer.h
index 7ac221e47..3f2481d9a 100644
--- a/src/helper/binarybuffer.h
+++ b/src/helper/binarybuffer.h
@@ -33,6 +33,7 @@
* using the bits in @c value. This routine fast-paths writes
* of little-endian, byte-aligned, 32-bit words.
* @param _buffer The buffer whose bits will be set.
+ * Do not use uninitialized buffer or clang static analyzer emits a warning.
* @param first The bit offset in @c _buffer to start writing (0-31).
* @param num The number of bits from @c value to copy (1-32).
* @param value Up to 32 bits that will be copied to _buffer.
@@ -62,6 +63,7 @@ static inline void buf_set_u32(uint8_t *_buffer,
* using the bits in @c value. This routine fast-paths writes
* of little-endian, byte-aligned, 64-bit words.
* @param _buffer The buffer whose bits will be set.
+ * Do not use uninitialized buffer or clang static analyzer emits a warning.
* @param first The bit offset in @c _buffer to start writing (0-63).
* @param num The number of bits from @c value to copy (1-64).
* @param value Up to 64 bits that will be copied to _buffer.
diff --git a/src/jtag/core.c b/src/jtag/core.c
index 1d59712d1..c5011e522 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -1233,7 +1233,7 @@ static int jtag_examine_chain(void)
/* Add room for end-of-chain marker. */
max_taps++;
- uint8_t *idcode_buffer = malloc(max_taps * 4);
+ uint8_t *idcode_buffer = calloc(4, max_taps);
if (idcode_buffer == NULL)
return ERROR_JTAG_INIT_FAILED;
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index ba0cb1d1e..734b9c1cb 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -1131,7 +1131,7 @@ COMMAND_HANDLER(handle_irscan_command)
}
int field_size = tap->ir_length;
fields[i].num_bits = field_size;
- uint8_t *v = malloc(DIV_ROUND_UP(field_size, 8));
+ uint8_t *v = calloc(1, DIV_ROUND_UP(field_size, 8));
uint64_t value;
retval = parse_u64(CMD_ARGV[i * 2 + 1], &value);
diff --git a/src/target/arm_jtag.c b/src/target/arm_jtag.c
index 9b73d4ea8..49aca3487 100644
--- a/src/target/arm_jtag.c
+++ b/src/target/arm_jtag.c
@@ -33,7 +33,7 @@ int arm_jtag_set_instr_inner(struct jtag_tap *tap,
uint32_t new_instr, void *no_verify_capture, tap_state_t end_state)
{
struct scan_field field;
- uint8_t t[4];
+ uint8_t t[4] = { 0 };
field.num_bits = tap->ir_length;
field.out_value = t;
@@ -56,7 +56,7 @@ int arm_jtag_scann_inner(struct arm_jtag *jtag_info, uint32_t new_scan_chain, ta
{
int retval = ERROR_OK;
- uint8_t out_value[4];
+ uint8_t out_value[4] = { 0 };
buf_set_u32(out_value, 0, jtag_info->scann_size, new_scan_chain);
struct scan_field field = { .num_bits = jtag_info->scann_size, .out_value = out_value, };
diff --git a/src/target/avr32_jtag.c b/src/target/avr32_jtag.c
index c17fbe7f0..6a4d4b3e7 100644
--- a/src/target/avr32_jtag.c
+++ b/src/target/avr32_jtag.c
@@ -35,7 +35,7 @@ static int avr32_jtag_set_instr(struct avr32_jtag *jtag_info, int new_instr)
if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != (uint32_t)new_instr) {
do {
struct scan_field field;
- uint8_t t[4];
+ uint8_t t[4] = { 0 };
uint8_t ret[4];
field.num_bits = tap->ir_length;
diff --git a/src/target/esirisc_jtag.c b/src/target/esirisc_jtag.c
index 333a62225..700ae3a60 100644
--- a/src/target/esirisc_jtag.c
+++ b/src/target/esirisc_jtag.c
@@ -36,7 +36,7 @@ static void esirisc_jtag_set_instr(struct esirisc_jtag *jtag_info, uint32_t new_
if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
struct scan_field field;
- uint8_t t[4];
+ uint8_t t[4] = { 0 };
field.num_bits = tap->ir_length;
field.out_value = t;
diff --git a/src/target/etb.c b/src/target/etb.c
index 392c6ad7f..0c03c4dbe 100644
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -176,13 +176,13 @@ static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
fields[0].in_value = NULL;
fields[1].num_bits = 7;
- uint8_t temp1;
+ uint8_t temp1 = 0;
fields[1].out_value = &temp1;
buf_set_u32(&temp1, 0, 7, 4);
fields[1].in_value = NULL;
fields[2].num_bits = 1;
- uint8_t temp2;
+ uint8_t temp2 = 0;
fields[2].out_value = &temp2;
buf_set_u32(&temp2, 0, 1, 0);
fields[2].in_value = NULL;
@@ -229,7 +229,7 @@ static int etb_read_reg_w_check(struct reg *reg,
fields[0].check_mask = NULL;
fields[1].num_bits = 7;
- uint8_t temp1;
+ uint8_t temp1 = 0;
fields[1].out_value = &temp1;
buf_set_u32(&temp1, 0, 7, reg_addr);
fields[1].in_value = NULL;
@@ -237,7 +237,7 @@ static int etb_read_reg_w_check(struct reg *reg,
fields[1].check_mask = NULL;
fields[2].num_bits = 1;
- uint8_t temp2;
+ uint8_t temp2 = 0;
fields[2].out_value = &temp2;
buf_set_u32(&temp2, 0, 1, 0);
fields[2].in_value = NULL;
@@ -310,13 +310,13 @@ static int etb_write_reg(struct reg *reg, uint32_t value)
fields[0].in_value = NULL;
fields[1].num_bits = 7;
- uint8_t temp1;
+ uint8_t temp1 = 0;
fields[1].out_value = &temp1;
buf_set_u32(&temp1, 0, 7, reg_addr);
fields[1].in_value = NULL;
fields[2].num_bits = 1;
- uint8_t temp2;
+ uint8_t temp2 = 0;
fields[2].out_value = &temp2;
buf_set_u32(&temp2, 0, 1, 1);
fields[2].in_value = NULL;
diff --git a/src/target/etm.c b/src/target/etm.c
index d1cfe61f6..5218a9e48 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -533,7 +533,7 @@ static int etm_read_reg_w_check(struct reg *reg,
fields[0].check_mask = NULL;
fields[1].num_bits = 7;
- uint8_t temp1;
+ uint8_t temp1 = 0;
fields[1].out_value = &temp1;
buf_set_u32(&temp1, 0, 7, reg_addr);
fields[1].in_value = NULL;
@@ -541,7 +541,7 @@ static int etm_read_reg_w_check(struct reg *reg,
fields[1].check_mask = NULL;
fields[2].num_bits = 1;
- uint8_t temp2;
+ uint8_t temp2 = 0;
fields[2].out_value = &temp2;
buf_set_u32(&temp2, 0, 1, 0);
fields[2].in_value = NULL;
@@ -620,13 +620,13 @@ static int etm_write_reg(struct reg *reg, uint32_t value)
fields[0].in_value = NULL;
fields[1].num_bits = 7;
- uint8_t tmp2;
+ uint8_t tmp2 = 0;
fields[1].out_value = &tmp2;
buf_set_u32(&tmp2, 0, 7, reg_addr);
fields[1].in_value = NULL;
fields[2].num_bits = 1;
- uint8_t tmp3;
+ uint8_t tmp3 = 0;
fields[2].out_value = &tmp3;
buf_set_u32(&tmp3, 0, 1, 1);
fields[2].in_value = NULL;
diff --git a/src/target/ls1_sap.c b/src/target/ls1_sap.c
index bc46ed4db..330042f00 100644
--- a/src/target/ls1_sap.c
+++ b/src/target/ls1_sap.c
@@ -113,7 +113,7 @@ static void ls1_sap_set_instr(struct jtag_tap *tap, uint32_t new_instr)
static void ls1_sap_set_addr_high(struct jtag_tap *tap, uint16_t addr_high)
{
struct scan_field field;
- uint8_t buf[2];
+ uint8_t buf[2] = { 0 };
ls1_sap_set_instr(tap, 0x21);
@@ -130,7 +130,7 @@ static void ls1_sap_memory_cmd(struct jtag_tap *tap, uint32_t address,
int32_t size, bool rnw)
{
struct scan_field field;
- uint8_t cmd[8];
+ uint8_t cmd[8] = { 0 };
ls1_sap_set_instr(tap, 0x24);
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 6d35e211d..00bafd033 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -43,7 +43,7 @@ void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, uint32_t new_instr)
struct scan_field field;
field.num_bits = tap->ir_length;
- uint8_t t[4];
+ uint8_t t[4] = { 0 };
field.out_value = t;
buf_set_u32(t, 0, field.num_bits, new_instr);
@@ -100,7 +100,7 @@ int mips_ejtag_drscan_64(struct mips_ejtag *ejtag_info, uint64_t *data)
if (tap == NULL)
return ERROR_FAIL;
struct scan_field field;
- uint8_t t[8], r[8];
+ uint8_t t[8] = { 0 }, r[8];
int retval;
field.num_bits = 64;
@@ -130,7 +130,7 @@ void mips_ejtag_drscan_32_queued(struct mips_ejtag *ejtag_info, uint32_t data_ou
struct scan_field field;
field.num_bits = 32;
- uint8_t scan_out[4];
+ uint8_t scan_out[4] = { 0 };
field.out_value = scan_out;
buf_set_u32(scan_out, 0, field.num_bits, data_out);
diff --git a/src/target/openrisc/or1k_tap_vjtag.c b/src/target/openrisc/or1k_tap_vjtag.c
index 607451a7c..db10f103b 100644
--- a/src/target/openrisc/or1k_tap_vjtag.c
+++ b/src/target/openrisc/or1k_tap_vjtag.c
@@ -149,7 +149,7 @@ static int or1k_tap_vjtag_init(struct or1k_jtag *jtag_info)
* into the USER1 DR is sufficient to cover the most conservative case for m and n.
*/
- uint8_t t[4];
+ uint8_t t[4] = { 0 };
struct scan_field field;
struct jtag_tap *tap = jtag_info->tap;
diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c
index eded86246..cb7b744da 100644
--- a/src/target/riscv/riscv-011.c
+++ b/src/target/riscv/riscv-011.c
@@ -280,7 +280,7 @@ static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
{
struct scan_field field;
uint8_t in_value[4];
- uint8_t out_value[4];
+ uint8_t out_value[4] = { 0 };
buf_set_u32(out_value, 0, 32, out);
@@ -422,7 +422,7 @@ static dbus_status_t dbus_scan(struct target *target, uint16_t *address_in,
{
riscv011_info_t *info = get_info(target);
uint8_t in[8] = {0};
- uint8_t out[8];
+ uint8_t out[8] = {0};
struct scan_field field = {
.num_bits = info->addrbits + DBUS_OP_SIZE + DBUS_DATA_SIZE,
.out_value = out,
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 1e5c02764..66218b76e 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -402,7 +402,7 @@ static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
{
struct scan_field field;
uint8_t in_value[4];
- uint8_t out_value[4];
+ uint8_t out_value[4] = { 0 };
buf_set_u32(out_value, 0, 32, out);
@@ -468,6 +468,7 @@ static dmi_status_t dmi_scan(struct target *target, uint32_t *address_in,
}
memset(in, 0, num_bytes);
+ memset(out, 0, num_bytes);
assert(info->abits != 0);
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 8b5a361bb..1d6f66699 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -203,7 +203,7 @@ static uint32_t dtmcontrol_scan(struct target *target, uint32_t out)
{
struct scan_field field;
uint8_t in_value[4];
- uint8_t out_value[4];
+ uint8_t out_value[4] = { 0 };
buf_set_u32(out_value, 0, 32, out);
@@ -540,7 +540,7 @@ int riscv_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
return ERROR_FAIL;
}
- uint8_t buff[4];
+ uint8_t buff[4] = { 0 };
buf_set_u32(buff, 0, breakpoint->length * CHAR_BIT, breakpoint->length == 4 ? ebreak() : ebreak_c());
int const retval = target_write_memory(target, breakpoint->address, 2, breakpoint->length / 2, buff);
@@ -1047,7 +1047,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
/* Disable Interrupts before attempting to run the algorithm. */
uint64_t current_mstatus;
- uint8_t mstatus_bytes[8];
+ uint8_t mstatus_bytes[8] = { 0 };
LOG_DEBUG("Disabling Interrupts");
struct reg *reg_mstatus = register_get_by_name(target->reg_cache,
@@ -1103,7 +1103,7 @@ static int riscv_run_algorithm(struct target *target, int num_mem_params,
reg_mstatus->type->set(reg_mstatus, mstatus_bytes);
/* Restore registers */
- uint8_t buf[8];
+ uint8_t buf[8] = { 0 };
buf_set_u64(buf, 0, info->xlen[0], saved_pc);
if (reg_pc->type->set(reg_pc, buf) != ERROR_OK)
return ERROR_FAIL;
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 3ef8922b5..e57996585 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -129,7 +129,7 @@ static const struct xscale_reg xscale_reg_arch_info[] = {
/* convenience wrapper to access XScale specific registers */
static int xscale_set_reg_u32(struct reg *reg, uint32_t value)
{
- uint8_t buf[4];
+ uint8_t buf[4] = { 0 };
buf_set_u32(buf, 0, 32, value);
@@ -154,7 +154,7 @@ static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_s
if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
struct scan_field field;
- uint8_t scratch[4];
+ uint8_t scratch[4] = { 0 };
memset(&field, 0, sizeof field);
field.num_bits = tap->ir_length;
@@ -514,7 +514,7 @@ static int xscale_send(struct target *target, const uint8_t *buffer, int count,
TAP_IDLE);
static const uint8_t t0;
- uint8_t t1[4];
+ uint8_t t1[4] = { 0 };
static const uint8_t t2 = 1;
struct scan_field fields[3] = {
{ .num_bits = 3, .out_value = &t0 },
@@ -645,8 +645,8 @@ static unsigned int parity(unsigned int v)
static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8])
{
struct xscale_common *xscale = target_to_xscale(target);
- uint8_t packet[4];
- uint8_t cmd;
+ uint8_t packet[4] = { 0 };
+ uint8_t cmd = 0;
int word;
struct scan_field fields[2];
@@ -699,8 +699,8 @@ static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8]
static int xscale_invalidate_ic_line(struct target *target, uint32_t va)
{
struct xscale_common *xscale = target_to_xscale(target);
- uint8_t packet[4];
- uint8_t cmd;
+ uint8_t packet[4] = { 0 };
+ uint8_t cmd = 0;
struct scan_field fields[2];
xscale_jtag_set_instr(target->tap,
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/jtagspi.c | 2 +-
src/helper/binarybuffer.h | 2 ++
src/jtag/core.c | 2 +-
src/jtag/tcl.c | 2 +-
src/target/arm_jtag.c | 4 ++--
src/target/avr32_jtag.c | 2 +-
src/target/esirisc_jtag.c | 2 +-
src/target/etb.c | 12 ++++++------
src/target/etm.c | 8 ++++----
src/target/ls1_sap.c | 4 ++--
src/target/mips_ejtag.c | 6 +++---
src/target/openrisc/or1k_tap_vjtag.c | 2 +-
src/target/riscv/riscv-011.c | 4 ++--
src/target/riscv/riscv-013.c | 3 ++-
src/target/riscv/riscv.c | 8 ++++----
src/target/xscale.c | 14 +++++++-------
16 files changed, 40 insertions(+), 37 deletions(-)
hooks/post-receive
--
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|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-07 15:30:38
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 4e981bc27c36e696dc8ace3ab4bab534564770c1 (commit)
via 2ebedbdf383601104ed441dda19e107a76cdf248 (commit)
from b07604cc6aacc5591afd281e0d65ab27280f19b4 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 4e981bc27c36e696dc8ace3ab4bab534564770c1
Author: Tomas Vanek <va...@fb...>
Date: Fri Dec 20 23:43:13 2019 +0100
target/arm920t: fix clang static analyzer warning
Change-Id: I570dfb8b20a3f187f1fe660343cf0b75691e2c30
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: http://openocd.zylin.com/5375
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 2ecf218fd..3ddd19888 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -484,7 +484,7 @@ int arm920t_post_debug_entry(struct target *target)
/* EXPORTED to FA256 */
void arm920t_pre_restore_context(struct target *target)
{
- uint32_t cp15c15;
+ uint32_t cp15c15 = 0;
struct arm920t_common *arm920t = target_to_arm920(target);
/* restore i/d fault status and address register */
commit 2ebedbdf383601104ed441dda19e107a76cdf248
Author: Tomas Vanek <va...@fb...>
Date: Fri Dec 20 23:35:12 2019 +0100
rtos/linux: fix use of memory after it is freed
Discovered by clang static analyzer
Change-Id: I9f64a67f281b95562d8fd6e2ebb0ae3f79ae8039
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: http://openocd.zylin.com/5371
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/src/rtos/linux.c b/src/rtos/linux.c
index 74172b70a..9e59c41a5 100644
--- a/src/rtos/linux.c
+++ b/src/rtos/linux.c
@@ -621,17 +621,17 @@ struct threads *liste_del_task(struct threads *task_list, struct threads **t,
struct threads *prev)
{
LOG_INFO("del task %" PRId64, (*t)->threadid);
- prev->next = (*t)->next;
-
- if (prev == task_list)
- task_list = prev;
+ if (prev)
+ prev->next = (*t)->next;
+ else
+ task_list = (*t)->next;
/* free content of threads */
if ((*t)->context)
free((*t)->context);
free(*t);
- *t = prev;
+ *t = prev ? prev : task_list;
return task_list;
}
@@ -725,6 +725,7 @@ int linux_get_tasks(struct target *target, int context)
/* check that this thread is not one the current threads already
* created */
+ uint32_t base_addr;
#ifdef PID_CHECK
if (!current_pid(linux_os, t->pid)) {
@@ -745,12 +746,13 @@ int linux_get_tasks(struct target *target, int context)
t->context =
cpu_context_read(target, t->base_addr,
&t->thread_info_addr);
+ base_addr = next_task(target, t);
} else {
/*LOG_INFO("thread %s is a current thread already created",t->name); */
+ base_addr = next_task(target, t);
free(t);
}
- uint32_t base_addr = next_task(target, t);
t = calloc(1, sizeof(struct threads));
t->base_addr = base_addr;
}
@@ -1178,7 +1180,7 @@ int linux_gdb_T_packet(struct connection *connection,
if (linux_os->threads_needs_update == 0) {
struct threads *temp = linux_os->thread_list;
- struct threads *prev = linux_os->thread_list;
+ struct threads *prev = NULL;
while (temp != NULL) {
if (temp->threadid == threadid) {
-----------------------------------------------------------------------
Summary of changes:
src/rtos/linux.c | 16 +++++++++-------
src/target/arm920t.c | 2 +-
2 files changed, 10 insertions(+), 8 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-07 15:29:52
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via b07604cc6aacc5591afd281e0d65ab27280f19b4 (commit)
via 6ff852e415fe4ffaab793e5f4fe6f68e3e7fa452 (commit)
via c84f75de81ecd70afad0dd66dedd9daa27421fe0 (commit)
from e1051e1090d4dce0e45d428345015af285a21d7e (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit b07604cc6aacc5591afd281e0d65ab27280f19b4
Author: Tomas Vanek <va...@fb...>
Date: Fri Dec 20 23:33:55 2019 +0100
jtag/drivers/openjtag: fix clang static analyzer warnings
Change-Id: I900ce8157b3e220a4647871080bb9abc772446d1
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: http://openocd.zylin.com/5369
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/src/jtag/drivers/openjtag.c b/src/jtag/drivers/openjtag.c
index 7b07813d8..6131df914 100644
--- a/src/jtag/drivers/openjtag.c
+++ b/src/jtag/drivers/openjtag.c
@@ -229,7 +229,7 @@ static int openjtag_buf_write_standard(
return ERROR_JTAG_DEVICE_ERROR;
}
- *bytes_written += retval;
+ *bytes_written = retval;
return ERROR_OK;
}
@@ -652,7 +652,6 @@ static void openjtag_add_scan(uint8_t *buffer, int length, struct scan_command *
/* whole byte */
/* bits to transfer */
- bits = 7;
command |= (7 << 5);
length -= 8;
}
@@ -690,7 +689,7 @@ static void openjtag_execute_sleep(struct jtag_command *cmd)
static void openjtag_set_state(uint8_t openocd_state)
{
- int8_t state = openjtag_get_tap_state(openocd_state);
+ uint8_t state = openjtag_get_tap_state(openocd_state);
uint8_t buf = 0;
buf = 0x01;
commit 6ff852e415fe4ffaab793e5f4fe6f68e3e7fa452
Author: Tomas Vanek <va...@fb...>
Date: Fri Dec 20 23:32:37 2019 +0100
jtag/aice: fix clang static analyzer warnings
Change-Id: I6c801c2406cd117f2bcf930a5b329c441ab5f1ff
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: http://openocd.zylin.com/5368
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/src/jtag/aice/aice_transport.c b/src/jtag/aice/aice_transport.c
index 15ebcac97..682c6698a 100644
--- a/src/jtag/aice/aice_transport.c
+++ b/src/jtag/aice/aice_transport.c
@@ -47,6 +47,7 @@ static int jim_newtap_expected_id(Jim_Nvp *n, Jim_GetOptInfo *goi,
return JIM_ERR;
}
+ assert(pTap->expected_ids);
memcpy(new_expected_ids, pTap->expected_ids, expected_len);
new_expected_ids[pTap->expected_ids_cnt] = w;
diff --git a/src/jtag/aice/aice_usb.c b/src/jtag/aice/aice_usb.c
index 5fefdd0b4..a5cccfef4 100644
--- a/src/jtag/aice/aice_usb.c
+++ b/src/jtag/aice/aice_usb.c
@@ -484,7 +484,9 @@ static int aice_usb_packet_flush(void)
i = 0;
while (1) {
- aice_read_ctrl(AICE_READ_CTRL_BATCH_STATUS, &batch_status);
+ int retval = aice_read_ctrl(AICE_READ_CTRL_BATCH_STATUS, &batch_status);
+ if (retval != ERROR_OK)
+ return retval;
if (batch_status & 0x1)
return ERROR_OK;
@@ -1797,8 +1799,8 @@ static int aice_write_reg(uint32_t coreid, uint32_t num, uint32_t val);
static int check_suppressed_exception(uint32_t coreid, uint32_t dbger_value)
{
- uint32_t ir4_value;
- uint32_t ir6_value;
+ uint32_t ir4_value = 0;
+ uint32_t ir6_value = 0;
/* the default value of handling_suppressed_exception is false */
static bool handling_suppressed_exception;
@@ -1852,7 +1854,7 @@ static int check_privilege(uint32_t coreid, uint32_t dbger_value)
static int aice_check_dbger(uint32_t coreid, uint32_t expect_status)
{
uint32_t i = 0;
- uint32_t value_dbger;
+ uint32_t value_dbger = 0;
while (1) {
aice_read_misc(coreid, NDS_EDM_MISC_DBGER, &value_dbger);
@@ -1973,7 +1975,7 @@ static int aice_read_reg(uint32_t coreid, uint32_t num, uint32_t *val)
aice_execute_dim(coreid, instructions, 4);
- uint32_t value_edmsw;
+ uint32_t value_edmsw = 0;
aice_read_edmsr(coreid, NDS_EDM_SR_EDMSW, &value_edmsw);
if (value_edmsw & NDS_EDMSW_WDV)
aice_read_dtr(coreid, val);
@@ -2018,7 +2020,7 @@ static int aice_write_reg(uint32_t coreid, uint32_t num, uint32_t val)
LOG_DEBUG("aice_write_reg, reg_no: 0x%08" PRIx32 ", value: 0x%08" PRIx32, num, val);
uint32_t instructions[4]; /** execute instructions in DIM */
- uint32_t value_edmsw;
+ uint32_t value_edmsw = 0;
aice_write_dtr(coreid, val);
aice_read_edmsr(coreid, NDS_EDM_SR_EDMSW, &value_edmsw);
@@ -2447,7 +2449,7 @@ static int aice_backup_tmp_registers(uint32_t coreid)
LOG_DEBUG("backup_tmp_registers -");
/* backup target DTR first(if the target DTR is valid) */
- uint32_t value_edmsw;
+ uint32_t value_edmsw = 0;
aice_read_edmsr(coreid, NDS_EDM_SR_EDMSW, &value_edmsw);
core_info[coreid].edmsw_backup = value_edmsw;
if (value_edmsw & 0x1) { /* EDMSW.WDV == 1 */
@@ -2614,13 +2616,13 @@ static int aice_usb_halt(uint32_t coreid)
aice_init_edm_registers(coreid, false);
/** Clear EDM_CTL.DBGIM & EDM_CTL.DBGACKM */
- uint32_t edm_ctl_value;
+ uint32_t edm_ctl_value = 0;
aice_read_edmsr(coreid, NDS_EDM_SR_EDM_CTL, &edm_ctl_value);
if (edm_ctl_value & 0x3)
aice_write_edmsr(coreid, NDS_EDM_SR_EDM_CTL, edm_ctl_value & ~(0x3));
- uint32_t dbger;
- uint32_t acc_ctl_value;
+ uint32_t dbger = 0;
+ uint32_t acc_ctl_value = 0;
core_info[coreid].debug_under_dex_on = false;
aice_read_misc(coreid, NDS_EDM_MISC_DBGER, &dbger);
@@ -2661,7 +2663,7 @@ static int aice_usb_halt(uint32_t coreid)
* it is only for debugging 'debug exception handler' purpose.
* after openocd detaches from target, target behavior is
* undefined. */
- uint32_t ir0_value;
+ uint32_t ir0_value = 0;
uint32_t debug_mode_ir0_value;
aice_read_reg(coreid, IR0, &ir0_value);
debug_mode_ir0_value = ir0_value | 0x408; /* turn on DEX, set POM = 1 */
@@ -4029,7 +4031,7 @@ static int aice_usb_profiling(uint32_t coreid, uint32_t interval, uint32_t itera
/* check status */
uint32_t i;
- uint32_t batch_status;
+ uint32_t batch_status = 0;
i = 0;
while (1) {
commit c84f75de81ecd70afad0dd66dedd9daa27421fe0
Author: Tomas Vanek <va...@fb...>
Date: Fri Dec 20 23:26:51 2019 +0100
flash/nor/numicro: use flash infrastructure to align write
The aligning code generated a clang static analyzer warning and
imposed huge memory leak. This part of code was removed and
flash infrastructure to alignment is used instead.
Not tested on hw!
Change-Id: I7c71da87547e71d595a7e7071ae5adcc1cecc827
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: http://openocd.zylin.com/5367
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/src/flash/nor/numicro.c b/src/flash/nor/numicro.c
index c6dbfb851..a4852829e 100644
--- a/src/flash/nor/numicro.c
+++ b/src/flash/nor/numicro.c
@@ -1548,7 +1548,6 @@ static int numicro_write(struct flash_bank *bank, const uint8_t *buffer,
{
struct target *target = bank->target;
uint32_t timeout, status;
- uint8_t *new_buffer = NULL;
int retval = ERROR_OK;
if (target->state != TARGET_HALTED) {
@@ -1566,20 +1565,8 @@ static int numicro_write(struct flash_bank *bank, const uint8_t *buffer,
if (retval != ERROR_OK)
return retval;
- if (count & 0x3) {
- uint32_t old_count = count;
- count = (old_count | 3) + 1;
- new_buffer = malloc(count);
- if (new_buffer == NULL) {
- LOG_ERROR("odd number of bytes to write and no memory "
- "for padding buffer");
- return ERROR_FAIL;
- }
- LOG_INFO("odd number of bytes to write (%d), extending to %d "
- "and padding with 0xff", old_count, count);
- memset(new_buffer, 0xff, count);
- buffer = memcpy(new_buffer, buffer, old_count);
- }
+ assert(offset % 4 == 0);
+ assert(count % 4 == 0);
uint32_t words_remaining = count / 4;
@@ -1597,13 +1584,10 @@ static int numicro_write(struct flash_bank *bank, const uint8_t *buffer,
LOG_DEBUG("write longword @ %08X", offset + i);
- uint8_t padding[4] = {0xff, 0xff, 0xff, 0xff};
- memcpy(padding, buffer + i, MIN(4, count-i));
-
retval = target_write_u32(target, NUMICRO_FLASH_ISPADR, bank->base + offset + i);
if (retval != ERROR_OK)
return retval;
- retval = target_write_memory(target, NUMICRO_FLASH_ISPDAT, 4, 1, padding);
+ retval = target_write_memory(target, NUMICRO_FLASH_ISPDAT, 4, 1, buffer + i);
if (retval != ERROR_OK)
return retval;
retval = target_write_u32(target, NUMICRO_FLASH_ISPTRG, ISPTRG_ISPGO);
@@ -1754,6 +1738,7 @@ FLASH_BANK_COMMAND_HANDLER(numicro_flash_bank_command)
memset(bank_info, 0, sizeof(struct numicro_flash_bank));
bank->driver_priv = bank_info;
+ bank->write_start_alignment = bank->write_end_alignment = 4;
return ERROR_OK;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/numicro.c | 23 ++++-------------------
src/jtag/aice/aice_transport.c | 1 +
src/jtag/aice/aice_usb.c | 26 ++++++++++++++------------
src/jtag/drivers/openjtag.c | 5 ++---
4 files changed, 21 insertions(+), 34 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-07 15:29:24
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via e1051e1090d4dce0e45d428345015af285a21d7e (commit)
via b8524295002076a3f0e9e2211298a69a6ba9d858 (commit)
from 122c80087c3e66ecf5122d99081bcd83ab08fddc (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit e1051e1090d4dce0e45d428345015af285a21d7e
Author: Tomas Vanek <va...@fb...>
Date: Fri Dec 20 23:23:26 2019 +0100
flash/nor/fm4,tms470: fix clang static analyzer warnings
Change-Id: I18c1501918d40453fea6aeeb6f035e46d41fc524
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: http://openocd.zylin.com/5366
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/src/flash/nor/fm4.c b/src/flash/nor/fm4.c
index a8877b4fb..7e3a1c51f 100644
--- a/src/flash/nor/fm4.c
+++ b/src/flash/nor/fm4.c
@@ -207,7 +207,7 @@ static int fm4_flash_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t halfword_count = DIV_ROUND_UP(byte_count, 2);
uint32_t result;
unsigned i;
- int retval;
+ int retval, retval2 = ERROR_OK;
const uint8_t write_block_code[] = {
#include "../../../contrib/loaders/flash/fm4/write.inc"
};
@@ -327,7 +327,7 @@ static int fm4_flash_write(struct flash_bank *bank, const uint8_t *buffer,
err_run_ret:
err_run:
err_write_data:
- retval = fm4_enter_flash_cpu_rom_mode(target);
+ retval2 = fm4_enter_flash_cpu_rom_mode(target);
err_flash_mode:
for (i = 0; i < ARRAY_SIZE(reg_params); i++)
@@ -338,7 +338,9 @@ err_alloc_data:
err_write_code:
target_free_working_area(target, code_workarea);
- return retval;
+ if (retval != ERROR_OK)
+ return retval;
+ return retval2;
}
static int mb9bf_probe(struct flash_bank *bank)
diff --git a/src/flash/nor/tms470.c b/src/flash/nor/tms470.c
index 90557b8f1..bc16acab5 100644
--- a/src/flash/nor/tms470.c
+++ b/src/flash/nor/tms470.c
@@ -709,6 +709,7 @@ static int tms470_erase_sector(struct flash_bank *bank, int sector)
* Select one or more bits in FMBSEA or FMBSEB to disable Level 1
* protection for the particular sector to be erased/written.
*/
+ assert(sector >= 0);
if (sector < 16) {
target_read_u32(target, 0xFFE88008, &fmbsea);
target_write_u32(target, 0xFFE88008, fmbsea | (1 << sector));
commit b8524295002076a3f0e9e2211298a69a6ba9d858
Author: Tomas Vanek <va...@fb...>
Date: Fri Dec 20 23:18:37 2019 +0100
src/flash/nor/at91sam3|4l|7: fix clang static analyzer warnings
Change-Id: I5cd2b2ebb2bd1980bdd1632b5c35bda9718a1089
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: http://openocd.zylin.com/5365
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index 2457c15f3..af0b50b49 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -3653,7 +3653,8 @@ showall:
}
if ((who >= 0) && (((unsigned)(who)) < pChip->details.n_gpnvms)) {
r = FLASHD_GetGPNVM(&(pChip->details.bank[0]), who, &v);
- command_print(CMD, "sam3-gpnvm%u: %u", who, v);
+ if (r == ERROR_OK)
+ command_print(CMD, "sam3-gpnvm%u: %u", who, v);
return r;
} else {
command_print(CMD, "sam3-gpnvm invalid GPNVM: %u", who);
diff --git a/src/flash/nor/at91sam4l.c b/src/flash/nor/at91sam4l.c
index d356398dc..d4bfe5310 100644
--- a/src/flash/nor/at91sam4l.c
+++ b/src/flash/nor/at91sam4l.c
@@ -601,6 +601,7 @@ static int sam4l_write(struct flash_bank *bank, const uint8_t *buffer,
/* There's at least one aligned page to write out. */
if (count >= chip->page_size) {
+ assert(chip->page_size > 0);
int np = count / chip->page_size + ((count % chip->page_size) ? 1 : 0);
for (int i = 0; i < np; i++) {
diff --git a/src/flash/nor/at91sam7.c b/src/flash/nor/at91sam7.c
index 232260b93..039746c16 100644
--- a/src/flash/nor/at91sam7.c
+++ b/src/flash/nor/at91sam7.c
@@ -711,8 +711,6 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
uint16_t page_size;
uint16_t num_nvmbits;
- char *target_name_t;
-
int bnk, sec;
at91sam7_info = malloc(sizeof(struct at91sam7_flash_bank));
@@ -753,9 +751,6 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
return ERROR_OK;
}
- target_name_t = calloc(strlen(CMD_ARGV[7]) + 1, sizeof(char));
- strcpy(target_name_t, CMD_ARGV[7]);
-
/* calculate bank size */
bank_size = num_sectors * pages_per_sector * page_size;
@@ -794,7 +789,7 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
at91sam7_info = t_bank->driver_priv;
- at91sam7_info->target_name = target_name_t;
+ at91sam7_info->target_name = strdup(CMD_ARGV[7]);
at91sam7_info->flashmode = 0;
at91sam7_info->ext_freq = ext_freq;
at91sam7_info->num_nvmbits = num_nvmbits;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/at91sam3.c | 3 ++-
src/flash/nor/at91sam4l.c | 1 +
src/flash/nor/at91sam7.c | 7 +------
src/flash/nor/fm4.c | 8 +++++---
src/flash/nor/tms470.c | 1 +
5 files changed, 10 insertions(+), 10 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-07 15:28:54
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 122c80087c3e66ecf5122d99081bcd83ab08fddc (commit)
from 51dd4ce6bbc3c6f200001640f2cb1638b5185cb7 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 122c80087c3e66ecf5122d99081bcd83ab08fddc
Author: Marc Schink <de...@za...>
Date: Tue Jan 28 10:53:35 2020 +0100
flash/nor/stm32f1x: Group and cleanup device list
Group device list based on the device family and add clear
device family names.
Change-Id: I7a2dab1d1c0c8d141df02656c1964cb2c3fcbcd1
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5423
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index ba0d54e79..7d5a8f0a2 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -713,31 +713,63 @@ static int stm32x_probe(struct flash_bank *bank)
/* set page size, protection granularity and max flash size depending on family */
switch (device_id & 0xfff) {
- case 0x410: /* medium density */
+ case 0x440: /* stm32f05x */
+ case 0x444: /* stm32f03x */
+ case 0x445: /* stm32f04x */
+ page_size = 1024;
+ stm32x_info->ppage_size = 4;
+ max_flash_size_in_kb = 64;
+ stm32x_info->user_data_offset = 16;
+ stm32x_info->option_offset = 6;
+ stm32x_info->default_rdp = 0xAA;
+ stm32x_info->can_load_options = true;
+ break;
+ case 0x448: /* stm32f07x */
+ case 0x442: /* stm32f09x */
+ page_size = 2048;
+ stm32x_info->ppage_size = 4;
+ max_flash_size_in_kb = 256;
+ stm32x_info->user_data_offset = 16;
+ stm32x_info->option_offset = 6;
+ stm32x_info->default_rdp = 0xAA;
+ stm32x_info->can_load_options = true;
+ break;
+ case 0x410: /* stm32f1x medium-density */
page_size = 1024;
stm32x_info->ppage_size = 4;
max_flash_size_in_kb = 128;
break;
- case 0x412: /* low density */
+ case 0x412: /* stm32f1x low-density */
page_size = 1024;
stm32x_info->ppage_size = 4;
max_flash_size_in_kb = 32;
break;
- case 0x414: /* high density */
+ case 0x414: /* stm32f1x high-density */
page_size = 2048;
stm32x_info->ppage_size = 2;
max_flash_size_in_kb = 512;
break;
- case 0x418: /* connectivity line density */
+ case 0x418: /* stm32f1x connectivity */
page_size = 2048;
stm32x_info->ppage_size = 2;
max_flash_size_in_kb = 256;
break;
- case 0x420: /* value line density */
+ case 0x430: /* stm32f1 XL-density (dual flash banks) */
+ page_size = 2048;
+ stm32x_info->ppage_size = 2;
+ max_flash_size_in_kb = 1024;
+ stm32x_info->has_dual_banks = true;
+ break;
+ case 0x420: /* stm32f100xx low- and medium-density value line */
page_size = 1024;
stm32x_info->ppage_size = 4;
max_flash_size_in_kb = 128;
break;
+ case 0x428: /* stm32f100xx high-density value line */
+ page_size = 2048;
+ stm32x_info->ppage_size = 4;
+ max_flash_size_in_kb = 128;
+ break;
case 0x422: /* stm32f302/3xb/c */
page_size = 2048;
stm32x_info->ppage_size = 2;
@@ -756,17 +788,6 @@ static int stm32x_probe(struct flash_bank *bank)
stm32x_info->default_rdp = 0xAA;
stm32x_info->can_load_options = true;
break;
- case 0x428: /* value line High density */
- page_size = 2048;
- stm32x_info->ppage_size = 4;
- max_flash_size_in_kb = 128;
- break;
- case 0x430: /* xl line density (dual flash banks) */
- page_size = 2048;
- stm32x_info->ppage_size = 2;
- max_flash_size_in_kb = 1024;
- stm32x_info->has_dual_banks = true;
- break;
case 0x432: /* stm32f37x */
page_size = 2048;
stm32x_info->ppage_size = 2;
@@ -786,27 +807,6 @@ static int stm32x_probe(struct flash_bank *bank)
stm32x_info->default_rdp = 0xAA;
stm32x_info->can_load_options = true;
break;
- case 0x440: /* stm32f05x */
- case 0x444: /* stm32f03x */
- case 0x445: /* stm32f04x */
- page_size = 1024;
- stm32x_info->ppage_size = 4;
- max_flash_size_in_kb = 64;
- stm32x_info->user_data_offset = 16;
- stm32x_info->option_offset = 6;
- stm32x_info->default_rdp = 0xAA;
- stm32x_info->can_load_options = true;
- break;
- case 0x448: /* stm32f07x */
- case 0x442: /* stm32f09x */
- page_size = 2048;
- stm32x_info->ppage_size = 4;
- max_flash_size_in_kb = 256;
- stm32x_info->user_data_offset = 16;
- stm32x_info->option_offset = 6;
- stm32x_info->default_rdp = 0xAA;
- stm32x_info->can_load_options = true;
- break;
default:
LOG_WARNING("Cannot identify target as a STM32 family.");
return ERROR_FAIL;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32f1x.c | 74 ++++++++++++++++++++++++------------------------
1 file changed, 37 insertions(+), 37 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-03 09:12:46
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 51dd4ce6bbc3c6f200001640f2cb1638b5185cb7 (commit)
from 93c6bf2cce5f23e37d4a1dd5136a40e74c69285c (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 51dd4ce6bbc3c6f200001640f2cb1638b5185cb7
Author: Marc Schink <de...@za...>
Date: Wed Feb 5 16:07:48 2020 +0100
drivers: Rename 'libusb1_common' to 'libusb_helper'
The name 'common' does not make sense anymore. While at it,
remove some unnecessary #includes.
Change-Id: If9798a5cce179438d89428a598d8ca05c8e5f20c
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5434
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/src/jtag/aice/aice_interface.c b/src/jtag/aice/aice_interface.c
index f9bd87eeb..90871a138 100644
--- a/src/jtag/aice/aice_interface.c
+++ b/src/jtag/aice/aice_interface.c
@@ -25,7 +25,6 @@
#include <transport/transport.h>
#include <target/target.h>
#include <jtag/aice/aice_transport.h>
-#include <jtag/drivers/libusb_common.h>
#include "aice_usb.h"
#define AICE_KHZ_TO_SPEED_MAP_SIZE 16
diff --git a/src/jtag/aice/aice_usb.c b/src/jtag/aice/aice_usb.c
index 8c3a629a0..5fefdd0b4 100644
--- a/src/jtag/aice/aice_usb.c
+++ b/src/jtag/aice/aice_usb.c
@@ -19,7 +19,7 @@
#include "config.h"
#endif
-#include <jtag/drivers/libusb_common.h>
+#include <jtag/drivers/libusb_helper.h>
#include <helper/log.h>
#include <helper/time_support.h>
#include <target/target.h>
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index 47b19470e..aea09b38c 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -22,7 +22,7 @@ DRIVERFILES += %D%/driver.c
DRIVERFILES += %D%/jtag_usb_common.c
if USE_LIBUSB1
-DRIVERFILES += %D%/libusb1_common.c
+DRIVERFILES += %D%/libusb_helper.c
%C%_libocdjtagdrivers_la_CPPFLAGS += $(LIBUSB1_CFLAGS)
%C%_libocdjtagdrivers_la_LIBADD += $(LIBUSB1_LIBS)
endif
@@ -168,8 +168,7 @@ DRIVERHEADERS = \
%D%/bitbang.h \
%D%/bitq.h \
%D%/jtag_usb_common.h \
- %D%/libusb1_common.h \
- %D%/libusb_common.h \
+ %D%/libusb_helper.h \
%D%/minidriver_imp.h \
%D%/mpsse.h \
%D%/rlink.h \
diff --git a/src/jtag/drivers/ft232r.c b/src/jtag/drivers/ft232r.c
index 8fe63bb35..4812362a3 100644
--- a/src/jtag/drivers/ft232r.c
+++ b/src/jtag/drivers/ft232r.c
@@ -29,7 +29,7 @@
#include <jtag/interface.h>
#include <jtag/commands.h>
#include <helper/time_support.h>
-#include "libusb1_common.h"
+#include "libusb_helper.h"
/* system includes */
#include <string.h>
diff --git a/src/jtag/drivers/kitprog.c b/src/jtag/drivers/kitprog.c
index e26f5aa92..0c1e74c42 100644
--- a/src/jtag/drivers/kitprog.c
+++ b/src/jtag/drivers/kitprog.c
@@ -43,7 +43,7 @@
#include <jtag/swd.h>
#include <jtag/commands.h>
-#include "libusb_common.h"
+#include "libusb_helper.h"
#define VID 0x04b4
#define PID 0xf139
diff --git a/src/jtag/drivers/libusb_common.h b/src/jtag/drivers/libusb_common.h
deleted file mode 100644
index 47aca5d91..000000000
--- a/src/jtag/drivers/libusb_common.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/***************************************************************************
- * Copyright (C) 2011 by Mauro Gamba <mau...@gm...> *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
- ***************************************************************************/
-
-#ifndef OPENOCD_JTAG_DRIVERS_LIBUSB_COMMON_H
-#define OPENOCD_JTAG_DRIVERS_LIBUSB_COMMON_H
-
-#ifdef HAVE_LIBUSB1
-#include "libusb1_common.h"
-#endif
-
-#endif /* OPENOCD_JTAG_DRIVERS_LIBUSB_COMMON_H */
diff --git a/src/jtag/drivers/libusb1_common.c b/src/jtag/drivers/libusb_helper.c
similarity index 99%
rename from src/jtag/drivers/libusb1_common.c
rename to src/jtag/drivers/libusb_helper.c
index 607b6d4aa..5a8129cb9 100644
--- a/src/jtag/drivers/libusb1_common.c
+++ b/src/jtag/drivers/libusb_helper.c
@@ -21,7 +21,7 @@
#include "config.h"
#endif
#include <jtag/drivers/jtag_usb_common.h>
-#include "libusb1_common.h"
+#include "libusb_helper.h"
#include "log.h"
/*
diff --git a/src/jtag/drivers/libusb1_common.h b/src/jtag/drivers/libusb_helper.h
similarity index 95%
rename from src/jtag/drivers/libusb1_common.h
rename to src/jtag/drivers/libusb_helper.h
index b132e26ae..46e4954e7 100644
--- a/src/jtag/drivers/libusb1_common.h
+++ b/src/jtag/drivers/libusb_helper.h
@@ -17,8 +17,8 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
-#ifndef OPENOCD_JTAG_DRIVERS_LIBUSB1_COMMON_H
-#define OPENOCD_JTAG_DRIVERS_LIBUSB1_COMMON_H
+#ifndef OPENOCD_JTAG_DRIVERS_LIBUSB_HELPER_H
+#define OPENOCD_JTAG_DRIVERS_LIBUSB_HELPER_H
#include <libusb.h>
@@ -55,4 +55,4 @@ int jtag_libusb_choose_interface(struct libusb_device_handle *devh,
int bclass, int subclass, int protocol, int trans_type);
int jtag_libusb_get_pid(struct libusb_device *dev, uint16_t *pid);
-#endif /* OPENOCD_JTAG_DRIVERS_LIBUSB1_COMMON_H */
+#endif /* OPENOCD_JTAG_DRIVERS_LIBUSB_HELPER_H */
diff --git a/src/jtag/drivers/opendous.c b/src/jtag/drivers/opendous.c
index 18d954308..7298a2a10 100644
--- a/src/jtag/drivers/opendous.c
+++ b/src/jtag/drivers/opendous.c
@@ -32,7 +32,7 @@
#include <jtag/interface.h>
#include <jtag/commands.h>
-#include "libusb_common.h"
+#include "libusb_helper.h"
#include <string.h>
#include <time.h>
diff --git a/src/jtag/drivers/openjtag.c b/src/jtag/drivers/openjtag.c
index 3bfcccf6e..7b07813d8 100644
--- a/src/jtag/drivers/openjtag.c
+++ b/src/jtag/drivers/openjtag.c
@@ -45,7 +45,7 @@
#include <jtag/interface.h>
#include <jtag/commands.h>
-#include "libusb_common.h"
+#include "libusb_helper.h"
static enum {
OPENJTAG_VARIANT_STANDARD,
diff --git a/src/jtag/drivers/osbdm.c b/src/jtag/drivers/osbdm.c
index 30c46234e..aea126d0d 100644
--- a/src/jtag/drivers/osbdm.c
+++ b/src/jtag/drivers/osbdm.c
@@ -23,7 +23,7 @@
#include <helper/binarybuffer.h>
#include <helper/command.h>
#include <jtag/interface.h>
-#include "libusb_common.h"
+#include "libusb_helper.h"
struct sequence {
int len;
diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c
index a186dfdef..ca7a4df4e 100644
--- a/src/jtag/drivers/stlink_usb.c
+++ b/src/jtag/drivers/stlink_usb.c
@@ -41,7 +41,7 @@
#include <target/cortex_m.h>
-#include "libusb_common.h"
+#include "libusb_helper.h"
#ifdef HAVE_LIBUSB1
#define USE_LIBUSB_ASYNCIO
diff --git a/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c b/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c
index 34fbb8952..4f7ee6300 100644
--- a/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c
+++ b/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c
@@ -23,7 +23,7 @@
#endif
#include <jtag/interface.h>
#include <jtag/commands.h>
-#include <libusb_common.h>
+#include <libusb_helper.h>
#include <target/image.h>
#include "ublast_access.h"
diff --git a/src/jtag/drivers/usb_blaster/ublast_access.h b/src/jtag/drivers/usb_blaster/ublast_access.h
index 5178ae10b..ad20d65d4 100644
--- a/src/jtag/drivers/usb_blaster/ublast_access.h
+++ b/src/jtag/drivers/usb_blaster/ublast_access.h
@@ -28,8 +28,6 @@
#ifndef OPENOCD_JTAG_DRIVERS_USB_BLASTER_UBLAST_ACCESS_H
#define OPENOCD_JTAG_DRIVERS_USB_BLASTER_UBLAST_ACCESS_H
-#include <libusb_common.h>
-
/* Low level flags */
#define COPY_TDO_BUFFER (1 << 0)
-----------------------------------------------------------------------
Summary of changes:
src/jtag/aice/aice_interface.c | 1 -
src/jtag/aice/aice_usb.c | 2 +-
src/jtag/drivers/Makefile.am | 5 ++---
src/jtag/drivers/ft232r.c | 2 +-
src/jtag/drivers/kitprog.c | 2 +-
src/jtag/drivers/libusb_common.h | 25 ----------------------
.../drivers/{libusb1_common.c => libusb_helper.c} | 2 +-
.../drivers/{libusb1_common.h => libusb_helper.h} | 6 +++---
src/jtag/drivers/opendous.c | 2 +-
src/jtag/drivers/openjtag.c | 2 +-
src/jtag/drivers/osbdm.c | 2 +-
src/jtag/drivers/stlink_usb.c | 2 +-
.../drivers/usb_blaster/ublast2_access_libusb.c | 2 +-
src/jtag/drivers/usb_blaster/ublast_access.h | 2 --
14 files changed, 14 insertions(+), 43 deletions(-)
delete mode 100644 src/jtag/drivers/libusb_common.h
rename src/jtag/drivers/{libusb1_common.c => libusb_helper.c} (99%)
rename src/jtag/drivers/{libusb1_common.h => libusb_helper.h} (95%)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-03 07:25:16
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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- Log -----------------------------------------------------------------
commit 93c6bf2cce5f23e37d4a1dd5136a40e74c69285c
Author: Marc Schink <de...@za...>
Date: Wed Feb 5 15:50:31 2020 +0100
drivers: libusb1_common code cleanup
Remove unncessary wrapper functions and 'jtag_' prefixes.
Change-Id: I0fd866ff1e1cf7386c4d58a808dfda2c1c0a1518
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5433
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/src/jtag/aice/aice_usb.c b/src/jtag/aice/aice_usb.c
index 9e4741342..8c3a629a0 100644
--- a/src/jtag/aice/aice_usb.c
+++ b/src/jtag/aice/aice_usb.c
@@ -349,8 +349,8 @@ static void aice_unpack_dthmb(uint8_t *cmd_ack_code, uint8_t *target_id,
/* calls the given usb_bulk_* function, allowing for the data to
* trickle in with some timeouts */
static int usb_bulk_with_retries(
- int (*f)(jtag_libusb_device_handle *, int, char *, int, int, int *),
- jtag_libusb_device_handle *dev, int ep,
+ int (*f)(libusb_device_handle *, int, char *, int, int, int *),
+ libusb_device_handle *dev, int ep,
char *bytes, int size, int timeout, int *transferred)
{
int tries = 3, count = 0;
@@ -369,7 +369,7 @@ static int usb_bulk_with_retries(
return ERROR_OK;
}
-static int wrap_usb_bulk_write(jtag_libusb_device_handle *dev, int ep,
+static int wrap_usb_bulk_write(libusb_device_handle *dev, int ep,
char *buff, int size, int timeout, int *transferred)
{
@@ -379,7 +379,7 @@ static int wrap_usb_bulk_write(jtag_libusb_device_handle *dev, int ep,
return 0;
}
-static inline int usb_bulk_write_ex(jtag_libusb_device_handle *dev, int ep,
+static inline int usb_bulk_write_ex(libusb_device_handle *dev, int ep,
char *bytes, int size, int timeout)
{
int tr = 0;
@@ -389,7 +389,7 @@ static inline int usb_bulk_write_ex(jtag_libusb_device_handle *dev, int ep,
return tr;
}
-static inline int usb_bulk_read_ex(jtag_libusb_device_handle *dev, int ep,
+static inline int usb_bulk_read_ex(struct libusb_device_handle *dev, int ep,
char *bytes, int size, int timeout)
{
int tr = 0;
@@ -2107,7 +2107,7 @@ static int aice_usb_open(struct aice_port_param_s *param)
{
const uint16_t vids[] = { param->vid, 0 };
const uint16_t pids[] = { param->pid, 0 };
- struct jtag_libusb_device_handle *devh;
+ struct libusb_device_handle *devh;
if (jtag_libusb_open(vids, pids, NULL, &devh) != ERROR_OK)
return ERROR_FAIL;
@@ -2125,7 +2125,7 @@ static int aice_usb_open(struct aice_port_param_s *param)
#if IS_WIN32 == 0
- jtag_libusb_reset_device(devh);
+ libusb_reset_device(devh);
#if IS_DARWIN == 0
@@ -2146,8 +2146,8 @@ static int aice_usb_open(struct aice_port_param_s *param)
#endif
/* usb_set_configuration required under win32 */
- jtag_libusb_set_configuration(devh, 0);
- jtag_libusb_claim_interface(devh, 0);
+ libusb_set_configuration(devh, 0);
+ libusb_claim_interface(devh, 0);
unsigned int aice_read_ep;
unsigned int aice_write_ep;
diff --git a/src/jtag/aice/aice_usb.h b/src/jtag/aice/aice_usb.h
index 15cc1f60d..04021de3b 100644
--- a/src/jtag/aice/aice_usb.h
+++ b/src/jtag/aice/aice_usb.h
@@ -93,7 +93,7 @@
struct aice_usb_handler_s {
unsigned int usb_read_ep;
unsigned int usb_write_ep;
- struct jtag_libusb_device_handle *usb_handle;
+ struct libusb_device_handle *usb_handle;
};
struct cache_info {
diff --git a/src/jtag/drivers/ft232r.c b/src/jtag/drivers/ft232r.c
index c20367fc0..8fe63bb35 100644
--- a/src/jtag/drivers/ft232r.c
+++ b/src/jtag/drivers/ft232r.c
@@ -71,7 +71,7 @@
static char *ft232r_serial_desc;
static uint16_t ft232r_vid = 0x0403; /* FTDI */
static uint16_t ft232r_pid = 0x6001; /* FT232R */
-static jtag_libusb_device_handle *adapter;
+static struct libusb_device_handle *adapter;
static uint8_t *ft232r_output;
static size_t ft232r_output_len;
@@ -268,7 +268,7 @@ static int ft232r_init(void)
else /* serial port will be restored after jtag: */
libusb_set_auto_detach_kernel_driver(adapter, 1); /* 1: DONT_DETACH_SIO_MODULE */
- if (jtag_libusb_claim_interface(adapter, 0)) {
+ if (libusb_claim_interface(adapter, 0)) {
LOG_ERROR("unable to claim interface");
return ERROR_JTAG_INIT_FAILED;
}
@@ -330,7 +330,7 @@ static int ft232r_quit(void)
}
}
- if (jtag_libusb_release_interface(adapter, 0) != 0)
+ if (libusb_release_interface(adapter, 0) != 0)
LOG_ERROR("usb release interface failed");
jtag_libusb_close(adapter);
diff --git a/src/jtag/drivers/kitprog.c b/src/jtag/drivers/kitprog.c
index 7b339aa0b..e26f5aa92 100644
--- a/src/jtag/drivers/kitprog.c
+++ b/src/jtag/drivers/kitprog.c
@@ -95,7 +95,7 @@
struct kitprog {
hid_device *hid_handle;
- struct jtag_libusb_device_handle *usb_handle;
+ struct libusb_device_handle *usb_handle;
uint16_t packet_size;
uint16_t packet_index;
uint8_t *packet_buffer;
@@ -311,7 +311,7 @@ static int kitprog_usb_open(void)
}
/* Claim the KitProg Programmer (bulk transfer) interface */
- if (jtag_libusb_claim_interface(kitprog_handle->usb_handle, 1) != ERROR_OK) {
+ if (libusb_claim_interface(kitprog_handle->usb_handle, 1) != ERROR_OK) {
LOG_ERROR("Failed to claim KitProg Programmer (bulk transfer) interface");
return ERROR_FAIL;
}
diff --git a/src/jtag/drivers/libusb1_common.c b/src/jtag/drivers/libusb1_common.c
index 0d4bcbab6..607b6d4aa 100644
--- a/src/jtag/drivers/libusb1_common.c
+++ b/src/jtag/drivers/libusb1_common.c
@@ -125,12 +125,12 @@ static bool string_descriptor_equal(libusb_device_handle *device, uint8_t str_in
int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
const char *serial,
- struct jtag_libusb_device_handle **out)
+ struct libusb_device_handle **out)
{
int cnt, idx, errCode;
int retval = ERROR_FAIL;
bool serial_mismatch = false;
- struct jtag_libusb_device_handle *libusb_handle = NULL;
+ struct libusb_device_handle *libusb_handle = NULL;
if (libusb_init(&jtag_libusb_context) < 0)
return ERROR_FAIL;
@@ -180,7 +180,7 @@ int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
return retval;
}
-void jtag_libusb_close(jtag_libusb_device_handle *dev)
+void jtag_libusb_close(struct libusb_device_handle *dev)
{
/* Close device */
libusb_close(dev);
@@ -188,7 +188,7 @@ void jtag_libusb_close(jtag_libusb_device_handle *dev)
libusb_exit(jtag_libusb_context);
}
-int jtag_libusb_control_transfer(jtag_libusb_device_handle *dev, uint8_t requestType,
+int jtag_libusb_control_transfer(struct libusb_device_handle *dev, uint8_t requestType,
uint8_t request, uint16_t wValue, uint16_t wIndex, char *bytes,
uint16_t size, unsigned int timeout)
{
@@ -203,7 +203,7 @@ int jtag_libusb_control_transfer(jtag_libusb_device_handle *dev, uint8_t request
return transferred;
}
-int jtag_libusb_bulk_write(jtag_libusb_device_handle *dev, int ep, char *bytes,
+int jtag_libusb_bulk_write(struct libusb_device_handle *dev, int ep, char *bytes,
int size, int timeout, int *transferred)
{
int ret;
@@ -220,7 +220,7 @@ int jtag_libusb_bulk_write(jtag_libusb_device_handle *dev, int ep, char *bytes,
return ERROR_OK;
}
-int jtag_libusb_bulk_read(jtag_libusb_device_handle *dev, int ep, char *bytes,
+int jtag_libusb_bulk_read(struct libusb_device_handle *dev, int ep, char *bytes,
int size, int timeout, int *transferred)
{
int ret;
@@ -237,10 +237,10 @@ int jtag_libusb_bulk_read(jtag_libusb_device_handle *dev, int ep, char *bytes,
return ERROR_OK;
}
-int jtag_libusb_set_configuration(jtag_libusb_device_handle *devh,
+int jtag_libusb_set_configuration(struct libusb_device_handle *devh,
int configuration)
{
- struct jtag_libusb_device *udev = jtag_libusb_get_device(devh);
+ struct libusb_device *udev = libusb_get_device(devh);
int retCode = -99;
struct libusb_config_descriptor *config = NULL;
@@ -265,12 +265,12 @@ int jtag_libusb_set_configuration(jtag_libusb_device_handle *devh,
return retCode;
}
-int jtag_libusb_choose_interface(struct jtag_libusb_device_handle *devh,
+int jtag_libusb_choose_interface(struct libusb_device_handle *devh,
unsigned int *usb_read_ep,
unsigned int *usb_write_ep,
int bclass, int subclass, int protocol, int trans_type)
{
- struct jtag_libusb_device *udev = jtag_libusb_get_device(devh);
+ struct libusb_device *udev = libusb_get_device(devh);
const struct libusb_interface *inter;
const struct libusb_interface_descriptor *interdesc;
const struct libusb_endpoint_descriptor *epdesc;
@@ -317,7 +317,7 @@ int jtag_libusb_choose_interface(struct jtag_libusb_device_handle *devh,
return ERROR_FAIL;
}
-int jtag_libusb_get_pid(struct jtag_libusb_device *dev, uint16_t *pid)
+int jtag_libusb_get_pid(struct libusb_device *dev, uint16_t *pid)
{
struct libusb_device_descriptor dev_desc;
diff --git a/src/jtag/drivers/libusb1_common.h b/src/jtag/drivers/libusb1_common.h
index 34be691f5..b132e26ae 100644
--- a/src/jtag/drivers/libusb1_common.h
+++ b/src/jtag/drivers/libusb1_common.h
@@ -22,41 +22,18 @@
#include <libusb.h>
-#define jtag_libusb_device libusb_device
-#define jtag_libusb_device_handle libusb_device_handle
-#define jtag_libusb_device_descriptor libusb_device_descriptor
-#define jtag_libusb_interface libusb_interface
-#define jtag_libusb_interface_descriptor libusb_interface_descriptor
-#define jtag_libusb_endpoint_descriptor libusb_endpoint_descriptor
-#define jtag_libusb_config_descriptor libusb_config_descriptor
-
-#define jtag_libusb_reset_device(dev) libusb_reset_device(dev)
-#define jtag_libusb_get_device(devh) libusb_get_device(devh)
-
-static inline int jtag_libusb_claim_interface(jtag_libusb_device_handle *devh,
- int iface)
-{
- return libusb_claim_interface(devh, iface);
-};
-
-static inline int jtag_libusb_release_interface(jtag_libusb_device_handle *devh,
- int iface)
-{
- return libusb_release_interface(devh, iface);
-}
-
int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
const char *serial,
- struct jtag_libusb_device_handle **out);
-void jtag_libusb_close(jtag_libusb_device_handle *dev);
-int jtag_libusb_control_transfer(jtag_libusb_device_handle *dev,
+ struct libusb_device_handle **out);
+void jtag_libusb_close(struct libusb_device_handle *dev);
+int jtag_libusb_control_transfer(struct libusb_device_handle *dev,
uint8_t requestType, uint8_t request, uint16_t wValue,
uint16_t wIndex, char *bytes, uint16_t size, unsigned int timeout);
-int jtag_libusb_bulk_write(struct jtag_libusb_device_handle *dev, int ep,
+int jtag_libusb_bulk_write(struct libusb_device_handle *dev, int ep,
char *bytes, int size, int timeout, int *transferred);
-int jtag_libusb_bulk_read(struct jtag_libusb_device_handle *dev, int ep,
+int jtag_libusb_bulk_read(struct libusb_device_handle *dev, int ep,
char *bytes, int size, int timeout, int *transferred);
-int jtag_libusb_set_configuration(jtag_libusb_device_handle *devh,
+int jtag_libusb_set_configuration(struct libusb_device_handle *devh,
int configuration);
/**
* Find the first interface optionally matching class, subclass and
@@ -72,10 +49,10 @@ int jtag_libusb_set_configuration(jtag_libusb_device_handle *devh,
* @param trans_type `bmAttributes Bits 0..1 Transfer type` to match, or -1 to ignore this field.
* @returns Returns ERROR_OK on success, ERROR_FAIL otherwise.
*/
-int jtag_libusb_choose_interface(struct jtag_libusb_device_handle *devh,
+int jtag_libusb_choose_interface(struct libusb_device_handle *devh,
unsigned int *usb_read_ep,
unsigned int *usb_write_ep,
int bclass, int subclass, int protocol, int trans_type);
-int jtag_libusb_get_pid(struct jtag_libusb_device *dev, uint16_t *pid);
+int jtag_libusb_get_pid(struct libusb_device *dev, uint16_t *pid);
#endif /* OPENOCD_JTAG_DRIVERS_LIBUSB1_COMMON_H */
diff --git a/src/jtag/drivers/opendous.c b/src/jtag/drivers/opendous.c
index d5c279b08..18d954308 100644
--- a/src/jtag/drivers/opendous.c
+++ b/src/jtag/drivers/opendous.c
@@ -134,7 +134,7 @@ static void opendous_tap_append_scan(int length, uint8_t *buffer, struct scan_co
/* opendous lowlevel functions */
struct opendous_jtag {
- struct jtag_libusb_device_handle *usb_handle;
+ struct libusb_device_handle *usb_handle;
};
static struct opendous_jtag *opendous_usb_open(void);
@@ -714,12 +714,12 @@ struct opendous_jtag *opendous_usb_open(void)
{
struct opendous_jtag *result;
- struct jtag_libusb_device_handle *devh;
+ struct libusb_device_handle *devh;
if (jtag_libusb_open(opendous_probe->VID, opendous_probe->PID, NULL, &devh) != ERROR_OK)
return NULL;
jtag_libusb_set_configuration(devh, 0);
- jtag_libusb_claim_interface(devh, 0);
+ libusb_claim_interface(devh, 0);
result = malloc(sizeof(*result));
result->usb_handle = devh;
diff --git a/src/jtag/drivers/openjtag.c b/src/jtag/drivers/openjtag.c
index c42b620bb..3bfcccf6e 100644
--- a/src/jtag/drivers/openjtag.c
+++ b/src/jtag/drivers/openjtag.c
@@ -111,7 +111,7 @@ static uint8_t usb_rx_buf[OPENJTAG_BUFFER_SIZE];
static struct openjtag_scan_result openjtag_scan_result_buffer[OPENJTAG_MAX_PENDING_RESULTS];
static int openjtag_scan_result_count;
-static jtag_libusb_device_handle *usbh;
+static struct libusb_device_handle *usbh;
/* CY7C65215 model only */
#define CY7C65215_JTAG_REQUEST 0x40 /* bmRequestType: vendor host-to-device */
diff --git a/src/jtag/drivers/osbdm.c b/src/jtag/drivers/osbdm.c
index 3323557b7..30c46234e 100644
--- a/src/jtag/drivers/osbdm.c
+++ b/src/jtag/drivers/osbdm.c
@@ -132,7 +132,7 @@ static const uint16_t osbdm_vid[] = { 0x15a2, 0x15a2, 0x15a2, 0 };
static const uint16_t osbdm_pid[] = { 0x0042, 0x0058, 0x005e, 0 };
struct osbdm {
- struct jtag_libusb_device_handle *devh; /* USB handle */
+ struct libusb_device_handle *devh; /* USB handle */
uint8_t buffer[OSBDM_USB_BUFSIZE]; /* Data to send and receive */
int count; /* Count data to send and to read */
};
@@ -377,7 +377,7 @@ static int osbdm_open(struct osbdm *osbdm)
if (jtag_libusb_open(osbdm_vid, osbdm_pid, NULL, &osbdm->devh) != ERROR_OK)
return ERROR_FAIL;
- if (jtag_libusb_claim_interface(osbdm->devh, 0) != ERROR_OK)
+ if (libusb_claim_interface(osbdm->devh, 0) != ERROR_OK)
return ERROR_FAIL;
return ERROR_OK;
diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c
index da1d1b564..a186dfdef 100644
--- a/src/jtag/drivers/stlink_usb.c
+++ b/src/jtag/drivers/stlink_usb.c
@@ -111,7 +111,7 @@ struct stlink_usb_version {
/** */
struct stlink_usb_handle_s {
/** */
- struct jtag_libusb_device_handle *fd;
+ struct libusb_device_handle *fd;
/** */
struct libusb_transfer *trans;
/** */
@@ -451,7 +451,7 @@ struct jtag_xfer {
};
static int jtag_libusb_bulk_transfer_n(
- jtag_libusb_device_handle * dev_handle,
+ struct libusb_device_handle *dev_handle,
struct jtag_xfer *transfers,
size_t n_transfers,
int timeout)
@@ -2785,7 +2785,7 @@ static int stlink_usb_open(struct hl_interface_param_s *param, void **fd)
jtag_libusb_set_configuration(h->fd, 0);
- if (jtag_libusb_claim_interface(h->fd, 0) != ERROR_OK) {
+ if (libusb_claim_interface(h->fd, 0) != ERROR_OK) {
LOG_DEBUG("claim interface failed");
goto error_open;
}
@@ -2794,7 +2794,7 @@ static int stlink_usb_open(struct hl_interface_param_s *param, void **fd)
h->rx_ep = STLINK_RX_EP;
uint16_t pid;
- if (jtag_libusb_get_pid(jtag_libusb_get_device(h->fd), &pid) != ERROR_OK) {
+ if (jtag_libusb_get_pid(libusb_get_device(h->fd), &pid) != ERROR_OK) {
LOG_DEBUG("libusb_get_pid failed");
goto error_open;
}
@@ -2838,13 +2838,13 @@ static int stlink_usb_open(struct hl_interface_param_s *param, void **fd)
LOG_ERROR("read version failed");
goto error_open;
} else {
- err = jtag_libusb_release_interface(h->fd, 0);
+ err = libusb_release_interface(h->fd, 0);
if (err != ERROR_OK) {
LOG_ERROR("release interface failed");
goto error_open;
}
- err = jtag_libusb_reset_device(h->fd);
+ err = libusb_reset_device(h->fd);
if (err != ERROR_OK) {
LOG_ERROR("reset device failed");
goto error_open;
diff --git a/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c b/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c
index fb1e4440a..34fbb8952 100644
--- a/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c
+++ b/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c
@@ -72,7 +72,7 @@ static int ublast2_libusb_write(struct ublast_lowlevel *low, uint8_t *buf,
}
-static int ublast2_write_firmware_section(struct jtag_libusb_device_handle *libusb_dev,
+static int ublast2_write_firmware_section(struct libusb_device_handle *libusb_dev,
struct image *firmware_image, int section_index)
{
uint16_t chunk_size;
@@ -123,7 +123,7 @@ static int ublast2_write_firmware_section(struct jtag_libusb_device_handle *libu
return ERROR_OK;
}
-static int load_usb_blaster_firmware(struct jtag_libusb_device_handle *libusb_dev,
+static int load_usb_blaster_firmware(struct libusb_device_handle *libusb_dev,
struct ublast_lowlevel *low)
{
struct image ublast2_firmware_image;
@@ -191,7 +191,7 @@ static int ublast2_libusb_init(struct ublast_lowlevel *low)
{
const uint16_t vids[] = { low->ublast_vid_uninit, 0 };
const uint16_t pids[] = { low->ublast_pid_uninit, 0 };
- struct jtag_libusb_device_handle *temp;
+ struct libusb_device_handle *temp;
bool renumeration = false;
int ret;
diff --git a/src/jtag/drivers/usb_blaster/ublast_access.h b/src/jtag/drivers/usb_blaster/ublast_access.h
index 252f003a9..5178ae10b 100644
--- a/src/jtag/drivers/usb_blaster/ublast_access.h
+++ b/src/jtag/drivers/usb_blaster/ublast_access.h
@@ -39,7 +39,7 @@ struct ublast_lowlevel {
uint16_t ublast_vid_uninit;
uint16_t ublast_pid_uninit;
char *ublast_device_desc;
- struct jtag_libusb_device_handle *libusb_dev;
+ struct libusb_device_handle *libusb_dev;
char *firmware_path;
int (*write)(struct ublast_lowlevel *low, uint8_t *buf, int size,
-----------------------------------------------------------------------
Summary of changes:
src/jtag/aice/aice_usb.c | 18 +++++-----
src/jtag/aice/aice_usb.h | 2 +-
src/jtag/drivers/ft232r.c | 6 ++--
src/jtag/drivers/kitprog.c | 4 +--
src/jtag/drivers/libusb1_common.c | 22 ++++++------
src/jtag/drivers/libusb1_common.h | 39 +++++-----------------
src/jtag/drivers/opendous.c | 6 ++--
src/jtag/drivers/openjtag.c | 2 +-
src/jtag/drivers/osbdm.c | 4 +--
src/jtag/drivers/stlink_usb.c | 12 +++----
.../drivers/usb_blaster/ublast2_access_libusb.c | 6 ++--
src/jtag/drivers/usb_blaster/ublast_access.h | 2 +-
12 files changed, 50 insertions(+), 73 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-03 06:50:48
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 8ce51b6a207e8cefdf5b6cb06d3c57d1cbef5a99 (commit)
from 8abe91cff960709ffd3ebbb9eb1dcf710dd83c1f (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 8ce51b6a207e8cefdf5b6cb06d3c57d1cbef5a99
Author: Marek Vasut <mar...@gm...>
Date: Tue Jan 7 22:53:28 2020 +0100
tcl/target: Drop old Renesas Gen2 SoC configs
Drop old Renesas Gen2 SoC configurations, as they were superseded by
the new unified config.
Change-Id: I7c2ccbdc13b01a552ce9cafdc1538f226beaa9f2
Signed-off-by: Marek Vasut <mar...@gm...>
Reviewed-on: http://openocd.zylin.com/5399
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/tcl/target/renesas_r8a7790.cfg b/tcl/target/renesas_r8a7790.cfg
deleted file mode 100644
index a662b6b37..000000000
--- a/tcl/target/renesas_r8a7790.cfg
+++ /dev/null
@@ -1,36 +0,0 @@
-# Renesas R-Car H2
-# https://www.renesas.com/en-us/solutions/automotive/products/rcar-h2.html
-
-if { [info exists DAP_TAPID] } {
- set _DAP_TAPID $DAP_TAPID
-} else {
- set _DAP_TAPID 0x4ba00477
-}
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME r8a7790
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
-
-# Configuring only one core using DAP.
-# Base addresses of Cortex A15 cores:
-# core 0 - 0x800B0000
-# core 1 - 0x800B2000
-# core 2 - 0x800B4000
-# core 3 - 0x800B6000
-# Base addresses of Cortex A7 cores (not supported yet):
-# core 0 - 0x800F0000
-# core 1 - 0x800F2000
-# core 2 - 0x800F4000
-# core 3 - 0x800F6000
-set _TARGETNAME $_CHIPNAME.ca15.
-dap create ${_CHIPNAME}.dap -chain-position $_CHIPNAME.cpu
-target create ${_TARGETNAME}0 cortex_a -dap ${_CHIPNAME}.dap -coreid 0 -dbgbase 0x800B0000
-target create ${_TARGETNAME}1 cortex_a -dap ${_CHIPNAME}.dap -coreid 1 -dbgbase 0x800B2000 -defer-examine
-target create ${_TARGETNAME}2 cortex_a -dap ${_CHIPNAME}.dap -coreid 2 -dbgbase 0x800B4000 -defer-examine
-target create ${_TARGETNAME}3 cortex_a -dap ${_CHIPNAME}.dap -coreid 3 -dbgbase 0x800B6000 -defer-examine
-
-targets ${_TARGETNAME}0
diff --git a/tcl/target/renesas_r8a7791.cfg b/tcl/target/renesas_r8a7791.cfg
deleted file mode 100644
index f93cbb8f1..000000000
--- a/tcl/target/renesas_r8a7791.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-# Renesas R-Car M2
-# https://www.renesas.com/en-us/solutions/automotive/products/rcar-m2.html
-
-if { [info exists DAP_TAPID] } {
- set _DAP_TAPID $DAP_TAPID
-} else {
- set _DAP_TAPID 0x4ba00477
-}
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME r8a7791
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
-
-# Configuring only one core using DAP.
-# Base addresses of cores:
-# core 0 - 0x800B0000
-# core 1 - 0x800B2000
-set _TARGETNAME $_CHIPNAME.ca15.
-dap create ${_CHIPNAME}.dap -chain-position $_CHIPNAME.cpu
-target create ${_TARGETNAME}0 cortex_a -dap ${_CHIPNAME}.dap -coreid 0 -dbgbase 0x800B0000
-target create ${_TARGETNAME}1 cortex_a -dap ${_CHIPNAME}.dap -coreid 1 -dbgbase 0x800B2000 -defer-examine
-
-targets ${_TARGETNAME}0
diff --git a/tcl/target/renesas_r8a7794.cfg b/tcl/target/renesas_r8a7794.cfg
deleted file mode 100644
index e3e27246c..000000000
--- a/tcl/target/renesas_r8a7794.cfg
+++ /dev/null
@@ -1,27 +0,0 @@
-# Renesas R-Car E2
-# https://www.renesas.com/en-us/solutions/automotive/products/rcar-e2.html
-
-if { [info exists DAP_TAPID] } {
- set _DAP_TAPID $DAP_TAPID
-} else {
- set _DAP_TAPID 0x4ba00477
-}
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME r8a7794
-}
-
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
-
-# Configuring only one core using DAP.
-# Base addresses of cores:
-# core 0 - 0x800F0000
-# core 1 - 0x800F2000
-set _TARGETNAME $_CHIPNAME.ca7.
-dap create ${_CHIPNAME}.dap -chain-position $_CHIPNAME.cpu
-target create ${_TARGETNAME}0 cortex_a -dap ${_CHIPNAME}.dap -coreid 0 -dbgbase 0x800F0000
-target create ${_TARGETNAME}1 cortex_a -dap ${_CHIPNAME}.dap -coreid 1 -dbgbase 0x800F2000 -defer-examine
-
-targets ${_TARGETNAME}0
-----------------------------------------------------------------------
Summary of changes:
tcl/target/renesas_r8a7790.cfg | 36 ------------------------------------
tcl/target/renesas_r8a7791.cfg | 27 ---------------------------
tcl/target/renesas_r8a7794.cfg | 27 ---------------------------
3 files changed, 90 deletions(-)
delete mode 100644 tcl/target/renesas_r8a7790.cfg
delete mode 100644 tcl/target/renesas_r8a7791.cfg
delete mode 100644 tcl/target/renesas_r8a7794.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-03 06:49:36
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 8abe91cff960709ffd3ebbb9eb1dcf710dd83c1f (commit)
from a01474bb4c4c43a2d10781668efa26e6774364ed (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 8abe91cff960709ffd3ebbb9eb1dcf710dd83c1f
Author: Oleksij Rempel <li...@re...>
Date: Mon Feb 3 19:44:40 2020 +0100
remove libusb0_common support
Supporting two libusb versions provides additional development challenges
without additional advantage. In most cases we need to patch libusb0_common and
libusb1_common without real ability to test libusb0_common.
Change-Id: Icbb19c6809b14533fe2acf7a877377b3be4cbd61
Signed-off-by: Oleksij Rempel <li...@re...>
Reviewed-on: http://openocd.zylin.com/5432
Tested-by: jenkins
diff --git a/configure.ac b/configure.ac
index e87959c04..497b15fd1 100644
--- a/configure.ac
+++ b/configure.ac
@@ -116,10 +116,8 @@ m4_define([USB1_ADAPTERS],
[[usb_blaster_2], [Altera USB-Blaster II Compatible], [USB_BLASTER_2]],
[[ft232r], [Bitbang mode of FT232R based devices], [FT232R]],
[[vsllink], [Versaloon-Link JTAG Programmer], [VSLLINK]],
- [[xds110], [TI XDS110 Debug Probe], [XDS110]]])
-
-m4_define([USB_ADAPTERS],
- [[[osbdm], [OSBDM (JTAG only) Programmer], [OSBDM]],
+ [[xds110], [TI XDS110 Debug Probe], [XDS110]],
+ [[osbdm], [OSBDM (JTAG only) Programmer], [OSBDM]],
[[opendous], [eStick/opendous JTAG Programmer], [OPENDOUS]],
[[aice], [Andes JTAG Programmer], [AICE]]])
@@ -235,7 +233,6 @@ m4_define([AC_ARG_ADAPTERS], [
AC_ARG_ADAPTERS([
USB1_ADAPTERS,
- USB_ADAPTERS,
USB0_ADAPTERS,
HIDAPI_ADAPTERS,
HIDAPI_USB1_ADAPTERS,
@@ -665,7 +662,6 @@ m4_define([PROCESS_ADAPTERS], [
])
PROCESS_ADAPTERS([USB1_ADAPTERS], ["x$use_libusb1" = "xyes"], [libusb-1.x])
-PROCESS_ADAPTERS([USB_ADAPTERS], ["x$use_libusb1" = "xyes" -o "x$use_libusb0" = "xyes"], [libusb-1.x or libusb-0.1])
PROCESS_ADAPTERS([USB0_ADAPTERS], ["x$use_libusb0" = "xyes"], [libusb-0.1])
PROCESS_ADAPTERS([HIDAPI_ADAPTERS], ["x$use_hidapi" = "xyes"], [hidapi])
PROCESS_ADAPTERS([HIDAPI_USB1_ADAPTERS], ["x$use_hidapi" = "xyes" -a "x$use_libusb1" = "xyes"], [hidapi and libusb-1.x])
@@ -800,7 +796,7 @@ echo
echo
echo OpenOCD configuration summary
echo --------------------------------------------------
-m4_foreach([adapter], [USB1_ADAPTERS, USB_ADAPTERS, USB0_ADAPTERS,
+m4_foreach([adapter], [USB1_ADAPTERS, USB0_ADAPTERS,
HIDAPI_ADAPTERS, HIDAPI_USB1_ADAPTERS, LIBFTDI_ADAPTERS,
LIBJAYLINK_ADAPTERS, PCIE_ADAPTERS],
[s=m4_format(["%-40s"], ADAPTER_DESC([adapter]))
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index 7fbcd584f..47b19470e 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -31,9 +31,6 @@ if USE_LIBUSB0
DRIVERFILES += %D%/usb_common.c
%C%_libocdjtagdrivers_la_CPPFLAGS += $(LIBUSB0_CFLAGS)
%C%_libocdjtagdrivers_la_LIBADD += $(LIBUSB0_LIBS)
-if !USE_LIBUSB1
-DRIVERFILES += %D%/libusb0_common.c
-endif
endif
if USE_LIBFTDI
@@ -171,7 +168,6 @@ DRIVERHEADERS = \
%D%/bitbang.h \
%D%/bitq.h \
%D%/jtag_usb_common.h \
- %D%/libusb0_common.h \
%D%/libusb1_common.h \
%D%/libusb_common.h \
%D%/minidriver_imp.h \
diff --git a/src/jtag/drivers/libusb0_common.c b/src/jtag/drivers/libusb0_common.c
deleted file mode 100644
index 0e7858911..000000000
--- a/src/jtag/drivers/libusb0_common.c
+++ /dev/null
@@ -1,230 +0,0 @@
-/***************************************************************************
- * Copyright (C) 2009 by Zachary T Welch <zw...@su...> *
- * *
- * Copyright (C) 2011 by Mauro Gamba <mau...@gm...> *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
- ***************************************************************************/
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-#include "log.h"
-#include "libusb0_common.h"
-
-static int jtag_libusb_error(int err)
-{
- switch (err) {
- case 0:
- return ERROR_OK;
- case -ETIMEDOUT:
- return ERROR_TIMEOUT_REACHED;
- default:
- return ERROR_FAIL;
- }
-}
-
-static bool jtag_libusb_match(struct jtag_libusb_device *dev,
- const uint16_t vids[], const uint16_t pids[])
-{
- for (unsigned i = 0; vids[i]; i++) {
- if (dev->descriptor.idVendor == vids[i] &&
- dev->descriptor.idProduct == pids[i]) {
- return true;
- }
- }
- return false;
-}
-
-/* Returns true if the string descriptor indexed by str_index in device matches string */
-static bool string_descriptor_equal(usb_dev_handle *device, uint8_t str_index,
- const char *string)
-{
- int retval;
- bool matched;
- char desc_string[256+1]; /* Max size of string descriptor */
-
- if (str_index == 0)
- return false;
-
- retval = usb_get_string_simple(device, str_index,
- desc_string, sizeof(desc_string)-1);
- if (retval < 0) {
- LOG_ERROR("usb_get_string_simple() failed with %d", retval);
- return false;
- }
-
- /* Null terminate descriptor string in case it needs to be logged. */
- desc_string[sizeof(desc_string)-1] = '\0';
-
- matched = strncmp(string, desc_string, sizeof(desc_string)) == 0;
- if (!matched)
- LOG_DEBUG("Device serial number '%s' doesn't match requested serial '%s'",
- desc_string, string);
- return matched;
-}
-
-int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
- const char *serial,
- struct jtag_libusb_device_handle **out)
-{
- int retval = ERROR_FAIL;
- bool serial_mismatch = false;
- struct jtag_libusb_device_handle *libusb_handle;
- usb_init();
-
- usb_find_busses();
- usb_find_devices();
-
- struct usb_bus *busses = usb_get_busses();
- for (struct usb_bus *bus = busses; bus; bus = bus->next) {
- for (struct usb_device *dev = bus->devices;
- dev; dev = dev->next) {
- if (!jtag_libusb_match(dev, vids, pids))
- continue;
-
- libusb_handle = usb_open(dev);
- if (NULL == libusb_handle) {
- LOG_ERROR("usb_open() failed with %s", usb_strerror());
- continue;
- }
-
- /* Device must be open to use libusb_get_string_descriptor_ascii. */
- if (serial != NULL &&
- !string_descriptor_equal(libusb_handle, dev->descriptor.iSerialNumber, serial)) {
- serial_mismatch = true;
- usb_close(libusb_handle);
- continue;
- }
- *out = libusb_handle;
- retval = ERROR_OK;
- serial_mismatch = false;
- break;
- }
- }
-
- if (serial_mismatch)
- LOG_INFO("No device matches the serial string");
-
- return retval;
-}
-
-void jtag_libusb_close(jtag_libusb_device_handle *dev)
-{
- /* Close device */
- usb_close(dev);
-}
-
-int jtag_libusb_control_transfer(jtag_libusb_device_handle *dev, uint8_t requestType,
- uint8_t request, uint16_t wValue, uint16_t wIndex, char *bytes,
- uint16_t size, unsigned int timeout)
-{
- int transferred = 0;
-
- transferred = usb_control_msg(dev, requestType, request, wValue, wIndex,
- bytes, size, timeout);
-
- if (transferred < 0)
- transferred = 0;
-
- return transferred;
-}
-
-int jtag_libusb_bulk_write(jtag_libusb_device_handle *dev, int ep, char *bytes,
- int size, int timeout, int *transferred)
-{
- int ret;
-
- *transferred = 0;
-
- ret = usb_bulk_write(dev, ep, bytes, size, timeout);
-
- if (ret < 0) {
- LOG_ERROR("usb_bulk_write error: %i", ret);
- return jtag_libusb_error(ret);
- }
-
- return ERROR_OK;
-}
-
-int jtag_libusb_bulk_read(jtag_libusb_device_handle *dev, int ep, char *bytes,
- int size, int timeout, int *transferred)
-{
- int ret;
-
- *transferred = 0;
-
- ret = usb_bulk_read(dev, ep, bytes, size, timeout);
-
- if (ret < 0) {
- LOG_ERROR("usb_bulk_read error: %i", ret);
- return jtag_libusb_error(ret);
- }
-
- return ERROR_OK;
-}
-
-int jtag_libusb_set_configuration(jtag_libusb_device_handle *devh,
- int configuration)
-{
- struct jtag_libusb_device *udev = jtag_libusb_get_device(devh);
-
- return usb_set_configuration(devh,
- udev->config[configuration].bConfigurationValue);
-}
-
-int jtag_libusb_choose_interface(struct jtag_libusb_device_handle *devh,
- unsigned int *usb_read_ep,
- unsigned int *usb_write_ep,
- int bclass, int subclass, int protocol, int trans_type)
-{
- struct jtag_libusb_device *udev = jtag_libusb_get_device(devh);
- struct usb_interface *iface = udev->config->interface;
- struct usb_interface_descriptor *desc = iface->altsetting;
-
- *usb_read_ep = *usb_write_ep = 0;
-
- for (int i = 0; i < desc->bNumEndpoints; i++) {
- if ((bclass > 0 && desc->bInterfaceClass != bclass) ||
- (subclass > 0 && desc->bInterfaceSubClass != subclass) ||
- (protocol > 0 && desc->bInterfaceProtocol != protocol) ||
- (trans_type > 0 && (desc->endpoint[i].bmAttributes & 0x3) != trans_type))
- continue;
-
- uint8_t epnum = desc->endpoint[i].bEndpointAddress;
- bool is_input = epnum & 0x80;
- LOG_DEBUG("usb ep %s %02x", is_input ? "in" : "out", epnum);
- if (is_input)
- *usb_read_ep = epnum;
- else
- *usb_write_ep = epnum;
-
- if (*usb_read_ep && *usb_write_ep) {
- LOG_DEBUG("Claiming interface %d", (int)desc->bInterfaceNumber);
- usb_claim_interface(devh, (int)desc->bInterfaceNumber);
- return ERROR_OK;
- }
- }
-
- return ERROR_FAIL;
-}
-
-int jtag_libusb_get_pid(struct jtag_libusb_device *dev, uint16_t *pid)
-{
- if (!dev)
- return ERROR_FAIL;
-
- *pid = dev->descriptor.idProduct;
- return ERROR_OK;
-}
diff --git a/src/jtag/drivers/libusb0_common.h b/src/jtag/drivers/libusb0_common.h
deleted file mode 100644
index 6f632c462..000000000
--- a/src/jtag/drivers/libusb0_common.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/***************************************************************************
- * Copyright (C) 2009 by Zachary T Welch <zw...@su...> *
- * *
- * Copyright (C) 2011 by Mauro Gamba <mau...@gm...> *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program. If not, see <http://www.gnu.org/licenses/>. *
- ***************************************************************************/
-
-#ifndef OPENOCD_JTAG_DRIVERS_LIBUSB0_COMMON_H
-#define OPENOCD_JTAG_DRIVERS_LIBUSB0_COMMON_H
-
-#include <usb.h>
-
-#define jtag_libusb_device usb_device
-#define jtag_libusb_device_handle usb_dev_handle
-#define jtag_libusb_device_descriptor usb_device_descriptor
-#define jtag_libusb_interface usb_interface
-#define jtag_libusb_interface_descriptor usb_interface_descriptor
-#define jtag_libusb_endpoint_descriptor usb_endpoint_descriptor
-#define jtag_libusb_config_descriptor usb_config_descriptor
-
-#define jtag_libusb_reset_device(dev) usb_reset(dev)
-#define jtag_libusb_get_device(devh) usb_device(devh)
-
-/* make some defines compatible to libusb1 */
-#define LIBUSB_REQUEST_TYPE_VENDOR USB_TYPE_VENDOR
-#define LIBUSB_RECIPIENT_DEVICE USB_RECIP_DEVICE
-#define LIBUSB_ENDPOINT_OUT USB_ENDPOINT_OUT
-#define LIBUSB_ENDPOINT_IN USB_ENDPOINT_IN
-#define LIBUSB_TRANSFER_TYPE_BULK USB_ENDPOINT_TYPE_BULK
-
-static inline int jtag_libusb_claim_interface(jtag_libusb_device_handle *devh,
- int iface)
-{
- return usb_claim_interface(devh, iface);
-};
-
-static inline int jtag_libusb_release_interface(jtag_libusb_device_handle *devh,
- int iface)
-{
- return usb_release_interface(devh, iface);
-}
-
-int jtag_libusb_open(const uint16_t vids[], const uint16_t pids[],
- const char *serial,
- struct jtag_libusb_device_handle **out);
-void jtag_libusb_close(jtag_libusb_device_handle *dev);
-int jtag_libusb_control_transfer(jtag_libusb_device_handle *dev,
- uint8_t requestType, uint8_t request, uint16_t wValue,
- uint16_t wIndex, char *bytes, uint16_t size, unsigned int timeout);
-int jtag_libusb_bulk_write(struct jtag_libusb_device_handle *dev, int ep,
- char *bytes, int size, int timeout, int *transferred);
-int jtag_libusb_bulk_read(struct jtag_libusb_device_handle *dev, int ep,
- char *bytes, int size, int timeout, int *transferred);
-int jtag_libusb_set_configuration(jtag_libusb_device_handle *devh,
- int configuration);
-int jtag_libusb_choose_interface(struct jtag_libusb_device_handle *devh,
- unsigned int *usb_read_ep,
- unsigned int *usb_write_ep,
- int bclass, int subclass, int protocol, int trans_type);
-int jtag_libusb_get_pid(struct jtag_libusb_device *dev, uint16_t *pid);
-
-#endif /* OPENOCD_JTAG_DRIVERS_LIBUSB0_COMMON_H */
diff --git a/src/jtag/drivers/libusb_common.h b/src/jtag/drivers/libusb_common.h
index 599a0a9b0..47aca5d91 100644
--- a/src/jtag/drivers/libusb_common.h
+++ b/src/jtag/drivers/libusb_common.h
@@ -20,8 +20,6 @@
#ifdef HAVE_LIBUSB1
#include "libusb1_common.h"
-#else
-#include "libusb0_common.h"
#endif
#endif /* OPENOCD_JTAG_DRIVERS_LIBUSB_COMMON_H */
-----------------------------------------------------------------------
Summary of changes:
configure.ac | 10 +-
src/jtag/drivers/Makefile.am | 4 -
src/jtag/drivers/libusb0_common.c | 230 --------------------------------------
src/jtag/drivers/libusb0_common.h | 74 ------------
src/jtag/drivers/libusb_common.h | 2 -
5 files changed, 3 insertions(+), 317 deletions(-)
delete mode 100644 src/jtag/drivers/libusb0_common.c
delete mode 100644 src/jtag/drivers/libusb0_common.h
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-02 15:33:19
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via a01474bb4c4c43a2d10781668efa26e6774364ed (commit)
via 3a8bffbef6afb4b7349d6340c9bae6789c05a3d3 (commit)
via d55bcde16c54bbc76f5b670c076ce6c24a34faaa (commit)
from 0b7eca17691a16e79881243d6d0f38c3eaeb360d (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit a01474bb4c4c43a2d10781668efa26e6774364ed
Author: Marek Vasut <mar...@gm...>
Date: Tue Jan 7 22:54:32 2020 +0100
tcl/target: Switch Renesas R-Car Gen2 boards to new config
Switch Renesas R-Car Gen2 boards which are currently supported from
the old ad-hoc SoC configuration to the new unified configuration.
Change-Id: I8a67bceb3ae92d840ae4dbac20868c75e83f7d58
Signed-off-by: Marek Vasut <mar...@gm...>
Reviewed-on: http://openocd.zylin.com/5398
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/tcl/board/renesas_porter.cfg b/tcl/board/renesas_porter.cfg
index c8032f512..b5622e683 100644
--- a/tcl/board/renesas_porter.cfg
+++ b/tcl/board/renesas_porter.cfg
@@ -1,4 +1,5 @@
# Renesas R-Car M2 Evaluation Board
-source [find target/renesas_r8a7791.cfg]
+set SOC M2
+source [find target/renesas_rcar_gen2.cfg]
source [find board/renesas_gen2_common.cfg]
diff --git a/tcl/board/renesas_silk.cfg b/tcl/board/renesas_silk.cfg
index a026537d4..36af47ff4 100644
--- a/tcl/board/renesas_silk.cfg
+++ b/tcl/board/renesas_silk.cfg
@@ -1,4 +1,5 @@
# Renesas R-Car E2 Evaluation Board
-source [find target/renesas_r8a7794.cfg]
+set SOC E2
+source [find target/renesas_rcar_gen2.cfg]
source [find board/renesas_gen2_common.cfg]
diff --git a/tcl/board/renesas_stout.cfg b/tcl/board/renesas_stout.cfg
index d35f8744f..7a8001796 100644
--- a/tcl/board/renesas_stout.cfg
+++ b/tcl/board/renesas_stout.cfg
@@ -1,4 +1,5 @@
# Renesas R-Car H2 Evaluation Board
-source [find target/renesas_r8a7790.cfg]
+set SOC H2
+source [find target/renesas_rcar_gen2.cfg]
source [find board/renesas_gen2_common.cfg]
commit 3a8bffbef6afb4b7349d6340c9bae6789c05a3d3
Author: Marek Vasut <mar...@gm...>
Date: Tue Jan 7 22:49:45 2020 +0100
tcl/target: Add unified config for Renesas R-Car Gen2 targets
Add configuration for the Renesas R-Car Generation 2 targets.
These are SoCs with Cortex A15s and A7s. All cores currently
supported by OpenOCD are supported here as well as two new
cores, M2N and V2H, for the sake of support completeness.
Change-Id: Ib6fe70a91360b4f8bd69822ee28b6dea530cfa0a
Signed-off-by: Marek Vasut <mar...@gm...>
Reviewed-on: http://openocd.zylin.com/5397
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/tcl/target/renesas_rcar_gen2.cfg b/tcl/target/renesas_rcar_gen2.cfg
new file mode 100644
index 000000000..9f7421d91
--- /dev/null
+++ b/tcl/target/renesas_rcar_gen2.cfg
@@ -0,0 +1,123 @@
+# Renesas R-Car Generation 2 SOCs
+# - There are a combination of Cortex-A15s and Cortex-A7s for each Gen2 SOC
+# - Each SOC can boot through any of the, up to 2, core types that it has
+# e.g. H2 can boot through Cortex-A15 or Cortex-A7
+
+# Supported Gen2 SOCs and their cores:
+# H2: Cortex-A15 x 4, Cortex-A7 x 4
+# M2: Cortex-A15 x 2
+# V2H: Cortex-A15 x 2
+# M2N: Cortex-A15 x 2
+# E2: Cortex-A7 x 2
+
+# Usage:
+# There are 2 configuration options:
+# SOC: Selects the supported SOC. (Default 'H2')
+# BOOT_CORE: Selects the booting core. 'CA15', or 'CA7'
+# Defaults to 'CA15' if the SOC has one, else defaults to 'CA7'
+
+if { [info exists SOC] } {
+ set _soc $SOC
+} else {
+ set _soc H2
+}
+
+# Set configuration for each SOC and the default 'BOOT_CORE'
+switch $_soc {
+ H2 {
+ set _CHIPNAME r8a7790
+ set _num_ca15 4
+ set _num_ca7 4
+ set _boot_core CA15
+ }
+ M2 {
+ set _CHIPNAME r8a7791
+ set _num_ca15 2
+ set _num_ca7 0
+ set _boot_core CA15
+ }
+ V2H {
+ set _CHIPNAME r8a7792
+ set _num_ca15 2
+ set _num_ca7 0
+ set _boot_core CA15
+ }
+ M2N {
+ set _CHIPNAME r8a7793
+ set _num_ca15 2
+ set _num_ca7 0
+ set _boot_core CA15
+ }
+ E2 {
+ set _CHIPNAME r8a7794
+ set _num_ca15 0
+ set _num_ca7 2
+ set _boot_core CA7
+ }
+ default {
+ error "'$_soc' is invalid!"
+ }
+}
+
+# If configured, override the default 'CHIPNAME'
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+}
+
+# If configured, override the default 'BOOT_CORE'
+if { [info exists BOOT_CORE] } {
+ set _boot_core $BOOT_CORE
+}
+
+if { [info exists DAP_TAPID] } {
+ set _DAP_TAPID $DAP_TAPID
+} else {
+ set _DAP_TAPID 0x4ba00477
+}
+
+echo "\t$_soc - $_num_ca15 CA15(s), $_num_ca7 CA7(s)"
+echo "\tBoot Core - $_boot_core\n"
+
+set _DAPNAME $_CHIPNAME.dap
+
+# TAP and DAP
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f -expected-id $_DAP_TAPID
+dap create $_DAPNAME -chain-position $_CHIPNAME.cpu
+
+set CA15_DBGBASE {0x800B0000 0x800B2000 0x800B4000 0x800B6000}
+set CA7_DBGBASE {0x800F0000 0x800F2000 0x800F4000 0x800F6000}
+
+set smp_targets ""
+
+proc setup_ca {core_name dbgbase num boot} {
+ global _CHIPNAME
+ global _DAPNAME
+ global smp_targets
+ for { set _core 0 } { $_core < $num } { incr _core } {
+ set _TARGETNAME $_CHIPNAME.$core_name.$_core
+ set _CTINAME $_TARGETNAME.cti
+ set _command "target create $_TARGETNAME cortex_a -dap $_DAPNAME \
+ -coreid $_core -dbgbase [lindex $dbgbase $_core]"
+ if { $_core == 0 && $boot == 1 } {
+ set _targets "$_TARGETNAME"
+ } else {
+ set _command "$_command -defer-examine"
+ }
+ set smp_targets "$smp_targets $_TARGETNAME"
+ eval $_command
+ }
+}
+
+# Organize target list based on the boot core
+if { [string equal $_boot_core CA15] } {
+ setup_ca a15 $CA15_DBGBASE $_num_ca15 1
+ setup_ca a7 $CA7_DBGBASE $_num_ca7 0
+} elseif { [string equal $_boot_core CA7] } {
+ setup_ca a7 $CA7_DBGBASE $_num_ca7 1
+ setup_ca a15 $CA15_DBGBASE $_num_ca15 0
+} else {
+ setup_ca a15 $CA15_DBGBASE $_num_ca15 0
+ setup_ca a7 $CA7_DBGBASE $_num_ca7 0
+}
+
+eval "target smp $smp_targets"
commit d55bcde16c54bbc76f5b670c076ce6c24a34faaa
Author: Marek Vasut <mar...@gm...>
Date: Thu Feb 6 12:17:13 2020 +0100
tcl/target: Abort on invalid SoC selection on R-Car Gen3
Instead of printing error message and continue, abort on invalid SoC
selection right away.
Change-Id: I9c7a7111b590c6c49a0826562380b881a162a8dc
Signed-off-by: Marek Vasut <mar...@gm...>
Reviewed-on: http://openocd.zylin.com/5439
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/tcl/target/renesas_rcar_gen3.cfg b/tcl/target/renesas_rcar_gen3.cfg
index 2c478b268..34c191827 100644
--- a/tcl/target/renesas_rcar_gen3.cfg
+++ b/tcl/target/renesas_rcar_gen3.cfg
@@ -76,7 +76,7 @@ switch $_soc {
set _boot_core CA53
}
default {
- echo "'$_soc' is invalid!"
+ error "'$_soc' is invalid!"
}
}
-----------------------------------------------------------------------
Summary of changes:
tcl/board/renesas_porter.cfg | 3 +-
tcl/board/renesas_silk.cfg | 3 +-
tcl/board/renesas_stout.cfg | 3 +-
tcl/target/renesas_rcar_gen2.cfg | 123 +++++++++++++++++++++++++++++++++++++++
tcl/target/renesas_rcar_gen3.cfg | 2 +-
5 files changed, 130 insertions(+), 4 deletions(-)
create mode 100644 tcl/target/renesas_rcar_gen2.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-03-02 15:13:47
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 0b7eca17691a16e79881243d6d0f38c3eaeb360d (commit)
from 98ea23a7ff1e563e809111e3bc26f5bf90be0c5d (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 0b7eca17691a16e79881243d6d0f38c3eaeb360d
Author: Tarek BOCHKATI <tar...@gm...>
Date: Fri Feb 7 00:12:48 2020 +0100
flash/stm32h7x: add support of STM32H7Ax/H7Bx devices
this new device has the following features:
- single core cortex-M7
- 2MB flash - dual bank
- page size 8k
- write protection grouped by 4 sectors
- write block size 128 bits (16 bytes)
the bit definition of FLASH_CR is different than STM32H74x,
that's why we introduced a helper to compute the FLASH_CR value
Change-Id: I4da10cde8dd215b1b0f2645f0efdba9d198038d1
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: http://openocd.zylin.com/5441
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/contrib/loaders/flash/stm32/stm32h7x.S b/contrib/loaders/flash/stm32/stm32h7x.S
index beb8fdbd4..a4317229e 100644
--- a/contrib/loaders/flash/stm32/stm32h7x.S
+++ b/contrib/loaders/flash/stm32/stm32h7x.S
@@ -25,29 +25,35 @@
* Code limitations:
* The workarea must have size multiple of 4 bytes, since R/W
* operations are all at 32 bits.
- * The workarea must be big enough to contain 32 bytes of data,
- * thus the minimum size is (rp, wp, data) = 4 + 4 + 32 = 40 bytes.
+ * The workarea must be big enough to contain rp, wp and data, thus the minumum
+ * workarea size is: min_wa_size = sizeof(rp, wp, data) = 4 + 4 + sizeof(data).
+ * - for 0x450 devices: sizeof(data) = 32 bytes, thus min_wa_size = 40 bytes.
+ * - for 0x480 devices: sizeof(data) = 16 bytes, thus min_wa_size = 24 bytes.
* To benefit from concurrent host write-to-buffer and target
* write-to-flash, the workarea must be way bigger than the minimum.
- */
+ *
+ * To avoid confusions the write word size is got from .block_size member of
+ * struct stm32h7x_part_info defined in stm32h7x.c
+*/
/*
* Params :
* r0 = workarea start, status (out)
* r1 = workarea end
* r2 = target address
- * r3 = count (256 bit words)
- * r4 = flash reg base
+ * r3 = count (of write words)
+ * r4 = size of write word
+ * r5 = flash reg base
*
* Clobbered:
- * r5 - rp
- * r6 - wp, status, tmp
- * r7 - loop index, tmp
+ * r6 - rp
+ * r7 - wp, status, tmp
+ * r8 - loop index, tmp
*/
#define STM32_FLASH_CR_OFFSET 0x0C /* offset of CR register in FLASH struct */
#define STM32_FLASH_SR_OFFSET 0x10 /* offset of SR register in FLASH struct */
-#define STM32_CR_PROG 0x00000032 /* PSIZE64 | PG */
+#define STM32_CR_PROG 0x00000002 /* PG */
#define STM32_SR_QW_MASK 0x00000004 /* QW */
#define STM32_SR_ERROR_MASK 0x07ee0000 /* DBECCERR | SNECCERR | RDSERR | RDPERR | OPERR
| INCERR | STRBERR | PGSERR | WRPERR */
@@ -55,54 +61,55 @@
.thumb_func
.global _start
_start:
- ldr r5, [r0, #4] /* read rp */
+ ldr r6, [r0, #4] /* read rp */
wait_fifo:
- ldr r6, [r0, #0] /* read wp */
- cbz r6, exit /* abort if wp == 0, status = 0 */
- subs r6, r6, r5 /* number of bytes available for read in r6 */
+ ldr r7, [r0, #0] /* read wp */
+ cbz r7, exit /* abort if wp == 0, status = 0 */
+ subs r7, r7, r6 /* number of bytes available for read in r7 */
ittt mi /* if wrapped around */
- addmi r6, r1 /* add size of buffer */
- submi r6, r0
- submi r6, #8
- cmp r6, #32 /* wait until 32 bytes are available */
+ addmi r7, r1 /* add size of buffer */
+ submi r7, r0
+ submi r7, #8
+ cmp r7, r4 /* wait until data buffer is full */
bcc wait_fifo
- mov r6, #STM32_CR_PROG
- str r6, [r4, #STM32_FLASH_CR_OFFSET]
+ mov r7, #STM32_CR_PROG
+ str r7, [r5, #STM32_FLASH_CR_OFFSET]
- mov r7, #8 /* program by 8 words = 32 bytes */
+ mov r8, #4
+ udiv r8, r4, r8 /* number of words is size of write word devided by 4*/
write_flash:
dsb
- ldr r6, [r5], #0x04 /* read one word from src, increment ptr */
- str r6, [r2], #0x04 /* write one word to dst, increment ptr */
+ ldr r7, [r6], #0x04 /* read one word from src, increment ptr */
+ str r7, [r2], #0x04 /* write one word to dst, increment ptr */
dsb
- cmp r5, r1 /* if rp >= end of buffer ... */
+ cmp r6, r1 /* if rp >= end of buffer ... */
it cs
- addcs r5, r0, #8 /* ... then wrap at buffer start */
- subs r7, r7, #1 /* decrement loop index */
+ addcs r6, r0, #8 /* ... then wrap at buffer start */
+ subs r8, r8, #1 /* decrement loop index */
bne write_flash /* loop if not done */
busy:
- ldr r6, [r4, #STM32_FLASH_SR_OFFSET]
- tst r6, #STM32_SR_QW_MASK
+ ldr r7, [r5, #STM32_FLASH_SR_OFFSET]
+ tst r7, #STM32_SR_QW_MASK
bne busy /* operation in progress, wait ... */
- ldr r7, =STM32_SR_ERROR_MASK
- tst r6, r7
+ ldr r8, =STM32_SR_ERROR_MASK
+ tst r7, r8
bne error /* fail... */
- str r5, [r0, #4] /* store rp */
+ str r6, [r0, #4] /* store rp */
subs r3, r3, #1 /* decrement count */
bne wait_fifo /* loop if not done */
b exit
error:
- movs r7, #0
- str r7, [r0, #4] /* set rp = 0 on error */
+ movs r8, #0
+ str r8, [r0, #4] /* set rp = 0 on error */
exit:
- mov r0, r6 /* return status in r0 */
+ mov r0, r7 /* return status in r0 */
bkpt #0x00
.pool
diff --git a/contrib/loaders/flash/stm32/stm32h7x.inc b/contrib/loaders/flash/stm32/stm32h7x.inc
index ec14de0ef..015644ffa 100644
--- a/contrib/loaders/flash/stm32/stm32h7x.inc
+++ b/contrib/loaders/flash/stm32/stm32h7x.inc
@@ -1,7 +1,8 @@
/* Autogenerated with ../../../../src/helper/bin2char.sh */
-0x45,0x68,0x06,0x68,0x36,0xb3,0x76,0x1b,0x42,0xbf,0x76,0x18,0x36,0x1a,0x08,0x3e,
-0x20,0x2e,0xf6,0xd3,0x4f,0xf0,0x32,0x06,0xe6,0x60,0x4f,0xf0,0x08,0x07,0xbf,0xf3,
-0x4f,0x8f,0x55,0xf8,0x04,0x6b,0x42,0xf8,0x04,0x6b,0xbf,0xf3,0x4f,0x8f,0x8d,0x42,
-0x28,0xbf,0x00,0xf1,0x08,0x05,0x01,0x3f,0xf1,0xd1,0x26,0x69,0x16,0xf0,0x04,0x0f,
-0xfb,0xd1,0x05,0x4f,0x3e,0x42,0x03,0xd1,0x45,0x60,0x01,0x3b,0xd9,0xd1,0x01,0xe0,
-0x00,0x27,0x47,0x60,0x30,0x46,0x00,0xbe,0x00,0x00,0xee,0x07,
+0x46,0x68,0x07,0x68,0x6f,0xb3,0xbf,0x1b,0x42,0xbf,0x7f,0x18,0x3f,0x1a,0x08,0x3f,
+0xa7,0x42,0xf6,0xd3,0x4f,0xf0,0x02,0x07,0xef,0x60,0x4f,0xf0,0x04,0x08,0xb4,0xfb,
+0xf8,0xf8,0xbf,0xf3,0x4f,0x8f,0x56,0xf8,0x04,0x7b,0x42,0xf8,0x04,0x7b,0xbf,0xf3,
+0x4f,0x8f,0x8e,0x42,0x28,0xbf,0x00,0xf1,0x08,0x06,0xb8,0xf1,0x01,0x08,0xf0,0xd1,
+0x2f,0x69,0x17,0xf0,0x04,0x0f,0xfb,0xd1,0xdf,0xf8,0x1c,0x80,0x17,0xea,0x08,0x0f,
+0x03,0xd1,0x46,0x60,0x01,0x3b,0xd4,0xd1,0x03,0xe0,0x5f,0xf0,0x00,0x08,0xc0,0xf8,
+0x04,0x80,0x38,0x46,0x00,0xbe,0x00,0x00,0x00,0x00,0xee,0x07,
diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c
index d5b5daab2..7882c11a7 100644
--- a/src/flash/nor/stm32h7x.c
+++ b/src/flash/nor/stm32h7x.c
@@ -57,8 +57,6 @@
#define FLASH_FW (1 << 6)
#define FLASH_START (1 << 7)
-#define FLASH_SNB(a) ((a) << 8)
-
/* FLASH_SR register bits */
#define FLASH_BSY (1 << 0) /* Operation in progress */
#define FLASH_QW (1 << 2) /* Operation queue in progress */
@@ -101,25 +99,31 @@
#define FLASH_BANK1_ADDRESS 0x08100000
#define FLASH_REG_BASE_B0 0x52002000
#define FLASH_REG_BASE_B1 0x52002100
-#define FLASH_SIZE_ADDRESS 0x1FF1E880
-#define FLASH_BLOCK_SIZE 32
struct stm32h7x_rev {
uint16_t rev;
const char *str;
};
+/* stm32h7x_part_info permits the store each device information and specificities.
+ * the default unit is byte unless the suffix '_kb' is used. */
+
struct stm32h7x_part_info {
uint16_t id;
const char *device_str;
const struct stm32h7x_rev *revs;
size_t num_revs;
- unsigned int page_size;
+ unsigned int page_size_kb;
+ unsigned int block_size; /* flash write word size in bytes */
uint16_t max_flash_size_kb;
uint8_t has_dual_bank;
uint16_t first_bank_size_kb; /* Used when has_dual_bank is true */
uint32_t flash_regs_base; /* Flash controller registers location */
uint32_t fsize_addr; /* Location of FSIZE register */
+ uint32_t wps_group_size; /* write protection group sectors' count */
+ uint32_t wps_mask;
+ /* function to compute flash_cr register values */
+ uint32_t (*compute_flash_cr)(uint32_t cmd, int snb);
};
struct stm32h7x_flash_bank {
@@ -140,18 +144,58 @@ static const struct stm32h7x_rev stm32_450_revs[] = {
{ 0x1000, "A" }, { 0x1001, "Z" }, { 0x1003, "Y" }, { 0x2001, "X" }, { 0x2003, "V" },
};
+static const struct stm32h7x_rev stm32_480_revs[] = {
+ { 0x1000, "A"},
+};
+
+static uint32_t stm32x_compute_flash_cr_450(uint32_t cmd, int snb)
+{
+ return cmd | (snb << 8);
+}
+
+static uint32_t stm32x_compute_flash_cr_480(uint32_t cmd, int snb)
+{
+ /* save FW and START bits, to be right shifted by 2 bits later */
+ const uint32_t tmp = cmd & (FLASH_FW | FLASH_START);
+
+ /* mask parallelism (ignored), FW and START bits */
+ cmd &= ~(FLASH_PSIZE_64 | FLASH_FW | FLASH_START);
+
+ return cmd | (tmp >> 2) | (snb << 6);
+}
+
static const struct stm32h7x_part_info stm32h7x_parts[] = {
{
.id = 0x450,
.revs = stm32_450_revs,
.num_revs = ARRAY_SIZE(stm32_450_revs),
.device_str = "STM32H74x/75x",
- .page_size = 128, /* 128 KB */
+ .page_size_kb = 128,
+ .block_size = 32,
+ .max_flash_size_kb = 2048,
+ .first_bank_size_kb = 1024,
+ .has_dual_bank = 1,
+ .flash_regs_base = FLASH_REG_BASE_B0,
+ .fsize_addr = 0x1FF1E880,
+ .wps_group_size = 1,
+ .wps_mask = 0xFF,
+ .compute_flash_cr = stm32x_compute_flash_cr_450,
+ },
+ {
+ .id = 0x480,
+ .revs = stm32_480_revs,
+ .num_revs = ARRAY_SIZE(stm32_480_revs),
+ .device_str = "STM32H7Ax/7Bx",
+ .page_size_kb = 8,
+ .block_size = 16,
.max_flash_size_kb = 2048,
.first_bank_size_kb = 1024,
.has_dual_bank = 1,
.flash_regs_base = FLASH_REG_BASE_B0,
- .fsize_addr = FLASH_SIZE_ADDRESS,
+ .fsize_addr = 0x08FFF80C,
+ .wps_group_size = 4,
+ .wps_mask = 0xFFFFFFFF,
+ .compute_flash_cr = stm32x_compute_flash_cr_480,
},
};
@@ -170,9 +214,6 @@ FLASH_BANK_COMMAND_HANDLER(stm32x_flash_bank_command)
stm32x_info->probed = false;
stm32x_info->user_bank_size = bank->size;
- bank->write_start_alignment = FLASH_BLOCK_SIZE;
- bank->write_end_alignment = FLASH_BLOCK_SIZE;
-
return ERROR_OK;
}
@@ -403,14 +444,15 @@ static int stm32x_protect_check(struct flash_bank *bank)
return retval;
}
- for (int i = 0; i < bank->num_sectors; i++) {
- bank->sectors[i].is_protected = protection & (1 << i) ? 0 : 1;
- }
+ for (int i = 0; i < bank->num_prot_blocks; i++)
+ bank->prot_blocks[i].is_protected = protection & (1 << i) ? 0 : 1;
+
return ERROR_OK;
}
static int stm32x_erase(struct flash_bank *bank, int first, int last)
{
+ struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
int retval, retval2;
assert(first < bank->num_sectors);
@@ -436,13 +478,13 @@ static int stm32x_erase(struct flash_bank *bank, int first, int last)
for (int i = first; i <= last; i++) {
LOG_DEBUG("erase sector %d", i);
retval = stm32x_write_flash_reg(bank, FLASH_CR,
- FLASH_SER | FLASH_SNB(i) | FLASH_PSIZE_64);
+ stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64, i));
if (retval != ERROR_OK) {
LOG_ERROR("Error erase sector %d", i);
goto flash_lock;
}
retval = stm32x_write_flash_reg(bank, FLASH_CR,
- FLASH_SER | FLASH_SNB(i) | FLASH_PSIZE_64 | FLASH_START);
+ stm32x_info->part_info->compute_flash_cr(FLASH_SER | FLASH_PSIZE_64 | FLASH_START, i));
if (retval != ERROR_OK) {
LOG_ERROR("Error erase sector %d", i);
goto flash_lock;
@@ -501,18 +543,18 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
+ struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
/*
- * If the size of the data part of the buffer is not a multiple of FLASH_BLOCK_SIZE, we get
+ * If the size of the data part of the buffer is not a multiple of .block_size, we get
* "corrupted fifo read" pointer in target_run_flash_async_algorithm()
*/
- uint32_t data_size = 512 * FLASH_BLOCK_SIZE; /* 16384 */
+ uint32_t data_size = 512 * stm32x_info->part_info->block_size;
uint32_t buffer_size = 8 + data_size;
struct working_area *write_algorithm;
struct working_area *source;
uint32_t address = bank->base + offset;
- struct reg_param reg_params[5];
+ struct reg_param reg_params[6];
struct armv7m_algorithm armv7m_info;
- struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
int retval = ERROR_OK;
static const uint8_t stm32x_flash_write_code[] = {
@@ -555,21 +597,23 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
init_reg_param(®_params[0], "r0", 32, PARAM_IN_OUT); /* buffer start, status (out) */
init_reg_param(®_params[1], "r1", 32, PARAM_OUT); /* buffer end */
init_reg_param(®_params[2], "r2", 32, PARAM_OUT); /* target address */
- init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count (word-256 bits) */
- init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* flash reg base */
+ init_reg_param(®_params[3], "r3", 32, PARAM_OUT); /* count of words (word size = .block_size (bytes) */
+ init_reg_param(®_params[4], "r4", 32, PARAM_OUT); /* word size in bytes */
+ init_reg_param(®_params[5], "r5", 32, PARAM_OUT); /* flash reg base */
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, source->address + source->size);
buf_set_u32(reg_params[2].value, 0, 32, address);
buf_set_u32(reg_params[3].value, 0, 32, count);
- buf_set_u32(reg_params[4].value, 0, 32, stm32x_info->flash_regs_base);
+ buf_set_u32(reg_params[4].value, 0, 32, stm32x_info->part_info->block_size);
+ buf_set_u32(reg_params[5].value, 0, 32, stm32x_info->flash_regs_base);
retval = target_run_flash_async_algorithm(target,
buffer,
count,
- FLASH_BLOCK_SIZE,
+ stm32x_info->part_info->block_size,
0, NULL,
- 5, reg_params,
+ ARRAY_SIZE(reg_params), reg_params,
source->address, source->size,
write_algorithm->address, 0,
&armv7m_info);
@@ -598,6 +642,7 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
destroy_reg_param(®_params[2]);
destroy_reg_param(®_params[3]);
destroy_reg_param(®_params[4]);
+ destroy_reg_param(®_params[5]);
return retval;
}
@@ -605,6 +650,7 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
+ struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
uint32_t address = bank->base + offset;
int retval, retval2;
@@ -614,18 +660,18 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
}
/* should be enforced via bank->write_start_alignment */
- assert(!(offset % FLASH_BLOCK_SIZE));
+ assert(!(offset % stm32x_info->part_info->block_size));
/* should be enforced via bank->write_end_alignment */
- assert(!(count % FLASH_BLOCK_SIZE));
+ assert(!(count % stm32x_info->part_info->block_size));
retval = stm32x_unlock_reg(bank);
if (retval != ERROR_OK)
goto flash_lock;
- uint32_t blocks_remaining = count / FLASH_BLOCK_SIZE;
+ uint32_t blocks_remaining = count / stm32x_info->part_info->block_size;
- /* multiple words (32-bytes) to be programmed in block */
+ /* multiple words (n * .block_size) to be programmed in block */
if (blocks_remaining) {
retval = stm32x_write_block(bank, buffer, offset, blocks_remaining);
if (retval != ERROR_OK) {
@@ -635,8 +681,8 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
}
} else {
- buffer += blocks_remaining * FLASH_BLOCK_SIZE;
- address += blocks_remaining * FLASH_BLOCK_SIZE;
+ buffer += blocks_remaining * stm32x_info->part_info->block_size;
+ address += blocks_remaining * stm32x_info->part_info->block_size;
blocks_remaining = 0;
}
if ((retval != ERROR_OK) && (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE))
@@ -653,11 +699,12 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
4. Wait for flash operations completion
*/
while (blocks_remaining > 0) {
- retval = stm32x_write_flash_reg(bank, FLASH_CR, FLASH_PG | FLASH_PSIZE_64);
+ retval = stm32x_write_flash_reg(bank, FLASH_CR,
+ stm32x_info->part_info->compute_flash_cr(FLASH_PG | FLASH_PSIZE_64, 0));
if (retval != ERROR_OK)
goto flash_lock;
- retval = target_write_buffer(target, address, FLASH_BLOCK_SIZE, buffer);
+ retval = target_write_buffer(target, address, stm32x_info->part_info->block_size, buffer);
if (retval != ERROR_OK)
goto flash_lock;
@@ -665,8 +712,8 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
if (retval != ERROR_OK)
goto flash_lock;
- buffer += FLASH_BLOCK_SIZE;
- address += FLASH_BLOCK_SIZE;
+ buffer += stm32x_info->part_info->block_size;
+ address += stm32x_info->part_info->block_size;
blocks_remaining--;
}
@@ -678,16 +725,6 @@ flash_lock:
return (retval == ERROR_OK) ? retval2 : retval;
}
-static void setup_sector(struct flash_bank *bank, int start, int num, int size)
-{
- for (int i = start; i < (start + num) ; i++) {
- assert(i < bank->num_sectors);
- bank->sectors[i].offset = bank->size;
- bank->sectors[i].size = size;
- bank->size += bank->sectors[i].size;
- }
-}
-
static int stm32x_read_id_code(struct flash_bank *bank, uint32_t *id)
{
/* read stm32 device id register */
@@ -779,35 +816,45 @@ static int stm32x_probe(struct flash_bank *bank)
/* did we assign flash size? */
assert(flash_size_in_kb != 0xffff);
- /* calculate numbers of pages */
- int num_pages = flash_size_in_kb / stm32x_info->part_info->page_size;
+ bank->base = base_address;
+ bank->size = flash_size_in_kb * 1024;
+ bank->write_start_alignment = stm32x_info->part_info->block_size;
+ bank->write_end_alignment = stm32x_info->part_info->block_size;
- /* check that calculation result makes sense */
- assert(num_pages > 0);
+ /* setup sectors */
+ bank->num_sectors = flash_size_in_kb / stm32x_info->part_info->page_size_kb;
+ assert(bank->num_sectors > 0);
- if (bank->sectors) {
+ if (bank->sectors)
free(bank->sectors);
- bank->sectors = NULL;
- }
- bank->base = base_address;
- bank->num_sectors = num_pages;
- bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
+ bank->sectors = alloc_block_array(0, stm32x_info->part_info->page_size_kb * 1024,
+ bank->num_sectors);
+
if (bank->sectors == NULL) {
LOG_ERROR("failed to allocate bank sectors");
return ERROR_FAIL;
}
- bank->size = 0;
- /* fixed memory */
- setup_sector(bank, 0, num_pages, stm32x_info->part_info->page_size * 1024);
+ /* setup protection blocks */
+ const uint32_t wpsn = stm32x_info->part_info->wps_group_size;
+ assert(bank->num_sectors % wpsn == 0);
+
+ bank->num_prot_blocks = bank->num_sectors / wpsn;
+ assert(bank->num_prot_blocks > 0);
- for (int i = 0; i < num_pages; i++) {
- bank->sectors[i].is_erased = -1;
- bank->sectors[i].is_protected = 0;
+ if (bank->prot_blocks)
+ free(bank->prot_blocks);
+
+ bank->prot_blocks = alloc_block_array(0, stm32x_info->part_info->page_size_kb * wpsn * 1024,
+ bank->num_prot_blocks);
+
+ if (bank->prot_blocks == NULL) {
+ LOG_ERROR("failed to allocate bank prot_block");
+ return ERROR_FAIL;
}
- stm32x_info->probed = true;
+ stm32x_info->probed = 1;
return ERROR_OK;
}
@@ -946,6 +993,7 @@ static int stm32x_mass_erase(struct flash_bank *bank)
{
int retval, retval2;
struct target *target = bank->target;
+ struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
@@ -957,11 +1005,13 @@ static int stm32x_mass_erase(struct flash_bank *bank)
goto flash_lock;
/* mass erase flash memory bank */
- retval = stm32x_write_flash_reg(bank, FLASH_CR, FLASH_BER | FLASH_PSIZE_64);
+ retval = stm32x_write_flash_reg(bank, FLASH_CR,
+ stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64, 0));
if (retval != ERROR_OK)
goto flash_lock;
- retval = stm32x_write_flash_reg(bank, FLASH_CR, FLASH_BER | FLASH_PSIZE_64 | FLASH_START);
+ retval = stm32x_write_flash_reg(bank, FLASH_CR,
+ stm32x_info->part_info->compute_flash_cr(FLASH_BER | FLASH_PSIZE_64 | FLASH_START, 0));
if (retval != ERROR_OK)
goto flash_lock;
-----------------------------------------------------------------------
Summary of changes:
contrib/loaders/flash/stm32/stm32h7x.S | 73 +++++++------
contrib/loaders/flash/stm32/stm32h7x.inc | 13 +--
src/flash/nor/stm32h7x.c | 176 ++++++++++++++++++++-----------
3 files changed, 160 insertions(+), 102 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2020-03-02 15:12:31
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 98ea23a7ff1e563e809111e3bc26f5bf90be0c5d (commit)
from 39d54ee96973d3e54a8722112cb9ca25245d01ad (commit)
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- Log -----------------------------------------------------------------
commit 98ea23a7ff1e563e809111e3bc26f5bf90be0c5d
Author: Michael Stoll <mic...@me...>
Date: Wed Feb 19 17:32:26 2020 +0100
Add support for SAMD21E17D device
Change-Id: Id0a533f8899b20cc87e3a9143383ddf279c86301
Signed-off-by: Michael Stoll <mic...@me...>
Reviewed-on: http://openocd.zylin.com/5458
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/flash/nor/at91samd.c b/src/flash/nor/at91samd.c
index b6cff9a67..6e89099ab 100644
--- a/src/flash/nor/at91samd.c
+++ b/src/flash/nor/at91samd.c
@@ -181,6 +181,23 @@ static const struct samd_part samd21_parts[] = {
{ 0x26, "SAMD21E16B", 64, 8 },
{ 0x27, "SAMD21E15B", 32, 4 },
+ /* SAMD21 D and L Variants (from Errata)
+ http://ww1.microchip.com/downloads/en/DeviceDoc/
+ SAM-D21-Family-Silicon-Errata-and-DataSheet-Clarification-DS80000760D.pdf */
+ { 0x55, "SAMD21E16BU", 64, 8 },
+ { 0x56, "SAMD21E15BU", 32, 4 },
+ { 0x57, "SAMD21G16L", 64, 8 },
+ { 0x3E, "SAMD21E16L", 64, 8 },
+ { 0x3F, "SAMD21E15L", 32, 4 },
+ { 0x62, "SAMD21E16CU", 64, 8 },
+ { 0x63, "SAMD21E15CU", 32, 4 },
+ { 0x92, "SAMD21J17D", 128, 16 },
+ { 0x93, "SAMD21G17D", 128, 16 },
+ { 0x94, "SAMD21E17D", 128, 16 },
+ { 0x95, "SAMD21E17DU", 128, 16 },
+ { 0x96, "SAMD21G17L", 128, 16 },
+ { 0x97, "SAMD21E17L", 128, 16 },
+
/* Known SAMDA1 parts.
SAMD-A1 series uses the same series identifier like the SAMD21
taken from http://ww1.microchip.com/downloads/en/DeviceDoc/40001895A.pdf (pages 14-17) */
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/at91samd.c | 17 +++++++++++++++++
1 file changed, 17 insertions(+)
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From: OpenOCD-Gerrit <ope...@us...> - 2020-02-29 15:59:14
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from 9ee9bdd2f9e69df816d313d23b50a563c0869428 (commit)
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- Log -----------------------------------------------------------------
commit 39d54ee96973d3e54a8722112cb9ca25245d01ad
Author: Evgeniy Didin <di...@sy...>
Date: Fri Feb 28 11:14:42 2020 +0300
target/arc: fix clang static analyzer warnings
Fixes:
* Removed typo in *bitfields initializations.
* Removed potentional memory leak allocating
reg_data_type_struct_field/reg_data_type_flags_field objects.
* Initialize buffers with "0" before usage in buf_set_u32().
* Removed memory leak in jim_arc_add_reg().
Change-Id: Iefde57cd4a48c4f3350c376475df8642607f52ff
Signed-off-by: Evgeniy Didin <di...@sy...>
Reviewed-on: http://openocd.zylin.com/5480
Reviewed-by: Tomas Vanek <va...@fb...>
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/src/target/arc.c b/src/target/arc.c
index 45ef725dc..244dd5247 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -1241,11 +1241,11 @@ static void arc_deinit_target(struct target *target)
/* Free arc-specific reg_data_types allocations*/
list_for_each_entry_safe_reverse(type, n, &arc->reg_data_types, list) {
if (type->data_type.type_class == REG_TYPE_CLASS_STRUCT) {
- free(type->data_type.reg_type_struct->fields);
+ free(type->reg_type_struct_field);
free(type->bitfields);
free(type);
} else if (type->data_type.type_class == REG_TYPE_CLASS_FLAGS) {
- free(type->data_type.reg_type_flags->fields);
+ free(type->reg_type_flags_field);
free(type->bitfields);
free(type);
}
diff --git a/src/target/arc.h b/src/target/arc.h
index 311648e15..af4149f97 100644
--- a/src/target/arc.h
+++ b/src/target/arc.h
@@ -61,6 +61,10 @@ struct arc_reg_data_type {
struct reg_data_type_struct data_type_struct;
char data_type_id[REG_TYPE_MAX_NAME_LENGTH];
struct arc_reg_bitfield *bitfields;
+ union {
+ struct reg_data_type_struct_field *reg_type_struct_field;
+ struct reg_data_type_flags_field *reg_type_flags_field;
+ };
};
diff --git a/src/target/arc_cmd.c b/src/target/arc_cmd.c
index 3f6caf751..3475762f4 100644
--- a/src/target/arc_cmd.c
+++ b/src/target/arc_cmd.c
@@ -163,7 +163,8 @@ static int jim_arc_add_reg_type_flags(Jim_Interp *interp, int argc,
struct arc_reg_data_type *type = calloc(1, sizeof(*type));
struct reg_data_type_flags *flags = &type->data_type_flags;
struct reg_data_type_flags_field *fields = calloc(fields_sz, sizeof(*fields));
- struct arc_reg_bitfield *bitfields = calloc(fields_sz, sizeof(*type));
+ type->reg_type_flags_field = fields;
+ struct arc_reg_bitfield *bitfields = calloc(fields_sz, sizeof(*bitfields));
if (!(type && fields && bitfields)) {
Jim_SetResultFormatted(goi.interp, "Failed to allocate memory.");
goto fail;
@@ -528,7 +529,8 @@ static int jim_arc_add_reg_type_struct(Jim_Interp *interp, int argc,
struct arc_reg_data_type *type = calloc(1, sizeof(*type));
struct reg_data_type_struct *struct_type = &type->data_type_struct;
struct reg_data_type_struct_field *fields = calloc(fields_sz, sizeof(*fields));
- struct arc_reg_bitfield *bitfields = calloc(fields_sz, sizeof(*type));
+ type->reg_type_struct_field = fields;
+ struct arc_reg_bitfield *bitfields = calloc(fields_sz, sizeof(*bitfields));
if (!(type && fields && bitfields)) {
Jim_SetResultFormatted(goi.interp, "Failed to allocate memory.");
goto fail;
@@ -789,6 +791,7 @@ static int jim_arc_add_reg(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
target = get_current_target(ctx);
if (!target) {
Jim_SetResultFormatted(goi.interp, "No current target");
+ free_reg_desc(reg);
return JIM_ERR;
}
diff --git a/src/target/arc_jtag.c b/src/target/arc_jtag.c
index dd800a462..274d61f3a 100644
--- a/src/target/arc_jtag.c
+++ b/src/target/arc_jtag.c
@@ -26,7 +26,7 @@ static void arc_jtag_enque_write_ir(struct arc_jtag *jtag_info, uint32_t
{
uint32_t current_instr;
struct jtag_tap *tap;
- uint8_t instr_buffer[sizeof(uint32_t)];
+ uint8_t instr_buffer[sizeof(uint32_t)] = {0};
assert(jtag_info);
assert(jtag_info->tap);
@@ -90,7 +90,7 @@ static void arc_jtag_enque_read_dr(struct arc_jtag *jtag_info, uint8_t *data,
static void arc_jtag_enque_write_dr(struct arc_jtag *jtag_info, uint32_t data,
tap_state_t end_state)
{
- uint8_t out_value[sizeof(uint32_t)];
+ uint8_t out_value[sizeof(uint32_t)] = {0};
assert(jtag_info);
assert(jtag_info->tap);
@@ -118,7 +118,7 @@ static void arc_jtag_enque_write_dr(struct arc_jtag *jtag_info, uint32_t data,
static void arc_jtag_enque_set_transaction(struct arc_jtag *jtag_info,
uint32_t new_trans, tap_state_t end_state)
{
- uint8_t out_value[sizeof(uint32_t)];
+ uint8_t out_value[sizeof(uint32_t)] = {0};
assert(jtag_info);
assert(jtag_info->tap);
-----------------------------------------------------------------------
Summary of changes:
src/target/arc.c | 4 ++--
src/target/arc.h | 4 ++++
src/target/arc_cmd.c | 7 +++++--
src/target/arc_jtag.c | 6 +++---
4 files changed, 14 insertions(+), 7 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2020-02-27 06:47:33
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 9ee9bdd2f9e69df816d313d23b50a563c0869428 (commit)
from 3bfe4926632d458da449f0438db6949c75b7af59 (commit)
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- Log -----------------------------------------------------------------
commit 9ee9bdd2f9e69df816d313d23b50a563c0869428
Author: Evgeniy Didin <di...@sy...>
Date: Mon Jan 27 15:22:27 2020 +0300
Introduce ARCv2 architecture related code
This patch is an initial bump of ARC-specific code
which implements the ARCv2 target(EMSK board) initializing
routine and some basic remote connection/load/continue
functionality.
Changes:
03.12.2019:
-Add return value checks.
-Using static code analizer next fixes were made:
Mem leak in functions:
arc_jtag_read_memory,arc_jtag_read_memory,
arc_jtag_write_registers, arc_jtag_read_registers,
jim_arc_add_reg_type_flags, jim_arc_add_reg_type_struct,
arc_build_reg_cache, arc_mem_read.
Dead code in "arc_mem_read";
In arc_save_context, arc_restore_context correct arguments
in"memset" calls.
In "build_bcr_reg_cache", "arc_build_reg_cache" check
if list is not empty.
29.12.2019
-Moved code from arc_v2.c to arc.c
-Added checks of the result of calloc/malloc calls
-Reworked arc_cmd.c: replaced spagetty code with functions
-Moved to one style in if statements - to "if(!bla)"
-Changed Licence headers
22.01.2020
-Removed unused variables in arc_common
-Renamed register operation functions
-Introduced arc_deinit_target function
-Fixed interrupt handling in halt/resume:
* add irq_state field in arc_common
* fix irq enable/disable calls ( now STATUS32 register is used)
-Switched from buf_set(get)_us32() usage to target_buffer_set(get)_u32()
-Made some cleanup
30.01.2020
-Removed redundant arc_register struct, moved target link to arc_reg_desc
-Introduced link to BCR reg cache in arc_common for freeing memory.
-Now arc_deinit_target frees all arc-related allocated memory.
Valgrind shows no memory leaks.
-Inroduced arch description in arc.c
01.02.2020
-Remove small memory allocations in arc_init_reg. Instead created reg_value
and feature fields in arc_reg_desc.
-Add return value for arc_init_reg() func.
-Replaced some integer constants(61,62,63) with defines.
-Removed redundant conversions in arc_reg_get_field().
-Moved iccm/dccm configuration code from arc_configure()
to separate functions.
19.02.2020
-Change sizeof(struct) to sizeof(*ptr) in allocations
-Changed if/while(ptr != NULL) to if/while(ptr)
-Removed unused variables from struct arc_jtag
-Add additional structs to arc_reg_data_type
to reduce amount of memory allocations calls
and simplifying memory freeing.
-Add helper arc_reg_bitfield_t struct which includes
reg_data_type_bitfield object and char[] name. Reduces
memory allocations calls.
-Add limit for reg_type/reg_type_field names(20 symbols).
-Add in jim_arc_add_reg_type*() functions additional
argnument checks(amount of field/name size).
-In jim_arc_add_reg_type*() reduced amount of memory allocations.
-Cleanup of jim_arc_add_reg_type*() functions.
-For commands update ".usage" fields according docopt.
-Cleanup in arc_jtag.c
-Renamed functions which require jtag_exeutre_queue() to arc_jtag_enque_*()
-Add arc_jtag_enque_register_rw() function, which r/w to jtag ir/dr regs
during regiter r/w.
24.02:
-Change include guards in arc* files according coding style
-Remove _t suffix in struct arc_reg_bitfield_t
-Some cleanup
Change-Id: I6ab0e82b12e6ddb683c9d13dfb7dd6f49a30cb9f
Signed-off-by: Evgeniy Didin <di...@sy...>
Cc: Alexey Brodkin <abr...@sy...>
Reviewed-on: http://openocd.zylin.com/5332
Tested-by: jenkins
Reviewed-by: Oleksij Rempel <li...@re...>
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 5a16def55..30d2339bf 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -24,6 +24,7 @@ noinst_LTLIBRARIES += %D%/libtarget.la
$(STM8_SRC) \
$(INTEL_IA32_SRC) \
$(ESIRISC_SRC) \
+ $(ARC_SRC) \
%D%/avrt.c \
%D%/dsp563xx.c \
%D%/dsp563xx_once.c \
@@ -156,6 +157,12 @@ ESIRISC_SRC = \
%D%/esirisc_jtag.c \
%D%/esirisc_trace.c
+ARC_SRC = \
+ %D%/arc.c \
+ %D%/arc_cmd.c \
+ %D%/arc_jtag.c \
+ %D%/arc_mem.c
+
%C%_libtarget_la_SOURCES += \
%D%/algorithm.h \
%D%/arm.h \
@@ -243,7 +250,11 @@ ESIRISC_SRC = \
%D%/esirisc.h \
%D%/esirisc_jtag.h \
%D%/esirisc_regs.h \
- %D%/esirisc_trace.h
+ %D%/esirisc_trace.h \
+ %D%/arc.h \
+ %D%/arc_cmd.h \
+ %D%/arc_jtag.h \
+ %D%/arc_mem.h
include %D%/openrisc/Makefile.am
include %D%/riscv/Makefile.am
diff --git a/src/target/arc.c b/src/target/arc.c
new file mode 100644
index 000000000..45ef725dc
--- /dev/null
+++ b/src/target/arc.c
@@ -0,0 +1,1339 @@
+/***************************************************************************
+ * Copyright (C) 2013-2015,2019-2020 Synopsys, Inc. *
+ * Frank Dols <fra...@sy...> *
+ * Mischa Jonker <mis...@sy...> *
+ * Anton Kolesov <ant...@sy...> *
+ * Evgeniy Didin <di...@sy...> *
+ * *
+ * SPDX-License-Identifier: GPL-2.0-or-later *
+ ***************************************************************************/
+
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "arc.h"
+
+
+
+/*
+ * ARC architecture specific details.
+ *
+ * ARC has two types of registers:
+ * 1) core registers(e.g. r0,r1..) [is_core = true]
+ * 2) Auxiliary registers [is_core = false]..
+ *
+ * Auxiliary registers at the same time can be divided into
+ * read-only BCR(build configuration regs, e.g. isa_config, mpu_build) and
+ * R/RW non-BCR ("control" register, e.g. pc, status32_t, debug).
+ *
+ * The way of accessing to Core and AUX registers differs on Jtag level.
+ * BCR/non-BCR describes if the register is immutable and that reading
+ * unexisting register is safe RAZ, rather then an error.
+ * Note, core registers cannot be BCR.
+ *
+ * In arc/cpu/ tcl files all regiters are defined as core, non-BCR aux
+ * and BCR aux, in "add-reg" command they are passed to three lists
+ * respectively: core_reg_descriptions, aux_reg_descriptions,
+ * bcr_reg_descriptions.
+ *
+ * Due to the specifics of accessing to BCR/non-BCR registers there are two
+ * register caches:
+ * 1) core_and_aux_cache - includes registers described in
+ * core_reg_descriptions and aux_reg_descriptions lists.
+ * Used during save/restore context step.
+ * 2) bcr_cache - includes registers described bcr_reg_descriptions.
+ * Currently used internally during configure step.
+ */
+
+
+
+void arc_reg_data_type_add(struct target *target,
+ struct arc_reg_data_type *data_type)
+{
+ LOG_DEBUG("Adding %s reg_data_type", data_type->data_type.id);
+ struct arc_common *arc = target_to_arc(target);
+ assert(arc);
+
+ list_add_tail(&data_type->list, &arc->reg_data_types);
+}
+
+/**
+ * Private implementation of register_get_by_name() for ARC that
+ * doesn't skip not [yet] existing registers. Used in many places
+ * for iteration through registers and even for marking required registers as
+ * existing.
+ */
+struct reg *arc_reg_get_by_name(struct reg_cache *first,
+ const char *name, bool search_all)
+{
+ unsigned int i;
+ struct reg_cache *cache = first;
+
+ while (cache) {
+ for (i = 0; i < cache->num_regs; i++) {
+ if (!strcmp(cache->reg_list[i].name, name))
+ return &(cache->reg_list[i]);
+ }
+
+ if (search_all)
+ cache = cache->next;
+ else
+ break;
+ }
+
+ return NULL;
+}
+
+
+/* Initialize arc_common structure, which passes to openocd target instance */
+static int arc_init_arch_info(struct target *target, struct arc_common *arc,
+ struct jtag_tap *tap)
+{
+ arc->common_magic = ARC_COMMON_MAGIC;
+ target->arch_info = arc;
+
+ arc->jtag_info.tap = tap;
+
+ /* The only allowed ir_length is 4 for ARC jtag. */
+ if (tap->ir_length != 4) {
+ LOG_ERROR("ARC jtag instruction length should be equal to 4");
+ return ERROR_FAIL;
+ }
+
+ /* Add standard GDB data types */
+ INIT_LIST_HEAD(&arc->reg_data_types);
+ struct arc_reg_data_type *std_types = calloc(ARRAY_SIZE(standard_gdb_types),
+ sizeof(*std_types));
+
+ if (!std_types) {
+ LOG_ERROR("Unable to allocate memory");
+ return ERROR_FAIL;
+ }
+
+ for (unsigned int i = 0; i < ARRAY_SIZE(standard_gdb_types); i++) {
+ std_types[i].data_type.type = standard_gdb_types[i].type;
+ std_types[i].data_type.id = standard_gdb_types[i].id;
+ arc_reg_data_type_add(target, &(std_types[i]));
+ }
+
+ /* Fields related to target descriptions */
+ INIT_LIST_HEAD(&arc->core_reg_descriptions);
+ INIT_LIST_HEAD(&arc->aux_reg_descriptions);
+ INIT_LIST_HEAD(&arc->bcr_reg_descriptions);
+ arc->num_regs = 0;
+ arc->num_core_regs = 0;
+ arc->num_aux_regs = 0;
+ arc->num_bcr_regs = 0;
+ arc->last_general_reg = ULONG_MAX;
+ arc->pc_index_in_cache = ULONG_MAX;
+ arc->debug_index_in_cache = ULONG_MAX;
+
+ return ERROR_OK;
+}
+
+int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg,
+ const char * const type_name, const size_t type_name_len)
+{
+ assert(target);
+ assert(arc_reg);
+
+ struct arc_common *arc = target_to_arc(target);
+ assert(arc);
+
+ /* Find register type */
+ {
+ struct arc_reg_data_type *type;
+ list_for_each_entry(type, &arc->reg_data_types, list)
+ if (!strncmp(type->data_type.id, type_name, type_name_len)) {
+ arc_reg->data_type = &(type->data_type);
+ break;
+ }
+
+ if (!arc_reg->data_type)
+ return ERROR_ARC_REGTYPE_NOT_FOUND;
+ }
+
+ if (arc_reg->is_core) {
+ list_add_tail(&arc_reg->list, &arc->core_reg_descriptions);
+ arc->num_core_regs += 1;
+ } else if (arc_reg->is_bcr) {
+ list_add_tail(&arc_reg->list, &arc->bcr_reg_descriptions);
+ arc->num_bcr_regs += 1;
+ } else {
+ list_add_tail(&arc_reg->list, &arc->aux_reg_descriptions);
+ arc->num_aux_regs += 1;
+ }
+ arc->num_regs += 1;
+
+ LOG_DEBUG(
+ "added register {name=%s, num=0x%x, type=%s%s%s%s}",
+ arc_reg->name, arc_reg->arch_num, arc_reg->data_type->id,
+ arc_reg->is_core ? ", core" : "", arc_reg->is_bcr ? ", bcr" : "",
+ arc_reg->is_general ? ", general" : ""
+ );
+
+ return ERROR_OK;
+}
+
+/* Reading core or aux register */
+static int arc_get_register(struct reg *reg)
+{
+ assert(reg);
+
+ struct arc_reg_desc *desc = reg->arch_info;
+ struct target *target = desc->target;
+ struct arc_common *arc = target_to_arc(target);
+
+ uint32_t value;
+
+ if (reg->valid) {
+ LOG_DEBUG("Get register (cached) gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
+ reg->number, desc->name, target_buffer_get_u32(target, reg->value));
+ return ERROR_OK;
+ }
+
+ if (desc->is_core) {
+ /* Accessing to R61/R62 registers causes Jtag hang */
+ if (desc->arch_num == CORE_R61_NUM || desc->arch_num == CORE_R62_NUM) {
+ LOG_ERROR("It is forbidden to read core registers 61 and 62.");
+ return ERROR_FAIL;
+ }
+ CHECK_RETVAL(arc_jtag_read_core_reg_one(&arc->jtag_info, desc->arch_num,
+ &value));
+ } else {
+ CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, desc->arch_num,
+ &value));
+ }
+
+ target_buffer_set_u32(target, reg->value, value);
+
+ /* If target is unhalted all register reads should be uncached. */
+ if (target->state == TARGET_HALTED)
+ reg->valid = true;
+ else
+ reg->valid = false;
+
+ reg->dirty = false;
+
+ LOG_DEBUG("Get register gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
+ reg->number , desc->name, value);
+
+
+ return ERROR_OK;
+}
+
+/* Writing core or aux register */
+static int arc_set_register(struct reg *reg, uint8_t *buf)
+{
+ struct arc_reg_desc *desc = reg->arch_info;
+ struct target *target = desc->target;
+ uint32_t value = target_buffer_get_u32(target, buf);
+ /* Unlike "get" function "set" is supported only if target
+ * is in halt mode. Async writes are not supported yet. */
+ if (target->state != TARGET_HALTED)
+ return ERROR_TARGET_NOT_HALTED;
+
+ /* Accessing to R61/R62 registers causes Jtag hang */
+ if (desc->is_core && (desc->arch_num == CORE_R61_NUM ||
+ desc->arch_num == CORE_R62_NUM)) {
+ LOG_ERROR("It is forbidden to write core registers 61 and 62.");
+ return ERROR_FAIL;
+ }
+ target_buffer_set_u32(target, reg->value, value);
+
+ LOG_DEBUG("Set register gdb_num=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
+ reg->number, desc->name, value);
+
+ reg->valid = true;
+ reg->dirty = true;
+
+ return ERROR_OK;
+}
+
+const struct reg_arch_type arc_reg_type = {
+ .get = arc_get_register,
+ .set = arc_set_register,
+};
+
+/* GDB register groups. For now we suport only general and "empty" */
+static const char * const reg_group_general = "general";
+static const char * const reg_group_other = "";
+
+/* Common code to initialize `struct reg` for different registers: core, aux, bcr. */
+static int arc_init_reg(struct target *target, struct reg *reg,
+ struct arc_reg_desc *reg_desc, unsigned long number)
+{
+ assert(target);
+ assert(reg);
+ assert(reg_desc);
+
+ struct arc_common *arc = target_to_arc(target);
+
+ /* Initialize struct reg */
+ reg->name = reg_desc->name;
+ reg->size = 32; /* All register in ARC are 32-bit */
+ reg->value = ®_desc->reg_value;
+ reg->type = &arc_reg_type;
+ reg->arch_info = reg_desc;
+ reg->caller_save = true; /* @todo should be configurable. */
+ reg->reg_data_type = reg_desc->data_type;
+ reg->feature = ®_desc->feature;
+
+ reg->feature->name = reg_desc->gdb_xml_feature;
+
+ /* reg->number is used by OpenOCD as value for @regnum. Thus when setting
+ * value of a register GDB will use it as a number of register in
+ * P-packet. OpenOCD gdbserver will then use number of register in
+ * P-packet as an array index in the reg_list returned by
+ * arc_regs_get_gdb_reg_list. So to ensure that registers are assigned
+ * correctly it would be required to either sort registers in
+ * arc_regs_get_gdb_reg_list or to assign numbers sequentially here and
+ * according to how registers will be sorted in
+ * arc_regs_get_gdb_reg_list. Second options is much more simpler. */
+ reg->number = number;
+
+ if (reg_desc->is_general) {
+ arc->last_general_reg = reg->number;
+ reg->group = reg_group_general;
+ } else {
+ reg->group = reg_group_other;
+ }
+
+ return ERROR_OK;
+}
+
+/* Building aux/core reg_cache */
+static int arc_build_reg_cache(struct target *target)
+{
+ unsigned long i = 0;
+ struct arc_reg_desc *reg_desc;
+ /* get pointers to arch-specific information */
+ struct arc_common *arc = target_to_arc(target);
+ const unsigned long num_regs = arc->num_core_regs + arc->num_aux_regs;
+ struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
+ struct reg_cache *cache = calloc(1, sizeof(*cache));
+ struct reg *reg_list = calloc(num_regs, sizeof(*reg_list));
+
+ if (!cache || !reg_list) {
+ LOG_ERROR("Not enough memory");
+ goto fail;
+ }
+
+ /* Build the process context cache */
+ cache->name = "arc registers";
+ cache->next = NULL;
+ cache->reg_list = reg_list;
+ cache->num_regs = num_regs;
+ arc->core_and_aux_cache = cache;
+ (*cache_p) = cache;
+
+ if (list_empty(&arc->core_reg_descriptions)) {
+ LOG_ERROR("No core registers were defined");
+ goto fail;
+ }
+
+ list_for_each_entry(reg_desc, &arc->core_reg_descriptions, list) {
+ CHECK_RETVAL(arc_init_reg(target, ®_list[i], reg_desc, i));
+
+ LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
+ reg_list[i].name, reg_list[i].group,
+ reg_list[i].feature->name);
+
+ i += 1;
+ }
+
+ if (list_empty(&arc->aux_reg_descriptions)) {
+ LOG_ERROR("No aux registers were defined");
+ goto fail;
+ }
+
+ list_for_each_entry(reg_desc, &arc->aux_reg_descriptions, list) {
+ CHECK_RETVAL(arc_init_reg(target, ®_list[i], reg_desc, i));
+
+ LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
+ reg_list[i].name, reg_list[i].group,
+ reg_list[i].feature->name);
+
+ /* PC and DEBUG are essential so we search for them. */
+ if (!strcmp("pc", reg_desc->name)) {
+ if (arc->pc_index_in_cache != ULONG_MAX) {
+ LOG_ERROR("Double definition of PC in configuration");
+ goto fail;
+ }
+ arc->pc_index_in_cache = i;
+ } else if (!strcmp("debug", reg_desc->name)) {
+ if (arc->debug_index_in_cache != ULONG_MAX) {
+ LOG_ERROR("Double definition of DEBUG in configuration");
+ goto fail;
+ }
+ arc->debug_index_in_cache = i;
+ }
+ i += 1;
+ }
+
+ if (arc->pc_index_in_cache == ULONG_MAX
+ || arc->debug_index_in_cache == ULONG_MAX) {
+ LOG_ERROR("`pc' and `debug' registers must be present in target description.");
+ goto fail;
+ }
+
+ assert(i == (arc->num_core_regs + arc->num_aux_regs));
+
+ arc->core_aux_cache_built = true;
+
+ return ERROR_OK;
+
+fail:
+ free(cache);
+ free(reg_list);
+
+ return ERROR_FAIL;
+}
+
+/* Build bcr reg_cache.
+ * This function must be called only after arc_build_reg_cache */
+static int arc_build_bcr_reg_cache(struct target *target)
+{
+ /* get pointers to arch-specific information */
+ struct arc_common *arc = target_to_arc(target);
+ const unsigned long num_regs = arc->num_bcr_regs;
+ struct reg_cache **cache_p = register_get_last_cache_p(&target->reg_cache);
+ struct reg_cache *cache = malloc(sizeof(*cache));
+ struct reg *reg_list = calloc(num_regs, sizeof(*reg_list));
+
+ struct arc_reg_desc *reg_desc;
+ unsigned long i = 0;
+ unsigned long gdb_regnum = arc->core_and_aux_cache->num_regs;
+
+ if (!cache || !reg_list) {
+ LOG_ERROR("Unable to allocate memory");
+ goto fail;
+ }
+
+ /* Build the process context cache */
+ cache->name = "arc.bcr";
+ cache->next = NULL;
+ cache->reg_list = reg_list;
+ cache->num_regs = num_regs;
+ arc->bcr_cache = cache;
+ (*cache_p) = cache;
+
+ if (list_empty(&arc->bcr_reg_descriptions)) {
+ LOG_ERROR("No BCR registers are defined");
+ goto fail;
+ }
+
+ list_for_each_entry(reg_desc, &arc->bcr_reg_descriptions, list) {
+ CHECK_RETVAL(arc_init_reg(target, ®_list[i], reg_desc, gdb_regnum));
+ /* BCRs always semantically, they are just read-as-zero, if there is
+ * not real register. */
+ reg_list[i].exist = true;
+
+ LOG_DEBUG("reg n=%3li name=%3s group=%s feature=%s", i,
+ reg_list[i].name, reg_list[i].group,
+ reg_list[i].feature->name);
+ i += 1;
+ gdb_regnum += 1;
+ }
+
+ assert(i == arc->num_bcr_regs);
+
+ arc->bcr_cache_built = true;
+
+
+ return ERROR_OK;
+fail:
+ free(cache);
+ free(reg_list);
+
+ return ERROR_FAIL;
+}
+
+
+static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
+ int *reg_list_size, enum target_register_class reg_class)
+{
+ assert(target->reg_cache);
+ struct arc_common *arc = target_to_arc(target);
+
+ /* get pointers to arch-specific information storage */
+ *reg_list_size = arc->num_regs;
+ *reg_list = calloc(*reg_list_size, sizeof(struct reg *));
+
+ if (!*reg_list) {
+ LOG_ERROR("Unable to allocate memory");
+ return ERROR_FAIL;
+ }
+
+ /* OpenOCD gdb_server API seems to be inconsistent here: when it generates
+ * XML tdesc it filters out !exist registers, however when creating a
+ * g-packet it doesn't do so. REG_CLASS_ALL is used in first case, and
+ * REG_CLASS_GENERAL used in the latter one. Due to this we had to filter
+ * out !exist register for "general", but not for "all". Attempts to filter out
+ * !exist for "all" as well will cause a failed check in OpenOCD GDB
+ * server. */
+ if (reg_class == REG_CLASS_ALL) {
+ unsigned long i = 0;
+ struct reg_cache *reg_cache = target->reg_cache;
+ while (reg_cache) {
+ for (unsigned j = 0; j < reg_cache->num_regs; j++, i++)
+ (*reg_list)[i] = ®_cache->reg_list[j];
+ reg_cache = reg_cache->next;
+ }
+ assert(i == arc->num_regs);
+ LOG_DEBUG("REG_CLASS_ALL: number of regs=%i", *reg_list_size);
+ } else {
+ unsigned long i = 0;
+ unsigned long gdb_reg_number = 0;
+ struct reg_cache *reg_cache = target->reg_cache;
+ while (reg_cache) {
+ for (unsigned j = 0;
+ j < reg_cache->num_regs && gdb_reg_number <= arc->last_general_reg;
+ j++) {
+ if (reg_cache->reg_list[j].exist) {
+ (*reg_list)[i] = ®_cache->reg_list[j];
+ i++;
+ }
+ gdb_reg_number += 1;
+ }
+ reg_cache = reg_cache->next;
+ }
+ *reg_list_size = i;
+ LOG_DEBUG("REG_CLASS_GENERAL: number of regs=%i", *reg_list_size);
+ }
+
+ return ERROR_OK;
+}
+
+/* Reading field of struct_type register */
+int arc_reg_get_field(struct target *target, const char *reg_name,
+ const char *field_name, uint32_t *value_ptr)
+{
+ struct reg_data_type_struct_field *field;
+
+ LOG_DEBUG("getting register field (reg_name=%s, field_name=%s)", reg_name, field_name);
+
+ /* Get register */
+ struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
+
+ if (!reg) {
+ LOG_ERROR("Requested register `%s' doens't exist.", reg_name);
+ return ERROR_ARC_REGISTER_NOT_FOUND;
+ }
+
+ if (reg->reg_data_type->type != REG_TYPE_ARCH_DEFINED
+ || reg->reg_data_type->type_class != REG_TYPE_CLASS_STRUCT)
+ return ERROR_ARC_REGISTER_IS_NOT_STRUCT;
+
+ /* Get field in a register */
+ struct reg_data_type_struct *reg_struct =
+ reg->reg_data_type->reg_type_struct;
+ for (field = reg_struct->fields;
+ field;
+ field = field->next) {
+ if (!strcmp(field->name, field_name))
+ break;
+ }
+
+ if (!field)
+ return ERROR_ARC_REGISTER_FIELD_NOT_FOUND;
+
+ if (!field->use_bitfields)
+ return ERROR_ARC_FIELD_IS_NOT_BITFIELD;
+
+ if (!reg->valid)
+ CHECK_RETVAL(reg->type->get(reg));
+
+ /* First do endiannes-safe read of register value
+ * then convert it to binary buffer for further
+ * field extraction */
+
+ *value_ptr = buf_get_u32(reg->value, field->bitfield->start,
+ field->bitfield->end - field->bitfield->start + 1);
+
+ return ERROR_OK;
+}
+
+static int arc_get_register_value(struct target *target, const char *reg_name,
+ uint32_t *value_ptr)
+{
+ LOG_DEBUG("reg_name=%s", reg_name);
+
+ struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
+
+ if (!reg)
+ return ERROR_ARC_REGISTER_NOT_FOUND;
+
+ if (!reg->valid)
+ CHECK_RETVAL(reg->type->get(reg));
+
+ *value_ptr = target_buffer_get_u32(target, reg->value);
+
+ return ERROR_OK;
+}
+
+
+/* Configure DCCM's */
+static int arc_configure_dccm(struct target *target)
+{
+ struct arc_common *arc = target_to_arc(target);
+
+ uint32_t dccm_build_version, dccm_build_size0, dccm_build_size1;
+ CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "version",
+ &dccm_build_version));
+ CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "size0",
+ &dccm_build_size0));
+ CHECK_RETVAL(arc_reg_get_field(target, "dccm_build", "size1",
+ &dccm_build_size1));
+ /* There is no yet support of configurable number of cycles,
+ * So there is no difference between v3 and v4 */
+ if ((dccm_build_version == 3 || dccm_build_version == 4) && dccm_build_size0 > 0) {
+ CHECK_RETVAL(arc_get_register_value(target, "aux_dccm", &(arc->dccm_start)));
+ uint32_t dccm_size = 0x100;
+ dccm_size <<= dccm_build_size0;
+ if (dccm_build_size0 == 0xF)
+ dccm_size <<= dccm_build_size1;
+ arc->dccm_end = arc->dccm_start + dccm_size;
+ LOG_DEBUG("DCCM detected start=0x%" PRIx32 " end=0x%" PRIx32,
+ arc->dccm_start, arc->dccm_end);
+
+ }
+ return ERROR_OK;
+}
+
+
+/* Configure ICCM's */
+
+static int arc_configure_iccm(struct target *target)
+{
+ struct arc_common *arc = target_to_arc(target);
+
+ /* ICCM0 */
+ uint32_t iccm_build_version, iccm_build_size00, iccm_build_size01;
+ uint32_t aux_iccm = 0;
+ CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "version",
+ &iccm_build_version));
+ CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm0_size0",
+ &iccm_build_size00));
+ CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm0_size1",
+ &iccm_build_size01));
+ if (iccm_build_version == 4 && iccm_build_size00 > 0) {
+ CHECK_RETVAL(arc_get_register_value(target, "aux_iccm", &aux_iccm));
+ uint32_t iccm0_size = 0x100;
+ iccm0_size <<= iccm_build_size00;
+ if (iccm_build_size00 == 0xF)
+ iccm0_size <<= iccm_build_size01;
+ /* iccm0 start is located in highest 4 bits of aux_iccm */
+ arc->iccm0_start = aux_iccm & 0xF0000000;
+ arc->iccm0_end = arc->iccm0_start + iccm0_size;
+ LOG_DEBUG("ICCM0 detected start=0x%" PRIx32 " end=0x%" PRIx32,
+ arc->iccm0_start, arc->iccm0_end);
+ }
+
+ /* ICCM1 */
+ uint32_t iccm_build_size10, iccm_build_size11;
+ CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm1_size0",
+ &iccm_build_size10));
+ CHECK_RETVAL(arc_reg_get_field(target, "iccm_build", "iccm1_size1",
+ &iccm_build_size11));
+ if (iccm_build_version == 4 && iccm_build_size10 > 0) {
+ /* Use value read for ICCM0 */
+ if (!aux_iccm)
+ CHECK_RETVAL(arc_get_register_value(target, "aux_iccm", &aux_iccm));
+ uint32_t iccm1_size = 0x100;
+ iccm1_size <<= iccm_build_size10;
+ if (iccm_build_size10 == 0xF)
+ iccm1_size <<= iccm_build_size11;
+ arc->iccm1_start = aux_iccm & 0x0F000000;
+ arc->iccm1_end = arc->iccm1_start + iccm1_size;
+ LOG_DEBUG("ICCM1 detected start=0x%" PRIx32 " end=0x%" PRIx32,
+ arc->iccm1_start, arc->iccm1_end);
+ }
+ return ERROR_OK;
+}
+
+/* Configure some core features, depending on BCRs. */
+static int arc_configure(struct target *target)
+{
+ LOG_DEBUG("Configuring ARC ICCM and DCCM");
+
+ /* Configuring DCCM if DCCM_BUILD and AUX_DCCM are known registers. */
+ if (arc_reg_get_by_name(target->reg_cache, "dccm_build", true) &&
+ arc_reg_get_by_name(target->reg_cache, "aux_dccm", true))
+ CHECK_RETVAL(arc_configure_dccm(target));
+
+ /* Configuring ICCM if ICCM_BUILD and AUX_ICCM are known registers. */
+ if (arc_reg_get_by_name(target->reg_cache, "iccm_build", true) &&
+ arc_reg_get_by_name(target->reg_cache, "aux_iccm", true))
+ CHECK_RETVAL(arc_configure_iccm(target));
+
+ return ERROR_OK;
+}
+
+/* arc_examine is function, which is used for all arc targets*/
+static int arc_examine(struct target *target)
+{
+ uint32_t status;
+ struct arc_common *arc = target_to_arc(target);
+
+ CHECK_RETVAL(arc_jtag_startup(&arc->jtag_info));
+
+ if (!target_was_examined(target)) {
+ CHECK_RETVAL(arc_jtag_status(&arc->jtag_info, &status));
+ if (status & ARC_JTAG_STAT_RU)
+ target->state = TARGET_RUNNING;
+ else
+ target->state = TARGET_HALTED;
+
+ /* Read BCRs and configure optional registers. */
+ CHECK_RETVAL(arc_configure(target));
+
+ target_set_examined(target);
+ }
+
+ return ERROR_OK;
+}
+
+static int arc_halt(struct target *target)
+{
+ uint32_t value, irq_state;
+ struct arc_common *arc = target_to_arc(target);
+
+ LOG_DEBUG("target->state: %s", target_state_name(target));
+
+ if (target->state == TARGET_HALTED) {
+ LOG_DEBUG("target was already halted");
+ return ERROR_OK;
+ }
+
+ if (target->state == TARGET_UNKNOWN)
+ LOG_WARNING("target was in unknown state when halt was requested");
+
+ if (target->state == TARGET_RESET) {
+ if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
+ LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
+ return ERROR_TARGET_FAILURE;
+ } else {
+ target->debug_reason = DBG_REASON_DBGRQ;
+ }
+ }
+
+ /* Break (stop) processor.
+ * Do read-modify-write sequence, or DEBUG.UB will be reset unintentionally.
+ * We do not use here arc_get/set_core_reg functions here because they imply
+ * that the processor is already halted. */
+ CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, &value));
+ value |= SET_CORE_FORCE_HALT; /* set the HALT bit */
+ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DEBUG_REG, value));
+ alive_sleep(1);
+
+ /* Save current IRQ state */
+ CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &irq_state));
+
+ if (irq_state & AUX_STATUS32_REG_IE_BIT)
+ arc->irq_state = 1;
+ else
+ arc->irq_state = 0;
+
+ /* update state and notify gdb*/
+ target->state = TARGET_HALTED;
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
+
+ /* some more debug information */
+ if (debug_level >= LOG_LVL_DEBUG) {
+ LOG_DEBUG("core stopped (halted) DEGUB-REG: 0x%08" PRIx32, value);
+ CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
+ LOG_DEBUG("core STATUS32: 0x%08" PRIx32, value);
+ }
+
+ return ERROR_OK;
+}
+
+/**
+ * Read registers that are used in GDB g-packet. We don't read them one-by-one,
+ * but do that in one batch operation to improve speed. Calls to JTAG layer are
+ * expensive so it is better to make one big call that reads all necessary
+ * registers, instead of many calls, one for one register.
+ */
+static int arc_save_context(struct target *target)
+{
+ int retval = ERROR_OK;
+ unsigned int i;
+ struct arc_common *arc = target_to_arc(target);
+ struct reg *reg_list = arc->core_and_aux_cache->reg_list;
+
+ LOG_DEBUG("Saving aux and core registers values");
+ assert(reg_list);
+
+ /* It is assumed that there is at least one AUX register in the list, for
+ * example PC. */
+ const uint32_t core_regs_size = arc->num_core_regs * sizeof(uint32_t);
+ /* last_general_reg is inclusive number. To get count of registers it is
+ * required to do +1. */
+ const uint32_t regs_to_scan =
+ MIN(arc->last_general_reg + 1, arc->num_regs);
+ const uint32_t aux_regs_size = arc->num_aux_regs * sizeof(uint32_t);
+ uint32_t *core_values = malloc(core_regs_size);
+ uint32_t *aux_values = malloc(aux_regs_size);
+ uint32_t *core_addrs = malloc(core_regs_size);
+ uint32_t *aux_addrs = malloc(aux_regs_size);
+ unsigned int core_cnt = 0;
+ unsigned int aux_cnt = 0;
+
+ if (!core_values || !core_addrs || !aux_values || !aux_addrs) {
+ LOG_ERROR("Unable to allocate memory");
+ retval = ERROR_FAIL;
+ goto exit;
+ }
+
+ memset(core_values, 0xff, core_regs_size);
+ memset(core_addrs, 0xff, core_regs_size);
+ memset(aux_values, 0xff, aux_regs_size);
+ memset(aux_addrs, 0xff, aux_regs_size);
+
+ for (i = 0; i < MIN(arc->num_core_regs, regs_to_scan); i++) {
+ struct reg *reg = &(reg_list[i]);
+ struct arc_reg_desc *arc_reg = reg->arch_info;
+ if (!reg->valid && reg->exist) {
+ core_addrs[core_cnt] = arc_reg->arch_num;
+ core_cnt += 1;
+ }
+ }
+
+ for (i = arc->num_core_regs; i < regs_to_scan; i++) {
+ struct reg *reg = &(reg_list[i]);
+ struct arc_reg_desc *arc_reg = reg->arch_info;
+ if (!reg->valid && reg->exist) {
+ aux_addrs[aux_cnt] = arc_reg->arch_num;
+ aux_cnt += 1;
+ }
+ }
+
+ /* Read data from target. */
+ if (core_cnt > 0) {
+ retval = arc_jtag_read_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
+ if (ERROR_OK != retval) {
+ LOG_ERROR("Attempt to read core registers failed.");
+ retval = ERROR_FAIL;
+ goto exit;
+ }
+ }
+ if (aux_cnt > 0) {
+ retval = arc_jtag_read_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
+ if (ERROR_OK != retval) {
+ LOG_ERROR("Attempt to read aux registers failed.");
+ retval = ERROR_FAIL;
+ goto exit;
+ }
+ }
+
+ /* Parse core regs */
+ core_cnt = 0;
+ for (i = 0; i < MIN(arc->num_core_regs, regs_to_scan); i++) {
+ struct reg *reg = &(reg_list[i]);
+ struct arc_reg_desc *arc_reg = reg->arch_info;
+ if (!reg->valid && reg->exist) {
+ target_buffer_set_u32(target, reg->value, core_values[core_cnt]);
+ core_cnt += 1;
+ reg->valid = true;
+ reg->dirty = false;
+ LOG_DEBUG("Get core register regnum=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
+ i, arc_reg->name, core_values[core_cnt]);
+ }
+ }
+
+ /* Parse aux regs */
+ aux_cnt = 0;
+ for (i = arc->num_core_regs; i < regs_to_scan; i++) {
+ struct reg *reg = &(reg_list[i]);
+ struct arc_reg_desc *arc_reg = reg->arch_info;
+ if (!reg->valid && reg->exist) {
+ target_buffer_set_u32(target, reg->value, aux_values[aux_cnt]);
+ aux_cnt += 1;
+ reg->valid = true;
+ reg->dirty = false;
+ LOG_DEBUG("Get aux register regnum=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
+ i , arc_reg->name, aux_values[aux_cnt]);
+ }
+ }
+
+exit:
+ free(core_values);
+ free(core_addrs);
+ free(aux_values);
+ free(aux_addrs);
+
+ return retval;
+}
+
+static int arc_examine_debug_reason(struct target *target)
+{
+ uint32_t debug_bh;
+
+ /* Only check for reason if don't know it already. */
+ /* BTW After singlestep at this point core is not marked as halted, so
+ * reading from memory to get current instruction wouldn't work anyway. */
+ if (target->debug_reason == DBG_REASON_DBGRQ ||
+ target->debug_reason == DBG_REASON_SINGLESTEP) {
+ return ERROR_OK;
+ }
+
+ CHECK_RETVAL(arc_reg_get_field(target, "debug", "bh",
+ &debug_bh));
+
+ if (debug_bh) {
+ /* DEBUG.BH is set if core halted due to BRK instruction. */
+ target->debug_reason = DBG_REASON_BREAKPOINT;
+ } else {
+ /* TODO: Add Actionpoint check when AP support will be introduced*/
+ LOG_WARNING("Unknown debug reason");
+ }
+
+ return ERROR_OK;
+}
+
+static int arc_debug_entry(struct target *target)
+{
+ CHECK_RETVAL(arc_save_context(target));
+
+ /* TODO: reset internal indicators of caches states, otherwise D$/I$
+ * will not be flushed/invalidated when required. */
+ CHECK_RETVAL(arc_examine_debug_reason(target));
+
+ return ERROR_OK;
+}
+
+static int arc_poll(struct target *target)
+{
+ uint32_t status, value;
+ struct arc_common *arc = target_to_arc(target);
+
+ /* gdb calls continuously through this arc_poll() function */
+ CHECK_RETVAL(arc_jtag_status(&arc->jtag_info, &status));
+
+ /* check for processor halted */
+ if (status & ARC_JTAG_STAT_RU) {
+ if (target->state != TARGET_RUNNING) {
+ LOG_WARNING("target is still running!");
+ target->state = TARGET_RUNNING;
+ }
+ return ERROR_OK;
+ }
+ /* In some cases JTAG status register indicates that
+ * processor is in halt mode, but processor is still running.
+ * We check halt bit of AUX STATUS32 register for setting correct state. */
+ if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET)) {
+ CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
+ if (value & AUX_STATUS32_REG_HALT_BIT) {
+ LOG_DEBUG("ARC core in halt or reset state.");
+ target->state = TARGET_HALTED;
+ CHECK_RETVAL(arc_debug_entry(target));
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
+ } else {
+ LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "
+ "target is still running");
+ }
+
+ } else if (target->state == TARGET_DEBUG_RUNNING) {
+
+ target->state = TARGET_HALTED;
+ LOG_DEBUG("ARC core is in debug running mode");
+
+ CHECK_RETVAL(arc_debug_entry(target));
+
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_DEBUG_HALTED));
+ }
+
+ return ERROR_OK;
+}
+
+static int arc_assert_reset(struct target *target)
+{
+ struct arc_common *arc = target_to_arc(target);
+ enum reset_types jtag_reset_config = jtag_get_reset_config();
+ bool srst_asserted = false;
+
+ LOG_DEBUG("target->state: %s", target_state_name(target));
+
+ if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) {
+ /* allow scripts to override the reset event */
+
+ target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
+ register_cache_invalidate(arc->core_and_aux_cache);
+ /* An ARC target might be in halt state after reset, so
+ * if script requested processor to resume, then it must
+ * be manually started to ensure that this request
+ * is satisfied. */
+ if (target->state == TARGET_HALTED && !target->reset_halt) {
+ /* Resume the target and continue from the current
+ * PC register value. */
+ LOG_DEBUG("Starting CPU execution after reset");
+ CHECK_RETVAL(target_resume(target, 1, 0, 0, 0));
+ }
+ target->state = TARGET_RESET;
+
+ return ERROR_OK;
+ }
+
+ /* some cores support connecting while srst is asserted
+ * use that mode if it has been configured */
+ if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) &&
+ (jtag_reset_config & RESET_SRST_NO_GATING)) {
+ jtag_add_reset(0, 1);
+ srst_asserted = true;
+ }
+
+ if (jtag_reset_config & RESET_HAS_SRST) {
+ /* should issue a srst only, but we may have to assert trst as well */
+ if (jtag_reset_config & RESET_SRST_PULLS_TRST)
+ jtag_add_reset(1, 1);
+ else if (!srst_asserted)
+ jtag_add_reset(0, 1);
+ }
+
+ target->state = TARGET_RESET;
+ jtag_add_sleep(50000);
+
+ register_cache_invalidate(arc->core_and_aux_cache);
+
+ if (target->reset_halt)
+ CHECK_RETVAL(target_halt(target));
+
+ return ERROR_OK;
+}
+
+static int arc_deassert_reset(struct target *target)
+{
+ LOG_DEBUG("target->state: %s", target_state_name(target));
+
+ /* deassert reset lines */
+ jtag_add_reset(0, 0);
+
+ return ERROR_OK;
+}
+
+static int arc_arch_state(struct target *target)
+{
+ uint32_t pc_value;
+
+ if (debug_level < LOG_LVL_DEBUG)
+ return ERROR_OK;
+
+ CHECK_RETVAL(arc_get_register_value(target, "pc", &pc_value));
+
+ LOG_DEBUG("target state: %s; PC at: 0x%08" PRIx32,
+ target_state_name(target),
+ pc_value);
+
+ return ERROR_OK;
+}
+
+/**
+ * See arc_save_context() for reason why we want to dump all regs at once.
+ * This however means that if there are dependencies between registers they
+ * will not be observable until target will be resumed.
+ */
+static int arc_restore_context(struct target *target)
+{
+ int retval = ERROR_OK;
+ unsigned int i;
+ struct arc_common *arc = target_to_arc(target);
+ struct reg *reg_list = arc->core_and_aux_cache->reg_list;
+
+ LOG_DEBUG("Restoring registers values");
+ assert(reg_list);
+
+ const uint32_t core_regs_size = arc->num_core_regs * sizeof(uint32_t);
+ const uint32_t aux_regs_size = arc->num_aux_regs * sizeof(uint32_t);
+ uint32_t *core_values = malloc(core_regs_size);
+ uint32_t *aux_values = malloc(aux_regs_size);
+ uint32_t *core_addrs = malloc(core_regs_size);
+ uint32_t *aux_addrs = malloc(aux_regs_size);
+ unsigned int core_cnt = 0;
+ unsigned int aux_cnt = 0;
+
+ if (!core_values || !core_addrs || !aux_values || !aux_addrs) {
+ LOG_ERROR("Unable to allocate memory");
+ retval = ERROR_FAIL;
+ goto exit;
+ }
+
+ memset(core_values, 0xff, core_regs_size);
+ memset(core_addrs, 0xff, core_regs_size);
+ memset(aux_values, 0xff, aux_regs_size);
+ memset(aux_addrs, 0xff, aux_regs_size);
+
+ for (i = 0; i < arc->num_core_regs; i++) {
+ struct reg *reg = &(reg_list[i]);
+ struct arc_reg_desc *arc_reg = reg->arch_info;
+ if (reg->valid && reg->exist && reg->dirty) {
+ LOG_DEBUG("Will write regnum=%u", i);
+ core_addrs[core_cnt] = arc_reg->arch_num;
+ core_values[core_cnt] = target_buffer_get_u32(target, reg->value);
+ core_cnt += 1;
+ }
+ }
+
+ for (i = 0; i < arc->num_aux_regs; i++) {
+ struct reg *reg = &(reg_list[arc->num_core_regs + i]);
+ struct arc_reg_desc *arc_reg = reg->arch_info;
+ if (reg->valid && reg->exist && reg->dirty) {
+ LOG_DEBUG("Will write regnum=%lu", arc->num_core_regs + i);
+ aux_addrs[aux_cnt] = arc_reg->arch_num;
+ aux_values[aux_cnt] = target_buffer_get_u32(target, reg->value);
+ aux_cnt += 1;
+ }
+ }
+
+ /* Write data to target.
+ * Check before write, if aux and core count is greater than 0. */
+ if (core_cnt > 0) {
+ retval = arc_jtag_write_core_reg(&arc->jtag_info, core_addrs, core_cnt, core_values);
+ if (ERROR_OK != retval) {
+ LOG_ERROR("Attempt to write to core registers failed.");
+ retval = ERROR_FAIL;
+ goto exit;
+ }
+ }
+
+ if (aux_cnt > 0) {
+ retval = arc_jtag_write_aux_reg(&arc->jtag_info, aux_addrs, aux_cnt, aux_values);
+ if (ERROR_OK != retval) {
+ LOG_ERROR("Attempt to write to aux registers failed.");
+ retval = ERROR_FAIL;
+ goto exit;
+ }
+ }
+
+exit:
+ free(core_values);
+ free(core_addrs);
+ free(aux_values);
+ free(aux_addrs);
+
+ return retval;
+}
+
+static int arc_enable_interrupts(struct target *target, int enable)
+{
+ uint32_t value;
+
+ struct arc_common *arc = target_to_arc(target);
+
+ CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
+
+ if (enable) {
+ /* enable interrupts */
+ value |= SET_CORE_ENABLE_INTERRUPTS;
+ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
+ LOG_DEBUG("interrupts enabled");
+ } else {
+ /* disable interrupts */
+ value &= ~SET_CORE_ENABLE_INTERRUPTS;
+ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
+ LOG_DEBUG("interrupts disabled");
+ }
+
+ return ERROR_OK;
+}
+
+static int arc_resume(struct target *target, int current, target_addr_t address,
+ int handle_breakpoints, int debug_execution)
+{
+ struct arc_common *arc = target_to_arc(target);
+ uint32_t resume_pc = 0;
+ uint32_t value;
+ struct reg *pc = &arc->core_and_aux_cache->reg_list[arc->pc_index_in_cache];
+
+ LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints(not supported yet):%i,"
+ " debug_execution:%i", current, address, handle_breakpoints, debug_execution);
+
+ if (target->state != TARGET_HALTED) {
+ LOG_WARNING("target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ /* current = 1: continue on current PC, otherwise continue at <address> */
+ if (!current) {
+ target_buffer_set_u32(target, pc->value, address);
+ pc->dirty = 1;
+ pc->valid = 1;
+ LOG_DEBUG("Changing the value of current PC to 0x%08" TARGET_PRIxADDR, address);
+ }
+
+ if (!current)
+ resume_pc = address;
+ else
+ resume_pc = target_buffer_get_u32(target, pc->value);
+
+ CHECK_RETVAL(arc_restore_context(target));
+
+ LOG_DEBUG("Target resumes from PC=0x%" PRIx32 ", pc.dirty=%i, pc.valid=%i",
+ resume_pc, pc->dirty, pc->valid);
+
+ /* check if GDB tells to set our PC where to continue from */
+ if ((pc->valid == 1) && (resume_pc == target_buffer_get_u32(target, pc->value))) {
+ value = target_buffer_get_u32(target, pc->value);
+ LOG_DEBUG("resume Core (when start-core) with PC @:0x%08" PRIx32, value);
+ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_PC_REG, value));
+ }
+
+ /* Restore IRQ state if not in debug_execution*/
+ if (!debug_execution)
+ CHECK_RETVAL(arc_enable_interrupts(target, arc->irq_state));
+ else
+ CHECK_RETVAL(arc_enable_interrupts(target, !debug_execution));
+
+ target->debug_reason = DBG_REASON_NOTHALTED;
+
+ /* ready to get us going again */
+ target->state = TARGET_RUNNING;
+ CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, &value));
+ value &= ~SET_CORE_HALT_BIT; /* clear the HALT bit */
+ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_STATUS32_REG, value));
+ LOG_DEBUG("Core started to run");
+
+ /* registers are now invalid */
+ register_cache_invalidate(arc->core_and_aux_cache);
+
+ if (!debug_execution) {
+ target->state = TARGET_RUNNING;
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
+ LOG_DEBUG("target resumed at 0x%08" PRIx32, resume_pc);
+ } else {
+ target->state = TARGET_DEBUG_RUNNING;
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED));
+ LOG_DEBUG("target debug resumed at 0x%08" PRIx32, resume_pc);
+ }
+
+ return ERROR_OK;
+}
+
+static int arc_init_target(struct command_context *cmd_ctx, struct target *target)
+{
+ CHECK_RETVAL(arc_build_reg_cache(target));
+ CHECK_RETVAL(arc_build_bcr_reg_cache(target));
+ target->debug_reason = DBG_REASON_DBGRQ;
+ return ERROR_OK;
+}
+
+static void arc_free_reg_cache(struct reg_cache *cache)
+{
+ free(cache->reg_list);
+ free(cache);
+}
+
+static void arc_deinit_target(struct target *target)
+{
+ struct arc_common *arc = target_to_arc(target);
+
+ LOG_DEBUG("deinitialization of target");
+ if (arc->core_aux_cache_built)
+ arc_free_reg_cache(arc->core_and_aux_cache);
+ if (arc->bcr_cache_built)
+ arc_free_reg_cache(arc->bcr_cache);
+
+ struct arc_reg_data_type *type, *n;
+ struct arc_reg_desc *desc, *k;
+
+ /* Free arc-specific reg_data_types allocations*/
+ list_for_each_entry_safe_reverse(type, n, &arc->reg_data_types, list) {
+ if (type->data_type.type_class == REG_TYPE_CLASS_STRUCT) {
+ free(type->data_type.reg_type_struct->fields);
+ free(type->bitfields);
+ free(type);
+ } else if (type->data_type.type_class == REG_TYPE_CLASS_FLAGS) {
+ free(type->data_type.reg_type_flags->fields);
+ free(type->bitfields);
+ free(type);
+ }
+ }
+
+ /* Free standard_gdb_types reg_data_types allocations */
+ type = list_first_entry(&arc->reg_data_types, struct arc_reg_data_type, list);
+ free(type);
+
+ list_for_each_entry_safe(desc, k, &arc->aux_reg_descriptions, list)
+ free_reg_desc(desc);
+
+ list_for_each_entry_safe(desc, k, &arc->core_reg_descriptions, list)
+ free_reg_desc(desc);
+
+ list_for_each_entry_safe(desc, k, &arc->bcr_reg_descriptions, list)
+ free_reg_desc(desc);
+
+ free(arc);
+}
+
+
+static int arc_target_create(struct target *target, Jim_Interp *interp)
+{
+ struct arc_common *arc = calloc(1, sizeof(*arc));
+
+ if (!arc) {
+ LOG_ERROR("Unable to allocate memory");
+ return ERROR_FAIL;
+ }
+
+ LOG_DEBUG("Entering");
+ CHECK_RETVAL(arc_init_arch_info(target, arc, target->tap));
+
+ return ERROR_OK;
+}
+
+
+/* ARC v2 target */
+struct target_type arcv2_target = {
+ .name = "arcv2",
+
+ .poll = arc_poll,
+
+ .arch_state = arc_arch_state,
+
+ /* TODO That seems like something similiar to metaware hostlink, so perhaps
+ * we can exploit this in the future. */
+ .target_request_data = NULL,
+
+ .halt = arc_halt,
+ .resume = arc_resume,
+ .step = NULL,
+
+ .assert_reset = arc_assert_reset,
+ .deassert_reset = arc_deassert_reset,
+
+ /* TODO Implement soft_reset_halt */
+ .soft_reset_halt = NULL,
+
+ .get_gdb_reg_list = arc_get_gdb_reg_list,
+
+ .read_memory = arc_mem_read,
+ .write_memory = arc_mem_write,
+ .checksum_memory = NULL,
+ .blank_check_memory = NULL,
+
+ .add_breakpoint = NULL,
+ .add_context_breakpoint = NULL,
+ .add_hybrid_breakpoint = NULL,
+ .remove_breakpoint = NULL,
+ .add_watchpoint = NULL,
+ .remove_watchpoint = NULL,
+ .hit_watchpoint = NULL,
+
+ .run_algorithm = NULL,
+ .start_algorithm = NULL,
+ .wait_algorithm = NULL,
+
+ .commands = arc_monitor_command_handlers,
+
+ .target_create = arc_target_create,
+ .init_target = arc_init_target,
+ .deinit_target = arc_deinit_target,
+ .examine = arc_examine,
+
+ .virt2phys = NULL,
+ .read_phys_memory = NULL,
+ .write_phys_memory = NULL,
+ .mmu = NULL,
+};
diff --git a/src/target/arc.h b/src/target/arc.h
new file mode 100644
index 000000000..311648e15
--- /dev/null
+++ b/src/target/arc.h
@@ -0,0 +1,212 @@
+/***************************************************************************
+ * Copyright (C) 2013-2015,2019-2020 Synopsys, Inc. *
+ * Frank Dols <fra...@sy...> *
+ * Mischa Jonker <mis...@sy...> *
+ * Anton Kolesov <ant...@sy...> *
+ * Evgeniy Didin <di...@sy...> *
+ * *
+ * SPDX-License-Identifier: GPL-2.0-or-later *
+ ***************************************************************************/
+
+#ifndef OPENOCD_TARGET_ARC_H
+#define OPENOCD_TARGET_ARC_H
+
+#include <helper/time_support.h>
+#include <jtag/jtag.h>
+
+#include "algorithm.h"
+#include "breakpoints.h"
+#include "jtag/interface.h"
+#include "register.h"
+#include "target.h"
+#include "target_request.h"
+#include "target_type.h"
+#include "helper/bits.h"
+
+#include "arc_jtag.h"
+#include "arc_cmd.h"
+#include "arc_mem.h"
+
+#define ARC_COMMON_MAGIC 0xB32EB324 /* just a unique number */
+
+#define AUX_DEBUG_REG 0x5
+#define AUX_PC_REG 0x6
+#define AUX_STATUS32_REG 0xA
+
+#define SET_CORE_FORCE_HALT BIT(1)
+#define SET_CORE_HALT_BIT BIT(0) /* STATUS32[0] = H field */
+#define SET_CORE_ENABLE_INTERRUPTS BIT(31)
+
+#define AUX_STATUS32_REG_HALT_BIT BIT(0)
+#define AUX_STATUS32_REG_IE_BIT BIT(31) /* STATUS32[31] = IE field */
+
+/* Reserved core registers */
+#define CORE_R61_NUM (61)
+#define CORE_R62_NUM (62)
+
+#define CORE_REG_MAX_NUMBER (63)
+
+/* Limit reg_type/reg_type_field name to 20 symbols */
+#define REG_TYPE_MAX_NAME_LENGTH 20
+
+struct arc_reg_bitfield {
+ struct reg_data_type_bitfield bitfield;
+ char name[REG_TYPE_MAX_NAME_LENGTH];
+};
+/* Register data type */
+struct arc_reg_data_type {
+ struct list_head list;
+ struct reg_data_type data_type;
+ struct reg_data_type_flags data_type_flags;
+ struct reg_data_type_struct data_type_struct;
+ char data_type_id[REG_TYPE_MAX_NAME_LENGTH];
+ struct arc_reg_bitfield *bitfields;
+};
+
+
+
+/* Standard GDB register types */
+static const struct reg_data_type standard_gdb_types[] = {
+ { .type = REG_TYPE_INT, .id = "int" },
+ { .type = REG_TYPE_INT8, .id = "int8" },
+ { .type = REG_TYPE_INT16, .id = "int16" },
+ { .type = REG_TYPE_INT32, .id = "int32" },
+ { .type = REG_TYPE_INT64, .id = "int64" },
+ { .type = REG_TYPE_INT128, .id = "int128" },
+ { .type = REG_TYPE_UINT8, .id = "uint8" },
+ { .type = REG_TYPE_UINT16, .id = "uint16" },
+ { .type = REG_TYPE_UINT32, .id = "uint32" },
+ { .type = REG_TYPE_UINT64, .id = "uint64" },
+ { .type = REG_TYPE_UINT128, .id = "uint128" },
+ { .type = REG_TYPE_CODE_PTR, .id = "code_ptr" },
+ { .type = REG_TYPE_DATA_PTR, .id = "data_ptr" },
+ { .type = REG_TYPE_FLOAT, .id = "float" },
+ { .type = REG_TYPE_IEEE_SINGLE, .id = "ieee_single" },
+ { .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double" },
+};
+
+
+struct arc_common {
+ uint32_t common_magic;
+
+ struct arc_jtag jtag_info;
+
+ struct reg_cache *core_and_aux_cache;
+ struct reg_cache *bcr_cache;
+
+ /* Indicate if cach was built (for deinit function) */
+ bool core_aux_cache_built;
+ bool bcr_cache_built;
+ /* Closely Coupled memory(CCM) regions for performance-critical
+ * code (optional). */
+ uint32_t iccm0_start;
+ uint32_t iccm0_end;
+ uint32_t iccm1_start;
+ uint32_t iccm1_end;
+ uint32_t dccm_start;
+ uint32_t dccm_end;
+
+ int irq_state;
+
+ /* Register descriptions */
+ struct list_head reg_data_types;
+ struct list_head core_reg_descriptions;
+ struct list_head aux_reg_descriptions;
+ struct list_head bcr_reg_descriptions;
+ unsigned long num_regs;
+ unsigned long num_core_regs;
+ unsigned long num_aux_regs;
+ unsigned long num_bcr_regs;
+ unsigned long last_general_reg;
+
+ /* PC register location in register cache. */
+ unsigned long pc_index_in_cache;
+ /* DEBUG register location in register cache. */
+ unsigned long debug_index_in_cache;
+};
+
+/* Borrowed from nds32.h */
+#define CHECK_RETVAL(action) \
+ do { \
+ int __retval = (action); \
+ if (__retval != ERROR_OK) { \
+ LOG_DEBUG("error while calling \"%s\"", \
+ # action); \
+ return __retval; \
+ } \
+ } while (0)
+
+#define JIM_CHECK_RETVAL(action) \
+ do { \
+ int __retval = (action); \
+ if (__retval != JIM_OK) { \
+ LOG_DEBUG("error while calling \"%s\"", \
+ # action); \
+ return __retval; \
+ } \
+ } while (0)
+
+static inline struct arc_common *target_to_arc(struct target *target)
+{
+ return target->arch_info;
+}
+
+
+/* ARC Register description */
+struct arc_reg_desc {
+
+ struct target *target;
+
+ /* Register name */
+ char *name;
+
+ /* Actual place of storing reg_value */
+ uint8_t reg_value[4];
+
+ /* Actual place of storing register feature */
+ struct reg_feature feature;
+
+ /* GDB XML feature */
+ char *gdb_xml_feature;
+
+ /* Is this a register in g/G-packet? */
+ bool is_general;
+
+ /* Architectural number: core reg num or AUX reg num */
+ uint32_t arch_num;
+
+ /* Core or AUX register? */
+ bool is_core;
+
+ /* Build configuration register? */
+ bool is_bcr;
+
+ /* Data type */
+ struct reg_data_type *data_type;
+
+ struct list_head list;
+};
+
+/* Error codes */
+#define ERROR_ARC_REGISTER_NOT_FOUND (-700)
+#define ERROR_ARC_REGISTER_FIELD_NOT_FOUND (-701)
+#define ERROR_ARC_REGISTER_IS_NOT_STRUCT (-702)
+#define ERROR_ARC_FIELD_IS_NOT_BITFIELD (-703)
+#define ERROR_ARC_REGTYPE_NOT_FOUND (-704)
+
+void free_reg_desc(struct arc_reg_desc *r);
+
+
+void arc_reg_data_type_add(struct target *target,
+ struct arc_reg_data_type *data_type);
+
+int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg,
+ const char * const type_name, const size_t type_name_len);
+
+struct reg *arc_reg_get_by_name(struct reg_cache *first,
+ const char *name, bool search_all);
+
+int arc_reg_get_field(struct target *target, const char *reg_name,
+ const char *field_name, uint32_t *value_ptr);
+
+#endif /* OPENOCD_TARGET_ARC_H */
diff --git a/src/target/arc_cmd.c b/src/target/arc_cmd.c
new file mode 100644
index 000000000..3f6caf751
--- /dev/null
+++ b/src/target/arc_cmd.c
@@ -0,0 +1,977 @@
+/***************************************************************************
+ * Copyright (C) 2013-2015,2019-2020 Synopsys, Inc. *
+ * Frank Dols <fra...@sy...> *
+ * Mischa Jonker <mis...@sy...> *
+ * Anton Kolesov <ant...@sy...> *
+ * Evgeniy Didin <di...@sy...> *
+ * *
+ * SPDX-License-Identifier: GPL-2.0-or-later *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "arc.h"
+
+/* --------------------------------------------------------------------------
+ *
+ * ARC targets expose command interface.
+ * It can be accessed via GDB through the (gdb) monitor command.
+ *
+ * ------------------------------------------------------------------------- */
+
+
+static int arc_cmd_jim_get_uint32(Jim_GetOptInfo *goi, uint32_t *value)
+{
+ jim_wide value_wide;
+ JIM_CHECK_RETVAL(Jim_GetOpt_Wide(goi, &value_wide));
+ *value = (uint32_t)value_wide;
+ return JIM_OK;
+}
+
+enum add_reg_types {
+ CFG_ADD_REG_TYPE_FLAG,
+ CFG_ADD_REG_TYPE_STRUCT,
+};
+/* Add flags register data type */
+enum add_reg_type_flags {
+ CFG_ADD_REG_TYPE_FLAGS_NAME,
+ CFG_ADD_REG_TYPE_FLAGS_FLAG,
+};
+
+static Jim_Nvp nvp_add_reg_type_flags_opts[] = {
+ { .name = "-name", .value = CFG_ADD_REG_TYPE_FLAGS_NAME },
+ { .name = "-flag", .value = CFG_ADD_REG_TYPE_FLAGS_FLAG },
+ { .name = NULL, .value = -1 }
+};
+
+/* Helper function to check if all field required for register
+ * are set up */
+static const char *validate_register(const struct arc_reg_desc * const reg, bool arch_num_set)
+{
+ /* Check that required fields are set */
+ if (!reg->name)
+ return "-name option is required";
+ if (!reg->gdb_xml_feature)
+ return "-feature option is required";
+ if (!arch_num_set)
+ return "-num option is required";
+ if (reg->is_bcr && reg->is_core)
+ return "Register cannot be both -core and -bcr.";
+ return NULL;
+}
+
+/* Helper function to read the name of register type or register from
+ * configure files */
+static int jim_arc_read_reg_name_field(Jim_GetOptInfo *goi,
+ const char **name, int *name_len)
+{
+ int e = JIM_OK;
+
+ if (!goi->argc) {
+ Jim_WrongNumArgs(goi->interp, goi->argc, goi->argv, "-name <name> ...");
+ return JIM_ERR;
+ }
+ e = Jim_GetOpt_String(goi, name, name_len);
+ return e;
+}
+
+/* Helper function to read bitfields/flags of register type. */
+static int jim_arc_read_reg_type_field(Jim_GetOptInfo *goi, const char **field_name, int *field_name_len,
+ struct arc_reg_bitfield *bitfields, int cur_field, int type)
+{
+ jim_wide start_pos, end_pos;
+
+ int e = JIM_OK;
+ if ((type == CFG_ADD_REG_TYPE_STRUCT && goi->argc < 3) ||
+ (type == CFG_ADD_REG_TYPE_FLAG && goi->argc < 2)) {
+ Jim_SetResultFormatted(goi->interp, "Not enough argmunets after -flag/-bitfield");
+ return JIM_ERR;
+ }
+
+ e = Jim_GetOpt_String(goi, field_name, field_name_len);
+ if (e != JIM_OK)
+ return e;
+
+ /* read start position of bitfield/flag */
+ e = Jim_GetOpt_Wide(goi, &start_pos);
+ if (e != JIM_OK)
+ return e;
+
+ end_pos = start_pos;
+
+ /* Check if any argnuments remain,
+ * set bitfields[cur_field].end if flag is multibit */
+ if (goi->argc > 0)
+ /* Check current argv[0], if it is equal to "-flag",
+ * than bitfields[cur_field].end remains start */
+ if ((strcmp(Jim_String(goi->argv[0]), "-flag") && type == CFG_ADD_REG_TYPE_FLAG)
+ || (type == CFG_ADD_REG_TYPE_STRUCT)) {
+ e = Jim_GetOpt_Wide(goi, &end_pos);
+ if (e != JIM_OK) {
+ Jim_SetResultFormatted(goi->interp, "Error reading end position");
+ return e;
+ }
+ }
+
+ bitfields[cur_field].bitfield.start = start_pos;
+ bitfields[cur_field].bitfield.end = end_pos;
+ if ((end_pos != start_pos) || (type == CFG_ADD_REG_TYPE_STRUCT))
+ bitfields[cur_field].bitfield.type = REG_TYPE_INT;
+ return e;
+}
+
+static int jim_arc_add_reg_type_flags(Jim_Interp *interp, int argc,
+ Jim_Obj * const *argv)
+{
+ Jim_GetOptInfo goi;
+ JIM_CHECK_RETVAL(Jim_GetOpt_Setup(&goi, interp, argc-1, argv+1));
+
+ LOG_DEBUG("-");
+
+ struct command_context *ctx;
+ struct target *target;
+
+ ctx = current_command_context(interp);
+ assert(ctx);
+ target = get_current_target(ctx);
+ if (!target) {
+ Jim_SetResultFormatted(goi.interp, "No current target");
+ return JIM_ERR;
+ }
+
+ int e = JIM_OK;
+
+ /* Check if the amount of argnuments is not zero */
+ if (goi.argc <= 0) {
+ Jim_SetResultFormatted(goi.interp, "The command has no argnuments");
+ return JIM_ERR;
+ }
+
+ /* Estimate number of registers as (argc - 2)/3 as each -flag option has 2
+ * arguments while -name is required. */
+ unsigned int fields_sz = (goi.argc - 2) / 3;
+ unsigned int cur_field = 0;
+
+ /* Tha maximum amount of bitfilds is 32 */
+ if (fields_sz > 32) {
+ Jim_SetResultFormatted(goi.interp, "The amount of bitfields exceed 32");
+ return JIM_ERR;
+ }
+
+ struct arc_reg_data_type *type = calloc(1, sizeof(*type));
+ struct reg_data_type_flags *flags = &type->data_type_flags;
+ struct reg_data_type_flags_field *fields = calloc(fields_sz, sizeof(*fields));
+ struct arc_reg_bitfield *bitfields = calloc(fields_sz, sizeof(*type));
+ if (!(type && fields && bitfields)) {
+ Jim_SetResultFormatted(goi.interp, "Failed to allocate memory.");
+ goto fail;
+ }
+
+ /* Initialize type */
+ type->bitfields = bitfields;
+ type->data_type.id = type->data_type_id;
+ type->data_type.type = REG_TYPE_ARCH_DEFINED;
+ type->data_type.type_class = REG_TYPE_CLASS_FLAGS;
+ type->data_type.reg_type_flags = flags;
+ flags->size = 4; /* For now ARC has only 32-bit registers */
+
+ while (goi.argc > 0 && e == JIM_OK) {
+ Jim_Nvp *n;
+ e = Jim_GetOpt_Nvp(&goi, nvp_add_reg_type_flags_opts, &n);
+ if (e != JIM_OK) {
+ Jim_GetOpt_NvpUnknown(&goi, nvp_add_reg_type_flags_opts, 0);
+ continue;
+ }
+
+ switch (n->value) {
+ case CFG_ADD_REG_TYPE_FLAGS_NAME:
+ {
+ const char *name = NULL;
+ int name_len = 0;
+
+ e = jim_arc_read_reg_name_field(&goi, &name, &name_len);
+ if (e != JIM_OK) {
+ Jim_SetResultFormatted(goi.interp, "Unable to read reg name.");
+ goto fail;
+ }
+
+ if (name_len > REG_TYPE_MAX_NAME_LENGTH) {
+ Jim_SetResultFormatted(goi.interp, "Reg type name is too big.");
+ goto fail;
+ }
+
+ strncpy((void *)type->data_type.id, name, name_len);
+ if (!type->data_type.id) {
+ Jim_SetResultFormatted(goi.interp, "Unable to setup reg type name.");
+ goto fail;
+ }
+
+ break;
+ }
+
+ case CFG_ADD_REG_TYPE_FLAGS_FLAG:
+ {
+ const char *field_name = NULL;
+ int field_name_len = 0;
+
+ e = jim_arc_read_reg_type_field(&goi, &field_name, &field_name_len, bitfields,
+ cur_field, CFG_ADD_REG_TYPE_FLAG);
+ if (e != JIM_OK) {
+ Jim_SetResultFormatted(goi.interp, "Unable to add reg_type_flag field.");
+ goto fail;
+ }
+
+ if (field_name_len > REG_TYPE_MAX_NAME_LENGTH) {
+ ...
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