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commit c60252ac2b636c4d99b766a574b9df0966151696
Author: Andreas Fritiofson <and...@gm...>
Date:   Fri Apr 17 13:49:28 2020 +0200

    bitbang: Fix FTBFS with GCC 10
    
    GCC 10 defaults to -fno-common which breaks the sharing of bitbang_swd
    struct between bitbang drivers due to a missing extern.
    
    Change-Id: I2b4122f7939cec91a72284006748f99a23548324
    Signed-off-by: Andreas Fritiofson <and...@gm...>
    Reviewed-on: http://openocd.zylin.com/5592
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Jonathan McDowell <noo...@ea...>

diff --git a/src/jtag/drivers/bitbang.h b/src/jtag/drivers/bitbang.h
index edb779cad..bbbc693df 100644
--- a/src/jtag/drivers/bitbang.h
+++ b/src/jtag/drivers/bitbang.h
@@ -56,7 +56,7 @@ struct bitbang_interface {
 	void (*swdio_drive)(bool on);
 };
 
-const struct swd_driver bitbang_swd;
+extern const struct swd_driver bitbang_swd;
 
 extern bool swd_mode;
 

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/bitbang.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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commit bed0215573269cd9f85d23eaa15a27ce13a53e87
Author: Ilya Kharin <ak...@gm...>
Date:   Thu Apr 16 03:21:30 2020 +0400

    flash/nor/stm32l4x: cast wrpxxr_mask to uint16_to to print
    
    Fix build error on Mac OS X Catalina (10.15.4) caused by formatting
    stm32l4_info->wrpxxr_mask, which is uint32_t, as uint16_t in the debug
    log message. Adding casting to uint16_t before substitution because only
    lower 16 bits are significant for debug purposes.
    
    Change-Id: Iddb87cd156dfc84ab1f91cd15a1ddee6b646d412
    Signed-off-by: Ilya Kharin <ak...@gm...>
    Reviewed-on: http://openocd.zylin.com/5590
    Tested-by: jenkins
    Reviewed-by: Andreas Bolsch <hyp...@gm...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index 2cc378a90..4b7edae5f 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -1038,7 +1038,7 @@ static int stm32l4_probe(struct flash_bank *bank)
 	/* in dual bank mode number of pages is doubled, but extra bit is bank selection */
 	stm32l4_info->wrpxxr_mask = ((max_pages >> (stm32l4_info->dual_bank_mode ? 1 : 0)) - 1);
 	assert((stm32l4_info->wrpxxr_mask & 0xFFFF0000) == 0);
-	LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, stm32l4_info->wrpxxr_mask);
+	LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, (uint16_t)stm32l4_info->wrpxxr_mask);
 
 	if (bank->sectors) {
 		free(bank->sectors);

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/stm32l4x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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commit 38d205ecc5335191214dbd0f714f4561a7b7b746
Author: Leonard Crestez <leo...@nx...>
Date:   Thu Feb 6 16:13:25 2020 +0200

    ftdi: Report an error if no ftdi_vid_pid is specified
    
    By default the list of VID/PID is empty so if ftdi_vid_pid is not called
    then no matches are attempted. The only message is at -d3:
    
            Command 'init' failed with error code -100"
    
    Check for this condition explicitly to make life easier for people
    configuring adapters.
    
    Change-Id: If0f93370c9e9ddc9700aae7c346c1c6dd319152e
    Signed-off-by: Leonard Crestez <leo...@nx...>
    Reviewed-on: http://openocd.zylin.com/5440
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/jtag/drivers/ftdi.c b/src/jtag/drivers/ftdi.c
index 121cb469f..f1d28d2fd 100644
--- a/src/jtag/drivers/ftdi.c
+++ b/src/jtag/drivers/ftdi.c
@@ -647,6 +647,11 @@ static int ftdi_initialize(void)
 	else
 		LOG_DEBUG("ftdi interface using shortest path jtag state transitions");
 
+	if (!ftdi_vid[0] && !ftdi_pid[0]) {
+		LOG_ERROR("Please specify ftdi_vid_pid");
+		return ERROR_JTAG_INIT_FAILED;
+	}
+
 	for (int i = 0; ftdi_vid[i] || ftdi_pid[i]; i++) {
 		mpsse_ctx = mpsse_open(&ftdi_vid[i], &ftdi_pid[i], ftdi_device_desc,
 				ftdi_serial, jtag_usb_get_location(), ftdi_channel);

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/ftdi.c | 5 +++++
 1 file changed, 5 insertions(+)


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commit 86cf8d9fb0e9ef29d69b97d30aa5670814e00a24
Author: Kevin Burke <ke...@os...>
Date:   Mon Nov 4 20:11:06 2019 +0000

    target/armv8: Add ARM target name on halt status
    
    The CPU target name is added to the HALT status message so the user
    can see which target halted at the designated program counter.
    
    Tested on an Ampere eMAG8180 and Quicksilver silicon
    
    Change-Id: I51e6f21296c85a822df28c5b7c4068e8ff66f29e
    Signed-off-by: Kevin Burke <ke...@os...>
    Signed-off-by: Daniel Goehring <dgo...@os...>
    Reviewed-on: http://openocd.zylin.com/5571
    Tested-by: jenkins
    Reviewed-by: Tarek BOCHKATI <tar...@gm...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/armv8.c b/src/target/armv8.c
index 88b932073..61f11f24a 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -1131,8 +1131,9 @@ int armv8_aarch64_state(struct target *target)
 		return ERROR_FAIL;
 	}
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
+	LOG_USER("%s halted in %s state due to %s, current mode: %s\n"
 		"cpsr: 0x%8.8" PRIx32 " pc: 0x%" PRIx64 "%s",
+		target_name(target),
 		armv8_state_strings[arm->core_state],
 		debug_reason_name(target),
 		armv8_mode_name(arm->core_mode),

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv8.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)


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commit ff9ee132e52cf90275cfd9debee4c8d73412418e
Author: Tomas Vanek <va...@fb...>
Date:   Sun Oct 20 15:03:44 2019 +0200

    target/armv7m: minor fixes of target algo exit point check
    
    Introduce a new ERROR_TARGET_ALGO_EXIT as currently used
    ERROR_TARGET_TIMEOUT should be reserved for the timeout only.
    
    Do not load PC directly from CPU HW as the register value
    has already been cached.
    
    Change-Id: I0d3630da41fd021676789dc12b52545cc0432ba8
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: http://openocd.zylin.com/5329
    Tested-by: jenkins
    Reviewed-by: Christopher Head <ch...@za...>
    Reviewed-by: Tarek BOCHKATI <tar...@gm...>

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 82d6e6307..837ccc94e 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -462,7 +462,6 @@ int armv7m_wait_algorithm(struct target *target,
 	struct armv7m_common *armv7m = target_to_armv7m(target);
 	struct armv7m_algorithm *armv7m_algorithm_info = arch_info;
 	int retval = ERROR_OK;
-	uint32_t pc;
 
 	/* NOTE: armv7m_run_algorithm requires that each algorithm uses a software breakpoint
 	 * at the exit point */
@@ -484,12 +483,14 @@ int armv7m_wait_algorithm(struct target *target,
 		return ERROR_TARGET_TIMEOUT;
 	}
 
-	armv7m->load_core_reg_u32(target, 15, &pc);
-	if (exit_point && (pc != exit_point)) {
-		LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
-			pc,
-			exit_point);
-		return ERROR_TARGET_TIMEOUT;
+	if (exit_point) {
+		/* PC value has been cached in cortex_m_debug_entry() */
+		uint32_t pc = buf_get_u32(armv7m->arm.pc->value, 0, 32);
+		if (pc != exit_point) {
+			LOG_DEBUG("failed algorithm halted at 0x%" PRIx32 ", expected 0x%" TARGET_PRIxADDR,
+					  pc, exit_point);
+			return ERROR_TARGET_ALGO_EXIT;
+		}
 	}
 
 	/* Read memory values to mem_params[] */
diff --git a/src/target/target.h b/src/target/target.h
index ddeb00b57..fc150442d 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -759,6 +759,7 @@ void target_handle_md_output(struct command_invocation *cmd,
 #define ERROR_TARGET_NOT_RUNNING (-310)
 #define ERROR_TARGET_NOT_EXAMINED (-311)
 #define ERROR_TARGET_DUPLICATE_BREAKPOINT (-312)
+#define ERROR_TARGET_ALGO_EXIT  (-313)
 
 extern bool get_target_reset_nag(void);
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv7m.c | 15 ++++++++-------
 src/target/target.h |  1 +
 2 files changed, 9 insertions(+), 7 deletions(-)


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commit 6e86ad6166407ca993a8fd37e05269297d470796
Author: Tomas Vanek <va...@fb...>
Date:   Thu Nov 22 19:05:04 2018 +0100

    flash/nor: add flash mdw/h/b commands
    
    Some flash banks are not mapped in the target memory
    (e.g. SPI flash, some special pages).
    
    Add flash version of mdw/h/b which reads data using
    the flash driver.
    
    Change-Id: I66910e0a69cf523fe5ca1ed6ce7b9e8e176aef4a
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: http://openocd.zylin.com/4776
    Tested-by: jenkins
    Reviewed-by: Andreas Bolsch <hyp...@gm...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 35a41d4de..2dbe770ad 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5121,6 +5121,19 @@ each block, and the specified length must stay within that bank.
 @end deffn
 @comment no current checks for errors if fill blocks touch multiple banks!
 
+@deffn Command {flash mdw} addr [count]
+@deffnx Command {flash mdh} addr [count]
+@deffnx Command {flash mdb} addr [count]
+Display contents of address @var{addr}, as
+32-bit words (@command{mdw}), 16-bit halfwords (@command{mdh}),
+or 8-bit bytes (@command{mdb}).
+If @var{count} is specified, displays that many units.
+Reads from flash using the flash driver, therefore it enables reading
+from a bank not mapped in target address space.
+The flash bank to use is inferred from the @var{address} of
+each block, and the specified length must stay within that bank.
+@end deffn
+
 @deffn Command {flash write_bank} num filename [offset]
 Write the binary @file{filename} to flash bank @var{num},
 starting at @var{offset} bytes from the beginning of the bank. If @var{offset}
diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
index 30c5d4c80..00bfeb18e 100644
--- a/src/flash/nor/tcl.c
+++ b/src/flash/nor/tcl.c
@@ -628,6 +628,67 @@ done:
 	return retval;
 }
 
+COMMAND_HANDLER(handle_flash_md_command)
+{
+	int retval;
+
+	if (CMD_ARGC < 1 || CMD_ARGC > 2)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	target_addr_t address;
+	COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
+
+	uint32_t count = 1;
+	if (CMD_ARGC == 2)
+		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], count);
+
+	unsigned int wordsize;
+	switch (CMD_NAME[2]) {
+		case 'w':
+			wordsize = 4;
+			break;
+		case 'h':
+			wordsize = 2;
+			break;
+		case 'b':
+			wordsize = 1;
+			break;
+		default:
+			return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+
+	if (count == 0)
+		return ERROR_OK;
+
+	struct target *target = get_current_target(CMD_CTX);
+	struct flash_bank *bank;
+	retval = get_flash_bank_by_addr(target, address, true, &bank);
+	if (retval != ERROR_OK)
+		return retval;
+
+	uint32_t offset = address - bank->base;
+	uint32_t sizebytes = count * wordsize;
+	if (offset + sizebytes > bank->size) {
+		command_print(CMD, "Cannot cross flash bank borders");
+		return ERROR_FAIL;
+	}
+
+	uint8_t *buffer = calloc(count, wordsize);
+	if (buffer == NULL) {
+		command_print(CMD, "No memory for flash read buffer");
+		return ERROR_FAIL;
+	}
+
+	retval = flash_driver_read(bank, buffer, offset, sizebytes);
+	if (retval == ERROR_OK)
+		target_handle_md_output(CMD, target, address, wordsize, count, buffer);
+
+	free(buffer);
+
+	return retval;
+}
+
+
 COMMAND_HANDLER(handle_flash_write_bank_command)
 {
 	uint32_t offset;
@@ -1049,6 +1110,27 @@ static const struct command_registration flash_exec_command_handlers[] = {
 		.help = "Fill n bytes with 8-bit value, starting at "
 			"word address.  (No autoerase.)",
 	},
+	{
+		.name = "mdb",
+		.handler = handle_flash_md_command,
+		.mode = COMMAND_EXEC,
+		.usage = "address [count]",
+		.help = "Display bytes from flash.",
+	},
+	{
+		.name = "mdh",
+		.handler = handle_flash_md_command,
+		.mode = COMMAND_EXEC,
+		.usage = "address [count]",
+		.help = "Display half-words from flash.",
+	},
+	{
+		.name = "mdw",
+		.handler = handle_flash_md_command,
+		.mode = COMMAND_EXEC,
+		.usage = "address [count]",
+		.help = "Display words from flash.",
+	},
 	{
 		.name = "write_bank",
 		.handler = handle_flash_write_bank_command,

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi    | 13 +++++++++
 src/flash/nor/tcl.c | 82 +++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 95 insertions(+)


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- Log -----------------------------------------------------------------
commit 73a5f58adba73306b08b7bb22ff8a9511e79869f
Author: Tomas Vanek <va...@fb...>
Date:   Fri Mar 1 13:35:31 2019 +0100

    tcl/target/nrf52.cfg: detect AP lock and add command to recover
    
    Change-Id: I8d2e29ed88a957d412473255e42b022a00dfb9cb
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: http://openocd.zylin.com/4984
    Tested-by: jenkins

diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg
index 00901bf8a..88f2c6912 100644
--- a/tcl/target/nrf52.cfg
+++ b/tcl/target/nrf52.cfg
@@ -34,9 +34,82 @@ adapter speed 1000
 
 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
 
-if { ![using_hla] } {
+if { [using_hla] } {
+	echo ""
+	echo "nRF52 device has a CTRL-AP dedicated to recover the device from AP lock."
+	echo "A high level adapter (like a ST-Link) you are currently using cannot access"
+	echo "the CTRL-AP so 'nrf52_recover' command will not work."
+	echo "Do not enable UICR APPROTECT."
+	echo ""
+} else {
 	cortex_m reset_config sysresetreq
+
+	$_TARGETNAME configure -event examine-fail nrf52_check_ap_lock
 }
 
 flash bank $_CHIPNAME.flash nrf5 0x00000000 0 1 1 $_TARGETNAME
 flash bank $_CHIPNAME.uicr nrf5 0x10001000 0 1 1 $_TARGETNAME
+
+# Test if MEM-AP is locked by UICR APPROTECT
+proc nrf52_check_ap_lock {} {
+	set dap [[target current] cget -dap]
+	set err [catch {set APPROTECTSTATUS [ocd_$dap apreg 1 0xc]}]
+	if {$err == 0 && $APPROTECTSTATUS != 1} {
+		echo "****** WARNING ******"
+		echo "nRF52 device has AP lock engaged (see UICR APPROTECT register)."
+		echo "Debug access is denied."
+		echo "Use 'nrf52_recover' to erase and unlock the device."
+		echo ""
+		poll off
+	}
+}
+
+# Mass erase and unlock the device using proprietary nRF CTRL-AP (AP #1)
+# http://www.ebyte.com produces modules with nRF52 locked by default,
+# use nrf52_recover to enable flashing and debug.
+proc nrf52_recover {} {
+	set target [target current]
+	set dap [$target cget -dap]
+
+	set IDR [ocd_$dap apreg 1 0xfc]
+	if {$IDR != 0x02880000} {
+		echo "Error: Cannot access nRF52 CTRL-AP!"
+		return
+	}
+
+	poll off
+
+	# Assert reset
+	$dap apreg 1 0 1
+
+	# Reset ERASEALLSTATUS event
+	$dap apreg 1 8 0
+
+	# Trigger ERASEALL task
+	$dap apreg 1 4 0
+	$dap apreg 1 4 1
+
+	for {set i 0} {1} {incr i} {
+		set ERASEALLSTATUS [ocd_$dap apreg 1 8]
+		if {$ERASEALLSTATUS == 1} {
+			echo "$target device has been successfully erased and unlocked."
+			break
+		}
+		if {$i >= 5} {
+			echo "Error: $target recovery failed."
+			break
+		}
+		sleep 100
+	}
+
+	# Deassert reset
+	$dap apreg 1 0 0
+
+	if {$ERASEALLSTATUS == 1} {
+		sleep 100
+		$target arp_examine
+		poll on
+	}
+}
+
+add_help_text nrf52_recover "Mass erase and unlock nRF52 device"

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/nrf52.cfg | 75 +++++++++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 74 insertions(+), 1 deletion(-)


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- Log -----------------------------------------------------------------
commit ec16e522bf6518f38e8923ed4f271bc9bb23c409
Author: Aurélien Martin <mar...@gm...>
Date:   Tue Aug 6 22:08:18 2019 +0200

    nrf5: Comment the flash loader
    
    Change-Id: Ia84b5b8ede53f59299a02dc6163d6bbaa31e0fbd
    Signed-off-by: Aurélien Martin <mar...@gm...>
    Reviewed-on: http://openocd.zylin.com/5272
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/contrib/loaders/flash/nrf5/nrf5.S b/contrib/loaders/flash/nrf5/nrf5.S
index 6f7ed9ae7..53551a2c2 100644
--- a/contrib/loaders/flash/nrf5/nrf5.S
+++ b/contrib/loaders/flash/nrf5/nrf5.S
@@ -35,24 +35,35 @@
 	.global _start
 _start:
 wait_fifo:
+	// Kick the watchdog
 	str	r6, [r7, #0]
+	// Load write pointer
 	ldr	r5, [r1, #0]
+	// Abort if it is NULL
 	cmp	r5, #0
 	beq.n	exit
+	// Load read pointer
 	ldr	r4, [r1, #4]
+	// Continue waiting if it equals the write pointer
 	cmp	r4, r5
 	beq.n	wait_fifo
+	// Copy one word from buffer to target, and increment pointers
 	ldmia	r4!, {r5}
 	stmia	r3!, {r5}
+	// If at end of buffer, wrap back to buffer start
 	cmp	r4, r2
 	bcc.n   no_wrap
 	mov	r4, r1
 	adds	r4, #8
 no_wrap:
+	// Update read pointer inside the buffer
 	str	r4, [r1, #4]
+	// Deduce the word transferred from the byte count
 	subs	r0, #4
+	// Start again
 	bne.n   wait_fifo
 exit:
+	// Wait for OpenOCD
 	bkpt	#0x00
 
 	.pool

-----------------------------------------------------------------------

Summary of changes:
 contrib/loaders/flash/nrf5/nrf5.S | 11 +++++++++++
 1 file changed, 11 insertions(+)


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commit 3c8aa12859e909b4d14162bd7578bf84571bac20
Author: Aurélien Martin <mar...@gm...>
Date:   Mon Jul 22 23:13:29 2019 +0200

    nrf5: Refresh the watchdog while flashing
    
    If watchdog is enabled, there's no way we can disable it while the flashing firmware
    is running. (Halt disables it, but software reset doesn't.) So let's have the flashing
    firmware refresh the watchdog regularly, in case it has been enabled by previously
    running software. Failure to do so could lead to a watchdog reset in the middle of
    the chip bieng programmed.
    
    Change-Id: I79d41593948aae0080480e891552e1c2ee3ccbd0
    Signed-off-by: Aurélien Martin <mar...@gm...>
    Reviewed-on: http://openocd.zylin.com/5266
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/contrib/loaders/flash/nrf5/nrf5.S b/contrib/loaders/flash/nrf5/nrf5.S
index b148e3caf..6f7ed9ae7 100644
--- a/contrib/loaders/flash/nrf5/nrf5.S
+++ b/contrib/loaders/flash/nrf5/nrf5.S
@@ -27,12 +27,15 @@
  * r1 = buffer start
  * r2 = buffer end
  * r3 = target address
+ * r6 = watchdog refresh value
+ * r7 = watchdog refresh register address
  */
 
 	.thumb_func
 	.global _start
 _start:
 wait_fifo:
+	str	r6, [r7, #0]
 	ldr	r5, [r1, #0]
 	cmp	r5, #0
 	beq.n	exit
diff --git a/contrib/loaders/flash/nrf5/nrf5.inc b/contrib/loaders/flash/nrf5/nrf5.inc
index a9b185c45..2b35b5d6d 100644
--- a/contrib/loaders/flash/nrf5/nrf5.inc
+++ b/contrib/loaders/flash/nrf5/nrf5.inc
@@ -1,3 +1,4 @@
 /* Autogenerated with ../../../../src/helper/bin2char.sh */
-0x0d,0x68,0x00,0x2d,0x0b,0xd0,0x4c,0x68,0xac,0x42,0xf9,0xd0,0x20,0xcc,0x20,0xc3,
-0x94,0x42,0x01,0xd3,0x0c,0x46,0x08,0x34,0x4c,0x60,0x04,0x38,0xf0,0xd1,0x00,0xbe,
+0x3e,0x60,0x0d,0x68,0x00,0x2d,0x0b,0xd0,0x4c,0x68,0xac,0x42,0xf8,0xd0,0x20,0xcc,
+0x20,0xc3,0x94,0x42,0x01,0xd3,0x0c,0x46,0x08,0x34,0x4c,0x60,0x04,0x38,0xef,0xd1,
+0x00,0xbe,
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index c569c1800..fa67e2bf3 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -28,6 +28,10 @@
 #include <helper/types.h>
 #include <helper/time_support.h>
 
+/* Both those values are constant across the current spectrum ofr nRF5 devices */
+#define WATCHDOG_REFRESH_REGISTER       0x40010600
+#define WATCHDOG_REFRESH_VALUE          0x6e524635
+
 enum {
 	NRF5_FLASH_BASE = 0x00000000,
 };
@@ -907,7 +911,7 @@ static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const u
 	uint32_t buffer_size = 8192;
 	struct working_area *write_algorithm;
 	struct working_area *source;
-	struct reg_param reg_params[4];
+	struct reg_param reg_params[6];
 	struct armv7m_algorithm armv7m_info;
 	int retval = ERROR_OK;
 
@@ -965,15 +969,19 @@ static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const u
 	init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);	/* buffer start */
 	init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);	/* buffer end */
 	init_reg_param(&reg_params[3], "r3", 32, PARAM_IN_OUT);	/* target address */
+	init_reg_param(&reg_params[4], "r6", 32, PARAM_OUT);	/* watchdog refresh value */
+	init_reg_param(&reg_params[5], "r7", 32, PARAM_OUT);	/* watchdog refresh register address */
 
 	buf_set_u32(reg_params[0].value, 0, 32, bytes);
 	buf_set_u32(reg_params[1].value, 0, 32, source->address);
 	buf_set_u32(reg_params[2].value, 0, 32, source->address + source->size);
 	buf_set_u32(reg_params[3].value, 0, 32, address);
+	buf_set_u32(reg_params[4].value, 0, 32, WATCHDOG_REFRESH_VALUE);
+	buf_set_u32(reg_params[5].value, 0, 32, WATCHDOG_REFRESH_REGISTER);
 
 	retval = target_run_flash_async_algorithm(target, buffer, bytes/4, 4,
 			0, NULL,
-			4, reg_params,
+			ARRAY_SIZE(reg_params), reg_params,
 			source->address, source->size,
 			write_algorithm->address, 0,
 			&armv7m_info);
@@ -985,6 +993,8 @@ static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const u
 	destroy_reg_param(&reg_params[1]);
 	destroy_reg_param(&reg_params[2]);
 	destroy_reg_param(&reg_params[3]);
+	destroy_reg_param(&reg_params[4]);
+	destroy_reg_param(&reg_params[5]);
 
 	return retval;
 }

-----------------------------------------------------------------------

Summary of changes:
 contrib/loaders/flash/nrf5/nrf5.S   |  3 +++
 contrib/loaders/flash/nrf5/nrf5.inc |  5 +++--
 src/flash/nor/nrf5.c                | 14 ++++++++++++--
 3 files changed, 18 insertions(+), 4 deletions(-)


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commit 65d8fdf0d1e7aa931dd70cb2b0784473fe7834e1
Author: Aurélien Martin <mar...@gm...>
Date:   Tue Jul 23 21:21:39 2019 +0200

    nrf5: Include generated loader code
    
    Dump legacy hexadecimal machine code
    
    Change-Id: I336efa461058bccc3894131cb22473785b68479c
    Signed-off-by: Aurélien Martin <mar...@gm...>
    Reviewed-on: http://openocd.zylin.com/5267
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/contrib/loaders/flash/nrf5/Makefile b/contrib/loaders/flash/nrf5/Makefile
new file mode 100644
index 000000000..67390b9bd
--- /dev/null
+++ b/contrib/loaders/flash/nrf5/Makefile
@@ -0,0 +1,28 @@
+BIN2C = ../../../../src/helper/bin2char.sh
+
+CROSS_COMPILE ?= arm-none-eabi-
+
+CC=$(CROSS_COMPILE)gcc
+OBJCOPY=$(CROSS_COMPILE)objcopy
+OBJDUMP=$(CROSS_COMPILE)objdump
+
+CFLAGS = -static -nostartfiles -mlittle-endian -Wa,-EL
+
+all: nrf5.inc
+
+.PHONY: clean
+
+%.elf: %.S
+	$(CC) $(CFLAGS) $< -o $@
+
+%.lst: %.elf
+	$(OBJDUMP) -S $< > $@
+
+%.bin: %.elf
+	$(OBJCOPY) -Obinary $< $@
+
+%.inc: %.bin
+	$(BIN2C) < $< > $@
+
+clean:
+	-rm -f *.elf *.lst *.bin *.inc
diff --git a/contrib/loaders/flash/nrf5/nrf5.S b/contrib/loaders/flash/nrf5/nrf5.S
new file mode 100644
index 000000000..b148e3caf
--- /dev/null
+++ b/contrib/loaders/flash/nrf5/nrf5.S
@@ -0,0 +1,55 @@
+/***************************************************************************
+ *   Copyright (C) 2014 Angus Gratton                                      *
+ *   gu...@pr...                                                    *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.                                        *
+ ***************************************************************************/
+
+	.text
+	.syntax unified
+	.thumb
+
+/*
+ * Params :
+ * r0 = byte count
+ * r1 = buffer start
+ * r2 = buffer end
+ * r3 = target address
+ */
+
+	.thumb_func
+	.global _start
+_start:
+wait_fifo:
+	ldr	r5, [r1, #0]
+	cmp	r5, #0
+	beq.n	exit
+	ldr	r4, [r1, #4]
+	cmp	r4, r5
+	beq.n	wait_fifo
+	ldmia	r4!, {r5}
+	stmia	r3!, {r5}
+	cmp	r4, r2
+	bcc.n   no_wrap
+	mov	r4, r1
+	adds	r4, #8
+no_wrap:
+	str	r4, [r1, #4]
+	subs	r0, #4
+	bne.n   wait_fifo
+exit:
+	bkpt	#0x00
+
+	.pool
diff --git a/contrib/loaders/flash/nrf5/nrf5.inc b/contrib/loaders/flash/nrf5/nrf5.inc
new file mode 100644
index 000000000..a9b185c45
--- /dev/null
+++ b/contrib/loaders/flash/nrf5/nrf5.inc
@@ -0,0 +1,3 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
+0x0d,0x68,0x00,0x2d,0x0b,0xd0,0x4c,0x68,0xac,0x42,0xf9,0xd0,0x20,0xcc,0x20,0xc3,
+0x94,0x42,0x01,0xd3,0x0c,0x46,0x08,0x34,0x4c,0x60,0x04,0x38,0xf0,0xd1,0x00,0xbe,
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index 5bef8487c..c569c1800 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -900,30 +900,6 @@ static int nrf5_erase_page(struct flash_bank *bank,
 	return res;
 }
 
-static const uint8_t nrf5_flash_write_code[] = {
-	/* See contrib/loaders/flash/cortex-m0.S */
-/* <wait_fifo>: */
-	0x0d, 0x68,		/* ldr	r5,	[r1,	#0] */
-	0x00, 0x2d,		/* cmp	r5,	#0 */
-	0x0b, 0xd0,		/* beq.n	1e <exit> */
-	0x4c, 0x68,		/* ldr	r4,	[r1,	#4] */
-	0xac, 0x42,		/* cmp	r4,	r5 */
-	0xf9, 0xd0,		/* beq.n	0 <wait_fifo> */
-	0x20, 0xcc,		/* ldmia	r4!,	{r5} */
-	0x20, 0xc3,		/* stmia	r3!,	{r5} */
-	0x94, 0x42,		/* cmp	r4,	r2 */
-	0x01, 0xd3,		/* bcc.n	18 <no_wrap> */
-	0x0c, 0x46,		/* mov	r4,	r1 */
-	0x08, 0x34,		/* adds	r4,	#8 */
-/* <no_wrap>: */
-	0x4c, 0x60,		/* str	r4, [r1,	#4] */
-	0x04, 0x38,		/* subs	r0, #4 */
-	0xf0, 0xd1,		/* bne.n	0 <wait_fifo> */
-/* <exit>: */
-	0x00, 0xbe		/* bkpt	0x0000 */
-};
-
-
 /* Start a low level flash write for the specified region */
 static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const uint8_t *buffer, uint32_t bytes)
 {
@@ -935,6 +911,10 @@ static int nrf5_ll_flash_write(struct nrf5_info *chip, uint32_t address, const u
 	struct armv7m_algorithm armv7m_info;
 	int retval = ERROR_OK;
 
+	static const uint8_t nrf5_flash_write_code[] = {
+#include "../../../contrib/loaders/flash/nrf5/nrf5.inc"
+	};
+
 	LOG_DEBUG("Writing buffer to flash address=0x%"PRIx32" bytes=0x%"PRIx32, address, bytes);
 	assert(bytes % 4 == 0);
 

-----------------------------------------------------------------------

Summary of changes:
 contrib/loaders/flash/{stm32 => nrf5}/Makefile     |  2 +-
 .../armv4_5_erase_check.s => flash/nrf5/nrf5.S}    | 56 ++++++++++++++--------
 contrib/loaders/flash/nrf5/nrf5.inc                |  3 ++
 src/flash/nor/nrf5.c                               | 28 ++---------
 4 files changed, 44 insertions(+), 45 deletions(-)
 copy contrib/loaders/flash/{stm32 => nrf5}/Makefile (86%)
 copy contrib/loaders/{erase_check/armv4_5_erase_check.s => flash/nrf5/nrf5.S} (65%)
 create mode 100644 contrib/loaders/flash/nrf5/nrf5.inc


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commit 5c6e32612df3360abe0ada4e434783b5636643f2
Author: Florian Fainelli <f.f...@gm...>
Date:   Mon Jun 17 15:46:11 2019 -0700

    Remove BUILD_TARGET64
    
    BUILD_TARGET64 creates a larger test matrix and mostly gates the
    building of the aarch64/armv8 target, make that unconditional, which
    would help fixing any issues with 64-bit address types anyway.
    
    Rebased by Antonio Borneo after commit 1fbe8450a9dd ("mips: Add
    MIPS64 support")
    
    Change-Id: I219f62b744d540d9dde9a42e6b63fd7d91df3dbb
    Suggested-by: Matthias Welwarsky <mat...@we...>
    Signed-off-by: Florian Fainelli <f.f...@gm...>
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5240
    Tested-by: jenkins

diff --git a/configure.ac b/configure.ac
index 1c921fb1c..a6bda8856 100644
--- a/configure.ac
+++ b/configure.ac
@@ -360,10 +360,6 @@ AC_ARG_ENABLE([internal-libjaylink],
   [Disable building internal libjaylink]),
   [use_internal_libjaylink=$enableval], [use_internal_libjaylink=yes])
 
-AC_ARG_ENABLE([target64],
-  AS_HELP_STRING([--disable-target64], [Disable 64-bit target address]),
-    [build_target64=$enableval], [build_target64=yes])
-
 build_minidriver=no
 AC_MSG_CHECKING([whether to enable ZY1000 minidriver])
 AS_IF([test "x$build_zy1000" = "xyes"], [
@@ -617,13 +613,6 @@ AS_IF([test "x$build_xlnx_pcie_xvc" = "xyes"], [
   AC_DEFINE([BUILD_XLNX_PCIE_XVC], [0], [0 if you don't want Xilinx XVC/PCIe driver.])
 ])
 
-AS_IF([test "x$build_target64" = "xyes"], [
-  AC_DEFINE([BUILD_TARGET64], [1], [1 if you want 64-bit addresses.])
-], [
-  AC_DEFINE([BUILD_TARGET64], [0], [0 if you don't want 64-bit addresses.])
-])
-
-
 PKG_CHECK_MODULES([LIBUSB1], [libusb-1.0], [
 	use_libusb1=yes
 	AC_DEFINE([HAVE_LIBUSB1], [1], [Define if you have libusb-1.x])
@@ -746,7 +735,6 @@ AM_CONDITIONAL([BITQ], [test "x$build_bitq" = "xyes"])
 AM_CONDITIONAL([USE_LIBFTDI], [test "x$use_libftdi" = "xyes"])
 AM_CONDITIONAL([USE_HIDAPI], [test "x$use_hidapi" = "xyes"])
 AM_CONDITIONAL([USE_LIBJAYLINK], [test "x$use_libjaylink" = "xyes"])
-AM_CONDITIONAL([TARGET64], [test "x$build_target64" = "xyes"])
 AM_CONDITIONAL([RSHIM], [test "x$build_rshim" = "xyes"])
 
 AM_CONDITIONAL([MINIDRIVER], [test "x$build_minidriver" = "xyes"])
diff --git a/src/helper/types.h b/src/helper/types.h
index b6747f8d4..f3d5e04a3 100644
--- a/src/helper/types.h
+++ b/src/helper/types.h
@@ -349,7 +349,6 @@ typedef uint64_t uintmax_t;
 
 #endif
 
-#if BUILD_TARGET64
 typedef uint64_t target_addr_t;
 #define TARGET_ADDR_MAX UINT64_MAX
 #define TARGET_PRIdADDR PRId64
@@ -357,15 +356,6 @@ typedef uint64_t target_addr_t;
 #define TARGET_PRIoADDR PRIo64
 #define TARGET_PRIxADDR PRIx64
 #define TARGET_PRIXADDR PRIX64
-#else
-typedef uint32_t target_addr_t;
-#define TARGET_ADDR_MAX UINT32_MAX
-#define TARGET_PRIdADDR PRId32
-#define TARGET_PRIuADDR PRIu32
-#define TARGET_PRIoADDR PRIo32
-#define TARGET_PRIxADDR PRIx32
-#define TARGET_PRIXADDR PRIX32
-#endif
 #define TARGET_ADDR_FMT "0x%8.8" TARGET_PRIxADDR
 
 #endif /* OPENOCD_HELPER_TYPES_H */
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 30d2339bf..42d809d01 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -29,12 +29,9 @@ noinst_LTLIBRARIES += %D%/libtarget.la
 	%D%/dsp563xx.c \
 	%D%/dsp563xx_once.c \
 	%D%/dsp5680xx.c \
-	%D%/hla_target.c
-
-if TARGET64
-%C%_libtarget_la_SOURCES +=$(ARMV8_SRC)
-%C%_libtarget_la_SOURCES +=$(MIPS64_SRC)
-endif
+	%D%/hla_target.c \
+	$(ARMV8_SRC) \
+	$(MIPS64_SRC)
 
 TARGET_CORE_SRC = \
 	%D%/algorithm.c \
diff --git a/src/target/armv7a_mmu.c b/src/target/armv7a_mmu.c
index f83228d55..eec14a36f 100644
--- a/src/target/armv7a_mmu.c
+++ b/src/target/armv7a_mmu.c
@@ -62,12 +62,6 @@ int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
 
 	/* decode memory attribute */
 	SS = (value >> 1) & 1;
-#if !BUILD_TARGET64
-	if (SS) {
-		LOG_ERROR("Super section found with no-64 bit address support");
-		return ERROR_FAIL;
-	}
-#endif
 	NOS = (value >> 10) & 1;	/*  Not Outer shareable */
 	NS = (value >> 9) & 1;	/* Non secure */
 	INNER = (value >> 4) &  0x7;
diff --git a/src/target/mips64.c b/src/target/mips64.c
index f65aec114..6a7c4252b 100644
--- a/src/target/mips64.c
+++ b/src/target/mips64.c
@@ -18,8 +18,6 @@
 #include "config.h"
 #endif
 
-#if BUILD_TARGET64 == 1
-
 #include "mips64.h"
 
 static const struct {
@@ -623,5 +621,3 @@ int mips64_enable_interrupts(struct target *target, bool enable)
 
 	return ERROR_OK;
 }
-
-#endif /* BUILD_TARGET64 */
diff --git a/src/target/mips64_pracc.c b/src/target/mips64_pracc.c
index 57addc72a..b19fd044e 100644
--- a/src/target/mips64_pracc.c
+++ b/src/target/mips64_pracc.c
@@ -17,8 +17,6 @@
 #include "config.h"
 #endif
 
-#if BUILD_TARGET64 == 1
-
 #include "mips64.h"
 #include "mips64_pracc.h"
 
@@ -1427,5 +1425,3 @@ int mips64_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info,
 
 	return retval;
 }
-
-#endif /* BUILD_TARGET64 */
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 00bafd033..3735cbb67 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -27,11 +27,8 @@
 #include "mips32.h"
 #include "mips_ejtag.h"
 #include "mips32_dmaacc.h"
-
-#if BUILD_TARGET64 == 1
 #include "mips64.h"
 #include "mips64_pracc.h"
-#endif
 
 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, uint32_t new_instr)
 {
@@ -458,8 +455,6 @@ int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_
 	return ERROR_OK;
 }
 
-#if BUILD_TARGET64 == 1
-
 int mips64_ejtag_config_step(struct mips_ejtag *ejtag_info, bool enable_step)
 {
 	const uint32_t code_enable[] = {
@@ -564,5 +559,3 @@ int mips64_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, bool write_t, uint
 
 	return ERROR_OK;
 }
-
-#endif /* BUILD_TARGET64 */
diff --git a/src/target/mips_mips64.c b/src/target/mips_mips64.c
index d91700dfe..3a592f7f3 100644
--- a/src/target/mips_mips64.c
+++ b/src/target/mips_mips64.c
@@ -16,8 +16,6 @@
 #include "config.h"
 #endif
 
-#if BUILD_TARGET64 == 1
-
 #include "breakpoints.h"
 #include "mips32.h"
 #include "mips64.h"
@@ -1193,5 +1191,3 @@ struct target_type mips_mips64_target = {
 
 	.commands = mips64_commands_handlers,
 };
-
-#endif /* BUILD_TARGET64 */
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 66218b76e..8307b0224 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -1892,11 +1892,9 @@ static target_addr_t sb_read_address(struct target *target)
 	target_addr_t address = 0;
 	uint32_t v;
 	if (sbasize > 32) {
-#if BUILD_TARGET64
 		dmi_read(target, &v, DMI_SBADDRESS1);
 		address |= v;
 		address <<= 32;
-#endif
 	}
 	dmi_read(target, &v, DMI_SBADDRESS0);
 	address |= v;
@@ -1913,11 +1911,7 @@ static int sb_write_address(struct target *target, target_addr_t address)
 	if (sbasize > 64)
 		dmi_write(target, DMI_SBADDRESS2, 0);
 	if (sbasize > 32)
-#if BUILD_TARGET64
 		dmi_write(target, DMI_SBADDRESS1, address >> 32);
-#else
-		dmi_write(target, DMI_SBADDRESS1, 0);
-#endif
 	return dmi_write(target, DMI_SBADDRESS0, address);
 }
 
diff --git a/src/target/target.c b/src/target/target.c
index 24fa416f8..538831b5b 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -148,10 +148,8 @@ static struct target_type *target_types[] = {
 	&mem_ap_target,
 	&esirisc_target,
 	&arcv2_target,
-#if BUILD_TARGET64
 	&aarch64_target,
 	&mips_mips64_target,
-#endif
 	NULL,
 };
 

-----------------------------------------------------------------------

Summary of changes:
 configure.ac                 | 12 ------------
 src/helper/types.h           | 10 ----------
 src/target/Makefile.am       |  9 +++------
 src/target/armv7a_mmu.c      |  6 ------
 src/target/mips64.c          |  4 ----
 src/target/mips64_pracc.c    |  4 ----
 src/target/mips_ejtag.c      |  7 -------
 src/target/mips_mips64.c     |  4 ----
 src/target/riscv/riscv-013.c |  6 ------
 src/target/target.c          |  2 --
 10 files changed, 3 insertions(+), 61 deletions(-)


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- Log -----------------------------------------------------------------
commit 5c8de6a7253641bf1e4789bdc3b1e89ab741b1d1
Author: Liming Sun <ls...@me...>
Date:   Fri Apr 3 22:51:13 2020 -0400

    jtag/drivers/rshim: Disable the driver by default
    
    This is a follow-up change of commit 6d6a69d5 to disable it by
    default. The driver was introduced in 6d6a69d5 and enabled by
    default in order to run the jenkins build.
    
    Signed-off-by: Liming Sun <ls...@me...>
    Change-Id: I5c5fc6711b971b65dd5846a6163025879044ec40
    Reviewed-on: http://openocd.zylin.com/5563
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/configure.ac b/configure.ac
index 9c2f1d7ea..1c921fb1c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -222,11 +222,9 @@ AC_ARG_ENABLE([dummy],
   AS_HELP_STRING([--enable-dummy], [Enable building the dummy port driver]),
   [build_dummy=$enableval], [build_dummy=no])
 
-AS_CASE([$host_os], [linux*], [host_os_linux=yes], [host_os_linux=no])
-
 AC_ARG_ENABLE([rshim],
   AS_HELP_STRING([--enable-rshim], [Enable building the rshim driver]),
-  [build_rshim=$enableval], [build_rshim=$host_os_linux])
+  [build_rshim=$enableval], [build_rshim=no])
 
 m4_define([AC_ARG_ADAPTERS], [
   m4_foreach([adapter], [$1],

commit 699a8475a1cdc4a374470f1269106534102db148
Author: Liming Sun <ls...@me...>
Date:   Fri May 10 11:02:31 2019 -0400

    jtag/drivers: add debugging support for Mellanox BlueField SoC
    
    This commits adds debugging support for the Mellanox BlueField
    SoC via rshim, which is an interface accessible from external USB
    or PCIe (for SmartNIC case) via the rshim driver. It implements
    the arm dap interfaces based on the existing dapdirect framework.
    
    Change-Id: I18eb1c54293ec2c581f853e0e55b3f96d7978b56
    Signed-off-by: Liming Sun <ls...@me...>
    Reviewed-on: http://openocd.zylin.com/5457
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/configure.ac b/configure.ac
index 497b15fd1..9c2f1d7ea 100644
--- a/configure.ac
+++ b/configure.ac
@@ -222,6 +222,12 @@ AC_ARG_ENABLE([dummy],
   AS_HELP_STRING([--enable-dummy], [Enable building the dummy port driver]),
   [build_dummy=$enableval], [build_dummy=no])
 
+AS_CASE([$host_os], [linux*], [host_os_linux=yes], [host_os_linux=no])
+
+AC_ARG_ENABLE([rshim],
+  AS_HELP_STRING([--enable-rshim], [Enable building the rshim driver]),
+  [build_rshim=$enableval], [build_rshim=$host_os_linux])
+
 m4_define([AC_ARG_ADAPTERS], [
   m4_foreach([adapter], [$1],
 	[AC_ARG_ENABLE(ADAPTER_OPT([adapter]),
@@ -334,6 +340,13 @@ AS_CASE([$host_os],
     AS_IF([test "x$build_xlnx_pcie_xvc" = "xyes"], [
       AC_MSG_ERROR([xlnx_pcie_xvc is only available on linux])
     ])
+
+    AS_CASE([$host_os], [freebsd*], [],
+    [
+      AS_IF([test "x$build_rshim" = "xyes"], [
+        AC_MSG_ERROR([build_rshim is only available on linux or freebsd])
+      ])
+    ])
 ])
 
 AC_ARG_ENABLE([minidriver_dummy],
@@ -482,6 +495,12 @@ AS_IF([test "x$build_parport" = "xyes"], [
   AC_DEFINE([BUILD_PARPORT], [0], [0 if you don't want parport.])
 ])
 
+AS_IF([test "x$build_rshim" = "xyes"], [
+  AC_DEFINE([BUILD_RSHIM], [1], [1 if you want to debug BlueField SoC via rshim.])
+], [
+  AC_DEFINE([BUILD_RSHIM], [0], [0 if you don't want to debug BlueField SoC via rshim.])
+])
+
 AS_IF([test "x$build_dummy" = "xyes"], [
   build_bitbang=yes
   AC_DEFINE([BUILD_DUMMY], [1], [1 if you want dummy driver.])
@@ -730,6 +749,7 @@ AM_CONDITIONAL([USE_LIBFTDI], [test "x$use_libftdi" = "xyes"])
 AM_CONDITIONAL([USE_HIDAPI], [test "x$use_hidapi" = "xyes"])
 AM_CONDITIONAL([USE_LIBJAYLINK], [test "x$use_libjaylink" = "xyes"])
 AM_CONDITIONAL([TARGET64], [test "x$build_target64" = "xyes"])
+AM_CONDITIONAL([RSHIM], [test "x$build_rshim" = "xyes"])
 
 AM_CONDITIONAL([MINIDRIVER], [test "x$build_minidriver" = "xyes"])
 AM_CONDITIONAL([MINIDRIVER_DUMMY], [test "x$build_minidriver_dummy" = "xyes"])
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index aea09b38c..ba758e720 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -133,6 +133,9 @@ if HLADAPTER
 DRIVERFILES += %D%/stlink_usb.c
 DRIVERFILES += %D%/ti_icdi_usb.c
 endif
+if RSHIM
+DRIVERFILES += %D%/rshim.c
+endif
 if OSBDM
 DRIVERFILES += %D%/osbdm.c
 endif
diff --git a/src/jtag/drivers/rshim.c b/src/jtag/drivers/rshim.c
new file mode 100644
index 000000000..c718af5d2
--- /dev/null
+++ b/src/jtag/drivers/rshim.c
@@ -0,0 +1,523 @@
+/*
+ * Copyright (c) 2020, Mellanox Technologies Ltd. - All Rights Reserved
+ * Liming Sun <ls...@me...>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <helper/types.h>
+#include <helper/system.h>
+#include <helper/time_support.h>
+#include <helper/list.h>
+#include <jtag/interface.h>
+#ifdef HAVE_SYS_IOCTL_H
+#include <sys/ioctl.h>
+#endif
+#include <target/arm_adi_v5.h>
+#include <transport/transport.h>
+
+/* Rshim channel where the CoreSight register resides. */
+#define RSH_MMIO_CHANNEL_RSHIM	0x1
+
+/* APB and tile address translation. */
+#define RSH_CS_ROM_BASE		0x80000000
+#define RSH_CS_TILE_BASE	0x44000000
+#define RSH_CS_TILE_SIZE	0x04000000
+
+/*
+ * APB-AP Identification Register
+ * The default value is defined in "CoreSight on-chip trace and debug
+ * (Revision: r1p0)", Section 3.16.5 APB-AP register summary.
+ */
+#define APB_AP_IDR			0x44770002
+
+/* CoreSight register definition. */
+#define RSH_CORESIGHT_CTL		0x0e00
+#define RSH_CORESIGHT_CTL_GO_SHIFT	0
+#define RSH_CORESIGHT_CTL_GO_MASK	0x1ULL
+#define RSH_CORESIGHT_CTL_ACTION_SHIFT	1
+#define RSH_CORESIGHT_CTL_ACTION_MASK	0x2ULL
+#define RSH_CORESIGHT_CTL_ADDR_SHIFT	2
+#define RSH_CORESIGHT_CTL_ADDR_MASK	0x7ffffffcULL
+#define RSH_CORESIGHT_CTL_ERR_SHIFT	31
+#define RSH_CORESIGHT_CTL_ERR_MASK	0x80000000ULL
+#define RSH_CORESIGHT_CTL_DATA_SHIFT	32
+#define RSH_CORESIGHT_CTL_DATA_MASK	0xffffffff00000000ULL
+
+/* Util macros to access the CoreSight register. */
+#define RSH_CS_GET_FIELD(reg, field) \
+	(((uint64_t)(reg) & RSH_CORESIGHT_CTL_##field##_MASK) >> \
+		RSH_CORESIGHT_CTL_##field##_SHIFT)
+
+#define RSH_CS_SET_FIELD(reg, field, value) \
+	(reg) = (((reg) & ~RSH_CORESIGHT_CTL_##field##_MASK) | \
+		(((uint64_t)(value) << RSH_CORESIGHT_CTL_##field##_SHIFT) & \
+		RSH_CORESIGHT_CTL_##field##_MASK))
+
+#ifdef HAVE_SYS_IOCTL_H
+/* Message used to program rshim via ioctl(). */
+typedef struct {
+	uint32_t addr;
+	uint64_t data;
+} __attribute__((packed)) rshim_ioctl_msg;
+
+enum {
+	RSH_IOC_READ = _IOWR('R', 0, rshim_ioctl_msg),
+	RSH_IOC_WRITE = _IOWR('R', 1, rshim_ioctl_msg),
+};
+#endif
+
+/* Use local variable stub for DP/AP registers. */
+static uint32_t dp_ctrl_stat;
+static uint32_t dp_id_code;
+static uint32_t ap_sel, ap_bank;
+static uint32_t ap_csw;
+static uint32_t ap_drw;
+static uint32_t ap_tar, ap_tar_inc;
+
+/* Static functions to read/write via rshim/coresight. */
+static int (*rshim_read)(int chan, int addr, uint64_t *value);
+static int (*rshim_write)(int chan, int addr, uint64_t value);
+static int coresight_write(uint32_t tile, uint32_t addr, uint32_t wdata);
+static int coresight_read(uint32_t tile, uint32_t addr, uint32_t *value);
+
+/* RShim file handler. */
+static int rshim_fd = -1;
+
+/* DAP error code. */
+static int rshim_dap_retval = ERROR_OK;
+
+/* Default rshim device. */
+#define RSHIM_DEV_PATH_DEFAULT	"/dev/rshim0/rshim"
+static char *rshim_dev_path;
+
+static int rshim_dev_read(int chan, int addr, uint64_t *value)
+{
+	int rc;
+
+	addr = (addr & 0xFFFF) | (1 << 16);
+	rc = pread(rshim_fd, value, sizeof(*value), addr);
+
+#ifdef HAVE_SYS_IOCTL_H
+	if (rc < 0 && errno == ENOSYS) {
+		rshim_ioctl_msg msg;
+
+		msg.addr = addr;
+		msg.data = 0;
+		rc = ioctl(rshim_fd, RSH_IOC_READ, &msg);
+		if (!rc)
+			*value = msg.data;
+	}
+#endif
+
+	return rc;
+}
+
+static int rshim_dev_write(int chan, int addr, uint64_t value)
+{
+	int rc;
+
+	addr = (addr & 0xFFFF) | (1 << 16);
+	rc = pwrite(rshim_fd, &value, sizeof(value), addr);
+
+#ifdef HAVE_SYS_IOCTL_H
+	if (rc < 0 && errno == ENOSYS) {
+		rshim_ioctl_msg msg;
+
+		msg.addr = addr;
+		msg.data = value;
+		rc = ioctl(rshim_fd, RSH_IOC_WRITE, &msg);
+	}
+#endif
+
+	return rc;
+}
+
+/* Convert AP address to tile local address. */
+static void ap_addr_2_tile(int *tile, uint32_t *addr)
+{
+	*addr -= RSH_CS_ROM_BASE;
+
+	if (*addr < RSH_CS_TILE_BASE) {
+		*tile = 0;
+	} else {
+		*addr -= RSH_CS_TILE_BASE;
+		*tile = *addr / RSH_CS_TILE_SIZE + 1;
+		*addr = *addr % RSH_CS_TILE_SIZE;
+	}
+}
+
+/*
+ * Write 4 bytes on the APB bus.
+ * tile = 0: access the root CS_ROM table
+ *      > 0: access the ROM table of cluster (tile - 1)
+ */
+static int coresight_write(uint32_t tile, uint32_t addr, uint32_t wdata)
+{
+	uint64_t ctl = 0;
+	int rc;
+
+	if (!rshim_read || !rshim_write)
+		return ERROR_FAIL;
+
+	/*
+	 * ADDR[28]    - must be set to 1 due to coresight ip.
+	 * ADDR[27:24] - linear tile id
+	 */
+	addr = (addr >> 2) | (tile << 24);
+	if (tile)
+		addr |= (1 << 28);
+	RSH_CS_SET_FIELD(ctl, ADDR, addr);
+	RSH_CS_SET_FIELD(ctl, ACTION, 0);	/* write */
+	RSH_CS_SET_FIELD(ctl, DATA, wdata);
+	RSH_CS_SET_FIELD(ctl, GO, 1);		/* start */
+
+	rshim_write(RSH_MMIO_CHANNEL_RSHIM, RSH_CORESIGHT_CTL, ctl);
+
+	do {
+		rc = rshim_read(RSH_MMIO_CHANNEL_RSHIM,
+				RSH_CORESIGHT_CTL, &ctl);
+		if (rc < 0) {
+			LOG_ERROR("Failed to read rshim.\n");
+			return rc;
+		}
+	} while (RSH_CS_GET_FIELD(ctl, GO));
+
+	return ERROR_OK;
+}
+
+static int coresight_read(uint32_t tile, uint32_t addr, uint32_t *value)
+{
+	uint64_t ctl = 0;
+	int rc;
+
+	if (!rshim_read || !rshim_write)
+		return ERROR_FAIL;
+
+	/*
+	 * ADDR[28]    - must be set to 1 due to coresight ip.
+	 * ADDR[27:24] - linear tile id
+	 */
+	addr = (addr >> 2) | (tile << 24);
+	if (tile)
+		addr |= (1 << 28);
+	RSH_CS_SET_FIELD(ctl, ADDR, addr);
+	RSH_CS_SET_FIELD(ctl, ACTION, 1);	/* read */
+	RSH_CS_SET_FIELD(ctl, GO, 1);		/* start */
+
+	rshim_write(RSH_MMIO_CHANNEL_RSHIM, RSH_CORESIGHT_CTL, ctl);
+
+	do {
+		rc = rshim_read(RSH_MMIO_CHANNEL_RSHIM,
+				RSH_CORESIGHT_CTL, &ctl);
+		if (rc < 0) {
+			LOG_ERROR("Failed to write rshim.\n");
+			return rc;
+		}
+	} while (RSH_CS_GET_FIELD(ctl, GO));
+
+	*value = RSH_CS_GET_FIELD(ctl, DATA);
+	return ERROR_OK;
+}
+
+static int rshim_dp_q_read(struct adiv5_dap *dap, unsigned int reg,
+			   uint32_t *data)
+{
+	if (!data)
+		return ERROR_OK;
+
+	switch (reg) {
+	case DP_DPIDR:
+		*data = dp_id_code;
+		break;
+
+	case DP_CTRL_STAT:
+		*data = CDBGPWRUPACK | CSYSPWRUPACK;
+		break;
+
+	default:
+		break;
+	}
+
+	return ERROR_OK;
+}
+
+static int rshim_dp_q_write(struct adiv5_dap *dap, unsigned int reg,
+			    uint32_t data)
+{
+	switch (reg) {
+	case DP_CTRL_STAT:
+		dp_ctrl_stat = data;
+		break;
+	case DP_SELECT:
+		ap_sel = (data & DP_SELECT_APSEL) >> 24;
+		ap_bank = (data & DP_SELECT_APBANK) >> 4;
+		break;
+	default:
+		LOG_INFO("Unknown command");
+		break;
+	}
+
+	return ERROR_OK;
+}
+
+static int rshim_ap_q_read(struct adiv5_ap *ap, unsigned int reg,
+			   uint32_t *data)
+{
+	uint32_t addr;
+	int rc = ERROR_OK, tile;
+
+	switch (reg) {
+	case MEM_AP_REG_CSW:
+		*data = ap_csw;
+		break;
+
+	case MEM_AP_REG_CFG:
+		*data = 0;
+		break;
+
+	case MEM_AP_REG_BASE:
+		*data = RSH_CS_ROM_BASE;
+		break;
+
+	case AP_REG_IDR:
+		if (ap->ap_num == 0)
+			*data = APB_AP_IDR;
+		else
+			*data = 0;
+		break;
+
+	case MEM_AP_REG_BD0:
+	case MEM_AP_REG_BD1:
+	case MEM_AP_REG_BD2:
+	case MEM_AP_REG_BD3:
+		addr = (ap_tar & ~0xf) + (reg & 0x0C);
+		ap_addr_2_tile(&tile, &addr);
+		rc = coresight_read(tile, addr, data);
+		break;
+
+	case MEM_AP_REG_DRW:
+		addr = (ap_tar & ~0x3) + ap_tar_inc;
+		ap_addr_2_tile(&tile, &addr);
+		rc = coresight_read(tile, addr, data);
+		if (!rc && (ap_csw & CSW_ADDRINC_MASK))
+			ap_tar_inc += (ap_csw & 0x03) * 2;
+		break;
+
+	default:
+		LOG_INFO("Unknown command");
+		rc = ERROR_FAIL;
+		break;
+	}
+
+	/* Track the last error code. */
+	if (rc != ERROR_OK)
+		rshim_dap_retval = rc;
+
+	return rc;
+}
+
+static int rshim_ap_q_write(struct adiv5_ap *ap, unsigned int reg,
+			    uint32_t data)
+{
+	int rc = ERROR_OK, tile;
+	uint32_t addr;
+
+	if (ap_bank != 0) {
+		rshim_dap_retval = ERROR_FAIL;
+		return ERROR_FAIL;
+	}
+
+	switch (reg) {
+	case MEM_AP_REG_CSW:
+		ap_csw = data;
+		break;
+
+	case MEM_AP_REG_TAR:
+		ap_tar = data;
+		ap_tar_inc = 0;
+		break;
+
+	case MEM_AP_REG_BD0:
+	case MEM_AP_REG_BD1:
+	case MEM_AP_REG_BD2:
+	case MEM_AP_REG_BD3:
+		addr = (ap_tar & ~0xf) + (reg & 0x0C);
+		ap_addr_2_tile(&tile, &addr);
+		rc = coresight_write(tile, addr, data);
+		break;
+
+	case MEM_AP_REG_DRW:
+		ap_drw = data;
+		addr = (ap_tar & ~0x3) + ap_tar_inc;
+		ap_addr_2_tile(&tile, &addr);
+		rc = coresight_write(tile, addr, data);
+		if (!rc && (ap_csw & CSW_ADDRINC_MASK))
+			ap_tar_inc += (ap_csw & 0x03) * 2;
+		break;
+
+	default:
+		rc = EINVAL;
+		break;
+	}
+
+	/* Track the last error code. */
+	if (rc != ERROR_OK)
+		rshim_dap_retval = rc;
+
+	return rc;
+}
+
+static int rshim_ap_q_abort(struct adiv5_dap *dap, uint8_t *ack)
+{
+	return ERROR_OK;
+}
+
+static int rshim_dp_run(struct adiv5_dap *dap)
+{
+	int retval = rshim_dap_retval;
+
+	/* Clear the error code. */
+	rshim_dap_retval = ERROR_OK;
+
+	return retval;
+}
+
+static int rshim_connect(struct adiv5_dap *dap)
+{
+	char *path = rshim_dev_path ? rshim_dev_path : RSHIM_DEV_PATH_DEFAULT;
+
+	rshim_fd = open(path, O_RDWR | O_SYNC);
+	if (rshim_fd == -1) {
+		LOG_ERROR("Unable to open %s\n", path);
+		return ERROR_FAIL;
+	}
+
+	/*
+	 * Set read/write operation via the device file. Funtion pointers
+	 * are used here so more ways like remote accessing via socket could
+	 * be added later.
+	 */
+	rshim_read = rshim_dev_read;
+	rshim_write = rshim_dev_write;
+
+	return ERROR_OK;
+}
+
+static void rshim_disconnect(struct adiv5_dap *dap)
+{
+	if (rshim_fd != -1) {
+		close(rshim_fd);
+		rshim_fd = -1;
+	}
+}
+
+COMMAND_HANDLER(rshim_dap_device_command)
+{
+	if (CMD_ARGC != 1) {
+		command_print(CMD, "Too many arguments");
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+
+	free(rshim_dev_path);
+	rshim_dev_path = strdup(CMD_ARGV[0]);
+	return ERROR_OK;
+}
+
+static const struct command_registration rshim_dap_subcommand_handlers[] = {
+	{
+		.name = "device",
+		.handler = rshim_dap_device_command,
+		.mode = COMMAND_CONFIG,
+		.help = "set the rshim device",
+		.usage = "</dev/rshim<N>/rshim>",
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration rshim_dap_command_handlers[] = {
+	{
+		.name = "rshim",
+		.mode = COMMAND_ANY,
+		.help = "perform rshim management",
+		.chain = rshim_dap_subcommand_handlers,
+		.usage = "",
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
+static int rshim_dap_init(void)
+{
+	return ERROR_OK;
+}
+
+static int rshim_dap_quit(void)
+{
+	return ERROR_OK;
+}
+
+static int rshim_dap_reset(int req_trst, int req_srst)
+{
+	return ERROR_OK;
+}
+
+static int rshim_dap_speed(int speed)
+{
+	return ERROR_OK;
+}
+
+static int rshim_dap_khz(int khz, int *jtag_speed)
+{
+	*jtag_speed = khz;
+	return ERROR_OK;
+}
+
+static int rshim_dap_speed_div(int speed, int *khz)
+{
+	*khz = speed;
+	return ERROR_OK;
+}
+
+/* DAP operations. */
+static const struct dap_ops rshim_dap_ops = {
+	.connect = rshim_connect,
+	.queue_dp_read = rshim_dp_q_read,
+	.queue_dp_write = rshim_dp_q_write,
+	.queue_ap_read = rshim_ap_q_read,
+	.queue_ap_write = rshim_ap_q_write,
+	.queue_ap_abort = rshim_ap_q_abort,
+	.run = rshim_dp_run,
+	.quit = rshim_disconnect,
+};
+
+static const char *const rshim_dap_transport[] = { "dapdirect_swd", NULL };
+
+struct adapter_driver rshim_dap_adapter_driver = {
+	.name = "rshim",
+	.transports = rshim_dap_transport,
+	.commands = rshim_dap_command_handlers,
+
+	.init = rshim_dap_init,
+	.quit = rshim_dap_quit,
+	.reset = rshim_dap_reset,
+	.speed = rshim_dap_speed,
+	.khz = rshim_dap_khz,
+	.speed_div = rshim_dap_speed_div,
+
+	.dap_swd_ops = &rshim_dap_ops,
+};
diff --git a/src/jtag/interfaces.c b/src/jtag/interfaces.c
index 00b3bb502..25858ea73 100644
--- a/src/jtag/interfaces.c
+++ b/src/jtag/interfaces.c
@@ -141,6 +141,9 @@ extern struct adapter_driver xds110_adapter_driver;
 #if BUILD_HLADAPTER == 1
 extern struct adapter_driver stlink_dap_adapter_driver;
 #endif
+#if BUILD_RSHIM == 1
+extern struct adapter_driver rshim_dap_adapter_driver;
+#endif
 #endif /* standard drivers */
 
 /**
@@ -252,6 +255,9 @@ struct adapter_driver *adapter_drivers[] = {
 #if BUILD_HLADAPTER == 1
 		&stlink_dap_adapter_driver,
 #endif
+#if BUILD_RSHIM == 1
+		&rshim_dap_adapter_driver,
+#endif
 #endif /* standard drivers */
 		NULL,
 	};
diff --git a/tcl/board/bluefield.cfg b/tcl/board/bluefield.cfg
new file mode 100644
index 000000000..3058d48ca
--- /dev/null
+++ b/tcl/board/bluefield.cfg
@@ -0,0 +1,6 @@
+#
+# Board configuration for BlueField SoC.
+#
+
+source [find interface/rshim.cfg]
+source [find target/bluefield.cfg]
diff --git a/tcl/interface/rshim.cfg b/tcl/interface/rshim.cfg
new file mode 100644
index 000000000..accabf534
--- /dev/null
+++ b/tcl/interface/rshim.cfg
@@ -0,0 +1,6 @@
+#
+# BlueField SoC in-circuit debugger/programmer
+#
+
+adapter driver rshim
+transport select dapdirect_swd
diff --git a/tcl/target/bluefield.cfg b/tcl/target/bluefield.cfg
new file mode 100644
index 000000000..b31dfe8d6
--- /dev/null
+++ b/tcl/target/bluefield.cfg
@@ -0,0 +1,78 @@
+# BlueField SoC Target
+
+set _CHIPNAME bluefield
+
+# Specify the target device
+#rshim device /dev/rshim0/rshim
+
+# Main DAP
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x4ba00477
+}
+
+adapter speed 1500
+
+swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+# Initialize the target name and command variable.
+set _TARGETNAME $_CHIPNAME.cpu
+set _smp_command ""
+
+# CTI relative address
+set $_TARGETNAME.cti(0) 0xC4020000
+set $_TARGETNAME.cti(1) 0xC4120000
+set $_TARGETNAME.cti(2) 0xC8020000
+set $_TARGETNAME.cti(3) 0xC8120000
+set $_TARGETNAME.cti(4) 0xCC020000
+set $_TARGETNAME.cti(5) 0xCC120000
+set $_TARGETNAME.cti(6) 0xD0020000
+set $_TARGETNAME.cti(7) 0xD0120000
+set $_TARGETNAME.cti(8) 0xD4020000
+set $_TARGETNAME.cti(9) 0xD4120000
+set $_TARGETNAME.cti(10) 0xD8020000
+set $_TARGETNAME.cti(11) 0xD8120000
+set $_TARGETNAME.cti(12) 0xDC020000
+set $_TARGETNAME.cti(13) 0xDC120000
+set $_TARGETNAME.cti(14) 0xE0020000
+set $_TARGETNAME.cti(15) 0xE0120000
+
+# Create debug targets for a number of cores starting from core '_core_start'.
+# Adjust the numbers according to board configuration.
+set _core_start 0
+set _cores 16
+
+# Create each core
+for { set _core $_core_start } { $_core < $_core_start + $_cores } { incr _core 1 } {
+    cti create cti$_core -dap $_CHIPNAME.dap -ctibase [set $_TARGETNAME.cti($_core)] -ap-num 0
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core"
+
+    if { $_core != $_core_start } {
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+    } else {
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+# Configure SMP
+if { $_cores > 1 } {
+    eval $_smp_command
+}
+
+# Make sure the default target is the boot core
+targets ${_TARGETNAME}0
+
+proc core_up { args } {
+	global _TARGETNAME
+
+	# Examine remaining cores
+	foreach _core [set args] {
+		${_TARGETNAME}$_core arp_examine
+	}
+}

-----------------------------------------------------------------------

Summary of changes:
 configure.ac                 |  18 ++
 src/jtag/drivers/Makefile.am |   3 +
 src/jtag/drivers/rshim.c     | 523 +++++++++++++++++++++++++++++++++++++++++++
 src/jtag/interfaces.c        |   6 +
 tcl/board/bluefield.cfg      |   6 +
 tcl/interface/rshim.cfg      |   6 +
 tcl/target/bluefield.cfg     |  78 +++++++
 7 files changed, 640 insertions(+)
 create mode 100644 src/jtag/drivers/rshim.c
 create mode 100644 tcl/board/bluefield.cfg
 create mode 100644 tcl/interface/rshim.cfg
 create mode 100644 tcl/target/bluefield.cfg


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1191-g76a1524b5

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      from  278c7adcce51ca11c30b7dd5c178fa28d19dc4e6 (commit)

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- Log -----------------------------------------------------------------
commit 76a1524b5e4b89149d7126b681c935de4aaa441a
Author: Antonio Borneo <bor...@gm...>
Date:   Wed Apr 10 12:46:54 2019 +0200

    tools/checkpatch.sh: remove flag --no-tree
    
    Commit c5d89883165e02ea4f318e3cb0ba40d1fb6f04d1 ("checkpatch.pl:
    check for openocd tree, not for kernel tree") has already fixed
    the check for OpenOCD tree, thus we do not need to skip it in the
    shell wrapper.
    
    Remove flag --no-tree from the shell wrapper.
    
    Change-Id: I8be497258624d89bde7742fee141a8f56bf9188e
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5110
    Tested-by: jenkins

diff --git a/tools/checkpatch.sh b/tools/checkpatch.sh
index e1dd267f9..0a630a248 100755
--- a/tools/checkpatch.sh
+++ b/tools/checkpatch.sh
@@ -2,4 +2,4 @@
 #
 
 since=${1:-HEAD^}
-git format-patch -M --stdout $since | tools/scripts/checkpatch.pl - --no-tree
+git format-patch -M --stdout $since | tools/scripts/checkpatch.pl -

-----------------------------------------------------------------------

Summary of changes:
 tools/checkpatch.sh | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1190-g278c7adcc

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- Log -----------------------------------------------------------------
commit 278c7adcce51ca11c30b7dd5c178fa28d19dc4e6
Author: Marek Vasut <mar...@gm...>
Date:   Sat Apr 4 13:20:56 2020 +0200

    tcl/target: Drop reference to renesas_gen2_common.cfg
    
    Drop bogus reference to board/renesas_gen2_common.cfg , which is a
    non-existing file.
    
    Fixes: a01474bb4c4c ("tcl/target: Switch Renesas R-Car Gen2 boards to new config")
    Change-Id: Icb22d8456b7ac94d3a9a4ed354b246ee1332b122
    Signed-off-by: Marek Vasut <mar...@gm...>
    Reviewed-on: http://openocd.zylin.com/5564
    Tested-by: jenkins
    Reviewed-by: Oleksij Rempel <li...@re...>

diff --git a/tcl/board/renesas_porter.cfg b/tcl/board/renesas_porter.cfg
index b5622e683..7f23fb63c 100644
--- a/tcl/board/renesas_porter.cfg
+++ b/tcl/board/renesas_porter.cfg
@@ -2,4 +2,3 @@
 
 set SOC M2
 source [find target/renesas_rcar_gen2.cfg]
-source [find board/renesas_gen2_common.cfg]
diff --git a/tcl/board/renesas_silk.cfg b/tcl/board/renesas_silk.cfg
index 36af47ff4..08bcb666f 100644
--- a/tcl/board/renesas_silk.cfg
+++ b/tcl/board/renesas_silk.cfg
@@ -2,4 +2,3 @@
 
 set SOC E2
 source [find target/renesas_rcar_gen2.cfg]
-source [find board/renesas_gen2_common.cfg]
diff --git a/tcl/board/renesas_stout.cfg b/tcl/board/renesas_stout.cfg
index 7a8001796..51b53e154 100644
--- a/tcl/board/renesas_stout.cfg
+++ b/tcl/board/renesas_stout.cfg
@@ -2,4 +2,3 @@
 
 set SOC H2
 source [find target/renesas_rcar_gen2.cfg]
-source [find board/renesas_gen2_common.cfg]

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/renesas_porter.cfg | 1 -
 tcl/board/renesas_silk.cfg   | 1 -
 tcl/board/renesas_stout.cfg  | 1 -
 3 files changed, 3 deletions(-)


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- Log -----------------------------------------------------------------
commit 7a94d0a19fbe1762d1be26d35958ca3edb74b41e
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Feb 14 16:49:45 2020 +0100

    tcl: stm32mp15x: add target and board config files
    
    The stm32mp15x has one or two Cortex-A7 (depending on the P/N) and
    one Cortex-M4.
    The second core is automatically detected by the target script.
    In "engineering boot" all the cores are accessible.
    In "production boot" the Cortex-M4 is kept in reset state after
    power-on or NRST.
    
    The board DK2 includes a ST-Link/V2, but only SWD is connected.
    
    Change-Id: Ib6ebefcc696b1716e0f98694cadf0b04fd7d11d6
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5454
    Tested-by: jenkins
    Reviewed-by: Oleksij Rempel <li...@re...>

diff --git a/tcl/board/stm32mp15x_dk2.cfg b/tcl/board/stm32mp15x_dk2.cfg
new file mode 100644
index 000000000..0233c6d75
--- /dev/null
+++ b/tcl/board/stm32mp15x_dk2.cfg
@@ -0,0 +1,11 @@
+# board MB1272B
+# http://www.st.com/en/evaluation-tools/stm32mp157a-dk1.html
+# http://www.st.com/en/evaluation-tools/stm32mp157c-dk2.html
+
+source [find interface/stlink-dap.cfg]
+
+transport select dapdirect_swd
+
+source [find target/stm32mp15x.cfg]
+
+reset_config srst_only
diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/stm32mp15x.cfg
new file mode 100644
index 000000000..a11f6665e
--- /dev/null
+++ b/tcl/target/stm32mp15x.cfg
@@ -0,0 +1,121 @@
+# STMicroelectronics STM32MP15x (Single/Dual Cortex-A7 plus Cortex-M4)
+# http://www.st.com/stm32mp1
+
+# HLA does not support multi-cores nor custom CSW nor AP other than 0
+if { [using_hla] } {
+	echo "ERROR: HLA transport cannot work with this target."
+	echo "ERROR: To use STLink switch to DAP mode, as in \"board/stm32mp15x_dk2.cfg\"."
+	shutdown
+}
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32mp15x
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} else {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Chip Level TAP Controller, only in jtag mode
+if { [info exists CLCTAPID] } {
+	set _CLCTAPID $CLCTAPID
+} else {
+	set _CLCTAPID 0x06500041
+}
+
+swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4
+if { [using_jtag] } {
+	jtag newtap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
+
+# FIXME: Cortex-M code requires target accessible during reset, but this is not possible in STM32MP1
+# so defer-examine it until the reset framework get merged
+# NOTE: keep ap-num and dbgbase to speed-up examine after reset
+# NOTE: do not change the order of target create
+target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
+target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
+target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000
+target create $_CHIPNAME.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
+
+targets $_CHIPNAME.cpu0
+
+target smp $_CHIPNAME.cpu0 $_CHIPNAME.cpu1
+$_CHIPNAME.cpu0 cortex_a maskisr on
+$_CHIPNAME.cpu1 cortex_a maskisr on
+$_CHIPNAME.cpu0 cortex_a dacrfixup on
+$_CHIPNAME.cpu1 cortex_a dacrfixup on
+
+cti create $_CHIPNAME.cti.sys  -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE0094000
+cti create $_CHIPNAME.cti.cpu0 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE00D8000
+cti create $_CHIPNAME.cti.cpu1 -dap $_CHIPNAME.dap -ap-num 1 -ctibase 0xE00D9000
+cti create $_CHIPNAME.cti.cm4  -dap $_CHIPNAME.dap -ap-num 2 -ctibase 0xE0043000
+
+# interface does not work while srst is asserted
+# this is target specific, valid for every board
+# Errata "2.3.5 Incorrect reset of glitch-free kernel clock switch" requires
+# srst to force VDDCORE power cycle or pull srst_core. Both cases reset the
+# debug unit, behavior equivalent to "srst_pulls_trst"
+reset_config srst_gates_jtag srst_pulls_trst
+
+adapter speed 5000
+adapter srst pulse_width 200
+# bootrom has an internal timeout of 1 second for detecting the boot flash.
+# wait at least 1 second to guarantee we are out of bootrom
+adapter srst delay 1100
+
+add_help_text axi_secure "Set secure mode for following AXI accesses"
+proc axi_secure {} {
+	$::_CHIPNAME.dap apsel 0
+	$::_CHIPNAME.dap apcsw 0x10006000
+}
+
+add_help_text axi_nsecure "Set non-secure mode for following AXI accesses"
+proc axi_nsecure {} {
+	$::_CHIPNAME.dap apsel 0
+	$::_CHIPNAME.dap apcsw 0x30006000
+}
+
+axi_secure
+
+proc dbgmcu_enable_debug {} {
+	# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
+	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
+}
+
+proc toggle_cpu0_dbg_claim0 {} {
+	# toggle CPU0 DBG_CLAIM[0]
+	$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
+	$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
+}
+
+proc detect_cpu1 {} {
+	$::_CHIPNAME.ap1 mem2array cpu1_prsr 32 0xE00D2314 1
+	set dual_core [expr $cpu1_prsr(0) & 1]
+	if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
+}
+
+# FIXME: most of handler below will be removed once reset framework get merged
+$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;dap init;catch {$::_CHIPNAME.dap apid 1}}
+$_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug}
+$_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
+$_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}
+$_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
+$_CHIPNAME.cm4  configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
+$_CHIPNAME.ap1  configure -event examine-start       {dap init}
+$_CHIPNAME.ap2  configure -event examine-start       {dbgmcu_enable_debug}
+$_CHIPNAME.cpu0 configure -event examine-end         {detect_cpu1}
+$_CHIPNAME.ap2  configure -event examine-end         {$::_CHIPNAME.cm4 arp_examine}

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/stm32mp15x_dk2.cfg |  11 ++++
 tcl/target/stm32mp15x.cfg    | 121 +++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 132 insertions(+)
 create mode 100644 tcl/board/stm32mp15x_dk2.cfg
 create mode 100644 tcl/target/stm32mp15x.cfg


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commit 3c296bd19480033037f4e3f2db4a876a34a41f58
Author: Tomas Vanek <va...@fb...>
Date:   Fri Mar 13 15:34:47 2020 +0100

    jtag/drivers/ulink: fix clang static analyzer warnings
    
    scan-build-9:
    Description: Potential leak of memory pointed to by 'cmd'
    File: /home/vanekt/openocd/scanbuild9/../src/jtag/drivers/ulink.c
    Line: 1075
    
    Description: Potential leak of memory pointed to by 'cmd'
    File: /home/vanekt/openocd/scanbuild9/../src/jtag/drivers/ulink.c
    Line: 1275
    
    ulink_append_xxx_cmd() functions allocate memory for cmd
    and then call ulink_allocate_payload(), which allocates cmd->payload_out
    or cmd->payload_in.
    
    ulink_append_queue() checks the size of queue and if the new payload
    does not fit, calls ulink_execute_queued_commands() and then
    ulink_post_process_queue(). If any of these two fails, an error is
    returned, allocated cmd struct leaks and the queue is left in an undefined
    state.
    
    Change ulink_append_queue() flow to proceed to appending cmd to the queue
    even in the case of fail in previous ulink_execute_queued_commands()
    or ulink_post_process_queue(). In case of fail then clear the queue
    including the last appended cmd.
    
    Change-Id: I967c07af19e9020c93bcb4ef403cf1f557dd1db1
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: http://openocd.zylin.com/5370
    Tested-by: jenkins
    Reviewed-by: Oleksij Rempel <li...@re...>

diff --git a/src/jtag/drivers/ulink.c b/src/jtag/drivers/ulink.c
index 4066d6109..c6683abda 100644
--- a/src/jtag/drivers/ulink.c
+++ b/src/jtag/drivers/ulink.c
@@ -650,7 +650,7 @@ void ulink_clear_queue(struct ulink *device)
 int ulink_append_queue(struct ulink *device, struct ulink_cmd *ulink_cmd)
 {
 	int newsize_out, newsize_in;
-	int ret;
+	int ret = ERROR_OK;
 
 	newsize_out = ulink_get_queue_size(device, PAYLOAD_DIRECTION_OUT) + 1
 		+ ulink_cmd->payload_out_size;
@@ -663,14 +663,12 @@ int ulink_append_queue(struct ulink *device, struct ulink_cmd *ulink_cmd)
 		/* New command does not fit. Execute all commands in queue before starting
 		 * new queue with the current command as first entry. */
 		ret = ulink_execute_queued_commands(device, USB_TIMEOUT);
-		if (ret != ERROR_OK)
-			return ret;
 
-		ret = ulink_post_process_queue(device);
-		if (ret != ERROR_OK)
-			return ret;
+		if (ret == ERROR_OK)
+			ret = ulink_post_process_queue(device);
 
-		ulink_clear_queue(device);
+		if (ret == ERROR_OK)
+			ulink_clear_queue(device);
 	}
 
 	if (device->queue_start == NULL) {
@@ -687,7 +685,10 @@ int ulink_append_queue(struct ulink *device, struct ulink_cmd *ulink_cmd)
 		device->queue_end = ulink_cmd;
 	}
 
-	return ERROR_OK;
+	if (ret != ERROR_OK)
+		ulink_clear_queue(device);
+
+	return ret;
 }
 
 /**

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/ulink.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)


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- Log -----------------------------------------------------------------
commit 6dcd255b7bde5d7d3a8805c3a0e81f5edf42ccf4
Author: Tomas Vanek <va...@fb...>
Date:   Fri Mar 13 15:13:21 2020 +0100

    jtag/drivers/ulink: fix clang static analyzer warning
    
    scan-build-9:
    Description: Access to field 'payload_in' results in a dereference
     of a null pointer (loaded from field 'queue_start')
    File: src/jtag/drivers/ulink.c
    Line: 2216
    
    Set input/output_signals conditionally if ulink_append_get_signals_cmd()
    and ulink_execute_queued_commands() returns no error.
    Do not fail driver initialisation as the signals are only printed.
    
    Change-Id: I6c842f0e9a604712abf7444a2fa95ba5810de1ff
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: http://openocd.zylin.com/5520
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Oleksij Rempel <li...@re...>

diff --git a/src/jtag/drivers/ulink.c b/src/jtag/drivers/ulink.c
index 9235eb893..4066d6109 100644
--- a/src/jtag/drivers/ulink.c
+++ b/src/jtag/drivers/ulink.c
@@ -2210,14 +2210,17 @@ static int ulink_init(void)
 	}
 	ulink_clear_queue(ulink_handle);
 
-	ulink_append_get_signals_cmd(ulink_handle);
-	ulink_execute_queued_commands(ulink_handle, 200);
+	ret = ulink_append_get_signals_cmd(ulink_handle);
+	if (ret == ERROR_OK)
+		ret = ulink_execute_queued_commands(ulink_handle, 200);
 
-	/* Post-process the single CMD_GET_SIGNALS command */
-	input_signals = ulink_handle->queue_start->payload_in[0];
-	output_signals = ulink_handle->queue_start->payload_in[1];
+	if (ret == ERROR_OK) {
+		/* Post-process the single CMD_GET_SIGNALS command */
+		input_signals = ulink_handle->queue_start->payload_in[0];
+		output_signals = ulink_handle->queue_start->payload_in[1];
 
-	ulink_print_signal_states(input_signals, output_signals);
+		ulink_print_signal_states(input_signals, output_signals);
+	}
 
 	ulink_clear_queue(ulink_handle);
 

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/ulink.c | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)


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- Log -----------------------------------------------------------------
commit c0644401622d1d5bf42e522452c7c9f83293cfd8
Author: Tomas Vanek <va...@fb...>
Date:   Fri Dec 20 23:34:19 2019 +0100

    jtag/drivers/ulink: fix clang static analyzer warning
    
    scan-build-9:
    Description: Potential leak of memory pointed to by 'tdo_buffer'
    File: src/jtag/drivers/ulink.c
    Line: 1629
    
    Free the buffer before error return.
    
    Change-Id: Ic47651a5ae78c7a47ae4fcbad225f329b14c45cb
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: http://openocd.zylin.com/5519
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Oleksij Rempel <li...@re...>

diff --git a/src/jtag/drivers/ulink.c b/src/jtag/drivers/ulink.c
index 77fbe6193..9235eb893 100644
--- a/src/jtag/drivers/ulink.c
+++ b/src/jtag/drivers/ulink.c
@@ -1627,6 +1627,7 @@ int ulink_queue_scan(struct ulink *device, struct jtag_command *cmd)
 
 		if (ret != ERROR_OK) {
 			free(tdi_buffer_start);
+			free(tdo_buffer_start);
 			return ret;
 		}
 	}

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/ulink.c | 1 +
 1 file changed, 1 insertion(+)


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- Log -----------------------------------------------------------------
commit 46f077aa003449f95781170fc2d0cf674272ad3e
Author: Tomas Vanek <va...@fb...>
Date:   Fri Mar 13 12:10:50 2020 +0100

    flash/nand/core: fix clang static analyzer warning
    
    core.c:446:
    The left operand of '>>' is a garbage value
    
    There are many places where an error code returned from nand->controller
    operations are ignored. To keep the change minimal, the error checks are
    added only to reading of extended nand info as it was suspected
    to be the cause of the warning.
    
    Addition of the error checks did not fix the warning.
    scan-build-9 report was inspected and IMHO the warning is bogus:
    the term (nand->device->erase_size == 0) cannot give false at line 395
    and then evaluate true at line 462. Fixed by zeroing id_buff.
    
    Change-Id: I97ed7ce0fdf1aa23d746d5fb898bacd050e20ae8
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: http://openocd.zylin.com/5518
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Oleksij Rempel <li...@re...>

diff --git a/src/flash/nand/core.c b/src/flash/nand/core.c
index b9ac793f2..baef5d59c 100644
--- a/src/flash/nand/core.c
+++ b/src/flash/nand/core.c
@@ -263,6 +263,7 @@ int nand_read_status(struct nand_device *nand, uint8_t *status)
 		return ERROR_NAND_DEVICE_NOT_PROBED;
 
 	/* Send read status command */
+	/* FIXME: errors returned from nand->controller are mostly ignored! */
 	nand->controller->command(nand, NAND_CMD_STATUS);
 
 	alive_sleep(1);
@@ -301,7 +302,8 @@ static int nand_poll_ready(struct nand_device *nand, int timeout)
 int nand_probe(struct nand_device *nand)
 {
 	uint8_t manufacturer_id, device_id;
-	uint8_t id_buff[6];
+	uint8_t id_buff[6] = { 0 };	/* zero buff to silence false warning
+					 * from clang static analyzer */
 	int retval;
 	int i;
 
@@ -392,19 +394,34 @@ int nand_probe(struct nand_device *nand)
 	if (nand->device->page_size == 0 ||
 			nand->device->erase_size == 0) {
 		if (nand->bus_width == 8) {
-			nand->controller->read_data(nand, id_buff + 3);
-			nand->controller->read_data(nand, id_buff + 4);
-			nand->controller->read_data(nand, id_buff + 5);
+			retval = nand->controller->read_data(nand, id_buff + 3);
+			if (retval != ERROR_OK)
+				return retval;
+
+			retval = nand->controller->read_data(nand, id_buff + 4);
+			if (retval != ERROR_OK)
+				return retval;
+
+			retval = nand->controller->read_data(nand, id_buff + 5);
+			if (retval != ERROR_OK)
+				return retval;
+
 		} else {
 			uint16_t data_buf;
 
-			nand->controller->read_data(nand, &data_buf);
+			retval = nand->controller->read_data(nand, &data_buf);
+			if (retval != ERROR_OK)
+				return retval;
 			id_buff[3] = data_buf;
 
-			nand->controller->read_data(nand, &data_buf);
+			retval = nand->controller->read_data(nand, &data_buf);
+			if (retval != ERROR_OK)
+				return retval;
 			id_buff[4] = data_buf;
 
-			nand->controller->read_data(nand, &data_buf);
+			retval = nand->controller->read_data(nand, &data_buf);
+			if (retval != ERROR_OK)
+				return retval;
 			id_buff[5] = data_buf >> 8;
 		}
 	}

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nand/core.c | 31 ++++++++++++++++++++++++-------
 1 file changed, 24 insertions(+), 7 deletions(-)


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- Log -----------------------------------------------------------------
commit ea4f98046fe2f9d8362feadb50f058a9fff7ad4f
Author: Evgeniy Didin <di...@sy...>
Date:   Tue Mar 17 14:06:24 2020 +0300

    target/arc: remove saving context during reset
    
    In arc_poll() function we handle the cases, when jtag indicates, that
    processor is halted, but target->state is not TARGET_HALTED.
    In case, when processor was halted and target->state was TARGET_RUNNING,
    we should save context. At the same time if target->state was TARGET_RESET
    we do not need to save context.
    
    Changes: 16.04:
    Fix - Move setting target->state = TARGET_HALT after
    "target->state == TARGET_RUNNIG" check, otherwise
    this check makes no sense
    
    Change-Id: I92ab6ec71cf58273bb8401d14a562035de3deab4
    Signed-off-by: Evgeniy Didin <di...@sy...>
    Reviewed-on: http://openocd.zylin.com/5524
    Tested-by: jenkins
    Reviewed-by: Oleksij Rempel <li...@re...>

diff --git a/src/target/arc.c b/src/target/arc.c
index 244dd5247..823b9ed70 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -928,8 +928,10 @@ static int arc_poll(struct target *target)
 		CHECK_RETVAL(arc_get_register_value(target, "status32", &value));
 		if (value & AUX_STATUS32_REG_HALT_BIT) {
 			LOG_DEBUG("ARC core in halt or reset state.");
+			/* Save context if target was not in reset state */
+			if (target->state == TARGET_RUNNING)
+				CHECK_RETVAL(arc_debug_entry(target));
 			target->state = TARGET_HALTED;
-			CHECK_RETVAL(arc_debug_entry(target));
 			CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
 		} else {
 		LOG_DEBUG("Discrepancy of STATUS32[0] HALT bit and ARC_JTAG_STAT_RU, "

-----------------------------------------------------------------------

Summary of changes:
 src/target/arc.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)


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- Log -----------------------------------------------------------------
commit a7d98680e20bf8eccb9a7ccc67fef390ddb90f03
Author: Evgeniy Didin <di...@sy...>
Date:   Thu Nov 28 08:34:46 2019 +0300

    Add documentation section for ARCv2
    
    Changes since v1:
    -Moved from http://openocd.zylin.com/#/c/5332/4
     into separate commit.
    
    28.02.2020:
    -Removed multiple cpu configuration section, currently
     only ARC EM is supported.
    
    17.03.2020:
    -Some cleanup
    -For "arc set-reg-exists" command limitize the number of
     arguments (50 maximum).
    
    17.03.2020(v2):
    -Revert limitation for "arc set-reg-exist" command
    
    Change-Id: I4b06f89df95f2773bfde6e1bd2ae2b6b880bfaa8
    Signed-off-by: Evgeniy Didin <di...@sy...>
    Cc: Alexey Brodkin <abr...@sy...>
    Reviewed-on: http://openocd.zylin.com/5351
    Tested-by: jenkins
    Reviewed-by: Oleksij Rempel <li...@re...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 0c58a682c..35a41d4de 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -9685,6 +9685,135 @@ Perform a 32-bit DMI read at address, returning the value.
 Perform a 32-bit DMI write of value at address.
 @end deffn
 
+@section ARC Architecture
+@cindex ARC
+
+Synopsys DesignWare ARC Processors are a family of 32-bit CPUs that SoC
+designers can optimize for a wide range of uses, from deeply embedded to
+high-performance host applications in a variety of market segments. See more
+at: http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx.
+OpenOCD currently supports ARC EM processors.
+There is a set ARC-specific OpenOCD commands that allow low-level
+access to the core and provide necessary support for ARC extensibility and
+configurability capabilities. ARC processors has much more configuration
+capabilities than most of the other processors and in addition there is an
+extension interface that allows SoC designers to add custom registers and
+instructions. For the OpenOCD that mostly means that set of core and AUX
+registers in target will vary and is not fixed for a particular processor
+model. To enable extensibility several TCL commands are provided that allow to
+describe those optional registers in OpenOCD configuration files. Moreover
+those commands allow for a dynamic target features discovery.
+
+
+@subsection General ARC commands
+
+@deffn {Config Command} {arc add-reg} configparams
+
+Add a new register to processor target. By default newly created register is
+marked as not existing. @var{configparams} must have following required
+arguments:
+
+@itemize @bullet
+
+@item @code{-name} name
+@*Name of a register.
+
+@item @code{-num} number
+@*Architectural register number: core register number or AUX register number.
+
+@item @code{-feature} XML_feature
+@*Name of GDB XML target description feature.
+
+@end itemize
+
+@var{configparams} may have following optional arguments:
+
+@itemize @bullet
+
+@item @code{-gdbnum} number
+@*GDB register number. It is recommended to not assign GDB register number
+manually, because there would be a risk that two register will have same
+number. When register GDB number is not set with this option, then register
+will get a previous register number + 1. This option is required only for those
+registers that must be at particular address expected by GDB.
+
+@item @code{-core}
+@*This option specifies that register is a core registers. If not - this is an
+AUX register. AUX registers and core registers reside in different address
+spaces.
+
+@item @code{-bcr}
+@*This options specifies that register is a BCR register. BCR means Build
+Configuration Registers - this is a special type of AUX registers that are read
+only and non-volatile, that is - they never change their value. Therefore OpenOCD
+never invalidates values of those registers in internal caches. Because BCR is a
+type of AUX registers, this option cannot be used with @code{-core}.
+
+@item @code{-type} type_name
+@*Name of type of this register. This can be either one of the basic GDB types,
+or a custom types described with @command{arc add-reg-type-[flags|struct]}.
+
+@item @code{-g}
+@* If specified then this is a "general" register. General registers are always
+read by OpenOCD on context save (when core has just been halted) and is always
+transfered to GDB client in a response to g-packet. Contrary to this,
+non-general registers are read and sent to GDB client on-demand. In general it
+is not recommended to apply this option to custom registers.
+
+@end itemize
+
+@end deffn
+
+@deffn {Config Command} {arc add-reg-type-flags} -name name flags...
+Adds new register type of ``flags'' class. ``Flags'' types can contain only
+one-bit fields. Each flag definition looks like @code{-flag name bit-position}.
+@end deffn
+
+@anchor{add-reg-type-struct}
+@deffn {Config Command} {arc add-reg-type-struct} -name name structs...
+Adds new register type of ``struct'' class. ``Struct'' types can contain either
+bit-fields or fields of other types, however at the moment only bit fields are
+supported. Structure bit field definition looks like @code{-bitfield name
+startbit endbit}.
+@end deffn
+
+@deffn {Command} {arc get-reg-field} reg-name field-name
+Returns value of bit-field in a register. Register must be ``struct'' register
+type, @xref{add-reg-type-struct} command definition.
+@end deffn
+
+@deffn {Command} {arc set-reg-exists} reg-names...
+Specify that some register exists. Any amount of names can be passed
+as an argument for a single command invocation.
+@end deffn
+
+@subsection ARC JTAG commands
+
+@deffn {Command} {arc jtag set-aux-reg} regnum value
+This command writes value to AUX register via its number. This command access
+register in target directly via JTAG, bypassing any OpenOCD internal caches,
+therefore it is unsafe to use if that register can be operated by other means.
+
+@end deffn
+
+@deffn {Command} {arc jtag set-core-reg} regnum value
+This command is similiar to @command{arc jtag set-aux-reg} but is for core
+registers.
+@end deffn
+
+@deffn {Command} {arc jtag get-aux-reg} regnum
+This command returns the value storded in AUX register via its number. This commands access
+register in target directly via JTAG, bypassing any OpenOCD internal caches,
+therefore it is unsafe to use if that register can be operated by other means.
+
+@end deffn
+
+@deffn {Command} {arc jtag get-core-reg} regnum
+This command is similiar to @command{arc jtag get-aux-reg} but is for core
+registers.
+@end deffn
+
+
 @anchor{softwaredebugmessagesandtracing}
 @section Software Debug Messages and Tracing
 @cindex Linux-ARM DCC support

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi | 129 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 129 insertions(+)


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commit 435e6101c68616f0555193d1113a27b926f2c50d
Author: Evgeniy Didin <di...@sy...>
Date:   Thu Nov 28 08:34:01 2019 +0300

    Introduce ARCv2 tcl config files
    
    With this commit we add tcl files which describes
    ARCv2 architecture features and configure files
    for ARCv2 EMSK board.
    
    Changes since v1:
    -Moved from http://openocd.zylin.com/#/c/5332/4
     into separate commit.
    
    Changes:
    22.01.2020:
    -Removed "actionpoints" handling code in
     tcl/cpu/arc/v2.tcl because this capability
     is not supported yet.
    
    Changes:
    17.03.2020:
    -Update Licence headers
    -Cleanup indents
    -Removed "reset halt" in boards .tcl
    -Updated adapter frequency commands
    
    Changes:
    15.03.2020:
    -Removed "init" in the of boards .tcl
    
    Change-Id: I51bf620abe7b8e046e1dccc861a7d963965d3a42
    Signed-off-by: Evgeniy Didin <di...@sy...>
    Cc: Alexey Brodkin <abr...@sy...>
    Reviewed-on: http://openocd.zylin.com/5350
    Tested-by: jenkins
    Reviewed-by: Oleksij Rempel <li...@re...>

diff --git a/tcl/board/snps_em_sk.cfg b/tcl/board/snps_em_sk.cfg
new file mode 100644
index 000000000..63c39a4d4
--- /dev/null
+++ b/tcl/board/snps_em_sk.cfg
@@ -0,0 +1,22 @@
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov <ant...@sy...>
+#  Didin Evgeniy <di...@sy...>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.x
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# 5MHz seems to work good with all cores that might happen in 2.x
+adapter speed 5000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/tcl/board/snps_em_sk_v1.cfg b/tcl/board/snps_em_sk_v1.cfg
new file mode 100644
index 000000000..2e9d6025e
--- /dev/null
+++ b/tcl/board/snps_em_sk_v1.cfg
@@ -0,0 +1,20 @@
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov <ant...@sy...>
+#  Didin Evgeniy <di...@sy...>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v1.0 and v1.1
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+adapter speed 10000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/tcl/board/snps_em_sk_v2.1.cfg b/tcl/board/snps_em_sk_v2.1.cfg
new file mode 100644
index 000000000..5df8de571
--- /dev/null
+++ b/tcl/board/snps_em_sk_v2.1.cfg
@@ -0,0 +1,23 @@
+#  Copyright (C) 2014-2016,2020 Synopsys, Inc.
+#  Anton Kolesov <ant...@sy...>
+#  Didin Evgeniy <di...@sy...>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.1
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# JTAG 10MHz is too fast for EM7D FPU in EM SK 2.1 which has core frequency
+# 20MHz. 7.5 MHz seems to work fine.
+adapter speed 7500
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/tcl/board/snps_em_sk_v2.2.cfg b/tcl/board/snps_em_sk_v2.2.cfg
new file mode 100644
index 000000000..7f3708e5c
--- /dev/null
+++ b/tcl/board/snps_em_sk_v2.2.cfg
@@ -0,0 +1,22 @@
+#  Copyright (C) 2016,2020 Synopsys, Inc.
+#  Anton Kolesov <ant...@sy...>
+#  Didin Evgeniy <di...@sy...>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC EM Starter Kit v2.2
+#
+
+# Configure JTAG cable
+# EM Starter Kit has built-in FT2232 chip, which is similiar to Digilent HS-1.
+source [find interface/ftdi/digilent-hs1.cfg]
+
+# EM11D reportedly requires 5 MHz. Other cores and board can work faster.
+adapter speed 5000
+
+# ARCs support only JTAG.
+transport select jtag
+
+# Configure FPGA. This script supports both LX45 and LX150.
+source [find target/snps_em_sk_fpga.cfg]
diff --git a/tcl/cpu/arc/common.tcl b/tcl/cpu/arc/common.tcl
new file mode 100644
index 000000000..e9a915717
--- /dev/null
+++ b/tcl/cpu/arc/common.tcl
@@ -0,0 +1,40 @@
+#  Copyright (C) 2015, 2020 Synopsys, Inc.
+#  Anton Kolesov <ant...@sy...>
+#  Didin Evgeniy <di...@sy...>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Things common to all ARCs
+
+# It is assumed that target is already halted.
+proc arc_common_reset { {target ""} } {
+        if { $target != "" } {
+                targets $target
+        }
+
+        halt
+
+        # 1. Interrupts are disabled (STATUS32.IE)
+        # 2. The status register flags are cleared.
+        # All fields, except the H bit, are set to 0 when the processor is Reset.
+
+        arc jtag set-aux-reg 0xA 0x1
+
+        # 3. The loop count, loop start, and loop end registers are cleared.
+        arc jtag set-core-reg 60 0
+        arc jtag set-aux-reg 0x2 0
+        arc jtag set-aux-reg 0x3 0
+
+        # Program execution begins at the address referenced by the four byte reset
+        # vector located at the interrupt vector base address, which is the first
+        # entry (offset 0x00) in the vector table.
+        set int_vector_base [arc jtag get-aux-reg 0x25]
+        set start_pc ""
+        mem2array start_pc 32 $int_vector_base 1
+        arc jtag set-aux-reg 0x6 $start_pc(0)
+
+        # It is OK to do uncached writes - register cache will be invalidated by
+        # the reset_assert() function.
+}
+
+# vim:expandtab:
diff --git a/tcl/cpu/arc/em.tcl b/tcl/cpu/arc/em.tcl
new file mode 100644
index 000000000..f0455bb74
--- /dev/null
+++ b/tcl/cpu/arc/em.tcl
@@ -0,0 +1,32 @@
+#  Copyright (C) 2015, 2020 Synopsys, Inc.
+#  Anton Kolesov <ant...@sy...>
+#  Didin Evgeniy <di...@sy...>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find cpu/arc/v2.tcl]
+
+proc arc_em_examine_target { {target ""} } {
+	# Will set current target
+	arc_v2_examine_target $target
+}
+
+proc arc_em_init_regs { } {
+	arc_v2_init_regs
+
+	[target current] configure \
+		-event examine-end "arc_em_examine_target [target current]"
+}
+
+# Scripts in "target" folder should call this function instead of direct
+# invocation of arc_common_reset.
+proc arc_em_reset { {target ""} } {
+	arc_v2_reset $target
+
+	# Set DEBUG.ED bit to enable clock in actionpoint module.
+	# This is specific to ARC EM.
+	set debug [arc jtag get-aux-reg 5]
+	if { !($debug & (1 << 20)) } {
+		arc jtag set-aux-reg 5 [expr $debug | (1 << 20)]
+	}
+}
diff --git a/tcl/cpu/arc/v2.tcl b/tcl/cpu/arc/v2.tcl
new file mode 100644
index 000000000..ad55361a5
--- /dev/null
+++ b/tcl/cpu/arc/v2.tcl
@@ -0,0 +1,288 @@
+#  Copyright (C) 2015, 2020 Synopsys, Inc.
+#  Anton Kolesov <ant...@sy...>
+#  Didin Evgeniy <di...@sy...>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find cpu/arc/common.tcl]
+
+# Currently 'examine_target' can only read JTAG registers and set properties -
+# but it shouldn't write any of registers - writes will be cached, but cache
+# will be invalidated before flushing after examine_target, and changes will be
+# lost.  Perhaps that would be fixed later - perhaps writes shouldn't be cached
+# after all.  But if write to register is really needed from TCL - then it
+# should be done via "arc jtag" for now.
+proc arc_v2_examine_target { {target ""} } {
+	# Set current target, because OpenOCD event handlers don't do this for us.
+	if { $target != "" } {
+		targets $target
+	}
+
+	# Those registers always exist. DEBUG and DEBUGI are formally optional,
+	# however they come with JTAG interface, and so far there is no way
+	# OpenOCD can communicate with target without JTAG interface.
+	arc set-reg-exists identity pc status32 bta debug lp_start lp_end \
+		eret erbta erstatus ecr efa
+
+	# 32 core registers
+	arc set-reg-exists \
+		r0  r1  r2  r3  r4  r5  r6  r7  r8  r9  r10 r11 r12 \
+		r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 \
+		gp fp sp ilink r30 blink lp_count pcl
+
+	# DCCM
+	set dccm_version [arc get-reg-field dccm_build version]
+	if { $dccm_version == 3 || $dccm_version == 4 } {
+		arc set-reg-exists aux_dccm
+	}
+
+	# ICCM
+	if { [arc get-reg-field iccm_build version] == 4 } {
+		arc set-reg-exists aux_iccm
+	}
+
+	# MPU
+	if { [arc get-reg-field mpu_build version] >= 2 &&
+		 [arc get-reg-field mpu_build version] <= 4 } {
+		arc set-reg-exists mpu_en mpu_ecr
+		set mpu_regions [arc get-reg-field mpu_build regions]
+		for {set i 0} {$i < $mpu_regions} {incr i} {
+			arc set-reg-exists mpu_rdp$i mpu_rdb$i
+		}
+
+		# Secure MPU
+		if { [arc get-reg-field mpu_build version] == 4 } {
+			arc set-reg-exists mpu_index mpu_rstart mpu_rend mpu_rper
+		}
+	}
+}
+
+proc arc_v2_init_regs { } {
+	# XML features
+	set core_feature "org.gnu.gdb.arc.core.v2"
+	set aux_min_feature "org.gnu.gdb.arc.aux-minimal"
+	set aux_other_feature "org.gnu.gdb.arc.aux-other"
+
+	# Describe types
+	# Types are sorted alphabetically according to their name.
+	arc add-reg-type-struct -name ap_build_t -bitfield version 0 7 \
+		-bitfield type 8 11
+	arc add-reg-type-struct -name ap_control_t -bitfield at 0 3 -bitfield tt 4 5 \
+		-bitfield m 6 6 -bitfield p 7 7 -bitfield aa 8 8 -bitfield q 9 9
+	# Cycles field added in version 4.
+	arc add-reg-type-struct -name dccm_build_t -bitfield version 0 7 \
+		-bitfield size0 8 11 -bitfield size1 12 15 -bitfield cycles 17 19
+
+	arc add-reg-type-struct -name debug_t \
+		-bitfield fh 1 1   -bitfield ah 2 2   -bitfield asr 3 10 \
+		-bitfield is 11 11 -bitfield ep 19 19 -bitfield ed 20 20 \
+		-bitfield eh 21 21 -bitfield ra 22 22 -bitfield zz 23 23 \
+		-bitfield sm 24 26 -bitfield ub 28 28 -bitfield bh 29 29 \
+		-bitfield sh 30 30 -bitfield ld 31 31
+
+	arc add-reg-type-struct -name ecr_t \
+		-bitfield parameter 0 7 \
+		-bitfield cause 8 15 \
+		-bitfield vector 16 23 \
+		-bitfield U 30 30 \
+		-bitfield P 31 31
+	arc add-reg-type-struct -name iccm_build_t -bitfield version 0 7 \
+		-bitfield iccm0_size0  8 11 -bitfield iccm1_size0 12 15 \
+		-bitfield iccm0_size1 16 19 -bitfield iccm1_size1 20 23
+	arc add-reg-type-struct -name identity_t \
+		-bitfield arcver 0 7 -bitfield arcnum 8 15 -bitfield chipid 16 31
+	arc add-reg-type-struct -name isa_config_t -bitfield version 0 7 \
+		-bitfield pc_size 8 11 -bitfield lpc_size 12 15 -bitfield addr_size 16 19 \
+		-bitfield b 20 20 -bitfield a 21 21 -bitfield n 22 22 -bitfield l 23 23 \
+		-bitfield c 24 27 -bitfield d 28 31
+	arc add-reg-type-struct -name mpu_build_t -bitfield version 0 7 \
+		-bitfield regions 8 15 \
+		-bitfield s 16 16 \
+		-bitfield i 17 17
+	arc add-reg-type-struct -name mpu_ecr_t \
+		-bitfield MR 0 7 \
+		-bitfield VT 8 9 \
+		-bitfield EC_CODE 16 31
+	arc add-reg-type-struct -name mpu_en_t \
+		-bitfield UE  3  3 -bitfield UW   4  4 -bitfield UR 5 5 \
+		-bitfield KE  6  6 -bitfield KW   7  7 -bitfield KR 8 8 \
+		-bitfield S  15 15 -bitfield SID 16 23 \
+		-bitfield EN 30 30
+	arc add-reg-type-struct -name mpu_index_t \
+		-bitfield I 0 3 -bitfield M 30 30 -bitfield D 31 31
+	arc add-reg-type-struct -name mpu_rper_t \
+		-bitfield V 0 0 \
+		-bitfield UE 3 3 -bitfield UW 4 4 -bitfield UR 5 5 \
+		-bitfield KE 6 6 -bitfield KW 7 7 -bitfield KR 8 8 \
+		-bitfield S 15 15 -bitfield SID 16 23
+	arc add-reg-type-flags -name status32_t \
+		-flag   H  0 -flag E0   1 -flag E1   2 -flag E2  3 \
+		-flag  E3  4 -flag AE   5 -flag DE   6 -flag  U  7 \
+		-flag   V  8 -flag  C   9 -flag  N  10 -flag  Z 11 \
+		-flag   L 12 -flag DZ  13 -flag SC  14 -flag ES 15 \
+		-flag RB0 16 -flag RB1 17 -flag RB2 18 \
+		-flag  AD 19 -flag US  20 -flag IE  31
+
+	# Core registers
+	set core_regs {
+		r0       0  uint32
+		r1       1  uint32
+		r2       2  uint32
+		r3       3  uint32
+		r4       4  uint32
+		r5       5  uint32
+		r6       6  uint32
+		r7       7  uint32
+		r8       8  uint32
+		r9       9  uint32
+		r10      10 uint32
+		r11      11 uint32
+		r12      12 uint32
+		r13      13 uint32
+		r14      14 uint32
+		r15      15 uint32
+		r16      16 uint32
+		r17      17 uint32
+		r18      18 uint32
+		r19      19 uint32
+		r20      20 uint32
+		r21      21 uint32
+		r22      23 uint32
+		r23      24 uint32
+		r24      24 uint32
+		r25      25 uint32
+		gp       26 data_ptr
+		fp       27 data_ptr
+		sp       28 data_ptr
+		ilink    29 code_ptr
+		r30      30 uint32
+		blink    31 code_ptr
+		r32      32 uint32
+		r33      33 uint32
+		r34      34 uint32
+		r35      35 uint32
+		r36      36 uint32
+		r37      37 uint32
+		r38      38 uint32
+		r39      39 uint32
+		r40      40 uint32
+		r41      41 uint32
+		r42      42 uint32
+		r43      43 uint32
+		r44      44 uint32
+		r45      45 uint32
+		r46      46 uint32
+		r47      47 uint32
+		r48      48 uint32
+		r49      49 uint32
+		r50      50 uint32
+		r51      51 uint32
+		r52      52 uint32
+		r53      53 uint32
+		r54      54 uint32
+		r55      55 uint32
+		r56      56 uint32
+		r57      57 uint32
+		accl     58 uint32
+		acch     59 uint32
+		lp_count 60 uint32
+		limm     61 uint32
+		reserved 62 uint32
+		pcl      63 code_ptr
+	}
+	foreach {reg count type} $core_regs {
+		arc add-reg -name $reg -num $count -core -type $type -g \
+			-feature $core_feature
+	}
+
+	# AUX min
+	set aux_min {
+		0x6 pc       code_ptr
+		0x2 lp_start code_ptr
+		0x3 lp_end   code_ptr
+		0xA status32 status32_t
+	}
+	foreach {num name type} $aux_min {
+		arc add-reg -name $name -num $num -type $type -feature $aux_min_feature -g
+	}
+
+	# AUX other
+	set aux_other {
+		0x004 identity	identity_t
+		0x005 debug		debug_t
+		0x018 aux_dccm	int
+		0x208 aux_iccm	int
+
+
+		0x400 eret		code_ptr
+		0x401 erbta		code_ptr
+		0x402 erstatus	status32_t
+		0x403 ecr		ecr_t
+		0x404 efa		data_ptr
+
+		0x409 mpu_en	mpu_en_t
+
+		0x412 bta		code_ptr
+
+		0x420 mpu_ecr	mpu_ecr_t
+		0x422 mpu_rdb0	int
+		0x423 mpu_rdp0	int
+		0x424 mpu_rdb1	int
+		0x425 mpu_rdp1	int
+		0x426 mpu_rdb2	int
+		0x427 mpu_rdp2	int
+		0x428 mpu_rdb3	int
+		0x429 mpu_rdp3	int
+		0x42A mpu_rdb4	int
+		0x42B mpu_rdp4	int
+		0x42C mpu_rdb5	int
+		0x42D mpu_rdp5	int
+		0x42E mpu_rdb6	int
+		0x42F mpu_rdp6	int
+		0x430 mpu_rdb7	int
+		0x431 mpu_rdp7	int
+		0x432 mpu_rdb8	int
+		0x433 mpu_rdp8	int
+		0x434 mpu_rdb9	int
+		0x435 mpu_rdp9	int
+		0x436 mpu_rdb10	int
+		0x437 mpu_rdp10	int
+		0x438 mpu_rdb11	int
+		0x439 mpu_rdp11	int
+		0x43A mpu_rdb12	int
+		0x43B mpu_rdp12	int
+		0x43C mpu_rdb13	int
+		0x43D mpu_rdp13	int
+		0x43E mpu_rdb14	int
+		0x43F mpu_rdp14	int
+		0x440 mpu_rdb15	int
+		0x441 mpu_rdp15	int
+		0x448 mpu_index	mpu_index_t
+		0x449 mpu_rstart uint32
+		0x44A mpu_rend	uint32
+		0x44B mpu_rper	mpu_rper_t
+		0x44C mpu_probe uint32
+	}
+	foreach {num name type} $aux_other {
+		arc add-reg -name $name -num $num -type $type -feature $aux_other_feature
+	}
+
+	# AUX BCR
+	set bcr {
+		0x6D mpu_build
+		0x74 dccm_build
+		0x76 ap_build
+		0x78 iccm_build
+		0xC1 isa_config
+	}
+	foreach {num reg} $bcr {
+		arc add-reg -name $reg -num $num -type ${reg}_t -bcr -feature $aux_other_feature
+	}
+
+	[target current] configure \
+		-event examine-end "arc_v2_examine_target [target current]"
+}
+
+proc arc_v2_reset { {target ""} } {
+	arc_common_reset $target
+}
diff --git a/tcl/target/snps_em_sk_fpga.cfg b/tcl/target/snps_em_sk_fpga.cfg
new file mode 100644
index 000000000..d52c7e8db
--- /dev/null
+++ b/tcl/target/snps_em_sk_fpga.cfg
@@ -0,0 +1,34 @@
+#  Copyright (C) 2014-2015,2020 Synopsys, Inc.
+#  Anton Kolesov <ant...@sy...>
+#  Didin Evgeniy <di...@sy...>
+#
+#  SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Xilinx Spartan-6 XC6SLX45  FPGA on EM Starter Kit v1.
+# Xilinx Spartan-6 XC6SLX150 FPGA on EM Starter Kit v2.
+#
+
+source [find cpu/arc/em.tcl]
+
+set _CHIPNAME arc-em
+set _TARGETNAME $_CHIPNAME.cpu
+
+# EM SK IDENTITY is 0x200444b1
+# EM SK v2 IDENTITY is 0x200044b1
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -expected-id 0x200444b1 \
+  -expected-id 0x200044b1
+
+set _coreid 0
+set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME \
+  -coreid 0 -dbgbase $_dbgbase -endian little
+
+# There is no SRST, so do a software reset
+$_TARGETNAME configure -event reset-assert "arc_em_reset $_TARGETNAME"
+
+arc_em_init_regs
+
+# vim:ft=tcl
+

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/snps_em_sk.cfg       |  22 ++++
 tcl/board/snps_em_sk_v1.cfg    |  20 +++
 tcl/board/snps_em_sk_v2.1.cfg  |  23 ++++
 tcl/board/snps_em_sk_v2.2.cfg  |  22 ++++
 tcl/cpu/arc/common.tcl         |  40 ++++++
 tcl/cpu/arc/em.tcl             |  32 +++++
 tcl/cpu/arc/v2.tcl             | 288 +++++++++++++++++++++++++++++++++++++++++
 tcl/target/snps_em_sk_fpga.cfg |  34 +++++
 8 files changed, 481 insertions(+)
 create mode 100644 tcl/board/snps_em_sk.cfg
 create mode 100644 tcl/board/snps_em_sk_v1.cfg
 create mode 100644 tcl/board/snps_em_sk_v2.1.cfg
 create mode 100644 tcl/board/snps_em_sk_v2.2.cfg
 create mode 100644 tcl/cpu/arc/common.tcl
 create mode 100644 tcl/cpu/arc/em.tcl
 create mode 100644 tcl/cpu/arc/v2.tcl
 create mode 100644 tcl/target/snps_em_sk_fpga.cfg


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- Log -----------------------------------------------------------------
commit a1c51caafbac67df36dbecb27dd4b195730354b9
Author: Tomas Vanek <va...@fb...>
Date:   Sun Apr 5 17:34:14 2020 +0200

    Revert "rtos/FreeRTOS: Fix FreeRTOS thread list reading"
    
    This reverts commit 6568d29cc1d0d94daafec5bdb73de7d4f17da257.
    The reverted change caused some tasks were missing in thread list.
    
    While on it add a comment explaining the relation of uxTopUsedPriority
    and configMAX_PRIORITIES, introduce config_max_priorities and
    change types to unsigned.
    
    Change-Id: I4371c8882470d13ee7360ef21b132c56ecb95af8
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: http://openocd.zylin.com/5577
    Tested-by: jenkins

diff --git a/src/rtos/FreeRTOS.c b/src/rtos/FreeRTOS.c
index 77c6e79d5..c45d9d645 100644
--- a/src/rtos/FreeRTOS.c
+++ b/src/rtos/FreeRTOS.c
@@ -157,7 +157,6 @@ static const struct symbols FreeRTOS_symbol_list[] = {
 
 static int FreeRTOS_update_threads(struct rtos *rtos)
 {
-	int i = 0;
 	int retval;
 	int tasks_found = 0;
 	const struct FreeRTOS_params *param;
@@ -245,32 +244,40 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 		LOG_ERROR("FreeRTOS: uxTopUsedPriority is not defined, consult the OpenOCD manual for a work-around");
 		return ERROR_FAIL;
 	}
-	int64_t max_used_priority = 0;
+	uint64_t top_used_priority = 0;
+	/* FIXME: endianess error on almost all target_read_buffer(), see also
+	 * other rtoses */
 	retval = target_read_buffer(rtos->target,
 			rtos->symbols[FreeRTOS_VAL_uxTopUsedPriority].address,
 			param->pointer_width,
-			(uint8_t *)&max_used_priority);
+			(uint8_t *)&top_used_priority);
 	if (retval != ERROR_OK)
 		return retval;
-	LOG_DEBUG("FreeRTOS: Read uxTopUsedPriority at 0x%" PRIx64 ", value %" PRId64 "\r\n",
+	LOG_DEBUG("FreeRTOS: Read uxTopUsedPriority at 0x%" PRIx64 ", value %" PRIu64 "\r\n",
 										rtos->symbols[FreeRTOS_VAL_uxTopUsedPriority].address,
-										max_used_priority);
-	if (max_used_priority > FREERTOS_MAX_PRIORITIES) {
-		LOG_ERROR("FreeRTOS maximum used priority is unreasonably big, not proceeding: %" PRId64 "",
-			max_used_priority);
+										top_used_priority);
+	if (top_used_priority > FREERTOS_MAX_PRIORITIES) {
+		LOG_ERROR("FreeRTOS top used priority is unreasonably big, not proceeding: %" PRIu64,
+			top_used_priority);
 		return ERROR_FAIL;
 	}
 
+	/* uxTopUsedPriority was defined as configMAX_PRIORITIES - 1
+	 * in old FreeRTOS versions (before V7.5.3)
+	 * Use contrib/rtos-helpers/FreeRTOS-openocd.c to get compatible symbol
+	 * in newer FreeRTOS versions.
+	 * Here we restore the original configMAX_PRIORITIES value */
+	unsigned int config_max_priorities = top_used_priority + 1;
+
 	symbol_address_t *list_of_lists =
-		malloc(sizeof(symbol_address_t) *
-			(max_used_priority + 5));
+		malloc(sizeof(symbol_address_t) * (config_max_priorities + 5));
 	if (!list_of_lists) {
-		LOG_ERROR("Error allocating memory for %" PRId64 " priorities", max_used_priority);
+		LOG_ERROR("Error allocating memory for %u priorities", config_max_priorities);
 		return ERROR_FAIL;
 	}
 
-	int num_lists;
-	for (num_lists = 0; num_lists < max_used_priority; num_lists++)
+	unsigned int num_lists;
+	for (num_lists = 0; num_lists < config_max_priorities; num_lists++)
 		list_of_lists[num_lists] = rtos->symbols[FreeRTOS_VAL_pxReadyTasksLists].address +
 			num_lists * param->list_width;
 
@@ -280,7 +287,7 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 	list_of_lists[num_lists++] = rtos->symbols[FreeRTOS_VAL_xSuspendedTaskList].address;
 	list_of_lists[num_lists++] = rtos->symbols[FreeRTOS_VAL_xTasksWaitingTermination].address;
 
-	for (i = 0; i < num_lists; i++) {
+	for (unsigned int i = 0; i < num_lists; i++) {
 		if (list_of_lists[i] == 0)
 			continue;
 
@@ -295,7 +302,7 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 			free(list_of_lists);
 			return retval;
 		}
-		LOG_DEBUG("FreeRTOS: Read thread count for list %d at 0x%" PRIx64 ", value %" PRId64 "\r\n",
+		LOG_DEBUG("FreeRTOS: Read thread count for list %u at 0x%" PRIx64 ", value %" PRId64 "\r\n",
 										i, list_of_lists[i], list_thread_count);
 
 		if (list_thread_count == 0)
@@ -313,7 +320,7 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 			free(list_of_lists);
 			return retval;
 		}
-		LOG_DEBUG("FreeRTOS: Read first item for list %d at 0x%" PRIx64 ", value 0x%" PRIx64 "\r\n",
+		LOG_DEBUG("FreeRTOS: Read first item for list %u at 0x%" PRIx64 ", value 0x%" PRIx64 "\r\n",
 										i, list_of_lists[i] + param->list_next_offset, list_elem_ptr);
 
 		while ((list_thread_count > 0) && (list_elem_ptr != 0) &&

-----------------------------------------------------------------------

Summary of changes:
 src/rtos/FreeRTOS.c | 39 +++++++++++++++++++++++----------------
 1 file changed, 23 insertions(+), 16 deletions(-)


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- Log -----------------------------------------------------------------
commit 10b39c3db020464aca14ed41e6453567e26277fa
Author: tscn92 <ts...@ka...>
Date:   Mon Apr 6 15:51:23 2020 +0200

    flash/nor/efm32: Chip support extension (EFM32GG12B Giant)
    
    For flash/nor/efm32 the EFM32GG12B Giant chip has been added to the
    efm32_family along with its respective series and msc_rebase.
    Testen on EFM32GG12B390F board
    
    Change-Id: Idd7dfa93f26ac22566aed1be28f30db678cc0a25
    Signed-off-by: tscn92 <ts...@ka...>
    Reviewed-on: http://openocd.zylin.com/5567
    Tested-by: jenkins
    Reviewed-by: Marc Schink <de...@za...>

diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 479e0d475..9cdc32573 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -169,6 +169,7 @@ static const struct efm32_family_data efm32_families[] = {
 		{ 91, "EFM32JG13B Jade", .series = 1 },
 		{ 100, "EFM32GG11B Giant", .series = 1, .msc_regbase = 0x40000000 },
 		{ 103, "EFM32TG11B Tiny", .series = 1, .msc_regbase = 0x40000000 },
+		{ 106, "EFM32GG12B Giant", .series = 1, .msc_regbase = 0x40000000 },
 		{ 120, "EZR32WG Wonder", .series = 0 },
 		{ 121, "EZR32LG Leopard", .series = 0 },
 		{ 122, "EZR32HG Happy", .series = 0, .page_size = 1024 },

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/efm32.c | 1 +
 1 file changed, 1 insertion(+)


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- Log -----------------------------------------------------------------
commit e7f9ad3932105928cb9aaf6041590be396243402
Author: Tarek BOCHKATI <tar...@gm...>
Date:   Mon Apr 6 13:41:36 2020 +0100

    server: set connection::input_pending type to bool
    
    Change-Id: Ifae8ac2761a7a8fa12732b71c2de456e7558bd2b
    Signed-off-by: Tarek BOCHKATI <tar...@gm...>
    Reviewed-on: http://openocd.zylin.com/5565
    Tested-by: jenkins
    Reviewed-by: Marc Schink <de...@za...>

diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 857cffd9c..6f326fe24 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -277,9 +277,9 @@ static int gdb_get_char_inner(struct connection *connection, int *next_char)
 	gdb_con->buf_cnt--;
 	*next_char = *(gdb_con->buf_p++);
 	if (gdb_con->buf_cnt > 0)
-		connection->input_pending = 1;
+		connection->input_pending = true;
 	else
-		connection->input_pending = 0;
+		connection->input_pending = false;
 #ifdef _DEBUG_GDB_IO_
 	LOG_DEBUG("returned char '%c' (0x%2.2x)", *next_char, *next_char);
 #endif
@@ -302,9 +302,9 @@ static inline int gdb_get_char_fast(struct connection *connection,
 		*next_char = **buf_p;
 		(*buf_p)++;
 		if (*buf_cnt > 0)
-			connection->input_pending = 1;
+			connection->input_pending = true;
 		else
-			connection->input_pending = 0;
+			connection->input_pending = false;
 
 #ifdef _DEBUG_GDB_IO_
 		LOG_DEBUG("returned char '%c' (0x%2.2x)", *next_char, *next_char);
diff --git a/src/server/server.c b/src/server/server.c
index 8e641176a..f32a9c76f 100644
--- a/src/server/server.c
+++ b/src/server/server.c
@@ -76,7 +76,7 @@ static int add_connection(struct service *service, struct command_context *cmd_c
 	memset(&c->sin, 0, sizeof(c->sin));
 	c->cmd_ctx = copy_command_context(cmd_ctx);
 	c->service = service;
-	c->input_pending = 0;
+	c->input_pending = false;
 	c->priv = NULL;
 	c->next = NULL;
 
diff --git a/src/server/server.h b/src/server/server.h
index 96e0b48ef..ab9b72f90 100644
--- a/src/server/server.h
+++ b/src/server/server.h
@@ -49,7 +49,7 @@ struct connection {
 	struct sockaddr_in sin;
 	struct command_context *cmd_ctx;
 	struct service *service;
-	int input_pending;
+	bool input_pending;
 	void *priv;
 	struct connection *next;
 };

-----------------------------------------------------------------------

Summary of changes:
 src/server/gdb_server.c | 8 ++++----
 src/server/server.c     | 2 +-
 src/server/server.h     | 2 +-
 3 files changed, 6 insertions(+), 6 deletions(-)


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