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From: OpenOCD-Gerrit <ope...@us...> - 2020-07-26 19:10:23
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 765c319277958e323ba0537b04c1a9ba818d3fde (commit)
from 36caeddf7175332d90f443153a6bbea2c272dc7e (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 765c319277958e323ba0537b04c1a9ba818d3fde
Author: Jiri Kastner <cz1...@gm...>
Date: Wed Jul 15 12:10:57 2020 +0200
src/target/arm_adi_v5.c: resorted ids
Change-Id: Ieeccf48254032244a86d6cd35793f8f6076527e9
Signed-off-by: Jiri Kastner <cz1...@gm...>
Reviewed-on: http://openocd.zylin.com/5772
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index f19514c85..241c00b04 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1072,6 +1072,8 @@ static const struct {
{ ARM_ID, 0x00c, "Cortex-M4 SCS", "(System Control Space)", },
{ ARM_ID, 0x00d, "CoreSight ETM11", "(Embedded Trace)", },
{ ARM_ID, 0x00e, "Cortex-M7 FPB", "(Flash Patch and Breakpoint)", },
+ { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
+ { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
{ ARM_ID, 0x490, "Cortex-A15 GIC", "(Generic Interrupt Controller)", },
{ ARM_ID, 0x4a1, "Cortex-A53 ROM", "(v8 Memory Map ROM Table)", },
{ ARM_ID, 0x4a2, "Cortex-A57 ROM", "(ROM Table)", },
@@ -1079,14 +1081,12 @@ static const struct {
{ ARM_ID, 0x4a4, "Cortex-A72 ROM", "(ROM Table)", },
{ ARM_ID, 0x4a9, "Cortex-A9 ROM", "(ROM Table)", },
{ ARM_ID, 0x4af, "Cortex-A15 ROM", "(ROM Table)", },
+ { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
{ ARM_ID, 0x4c0, "Cortex-M0+ ROM", "(ROM Table)", },
{ ARM_ID, 0x4c3, "Cortex-M3 ROM", "(ROM Table)", },
{ ARM_ID, 0x4c4, "Cortex-M4 ROM", "(ROM Table)", },
{ ARM_ID, 0x4c7, "Cortex-M7 PPB ROM", "(Private Peripheral Bus ROM Table)", },
{ ARM_ID, 0x4c8, "Cortex-M7 ROM", "(ROM Table)", },
- { ARM_ID, 0x4b5, "Cortex-R5 ROM", "(ROM Table)", },
- { ARM_ID, 0x470, "Cortex-M1 ROM", "(ROM Table)", },
- { ARM_ID, 0x471, "Cortex-M0 ROM", "(ROM Table)", },
{ ARM_ID, 0x906, "CoreSight CTI", "(Cross Trigger)", },
{ ARM_ID, 0x907, "CoreSight ETB", "(Trace Buffer)", },
{ ARM_ID, 0x908, "CoreSight CSTF", "(Trace Funnel)", },
@@ -1149,8 +1149,8 @@ static const struct {
{ 0x0E5, 0x000, "SHARC+/Blackfin+", "", },
{ 0x0F0, 0x440, "Qualcomm QDSS Component v1", "(Qualcomm Designed CoreSight Component v1)", },
{ 0x3eb, 0x181, "Tegra 186 ROM", "(ROM Table)", },
- { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
{ 0x3eb, 0x202, "Denver ETM", "(Denver Embedded Trace)", },
+ { 0x3eb, 0x211, "Tegra 210 ROM", "(ROM Table)", },
{ 0x3eb, 0x302, "Denver Debug", "(Debug Unit)", },
{ 0x3eb, 0x402, "Denver PMU", "(Performance Monitor Unit)", },
/* legacy comment: 0x113: what? */
-----------------------------------------------------------------------
Summary of changes:
src/target/arm_adi_v5.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-07-26 19:09:49
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 36caeddf7175332d90f443153a6bbea2c272dc7e (commit)
via bc987c8e316328df2c65f8bc9055439f4d5ea70d (commit)
from b2821b607460f8ce564b8b9d1cd968439058a108 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 36caeddf7175332d90f443153a6bbea2c272dc7e
Author: Christopher Head <ch...@za...>
Date: Fri Jul 17 11:37:59 2020 -0700
src/flash/nor/stm32f2x: fix format strings
* use proper type codes
* add 0x in front of hex values
* remove some concatenated empty strings
Change-Id: I77e8dd161887f02ecf8019b43d3e8e7cc122ad0e
Signed-off-by: Christopher Head <ch...@za...>
Reviewed-on: http://openocd.zylin.com/5780
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c
index c00b42307..f07f24aae 100644
--- a/src/flash/nor/stm32f2x.c
+++ b/src/flash/nor/stm32f2x.c
@@ -292,7 +292,7 @@ static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
retval = stm32x_get_flash_status(bank, &status);
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("status: 0x%" PRIx32 "", status);
+ LOG_DEBUG("status: 0x%" PRIx32, status);
if ((status & FLASH_BSY) == 0)
break;
if (timeout-- <= 0) {
@@ -349,7 +349,7 @@ static int stm32x_unlock_reg(struct target *target)
return retval;
if (ctrl & FLASH_LOCK) {
- LOG_ERROR("flash not unlocked STM32_FLASH_CR: %" PRIx32, ctrl);
+ LOG_ERROR("flash not unlocked STM32_FLASH_CR: 0x%" PRIx32, ctrl);
return ERROR_TARGET_FAILURE;
}
@@ -381,7 +381,7 @@ static int stm32x_unlock_option_reg(struct target *target)
return retval;
if (ctrl & OPTCR_LOCK) {
- LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32, ctrl);
+ LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: 0x%" PRIx32, ctrl);
return ERROR_TARGET_FAILURE;
}
@@ -778,7 +778,7 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
LOG_ERROR("flash memory write protected");
if (error != 0) {
- LOG_ERROR("flash write failed = %08" PRIx32, error);
+ LOG_ERROR("flash write failed = 0x%08" PRIx32, error);
/* Clear but report errors */
target_write_u32(target, STM32_FLASH_SR, error);
retval = ERROR_FAIL;
@@ -903,7 +903,7 @@ static void setup_sector(struct flash_bank *bank, unsigned int i,
bank->sectors[i].offset = bank->size;
bank->sectors[i].size = size;
bank->size += bank->sectors[i].size;
- LOG_DEBUG("sector %d: %dkBytes", i, size >> 10);
+ LOG_DEBUG("sector %u: %ukBytes", i, size >> 10);
}
static uint16_t sector_size_in_kb(int i, uint16_t max_sector_size_in_kb)
@@ -1037,7 +1037,7 @@ static int stm32x_probe(struct flash_bank *bank)
}
num_sectors = otp_size_in_b / otp_sector_size;
- LOG_INFO("flash size = %d bytes", otp_size_in_b);
+ LOG_INFO("flash size = %" PRIu16 " bytes", otp_size_in_b);
assert(num_sectors > 0);
@@ -1064,7 +1064,7 @@ static int stm32x_probe(struct flash_bank *bank)
int retval = stm32x_get_device_id(bank, &device_id);
if (retval != ERROR_OK)
return retval;
- LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
+ LOG_INFO("device id = 0x%08" PRIx32, device_id);
device_id &= 0xfff; /* only bits 0-11 are used further on */
/* set max flash size depending on family, id taken from AN2606 */
@@ -1137,7 +1137,7 @@ static int stm32x_probe(struct flash_bank *bank)
/* failed reading flash size or flash size invalid (early silicon),
* default to max target family */
if (retval != ERROR_OK || flash_size_in_kb == 0xffff || flash_size_in_kb == 0) {
- LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %dk flash",
+ LOG_WARNING("STM32 flash size failed, probe inaccurate - assuming %" PRIu16 "k flash",
max_flash_size_in_kb);
flash_size_in_kb = max_flash_size_in_kb;
}
@@ -1149,7 +1149,7 @@ static int stm32x_probe(struct flash_bank *bank)
flash_size_in_kb = stm32x_info->user_bank_size / 1024;
}
- LOG_INFO("flash size = %d kbytes", flash_size_in_kb);
+ LOG_INFO("flash size = %" PRIu16 " kbytes", flash_size_in_kb);
/* did we assign flash size? */
assert(flash_size_in_kb != 0xffff);
@@ -1164,10 +1164,10 @@ static int stm32x_probe(struct flash_bank *bank)
}
if ((flash_size_in_kb > 1024) || (optiondata & OPTCR_DB1M)) {
stm32x_info->has_large_mem = true;
- LOG_INFO("Dual Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
+ LOG_INFO("Dual Bank %" PRIu16 " kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
} else {
stm32x_info->has_large_mem = false;
- LOG_INFO("Single Bank %d kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
+ LOG_INFO("Single Bank %" PRIu16 " kiB STM32F42x/43x/469/479 found", flash_size_in_kb);
}
}
@@ -1181,11 +1181,11 @@ static int stm32x_probe(struct flash_bank *bank)
}
if (optiondata & OPTCR_NDBANK) {
stm32x_info->has_large_mem = false;
- LOG_INFO("Single Bank %d kiB STM32F76x/77x found", flash_size_in_kb);
+ LOG_INFO("Single Bank %" PRIu16 " kiB STM32F76x/77x found", flash_size_in_kb);
} else {
stm32x_info->has_large_mem = true;
max_sector_size_in_kb >>= 1; /* sector size divided by 2 in dual-bank mode */
- LOG_INFO("Dual Bank %d kiB STM32F76x/77x found", flash_size_in_kb);
+ LOG_INFO("Dual Bank %" PRIu16 " kiB STM32F76x/77x found", flash_size_in_kb);
}
}
@@ -1428,7 +1428,7 @@ static int get_stm32x_info(struct flash_bank *bank, char *buf, int buf_size)
if (rev_str != NULL)
snprintf(buf, buf_size, "%s - Rev: %s", device_str, rev_str);
else
- snprintf(buf, buf_size, "%s - Rev: unknown (0x%04x)", device_str, rev_id);
+ snprintf(buf, buf_size, "%s - Rev: unknown (0x%04" PRIx16 ")", device_str, rev_id);
return ERROR_OK;
}
@@ -1610,20 +1610,20 @@ COMMAND_HANDLER(stm32f2x_handle_options_read_command)
if (stm32x_info->has_boot_addr) {
uint32_t boot_addr = stm32x_info->option_bytes.boot_addr;
- command_print(CMD, "stm32f2x user_options 0x%03X,"
- " boot_add0 0x%04X, boot_add1 0x%04X",
+ command_print(CMD, "stm32f2x user_options 0x%03" PRIX16 ","
+ " boot_add0 0x%04" PRIX32 ", boot_add1 0x%04" PRIX32,
stm32x_info->option_bytes.user_options,
boot_addr & 0xffff, (boot_addr & 0xffff0000) >> 16);
if (stm32x_info->has_optcr2_pcrop) {
- command_print(CMD, "stm32f2x optcr2_pcrop 0x%08X",
+ command_print(CMD, "stm32f2x optcr2_pcrop 0x%08" PRIX32,
stm32x_info->option_bytes.optcr2_pcrop);
}
} else {
- command_print(CMD, "stm32f2x user_options 0x%03X",
+ command_print(CMD, "stm32f2x user_options 0x%03" PRIX16,
stm32x_info->option_bytes.user_options);
}
} else {
- command_print(CMD, "stm32f2x user_options 0x%02X",
+ command_print(CMD, "stm32f2x user_options 0x%02" PRIX16,
stm32x_info->option_bytes.user_options);
}
@@ -1753,7 +1753,7 @@ COMMAND_HANDLER(stm32x_handle_otp_command)
stm32x_otp_disable(bank);
} else if (strcmp(CMD_ARGV[1], "show") == 0) {
command_print(CMD,
- "OTP memory bank #%d is %s for write commands.",
+ "OTP memory bank #%u is %s for write commands.",
bank->bank_number,
stm32x_is_otp_unlocked(bank) ? "enabled" : "disabled");
} else {
commit bc987c8e316328df2c65f8bc9055439f4d5ea70d
Author: Christopher Head <ch...@za...>
Date: Fri Jul 17 11:04:50 2020 -0700
doc/target/mips: fix grammar
Change-Id: Ib9012a1cfccbe4f69682d106688536c4d92392dd
Signed-off-by: Christopher Head <ch...@za...>
Reviewed-on: http://openocd.zylin.com/5777
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/doc/manual/target/mips.txt b/doc/manual/target/mips.txt
index 25978a3d5..24124e8c9 100644
--- a/doc/manual/target/mips.txt
+++ b/doc/manual/target/mips.txt
@@ -393,15 +393,15 @@ for (i = 0; i < count; i++)
}
@endcode
-Each time when OpenOCD fills data to CPU (via dongle, via dmseg), CPU takes it and proceeds in executing the handler. However, since handler is in a assembly loop,
+Each time when OpenOCD fills data to CPU (via dongle, via dmseg), CPU takes it and proceeds to execute the handler. However, since the handler is in an assembly loop,
CPU comes to next instruction which also fetches data from FASTDATA area. So it stalls.
-Then OpenOCD fills the data again, from it's (OpenOCD's) loop. And this game continues until all the data has been filled.
+Then OpenOCD fills the data again, from its (OpenOCD's) loop. And this game continues until all the data has been filled.
After the last data has been given to CPU it sees that it reached the end address, so it proceeds with next instruction. However, this instruction do not point into dmseg, so
CPU executes bunch of handler instructions (all prologue) and in the end jumps to MIPS32_PRACC_TEXT address.
-On it's side, OpenOCD checks in CPU has jumped back to MIPS32_PRACC_TEXT, which is the confirmation that it correctly executed all the rest of the handler in RAM,
-and that is not stuck somewhere in the RAM, or stalling on some access in dmseg - that would be an error :
+On its side, OpenOCD checks in CPU has jumped back to MIPS32_PRACC_TEXT, which is the confirmation that it correctly executed all the rest of the handler in RAM,
+and that is not stuck somewhere in the RAM, or stalling on some access in dmesg - that would be an error:
@code
address = 0;
-----------------------------------------------------------------------
Summary of changes:
doc/manual/target/mips.txt | 8 ++++----
src/flash/nor/stm32f2x.c | 40 ++++++++++++++++++++--------------------
2 files changed, 24 insertions(+), 24 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-07-26 19:09:17
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via b2821b607460f8ce564b8b9d1cd968439058a108 (commit)
via 8fea8460dbc6ca23e34a16898e86231daab0594d (commit)
from 07df04b3b1eca3b920a9b4b411883d9d44fd06e5 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit b2821b607460f8ce564b8b9d1cd968439058a108
Author: Evgeniy Didin <di...@sy...>
Date: Mon Jul 20 13:27:46 2020 +0300
Introduce tcl config files for Synopsys HSDK board
With this commit we add tcl configure files
for ARCv2 HS Development kit(HSDK). HSDK board
has Quad-core ARC HS38 CPU with L1 and L2
caches.
Change-Id: I372ef45428c7c7ca1421a6da3e5ed08b86f705e0
Signed-off-by: Evgeniy Didin <di...@sy...>
Reviewed-on: http://openocd.zylin.com/5784
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/board/snps_hsdk.cfg b/tcl/board/snps_hsdk.cfg
new file mode 100644
index 000000000..fed7343de
--- /dev/null
+++ b/tcl/board/snps_hsdk.cfg
@@ -0,0 +1,18 @@
+# Copyright (C) 2019, 2020 Synopsys, Inc.
+# Anton Kolesov <ant...@sy...>
+# Didin Evgeniy <di...@sy...>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys DesignWare ARC HSDK Software Development Platform (HS38 cores)
+#
+
+source [find interface/ftdi/snps_sdp.cfg]
+adapter_khz 10000
+
+# ARCs supports only JTAG.
+transport select jtag
+
+# Configure SoC
+source [find target/snps_hsdk.cfg]
diff --git a/tcl/cpu/arc/hs.tcl b/tcl/cpu/arc/hs.tcl
new file mode 100644
index 000000000..f39f2a7d0
--- /dev/null
+++ b/tcl/cpu/arc/hs.tcl
@@ -0,0 +1,58 @@
+# Copyright (C) 2015, 2020 Synopsys, Inc.
+# Anton Kolesov <ant...@sy...>
+# Didin Evgeniy <di...@sy...>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+source [find cpu/arc/v2.tcl]
+
+proc arc_hs_examine_target { target } {
+ # Will set current target for us.
+ arc_v2_examine_target $target
+}
+
+proc arc_hs_init_regs { } {
+ arc_v2_init_regs
+
+ [target current] configure \
+ -event examine-end "arc_hs_examine_target [target current]"
+}
+
+# Scripts in "target" folder should call this function instead of direct
+# invocation of arc_common_reset.
+proc arc_hs_reset { {target ""} } {
+ arc_v2_reset $target
+
+ # Invalidate L2 cache if there is one.
+ set l2_config [$target arc jtag get-aux-reg 0x901]
+ # Will return 0, if cache is not present and register doesn't exist.
+ set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+ if { ($l2_config != 0) && (($l2_ctrl & 1) == 0) } {
+ puts "L2 cache is present and not disabled"
+
+ # Wait until BUSY bit is 0.
+ puts "Invalidating L2 cache..."
+ $target arc jtag set-aux-reg 0x905 1
+ # Dummy read of SLC_AUX_CACHE_CTRL bit, as described in:
+ # https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable.git/commit/arch/arc?id=c70c473396cbdec1168a6eff60e13029c0916854
+ set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+ set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+ while { ($l2_ctrl & 0x100) != 0 } {
+ set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+ }
+
+ # Flush cache if needed. If SLC_AUX_CACHE_CTRL.IM is 1, then invalidate
+ # operation already flushed everything.
+ if { ($l2_ctrl & 0x40) == 0 } {
+ puts "Flushing L2 cache..."
+ $target arc jtag set-aux-reg 0x904 1
+ set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+ set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+ while { [expr $l2_ctrl & 0x100] != 0 } {
+ set l2_ctrl [$target arc jtag get-aux-reg 0x903]
+ }
+ }
+
+ puts "L2 cache has been flushed and invalidated."
+ }
+}
diff --git a/tcl/interface/ftdi/snps_sdp.cfg b/tcl/interface/ftdi/snps_sdp.cfg
new file mode 100644
index 000000000..8d91c6d3c
--- /dev/null
+++ b/tcl/interface/ftdi/snps_sdp.cfg
@@ -0,0 +1,18 @@
+# Copyright (C) 2020 Synopsys, Inc.
+# Anton Kolesov <ant...@sy...>
+# Didin Evgeniy <di...@sy...>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Synopsys SDP Mainboard has embdded FT2232 chip, which is similiar to Digilent
+# HS-1, except that it uses channel B for JTAG communication, instead of
+# channel A.
+#
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6010
+ftdi_layout_init 0x0088 0x008b
+ftdi_channel 1
+
+
diff --git a/tcl/target/snps_hsdk.cfg b/tcl/target/snps_hsdk.cfg
new file mode 100644
index 000000000..634e07adc
--- /dev/null
+++ b/tcl/target/snps_hsdk.cfg
@@ -0,0 +1,86 @@
+# Copyright (C) 2019,2020 Synopsys, Inc.
+# Anton Kolesov <ant...@sy...>
+# Didin Evgeniy <di...@sy...>
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# HS Development Kit SoC.
+#
+# Contains quad-core ARC HS38.
+#
+
+source [find cpu/arc/hs.tcl]
+
+set _coreid 0
+set _dbgbase [expr ($_coreid << 13)]
+
+# CHIPNAME will be used to choose core family (600, 700 or EM). As far as
+# OpenOCD is concerned EM and HS are identical.
+set _CHIPNAME arc-em
+
+# OpenOCD discovers JTAG TAPs in reverse order.
+
+# ARC HS38 core 4
+set _TARGETNAME $_CHIPNAME.cpu4
+jtag newtap $_CHIPNAME cpu4 -irlen 4 -ircapture 0x1 -expected-id 0x200c24b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+# Flush L2$.
+$_TARGETNAME configure -event reset-assert "arc_hs_reset $_TARGETNAME"
+set _coreid [expr $_coreid + 1]
+set _dbgbase [expr ($_coreid << 13)]
+
+arc_hs_init_regs
+
+# Enable L2 cache support for core 4.
+$_TARGETNAME arc cache l2 auto 1
+
+# ARC HS38 core 3
+set _TARGETNAME $_CHIPNAME.cpu3
+jtag newtap $_CHIPNAME cpu3 -irlen 4 -ircapture 0x1 -expected-id 0x200824b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
+set _coreid [expr $_coreid + 1]
+set _dbgbase [expr ($_coreid << 13)]
+
+arc_hs_init_regs
+
+# Enable L2 cache support for core 3.
+$_TARGETNAME arc cache l2 auto 1
+
+# ARC HS38 core 2
+set _TARGETNAME $_CHIPNAME.cpu2
+jtag newtap $_CHIPNAME cpu2 -irlen 4 -ircapture 0x1 -expected-id 0x200424b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
+set _coreid [expr $_coreid + 1]
+set _dbgbase [expr ($_coreid << 13)]
+
+arc_hs_init_regs
+
+# Enable L2 cache support for core 2.
+$_TARGETNAME arc cache l2 auto 1
+
+# ARC HS38 core 1
+set _TARGETNAME $_CHIPNAME.cpu1
+jtag newtap $_CHIPNAME cpu1 -irlen 4 -ircapture 0x1 -expected-id 0x200024b1
+
+target create $_TARGETNAME arcv2 -chain-position $_TARGETNAME
+$_TARGETNAME configure -coreid $_coreid
+$_TARGETNAME configure -dbgbase $_dbgbase
+$_TARGETNAME configure -event reset-assert "arc_common_reset $_TARGETNAME"
+set _coreid [expr $_coreid + 1]
+set _dbgbase [expr 0x00000000 | ($_coreid << 13)]
+arc_hs_init_regs
+
+# Enable L2 cache support for core 1.
+$_TARGETNAME arc cache l2 auto 1
commit 8fea8460dbc6ca23e34a16898e86231daab0594d
Author: Evgeniy Didin <di...@sy...>
Date: Fri Jul 10 14:52:35 2020 +0300
target/arc: Introduce Actionpoints support
Actionpoint mechanism allows to setup HW breakpoints and watchpoints on Synopsys ARC CPUs.
This mechanism is controlled by DEBUG register and by a set of auxilary registers.
Each actionpoint is controlled by 3 aux registers: Actionpoint(AP) match mask(AP_AMM),
AP match value(AP_AMV) and AP control(AC).
Note: some fields of actionpoint_t structure will be used in further
support of watchpoints.
Change-Id: I4efb24675f247cc19d9122501c9e63c3126fcab4
Signed-off-by: Evgeniy Didin <di...@sy...>
Reviewed-on: http://openocd.zylin.com/5763
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/arc.c b/src/target/arc.c
index 1ac4a4335..db338031f 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -603,6 +603,27 @@ static int arc_get_register_value(struct target *target, const char *reg_name,
return ERROR_OK;
}
+static int arc_set_register_value(struct target *target, const char *reg_name,
+ uint32_t value)
+{
+ LOG_DEBUG("reg_name=%s value=0x%08" PRIx32, reg_name, value);
+
+ if (!(target && reg_name)) {
+ LOG_ERROR("Arguments cannot be NULL.");
+ return ERROR_FAIL;
+ }
+
+ struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
+
+ if (!reg)
+ return ERROR_ARC_REGISTER_NOT_FOUND;
+
+ uint8_t value_buf[4];
+ buf_set_u32(value_buf, 0, 32, value);
+ CHECK_RETVAL(reg->type->set(reg, value_buf));
+
+ return ERROR_OK;
+}
/* Configure DCCM's */
static int arc_configure_dccm(struct target *target)
@@ -897,6 +918,44 @@ exit:
return retval;
}
+/**
+ * Finds an actionpoint that triggered last actionpoint event, as specified by
+ * DEBUG.ASR.
+ *
+ * @param actionpoint Pointer to be set to last active actionpoint. Pointer
+ * will be set to NULL if DEBUG.AH is 0.
+ */
+static int get_current_actionpoint(struct target *target,
+ struct arc_actionpoint **actionpoint)
+{
+ assert(target != NULL);
+ assert(actionpoint != NULL);
+
+ uint32_t debug_ah;
+ /* Check if actionpoint caused halt */
+ CHECK_RETVAL(arc_reg_get_field(target, "debug", "ah",
+ &debug_ah));
+
+ if (debug_ah) {
+ struct arc_common *arc = target_to_arc(target);
+ unsigned int ap;
+ uint32_t debug_asr;
+ CHECK_RETVAL(arc_reg_get_field(target, "debug",
+ "asr", &debug_asr));
+
+ for (ap = 0; debug_asr > 1; debug_asr >>= 1)
+ ap += 1;
+
+ assert(ap < arc->actionpoints_num);
+
+ *actionpoint = &(arc->actionpoints_list[ap]);
+ } else {
+ *actionpoint = NULL;
+ }
+
+ return ERROR_OK;
+}
+
static int arc_examine_debug_reason(struct target *target)
{
uint32_t debug_bh;
@@ -916,8 +975,20 @@ static int arc_examine_debug_reason(struct target *target)
/* DEBUG.BH is set if core halted due to BRK instruction. */
target->debug_reason = DBG_REASON_BREAKPOINT;
} else {
- /* TODO: Add Actionpoint check when AP support will be introduced*/
- LOG_WARNING("Unknown debug reason");
+ struct arc_actionpoint *actionpoint = NULL;
+ CHECK_RETVAL(get_current_actionpoint(target, &actionpoint));
+
+ if (actionpoint != NULL) {
+ if (!actionpoint->used)
+ LOG_WARNING("Target halted by an unused actionpoint.");
+
+ if (actionpoint->type == ARC_AP_BREAKPOINT)
+ target->debug_reason = DBG_REASON_BREAKPOINT;
+ else if (actionpoint->type == ARC_AP_WATCHPOINT)
+ target->debug_reason = DBG_REASON_WATCHPOINT;
+ else
+ LOG_WARNING("Unknown type of actionpoint.");
+ }
}
return ERROR_OK;
@@ -1301,6 +1372,7 @@ static void arc_deinit_target(struct target *target)
list_for_each_entry_safe(desc, k, &arc->bcr_reg_descriptions, list)
free_reg_desc(desc);
+ free(arc->actionpoints_list);
free(arc);
}
@@ -1377,10 +1449,54 @@ int arc_read_instruction_u32(struct target *target, uint32_t address,
return ERROR_OK;
}
+/* Actionpoint mechanism allows to setup HW breakpoints
+ * and watchpoints. Each actionpoint is controlled by
+ * 3 aux registers: Actionpoint(AP) match mask(AP_AMM), AP match value(AP_AMV)
+ * and AP control(AC).
+ * This function is for setting/unsetting actionpoints:
+ * at - actionpoint target: trigger on mem/reg access
+ * tt - transaction type : trigger on r/w. */
+static int arc_configure_actionpoint(struct target *target, uint32_t ap_num,
+ uint32_t match_value, uint32_t control_tt, uint32_t control_at)
+{
+ struct arc_common *arc = target_to_arc(target);
+
+ if (control_tt != AP_AC_TT_DISABLE) {
+
+ if (arc->actionpoints_num_avail < 1) {
+ LOG_ERROR("No free actionpoints, maximim amount is %" PRIu32,
+ arc->actionpoints_num);
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ /* Names of register to set - 24 chars should be enough. Looks a little
+ * bit out-of-place for C code, but makes it aligned to the bigger
+ * concept of "ARC registers are defined in TCL" as far as possible.
+ */
+ char ap_amv_reg_name[24], ap_amm_reg_name[24], ap_ac_reg_name[24];
+ snprintf(ap_amv_reg_name, 24, "ap_amv%" PRIu32, ap_num);
+ snprintf(ap_amm_reg_name, 24, "ap_amm%" PRIu32, ap_num);
+ snprintf(ap_ac_reg_name, 24, "ap_ac%" PRIu32, ap_num);
+ CHECK_RETVAL(arc_set_register_value(target, ap_amv_reg_name,
+ match_value));
+ CHECK_RETVAL(arc_set_register_value(target, ap_amm_reg_name, 0));
+ CHECK_RETVAL(arc_set_register_value(target, ap_ac_reg_name,
+ control_tt | control_at));
+ arc->actionpoints_num_avail--;
+ } else {
+ char ap_ac_reg_name[24];
+ snprintf(ap_ac_reg_name, 24, "ap_ac%" PRIu32, ap_num);
+ CHECK_RETVAL(arc_set_register_value(target, ap_ac_reg_name,
+ AP_AC_TT_DISABLE));
+ arc->actionpoints_num_avail++;
+ }
+
+ return ERROR_OK;
+}
+
static int arc_set_breakpoint(struct target *target,
struct breakpoint *breakpoint)
{
-
if (breakpoint->set) {
LOG_WARNING("breakpoint already set");
return ERROR_OK;
@@ -1425,8 +1541,34 @@ static int arc_set_breakpoint(struct target *target,
breakpoint->set = 64; /* Any nice value but 0 */
} else if (breakpoint->type == BKPT_HARD) {
- LOG_DEBUG("Hardware breakpoints are not supported yet!");
- return ERROR_FAIL;
+ struct arc_common *arc = target_to_arc(target);
+ struct arc_actionpoint *ap_list = arc->actionpoints_list;
+ unsigned int bp_num;
+
+ for (bp_num = 0; bp_num < arc->actionpoints_num; bp_num++) {
+ if (!ap_list[bp_num].used)
+ break;
+ }
+
+ if (bp_num >= arc->actionpoints_num) {
+ LOG_ERROR("No free actionpoints, maximum amount is %" PRIu32,
+ arc->actionpoints_num);
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ int retval = arc_configure_actionpoint(target, bp_num,
+ breakpoint->address, AP_AC_TT_READWRITE, AP_AC_AT_INST_ADDR);
+
+ if (retval == ERROR_OK) {
+ breakpoint->set = bp_num + 1;
+ ap_list[bp_num].used = 1;
+ ap_list[bp_num].bp_value = breakpoint->address;
+ ap_list[bp_num].type = ARC_AP_BREAKPOINT;
+
+ LOG_DEBUG("bpid: %" PRIu32 ", bp_num %u bp_value 0x%" PRIx32,
+ breakpoint->unique_id, bp_num, ap_list[bp_num].bp_value);
+ }
+
} else {
LOG_DEBUG("ERROR: setting unknown breakpoint type");
return ERROR_FAIL;
@@ -1491,8 +1633,27 @@ static int arc_unset_breakpoint(struct target *target,
breakpoint->set = 0;
} else if (breakpoint->type == BKPT_HARD) {
- LOG_WARNING("Hardware breakpoints are not supported yet!");
- return ERROR_FAIL;
+ struct arc_common *arc = target_to_arc(target);
+ struct arc_actionpoint *ap_list = arc->actionpoints_list;
+ unsigned int bp_num = breakpoint->set - 1;
+
+ if ((breakpoint->set == 0) || (bp_num >= arc->actionpoints_num)) {
+ LOG_DEBUG("Invalid actionpoint ID: %u in breakpoint: %" PRIu32,
+ bp_num, breakpoint->unique_id);
+ return ERROR_OK;
+ }
+
+ retval = arc_configure_actionpoint(target, bp_num,
+ breakpoint->address, AP_AC_TT_DISABLE, AP_AC_AT_INST_ADDR);
+
+ if (retval == ERROR_OK) {
+ breakpoint->set = 0;
+ ap_list[bp_num].used = 0;
+ ap_list[bp_num].bp_value = 0;
+
+ LOG_DEBUG("bpid: %" PRIu32 " - released actionpoint ID: %i",
+ breakpoint->unique_id, bp_num);
+ }
} else {
LOG_DEBUG("ERROR: unsetting unknown breakpoint type");
return ERROR_FAIL;
@@ -1530,6 +1691,115 @@ static int arc_remove_breakpoint(struct target *target,
return ERROR_OK;
}
+void arc_reset_actionpoints(struct target *target)
+{
+ struct arc_common *arc = target_to_arc(target);
+ struct arc_actionpoint *ap_list = arc->actionpoints_list;
+ struct breakpoint *next_b;
+
+ while (target->breakpoints) {
+ next_b = target->breakpoints->next;
+ arc_remove_breakpoint(target, target->breakpoints);
+ free(target->breakpoints->orig_instr);
+ free(target->breakpoints);
+ target->breakpoints = next_b;
+ }
+ for (unsigned int i = 0; i < arc->actionpoints_num; i++) {
+ if ((ap_list[i].used) && (ap_list[i].reg_address))
+ arc_remove_auxreg_actionpoint(target, ap_list[i].reg_address);
+ }
+}
+
+int arc_set_actionpoints_num(struct target *target, uint32_t ap_num)
+{
+ LOG_DEBUG("target=%s actionpoints=%" PRIu32, target_name(target), ap_num);
+ struct arc_common *arc = target_to_arc(target);
+
+ /* Make sure that there are no enabled actionpoints in target. */
+ arc_reset_actionpoints(target);
+
+ /* Assume that all points have been removed from target. */
+ free(arc->actionpoints_list);
+
+ arc->actionpoints_num_avail = ap_num;
+ arc->actionpoints_num = ap_num;
+ /* calloc can be safely called when ncount == 0. */
+ arc->actionpoints_list = calloc(ap_num, sizeof(struct arc_actionpoint));
+
+ if (!arc->actionpoints_list) {
+ LOG_ERROR("Unable to allocate memory");
+ return ERROR_FAIL;
+ }
+ return ERROR_OK;
+}
+
+
+int arc_add_auxreg_actionpoint(struct target *target,
+ uint32_t auxreg_addr, uint32_t transaction)
+{
+ unsigned int ap_num = 0;
+ int retval = ERROR_OK;
+
+ if (target->state != TARGET_HALTED)
+ return ERROR_TARGET_NOT_HALTED;
+
+ struct arc_common *arc = target_to_arc(target);
+ struct arc_actionpoint *ap_list = arc->actionpoints_list;
+
+ while (ap_list[ap_num].used)
+ ap_num++;
+
+ if (ap_num >= arc->actionpoints_num) {
+ LOG_ERROR("No actionpoint free, maximum amount is %u",
+ arc->actionpoints_num);
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ retval = arc_configure_actionpoint(target, ap_num,
+ auxreg_addr, transaction, AP_AC_AT_AUXREG_ADDR);
+
+ if (retval == ERROR_OK) {
+ ap_list[ap_num].used = 1;
+ ap_list[ap_num].reg_address = auxreg_addr;
+ }
+
+ return retval;
+}
+
+int arc_remove_auxreg_actionpoint(struct target *target, uint32_t auxreg_addr)
+{
+ int retval = ERROR_OK;
+ bool ap_found = false;
+ unsigned int ap_num = 0;
+
+ if (target->state != TARGET_HALTED)
+ return ERROR_TARGET_NOT_HALTED;
+
+ struct arc_common *arc = target_to_arc(target);
+ struct arc_actionpoint *ap_list = arc->actionpoints_list;
+
+ while ((ap_list[ap_num].used) && (ap_num < arc->actionpoints_num)) {
+ if (ap_list[ap_num].reg_address == auxreg_addr) {
+ ap_found = true;
+ break;
+ }
+ ap_num++;
+ }
+
+ if (ap_found) {
+ retval = arc_configure_actionpoint(target, ap_num,
+ auxreg_addr, AP_AC_TT_DISABLE, AP_AC_AT_AUXREG_ADDR);
+
+ if (retval == ERROR_OK) {
+ ap_list[ap_num].used = 0;
+ ap_list[ap_num].bp_value = 0;
+ }
+ } else {
+ LOG_ERROR("Register actionpoint not found");
+ }
+ return retval;
+}
+
/* Helper function which swiches core to single_step mode by
* doing aux r/w operations. */
int arc_config_step(struct target *target, int enable_step)
diff --git a/src/target/arc.h b/src/target/arc.h
index 664141159..f9ee5b45e 100644
--- a/src/target/arc.h
+++ b/src/target/arc.h
@@ -78,6 +78,16 @@
#define SLC_AUX_CACHE_INV 0x905
#define L2_INV_IV BIT(0)
+ /* Action Point */
+#define AP_AC_AT_INST_ADDR 0x0
+#define AP_AC_AT_MEMORY_ADDR 0x2
+#define AP_AC_AT_AUXREG_ADDR 0x4
+
+#define AP_AC_TT_DISABLE 0x00
+#define AP_AC_TT_WRITE 0x10
+#define AP_AC_TT_READ 0x20
+#define AP_AC_TT_READWRITE 0x30
+
struct arc_reg_bitfield {
struct reg_data_type_bitfield bitfield;
char name[REG_TYPE_MAX_NAME_LENGTH];
@@ -96,8 +106,6 @@ struct arc_reg_data_type {
};
};
-
-
/* Standard GDB register types */
static const struct reg_data_type standard_gdb_types[] = {
{ .type = REG_TYPE_INT, .id = "int" },
@@ -118,6 +126,18 @@ static const struct reg_data_type standard_gdb_types[] = {
{ .type = REG_TYPE_IEEE_DOUBLE, .id = "ieee_double" },
};
+enum arc_actionpointype {
+ ARC_AP_BREAKPOINT,
+ ARC_AP_WATCHPOINT,
+};
+
+/* Actionpoint related fields */
+struct arc_actionpoint {
+ int used;
+ uint32_t bp_value;
+ uint32_t reg_address;
+ enum arc_actionpointype type;
+};
struct arc_common {
uint32_t common_magic;
@@ -172,6 +192,11 @@ struct arc_common {
unsigned long pc_index_in_cache;
/* DEBUG register location in register cache. */
unsigned long debug_index_in_cache;
+
+ /* Actionpoints */
+ unsigned int actionpoints_num;
+ unsigned int actionpoints_num_avail;
+ struct arc_actionpoint *actionpoints_list;
};
/* Borrowed from nds32.h */
@@ -284,4 +309,9 @@ int arc_reg_get_field(struct target *target, const char *reg_name,
int arc_cache_flush(struct target *target);
int arc_cache_invalidate(struct target *target);
+int arc_add_auxreg_actionpoint(struct target *target,
+ uint32_t auxreg_addr, uint32_t transaction);
+int arc_remove_auxreg_actionpoint(struct target *target, uint32_t auxreg_addr);
+int arc_set_actionpoints_num(struct target *target, uint32_t ap_num);
+
#endif /* OPENOCD_TARGET_ARC_H */
diff --git a/src/target/arc_cmd.c b/src/target/arc_cmd.c
index 59e1645d6..a1d5a0936 100644
--- a/src/target/arc_cmd.c
+++ b/src/target/arc_cmd.c
@@ -929,6 +929,50 @@ COMMAND_HANDLER(arc_l2_cache_disable_auto_cmd)
&arc->has_l2cache, "target has l2 cache enabled");
}
+static int jim_handle_actionpoints_num(Jim_Interp *interp, int argc,
+ Jim_Obj * const *argv)
+{
+ Jim_GetOptInfo goi;
+ Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
+
+ LOG_DEBUG("-");
+
+ if (goi.argc >= 2) {
+ Jim_WrongNumArgs(interp, goi.argc, goi.argv, "[<unsigned integer>]");
+ return JIM_ERR;
+ }
+
+ struct command_context *context = current_command_context(interp);
+ assert(context);
+
+ struct target *target = get_current_target(context);
+
+ if (!target) {
+ Jim_SetResultFormatted(goi.interp, "No current target");
+ return JIM_ERR;
+ }
+
+ struct arc_common *arc = target_to_arc(target);
+ /* It is not possible to pass &arc->actionpoints_num directly to
+ * handle_command_parse_uint, because this value should be valid during
+ * "actionpoint reset, initiated by arc_set_actionpoints_num. */
+ uint32_t ap_num = arc->actionpoints_num;
+
+ if (goi.argc == 1) {
+ JIM_CHECK_RETVAL(arc_cmd_jim_get_uint32(&goi, &ap_num));
+ int e = arc_set_actionpoints_num(target, ap_num);
+ if (e != ERROR_OK) {
+ Jim_SetResultFormatted(goi.interp,
+ "Failed to set number of actionpoints");
+ return JIM_ERR;
+ }
+ }
+
+ Jim_SetResultInt(interp, ap_num);
+
+ return JIM_OK;
+}
+
/* ----- Exported target commands ------------------------------------------ */
const struct command_registration arc_l2_cache_group_handlers[] = {
@@ -1024,6 +1068,13 @@ static const struct command_registration arc_core_command_handlers[] = {
.usage = "",
.chain = arc_cache_group_handlers,
},
+ {
+ .name = "num-actionpoints",
+ .jim_handler = jim_handle_actionpoints_num,
+ .mode = COMMAND_ANY,
+ .usage = "[<unsigned integer>]",
+ .help = "Prints or sets amount of actionpoints in the processor.",
+ },
COMMAND_REGISTRATION_DONE
};
diff --git a/tcl/cpu/arc/v2.tcl b/tcl/cpu/arc/v2.tcl
index ad55361a5..a3172c220 100644
--- a/tcl/cpu/arc/v2.tcl
+++ b/tcl/cpu/arc/v2.tcl
@@ -30,6 +30,32 @@ proc arc_v2_examine_target { {target ""} } {
r13 r14 r15 r16 r17 r18 r19 r20 r21 r22 r23 r24 r25 \
gp fp sp ilink r30 blink lp_count pcl
+ # Actionpoints
+ if { [arc get-reg-field ap_build version] == 5 } {
+ set ap_build_type [arc get-reg-field ap_build type]
+ # AP_BUILD.TYPE > 0b0110 is reserved in current ISA.
+ # Current ISA supports up to 8 actionpoints.
+ if { $ap_build_type < 8 } {
+ # Two LSB bits of AP_BUILD.TYPE define amount of actionpoints:
+ # 0b00 - 2 actionpoints
+ # 0b01 - 4 actionpoints
+ # 0b10 - 8 actionpoints
+ # 0b11 - reserved.
+ set ap_num [expr 0x2 << ($ap_build_type & 3)]
+ # Expression on top may produce 16 action points - which is a
+ # reserved value for now.
+ if { $ap_num < 16 } {
+ # Enable actionpoint registers
+ for {set i 0} {$i < $ap_num} {incr i} {
+ arc set-reg-exists ap_amv$i ap_amm$i ap_ac$i
+ }
+
+ # Set amount of actionpoints
+ arc num-actionpoints $ap_num
+ }
+ }
+ }
+
# DCCM
set dccm_version [arc get-reg-field dccm_build version]
if { $dccm_version == 3 || $dccm_version == 4 } {
@@ -213,6 +239,30 @@ proc arc_v2_init_regs { } {
0x018 aux_dccm int
0x208 aux_iccm int
+ 0x220 ap_amv0 uint32
+ 0x221 ap_amm0 uint32
+ 0x222 ap_ac0 ap_control_t
+ 0x223 ap_amv1 uint32
+ 0x224 ap_amm1 uint32
+ 0x225 ap_ac1 ap_control_t
+ 0x226 ap_amv2 uint32
+ 0x227 ap_amm2 uint32
+ 0x228 ap_ac2 ap_control_t
+ 0x229 ap_amv3 uint32
+ 0x22A ap_amm3 uint32
+ 0x22B ap_ac3 ap_control_t
+ 0x22C ap_amv4 uint32
+ 0x22D ap_amm4 uint32
+ 0x22E ap_ac4 ap_control_t
+ 0x22F ap_amv5 uint32
+ 0x230 ap_amm5 uint32
+ 0x231 ap_ac5 ap_control_t
+ 0x232 ap_amv6 uint32
+ 0x233 ap_amm6 uint32
+ 0x234 ap_ac6 ap_control_t
+ 0x235 ap_amv7 uint32
+ 0x236 ap_amm7 uint32
+ 0x237 ap_ac7 ap_control_t
0x400 eret code_ptr
0x401 erbta code_ptr
@@ -285,4 +335,12 @@ proc arc_v2_init_regs { } {
proc arc_v2_reset { {target ""} } {
arc_common_reset $target
+
+ # Disable all actionpoints. Cannot write via regcache yet, because it will
+ # not be flushed and all changes to registers will get lost. Therefore has
+ # to write directly via JTAG layer...
+ set num_ap [arc num-actionpoints]
+ for {set i 0} {$i < $num_ap} {incr i} {
+ arc jtag set-aux-reg [expr 0x222 + $i * 3] 0
+ }
}
-----------------------------------------------------------------------
Summary of changes:
src/target/arc.c | 284 +++++++++++++++++++++++++++++++++++++++-
src/target/arc.h | 34 ++++-
src/target/arc_cmd.c | 51 ++++++++
tcl/board/snps_hsdk.cfg | 18 +++
tcl/cpu/arc/hs.tcl | 58 ++++++++
tcl/cpu/arc/v2.tcl | 58 ++++++++
tcl/interface/ftdi/snps_sdp.cfg | 18 +++
tcl/target/snps_hsdk.cfg | 86 ++++++++++++
8 files changed, 598 insertions(+), 9 deletions(-)
create mode 100644 tcl/board/snps_hsdk.cfg
create mode 100644 tcl/cpu/arc/hs.tcl
create mode 100644 tcl/interface/ftdi/snps_sdp.cfg
create mode 100644 tcl/target/snps_hsdk.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-07-21 16:45:43
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 07df04b3b1eca3b920a9b4b411883d9d44fd06e5 (commit)
from 68611efcdf50327ebeccc8f2533380dc4d9fbf40 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 07df04b3b1eca3b920a9b4b411883d9d44fd06e5
Author: Hellosun Wu <wuj...@gm...>
Date: Mon Feb 3 10:47:02 2020 +0800
spi: add MX25U1635E flash
* Macronix 16 MBit SPI flash
* https://www.macronix.com/en-us/products/NOR-Flash/Serial-NOR-Flash/Pages/spec.aspx?p=MX25R1635F&m=Serial%20NOR%20Flash&n=PM2161
* used e.g. on Andestech ADP-XC7KFF676
Change-Id: Ida701cf3832e3302aa29b4dded1c390c5ff8c482
Signed-off-by: Hellosun Wu <wuj...@gm...>
Reviewed-on: http://openocd.zylin.com/5428
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <and...@gm...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/spi.c b/src/flash/nor/spi.c
index af72ffc40..54ee57e66 100644
--- a/src/flash/nor/spi.c
+++ b/src/flash/nor/spi.c
@@ -88,6 +88,7 @@ const struct flash_device flash_devices[] = {
FLASH_ID("mac 25r1635f", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x001528c2, 0x100, 0x10000, 0x200000),
FLASH_ID("mac 25r3235f", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x001628c2, 0x100, 0x10000, 0x400000),
FLASH_ID("mac 25r6435f", 0x03, 0x00, 0x02, 0xd8, 0xc7, 0x001728c2, 0x100, 0x10000, 0x800000),
+ FLASH_ID("mac 25u1635e", 0x03, 0xeb, 0x02, 0x20, 0xc7, 0x003525c2, 0x100, 0x1000, 0x100000),
FLASH_ID("micron n25q064", 0x03, 0xeb, 0x02, 0xd8, 0xc7, 0x0017ba20, 0x100, 0x10000, 0x800000),
FLASH_ID("micron n25q128", 0x03, 0xeb, 0x02, 0xd8, 0xc7, 0x0018ba20, 0x100, 0x10000, 0x1000000),
FLASH_ID("micron n25q256 3v", 0x13, 0xec, 0x12, 0xdc, 0xc7, 0x0019ba20, 0x100, 0x10000, 0x2000000),
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/spi.c | 1 +
1 file changed, 1 insertion(+)
hooks/post-receive
--
Main OpenOCD repository
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|
From: OpenOCD-Gerrit <ope...@us...> - 2020-07-13 23:40:52
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 68611efcdf50327ebeccc8f2533380dc4d9fbf40 (commit)
via 97b710131693bdcfdc112e4c183d8e65bd909e94 (commit)
via e466f389a9f0e824d62c5ed6092507a2812427b7 (commit)
from 3a5f84f8187ce5b473f0eaafa0d68d1ab23ec0cd (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 68611efcdf50327ebeccc8f2533380dc4d9fbf40
Author: Antonio Borneo <bor...@gm...>
Date: Mon Jun 29 23:58:09 2020 +0200
cmsis-dap: fix USB interface for NXP LPC-Link2
The adapter NXP LPC-Link2 is a USB composite device that provides
five interfaces; among three of them that are of HID class, only
one is cmsis-dap.
Accordingly to ticket 255, OpenOCD code is not opening the right
HID interface; then it fails to communicate with the cmsis-dap
while checking the adapter's info.
Unfortunately, hidapi does not provide any support for reading the
string descriptor of the interface, otherwise it would have been
trivial to look for the right cmsis-dap interface.
In fact the cmsis-dap specification reports:
The CMSIS-DAP Firmware can be also part of a USB composite
device. If this case, the HID Interface String must
contain the sub-string CMSIS-DAP.
This requirement is satisfied by the USB device descriptor of the
LPC-Link2 reported below, but cannot be used.
Add a quirk to let OpenOCD only accept interface number zero on a
LPC-Link2 device.
Bus 001 Device 050: ID 1fc9:0090 NXP Semiconductors
Device Descriptor:
bLength 18
bDescriptorType 1
bcdUSB 2.00
bDeviceClass 239 Miscellaneous Device
bDeviceSubClass 2
bDeviceProtocol 1 Interface Association
bMaxPacketSize0 64
idVendor 0x1fc9 NXP Semiconductors
idProduct 0x0090
bcdDevice 1.00
iManufacturer 1 NXP Semiconductors
iProduct 2 LPC-LINK2 CMSIS-DAP V5.224
iSerial 3 I3F4AABA
bNumConfigurations 1
Configuration Descriptor:
bLength 9
bDescriptorType 2
wTotalLength 0x00ab
bNumInterfaces 5
bConfigurationValue 1
iConfiguration 0
bmAttributes 0x80
(Bus Powered)
MaxPower 500mA
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 0
bAlternateSetting 0
bNumEndpoints 2
bInterfaceClass 3 Human Interface Device
bInterfaceSubClass 0
bInterfaceProtocol 0
iInterface 4 LPC-LINK2 CMSIS-DAP V5.224
HID Device Descriptor:
bLength 9
bDescriptorType 33
bcdHID 1.00
bCountryCode 0 Not supported
bNumDescriptors 1
bDescriptorType 34 Report
wDescriptorLength 35
Report Descriptors:
** UNAVAILABLE **
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x81 EP 1 IN
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0400 1x 1024 bytes
bInterval 4
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x01 EP 1 OUT
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0400 1x 1024 bytes
bInterval 4
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 4
bAlternateSetting 0
bNumEndpoints 2
bInterfaceClass 3 Human Interface Device
bInterfaceSubClass 0
bInterfaceProtocol 0
iInterface 7 LPC-LINK2 DATA PORT
HID Device Descriptor:
bLength 9
bDescriptorType 33
bcdHID 1.00
bCountryCode 0 Not supported
bNumDescriptors 1
bDescriptorType 34 Report
wDescriptorLength 35
Report Descriptors:
** UNAVAILABLE **
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x84 EP 4 IN
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0400 1x 1024 bytes
bInterval 1
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x04 EP 4 OUT
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0400 1x 1024 bytes
bInterval 1
Interface Association:
bLength 8
bDescriptorType 11
bFirstInterface 1
bInterfaceCount 2
bFunctionClass 2 Communications
bFunctionSubClass 2 Abstract (modem)
bFunctionProtocol 0
iFunction 5 VCOM
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 1
bAlternateSetting 0
bNumEndpoints 1
bInterfaceClass 2 Communications
bInterfaceSubClass 2 Abstract (modem)
bInterfaceProtocol 0
iInterface 5 VCOM
CDC Header:
bcdCDC 1.10
CDC Call Management:
bmCapabilities 0x01
call management
bDataInterface 2
CDC ACM:
bmCapabilities 0x02
line coding and serial state
CDC Union:
bMasterInterface 1
bSlaveInterface 2
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x83 EP 3 IN
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0010 1x 16 bytes
bInterval 4
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 2
bAlternateSetting 0
bNumEndpoints 2
bInterfaceClass 10 CDC Data
bInterfaceSubClass 0
bInterfaceProtocol 0
iInterface 5 VCOM
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x02 EP 2 OUT
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x82 EP 2 IN
bmAttributes 2
Transfer Type Bulk
Synch Type None
Usage Type Data
wMaxPacketSize 0x0200 1x 512 bytes
bInterval 0
Interface Descriptor:
bLength 9
bDescriptorType 4
bInterfaceNumber 3
bAlternateSetting 0
bNumEndpoints 2
bInterfaceClass 3 Human Interface Device
bInterfaceSubClass 0
bInterfaceProtocol 0
iInterface 6 LPCSIO
HID Device Descriptor:
bLength 9
bDescriptorType 33
bcdHID 1.11
bCountryCode 0 Not supported
bNumDescriptors 1
bDescriptorType 34 Report
wDescriptorLength 33
Report Descriptors:
** UNAVAILABLE **
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x85 EP 5 IN
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0040 1x 64 bytes
bInterval 2
Endpoint Descriptor:
bLength 7
bDescriptorType 5
bEndpointAddress 0x05 EP 5 OUT
bmAttributes 3
Transfer Type Interrupt
Synch Type None
Usage Type Data
wMaxPacketSize 0x0040 1x 64 bytes
bInterval 2
Device Qualifier (for other device speed):
bLength 10
bDescriptorType 6
bcdUSB 2.00
bDeviceClass 0
bDeviceSubClass 0
bDeviceProtocol 0
bMaxPacketSize0 64
bNumConfigurations 1
Device Status: 0x0000
(Bus Powered)
Change-Id: Ib3d46f87743a2d35a266842cb356035d898d466e
Signed-off-by: Antonio Borneo <bor...@gm...>
Suggested-by: Masatoshi Tateishi <tat...@gm...>
Reported-by: Donald Bailey <do...@us...>
Fixes: https://sourceforge.net/p/openocd/tickets/255/
Reviewed-on: http://openocd.zylin.com/5732
Tested-by: jenkins
diff --git a/src/jtag/drivers/cmsis_dap_usb.c b/src/jtag/drivers/cmsis_dap_usb.c
index 891583680..d87d0c9a5 100644
--- a/src/jtag/drivers/cmsis_dap_usb.c
+++ b/src/jtag/drivers/cmsis_dap_usb.c
@@ -270,6 +270,10 @@ static int cmsis_dap_usb_open(void)
found = true;
}
+ /* LPC-LINK2 has cmsis-dap on interface 0 and other HID functions on other interfaces */
+ if (cur_dev->vendor_id == 0x1fc9 && cur_dev->product_id == 0x0090 && cur_dev->interface_number != 0)
+ found = false;
+
if (found) {
/* we have found an adapter, so exit further checks */
/* check serial number matches if given */
commit 97b710131693bdcfdc112e4c183d8e65bd909e94
Author: Antonio Borneo <bor...@gm...>
Date: Mon Jun 29 23:22:37 2020 +0200
cmsis-dap: prevent hidapi to search again for the adapter
The code in cmsis_dap_usb_open() already searches for the right
HID device that corresponds to the adapter. By calling hid_open()
it asks hidapi to re-search the adapter again based on the VID:PID
and the serial string of the adapter it has just found!
Apart from being a run-time overhead, this has an additional
drawback; there are USB adapters built as composite USB devices
that, beside the cmsis-dap HID interface, have other HID
interfaces for other purposes.
A typical example is the NXP LPC-Link2, that over the 5 interfaces
0) cmsis-dap (HID)
1) VCOM-CDC
2) VCOM-CDC
3) LPCSIO (HID)
4) LPC-LINK2 DATA PORT (HID)
has 3 of them of HID class.
The code in cmsis_dap_usb_open() could select the right interface
but then cannot propagate this information to hid_open().
Replace the call to hid_open() with hid_open_path(), passing as
parameter the "unique" path of the HID device already found.
Checking in hidapi source code, the implementation of hid_open()
consists in enumerating the HID devices, scan for the first one
matching VID:PID and serial number, and opening it by calling
hid_open_path(). This analysis highlights that using directly
hid_open_path() should not introduce any regression.
While applying these changes, move hid_init() before enumerating
the HID devices. This has no real consequences because the HID API
is marked as optional but, logically, it should be called before
any other HID API.
Change-Id: I77ec01dca64223ec597f21f188f363366d0049c6
Signed-off-by: Antonio Borneo <bor...@gm...>
Suggested-by: Masatoshi Tateishi <tat...@gm...>
Reviewed-on: http://openocd.zylin.com/5731
Tested-by: jenkins
diff --git a/src/jtag/drivers/cmsis_dap_usb.c b/src/jtag/drivers/cmsis_dap_usb.c
index ee1cb533c..891583680 100644
--- a/src/jtag/drivers/cmsis_dap_usb.c
+++ b/src/jtag/drivers/cmsis_dap_usb.c
@@ -229,14 +229,16 @@ static int cmsis_dap_usb_open(void)
int i;
struct hid_device_info *devs, *cur_dev;
unsigned short target_vid, target_pid;
- wchar_t *target_serial = NULL;
-
bool found = false;
- bool serial_found = false;
target_vid = 0;
target_pid = 0;
+ if (hid_init() != 0) {
+ LOG_ERROR("unable to open HIDAPI");
+ return ERROR_FAIL;
+ }
+
/*
* The CMSIS-DAP specification stipulates:
* "The Product String must contain "CMSIS-DAP" somewhere in the string. This is used by the
@@ -273,7 +275,6 @@ static int cmsis_dap_usb_open(void)
/* check serial number matches if given */
if (cmsis_dap_serial != NULL) {
if ((cur_dev->serial_number != NULL) && wcscmp(cmsis_dap_serial, cur_dev->serial_number) == 0) {
- serial_found = true;
break;
}
} else
@@ -288,23 +289,16 @@ static int cmsis_dap_usb_open(void)
if (NULL != cur_dev) {
target_vid = cur_dev->vendor_id;
target_pid = cur_dev->product_id;
- if (serial_found)
- target_serial = cmsis_dap_serial;
}
- hid_free_enumeration(devs);
-
if (target_vid == 0 && target_pid == 0) {
LOG_ERROR("unable to find CMSIS-DAP device");
+ hid_free_enumeration(devs);
return ERROR_FAIL;
}
- if (hid_init() != 0) {
- LOG_ERROR("unable to open HIDAPI");
- return ERROR_FAIL;
- }
-
- dev = hid_open(target_vid, target_pid, target_serial);
+ dev = hid_open_path(cur_dev->path);
+ hid_free_enumeration(devs);
if (dev == NULL) {
LOG_ERROR("unable to open CMSIS-DAP device 0x%x:0x%x", target_vid, target_pid);
commit e466f389a9f0e824d62c5ed6092507a2812427b7
Author: Antonio Borneo <bor...@gm...>
Date: Sun Jun 28 23:19:23 2020 +0200
jtag/drivers: replace perror() with LOG_ERROR()
The function perror() sends the output to stderr, but OpenOCD
cannot intercept such output to send it to the log.
Replace all occurrences of perror() with LOG_ERROR(), but keeping
the same output format of perror().
The replacement is done automatically through:
sed -i 's/perror("\([^":]*\)[: ]*")/LOG_ERROR("\1: %s", strerror(errno))/' src/jtag/drivers/*.c
Change-Id: I4c140bdb09235d56cfd8bef75da9b56fbe7c2aec
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5728
Tested-by: jenkins
diff --git a/src/jtag/drivers/at91rm9200.c b/src/jtag/drivers/at91rm9200.c
index 1026847fe..bccb9bb23 100644
--- a/src/jtag/drivers/at91rm9200.c
+++ b/src/jtag/drivers/at91rm9200.c
@@ -231,14 +231,14 @@ static int at91rm9200_init(void)
dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
if (dev_mem_fd < 0) {
- perror("open");
+ LOG_ERROR("open: %s", strerror(errno));
return ERROR_JTAG_INIT_FAILED;
}
sys_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
MAP_SHARED, dev_mem_fd, AT91C_BASE_SYS);
if (sys_controller == MAP_FAILED) {
- perror("mmap");
+ LOG_ERROR("mmap: %s", strerror(errno));
close(dev_mem_fd);
return ERROR_JTAG_INIT_FAILED;
}
diff --git a/src/jtag/drivers/bcm2835gpio.c b/src/jtag/drivers/bcm2835gpio.c
index f868516d9..40cb5aa0b 100644
--- a/src/jtag/drivers/bcm2835gpio.c
+++ b/src/jtag/drivers/bcm2835gpio.c
@@ -473,7 +473,7 @@ static int bcm2835gpio_init(void)
dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
}
if (dev_mem_fd < 0) {
- perror("open");
+ LOG_ERROR("open: %s", strerror(errno));
return ERROR_JTAG_INIT_FAILED;
}
@@ -481,7 +481,7 @@ static int bcm2835gpio_init(void)
MAP_SHARED, dev_mem_fd, BCM2835_GPIO_BASE);
if (pio_base == MAP_FAILED) {
- perror("mmap");
+ LOG_ERROR("mmap: %s", strerror(errno));
close(dev_mem_fd);
return ERROR_JTAG_INIT_FAILED;
}
@@ -491,7 +491,7 @@ static int bcm2835gpio_init(void)
MAP_SHARED, dev_mem_fd, BCM2835_PADS_GPIO_0_27);
if (pads_base == MAP_FAILED) {
- perror("mmap");
+ LOG_ERROR("mmap: %s", strerror(errno));
close(dev_mem_fd);
return ERROR_JTAG_INIT_FAILED;
}
diff --git a/src/jtag/drivers/ep93xx.c b/src/jtag/drivers/ep93xx.c
index 5e0e62afa..94d65505f 100644
--- a/src/jtag/drivers/ep93xx.c
+++ b/src/jtag/drivers/ep93xx.c
@@ -127,7 +127,7 @@ static int set_gonk_mode(void)
syscon = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
MAP_SHARED, dev_mem_fd, 0x80930000);
if (syscon == MAP_FAILED) {
- perror("mmap");
+ LOG_ERROR("mmap: %s", strerror(errno));
return ERROR_JTAG_INIT_FAILED;
}
@@ -151,14 +151,14 @@ static int ep93xx_init(void)
dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
if (dev_mem_fd < 0) {
- perror("open");
+ LOG_ERROR("open: %s", strerror(errno));
return ERROR_JTAG_INIT_FAILED;
}
gpio_controller = mmap(NULL, 4096, PROT_READ | PROT_WRITE,
MAP_SHARED, dev_mem_fd, 0x80840000);
if (gpio_controller == MAP_FAILED) {
- perror("mmap");
+ LOG_ERROR("mmap: %s", strerror(errno));
close(dev_mem_fd);
return ERROR_JTAG_INIT_FAILED;
}
diff --git a/src/jtag/drivers/imx_gpio.c b/src/jtag/drivers/imx_gpio.c
index c80e84218..39b463d31 100644
--- a/src/jtag/drivers/imx_gpio.c
+++ b/src/jtag/drivers/imx_gpio.c
@@ -491,7 +491,7 @@ static int imx_gpio_init(void)
dev_mem_fd = open("/dev/mem", O_RDWR | O_SYNC);
if (dev_mem_fd < 0) {
- perror("open");
+ LOG_ERROR("open: %s", strerror(errno));
return ERROR_JTAG_INIT_FAILED;
}
@@ -502,7 +502,7 @@ static int imx_gpio_init(void)
MAP_SHARED, dev_mem_fd, imx_gpio_peri_base);
if (pio_base == MAP_FAILED) {
- perror("mmap");
+ LOG_ERROR("mmap: %s", strerror(errno));
close(dev_mem_fd);
return ERROR_JTAG_INIT_FAILED;
}
diff --git a/src/jtag/drivers/sysfsgpio.c b/src/jtag/drivers/sysfsgpio.c
index d9fd7756a..e16076942 100644
--- a/src/jtag/drivers/sysfsgpio.c
+++ b/src/jtag/drivers/sysfsgpio.c
@@ -127,7 +127,7 @@ static int setup_sysfs_gpio(int gpio, int is_output, int init_high)
LOG_WARNING("gpio %d is already exported", gpio);
} else {
LOG_ERROR("Couldn't export gpio %d", gpio);
- perror("sysfsgpio: ");
+ LOG_ERROR("sysfsgpio: %s", strerror(errno));
return ERROR_FAIL;
}
}
@@ -147,7 +147,7 @@ static int setup_sysfs_gpio(int gpio, int is_output, int init_high)
}
if (ret < 0) {
LOG_ERROR("Couldn't set direction for gpio %d", gpio);
- perror("sysfsgpio: ");
+ LOG_ERROR("sysfsgpio: %s", strerror(errno));
unexport_sysfs_gpio(gpio);
return ERROR_FAIL;
}
@@ -164,7 +164,7 @@ static int setup_sysfs_gpio(int gpio, int is_output, int init_high)
}
if (ret < 0) {
LOG_ERROR("Couldn't open value for gpio %d", gpio);
- perror("sysfsgpio: ");
+ LOG_ERROR("sysfsgpio: %s", strerror(errno));
unexport_sysfs_gpio(gpio);
}
@@ -208,7 +208,7 @@ static void sysfsgpio_swdio_drive(bool is_output)
ret = open_write_close(buf, is_output ? "high" : "in");
if (ret < 0) {
LOG_ERROR("Couldn't set direction for gpio %d", swdio_gpio);
- perror("sysfsgpio: ");
+ LOG_ERROR("sysfsgpio: %s", strerror(errno));
}
last_stored = false;
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/at91rm9200.c | 4 ++--
src/jtag/drivers/bcm2835gpio.c | 6 +++---
src/jtag/drivers/cmsis_dap_usb.c | 26 ++++++++++++--------------
src/jtag/drivers/ep93xx.c | 6 +++---
src/jtag/drivers/imx_gpio.c | 4 ++--
src/jtag/drivers/sysfsgpio.c | 8 ++++----
6 files changed, 26 insertions(+), 28 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-07-13 23:40:08
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 3a5f84f8187ce5b473f0eaafa0d68d1ab23ec0cd (commit)
from 6962da00287c88c3fa89df8a8623a956735379db (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 3a5f84f8187ce5b473f0eaafa0d68d1ab23ec0cd
Author: Antonio Borneo <bor...@gm...>
Date: Sat Jul 4 19:38:00 2020 +0200
doc: remove duplicated words
Remove occurrences of duplicated words in the documentation.
Change-Id: Ib6ef1607fc5e6387764be108b2b9c0c93ac10a62
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5754
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/README b/README
index 2ff0329ed..fe70e725f 100644
--- a/README
+++ b/README
@@ -288,7 +288,7 @@ Parallel Port Dongles
---------------------
If you want to access the parallel port using the PPDEV interface you
-have to specify both --enable-parport AND --enable-parport-ppdev, since the
+have to specify both --enable-parport AND --enable-parport-ppdev, since
the later option is an option to the parport driver.
The same is true for the --enable-parport-giveio option, you have to
diff --git a/doc/manual/release.txt b/doc/manual/release.txt
index 44de4464f..d1a6c6250 100644
--- a/doc/manual/release.txt
+++ b/doc/manual/release.txt
@@ -82,7 +82,7 @@ number will be zero (<code>z = 0</code>). For a <i>major releases</i>,
the minor version will @a also be zero (<code>y = 0, z = 0</code>).
After these required numeric components, release version strings
-may contain tags such as as <em>-rc1</em> or <em>-rc2</em>.
+may contain tags such as <em>-rc1</em> or <em>-rc2</em>.
These 'rc' tags indicate "release candidate" versions of the package.
Like major/minor/micro numbers, these are updated
as part of the release process.
diff --git a/doc/manual/server.txt b/doc/manual/server.txt
index 50fcac75e..8041c3df3 100644
--- a/doc/manual/server.txt
+++ b/doc/manual/server.txt
@@ -23,7 +23,7 @@ In early 2008, Oyvind Harboe and Duane Ellis had talked about how to
create a reasonable GUI for OpenOCD - something that is non-invasive,
simple to use and maintain, and does not tie OpenOCD to many other
packages. It would be wrong to "spider web" requirements into other
-external external packages. That makes it difficult for developers to
+external packages. That makes it difficult for developers to
write new code and creates a support nightmare.
In many ways, people had talked about the need for some type of
@@ -67,7 +67,7 @@ write scripts internally to help things, or we can write "C" code that
interfaces well with TCL.
From there, the developers wanted to create an external front-end that
-would be @a very usable and that that @a any language could utilize,
+would be @a very usable and that @a any language could utilize,
allowing simple front-ends to be (a) cross-platform (b) language
agnostic, and (c) easy to develop and use.
diff --git a/doc/manual/style.txt b/doc/manual/style.txt
index e654be9c3..7191a4b0e 100644
--- a/doc/manual/style.txt
+++ b/doc/manual/style.txt
@@ -52,7 +52,7 @@ OpenOCD project.
-# remove it entirely (git can retrieve the old version), or
-# use an @c \#if/\#endif block.
-Finally, try to avoid lines of code that are longer than than 72-80 columns:
+Finally, try to avoid lines of code that are longer than 72-80 columns:
- long lines frequently indicate other style problems:
- insufficient use of static functions, macros, or temporary variables
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 9f20e391d..6b461a30e 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1020,7 +1020,7 @@ will help support users of any board using that chip.
@end quotation
@item
-You may may need to write some C code.
+You may need to write some C code.
It may be as simple as supporting a new FT2232 or parport
based adapter; a bit more involved, like a NAND or NOR flash
controller driver; or a big piece of work like supporting
@@ -5661,7 +5661,7 @@ at91samd bootloader 16384
@deffn Command {at91samd dsu_reset_deassert}
This command releases internal reset held by DSU
and prepares reset vector catch in case of reset halt.
-Command is used internally in event event reset-deassert-post.
+Command is used internally in event reset-deassert-post.
@end deffn
@deffn Command {at91samd nvmuserrow}
@@ -5768,7 +5768,7 @@ The AT91SAM4L driver adds some additional commands:
@deffn Command {at91sam4l smap_reset_deassert}
This command releases internal reset held by SMAP
and prepares reset vector catch in case of reset halt.
-Command is used internally in event event reset-deassert-post.
+Command is used internally in event reset-deassert-post.
@end deffn
@end deffn
@@ -5809,7 +5809,7 @@ processor to be halted.
@deffn Command {atsame5 dsu_reset_deassert}
This command releases internal reset held by DSU
and prepares reset vector catch in case of reset halt.
-Command is used internally in event event reset-deassert-post.
+Command is used internally in event reset-deassert-post.
@end deffn
@deffn Command {atsame5 userpage}
@@ -8392,7 +8392,7 @@ and any buffered trace data is invalidated.
@itemize
@item @var{type} ... describing how data accesses are traced,
-when they pass any ViewData filtering that that was set up.
+when they pass any ViewData filtering that was set up.
The value is one of
@option{none} (save nothing),
@option{data} (save data),
@@ -8740,7 +8740,7 @@ and any other core-specific commands that may be available.
@deffn Command {arm7_9 dbgrq} [@option{enable}|@option{disable}]
Displays the value of the flag controlling use of the
-the EmbeddedIce DBGRQ signal to force entry into debug mode,
+EmbeddedIce DBGRQ signal to force entry into debug mode,
instead of breakpoints.
If a boolean parameter is provided, first assigns that flag.
-----------------------------------------------------------------------
Summary of changes:
README | 2 +-
doc/manual/release.txt | 2 +-
doc/manual/server.txt | 4 ++--
doc/manual/style.txt | 2 +-
doc/openocd.texi | 12 ++++++------
5 files changed, 11 insertions(+), 11 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-07-13 23:39:37
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 6962da00287c88c3fa89df8a8623a956735379db (commit)
via aa277fb358b7ff02b8231d4141c673722c580cf3 (commit)
via 93be480c908d4751936ed779be1f00998c668c87 (commit)
via ee86f3ef92adfe1f41ad67b4b154ee7ea0327cc8 (commit)
via a8e483a2bf9d1b4eb16b7a0e0851b455a935fcf0 (commit)
from ed17994757661ed7a32cd9ad59aa001e5cd22692 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 6962da00287c88c3fa89df8a8623a956735379db
Author: Antonio Borneo <bor...@gm...>
Date: Thu Apr 2 00:14:21 2020 +0200
tcl/interface: add example of linuxgpiod through dln-2
The USB adapter DLN-2 provides 32 GPIO (beside I2C, SPI, ...).
Use the first 6 GPIO for a SWD/JTAG bitbanging example through
linuxgpiod driver.
Change-Id: I229c2078142ec648fc6430b5d123539045dcfbda
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5561
Tested-by: jenkins
diff --git a/tcl/interface/dln-2-gpiod.cfg b/tcl/interface/dln-2-gpiod.cfg
new file mode 100644
index 000000000..1859688be
--- /dev/null
+++ b/tcl/interface/dln-2-gpiod.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Use DLN-2 GPIO through linuxgpiod
+#
+# +-----------+-------------+-------------+
+# | signal | DLN-2 | gpio offset |
+# +-----------+-------------+-------------+
+# | nSRST | J3.1 (PA0) | 0 |
+# | TDO | J3.2 (PA1) | 1 |
+# | TCK/SWCLK | J3.3 (PA2) | 2 |
+# | TMS/SWDIO | J3.4 (PA3) | 3 |
+# | TDI | J3.5 (PA4) | 4 |
+# | nTRST | J3.6 (PA5) | 5 |
+# | GND | J3.12 (GND) | |
+# +-----------+-------------+-------------+
+
+adapter driver linuxgpiod
+
+linuxgpiod_gpiochip 0
+linuxgpiod_jtag_nums 2 3 4 1
+linuxgpiod_trst_num 5
+linuxgpiod_swd_nums 2 3
+linuxgpiod_srst_num 0
+
+reset_config trst_and_srst separate srst_push_pull
commit aa277fb358b7ff02b8231d4141c673722c580cf3
Author: Antonio Borneo <bor...@gm...>
Date: Mon Mar 30 21:54:17 2020 +0200
contrib/60-openocd.rules: add udev rules for Linux gpiod
Change-Id: I767776d3659adddefe81a63f351794318463fd50
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5560
Tested-by: jenkins
diff --git a/contrib/60-openocd.rules b/contrib/60-openocd.rules
index 617346d1c..74fc84da6 100644
--- a/contrib/60-openocd.rules
+++ b/contrib/60-openocd.rules
@@ -3,6 +3,9 @@
# with the command "udevadm control --reload"
ACTION!="add|change", GOTO="openocd_rules_end"
+
+SUBSYSTEM=="gpio", MODE="0660", GROUP="plugdev", TAG+="uaccess"
+
SUBSYSTEM!="usb|tty|hidraw", GOTO="openocd_rules_end"
# Please keep this list sorted by VID:PID
commit 93be480c908d4751936ed779be1f00998c668c87
Author: Antonio Borneo <bor...@gm...>
Date: Sun Mar 29 16:08:50 2020 +0200
jtag/drivers: add linuxgpiod driver
New adapter driver for GPIO bitbanging over Linux GPIO descriptors
through the library libgpiod.
On Debian based distribution, the package libgpiod-dev is required
for build.
Change-Id: I1ce1a4f1ca79096d6d476b01b523c8c10f2cac07
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5559
Tested-by: jenkins
diff --git a/configure.ac b/configure.ac
index 382a00b6e..4d8c91635 100644
--- a/configure.ac
+++ b/configure.ac
@@ -137,6 +137,9 @@ m4_define([LIBFTDI_ADAPTERS],
[[presto], [ASIX Presto Adapter], [PRESTO]],
[[openjtag], [OpenJTAG Adapter], [OPENJTAG]]])
+m4_define([LIBGPIOD_ADAPTERS],
+ [[[linuxgpiod], [Linux GPIO bitbang through libgpiod], [LINUXGPIOD]]])
+
m4_define([LIBJAYLINK_ADAPTERS],
[[[jlink], [SEGGER J-Link Programmer], [JLINK]]])
@@ -241,6 +244,7 @@ AC_ARG_ADAPTERS([
HIDAPI_ADAPTERS,
HIDAPI_USB1_ADAPTERS,
LIBFTDI_ADAPTERS,
+ LIBGPIOD_ADAPTERS,
LIBJAYLINK_ADAPTERS
],[auto])
@@ -335,6 +339,10 @@ AS_CASE([$host_os],
AC_MSG_ERROR([sysfsgpio is only available on linux])
])
+ AS_IF([test "x$enable_linuxgpiod" = "xyes"], [
+ AC_MSG_ERROR([linuxgpiod is only available on linux])
+ ])
+
AS_IF([test "x$build_xlnx_pcie_xvc" = "xyes"], [
AC_MSG_ERROR([xlnx_pcie_xvc is only available on linux])
])
@@ -643,6 +651,8 @@ PKG_CHECK_MODULES([LIBFTDI], [libftdi1], [use_libftdi=yes], [
PKG_CHECK_MODULES([LIBFTDI], [libftdi], [use_libftdi=yes], [use_libftdi=no])
])
+PKG_CHECK_MODULES([LIBGPIOD], [libgpiod], [use_libgpiod=yes], [use_libgpiod=no])
+
PKG_CHECK_MODULES([LIBJAYLINK], [libjaylink >= 0.2],
[use_libjaylink=yes], [use_libjaylink=no])
@@ -672,6 +682,7 @@ PROCESS_ADAPTERS([USB0_ADAPTERS], ["x$use_libusb0" = "xyes"], [libusb-0.1])
PROCESS_ADAPTERS([HIDAPI_ADAPTERS], ["x$use_hidapi" = "xyes"], [hidapi])
PROCESS_ADAPTERS([HIDAPI_USB1_ADAPTERS], ["x$use_hidapi" = "xyes" -a "x$use_libusb1" = "xyes"], [hidapi and libusb-1.x])
PROCESS_ADAPTERS([LIBFTDI_ADAPTERS], ["x$use_libftdi" = "xyes"], [libftdi])
+PROCESS_ADAPTERS([LIBGPIOD_ADAPTERS], ["x$use_libgpiod" = "xyes"], [libgpiod])
PROCESS_ADAPTERS([LIBJAYLINK_ADAPTERS], ["x$use_internal_libjaylink" = "xyes" -o "x$use_libjaylink" = "xyes"], [libjaylink-0.2])
AS_IF([test "x$build_openjtag" = "xyes"], [
@@ -681,6 +692,10 @@ AS_IF([test "x$build_openjtag" = "xyes"], [
])
])
+AS_IF([test "x$enable_linuxgpiod" != "xno"], [
+ build_bitbang=yes
+])
+
AS_IF([test "x$enable_stlink" != "xno" -o "x$enable_ti_icdi" != "xno"], [
AC_DEFINE([BUILD_HLADAPTER], [1], [1 if you want the High Level JTAG driver.])
AM_CONDITIONAL([HLADAPTER], [true])
@@ -736,6 +751,7 @@ AM_CONDITIONAL([IS_WIN32], [test "x$is_win32" = "xyes"])
AM_CONDITIONAL([IS_DARWIN], [test "x$is_darwin" = "xyes"])
AM_CONDITIONAL([BITQ], [test "x$build_bitq" = "xyes"])
AM_CONDITIONAL([USE_LIBFTDI], [test "x$use_libftdi" = "xyes"])
+AM_CONDITIONAL([USE_LIBGPIOD], [test "x$use_libgpiod" = "xyes"])
AM_CONDITIONAL([USE_HIDAPI], [test "x$use_hidapi" = "xyes"])
AM_CONDITIONAL([USE_LIBJAYLINK], [test "x$use_libjaylink" = "xyes"])
AM_CONDITIONAL([RSHIM], [test "x$build_rshim" = "xyes"])
@@ -807,6 +823,7 @@ echo OpenOCD configuration summary
echo --------------------------------------------------
m4_foreach([adapter], [USB1_ADAPTERS, USB0_ADAPTERS,
HIDAPI_ADAPTERS, HIDAPI_USB1_ADAPTERS, LIBFTDI_ADAPTERS,
+ LIBGPIOD_ADAPTERS,
LIBJAYLINK_ADAPTERS, PCIE_ADAPTERS],
[s=m4_format(["%-40s"], ADAPTER_DESC([adapter]))
AS_CASE([$ADAPTER_VAR([adapter])],
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index b03f560b3..77d6fb2af 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -38,6 +38,11 @@ if USE_LIBFTDI
%C%_libocdjtagdrivers_la_LIBADD += $(LIBFTDI_LIBS)
endif
+if USE_LIBGPIOD
+%C%_libocdjtagdrivers_la_CPPFLAGS += $(LIBGPIOD_CFLAGS)
+%C%_libocdjtagdrivers_la_LIBADD += $(LIBGPIOD_LIBS)
+endif
+
if USE_HIDAPI
%C%_libocdjtagdrivers_la_CPPFLAGS += $(HIDAPI_CFLAGS)
%C%_libocdjtagdrivers_la_LIBADD += $(HIDAPI_LIBS)
@@ -71,6 +76,9 @@ endif
if FTDI
DRIVERFILES += %D%/ftdi.c %D%/mpsse.c
endif
+if LINUXGPIOD
+DRIVERFILES += %D%/linuxgpiod.c
+endif
if JTAG_VPI
DRIVERFILES += %D%/jtag_vpi.c
endif
diff --git a/src/jtag/drivers/linuxgpiod.c b/src/jtag/drivers/linuxgpiod.c
new file mode 100644
index 000000000..661a926f5
--- /dev/null
+++ b/src/jtag/drivers/linuxgpiod.c
@@ -0,0 +1,595 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Bitbang driver for Linux GPIO descriptors through libgpiod
+ * Copyright (C) 2020 Antonio Borneo <bor...@gm...>
+ *
+ * Largely based on sysfsgpio driver
+ * Copyright (C) 2012 by Creative Product Design, marc @ cpdesign.com.au
+ * Copyright (C) 2014 by Jean-Christian de Rivaz <jc...@ec...>
+ * Copyright (C) 2014 by Paul Fertser <fer...@gm...>
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <gpiod.h>
+#include <jtag/interface.h>
+#include <transport/transport.h>
+#include "bitbang.h"
+
+/* gpio numbers for each gpio. Negative values are invalid */
+static int tck_gpio = -1;
+static int tms_gpio = -1;
+static int tdi_gpio = -1;
+static int tdo_gpio = -1;
+static int trst_gpio = -1;
+static int srst_gpio = -1;
+static int swclk_gpio = -1;
+static int swdio_gpio = -1;
+static int gpiochip = -1;
+
+static struct gpiod_chip *gpiod_chip;
+static struct gpiod_line *gpiod_tck;
+static struct gpiod_line *gpiod_tms;
+static struct gpiod_line *gpiod_tdi;
+static struct gpiod_line *gpiod_tdo;
+static struct gpiod_line *gpiod_trst;
+static struct gpiod_line *gpiod_swclk;
+static struct gpiod_line *gpiod_swdio;
+static struct gpiod_line *gpiod_srst;
+
+static int last_swclk;
+static int last_swdio;
+static bool last_stored;
+static bool swdio_input;
+
+/* Bitbang interface read of TDO */
+static bb_value_t linuxgpiod_read(void)
+{
+ int retval;
+
+ retval = gpiod_line_get_value(gpiod_tdo);
+ if (retval < 0) {
+ LOG_WARNING("reading tdo failed");
+ return 0;
+ }
+
+ return retval ? BB_HIGH : BB_LOW;
+}
+
+/*
+ * Bitbang interface write of TCK, TMS, TDI
+ *
+ * Seeing as this is the only function where the outputs are changed,
+ * we can cache the old value to avoid needlessly writing it.
+ */
+static int linuxgpiod_write(int tck, int tms, int tdi)
+{
+ static int last_tck;
+ static int last_tms;
+ static int last_tdi;
+
+ static int first_time;
+
+ int retval;
+
+ if (!first_time) {
+ last_tck = !tck;
+ last_tms = !tms;
+ last_tdi = !tdi;
+ first_time = 1;
+ }
+
+ if (tdi != last_tdi) {
+ retval = gpiod_line_set_value(gpiod_tdi, tdi);
+ if (retval < 0)
+ LOG_WARNING("writing tdi failed");
+ }
+
+ if (tms != last_tms) {
+ retval = gpiod_line_set_value(gpiod_tms, tms);
+ if (retval < 0)
+ LOG_WARNING("writing tms failed");
+ }
+
+ /* write clk last */
+ if (tck != last_tck) {
+ retval = gpiod_line_set_value(gpiod_tck, tck);
+ if (retval < 0)
+ LOG_WARNING("writing tck failed");
+ }
+
+ last_tdi = tdi;
+ last_tms = tms;
+ last_tck = tck;
+
+ return ERROR_OK;
+}
+
+static int linuxgpiod_swdio_read(void)
+{
+ int retval;
+
+ retval = gpiod_line_get_value(gpiod_swdio);
+ if (retval < 0) {
+ LOG_WARNING("Fail read swdio");
+ return 0;
+ }
+
+ return retval;
+}
+
+static void linuxgpiod_swdio_drive(bool is_output)
+{
+ int retval;
+
+ /*
+ * FIXME: change direction requires release and re-require the line
+ * https://stackoverflow.com/questions/58735140/
+ * this would change in future libgpiod
+ */
+ gpiod_line_release(gpiod_swdio);
+
+ if (is_output) {
+ retval = gpiod_line_request_output(gpiod_swdio, "OpenOCD", 1);
+ if (retval < 0)
+ LOG_WARNING("Fail request_output line swdio");
+ } else {
+ retval = gpiod_line_request_input(gpiod_swdio, "OpenOCD");
+ if (retval < 0)
+ LOG_WARNING("Fail request_input line swdio");
+ }
+
+ last_stored = false;
+ swdio_input = !is_output;
+}
+
+static int linuxgpiod_swd_write(int swclk, int swdio)
+{
+ int retval;
+
+ if (!swdio_input) {
+ if (!last_stored || (swdio != last_swdio)) {
+ retval = gpiod_line_set_value(gpiod_swdio, swdio);
+ if (retval < 0)
+ LOG_WARNING("Fail set swdio");
+ }
+ }
+
+ /* write swclk last */
+ if (!last_stored || (swclk != last_swclk)) {
+ retval = gpiod_line_set_value(gpiod_swclk, swclk);
+ if (retval < 0)
+ LOG_WARNING("Fail set swclk");
+ }
+
+ last_swdio = swdio;
+ last_swclk = swclk;
+ last_stored = true;
+
+ return ERROR_OK;
+}
+
+static struct bitbang_interface linuxgpiod_bitbang = {
+ .read = linuxgpiod_read,
+ .write = linuxgpiod_write,
+ .swdio_read = linuxgpiod_swdio_read,
+ .swdio_drive = linuxgpiod_swdio_drive,
+ .swd_write = linuxgpiod_swd_write,
+ .blink = NULL,
+};
+
+/*
+ * Bitbang interface to manipulate reset lines SRST and TRST
+ *
+ * (1) assert or (0) deassert reset lines
+ */
+static int linuxgpiod_reset(int trst, int srst)
+{
+ int retval1 = 0, retval2 = 0;
+
+ LOG_DEBUG("linuxgpiod_reset");
+
+ /* assume active low */
+ if (gpiod_srst != NULL) {
+ retval1 = gpiod_line_set_value(gpiod_srst, srst ? 0 : 1);
+ if (retval1 < 0)
+ LOG_WARNING("set srst value failed");
+ }
+
+ /* assume active low */
+ if (gpiod_trst != NULL) {
+ retval2 = gpiod_line_set_value(gpiod_trst, trst ? 0 : 1);
+ if (retval2 < 0)
+ LOG_WARNING("set trst value failed");
+ }
+
+ return ((retval1 < 0) || (retval2 < 0)) ? ERROR_FAIL : ERROR_OK;
+}
+
+/*
+ * Helper function to determine if gpio number is valid
+ *
+ * Assume here that there will be less than 10000 gpios per gpiochip
+ */
+static bool is_gpio_valid(int gpio)
+{
+ return gpio >= 0 && gpio < 10000;
+}
+
+static bool linuxgpiod_jtag_mode_possible(void)
+{
+ if (!is_gpio_valid(tck_gpio))
+ return false;
+ if (!is_gpio_valid(tms_gpio))
+ return false;
+ if (!is_gpio_valid(tdi_gpio))
+ return false;
+ if (!is_gpio_valid(tdo_gpio))
+ return false;
+ return true;
+}
+
+static bool linuxgpiod_swd_mode_possible(void)
+{
+ if (!is_gpio_valid(swclk_gpio))
+ return false;
+ if (!is_gpio_valid(swdio_gpio))
+ return false;
+ return true;
+}
+
+static inline void helper_release(struct gpiod_line *line)
+{
+ if (line)
+ gpiod_line_release(line);
+}
+
+static int linuxgpiod_quit(void)
+{
+ helper_release(gpiod_srst);
+ helper_release(gpiod_swdio);
+ helper_release(gpiod_swclk);
+ helper_release(gpiod_trst);
+ helper_release(gpiod_tms);
+ helper_release(gpiod_tck);
+ helper_release(gpiod_tdi);
+ helper_release(gpiod_tdo);
+
+ gpiod_chip_close(gpiod_chip);
+
+ return ERROR_OK;
+}
+
+static struct gpiod_line *helper_get_input_line(const char *label, unsigned int offset)
+{
+ struct gpiod_line *line;
+ int retval;
+
+ line = gpiod_chip_get_line(gpiod_chip, offset);
+ if (line == NULL) {
+ LOG_ERROR("Error get line %s", label);
+ return NULL;
+ }
+
+ retval = gpiod_line_request_input(line, "OpenOCD");
+ if (retval < 0) {
+ LOG_ERROR("Error request_input line %s", label);
+ return NULL;
+ }
+
+ return line;
+}
+
+static struct gpiod_line *helper_get_output_line(const char *label, unsigned int offset, int val)
+{
+ struct gpiod_line *line;
+ int retval;
+
+ line = gpiod_chip_get_line(gpiod_chip, offset);
+ if (line == NULL) {
+ LOG_ERROR("Error get line %s", label);
+ return NULL;
+ }
+
+ retval = gpiod_line_request_output(line, "OpenOCD", val);
+ if (retval < 0) {
+ LOG_ERROR("Error request_output line %s", label);
+ return NULL;
+ }
+
+ return line;
+}
+
+static int linuxgpiod_init(void)
+{
+ LOG_INFO("Linux GPIOD JTAG/SWD bitbang driver");
+
+ bitbang_interface = &linuxgpiod_bitbang;
+
+ gpiod_chip = gpiod_chip_open_by_number(gpiochip);
+ if (gpiod_chip == NULL) {
+ LOG_ERROR("Cannot open LinuxGPIOD gpiochip %d", gpiochip);
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ /*
+ * Configure TDO as an input, and TDI, TCK, TMS, TRST, SRST
+ * as outputs. Drive TDI and TCK low, and TMS/TRST/SRST high.
+ * For SWD, SWCLK and SWDIO are configures as output high.
+ */
+
+ if (transport_is_jtag()) {
+ if (!linuxgpiod_jtag_mode_possible()) {
+ LOG_ERROR("Require tck, tms, tdi and tdo gpios for JTAG mode");
+ goto out_error;
+ }
+
+ gpiod_tdo = helper_get_input_line("tdo", tdo_gpio);
+ if (gpiod_tdo == NULL)
+ goto out_error;
+
+ gpiod_tdi = helper_get_output_line("tdi", tdi_gpio, 0);
+ if (gpiod_tdi == NULL)
+ goto out_error;
+
+ gpiod_tck = helper_get_output_line("tck", tck_gpio, 0);
+ if (gpiod_tck == NULL)
+ goto out_error;
+
+ gpiod_tms = helper_get_output_line("tms", tms_gpio, 1);
+ if (gpiod_tms == NULL)
+ goto out_error;
+
+ if (is_gpio_valid(trst_gpio)) {
+ gpiod_trst = helper_get_output_line("trst", trst_gpio, 1);
+ if (gpiod_trst == NULL)
+ goto out_error;
+ }
+ }
+
+ if (transport_is_swd()) {
+ if (!linuxgpiod_swd_mode_possible()) {
+ LOG_ERROR("Require swclk and swdio gpio for SWD mode");
+ goto out_error;
+ }
+
+ gpiod_swclk = helper_get_output_line("swclk", swclk_gpio, 1);
+ if (gpiod_swclk == NULL)
+ goto out_error;
+
+ gpiod_swdio = helper_get_output_line("swdio", swdio_gpio, 1);
+ if (gpiod_swdio == NULL)
+ goto out_error;
+ }
+
+ if (is_gpio_valid(srst_gpio)) {
+ gpiod_srst = helper_get_output_line("srst", srst_gpio, 1);
+ if (gpiod_srst == NULL)
+ goto out_error;
+ }
+
+ return ERROR_OK;
+
+out_error:
+ linuxgpiod_quit();
+
+ return ERROR_JTAG_INIT_FAILED;
+}
+
+COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionums)
+{
+ if (CMD_ARGC == 4) {
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio);
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], tms_gpio);
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[2], tdi_gpio);
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], tdo_gpio);
+ } else if (CMD_ARGC != 0) {
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ command_print(CMD,
+ "LinuxGPIOD nums: tck = %d, tms = %d, tdi = %d, tdo = %d",
+ tck_gpio, tms_gpio, tdi_gpio, tdo_gpio);
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_tck)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tck_gpio);
+
+ command_print(CMD, "LinuxGPIOD num: tck = %d", tck_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_tms)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tms_gpio);
+
+ command_print(CMD, "LinuxGPIOD num: tms = %d", tms_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_tdo)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tdo_gpio);
+
+ command_print(CMD, "LinuxGPIOD num: tdo = %d", tdo_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_tdi)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], tdi_gpio);
+
+ command_print(CMD, "LinuxGPIOD num: tdi = %d", tdi_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_srst)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], srst_gpio);
+
+ command_print(CMD, "LinuxGPIOD num: srst = %d", srst_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(linuxgpiod_handle_jtag_gpionum_trst)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], trst_gpio);
+
+ command_print(CMD, "LinuxGPIOD num: trst = %d", trst_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(linuxgpiod_handle_swd_gpionums)
+{
+ if (CMD_ARGC == 2) {
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swclk_gpio);
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], swdio_gpio);
+ } else if (CMD_ARGC != 0) {
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ command_print(CMD,
+ "LinuxGPIOD nums: swclk = %d, swdio = %d",
+ swclk_gpio, swdio_gpio);
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(linuxgpiod_handle_swd_gpionum_swclk)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swclk_gpio);
+
+ command_print(CMD, "LinuxGPIOD num: swclk = %d", swclk_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(linuxgpiod_handle_swd_gpionum_swdio)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], swdio_gpio);
+
+ command_print(CMD, "LinuxGPIOD num: swdio = %d", swdio_gpio);
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(linuxgpiod_handle_gpiochip)
+{
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], gpiochip);
+
+ command_print(CMD, "LinuxGPIOD gpiochip = %d", gpiochip);
+ return ERROR_OK;
+}
+
+static const struct command_registration linuxgpiod_command_handlers[] = {
+ {
+ .name = "linuxgpiod_jtag_nums",
+ .handler = linuxgpiod_handle_jtag_gpionums,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio numbers for tck, tms, tdi, tdo. (in that order)",
+ .usage = "tck tms tdi tdo",
+ },
+ {
+ .name = "linuxgpiod_tck_num",
+ .handler = linuxgpiod_handle_jtag_gpionum_tck,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for tck.",
+ .usage = "tck",
+ },
+ {
+ .name = "linuxgpiod_tms_num",
+ .handler = linuxgpiod_handle_jtag_gpionum_tms,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for tms.",
+ .usage = "tms",
+ },
+ {
+ .name = "linuxgpiod_tdo_num",
+ .handler = linuxgpiod_handle_jtag_gpionum_tdo,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for tdo.",
+ .usage = "tdo",
+ },
+ {
+ .name = "linuxgpiod_tdi_num",
+ .handler = linuxgpiod_handle_jtag_gpionum_tdi,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for tdi.",
+ .usage = "tdi",
+ },
+ {
+ .name = "linuxgpiod_srst_num",
+ .handler = linuxgpiod_handle_jtag_gpionum_srst,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for srst.",
+ .usage = "srst",
+ },
+ {
+ .name = "linuxgpiod_trst_num",
+ .handler = linuxgpiod_handle_jtag_gpionum_trst,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for trst.",
+ .usage = "trst",
+ },
+ {
+ .name = "linuxgpiod_swd_nums",
+ .handler = linuxgpiod_handle_swd_gpionums,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio numbers for swclk, swdio. (in that order)",
+ .usage = "swclk swdio",
+ },
+ {
+ .name = "linuxgpiod_swclk_num",
+ .handler = linuxgpiod_handle_swd_gpionum_swclk,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for swclk.",
+ .usage = "swclk",
+ },
+ {
+ .name = "linuxgpiod_swdio_num",
+ .handler = linuxgpiod_handle_swd_gpionum_swdio,
+ .mode = COMMAND_CONFIG,
+ .help = "gpio number for swdio.",
+ .usage = "swdio",
+ },
+ {
+ .name = "linuxgpiod_gpiochip",
+ .handler = linuxgpiod_handle_gpiochip,
+ .mode = COMMAND_CONFIG,
+ .help = "number of the gpiochip.",
+ .usage = "gpiochip",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static const char *const linuxgpiod_transport[] = { "swd", "jtag", NULL };
+
+static struct jtag_interface linuxgpiod_interface = {
+ .supported = DEBUG_CAP_TMS_SEQ,
+ .execute_queue = bitbang_execute_queue,
+};
+
+struct adapter_driver linuxgpiod_adapter_driver = {
+ .name = "linuxgpiod",
+ .transports = linuxgpiod_transport,
+ .commands = linuxgpiod_command_handlers,
+
+ .init = linuxgpiod_init,
+ .quit = linuxgpiod_quit,
+ .reset = linuxgpiod_reset,
+
+ .jtag_ops = &linuxgpiod_interface,
+ .swd_ops = &bitbang_swd,
+};
diff --git a/src/jtag/interfaces.c b/src/jtag/interfaces.c
index 87ea95822..45e30c9b0 100644
--- a/src/jtag/interfaces.c
+++ b/src/jtag/interfaces.c
@@ -117,6 +117,9 @@ extern struct adapter_driver opendous_adapter_driver;
#if BUILD_SYSFSGPIO == 1
extern struct adapter_driver sysfsgpio_adapter_driver;
#endif
+#if BUILD_LINUXGPIOD == 1
+extern struct adapter_driver linuxgpiod_adapter_driver;
+#endif
#if BUILD_XLNX_PCIE_XVC == 1
extern struct adapter_driver xlnx_pcie_xvc_adapter_driver;
#endif
@@ -231,6 +234,9 @@ struct adapter_driver *adapter_drivers[] = {
#if BUILD_SYSFSGPIO == 1
&sysfsgpio_adapter_driver,
#endif
+#if BUILD_LINUXGPIOD == 1
+ &linuxgpiod_adapter_driver,
+#endif
#if BUILD_XLNX_PCIE_XVC == 1
&xlnx_pcie_xvc_adapter_driver,
#endif
commit ee86f3ef92adfe1f41ad67b4b154ee7ea0327cc8
Author: Antonio Borneo <bor...@gm...>
Date: Wed Apr 1 12:03:47 2020 +0200
bcm2835gpio: enable only the transport specific gpio
Change-Id: Ice6744600079d5994d628bb3b782aa36e71f862e
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5558
Tested-by: jenkins
diff --git a/src/jtag/drivers/bcm2835gpio.c b/src/jtag/drivers/bcm2835gpio.c
index 77ae5668f..f868516d9 100644
--- a/src/jtag/drivers/bcm2835gpio.c
+++ b/src/jtag/drivers/bcm2835gpio.c
@@ -24,6 +24,7 @@
#endif
#include <jtag/interface.h>
+#include <transport/transport.h>
#include "bitbang.h"
#include <sys/mman.h>
@@ -456,15 +457,13 @@ static int bcm2835gpio_init(void)
LOG_INFO("BCM2835 GPIO JTAG/SWD bitbang driver");
- if (bcm2835gpio_jtag_mode_possible()) {
- if (bcm2835gpio_swd_mode_possible())
- LOG_INFO("JTAG and SWD modes enabled");
- else
- LOG_INFO("JTAG only mode enabled (specify swclk and swdio gpio to add SWD mode)");
- } else if (bcm2835gpio_swd_mode_possible()) {
- LOG_INFO("SWD only mode enabled (specify tck, tms, tdi and tdo gpios to add JTAG mode)");
- } else {
- LOG_ERROR("Require tck, tms, tdi and tdo gpios for JTAG mode and/or swclk and swdio gpio for SWD mode");
+ if (transport_is_jtag() && !bcm2835gpio_jtag_mode_possible()) {
+ LOG_ERROR("Require tck, tms, tdi and tdo gpios for JTAG mode");
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ if (transport_is_swd() && !bcm2835gpio_swd_mode_possible()) {
+ LOG_ERROR("Require swclk and swdio gpio for SWD mode");
return ERROR_JTAG_INIT_FAILED;
}
@@ -500,31 +499,42 @@ static int bcm2835gpio_init(void)
/* set 4mA drive strength, slew rate limited, hysteresis on */
pads_base[BCM2835_PADS_GPIO_0_27_OFFSET] = 0x5a000008 + 1;
- tdo_gpio_mode = MODE_GPIO(tdo_gpio);
- tdi_gpio_mode = MODE_GPIO(tdi_gpio);
- tck_gpio_mode = MODE_GPIO(tck_gpio);
- tms_gpio_mode = MODE_GPIO(tms_gpio);
- swclk_gpio_mode = MODE_GPIO(swclk_gpio);
- swdio_gpio_mode = MODE_GPIO(swdio_gpio);
/*
* Configure TDO as an input, and TDI, TCK, TMS, TRST, SRST
* as outputs. Drive TDI and TCK low, and TMS/TRST/SRST high.
*/
- INP_GPIO(tdo_gpio);
-
- GPIO_CLR = 1<<tdi_gpio | 1<<tck_gpio | 1<<swdio_gpio | 1<<swclk_gpio;
- GPIO_SET = 1<<tms_gpio;
-
- OUT_GPIO(tdi_gpio);
- OUT_GPIO(tck_gpio);
- OUT_GPIO(tms_gpio);
- OUT_GPIO(swclk_gpio);
- OUT_GPIO(swdio_gpio);
- if (trst_gpio != -1) {
- trst_gpio_mode = MODE_GPIO(trst_gpio);
- GPIO_SET = 1 << trst_gpio;
- OUT_GPIO(trst_gpio);
+ if (transport_is_jtag()) {
+ tdo_gpio_mode = MODE_GPIO(tdo_gpio);
+ tdi_gpio_mode = MODE_GPIO(tdi_gpio);
+ tck_gpio_mode = MODE_GPIO(tck_gpio);
+ tms_gpio_mode = MODE_GPIO(tms_gpio);
+
+ INP_GPIO(tdo_gpio);
+
+ GPIO_CLR = 1<<tdi_gpio | 1<<tck_gpio;
+ GPIO_SET = 1<<tms_gpio;
+
+ OUT_GPIO(tdi_gpio);
+ OUT_GPIO(tck_gpio);
+ OUT_GPIO(tms_gpio);
+
+ if (trst_gpio != -1) {
+ trst_gpio_mode = MODE_GPIO(trst_gpio);
+ GPIO_SET = 1 << trst_gpio;
+ OUT_GPIO(trst_gpio);
+ }
}
+
+ if (transport_is_swd()) {
+ swclk_gpio_mode = MODE_GPIO(swclk_gpio);
+ swdio_gpio_mode = MODE_GPIO(swdio_gpio);
+
+ GPIO_CLR = 1<<swdio_gpio | 1<<swclk_gpio;
+
+ OUT_GPIO(swclk_gpio);
+ OUT_GPIO(swdio_gpio);
+ }
+
if (srst_gpio != -1) {
srst_gpio_mode = MODE_GPIO(srst_gpio);
GPIO_SET = 1 << srst_gpio;
@@ -540,14 +550,20 @@ static int bcm2835gpio_init(void)
static int bcm2835gpio_quit(void)
{
- SET_MODE_GPIO(tdo_gpio, tdo_gpio_mode);
- SET_MODE_GPIO(tdi_gpio, tdi_gpio_mode);
- SET_MODE_GPIO(tck_gpio, tck_gpio_mode);
- SET_MODE_GPIO(tms_gpio, tms_gpio_mode);
- SET_MODE_GPIO(swclk_gpio, swclk_gpio_mode);
- SET_MODE_GPIO(swdio_gpio, swdio_gpio_mode);
- if (trst_gpio != -1)
- SET_MODE_GPIO(trst_gpio, trst_gpio_mode);
+ if (transport_is_jtag()) {
+ SET_MODE_GPIO(tdo_gpio, tdo_gpio_mode);
+ SET_MODE_GPIO(tdi_gpio, tdi_gpio_mode);
+ SET_MODE_GPIO(tck_gpio, tck_gpio_mode);
+ SET_MODE_GPIO(tms_gpio, tms_gpio_mode);
+ if (trst_gpio != -1)
+ SET_MODE_GPIO(trst_gpio, trst_gpio_mode);
+ }
+
+ if (transport_is_swd()) {
+ SET_MODE_GPIO(swclk_gpio, swclk_gpio_mode);
+ SET_MODE_GPIO(swdio_gpio, swdio_gpio_mode);
+ }
+
if (srst_gpio != -1)
SET_MODE_GPIO(srst_gpio, srst_gpio_mode);
commit a8e483a2bf9d1b4eb16b7a0e0851b455a935fcf0
Author: Antonio Borneo <bor...@gm...>
Date: Wed Apr 1 11:53:30 2020 +0200
imx_gpio: enable only the transport specific gpio
Change-Id: Idb1fabbc1e9385f8c23b643584bf7863ea91ffbf
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5557
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/jtag/drivers/imx_gpio.c b/src/jtag/drivers/imx_gpio.c
index b96b433f7..c80e84218 100644
--- a/src/jtag/drivers/imx_gpio.c
+++ b/src/jtag/drivers/imx_gpio.c
@@ -22,6 +22,7 @@
#endif
#include <jtag/interface.h>
+#include <transport/transport.h>
#include "bitbang.h"
#include <sys/mman.h>
@@ -478,15 +479,13 @@ static int imx_gpio_init(void)
LOG_INFO("imx_gpio GPIO JTAG/SWD bitbang driver");
- if (imx_gpio_jtag_mode_possible()) {
- if (imx_gpio_swd_mode_possible())
- LOG_INFO("JTAG and SWD modes enabled");
- else
- LOG_INFO("JTAG only mode enabled (specify swclk and swdio gpio to add SWD mode)");
- } else if (imx_gpio_swd_mode_possible()) {
- LOG_INFO("SWD only mode enabled (specify tck, tms, tdi and tdo gpios to add JTAG mode)");
- } else {
- LOG_ERROR("Require tck, tms, tdi and tdo gpios for JTAG mode and/or swclk and swdio gpio for SWD mode");
+ if (transport_is_jtag() && !imx_gpio_jtag_mode_possible()) {
+ LOG_ERROR("Require tck, tms, tdi and tdo gpios for JTAG mode");
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ if (transport_is_swd() && !imx_gpio_swd_mode_possible()) {
+ LOG_ERROR("Require swclk and swdio gpio for SWD mode");
return ERROR_JTAG_INIT_FAILED;
}
@@ -496,7 +495,6 @@ static int imx_gpio_init(void)
return ERROR_JTAG_INIT_FAILED;
}
-
LOG_INFO("imx_gpio mmap: pagesize: %u, regionsize: %u",
(unsigned int) sysconf(_SC_PAGE_SIZE), IMX_GPIO_REGS_COUNT * IMX_GPIO_SIZE);
pio_base = mmap(NULL, IMX_GPIO_REGS_COUNT * IMX_GPIO_SIZE,
@@ -513,7 +511,7 @@ static int imx_gpio_init(void)
* Configure TDO as an input, and TDI, TCK, TMS, TRST, SRST
* as outputs. Drive TDI and TCK low, and TMS/TRST/SRST high.
*/
- if (imx_gpio_jtag_mode_possible()) {
+ if (transport_is_jtag()) {
tdo_gpio_mode = gpio_mode_get(tdo_gpio);
tdi_gpio_mode = gpio_mode_get(tdi_gpio);
tck_gpio_mode = gpio_mode_get(tck_gpio);
@@ -527,8 +525,15 @@ static int imx_gpio_init(void)
gpio_mode_output_set(tdi_gpio);
gpio_mode_output_set(tck_gpio);
gpio_mode_output_set(tms_gpio);
+
+ if (trst_gpio != -1) {
+ trst_gpio_mode = gpio_mode_get(trst_gpio);
+ gpio_set(trst_gpio);
+ gpio_mode_output_set(trst_gpio);
+ }
}
- if (imx_gpio_swd_mode_possible()) {
+
+ if (transport_is_swd()) {
swclk_gpio_mode = gpio_mode_get(swclk_gpio);
swdio_gpio_mode = gpio_mode_get(swdio_gpio);
@@ -537,11 +542,7 @@ static int imx_gpio_init(void)
gpio_mode_output_set(swclk_gpio);
gpio_mode_output_set(swdio_gpio);
}
- if (trst_gpio != -1) {
- trst_gpio_mode = gpio_mode_get(trst_gpio);
- gpio_set(trst_gpio);
- gpio_mode_output_set(trst_gpio);
- }
+
if (srst_gpio != -1) {
srst_gpio_mode = gpio_mode_get(srst_gpio);
gpio_set(srst_gpio);
@@ -557,18 +558,21 @@ static int imx_gpio_init(void)
static int imx_gpio_quit(void)
{
- if (imx_gpio_jtag_mode_possible()) {
+ if (transport_is_jtag()) {
gpio_mode_set(tdo_gpio, tdo_gpio_mode);
gpio_mode_set(tdi_gpio, tdi_gpio_mode);
gpio_mode_set(tck_gpio, tck_gpio_mode);
gpio_mode_set(tms_gpio, tms_gpio_mode);
+
+ if (trst_gpio != -1)
+ gpio_mode_set(trst_gpio, trst_gpio_mode);
}
- if (imx_gpio_swd_mode_possible()) {
+
+ if (transport_is_swd()) {
gpio_mode_set(swclk_gpio, swclk_gpio_mode);
gpio_mode_set(swdio_gpio, swdio_gpio_mode);
}
- if (trst_gpio != -1)
- gpio_mode_set(trst_gpio, trst_gpio_mode);
+
if (srst_gpio != -1)
gpio_mode_set(srst_gpio, srst_gpio_mode);
-----------------------------------------------------------------------
Summary of changes:
configure.ac | 17 ++
contrib/60-openocd.rules | 3 +
src/jtag/drivers/Makefile.am | 8 +
src/jtag/drivers/bcm2835gpio.c | 90 ++++---
src/jtag/drivers/imx_gpio.c | 46 ++--
src/jtag/drivers/linuxgpiod.c | 595 +++++++++++++++++++++++++++++++++++++++++
src/jtag/interfaces.c | 6 +
tcl/interface/dln-2-gpiod.cfg | 25 ++
8 files changed, 732 insertions(+), 58 deletions(-)
create mode 100644 src/jtag/drivers/linuxgpiod.c
create mode 100644 tcl/interface/dln-2-gpiod.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-07-13 23:39:05
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via ed17994757661ed7a32cd9ad59aa001e5cd22692 (commit)
via 964680ecff5b252839f61f9328658339d9090bff (commit)
from 49232a80d2cb1a2e188a037cad94fd760ae64808 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit ed17994757661ed7a32cd9ad59aa001e5cd22692
Author: Antonio Borneo <bor...@gm...>
Date: Wed Apr 1 11:37:54 2020 +0200
sysfsgpio: enable only the transport specific gpio
If the configuration file specifies both SWD and JTAG gpios, the
current code request all of them. In case of overlap a warning is
generated when the same gpio is released for the second time.
Require and release only the gpio needed by the specified
transport.
Change-Id: I41a0970980ceeb559afa98ab34cfe93dffed2e1c
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5556
Tested-by: jenkins
diff --git a/src/jtag/drivers/sysfsgpio.c b/src/jtag/drivers/sysfsgpio.c
index a58962098..d9fd7756a 100644
--- a/src/jtag/drivers/sysfsgpio.c
+++ b/src/jtag/drivers/sysfsgpio.c
@@ -54,6 +54,7 @@
#include <helper/time_support.h>
#include <jtag/interface.h>
+#include <transport/transport.h>
#include "bitbang.h"
/*
@@ -586,14 +587,18 @@ static void cleanup_fd(int fd, int gpio)
static void cleanup_all_fds(void)
{
- cleanup_fd(tck_fd, tck_gpio);
- cleanup_fd(tms_fd, tms_gpio);
- cleanup_fd(tdi_fd, tdi_gpio);
- cleanup_fd(tdo_fd, tdo_gpio);
- cleanup_fd(trst_fd, trst_gpio);
+ if (transport_is_jtag()) {
+ cleanup_fd(tck_fd, tck_gpio);
+ cleanup_fd(tms_fd, tms_gpio);
+ cleanup_fd(tdi_fd, tdi_gpio);
+ cleanup_fd(tdo_fd, tdo_gpio);
+ cleanup_fd(trst_fd, trst_gpio);
+ }
+ if (transport_is_swd()) {
+ cleanup_fd(swclk_fd, swclk_gpio);
+ cleanup_fd(swdio_fd, swdio_gpio);
+ }
cleanup_fd(srst_fd, srst_gpio);
- cleanup_fd(swclk_fd, swclk_gpio);
- cleanup_fd(swdio_fd, swdio_gpio);
}
static bool sysfsgpio_jtag_mode_possible(void)
@@ -624,74 +629,64 @@ static int sysfsgpio_init(void)
LOG_INFO("SysfsGPIO JTAG/SWD bitbang driver");
- if (sysfsgpio_jtag_mode_possible()) {
- if (sysfsgpio_swd_mode_possible())
- LOG_INFO("JTAG and SWD modes enabled");
- else
- LOG_INFO("JTAG only mode enabled (specify swclk and swdio gpio to add SWD mode)");
- } else if (sysfsgpio_swd_mode_possible()) {
- LOG_INFO("SWD only mode enabled (specify tck, tms, tdi and tdo gpios to add JTAG mode)");
- } else {
- LOG_ERROR("Require tck, tms, tdi and tdo gpios for JTAG mode and/or swclk and swdio gpio for SWD mode");
- return ERROR_JTAG_INIT_FAILED;
- }
-
-
/*
* Configure TDO as an input, and TDI, TCK, TMS, TRST, SRST
* as outputs. Drive TDI and TCK low, and TMS/TRST/SRST high.
* For SWD, SWCLK and SWDIO are configures as output high.
*/
- if (tck_gpio >= 0) {
+
+ if (transport_is_jtag()) {
+ if (!sysfsgpio_jtag_mode_possible()) {
+ LOG_ERROR("Require tck, tms, tdi and tdo gpios for JTAG mode");
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
tck_fd = setup_sysfs_gpio(tck_gpio, 1, 0);
if (tck_fd < 0)
goto out_error;
- }
- if (tms_gpio >= 0) {
tms_fd = setup_sysfs_gpio(tms_gpio, 1, 1);
if (tms_fd < 0)
goto out_error;
- }
- if (tdi_gpio >= 0) {
tdi_fd = setup_sysfs_gpio(tdi_gpio, 1, 0);
if (tdi_fd < 0)
goto out_error;
- }
- if (tdo_gpio >= 0) {
tdo_fd = setup_sysfs_gpio(tdo_gpio, 0, 0);
if (tdo_fd < 0)
goto out_error;
- }
- /* assume active low*/
- if (trst_gpio >= 0) {
- trst_fd = setup_sysfs_gpio(trst_gpio, 1, 1);
- if (trst_fd < 0)
- goto out_error;
+ /* assume active low*/
+ if (trst_gpio >= 0) {
+ trst_fd = setup_sysfs_gpio(trst_gpio, 1, 1);
+ if (trst_fd < 0)
+ goto out_error;
+ }
}
- /* assume active low*/
- if (srst_gpio >= 0) {
- srst_fd = setup_sysfs_gpio(srst_gpio, 1, 1);
- if (srst_fd < 0)
- goto out_error;
- }
+ if (transport_is_swd()) {
+ if (!sysfsgpio_swd_mode_possible()) {
+ LOG_ERROR("Require swclk and swdio gpio for SWD mode");
+ return ERROR_JTAG_INIT_FAILED;
+ }
- if (swclk_gpio >= 0) {
swclk_fd = setup_sysfs_gpio(swclk_gpio, 1, 0);
if (swclk_fd < 0)
goto out_error;
- }
- if (swdio_gpio >= 0) {
swdio_fd = setup_sysfs_gpio(swdio_gpio, 1, 0);
if (swdio_fd < 0)
goto out_error;
}
+ /* assume active low*/
+ if (srst_gpio >= 0) {
+ srst_fd = setup_sysfs_gpio(srst_gpio, 1, 1);
+ if (srst_fd < 0)
+ goto out_error;
+ }
+
return ERROR_OK;
out_error:
commit 964680ecff5b252839f61f9328658339d9090bff
Author: Antonio Borneo <bor...@gm...>
Date: Wed Apr 1 11:00:39 2020 +0200
bitbang: split jtag and swd operations
The split in OpenOCD between SWD and JTAG has been already fully
implemented. The bitbang driver still keeps a single API write()
to drive the output lines.
Introduce a new SWD specific API swd_write().
Move the existing SWD bitbang drivers to the new API by extracting
the available conditional implementation.
Cleanup some function prototype.
Remove the now unused global swd_mode, handled implicitly.
Rename bitbang_exchange() as bitbang_swd_exchange() to track its
scope for SWD only.
Change-Id: Ie53080b941cb1ac7a34a1f80bad8bee4e304454d
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5555
Tested-by: jenkins
diff --git a/src/jtag/drivers/bcm2835gpio.c b/src/jtag/drivers/bcm2835gpio.c
index f547d93a4..77ae5668f 100644
--- a/src/jtag/drivers/bcm2835gpio.c
+++ b/src/jtag/drivers/bcm2835gpio.c
@@ -54,6 +54,7 @@ static int bcm2835gpio_write(int tck, int tms, int tdi);
static int bcm2835_swdio_read(void);
static void bcm2835_swdio_drive(bool is_output);
+static int bcm2835gpio_swd_write(int swclk, int swdio);
static int bcm2835gpio_init(void);
static int bcm2835gpio_quit(void);
@@ -63,6 +64,7 @@ static struct bitbang_interface bcm2835gpio_bitbang = {
.write = bcm2835gpio_write,
.swdio_read = bcm2835_swdio_read,
.swdio_drive = bcm2835_swdio_drive,
+ .swd_write = bcm2835gpio_swd_write,
.blink = NULL
};
@@ -108,10 +110,10 @@ static int bcm2835gpio_write(int tck, int tms, int tdi)
return ERROR_OK;
}
-static int bcm2835gpio_swd_write(int tck, int tms, int tdi)
+static int bcm2835gpio_swd_write(int swclk, int swdio)
{
- uint32_t set = tck<<swclk_gpio | tdi<<swdio_gpio;
- uint32_t clear = !tck<<swclk_gpio | !tdi<<swdio_gpio;
+ uint32_t set = swclk << swclk_gpio | swdio << swdio_gpio;
+ uint32_t clear = !swclk << swclk_gpio | !swdio << swdio_gpio;
GPIO_SET = set;
GPIO_CLR = clear;
@@ -533,10 +535,6 @@ static int bcm2835gpio_init(void)
"tdo %d trst %d srst %d", tck_gpio_mode, tms_gpio_mode,
tdi_gpio_mode, tdo_gpio_mode, trst_gpio_mode, srst_gpio_mode);
- if (swd_mode) {
- bcm2835gpio_bitbang.write = bcm2835gpio_swd_write;
- }
-
return ERROR_OK;
}
diff --git a/src/jtag/drivers/bitbang.c b/src/jtag/drivers/bitbang.c
index e5df3cf40..4417e1258 100644
--- a/src/jtag/drivers/bitbang.c
+++ b/src/jtag/drivers/bitbang.c
@@ -382,28 +382,24 @@ int bitbang_execute_queue(void)
return retval;
}
-
-bool swd_mode;
static int queued_retval;
static int bitbang_swd_init(void)
{
LOG_DEBUG("bitbang_swd_init");
- swd_mode = true;
return ERROR_OK;
}
-static void bitbang_exchange(bool rnw, uint8_t buf[], unsigned int offset, unsigned int bit_cnt)
+static void bitbang_swd_exchange(bool rnw, uint8_t buf[], unsigned int offset, unsigned int bit_cnt)
{
- LOG_DEBUG("bitbang_exchange");
- int tdi;
+ LOG_DEBUG("bitbang_swd_exchange");
for (unsigned int i = offset; i < bit_cnt + offset; i++) {
int bytec = i/8;
int bcval = 1 << (i % 8);
- tdi = !rnw && (buf[bytec] & bcval);
+ int swdio = !rnw && (buf[bytec] & bcval);
- bitbang_interface->write(0, 0, tdi);
+ bitbang_interface->swd_write(0, swdio);
if (rnw && buf) {
if (bitbang_interface->swdio_read())
@@ -412,7 +408,7 @@ static void bitbang_exchange(bool rnw, uint8_t buf[], unsigned int offset, unsig
buf[bytec] &= ~bcval;
}
- bitbang_interface->write(1, 0, tdi);
+ bitbang_interface->swd_write(1, swdio);
}
}
@@ -423,15 +419,15 @@ static int bitbang_swd_switch_seq(enum swd_special_seq seq)
switch (seq) {
case LINE_RESET:
LOG_DEBUG("SWD line reset");
- bitbang_exchange(false, (uint8_t *)swd_seq_line_reset, 0, swd_seq_line_reset_len);
+ bitbang_swd_exchange(false, (uint8_t *)swd_seq_line_reset, 0, swd_seq_line_reset_len);
break;
case JTAG_TO_SWD:
LOG_DEBUG("JTAG-to-SWD");
- bitbang_exchange(false, (uint8_t *)swd_seq_jtag_to_swd, 0, swd_seq_jtag_to_swd_len);
+ bitbang_swd_exchange(false, (uint8_t *)swd_seq_jtag_to_swd, 0, swd_seq_jtag_to_swd_len);
break;
case SWD_TO_JTAG:
LOG_DEBUG("SWD-to-JTAG");
- bitbang_exchange(false, (uint8_t *)swd_seq_swd_to_jtag, 0, swd_seq_swd_to_jtag_len);
+ bitbang_swd_exchange(false, (uint8_t *)swd_seq_swd_to_jtag, 0, swd_seq_swd_to_jtag_len);
break;
default:
LOG_ERROR("Sequence %d not supported", seq);
@@ -461,10 +457,10 @@ static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay
uint8_t trn_ack_data_parity_trn[DIV_ROUND_UP(4 + 3 + 32 + 1 + 4, 8)];
cmd |= SWD_CMD_START | (1 << 7);
- bitbang_exchange(false, &cmd, 0, 8);
+ bitbang_swd_exchange(false, &cmd, 0, 8);
bitbang_interface->swdio_drive(false);
- bitbang_exchange(true, trn_ack_data_parity_trn, 0, 1 + 3 + 32 + 1 + 1);
+ bitbang_swd_exchange(true, trn_ack_data_parity_trn, 0, 1 + 3 + 32 + 1 + 1);
bitbang_interface->swdio_drive(true);
int ack = buf_get_u32(trn_ack_data_parity_trn, 1, 3);
@@ -488,7 +484,7 @@ static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay
if (value)
*value = data;
if (cmd & SWD_CMD_APnDP)
- bitbang_exchange(true, NULL, 0, ap_delay_clk);
+ bitbang_swd_exchange(true, NULL, 0, ap_delay_clk);
return;
case SWD_ACK_WAIT:
LOG_DEBUG("SWD_ACK_WAIT");
@@ -522,12 +518,12 @@ static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay
buf_set_u32(trn_ack_data_parity_trn, 1 + 3 + 1 + 32, 1, parity_u32(value));
cmd |= SWD_CMD_START | (1 << 7);
- bitbang_exchange(false, &cmd, 0, 8);
+ bitbang_swd_exchange(false, &cmd, 0, 8);
bitbang_interface->swdio_drive(false);
- bitbang_exchange(true, trn_ack_data_parity_trn, 0, 1 + 3 + 1);
+ bitbang_swd_exchange(true, trn_ack_data_parity_trn, 0, 1 + 3 + 1);
bitbang_interface->swdio_drive(true);
- bitbang_exchange(false, trn_ack_data_parity_trn, 1 + 3 + 1, 32 + 1);
+ bitbang_swd_exchange(false, trn_ack_data_parity_trn, 1 + 3 + 1, 32 + 1);
int ack = buf_get_u32(trn_ack_data_parity_trn, 1, 3);
LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
@@ -540,7 +536,7 @@ static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay
switch (ack) {
case SWD_ACK_OK:
if (cmd & SWD_CMD_APnDP)
- bitbang_exchange(true, NULL, 0, ap_delay_clk);
+ bitbang_swd_exchange(true, NULL, 0, ap_delay_clk);
return;
case SWD_ACK_WAIT:
LOG_DEBUG("SWD_ACK_WAIT");
@@ -563,7 +559,7 @@ static int bitbang_swd_run_queue(void)
LOG_DEBUG("bitbang_swd_run_queue");
/* A transaction must be followed by another transaction or at least 8 idle cycles to
* ensure that data is clocked through the AP. */
- bitbang_exchange(true, NULL, 0, 8);
+ bitbang_swd_exchange(true, NULL, 0, 8);
int retval = queued_retval;
queued_retval = ERROR_OK;
diff --git a/src/jtag/drivers/bitbang.h b/src/jtag/drivers/bitbang.h
index 52dfbda30..bc2c506bc 100644
--- a/src/jtag/drivers/bitbang.h
+++ b/src/jtag/drivers/bitbang.h
@@ -62,12 +62,13 @@ struct bitbang_interface {
/** Set direction of SWDIO. */
void (*swdio_drive)(bool on);
+
+ /** Set SWCLK and SWDIO to the given value. */
+ int (*swd_write)(int swclk, int swdio);
};
extern const struct swd_driver bitbang_swd;
-extern bool swd_mode;
-
int bitbang_execute_queue(void);
extern struct bitbang_interface *bitbang_interface;
diff --git a/src/jtag/drivers/imx_gpio.c b/src/jtag/drivers/imx_gpio.c
index debddedfe..b96b433f7 100644
--- a/src/jtag/drivers/imx_gpio.c
+++ b/src/jtag/drivers/imx_gpio.c
@@ -87,6 +87,7 @@ static int imx_gpio_write(int tck, int tms, int tdi);
static int imx_gpio_swdio_read(void);
static void imx_gpio_swdio_drive(bool is_output);
+static int imx_gpio_swd_write(int swclk, int swdio);
static int imx_gpio_init(void);
static int imx_gpio_quit(void);
@@ -96,6 +97,7 @@ static struct bitbang_interface imx_gpio_bitbang = {
.write = imx_gpio_write,
.swdio_read = imx_gpio_swdio_read,
.swdio_drive = imx_gpio_swdio_drive,
+ .swd_write = imx_gpio_swd_write,
.blink = NULL
};
@@ -143,10 +145,10 @@ static int imx_gpio_write(int tck, int tms, int tdi)
return ERROR_OK;
}
-static int imx_gpio_swd_write(int tck, int tms, int tdi)
+static int imx_gpio_swd_write(int swclk, int swdio)
{
- tdi ? gpio_set(swdio_gpio) : gpio_clear(swdio_gpio);
- tck ? gpio_set(swclk_gpio) : gpio_clear(swclk_gpio);
+ swdio ? gpio_set(swdio_gpio) : gpio_clear(swdio_gpio);
+ swclk ? gpio_set(swclk_gpio) : gpio_clear(swclk_gpio);
for (unsigned int i = 0; i < jtag_delay; i++)
asm volatile ("");
@@ -550,10 +552,6 @@ static int imx_gpio_init(void)
"tdo %d trst %d srst %d", tck_gpio_mode, tms_gpio_mode,
tdi_gpio_mode, tdo_gpio_mode, trst_gpio_mode, srst_gpio_mode);
- if (swd_mode) {
- imx_gpio_bitbang.write = imx_gpio_swd_write;
- }
-
return ERROR_OK;
}
diff --git a/src/jtag/drivers/sysfsgpio.c b/src/jtag/drivers/sysfsgpio.c
index f9470a47b..a58962098 100644
--- a/src/jtag/drivers/sysfsgpio.c
+++ b/src/jtag/drivers/sysfsgpio.c
@@ -230,7 +230,7 @@ static int sysfsgpio_swdio_read(void)
return buf[0] != '0';
}
-static void sysfsgpio_swdio_write(int swclk, int swdio)
+static int sysfsgpio_swd_write(int swclk, int swdio)
{
const char one[] = "1";
const char zero[] = "0";
@@ -255,6 +255,8 @@ static void sysfsgpio_swdio_write(int swclk, int swdio)
last_swdio = swdio;
last_swclk = swclk;
last_stored = true;
+
+ return ERROR_OK;
}
/*
@@ -287,11 +289,6 @@ static bb_value_t sysfsgpio_read(void)
*/
static int sysfsgpio_write(int tck, int tms, int tdi)
{
- if (swd_mode) {
- sysfsgpio_swdio_write(tck, tdi);
- return ERROR_OK;
- }
-
const char one[] = "1";
const char zero[] = "0";
@@ -572,6 +569,7 @@ static struct bitbang_interface sysfsgpio_bitbang = {
.write = sysfsgpio_write,
.swdio_read = sysfsgpio_swdio_read,
.swdio_drive = sysfsgpio_swdio_drive,
+ .swd_write = sysfsgpio_swd_write,
.blink = 0
};
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/bcm2835gpio.c | 12 +++---
src/jtag/drivers/bitbang.c | 36 ++++++++---------
src/jtag/drivers/bitbang.h | 5 ++-
src/jtag/drivers/imx_gpio.c | 12 +++---
src/jtag/drivers/sysfsgpio.c | 89 +++++++++++++++++++-----------------------
5 files changed, 70 insertions(+), 84 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-07-13 22:53:39
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 49232a80d2cb1a2e188a037cad94fd760ae64808 (commit)
via 1f5962203a06803b8ccf4c374b81e45918291f4f (commit)
from fd9a7a8c8ab2431a2bc69ab515d868cdf5178761 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 49232a80d2cb1a2e188a037cad94fd760ae64808
Author: Antonio Borneo <bor...@gm...>
Date: Wed Apr 1 09:39:40 2020 +0200
bitbang: remove superfluous switch between jtag and swd
The SWD framework already takes care of switching between JTAG and
SWD by calling driver's switch_seq() in swd_connect() and in
swd_quit(); there is no need for the driver to force the switch
again.
Remove the extra switch between jtag and swd.
Change-Id: I84de4bffb593374b96fce31951c6cc83f92d2578
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5554
Tested-by: jenkins
diff --git a/src/jtag/drivers/bcm2835gpio.c b/src/jtag/drivers/bcm2835gpio.c
index df557c5c6..f547d93a4 100644
--- a/src/jtag/drivers/bcm2835gpio.c
+++ b/src/jtag/drivers/bcm2835gpio.c
@@ -535,7 +535,6 @@ static int bcm2835gpio_init(void)
if (swd_mode) {
bcm2835gpio_bitbang.write = bcm2835gpio_swd_write;
- bitbang_switch_to_swd();
}
return ERROR_OK;
diff --git a/src/jtag/drivers/bitbang.c b/src/jtag/drivers/bitbang.c
index 72e9320b4..e5df3cf40 100644
--- a/src/jtag/drivers/bitbang.c
+++ b/src/jtag/drivers/bitbang.c
@@ -416,7 +416,7 @@ static void bitbang_exchange(bool rnw, uint8_t buf[], unsigned int offset, unsig
}
}
-int bitbang_swd_switch_seq(enum swd_special_seq seq)
+static int bitbang_swd_switch_seq(enum swd_special_seq seq)
{
LOG_DEBUG("bitbang_swd_switch_seq");
@@ -441,12 +441,6 @@ int bitbang_swd_switch_seq(enum swd_special_seq seq)
return ERROR_OK;
}
-void bitbang_switch_to_swd(void)
-{
- LOG_DEBUG("bitbang_switch_to_swd");
- bitbang_exchange(false, (uint8_t *)swd_seq_jtag_to_swd, 0, swd_seq_jtag_to_swd_len);
-}
-
static void swd_clear_sticky_errors(void)
{
bitbang_swd_write_reg(swd_cmd(false, false, DP_ABORT),
diff --git a/src/jtag/drivers/bitbang.h b/src/jtag/drivers/bitbang.h
index 7516c24a6..52dfbda30 100644
--- a/src/jtag/drivers/bitbang.h
+++ b/src/jtag/drivers/bitbang.h
@@ -71,7 +71,5 @@ extern bool swd_mode;
int bitbang_execute_queue(void);
extern struct bitbang_interface *bitbang_interface;
-void bitbang_switch_to_swd(void);
-int bitbang_swd_switch_seq(enum swd_special_seq seq);
#endif /* OPENOCD_JTAG_DRIVERS_BITBANG_H */
diff --git a/src/jtag/drivers/imx_gpio.c b/src/jtag/drivers/imx_gpio.c
index 7dcfb6790..debddedfe 100644
--- a/src/jtag/drivers/imx_gpio.c
+++ b/src/jtag/drivers/imx_gpio.c
@@ -552,7 +552,6 @@ static int imx_gpio_init(void)
if (swd_mode) {
imx_gpio_bitbang.write = imx_gpio_swd_write;
- bitbang_switch_to_swd();
}
return ERROR_OK;
diff --git a/src/jtag/drivers/sysfsgpio.c b/src/jtag/drivers/sysfsgpio.c
index a4d7ad9ec..f9470a47b 100644
--- a/src/jtag/drivers/sysfsgpio.c
+++ b/src/jtag/drivers/sysfsgpio.c
@@ -694,13 +694,6 @@ static int sysfsgpio_init(void)
goto out_error;
}
- if (sysfsgpio_swd_mode_possible()) {
- if (swd_mode)
- bitbang_swd_switch_seq(JTAG_TO_SWD);
- else
- bitbang_swd_switch_seq(SWD_TO_JTAG);
- }
-
return ERROR_OK;
out_error:
commit 1f5962203a06803b8ccf4c374b81e45918291f4f
Author: Antonio Borneo <bor...@gm...>
Date: Wed Apr 1 09:37:54 2020 +0200
bitbang: document bitbang callbacks
Change-Id: I732c2eeb452f3ba8a2385d0e02fccbe86381812c
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5553
Tested-by: jenkins
diff --git a/src/jtag/drivers/bitbang.h b/src/jtag/drivers/bitbang.h
index bbbc693df..7516c24a6 100644
--- a/src/jtag/drivers/bitbang.h
+++ b/src/jtag/drivers/bitbang.h
@@ -38,21 +38,29 @@ typedef enum {
* sample requests together. Not waiting for a value to come back can greatly
* increase throughput. */
struct bitbang_interface {
- /** Sample TDO. */
+ /** Sample TDO and return the value. */
bb_value_t (*read)(void);
/** The number of TDO samples that can be buffered up before the caller has
* to call read_sample. */
size_t buf_size;
+
/** Sample TDO and put the result in a buffer. */
int (*sample)(void);
+
/** Return the next unread value from the buffer. */
bb_value_t (*read_sample)(void);
/** Set TCK, TMS, and TDI to the given values. */
int (*write)(int tck, int tms, int tdi);
+
+ /** Blink led (optional). */
int (*blink)(int on);
+
+ /** Sample SWDIO and return the value. */
int (*swdio_read)(void);
+
+ /** Set direction of SWDIO. */
void (*swdio_drive)(bool on);
};
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/bcm2835gpio.c | 1 -
src/jtag/drivers/bitbang.c | 8 +-------
src/jtag/drivers/bitbang.h | 12 +++++++++---
src/jtag/drivers/imx_gpio.c | 1 -
src/jtag/drivers/sysfsgpio.c | 7 -------
5 files changed, 10 insertions(+), 19 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2020-07-13 18:28:33
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via fd9a7a8c8ab2431a2bc69ab515d868cdf5178761 (commit)
via 8d7ca437754e2bd5774dd3543ec23b5b3a32fbb2 (commit)
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- Log -----------------------------------------------------------------
commit fd9a7a8c8ab2431a2bc69ab515d868cdf5178761
Author: Tomas Vanek <va...@fb...>
Date: Thu Jul 2 10:50:15 2020 +0200
flash/nor/kinetis: fix FCF handling
Kinetis Flash Configuration Field needs special handling to prevent unwanted
locking of the device. Warn user about any difference between generated
FCF and FCF data in the programmed file. Inform user that re-programming
of already programmed FCF may fail on devices with FTFE flash module.
While on it remove useless setting of is_erased flag after erase.
Change-Id: I3911f436674547fa12ef3886c7d5e8cd889f9e2b
Signed-off-by: Tomas Vanek <va...@fb...>
Fixes: https://sourceforge.net/p/openocd/tickets/270/
Reported-by: Noel Diviney <vk...@us...>
Reviewed-on: http://openocd.zylin.com/5753
Tested-by: jenkins
diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c
index d89747804..07c5eac36 100644
--- a/src/flash/nor/kinetis.c
+++ b/src/flash/nor/kinetis.c
@@ -389,7 +389,6 @@ static const struct kinetis_type kinetis_types_old[] = {
static bool allow_fcf_writes;
static uint8_t fcf_fopt = 0xff;
-static bool fcf_fopt_configured;
static bool create_banks;
@@ -1650,8 +1649,6 @@ static int kinetis_erase(struct flash_bank *bank, unsigned int first,
return ERROR_FLASH_OPERATION_FAILED;
}
- bank->sectors[i].is_erased = 1;
-
if (k_bank->prog_base == 0
&& bank->sectors[i].offset <= FCF_ADDRESS
&& bank->sectors[i].offset + bank->sectors[i].size > FCF_ADDRESS + FCF_SIZE) {
@@ -1665,7 +1662,8 @@ static int kinetis_erase(struct flash_bank *bank, unsigned int first,
result = kinetis_write_inner(bank, fcf_buffer, FCF_ADDRESS, FCF_SIZE);
if (result != ERROR_OK)
LOG_WARNING("Flash Configuration Field write failed");
- bank->sectors[i].is_erased = 0;
+ else
+ LOG_DEBUG("Generated FCF written");
}
}
}
@@ -1909,6 +1907,7 @@ static int kinetis_write(struct flash_bank *bank, const uint8_t *buffer,
int result;
bool set_fcf = false;
bool fcf_in_data_valid = false;
+ bool fcf_differs = false;
int sect = 0;
struct kinetis_flash_bank *k_bank = bank->driver_priv;
struct kinetis_chip *k_chip = k_bank->k_chip;
@@ -1941,31 +1940,45 @@ static int kinetis_write(struct flash_bank *bank, const uint8_t *buffer,
&& offset + count >= FCF_ADDRESS + FCF_SIZE;
if (fcf_in_data_valid) {
memcpy(fcf_in_data, buffer + FCF_ADDRESS - offset, FCF_SIZE);
- if (memcmp(fcf_in_data + FCF_FPROT, fcf_buffer, 4)) {
- fcf_in_data_valid = false;
- LOG_INFO("Flash protection requested in programmed file differs from current setting.");
+ if (memcmp(fcf_in_data, fcf_buffer, 8)) {
+ fcf_differs = true;
+ LOG_INFO("Setting of backdoor key is not supported in mode 'kinetis fcf_source protection'.");
+ }
+ if (memcmp(fcf_in_data + FCF_FPROT, fcf_buffer + FCF_FPROT, 4)) {
+ fcf_differs = true;
+ LOG_INFO("Flash protection requested in the programmed file differs from current setting.");
}
if (fcf_in_data[FCF_FDPROT] != fcf_buffer[FCF_FDPROT]) {
- fcf_in_data_valid = false;
- LOG_INFO("Data flash protection requested in programmed file differs from current setting.");
+ fcf_differs = true;
+ LOG_INFO("Data flash protection requested in the programmed file differs from current setting.");
}
if ((fcf_in_data[FCF_FSEC] & 3) != 2) {
fcf_in_data_valid = false;
- LOG_INFO("Device security requested in programmed file!");
- } else if (k_chip->flash_support & FS_ECC
- && fcf_in_data[FCF_FSEC] != fcf_buffer[FCF_FSEC]) {
- fcf_in_data_valid = false;
+ LOG_INFO("Device security requested in the programmed file! Write denied.");
+ } else if (fcf_in_data[FCF_FSEC] != fcf_buffer[FCF_FSEC]) {
+ fcf_differs = true;
LOG_INFO("Strange unsecure mode 0x%02" PRIx8
- "requested in programmed file!",
- fcf_in_data[FCF_FSEC]);
+ " requested in the programmed file, set FSEC = 0x%02" PRIx8
+ " in the startup code!",
+ fcf_in_data[FCF_FSEC], fcf_buffer[FCF_FSEC]);
}
- if ((k_chip->flash_support & FS_ECC || fcf_fopt_configured)
- && fcf_in_data[FCF_FOPT] != fcf_fopt) {
- fcf_in_data_valid = false;
- LOG_INFO("FOPT requested in programmed file differs from current setting.");
+ if (fcf_in_data[FCF_FOPT] != fcf_buffer[FCF_FOPT]) {
+ fcf_differs = true;
+ LOG_INFO("FOPT requested in the programmed file differs from current setting, set 'kinetis fopt 0x%02"
+ PRIx8 "'.", fcf_in_data[FCF_FOPT]);
+ }
+
+ /* If the device has ECC flash, then we cannot re-program FCF */
+ if (fcf_differs) {
+ if (k_chip->flash_support & FS_ECC) {
+ fcf_in_data_valid = false;
+ LOG_INFO("Cannot re-program FCF. Expect verify errors at FCF (0x400-0x40f).");
+ } else {
+ LOG_INFO("Trying to re-program FCF.");
+ if (!(k_chip->flash_support & FS_PROGRAM_LONGWORD))
+ LOG_INFO("Flash re-programming may fail on this device!");
+ }
}
- if (!fcf_in_data_valid)
- LOG_INFO("Expect verify errors at FCF (0x408-0x40f).");
}
}
@@ -3035,7 +3048,6 @@ COMMAND_HANDLER(kinetis_fopt_handler)
if (CMD_ARGC == 1) {
fcf_fopt = (uint8_t)strtoul(CMD_ARGV[0], NULL, 0);
- fcf_fopt_configured = true;
} else {
command_print(CMD, "FCF_FOPT 0x%02" PRIx8, fcf_fopt);
}
commit 8d7ca437754e2bd5774dd3543ec23b5b3a32fbb2
Author: Tomas Vanek <va...@fb...>
Date: Thu Jul 2 09:33:57 2020 +0200
flash/nor/kinetis: use target_get_working_area_avail()
Since e22c6484eaedd56d71 the trial/error allocation shows
"not enough working area available(requested 2048)" message
on klx.cfg. The message is not clear if it means a problem or not.
Replace with new style allocation using target_get_working_area_avail()
Change-Id: I87fe1e38248fcac29982b72aaba12217a0552f38
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: http://openocd.zylin.com/5752
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <and...@gm...>
diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c
index 6753f0fe3..d89747804 100644
--- a/src/flash/nor/kinetis.c
+++ b/src/flash/nor/kinetis.c
@@ -1250,7 +1250,7 @@ static int kinetis_write_block(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t wcount)
{
struct target *target = bank->target;
- uint32_t buffer_size = 2048; /* Default minimum value */
+ uint32_t buffer_size;
struct working_area *write_algorithm;
struct working_area *source;
struct kinetis_flash_bank *k_bank = bank->driver_priv;
@@ -1261,10 +1261,6 @@ static int kinetis_write_block(struct flash_bank *bank, const uint8_t *buffer,
int retval;
uint8_t fstat;
- /* Increase buffer_size if needed */
- if (buffer_size < (target->working_area_size/2))
- buffer_size = (target->working_area_size/2);
-
/* allocate working area with flash programming code */
if (target_alloc_working_area(target, sizeof(kinetis_flash_write_code),
&write_algorithm) != ERROR_OK) {
@@ -1277,16 +1273,19 @@ static int kinetis_write_block(struct flash_bank *bank, const uint8_t *buffer,
if (retval != ERROR_OK)
return retval;
- /* memory buffer */
- while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
- buffer_size /= 4;
- if (buffer_size <= 256) {
- /* free working area, write algorithm already allocated */
- target_free_working_area(target, write_algorithm);
+ /* memory buffer, size *must* be multiple of word */
+ buffer_size = target_get_working_area_avail(target) & ~(sizeof(uint32_t) - 1);
+ if (buffer_size < 256) {
+ LOG_WARNING("large enough working area not available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ } else if (buffer_size > 16384) {
+ /* probably won't benefit from more than 16k ... */
+ buffer_size = 16384;
+ }
- LOG_WARNING("No large enough working area available, can't do block memory writes");
- return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
- }
+ if (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK) {
+ LOG_ERROR("allocating working area failed");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/kinetis.c | 83 ++++++++++++++++++++++++++++---------------------
1 file changed, 47 insertions(+), 36 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2020-07-08 21:09:31
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via e8cfdd4a7208c4c2e7713eff46edecb4abbe37d6 (commit)
from 996ff5bcfc402227ac2f28601e931f30b62e393f (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit e8cfdd4a7208c4c2e7713eff46edecb4abbe37d6
Author: Antonio Borneo <bor...@gm...>
Date: Fri Sep 27 13:17:15 2019 +0200
gdb_server: suggest user to prefer GDB extended mode
In case of GDB connection not using extended mode, issue a warning
message to suggest the user to switch using the extended mode.
Issue the message only once at each run of OpenOCD, to avoid too
much noise.
Update the documentation to suggest using extended mode.
Change-Id: I9326e84f748d5d7912d5a48f00f0fb541ca19221
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5311
Tested-by: jenkins
Reviewed-by: Karl Palsson <ka...@tw...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index a0ce7e349..9f20e391d 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -10337,18 +10337,31 @@ OpenOCD can communicate with GDB in two ways:
@item
A socket (TCP/IP) connection is typically started as follows:
@example
-target remote localhost:3333
+target extended-remote localhost:3333
@end example
This would cause GDB to connect to the gdbserver on the local pc using port 3333.
-It is also possible to use the GDB extended remote protocol as follows:
+The extended remote protocol is a super-set of the remote protocol and should
+be the preferred choice. More details are available in GDB documentation
+@url{https://sourceware.org/gdb/onlinedocs/gdb/Connecting.html}
+
+To speed-up typing, any GDB command can be abbreviated, including the extended
+remote command above that becomes:
@example
-target extended-remote localhost:3333
+tar ext :3333
@end example
+
+@b{Note:} If any backward compatibility issue requires using the old remote
+protocol in place of the extended remote one, the former protocol is still
+available through the command:
+@example
+target remote localhost:3333
+@end example
+
@item
A pipe connection is typically started as follows:
@example
-target remote | openocd -c "gdb_port pipe; log_output openocd.log"
+target extended-remote | openocd -c "gdb_port pipe; log_output openocd.log"
@end example
This would cause GDB to run OpenOCD and communicate using pipes (stdin/stdout).
Using this method has the advantage of GDB starting/stopping OpenOCD for the debug
@@ -10370,7 +10383,7 @@ Most programs would be written into flash (address 0) and run from there.
@example
$ arm-none-eabi-gdb example.elf
-(gdb) target remote localhost:3333
+(gdb) target extended-remote localhost:3333
Remote debugging using localhost:3333
...
(gdb) monitor reset halt
@@ -10505,7 +10518,7 @@ set remote interrupt-on-connect off
If you switched gdb_memory_map off, you may want to setup GDB memory map
manually or issue @command{set mem inaccessible-by-default off}
-Now you can issue GDB command @command{target remote ...} and inspect memory
+Now you can issue GDB command @command{target extended-remote ...} and inspect memory
of a running target. Do not use GDB commands @command{continue},
@command{step} or @command{next} as they synchronize GDB with your target
and GDB would require stopping the target to get the prompt back.
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 0e0b595c6..17042fbf5 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -3228,6 +3228,7 @@ static int gdb_input_inner(struct connection *connection)
int packet_size;
int retval;
struct gdb_connection *gdb_con = connection->priv;
+ static bool warn_use_ext;
target = get_target_from_connection(connection);
@@ -3304,6 +3305,12 @@ static int gdb_input_inner(struct connection *connection)
break;
case '?':
gdb_last_signal_packet(connection, packet, packet_size);
+ /* '?' is sent after the eventual '!' */
+ if (!warn_use_ext && !gdb_con->extended_protocol) {
+ warn_use_ext = true;
+ LOG_WARNING("Prefer GDB command \"target extended-remote %s\" instead of \"target remote %s\"",
+ connection->service->port, connection->service->port);
+ }
break;
case 'c':
case 's':
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 25 +++++++++++++++++++------
src/server/gdb_server.c | 7 +++++++
2 files changed, 26 insertions(+), 6 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2020-07-08 21:08:52
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 996ff5bcfc402227ac2f28601e931f30b62e393f
Author: Antonio Borneo <bor...@gm...>
Date: Tue May 7 00:26:46 2019 +0200
coding style: add arguments to function prototypes
Issue identified by checkpatch script from Linux kernel v5.1 using
the command
find src/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types FUNCTION_ARGUMENTS -f {} \;
This patch also fixes an incorrect function prototype in zy1000.c.
ZY1000 minidriver implementation overrides the function
arm11_run_instr_data_to_core_noack_inner(), but the prototype is
not the same as in src/target/arm11_dbgtap.c and to avoid compile
error it was changed also the prototype of the called function
arm11_run_instr_data_to_core_noack_inner_default().
Change-Id: I476cda8cdb0e1e280795b3b43ca95c40d09e4a3d
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5630
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <and...@gm...>
diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h
index 7f033e0e7..9350642ff 100644
--- a/src/jtag/jtag.h
+++ b/src/jtag/jtag.h
@@ -392,7 +392,7 @@ typedef intptr_t jtag_callback_data_t;
typedef void (*jtag_callback1_t)(jtag_callback_data_t data0);
/** A simpler version of jtag_add_callback4(). */
-void jtag_add_callback(jtag_callback1_t, jtag_callback_data_t data0);
+void jtag_add_callback(jtag_callback1_t f, jtag_callback_data_t data0);
/**
diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c
index 37af2f7ae..669e6f45c 100644
--- a/src/jtag/zy1000/zy1000.c
+++ b/src/jtag/zy1000/zy1000.c
@@ -674,7 +674,7 @@ void embeddedice_write_dcc(struct jtag_tap *tap,
int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap,
uint32_t opcode,
- const uint32_t *data,
+ uint32_t *data,
size_t count)
{
/* bypass bits before and after */
@@ -684,8 +684,8 @@ int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap,
post_bits += 2;
if ((pre_bits > 32) || (post_bits > 32)) {
- int arm11_run_instr_data_to_core_noack_inner_default(struct jtag_tap *,
- uint32_t, const uint32_t *, size_t);
+ int arm11_run_instr_data_to_core_noack_inner_default(struct jtag_tap *tap,
+ uint32_t opcode, uint32_t *data, size_t count);
return arm11_run_instr_data_to_core_noack_inner_default(tap, opcode, data, count);
} else {
static const uint8_t zero;
diff --git a/src/server/server.h b/src/server/server.h
index f4cc39d3a..ff2ada9cb 100644
--- a/src/server/server.h
+++ b/src/server/server.h
@@ -87,7 +87,7 @@ int server_preinit(void);
int server_init(struct command_context *cmd_ctx);
int server_quit(void);
void server_free(void);
-void exit_on_signal(int);
+void exit_on_signal(int sig);
int server_loop(struct command_context *command_context);
diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index d05c66c43..82707822b 100644
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -62,29 +62,29 @@ struct arm_dpm {
uint64_t didr;
/** Invoke before a series of instruction operations */
- int (*prepare)(struct arm_dpm *);
+ int (*prepare)(struct arm_dpm *dpm);
/** Invoke after a series of instruction operations */
- int (*finish)(struct arm_dpm *);
+ int (*finish)(struct arm_dpm *dpm);
/** Runs one instruction. */
- int (*instr_execute)(struct arm_dpm *, uint32_t opcode);
+ int (*instr_execute)(struct arm_dpm *dpm, uint32_t opcode);
/* WRITE TO CPU */
/** Runs one instruction, writing data to DCC before execution. */
- int (*instr_write_data_dcc)(struct arm_dpm *,
+ int (*instr_write_data_dcc)(struct arm_dpm *dpm,
uint32_t opcode, uint32_t data);
- int (*instr_write_data_dcc_64)(struct arm_dpm *,
+ int (*instr_write_data_dcc_64)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t data);
/** Runs one instruction, writing data to R0 before execution. */
- int (*instr_write_data_r0)(struct arm_dpm *,
+ int (*instr_write_data_r0)(struct arm_dpm *dpm,
uint32_t opcode, uint32_t data);
/** Runs one instruction, writing data to R0 before execution. */
- int (*instr_write_data_r0_64)(struct arm_dpm *,
+ int (*instr_write_data_r0_64)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t data);
/** Optional core-specific operation invoked after CPSR writes. */
@@ -93,17 +93,17 @@ struct arm_dpm {
/* READ FROM CPU */
/** Runs one instruction, reading data from dcc after execution. */
- int (*instr_read_data_dcc)(struct arm_dpm *,
+ int (*instr_read_data_dcc)(struct arm_dpm *dpm,
uint32_t opcode, uint32_t *data);
- int (*instr_read_data_dcc_64)(struct arm_dpm *,
+ int (*instr_read_data_dcc_64)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t *data);
/** Runs one instruction, reading data from r0 after execution. */
- int (*instr_read_data_r0)(struct arm_dpm *,
+ int (*instr_read_data_r0)(struct arm_dpm *dpm,
uint32_t opcode, uint32_t *data);
- int (*instr_read_data_r0_64)(struct arm_dpm *,
+ int (*instr_read_data_r0_64)(struct arm_dpm *dpm,
uint32_t opcode, uint64_t *data);
struct reg *(*arm_reg_current)(struct arm *arm,
@@ -117,7 +117,7 @@ struct arm_dpm {
* must currently be disabled. Indices 0..15 are used for
* breakpoints; indices 16..31 are for watchpoints.
*/
- int (*bpwp_enable)(struct arm_dpm *, unsigned index_value,
+ int (*bpwp_enable)(struct arm_dpm *dpm, unsigned index_value,
uint32_t addr, uint32_t control);
/**
@@ -125,7 +125,7 @@ struct arm_dpm {
* hardware control registers. Indices are the same ones
* accepted by bpwp_enable().
*/
- int (*bpwp_disable)(struct arm_dpm *, unsigned index_value);
+ int (*bpwp_disable)(struct arm_dpm *dpm, unsigned index_value);
/* The breakpoint and watchpoint arrays are private to the
* DPM infrastructure. There are nbp indices in the dbp
@@ -153,12 +153,12 @@ int arm_dpm_setup(struct arm_dpm *dpm);
int arm_dpm_initialize(struct arm_dpm *dpm);
int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum);
-int arm_dpm_read_current_registers(struct arm_dpm *);
+int arm_dpm_read_current_registers(struct arm_dpm *dpm);
int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
-int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
+int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp);
-void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);
+void arm_dpm_report_wfar(struct arm_dpm *dpm, uint32_t wfar);
/* DSCR bits; see ARMv7a arch spec section C10.3.1.
* Not all v7 bits are valid in v6.
diff --git a/src/target/armv8_dpm.h b/src/target/armv8_dpm.h
index f40440370..ee6f699de 100644
--- a/src/target/armv8_dpm.h
+++ b/src/target/armv8_dpm.h
@@ -31,13 +31,13 @@ struct armv8_common;
int armv8_dpm_setup(struct arm_dpm *dpm);
int armv8_dpm_initialize(struct arm_dpm *dpm);
-int armv8_dpm_read_current_registers(struct arm_dpm *);
+int armv8_dpm_read_current_registers(struct arm_dpm *dpm);
int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
-int armv8_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
+int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp);
-void armv8_dpm_report_wfar(struct arm_dpm *, uint64_t wfar);
+void armv8_dpm_report_wfar(struct arm_dpm *dpm, uint64_t wfar);
/* DSCR bits; see ARMv7a arch spec section C10.3.1.
* Not all v7 bits are valid in v6.
diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h
index 59414fc08..51cf7f928 100644
--- a/src/target/riscv/riscv.h
+++ b/src/target/riscv/riscv.h
@@ -104,11 +104,11 @@ typedef struct {
* implementations. */
int (*get_register)(struct target *target,
riscv_reg_t *value, int hid, int rid);
- int (*set_register)(struct target *, int hartid, int regid,
+ int (*set_register)(struct target *target, int hartid, int regid,
uint64_t value);
- int (*select_current_hart)(struct target *);
+ int (*select_current_hart)(struct target *target);
bool (*is_halted)(struct target *target);
- int (*halt_current_hart)(struct target *);
+ int (*halt_current_hart)(struct target *target);
int (*resume_current_hart)(struct target *target);
int (*step_current_hart)(struct target *target);
int (*on_halt)(struct target *target);
commit e2315ccffd31757785130c3bf549a87d9be1689a
Author: Antonio Borneo <bor...@gm...>
Date: Mon May 6 18:16:17 2019 +0200
coding style: fix space separation
The checkpatch script from Linux kernel v5.1 complains about using
space before comma, before semicolon and between function name and
open parenthesis.
Fix them!
Issue identified using the command
find src/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types SPACING -f {} \;
The patch only changes amount and position of whitespace, thus
the following commands show empty diff
git diff -w
git log -w -p
git log -w --stat
Change-Id: I1062051d7f97d59922847f5061c6d6811742d30e
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5627
Tested-by: jenkins
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index 434891112..c8c4afe1f 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -1923,7 +1923,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
- .base_address = FLASH_BANK1_BASE_512K_AX ,
+ .base_address = FLASH_BANK1_BASE_512K_AX,
.controller_address = 0x400e0c00,
.flash_wait_states = 6, /* workaround silicon bug */
.present = 1,
diff --git a/src/flash/nor/fespi.c b/src/flash/nor/fespi.c
index 4afa1b8fb..6b2793f1b 100644
--- a/src/flash/nor/fespi.c
+++ b/src/flash/nor/fespi.c
@@ -136,9 +136,9 @@ struct fespi_target {
/* TODO !!! What is the right naming convention here? */
static const struct fespi_target target_devices[] = {
/* name, tap_idcode, ctrl_base */
- { "Freedom E310-G000 SPI Flash", 0x10e31913 , 0x10014000 },
- { "Freedom E310-G002 SPI Flash", 0x20000913 , 0x10014000 },
- { NULL, 0, 0 }
+ { "Freedom E310-G000 SPI Flash", 0x10e31913, 0x10014000 },
+ { "Freedom E310-G002 SPI Flash", 0x20000913, 0x10014000 },
+ { NULL, 0, 0 }
};
FLASH_BANK_COMMAND_HANDLER(fespi_flash_bank_command)
diff --git a/src/flash/nor/lpcspifi.c b/src/flash/nor/lpcspifi.c
index 13bb1f0a1..dd1c63d74 100644
--- a/src/flash/nor/lpcspifi.c
+++ b/src/flash/nor/lpcspifi.c
@@ -216,7 +216,7 @@ static int lpcspifi_set_hw_mode(struct flash_bank *bank)
/* Run the algorithm */
LOG_DEBUG("Running SPIFI init algorithm");
- retval = target_run_algorithm(target, 0 , NULL, 2, reg_params,
+ retval = target_run_algorithm(target, 0, NULL, 2, reg_params,
spifi_init_algorithm->address,
spifi_init_algorithm->address + sizeof(spifi_init_code) - 2,
1000, &armv7m_info);
@@ -550,7 +550,7 @@ static int lpcspifi_erase(struct flash_bank *bank, unsigned int first,
buf_set_u32(reg_params[3].value, 0, 32, bank->sectors[first].size);
/* Run the algorithm */
- retval = target_run_algorithm(target, 0 , NULL, 4, reg_params,
+ retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
erase_algorithm->address,
erase_algorithm->address + sizeof(lpcspifi_flash_erase_code) - 4,
3000*(last - first + 1), &armv7m_info);
diff --git a/src/flash/nor/niietcm4.c b/src/flash/nor/niietcm4.c
index 1ab0a5a35..085403885 100644
--- a/src/flash/nor/niietcm4.c
+++ b/src/flash/nor/niietcm4.c
@@ -1659,7 +1659,7 @@ static int niietcm4_probe_k1921vk01t(struct flash_bank *bank)
niietcm4_info->extmem_boot_pin,
niietcm4_info->extmem_boot_altfunc,
niietcm4_info->extmem_boot ? "enable" : "disable");
- } else{
+ } else {
bank->size = 0x100000;
bank->num_sectors = 128;
diff --git a/src/jtag/drivers/opendous.c b/src/jtag/drivers/opendous.c
index bb223f417..5572c4a0e 100644
--- a/src/jtag/drivers/opendous.c
+++ b/src/jtag/drivers/opendous.c
@@ -596,7 +596,7 @@ void opendous_tap_append_step(int tms, int tdi)
if (!bits)
tms_buffer[tap_index] = 0;
- tms_buffer[tap_index] |= (_tdi << bits)|(_tms << (bits + 1)) ;
+ tms_buffer[tap_index] |= (_tdi << bits)|(_tms << (bits + 1));
tap_length++;
} else
LOG_ERROR("opendous_tap_append_step, overflow");
diff --git a/src/jtag/hla/hla_layout.h b/src/jtag/hla/hla_layout.h
index 1d759e17d..68052952f 100644
--- a/src/jtag/hla/hla_layout.h
+++ b/src/jtag/hla/hla_layout.h
@@ -35,33 +35,33 @@ extern struct hl_layout_api_s icdi_usb_layout_api;
/** */
struct hl_layout_api_s {
/** */
- int (*open) (struct hl_interface_param_s *param, void **handle);
+ int (*open)(struct hl_interface_param_s *param, void **handle);
/** */
- int (*close) (void *handle);
+ int (*close)(void *handle);
/** */
- int (*reset) (void *handle);
+ int (*reset)(void *handle);
/** */
- int (*assert_srst) (void *handle, int srst);
+ int (*assert_srst)(void *handle, int srst);
/** */
- int (*run) (void *handle);
+ int (*run)(void *handle);
/** */
- int (*halt) (void *handle);
+ int (*halt)(void *handle);
/** */
- int (*step) (void *handle);
+ int (*step)(void *handle);
/** */
- int (*read_regs) (void *handle);
+ int (*read_regs)(void *handle);
/** */
- int (*read_reg) (void *handle, int num, uint32_t *val);
+ int (*read_reg)(void *handle, int num, uint32_t *val);
/** */
- int (*write_reg) (void *handle, int num, uint32_t val);
+ int (*write_reg)(void *handle, int num, uint32_t val);
/** */
- int (*read_mem) (void *handle, uint32_t addr, uint32_t size,
+ int (*read_mem)(void *handle, uint32_t addr, uint32_t size,
uint32_t count, uint8_t *buffer);
/** */
- int (*write_mem) (void *handle, uint32_t addr, uint32_t size,
+ int (*write_mem)(void *handle, uint32_t addr, uint32_t size,
uint32_t count, const uint8_t *buffer);
/** */
- int (*write_debug_reg) (void *handle, uint32_t addr, uint32_t val);
+ int (*write_debug_reg)(void *handle, uint32_t addr, uint32_t val);
/**
* Read the idcode of the target connected to the adapter
*
@@ -72,11 +72,11 @@ struct hl_layout_api_s {
* @param idcode Storage for the detected idcode
* @returns ERROR_OK on success, or an error code on failure.
*/
- int (*idcode) (void *handle, uint32_t *idcode);
+ int (*idcode)(void *handle, uint32_t *idcode);
/** */
- int (*override_target) (const char *targetname);
+ int (*override_target)(const char *targetname);
/** */
- int (*custom_command) (void *handle, const char *command);
+ int (*custom_command)(void *handle, const char *command);
/** */
int (*speed)(void *handle, int khz, bool query);
/**
@@ -107,7 +107,7 @@ struct hl_layout_api_s {
*/
int (*poll_trace)(void *handle, uint8_t *buf, size_t *size);
/** */
- enum target_state (*state) (void *fd);
+ enum target_state (*state)(void *fd);
};
/** */
@@ -115,9 +115,9 @@ struct hl_layout {
/** */
char *name;
/** */
- int (*open) (struct hl_interface_s *adapter);
+ int (*open)(struct hl_interface_s *adapter);
/** */
- int (*close) (struct hl_interface_s *adapter);
+ int (*close)(struct hl_interface_s *adapter);
/** */
struct hl_layout_api_s *api;
};
diff --git a/src/rtos/rtos_mqx_stackings.c b/src/rtos/rtos_mqx_stackings.c
index d18e59155..f2d3b2227 100644
--- a/src/rtos/rtos_mqx_stackings.c
+++ b/src/rtos/rtos_mqx_stackings.c
@@ -64,7 +64,7 @@ static const struct stack_register_offset rtos_mqx_arm_v7m_stack_offsets[ARMV7M_
{ ARMV7M_R10, 0x20, 32 }, /* r10 */
{ ARMV7M_R11, 0x24, 32 }, /* r11 */
{ ARMV7M_R12, 0x3C, 32 }, /* r12 */
- { ARMV7M_R13, -2 , 32 }, /* sp */
+ { ARMV7M_R13, -2, 32 }, /* sp */
{ ARMV7M_R14, 0x28, 32 }, /* lr */
{ ARMV7M_PC, 0x44, 32 }, /* pc */
{ ARMV7M_xPSR, 0x48, 32 }, /* xPSR */
diff --git a/src/svf/svf.c b/src/svf/svf.c
index fd27417e0..81400c530 100644
--- a/src/svf/svf.c
+++ b/src/svf/svf.c
@@ -226,7 +226,7 @@ static int svf_getline(char **lineptr, size_t *n, FILE *stream);
#define SVF_MAX_BUFFER_SIZE_TO_COMMIT (1024 * 1024)
static uint8_t *svf_tdi_buffer, *svf_tdo_buffer, *svf_mask_buffer;
-static int svf_buffer_index, svf_buffer_size ;
+static int svf_buffer_index, svf_buffer_size;
static int svf_quiet;
static int svf_nil;
static int svf_ignore_error;
@@ -246,7 +246,7 @@ static int svf_last_printed_percentage = -1;
* DEBUG, INFO, ERROR, USER
*/
#define SVF_BUF_LOG(_lvl, _buf, _nbits, _desc) \
- svf_hexbuf_print(LOG_LVL_##_lvl , __FILE__, __LINE__, __func__, _buf, _nbits, _desc)
+ svf_hexbuf_print(LOG_LVL_##_lvl, __FILE__, __LINE__, __func__, _buf, _nbits, _desc)
static void svf_hexbuf_print(int dbg_lvl, const char *file, unsigned line,
const char *function, const uint8_t *buf,
diff --git a/src/target/arc.c b/src/target/arc.c
index e9709f485..1ac4a4335 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -247,7 +247,7 @@ static int arc_get_register(struct reg *reg)
reg->dirty = false;
LOG_DEBUG("Get register gdb_num=%" PRIu32 ", name=%s, value=0x%" PRIx32,
- reg->number , desc->name, value);
+ reg->number, desc->name, value);
return ERROR_OK;
@@ -884,7 +884,7 @@ static int arc_save_context(struct target *target)
reg->valid = true;
reg->dirty = false;
LOG_DEBUG("Get aux register regnum=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
- i , arc_reg->name, aux_values[aux_cnt]);
+ i, arc_reg->name, aux_values[aux_cnt]);
}
}
diff --git a/src/target/armv8.c b/src/target/armv8.c
index 0c8508661..4f1ebce88 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -1288,13 +1288,13 @@ static struct reg_data_type aarch64v[] = {
};
static struct reg_data_type_bitfield aarch64_cpsr_bits[] = {
- { 0, 0 , REG_TYPE_UINT8 },
- { 2, 3, REG_TYPE_UINT8 },
- { 4, 4 , REG_TYPE_UINT8 },
- { 6, 6 , REG_TYPE_BOOL },
- { 7, 7 , REG_TYPE_BOOL },
- { 8, 8 , REG_TYPE_BOOL },
- { 9, 9 , REG_TYPE_BOOL },
+ { 0, 0, REG_TYPE_UINT8 },
+ { 2, 3, REG_TYPE_UINT8 },
+ { 4, 4, REG_TYPE_UINT8 },
+ { 6, 6, REG_TYPE_BOOL },
+ { 7, 7, REG_TYPE_BOOL },
+ { 8, 8, REG_TYPE_BOOL },
+ { 9, 9, REG_TYPE_BOOL },
{ 20, 20, REG_TYPE_BOOL },
{ 21, 21, REG_TYPE_BOOL },
{ 28, 28, REG_TYPE_BOOL },
@@ -1307,16 +1307,16 @@ static struct reg_data_type_flags_field aarch64_cpsr_fields[] = {
{ "SP", aarch64_cpsr_bits + 0, aarch64_cpsr_fields + 1 },
{ "EL", aarch64_cpsr_bits + 1, aarch64_cpsr_fields + 2 },
{ "nRW", aarch64_cpsr_bits + 2, aarch64_cpsr_fields + 3 },
- { "F" , aarch64_cpsr_bits + 3, aarch64_cpsr_fields + 4 },
- { "I" , aarch64_cpsr_bits + 4, aarch64_cpsr_fields + 5 },
- { "A" , aarch64_cpsr_bits + 5, aarch64_cpsr_fields + 6 },
- { "D" , aarch64_cpsr_bits + 6, aarch64_cpsr_fields + 7 },
- { "IL" , aarch64_cpsr_bits + 7, aarch64_cpsr_fields + 8 },
- { "SS" , aarch64_cpsr_bits + 8, aarch64_cpsr_fields + 9 },
- { "V" , aarch64_cpsr_bits + 9, aarch64_cpsr_fields + 10 },
- { "C" , aarch64_cpsr_bits + 10, aarch64_cpsr_fields + 11 },
- { "Z" , aarch64_cpsr_bits + 11, aarch64_cpsr_fields + 12 },
- { "N" , aarch64_cpsr_bits + 12, NULL }
+ { "F", aarch64_cpsr_bits + 3, aarch64_cpsr_fields + 4 },
+ { "I", aarch64_cpsr_bits + 4, aarch64_cpsr_fields + 5 },
+ { "A", aarch64_cpsr_bits + 5, aarch64_cpsr_fields + 6 },
+ { "D", aarch64_cpsr_bits + 6, aarch64_cpsr_fields + 7 },
+ { "IL", aarch64_cpsr_bits + 7, aarch64_cpsr_fields + 8 },
+ { "SS", aarch64_cpsr_bits + 8, aarch64_cpsr_fields + 9 },
+ { "V", aarch64_cpsr_bits + 9, aarch64_cpsr_fields + 10 },
+ { "C", aarch64_cpsr_bits + 10, aarch64_cpsr_fields + 11 },
+ { "Z", aarch64_cpsr_bits + 11, aarch64_cpsr_fields + 12 },
+ { "N", aarch64_cpsr_bits + 12, NULL }
};
static struct reg_data_type_flags aarch64_cpsr_flags[] = {
diff --git a/src/target/dsp563xx.h b/src/target/dsp563xx.h
index 4bb5aceaf..18428b854 100644
--- a/src/target/dsp563xx.h
+++ b/src/target/dsp563xx.h
@@ -46,8 +46,8 @@ struct dsp563xx_common {
struct once_reg once_regs[DSP563XX_NUMONCEREGS];
/* register cache to processor synchronization */
- int (*read_core_reg) (struct target *target, int num);
- int (*write_core_reg) (struct target *target, int num);
+ int (*read_core_reg)(struct target *target, int num);
+ int (*write_core_reg)(struct target *target, int num);
struct hardware_breakpoint hardware_breakpoint[1];
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 526003216..3929a8c99 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -226,7 +226,7 @@ static int mips32_write_core_reg(struct target *target, unsigned int num)
reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
mips32->core_regs[num] = reg_value;
- LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
+ LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
mips32->core_cache->reg_list[num].valid = true;
mips32->core_cache->reg_list[num].dirty = false;
diff --git a/src/target/mips64.c b/src/target/mips64.c
index 6a7c4252b..347cdfc4b 100644
--- a/src/target/mips64.c
+++ b/src/target/mips64.c
@@ -283,7 +283,7 @@ static int mips64_write_core_reg(struct target *target, int num)
reg_value = buf_get_u64(mips64->core_cache->reg_list[num].value, 0, 64);
mips64->core_regs[num] = reg_value;
- LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num , reg_value);
+ LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value);
mips64->core_cache->reg_list[num].valid = 1;
mips64->core_cache->reg_list[num].dirty = 0;
diff --git a/src/target/nds32.c b/src/target/nds32.c
index f40ce534b..0d1a23a8d 100644
--- a/src/target/nds32.c
+++ b/src/target/nds32.c
@@ -1711,8 +1711,8 @@ int nds32_cache_sync(struct target *target, target_addr_t address, uint32_t leng
/* (address + length - 1) / dcache_line_size */
end_line = (address + length - 1) >> (dcache->line_size + 2);
- for (cur_address = address, cur_line = start_line ;
- cur_line <= end_line ;
+ for (cur_address = address, cur_line = start_line;
+ cur_line <= end_line;
cur_address += dcache_line_size, cur_line++) {
/* D$ write back */
result = aice_cache_ctl(aice, AICE_CACHE_CTL_L1D_VA_WB, cur_address);
@@ -1732,8 +1732,8 @@ int nds32_cache_sync(struct target *target, target_addr_t address, uint32_t leng
/* (address + length - 1) / icache_line_size */
end_line = (address + length - 1) >> (icache->line_size + 2);
- for (cur_address = address, cur_line = start_line ;
- cur_line <= end_line ;
+ for (cur_address = address, cur_line = start_line;
+ cur_line <= end_line;
cur_address += icache_line_size, cur_line++) {
/* Because PSW.IT is turned off under debug exception, address MUST
* be physical address. L1I_VA_INVALIDATE uses PSW.IT to decide
diff --git a/src/target/openrisc/or1k.c b/src/target/openrisc/or1k.c
index 44825d002..ec07126f4 100644
--- a/src/target/openrisc/or1k.c
+++ b/src/target/openrisc/or1k.c
@@ -50,186 +50,186 @@ static int or1k_write_core_reg(struct target *target, int num);
static struct or1k_core_reg *or1k_core_reg_list_arch_info;
static const struct or1k_core_reg_init or1k_init_reg_list[] = {
- {"r0" , GROUP0 + 1024, "org.gnu.gdb.or1k.group0", NULL},
- {"r1" , GROUP0 + 1025, "org.gnu.gdb.or1k.group0", NULL},
- {"r2" , GROUP0 + 1026, "org.gnu.gdb.or1k.group0", NULL},
- {"r3" , GROUP0 + 1027, "org.gnu.gdb.or1k.group0", NULL},
- {"r4" , GROUP0 + 1028, "org.gnu.gdb.or1k.group0", NULL},
- {"r5" , GROUP0 + 1029, "org.gnu.gdb.or1k.group0", NULL},
- {"r6" , GROUP0 + 1030, "org.gnu.gdb.or1k.group0", NULL},
- {"r7" , GROUP0 + 1031, "org.gnu.gdb.or1k.group0", NULL},
- {"r8" , GROUP0 + 1032, "org.gnu.gdb.or1k.group0", NULL},
- {"r9" , GROUP0 + 1033, "org.gnu.gdb.or1k.group0", NULL},
- {"r10" , GROUP0 + 1034, "org.gnu.gdb.or1k.group0", NULL},
- {"r11" , GROUP0 + 1035, "org.gnu.gdb.or1k.group0", NULL},
- {"r12" , GROUP0 + 1036, "org.gnu.gdb.or1k.group0", NULL},
- {"r13" , GROUP0 + 1037, "org.gnu.gdb.or1k.group0", NULL},
- {"r14" , GROUP0 + 1038, "org.gnu.gdb.or1k.group0", NULL},
- {"r15" , GROUP0 + 1039, "org.gnu.gdb.or1k.group0", NULL},
- {"r16" , GROUP0 + 1040, "org.gnu.gdb.or1k.group0", NULL},
- {"r17" , GROUP0 + 1041, "org.gnu.gdb.or1k.group0", NULL},
- {"r18" , GROUP0 + 1042, "org.gnu.gdb.or1k.group0", NULL},
- {"r19" , GROUP0 + 1043, "org.gnu.gdb.or1k.group0", NULL},
- {"r20" , GROUP0 + 1044, "org.gnu.gdb.or1k.group0", NULL},
- {"r21" , GROUP0 + 1045, "org.gnu.gdb.or1k.group0", NULL},
- {"r22" , GROUP0 + 1046, "org.gnu.gdb.or1k.group0", NULL},
- {"r23" , GROUP0 + 1047, "org.gnu.gdb.or1k.group0", NULL},
- {"r24" , GROUP0 + 1048, "org.gnu.gdb.or1k.group0", NULL},
- {"r25" , GROUP0 + 1049, "org.gnu.gdb.or1k.group0", NULL},
- {"r26" , GROUP0 + 1050, "org.gnu.gdb.or1k.group0", NULL},
- {"r27" , GROUP0 + 1051, "org.gnu.gdb.or1k.group0", NULL},
- {"r28" , GROUP0 + 1052, "org.gnu.gdb.or1k.group0", NULL},
- {"r29" , GROUP0 + 1053, "org.gnu.gdb.or1k.group0", NULL},
- {"r30" , GROUP0 + 1054, "org.gnu.gdb.or1k.group0", NULL},
- {"r31" , GROUP0 + 1055, "org.gnu.gdb.or1k.group0", NULL},
- {"ppc" , GROUP0 + 18, "org.gnu.gdb.or1k.group0", NULL},
- {"npc" , GROUP0 + 16, "org.gnu.gdb.or1k.group0", NULL},
- {"sr" , GROUP0 + 17, "org.gnu.gdb.or1k.group0", NULL},
- {"vr" , GROUP0 + 0, "org.gnu.gdb.or1k.group0", "system"},
- {"upr" , GROUP0 + 1, "org.gnu.gdb.or1k.group0", "system"},
- {"cpucfgr" , GROUP0 + 2, "org.gnu.gdb.or1k.group0", "system"},
- {"dmmucfgr" , GROUP0 + 3, "org.gnu.gdb.or1k.group0", "system"},
- {"immucfgr" , GROUP0 + 4, "org.gnu.gdb.or1k.group0", "system"},
- {"dccfgr" , GROUP0 + 5, "org.gnu.gdb.or1k.group0", "system"},
- {"iccfgr" , GROUP0 + 6, "org.gnu.gdb.or1k.group0", "system"},
- {"dcfgr" , GROUP0 + 7, "org.gnu.gdb.or1k.group0", "system"},
- {"pccfgr" , GROUP0 + 8, "org.gnu.gdb.or1k.group0", "system"},
- {"fpcsr" , GROUP0 + 20, "org.gnu.gdb.or1k.group0", "system"},
- {"epcr0" , GROUP0 + 32, "org.gnu.gdb.or1k.group0", "system"},
- {"epcr1" , GROUP0 + 33, "org.gnu.gdb.or1k.group0", "system"},
- {"epcr2" , GROUP0 + 34, "org.gnu.gdb.or1k.group0", "system"},
- {"epcr3" , GROUP0 + 35, "org.gnu.gdb.or1k.group0", "system"},
- {"epcr4" , GROUP0 + 36, "org.gnu.gdb.or1k.group0", "system"},
- {"epcr5" , GROUP0 + 37, "org.gnu.gdb.or1k.group0", "system"},
- {"epcr6" , GROUP0 + 38, "org.gnu.gdb.or1k.group0", "system"},
- {"epcr7" , GROUP0 + 39, "org.gnu.gdb.or1k.group0", "system"},
- {"epcr8" , GROUP0 + 40, "org.gnu.gdb.or1k.group0", "system"},
- {"epcr9" , GROUP0 + 41, "org.gnu.gdb.or1k.group0", "system"},
- {"epcr10" , GROUP0 + 42, "org.gnu.gdb.or1k.group0", "system"},
- {"epcr11" , GROUP0 + 43, "org.gnu.gdb.or1k.group0", "system"},
- {"epcr12" , GROUP0 + 44, "org.gnu.gdb.or1k.group0", "system"},
- {"epcr13" , GROUP0 + 45, "org.gnu.gdb.or1k.group0", "system"},
- {"epcr14" , GROUP0 + 46, "org.gnu.gdb.or1k.group0", "system"},
- {"epcr15" , GROUP0 + 47, "org.gnu.gdb.or1k.group0", "system"},
- {"eear0" , GROUP0 + 48, "org.gnu.gdb.or1k.group0", "system"},
- {"eear1" , GROUP0 + 49, "org.gnu.gdb.or1k.group0", "system"},
- {"eear2" , GROUP0 + 50, "org.gnu.gdb.or1k.group0", "system"},
- {"eear3" , GROUP0 + 51, "org.gnu.gdb.or1k.group0", "system"},
- {"eear4" , GROUP0 + 52, "org.gnu.gdb.or1k.group0", "system"},
- {"eear5" , GROUP0 + 53, "org.gnu.gdb.or1k.group0", "system"},
- {"eear6" , GROUP0 + 54, "org.gnu.gdb.or1k.group0", "system"},
- {"eear7" , GROUP0 + 55, "org.gnu.gdb.or1k.group0", "system"},
- {"eear8" , GROUP0 + 56, "org.gnu.gdb.or1k.group0", "system"},
- {"eear9" , GROUP0 + 57, "org.gnu.gdb.or1k.group0", "system"},
- {"eear10" , GROUP0 + 58, "org.gnu.gdb.or1k.group0", "system"},
- {"eear11" , GROUP0 + 59, "org.gnu.gdb.or1k.group0", "system"},
- {"eear12" , GROUP0 + 60, "org.gnu.gdb.or1k.group0", "system"},
- {"eear13" , GROUP0 + 61, "org.gnu.gdb.or1k.group0", "system"},
- {"eear14" , GROUP0 + 62, "org.gnu.gdb.or1k.group0", "system"},
- {"eear15" , GROUP0 + 63, "org.gnu.gdb.or1k.group0", "system"},
- {"esr0" , GROUP0 + 64, "org.gnu.gdb.or1k.group0", "system"},
- {"esr1" , GROUP0 + 65, "org.gnu.gdb.or1k.group0", "system"},
- {"esr2" , GROUP0 + 66, "org.gnu.gdb.or1k.group0", "system"},
- {"esr3" , GROUP0 + 67, "org.gnu.gdb.or1k.group0", "system"},
- {"esr4" , GROUP0 + 68, "org.gnu.gdb.or1k.group0", "system"},
- {"esr5" , GROUP0 + 69, "org.gnu.gdb.or1k.group0", "system"},
- {"esr6" , GROUP0 + 70, "org.gnu.gdb.or1k.group0", "system"},
- {"esr7" , GROUP0 + 71, "org.gnu.gdb.or1k.group0", "system"},
- {"esr8" , GROUP0 + 72, "org.gnu.gdb.or1k.group0", "system"},
- {"esr9" , GROUP0 + 73, "org.gnu.gdb.or1k.group0", "system"},
- {"esr10" , GROUP0 + 74, "org.gnu.gdb.or1k.group0", "system"},
- {"esr11" , GROUP0 + 75, "org.gnu.gdb.or1k.group0", "system"},
- {"esr12" , GROUP0 + 76, "org.gnu.gdb.or1k.group0", "system"},
- {"esr13" , GROUP0 + 77, "org.gnu.gdb.or1k.group0", "system"},
- {"esr14" , GROUP0 + 78, "org.gnu.gdb.or1k.group0", "system"},
- {"esr15" , GROUP0 + 79, "org.gnu.gdb.or1k.group0", "system"},
-
- {"dmmuucr" , GROUP1 + 0, "org.gnu.gdb.or1k.group1", "dmmu"},
- {"dmmuupr" , GROUP1 + 1, "org.gnu.gdb.or1k.group1", "dmmu"},
- {"dtlbeir" , GROUP1 + 2, "org.gnu.gdb.or1k.group1", "dmmu"},
- {"datbmr0" , GROUP1 + 4, "org.gnu.gdb.or1k.group1", "dmmu"},
- {"datbmr1" , GROUP1 + 5, "org.gnu.gdb.or1k.group1", "dmmu"},
- {"datbmr2" , GROUP1 + 6, "org.gnu.gdb.or1k.group1", "dmmu"},
- {"datbmr3" , GROUP1 + 7, "org.gnu.gdb.or1k.group1", "dmmu"},
- {"datbtr0" , GROUP1 + 8, "org.gnu.gdb.or1k.group1", "dmmu"},
- {"datbtr1" , GROUP1 + 9, "org.gnu.gdb.or1k.group1", "dmmu"},
- {"datbtr2" , GROUP1 + 10, "org.gnu.gdb.or1k.group1", "dmmu"},
- {"datbtr3" , GROUP1 + 11, "org.gnu.gdb.or1k.group1", "dmmu"},
-
- {"immucr" , GROUP2 + 0, "org.gnu.gdb.or1k.group2", "immu"},
- {"immupr" , GROUP2 + 1, "org.gnu.gdb.or1k.group2", "immu"},
- {"itlbeir" , GROUP2 + 2, "org.gnu.gdb.or1k.group2", "immu"},
- {"iatbmr0" , GROUP2 + 4, "org.gnu.gdb.or1k.group2", "immu"},
- {"iatbmr1" , GROUP2 + 5, "org.gnu.gdb.or1k.group2", "immu"},
- {"iatbmr2" , GROUP2 + 6, "org.gnu.gdb.or1k.group2", "immu"},
- {"iatbmr3" , GROUP2 + 7, "org.gnu.gdb.or1k.group2", "immu"},
- {"iatbtr0" , GROUP2 + 8, "org.gnu.gdb.or1k.group2", "immu"},
- {"iatbtr1" , GROUP2 + 9, "org.gnu.gdb.or1k.group2", "immu"},
- {"iatbtr2" , GROUP2 + 10, "org.gnu.gdb.or1k.group2", "immu"},
- {"iatbtr3" , GROUP2 + 11, "org.gnu.gdb.or1k.group2", "immu"},
-
- {"dccr" , GROUP3 + 0, "org.gnu.gdb.or1k.group3", "dcache"},
- {"dcbpr" , GROUP3 + 1, "org.gnu.gdb.or1k.group3", "dcache"},
- {"dcbfr" , GROUP3 + 2, "org.gnu.gdb.or1k.group3", "dcache"},
- {"dcbir" , GROUP3 + 3, "org.gnu.gdb.or1k.group3", "dcache"},
- {"dcbwr" , GROUP3 + 4, "org.gnu.gdb.or1k.group3", "dcache"},
- {"dcblr" , GROUP3 + 5, "org.gnu.gdb.or1k.group3", "dcache"},
-
- {"iccr" , GROUP4 + 0, "org.gnu.gdb.or1k.group4", "icache"},
- {"icbpr" , GROUP4 + 1, "org.gnu.gdb.or1k.group4", "icache"},
- {"icbir" , GROUP4 + 2, "org.gnu.gdb.or1k.group4", "icache"},
- {"icblr" , GROUP4 + 3, "org.gnu.gdb.or1k.group4", "icache"},
-
- {"maclo" , GROUP5 + 0, "org.gnu.gdb.or1k.group5", "mac"},
- {"machi" , GROUP5 + 1, "org.gnu.gdb.or1k.group5", "mac"},
-
- {"dvr0" , GROUP6 + 0, "org.gnu.gdb.or1k.group6", "debug"},
- {"dvr1" , GROUP6 + 1, "org.gnu.gdb.or1k.group6", "debug"},
- {"dvr2" , GROUP6 + 2, "org.gnu.gdb.or1k.group6", "debug"},
- {"dvr3" , GROUP6 + 3, "org.gnu.gdb.or1k.group6", "debug"},
- {"dvr4" , GROUP6 + 4, "org.gnu.gdb.or1k.group6", "debug"},
- {"dvr5" , GROUP6 + 5, "org.gnu.gdb.or1k.group6", "debug"},
- {"dvr6" , GROUP6 + 6, "org.gnu.gdb.or1k.group6", "debug"},
- {"dvr7" , GROUP6 + 7, "org.gnu.gdb.or1k.group6", "debug"},
- {"dcr0" , GROUP6 + 8, "org.gnu.gdb.or1k.group6", "debug"},
- {"dcr1" , GROUP6 + 9, "org.gnu.gdb.or1k.group6", "debug"},
- {"dcr2" , GROUP6 + 10, "org.gnu.gdb.or1k.group6", "debug"},
- {"dcr3" , GROUP6 + 11, "org.gnu.gdb.or1k.group6", "debug"},
- {"dcr4" , GROUP6 + 12, "org.gnu.gdb.or1k.group6", "debug"},
- {"dcr5" , GROUP6 + 13, "org.gnu.gdb.or1k.group6", "debug"},
- {"dcr6" , GROUP6 + 14, "org.gnu.gdb.or1k.group6", "debug"},
- {"dcr7" , GROUP6 + 15, "org.gnu.gdb.or1k.group6", "debug"},
- {"dmr1" , GROUP6 + 16, "org.gnu.gdb.or1k.group6", "debug"},
- {"dmr2" , GROUP6 + 17, "org.gnu.gdb.or1k.group6", "debug"},
- {"dcwr0" , GROUP6 + 18, "org.gnu.gdb.or1k.group6", "debug"},
- {"dcwr1" , GROUP6 + 19, "org.gnu.gdb.or1k.group6", "debug"},
- {"dsr" , GROUP6 + 20, "org.gnu.gdb.or1k.group6", "debug"},
- {"drr" , GROUP6 + 21, "org.gnu.gdb.or1k.group6", "debug"},
-
- {"pccr0" , GROUP7 + 0, "org.gnu.gdb.or1k.group7", "perf"},
- {"pccr1" , GROUP7 + 1, "org.gnu.gdb.or1k.group7", "perf"},
- {"pccr2" , GROUP7 + 2, "org.gnu.gdb.or1k.group7", "perf"},
- {"pccr3" , GROUP7 + 3, "org.gnu.gdb.or1k.group7", "perf"},
- {"pccr4" , GROUP7 + 4, "org.gnu.gdb.or1k.group7", "perf"},
- {"pccr5" , GROUP7 + 5, "org.gnu.gdb.or1k.group7", "perf"},
- {"pccr6" , GROUP7 + 6, "org.gnu.gdb.or1k.group7", "perf"},
- {"pccr7" , GROUP7 + 7, "org.gnu.gdb.or1k.group7", "perf"},
- {"pcmr0" , GROUP7 + 8, "org.gnu.gdb.or1k.group7", "perf"},
- {"pcmr1" , GROUP7 + 9, "org.gnu.gdb.or1k.group7", "perf"},
- {"pcmr2" , GROUP7 + 10, "org.gnu.gdb.or1k.group7", "perf"},
- {"pcmr3" , GROUP7 + 11, "org.gnu.gdb.or1k.group7", "perf"},
- {"pcmr4" , GROUP7 + 12, "org.gnu.gdb.or1k.group7", "perf"},
- {"pcmr5" , GROUP7 + 13, "org.gnu.gdb.or1k.group7", "perf"},
- {"pcmr6" , GROUP7 + 14, "org.gnu.gdb.or1k.group7", "perf"},
- {"pcmr7" , GROUP7 + 15, "org.gnu.gdb.or1k.group7", "perf"},
-
- {"pmr" , GROUP8 + 0, "org.gnu.gdb.or1k.group8", "power"},
-
- {"picmr" , GROUP9 + 0, "org.gnu.gdb.or1k.group9", "pic"},
- {"picsr" , GROUP9 + 2, "org.gnu.gdb.or1k.group9", "pic"},
-
- {"ttmr" , GROUP10 + 0, "org.gnu.gdb.or1k.group10", "timer"},
- {"ttcr" , GROUP10 + 1, "org.gnu.gdb.or1k.group10", "timer"},
+ {"r0", GROUP0 + 1024, "org.gnu.gdb.or1k.group0", NULL},
+ {"r1", GROUP0 + 1025, "org.gnu.gdb.or1k.group0", NULL},
+ {"r2", GROUP0 + 1026, "org.gnu.gdb.or1k.group0", NULL},
+ {"r3", GROUP0 + 1027, "org.gnu.gdb.or1k.group0", NULL},
+ {"r4", GROUP0 + 1028, "org.gnu.gdb.or1k.group0", NULL},
+ {"r5", GROUP0 + 1029, "org.gnu.gdb.or1k.group0", NULL},
+ {"r6", GROUP0 + 1030, "org.gnu.gdb.or1k.group0", NULL},
+ {"r7", GROUP0 + 1031, "org.gnu.gdb.or1k.group0", NULL},
+ {"r8", GROUP0 + 1032, "org.gnu.gdb.or1k.group0", NULL},
+ {"r9", GROUP0 + 1033, "org.gnu.gdb.or1k.group0", NULL},
+ {"r10", GROUP0 + 1034, "org.gnu.gdb.or1k.group0", NULL},
+ {"r11", GROUP0 + 1035, "org.gnu.gdb.or1k.group0", NULL},
+ {"r12", GROUP0 + 1036, "org.gnu.gdb.or1k.group0", NULL},
+ {"r13", GROUP0 + 1037, "org.gnu.gdb.or1k.group0", NULL},
+ {"r14", GROUP0 + 1038, "org.gnu.gdb.or1k.group0", NULL},
+ {"r15", GROUP0 + 1039, "org.gnu.gdb.or1k.group0", NULL},
+ {"r16", GROUP0 + 1040, "org.gnu.gdb.or1k.group0", NULL},
+ {"r17", GROUP0 + 1041, "org.gnu.gdb.or1k.group0", NULL},
+ {"r18", GROUP0 + 1042, "org.gnu.gdb.or1k.group0", NULL},
+ {"r19", GROUP0 + 1043, "org.gnu.gdb.or1k.group0", NULL},
+ {"r20", GROUP0 + 1044, "org.gnu.gdb.or1k.group0", NULL},
+ {"r21", GROUP0 + 1045, "org.gnu.gdb.or1k.group0", NULL},
+ {"r22", GROUP0 + 1046, "org.gnu.gdb.or1k.group0", NULL},
+ {"r23", GROUP0 + 1047, "org.gnu.gdb.or1k.group0", NULL},
+ {"r24", GROUP0 + 1048, "org.gnu.gdb.or1k.group0", NULL},
+ {"r25", GROUP0 + 1049, "org.gnu.gdb.or1k.group0", NULL},
+ {"r26", GROUP0 + 1050, "org.gnu.gdb.or1k.group0", NULL},
+ {"r27", GROUP0 + 1051, "org.gnu.gdb.or1k.group0", NULL},
+ {"r28", GROUP0 + 1052, "org.gnu.gdb.or1k.group0", NULL},
+ {"r29", GROUP0 + 1053, "org.gnu.gdb.or1k.group0", NULL},
+ {"r30", GROUP0 + 1054, "org.gnu.gdb.or1k.group0", NULL},
+ {"r31", GROUP0 + 1055, "org.gnu.gdb.or1k.group0", NULL},
+ {"ppc", GROUP0 + 18, "org.gnu.gdb.or1k.group0", NULL},
+ {"npc", GROUP0 + 16, "org.gnu.gdb.or1k.group0", NULL},
+ {"sr", GROUP0 + 17, "org.gnu.gdb.or1k.group0", NULL},
+ {"vr", GROUP0 + 0, "org.gnu.gdb.or1k.group0", "system"},
+ {"upr", GROUP0 + 1, "org.gnu.gdb.or1k.group0", "system"},
+ {"cpucfgr", GROUP0 + 2, "org.gnu.gdb.or1k.group0", "system"},
+ {"dmmucfgr", GROUP0 + 3, "org.gnu.gdb.or1k.group0", "system"},
+ {"immucfgr", GROUP0 + 4, "org.gnu.gdb.or1k.group0", "system"},
+ {"dccfgr", GROUP0 + 5, "org.gnu.gdb.or1k.group0", "system"},
+ {"iccfgr", GROUP0 + 6, "org.gnu.gdb.or1k.group0", "system"},
+ {"dcfgr", GROUP0 + 7, "org.gnu.gdb.or1k.group0", "system"},
+ {"pccfgr", GROUP0 + 8, "org.gnu.gdb.or1k.group0", "system"},
+ {"fpcsr", GROUP0 + 20, "org.gnu.gdb.or1k.group0", "system"},
+ {"epcr0", GROUP0 + 32, "org.gnu.gdb.or1k.group0", "system"},
+ {"epcr1", GROUP0 + 33, "org.gnu.gdb.or1k.group0", "system"},
+ {"epcr2", GROUP0 + 34, "org.gnu.gdb.or1k.group0", "system"},
+ {"epcr3", GROUP0 + 35, "org.gnu.gdb.or1k.group0", "system"},
+ {"epcr4", GROUP0 + 36, "org.gnu.gdb.or1k.group0", "system"},
+ {"epcr5", GROUP0 + 37, "org.gnu.gdb.or1k.group0", "system"},
+ {"epcr6", GROUP0 + 38, "org.gnu.gdb.or1k.group0", "system"},
+ {"epcr7", GROUP0 + 39, "org.gnu.gdb.or1k.group0", "system"},
+ {"epcr8", GROUP0 + 40, "org.gnu.gdb.or1k.group0", "system"},
+ {"epcr9", GROUP0 + 41, "org.gnu.gdb.or1k.group0", "system"},
+ {"epcr10", GROUP0 + 42, "org.gnu.gdb.or1k.group0", "system"},
+ {"epcr11", GROUP0 + 43, "org.gnu.gdb.or1k.group0", "system"},
+ {"epcr12", GROUP0 + 44, "org.gnu.gdb.or1k.group0", "system"},
+ {"epcr13", GROUP0 + 45, "org.gnu.gdb.or1k.group0", "system"},
+ {"epcr14", GROUP0 + 46, "org.gnu.gdb.or1k.group0", "system"},
+ {"epcr15", GROUP0 + 47, "org.gnu.gdb.or1k.group0", "system"},
+ {"eear0", GROUP0 + 48, "org.gnu.gdb.or1k.group0", "system"},
+ {"eear1", GROUP0 + 49, "org.gnu.gdb.or1k.group0", "system"},
+ {"eear2", GROUP0 + 50, "org.gnu.gdb.or1k.group0", "system"},
+ {"eear3", GROUP0 + 51, "org.gnu.gdb.or1k.group0", "system"},
+ {"eear4", GROUP0 + 52, "org.gnu.gdb.or1k.group0", "system"},
+ {"eear5", GROUP0 + 53, "org.gnu.gdb.or1k.group0", "system"},
+ {"eear6", GROUP0 + 54, "org.gnu.gdb.or1k.group0", "system"},
+ {"eear7", GROUP0 + 55, "org.gnu.gdb.or1k.group0", "system"},
+ {"eear8", GROUP0 + 56, "org.gnu.gdb.or1k.group0", "system"},
+ {"eear9", GROUP0 + 57, "org.gnu.gdb.or1k.group0", "system"},
+ {"eear10", GROUP0 + 58, "org.gnu.gdb.or1k.group0", "system"},
+ {"eear11", GROUP0 + 59, "org.gnu.gdb.or1k.group0", "system"},
+ {"eear12", GROUP0 + 60, "org.gnu.gdb.or1k.group0", "system"},
+ {"eear13", GROUP0 + 61, "org.gnu.gdb.or1k.group0", "system"},
+ {"eear14", GROUP0 + 62, "org.gnu.gdb.or1k.group0", "system"},
+ {"eear15", GROUP0 + 63, "org.gnu.gdb.or1k.group0", "system"},
+ {"esr0", GROUP0 + 64, "org.gnu.gdb.or1k.group0", "system"},
+ {"esr1", GROUP0 + 65, "org.gnu.gdb.or1k.group0", "system"},
+ {"esr2", GROUP0 + 66, "org.gnu.gdb.or1k.group0", "system"},
+ {"esr3", GROUP0 + 67, "org.gnu.gdb.or1k.group0", "system"},
+ {"esr4", GROUP0 + 68, "org.gnu.gdb.or1k.group0", "system"},
+ {"esr5", GROUP0 + 69, "org.gnu.gdb.or1k.group0", "system"},
+ {"esr6", GROUP0 + 70, "org.gnu.gdb.or1k.group0", "system"},
+ {"esr7", GROUP0 + 71, "org.gnu.gdb.or1k.group0", "system"},
+ {"esr8", GROUP0 + 72, "org.gnu.gdb.or1k.group0", "system"},
+ {"esr9", GROUP0 + 73, "org.gnu.gdb.or1k.group0", "system"},
+ {"esr10", GROUP0 + 74, "org.gnu.gdb.or1k.group0", "system"},
+ {"esr11", GROUP0 + 75, "org.gnu.gdb.or1k.group0", "system"},
+ {"esr12", GROUP0 + 76, "org.gnu.gdb.or1k.group0", "system"},
+ {"esr13", GROUP0 + 77, "org.gnu.gdb.or1k.group0", "system"},
+ {"esr14", GROUP0 + 78, "org.gnu.gdb.or1k.group0", "system"},
+ {"esr15", GROUP0 + 79, "org.gnu.gdb.or1k.group0", "system"},
+
+ {"dmmuucr", GROUP1 + 0, "org.gnu.gdb.or1k.group1", "dmmu"},
+ {"dmmuupr", GROUP1 + 1, "org.gnu.gdb.or1k.group1", "dmmu"},
+ {"dtlbeir", GROUP1 + 2, "org.gnu.gdb.or1k.group1", "dmmu"},
+ {"datbmr0", GROUP1 + 4, "org.gnu.gdb.or1k.group1", "dmmu"},
+ {"datbmr1", GROUP1 + 5, "org.gnu.gdb.or1k.group1", "dmmu"},
+ {"datbmr2", GROUP1 + 6, "org.gnu.gdb.or1k.group1", "dmmu"},
+ {"datbmr3", GROUP1 + 7, "org.gnu.gdb.or1k.group1", "dmmu"},
+ {"datbtr0", GROUP1 + 8, "org.gnu.gdb.or1k.group1", "dmmu"},
+ {"datbtr1", GROUP1 + 9, "org.gnu.gdb.or1k.group1", "dmmu"},
+ {"datbtr2", GROUP1 + 10, "org.gnu.gdb.or1k.group1", "dmmu"},
+ {"datbtr3", GROUP1 + 11, "org.gnu.gdb.or1k.group1", "dmmu"},
+
+ {"immucr", GROUP2 + 0, "org.gnu.gdb.or1k.group2", "immu"},
+ {"immupr", GROUP2 + 1, "org.gnu.gdb.or1k.group2", "immu"},
+ {"itlbeir", GROUP2 + 2, "org.gnu.gdb.or1k.group2", "immu"},
+ {"iatbmr0", GROUP2 + 4, "org.gnu.gdb.or1k.group2", "immu"},
+ {"iatbmr1", GROUP2 + 5, "org.gnu.gdb.or1k.group2", "immu"},
+ {"iatbmr2", GROUP2 + 6, "org.gnu.gdb.or1k.group2", "immu"},
+ {"iatbmr3", GROUP2 + 7, "org.gnu.gdb.or1k.group2", "immu"},
+ {"iatbtr0", GROUP2 + 8, "org.gnu.gdb.or1k.group2", "immu"},
+ {"iatbtr1", GROUP2 + 9, "org.gnu.gdb.or1k.group2", "immu"},
+ {"iatbtr2", GROUP2 + 10, "org.gnu.gdb.or1k.group2", "immu"},
+ {"iatbtr3", GROUP2 + 11, "org.gnu.gdb.or1k.group2", "immu"},
+
+ {"dccr", GROUP3 + 0, "org.gnu.gdb.or1k.group3", "dcache"},
+ {"dcbpr", GROUP3 + 1, "org.gnu.gdb.or1k.group3", "dcache"},
+ {"dcbfr", GROUP3 + 2, "org.gnu.gdb.or1k.group3", "dcache"},
+ {"dcbir", GROUP3 + 3, "org.gnu.gdb.or1k.group3", "dcache"},
+ {"dcbwr", GROUP3 + 4, "org.gnu.gdb.or1k.group3", "dcache"},
+ {"dcblr", GROUP3 + 5, "org.gnu.gdb.or1k.group3", "dcache"},
+
+ {"iccr", GROUP4 + 0, "org.gnu.gdb.or1k.group4", "icache"},
+ {"icbpr", GROUP4 + 1, "org.gnu.gdb.or1k.group4", "icache"},
+ {"icbir", GROUP4 + 2, "org.gnu.gdb.or1k.group4", "icache"},
+ {"icblr", GROUP4 + 3, "org.gnu.gdb.or1k.group4", "icache"},
+
+ {"maclo", GROUP5 + 0, "org.gnu.gdb.or1k.group5", "mac"},
+ {"machi", GROUP5 + 1, "org.gnu.gdb.or1k.group5", "mac"},
+
+ {"dvr0", GROUP6 + 0, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dvr1", GROUP6 + 1, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dvr2", GROUP6 + 2, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dvr3", GROUP6 + 3, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dvr4", GROUP6 + 4, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dvr5", GROUP6 + 5, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dvr6", GROUP6 + 6, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dvr7", GROUP6 + 7, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dcr0", GROUP6 + 8, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dcr1", GROUP6 + 9, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dcr2", GROUP6 + 10, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dcr3", GROUP6 + 11, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dcr4", GROUP6 + 12, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dcr5", GROUP6 + 13, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dcr6", GROUP6 + 14, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dcr7", GROUP6 + 15, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dmr1", GROUP6 + 16, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dmr2", GROUP6 + 17, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dcwr0", GROUP6 + 18, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dcwr1", GROUP6 + 19, "org.gnu.gdb.or1k.group6", "debug"},
+ {"dsr", GROUP6 + 20, "org.gnu.gdb.or1k.group6", "debug"},
+ {"drr", GROUP6 + 21, "org.gnu.gdb.or1k.group6", "debug"},
+
+ {"pccr0", GROUP7 + 0, "org.gnu.gdb.or1k.group7", "perf"},
+ {"pccr1", GROUP7 + 1, "org.gnu.gdb.or1k.group7", "perf"},
+ {"pccr2", GROUP7 + 2, "org.gnu.gdb.or1k.group7", "perf"},
+ {"pccr3", GROUP7 + 3, "org.gnu.gdb.or1k.group7", "perf"},
+ {"pccr4", GROUP7 + 4, "org.gnu.gdb.or1k.group7", "perf"},
+ {"pccr5", GROUP7 + 5, "org.gnu.gdb.or1k.group7", "perf"},
+ {"pccr6", GROUP7 + 6, "org.gnu.gdb.or1k.group7", "perf"},
+ {"pccr7", GROUP7 + 7, "org.gnu.gdb.or1k.group7", "perf"},
+ {"pcmr0", GROUP7 + 8, "org.gnu.gdb.or1k.group7", "perf"},
+ {"pcmr1", GROUP7 + 9, "org.gnu.gdb.or1k.group7", "perf"},
+ {"pcmr2", GROUP7 + 10, "org.gnu.gdb.or1k.group7", "perf"},
+ {"pcmr3", GROUP7 + 11, "org.gnu.gdb.or1k.group7", "perf"},
+ {"pcmr4", GROUP7 + 12, "org.gnu.gdb.or1k.group7", "perf"},
+ {"pcmr5", GROUP7 + 13, "org.gnu.gdb.or1k.group7", "perf"},
+ {"pcmr6", GROUP7 + 14, "org.gnu.gdb.or1k.group7", "perf"},
+ {"pcmr7", GROUP7 + 15, "org.gnu.gdb.or1k.group7", "perf"},
+
+ {"pmr", GROUP8 + 0, "org.gnu.gdb.or1k.group8", "power"},
+
+ {"picmr", GROUP9 + 0, "org.gnu.gdb.or1k.group9", "pic"},
+ {"picsr", GROUP9 + 2, "org.gnu.gdb.or1k.group9", "pic"},
+
+ {"ttmr", GROUP10 + 0, "org.gnu.gdb.or1k.group10", "timer"},
+ {"ttcr", GROUP10 + 1, "org.gnu.gdb.or1k.group10", "timer"},
};
static int or1k_add_reg(struct target *target, struct or1k_core_reg *new_reg)
@@ -423,7 +423,7 @@ static int or1k_read_core_reg(struct target *target, int num)
if ((num >= 0) && (num < OR1KNUMCOREREGS)) {
reg_value = or1k->core_regs[num];
buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
- LOG_DEBUG("Read core reg %i value 0x%08" PRIx32, num , reg_value);
+ LOG_DEBUG("Read core reg %i value 0x%08" PRIx32, num, reg_value);
or1k->core_cache->reg_list[num].valid = true;
or1k->core_cache->reg_list[num].dirty = false;
} else {
@@ -435,7 +435,7 @@ static int or1k_read_core_reg(struct target *target, int num)
return retval;
}
buf_set_u32(or1k->core_cache->reg_list[num].value, 0, 32, reg_value);
- LOG_DEBUG("Read spr reg %i value 0x%08" PRIx32, num , reg_value);
+ LOG_DEBUG("Read spr reg %i value 0x%08" PRIx32, num, reg_value);
}
return ERROR_OK;
@@ -452,7 +452,7 @@ static int or1k_write_core_reg(struct target *target, int num)
uint32_t reg_value = buf_get_u32(or1k->core_cache->reg_list[num].value, 0, 32);
or1k->core_regs[num] = reg_value;
- LOG_DEBUG("Write core reg %i value 0x%08" PRIx32, num , reg_value);
+ LOG_DEBUG("Write core reg %i value 0x%08" PRIx32, num, reg_value);
or1k->core_cache->reg_list[num].valid = true;
or1k->core_cache->reg_list[num].dirty = false;
diff --git a/src/target/stm8.c b/src/target/stm8.c
index ce8cfaa51..ee3bb31a9 100644
--- a/src/target/stm8.c
+++ b/src/target/stm8.c
@@ -1143,7 +1143,7 @@ static int stm8_read_core_reg(struct target *target, unsigned int num)
return ERROR_COMMAND_SYNTAX_ERROR;
reg_value = stm8->core_regs[num];
- LOG_DEBUG("read core reg %i value 0x%" PRIx32 "", num , reg_value);
+ LOG_DEBUG("read core reg %i value 0x%" PRIx32 "", num, reg_value);
buf_set_u32(stm8->core_cache->reg_list[num].value, 0, 32, reg_value);
stm8->core_cache->reg_list[num].valid = true;
stm8->core_cache->reg_list[num].dirty = false;
@@ -1163,7 +1163,7 @@ static int stm8_write_core_reg(struct target *target, unsigned int num)
reg_value = buf_get_u32(stm8->core_cache->reg_list[num].value, 0, 32);
stm8->core_regs[num] = reg_value;
- LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
+ LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
stm8->core_cache->reg_list[num].valid = true;
stm8->core_cache->reg_list[num].dirty = false;
diff --git a/src/target/target.c b/src/target/target.c
index 2ea1e206c..8c0fd496e 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -176,10 +176,10 @@ static const Jim_Nvp nvp_error_target[] = {
{ .value = ERROR_TARGET_TIMEOUT, .name = "err-timeout" },
{ .value = ERROR_TARGET_NOT_HALTED, .name = "err-not-halted" },
{ .value = ERROR_TARGET_FAILURE, .name = "err-failure" },
- { .value = ERROR_TARGET_UNALIGNED_ACCESS , .name = "err-unaligned-access" },
- { .value = ERROR_TARGET_DATA_ABORT , .name = "err-data-abort" },
- { .value = ERROR_TARGET_RESOURCE_NOT_AVAILABLE , .name = "err-resource-not-available" },
- { .value = ERROR_TARGET_TRANSLATION_FAULT , .name = "err-translation-fault" },
+ { .value = ERROR_TARGET_UNALIGNED_ACCESS, .name = "err-unaligned-access" },
+ { .value = ERROR_TARGET_DATA_ABORT, .name = "err-data-abort" },
+ { .value = ERROR_TARGET_RESOURCE_NOT_AVAILABLE, .name = "err-resource-not-available" },
+ { .value = ERROR_TARGET_TRANSLATION_FAULT, .name = "err-translation-fault" },
{ .value = ERROR_TARGET_NOT_RUNNING, .name = "err-not-running" },
{ .value = ERROR_TARGET_NOT_EXAMINED, .name = "err-not-examined" },
{ .value = -1, .name = NULL }
@@ -229,10 +229,10 @@ static const Jim_Nvp nvp_target_event[] = {
{ .value = TARGET_EVENT_GDB_DETACH, .name = "gdb-detach" },
{ .value = TARGET_EVENT_GDB_FLASH_WRITE_START, .name = "gdb-flash-write-start" },
- { .value = TARGET_EVENT_GDB_FLASH_WRITE_END , .name = "gdb-flash-write-end" },
+ { .value = TARGET_EVENT_GDB_FLASH_WRITE_END, .name = "gdb-flash-write-end" },
{ .value = TARGET_EVENT_GDB_FLASH_ERASE_START, .name = "gdb-flash-erase-start" },
- { .value = TARGET_EVENT_GDB_FLASH_ERASE_END , .name = "gdb-flash-erase-end" },
+ { .value = TARGET_EVENT_GDB_FLASH_ERASE_END, .name = "gdb-flash-erase-end" },
{ .value = TARGET_EVENT_TRACE_CONFIG, .name = "trace-config" },
@@ -249,15 +249,15 @@ static const Jim_Nvp nvp_target_state[] = {
};
static const Jim_Nvp nvp_target_debug_reason[] = {
- { .name = "debug-request" , .value = DBG_REASON_DBGRQ },
- { .name = "breakpoint" , .value = DBG_REASON_BREAKPOINT },
- { .name = "watchpoint" , .value = DBG_REASON_WATCHPOINT },
+ { .name = "debug-request", .value = DBG_REASON_DBGRQ },
+ { .name = "breakpoint", .value = DBG_REASON_BREAKPOINT },
+ { .name = "watchpoint", .value = DBG_REASON_WATCHPOINT },
{ .name = "watchpoint-and-breakpoint", .value = DBG_REASON_WPTANDBKPT },
- { .name = "single-step" , .value = DBG_REASON_SINGLESTEP },
- { .name = "target-not-halted" , .value = DBG_REASON_NOTHALTED },
- { .name = "program-exit" , .value = DBG_REASON_EXIT },
- { .name = "exception-catch" , .value = DBG_REASON_EXC_CATCH },
- { .name = "undefined" , .value = DBG_REASON_UNDEFINED },
+ { .name = "single-step", .value = DBG_REASON_SINGLESTEP },
+ { .name = "target-not-halted", .value = DBG_REASON_NOTHALTED },
+ { .name = "program-exit", .value = DBG_REASON_EXIT },
+ { .name = "exception-catch", .value = DBG_REASON_EXC_CATCH },
+ { .name = "undefined", .value = DBG_REASON_UNDEFINED },
{ .name = NULL, .value = -1 },
};
@@ -271,10 +271,10 @@ static const Jim_Nvp nvp_target_endian[] = {
static const Jim_Nvp nvp_reset_modes[] = {
{ .name = "unknown", .value = RESET_UNKNOWN },
- { .name = "run" , .value = RESET_RUN },
- { .name = "halt" , .value = RESET_HALT },
- { .name = "init" , .value = RESET_INIT },
- { .name = NULL , .value = -1 },
+ { .name = "run", .value = RESET_RUN },
+ { .name = "halt", .value = RESET_HALT },
+ { .name = "init", .value = RESET_INIT },
+ { .name = NULL, .value = -1 },
};
const char *debug_reason_name(struct target *t)
@@ -2892,7 +2892,7 @@ COMMAND_HANDLER(handle_reg_command)
} else {
command_print(CMD, "(%i) %s (/%" PRIu32 ")",
count, reg->name,
- reg->size) ;
+ reg->size);
}
}
cache = cache->next;
@@ -4643,7 +4643,7 @@ static Jim_Nvp nvp_config_opts[] = {
{ .name = "-work-area-phys", .value = TCFG_WORK_AREA_PHYS },
{ .name = "-work-area-size", .value = TCFG_WORK_AREA_SIZE },
{ .name = "-work-area-backup", .value = TCFG_WORK_AREA_BACKUP },
- { .name = "-endian" , .value = TCFG_ENDIAN },
+ { .name = "-endian", .value = TCFG_ENDIAN },
{ .name = "-coreid", .value = TCFG_COREID },
{ .name = "-chain-position", .value = TCFG_CHAIN_POSITION },
{ .name = "-dbgbase", .value = TCFG_DBGBASE },
commit bf346292942868db6ed8a71e2c4c8b8359d6d300
Author: Antonio Borneo <bor...@gm...>
Date: Mon May 6 14:22:06 2019 +0200
coding style: fix print of hex values as decimal
It is an error to prefix with "0x" the print of values in decimal.
Replace the incorrect decimal format specifier with PRIx32.
Issue identified by checkpatch script from Linux kernel v5.1 using
the command
find src/ -type f -exec ./tools/scripts/checkpatch.pl \
-q --types PRINTF_0XDECIMAL -f {} \;
Change-Id: I2eb867ef654527b2737ba573a405ec8f97c6a739
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5624
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <and...@gm...>
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/flash/nor/pic32mx.c b/src/flash/nor/pic32mx.c
index 99b841991..b214642a0 100644
--- a/src/flash/nor/pic32mx.c
+++ b/src/flash/nor/pic32mx.c
@@ -817,7 +817,7 @@ static int pic32mx_info(struct flash_bank *bank, char *buf, int buf_size)
if (((device_id >> 1) & 0x7ff) != PIC32MX_MANUF_ID) {
snprintf(buf, buf_size,
- "Cannot identify target as a PIC32MX family (manufacturer 0x%03d != 0x%03d)\n",
+ "Cannot identify target as a PIC32MX family (manufacturer 0x%03x != 0x%03x)\n",
(unsigned)((device_id >> 1) & 0x7ff),
PIC32MX_MANUF_ID);
return ERROR_FLASH_OPERATION_FAILED;
diff --git a/src/target/image.c b/src/target/image.c
index 9bd8f6b0c..1003c3bdc 100644
--- a/src/target/image.c
+++ b/src/target/image.c
@@ -497,7 +497,7 @@ static int image_elf_read_section(struct image *image,
if (offset < field32(elf, segment->p_filesz)) {
/* maximal size present in file for the current segment */
read_size = MIN(size, field32(elf, segment->p_filesz) - offset);
- LOG_DEBUG("read elf: size = 0x%zu at 0x%" PRIx32 "", read_size,
+ LOG_DEBUG("read elf: size = 0x%zx at 0x%" PRIx32 "", read_size,
field32(elf, segment->p_offset) + offset);
/* read initialized area of the segment */
retval = fileio_seek(elf->fileio, field32(elf, segment->p_offset) + offset);
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/at91sam3.c | 2 +-
src/flash/nor/fespi.c | 6 +-
src/flash/nor/lpcspifi.c | 4 +-
src/flash/nor/niietcm4.c | 2 +-
src/flash/nor/pic32mx.c | 2 +-
src/jtag/drivers/opendous.c | 2 +-
src/jtag/hla/hla_layout.h | 38 ++---
src/jtag/jtag.h | 2 +-
src/jtag/zy1000/zy1000.c | 6 +-
src/rtos/rtos_mqx_stackings.c | 2 +-
src/server/server.h | 2 +-
src/svf/svf.c | 4 +-
src/target/arc.c | 4 +-
src/target/arm_dpm.h | 32 ++--
src/target/armv8.c | 34 ++--
src/target/armv8_dpm.h | 6 +-
src/target/dsp563xx.h | 4 +-
src/target/image.c | 2 +-
src/target/mips32.c | 2 +-
src/target/mips64.c | 2 +-
src/target/nds32.c | 8 +-
src/target/openrisc/or1k.c | 366 +++++++++++++++++++++---------------------
src/target/riscv/riscv.h | 6 +-
src/target/stm8.c | 4 +-
src/target/target.c | 40 ++---
25 files changed, 291 insertions(+), 291 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2020-07-08 21:08:20
|
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generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via f29d157882a756e562d224dd128eea1bbe3e3813 (commit)
via 6a81bad3b973e54ce68496d22750d643741afb32 (commit)
from 327d18220ffb005884a742992657b6b5a4be2232 (commit)
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- Log -----------------------------------------------------------------
commit f29d157882a756e562d224dd128eea1bbe3e3813
Author: Antonio Borneo <bor...@gm...>
Date: Sun Jun 14 23:18:21 2020 +0200
target/arm926ejs: fix memory leaks
The memory leaks detected and fixed are:
- arm register cache;
- EmbeddedICE register cache;
- arm_jtag_reset_callback internal data;
- struct arm926ejs_common.
Issue identified with valgrind.
Tested on SPEAr320 based on arm926ejs.
Change-Id: If2bed02c516051ce4d0eb29b204a3f3337fe5d6a
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5698
Tested-by: jenkins
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 6a7bf9da5..28fefc5aa 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2682,6 +2682,15 @@ int arm7_9_examine(struct target *target)
return retval;
}
+void arm7_9_deinit(struct target *target)
+{
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+
+ if (target_was_examined(target))
+ embeddedice_free_reg_cache(arm7_9->eice_cache);
+
+ arm_jtag_close_connection(&arm7_9->jtag_info);
+}
int arm7_9_check_reset(struct target *target)
{
diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h
index 811f9c593..4961212bb 100644
--- a/src/target/arm7_9_common.h
+++ b/src/target/arm7_9_common.h
@@ -186,6 +186,7 @@ int arm7_9_execute_sys_speed(struct target *target);
int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9);
int arm7_9_examine(struct target *target);
+void arm7_9_deinit(struct target *target);
int arm7_9_check_reset(struct target *target);
int arm7_9_endianness_callback(jtag_callback_data_t pu8_in,
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index ac30485b8..95a4f7ca0 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -723,6 +723,16 @@ static int arm926ejs_target_create(struct target *target, Jim_Interp *interp)
return arm926ejs_init_arch_info(target, arm926ejs, target->tap);
}
+void arm926ejs_deinit_target(struct target *target)
+{
+ struct arm *arm = target_to_arm(target);
+ struct arm926ejs_common *arm926ejs = target_to_arm926(target);
+
+ arm7_9_deinit(target);
+ arm_free_reg_cache(arm);
+ free(arm926ejs);
+}
+
COMMAND_HANDLER(arm926ejs_handle_cache_info_command)
{
int retval;
@@ -823,6 +833,7 @@ struct target_type arm926ejs_target = {
.commands = arm926ejs_command_handlers,
.target_create = arm926ejs_target_create,
.init_target = arm9tdmi_init_target,
+ .deinit_target = arm926ejs_deinit_target,
.examine = arm7_9_examine,
.check_reset = arm7_9_check_reset,
.virt2phys = arm926ejs_virt2phys,
diff --git a/src/target/arm_jtag.c b/src/target/arm_jtag.c
index 49aca3487..f9605acb1 100644
--- a/src/target/arm_jtag.c
+++ b/src/target/arm_jtag.c
@@ -92,3 +92,8 @@ int arm_jtag_setup_connection(struct arm_jtag *jtag_info)
return jtag_register_event_callback(arm_jtag_reset_callback, jtag_info);
}
+
+int arm_jtag_close_connection(struct arm_jtag *jtag_info)
+{
+ return jtag_unregister_event_callback(arm_jtag_reset_callback, jtag_info);
+}
diff --git a/src/target/arm_jtag.h b/src/target/arm_jtag.h
index bb92abb84..bf5b83748 100644
--- a/src/target/arm_jtag.h
+++ b/src/target/arm_jtag.h
@@ -61,6 +61,7 @@ static inline int arm_jtag_scann(struct arm_jtag *jtag_info, uint32_t new_scan_c
}
int arm_jtag_setup_connection(struct arm_jtag *jtag_info);
+int arm_jtag_close_connection(struct arm_jtag *jtag_info);
/* use this as a static so we can inline it in -O3 and refer to it via a pointer */
static inline void arm7flip32(jtag_callback_data_t arg)
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 61ee8bbd9..7c53c45c5 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -303,6 +303,22 @@ struct reg_cache *embeddedice_build_reg_cache(struct target *target,
return reg_cache;
}
+/**
+ * Free all memory allocated for EmbeddedICE register cache
+ */
+void embeddedice_free_reg_cache(struct reg_cache *reg_cache)
+{
+ if (!reg_cache)
+ return;
+
+ for (unsigned int i = 0; i < reg_cache->num_regs; i++)
+ free(reg_cache->reg_list[i].value);
+
+ free(reg_cache->reg_list[0].arch_info);
+ free(reg_cache->reg_list);
+ free(reg_cache);
+}
+
/**
* Initialize EmbeddedICE module, if needed.
*/
diff --git a/src/target/embeddedice.h b/src/target/embeddedice.h
index 39902fb3e..4b5c816a6 100644
--- a/src/target/embeddedice.h
+++ b/src/target/embeddedice.h
@@ -88,6 +88,7 @@ struct embeddedice_reg {
struct reg_cache *embeddedice_build_reg_cache(struct target *target,
struct arm7_9_common *arm7_9);
+void embeddedice_free_reg_cache(struct reg_cache *reg_cache);
int embeddedice_setup(struct target *target);
commit 6a81bad3b973e54ce68496d22750d643741afb32
Author: Antonio Borneo <bor...@gm...>
Date: Wed Jun 10 16:08:41 2020 +0200
configure: split build of hla layouts
Current hla driver supports two "layout": stlink and ti-icdi.
The configure script allows to independently enable/disable the
the two layout. But in reality by selecting only one of them the
whole hla driver is built, including both "layouts".
This is currently not a big issue because the dependencies of the
two layout are the same (libusb), so we are sure that selecting
one of them would permit to build both.
This is going to change with the merge of a third "layout" for
Nuvoton Nu-Link, because it would be based on hidapi.
We need, at least, to decouple the build of libusb and hidapi
"layouts". A full decouple of each "layout" is also welcome to
match the selection done during configure.
Introduce a new automake macro for each of the two "layout" and
use them to conditionally build the "layout" files.
Use the existing autoconf macros to conditionally compile the code
that depends by the "layout".
Change-Id: Ia20da7a260002a8d2af883425aa401b8920d3f36
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: http://openocd.zylin.com/5719
Tested-by: jenkins
diff --git a/configure.ac b/configure.ac
index a6bda8856..382a00b6e 100644
--- a/configure.ac
+++ b/configure.ac
@@ -683,10 +683,13 @@ AS_IF([test "x$build_openjtag" = "xyes"], [
AS_IF([test "x$enable_stlink" != "xno" -o "x$enable_ti_icdi" != "xno"], [
AC_DEFINE([BUILD_HLADAPTER], [1], [1 if you want the High Level JTAG driver.])
+ AM_CONDITIONAL([HLADAPTER], [true])
], [
AC_DEFINE([BUILD_HLADAPTER], [0], [0 if you want the High Level JTAG driver.])
+ AM_CONDITIONAL([HLADAPTER], [false])
])
-AM_CONDITIONAL([HLADAPTER], [test "x$enable_stlink" != "xno" -o "x$enable_ti_icdi" != "xno"])
+AM_CONDITIONAL([HLADAPTER_STLINK], [test "x$enable_stlink" != "xno"])
+AM_CONDITIONAL([HLADAPTER_ICDI], [test "x$enable_ti_icdi" != "xno"])
AS_IF([test "x$enable_jlink" != "xno"], [
AS_IF([test "x$use_internal_libjaylink" = "xyes"], [
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index 07824f678..b03f560b3 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -129,8 +129,10 @@ endif
if REMOTE_BITBANG
DRIVERFILES += %D%/remote_bitbang.c
endif
-if HLADAPTER
+if HLADAPTER_STLINK
DRIVERFILES += %D%/stlink_usb.c
+endif
+if HLADAPTER_ICDI
DRIVERFILES += %D%/ti_icdi_usb.c
endif
if RSHIM
diff --git a/src/jtag/hla/hla_layout.c b/src/jtag/hla/hla_layout.c
index c5e35182d..686e6f5b2 100644
--- a/src/jtag/hla/hla_layout.c
+++ b/src/jtag/hla/hla_layout.c
@@ -57,18 +57,22 @@ static int hl_layout_close(struct hl_interface_s *adapter)
}
static const struct hl_layout hl_layouts[] = {
+#if BUILD_HLADAPTER_STLINK
{
.name = "stlink",
.open = hl_layout_open,
.close = hl_layout_close,
.api = &stlink_usb_layout_api,
},
+#endif
+#if BUILD_HLADAPTER_ICDI
{
.name = "ti-icdi",
.open = hl_layout_open,
.close = hl_layout_close,
.api = &icdi_usb_layout_api,
},
+#endif
{.name = NULL, /* END OF TABLE */ },
};
diff --git a/src/jtag/interfaces.c b/src/jtag/interfaces.c
index 7d3f8a8ca..87ea95822 100644
--- a/src/jtag/interfaces.c
+++ b/src/jtag/interfaces.c
@@ -138,7 +138,7 @@ extern struct adapter_driver imx_gpio_adapter_driver;
#if BUILD_XDS110 == 1
extern struct adapter_driver xds110_adapter_driver;
#endif
-#if BUILD_HLADAPTER == 1
+#if BUILD_HLADAPTER_STLINK == 1
extern struct adapter_driver stlink_dap_adapter_driver;
#endif
#if BUILD_RSHIM == 1
@@ -252,7 +252,7 @@ struct adapter_driver *adapter_drivers[] = {
#if BUILD_XDS110 == 1
&xds110_adapter_driver,
#endif
-#if BUILD_HLADAPTER == 1
+#if BUILD_HLADAPTER_STLINK == 1
&stlink_dap_adapter_driver,
#endif
#if BUILD_RSHIM == 1
-----------------------------------------------------------------------
Summary of changes:
configure.ac | 5 ++++-
src/jtag/drivers/Makefile.am | 4 +++-
src/jtag/hla/hla_layout.c | 4 ++++
src/jtag/interfaces.c | 4 ++--
src/target/arm7_9_common.c | 9 +++++++++
src/target/arm7_9_common.h | 1 +
src/target/arm926ejs.c | 11 +++++++++++
src/target/arm_jtag.c | 5 +++++
src/target/arm_jtag.h | 1 +
src/target/embeddedice.c | 16 ++++++++++++++++
src/target/embeddedice.h | 1 +
11 files changed, 57 insertions(+), 4 deletions(-)
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|
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- Log -----------------------------------------------------------------
commit 327d18220ffb005884a742992657b6b5a4be2232
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:27:19 2020 +0200
flash/nor/w600: Use 'bool' data type
Change-Id: Ia71ffba82b23ed1860acc5daf6c66fa574a0d797
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5751
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/w600.c b/src/flash/nor/w600.c
index ce3bc6e99..714b27db2 100644
--- a/src/flash/nor/w600.c
+++ b/src/flash/nor/w600.c
@@ -87,7 +87,7 @@ static const struct w600_flash_param w600_param[] = {
};
struct w600_flash_bank {
- int probed;
+ bool probed;
uint32_t id;
const struct w600_flash_param *param;
@@ -107,7 +107,7 @@ FLASH_BANK_COMMAND_HANDLER(w600_flash_bank_command)
w600_info = malloc(sizeof(struct w600_flash_bank));
bank->driver_priv = w600_info;
- w600_info->probed = 0;
+ w600_info->probed = false;
w600_info->register_base = QFLASH_REGBASE;
w600_info->user_bank_size = bank->size;
@@ -287,7 +287,7 @@ static int w600_probe(struct flash_bank *bank)
uint32_t flash_id;
size_t i;
- w600_info->probed = 0;
+ w600_info->probed = false;
/* read stm32 device id register */
int retval = w600_get_flash_id(bank, &flash_id);
@@ -351,7 +351,7 @@ static int w600_probe(struct flash_bank *bank)
bank->sectors[i].is_protected = (i < W600_FLASH_PROTECT_SIZE / W600_FLASH_SECSIZE);
}
- w600_info->probed = 1;
+ w600_info->probed = true;
return ERROR_OK;
}
commit 86131594d4fb10efdc4032f49838335f900c44ab
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:27:11 2020 +0200
flash/nor/stmsmi: Use 'bool' data type
Change-Id: I0b9d3eb6fa40cc9fed6491c8f583580fb471bcac
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5750
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/stmsmi.c b/src/flash/nor/stmsmi.c
index e63401e33..278c73e7f 100644
--- a/src/flash/nor/stmsmi.c
+++ b/src/flash/nor/stmsmi.c
@@ -115,7 +115,7 @@
#define SMI_MAX_TIMEOUT (3000)
struct stmsmi_flash_bank {
- int probed;
+ bool probed;
uint32_t io_base;
uint32_t bank_num;
const struct flash_device *dev;
@@ -151,7 +151,7 @@ FLASH_BANK_COMMAND_HANDLER(stmsmi_flash_bank_command)
}
bank->driver_priv = stmsmi_info;
- stmsmi_info->probed = 0;
+ stmsmi_info->probed = false;
return ERROR_OK;
}
@@ -531,7 +531,7 @@ static int stmsmi_probe(struct flash_bank *bank)
if (stmsmi_info->probed)
free(bank->sectors);
- stmsmi_info->probed = 0;
+ stmsmi_info->probed = false;
for (target_device = target_devices ; target_device->name ; ++target_device)
if (target_device->tap_idcode == target->tap->idcode)
@@ -614,7 +614,7 @@ static int stmsmi_probe(struct flash_bank *bank)
}
bank->sectors = sectors;
- stmsmi_info->probed = 1;
+ stmsmi_info->probed = true;
return ERROR_OK;
}
commit 707291cf38175f01bfa6464ff8a7295e252d1f82
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:26:57 2020 +0200
flash/nor/stm32h7x: Use 'bool' data type
Change-Id: Ib9c567e2287f2a99172bd3bd35a81e3205cea421
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5749
Tested-by: jenkins
Reviewed-by: Christopher Head <ch...@za...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c
index 26def3f00..72bfa5f5e 100644
--- a/src/flash/nor/stm32h7x.c
+++ b/src/flash/nor/stm32h7x.c
@@ -882,7 +882,7 @@ static int stm32x_probe(struct flash_bank *bank)
return ERROR_FAIL;
}
- stm32x_info->probed = 1;
+ stm32x_info->probed = true;
return ERROR_OK;
}
commit 4acd965573728faa8f564514f2cb76a9db5fbc01
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:26:32 2020 +0200
flash/nor/sh_qspi: Use 'bool' data type
Change-Id: Id5567102013648b1565078310abc27bee4446992
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5748
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/sh_qspi.c b/src/flash/nor/sh_qspi.c
index e6c9be4b4..1ba975339 100644
--- a/src/flash/nor/sh_qspi.c
+++ b/src/flash/nor/sh_qspi.c
@@ -77,7 +77,7 @@
struct sh_qspi_flash_bank {
const struct flash_device *dev;
uint32_t io_base;
- int probed;
+ bool probed;
struct working_area *io_algorithm;
struct working_area *source;
unsigned int buffer_size;
@@ -755,7 +755,7 @@ static int sh_qspi_probe(struct flash_bank *bank)
if (info->probed)
free(bank->sectors);
- info->probed = 0;
+ info->probed = false;
for (target_device = target_devices; target_device->name;
++target_device)
@@ -825,7 +825,7 @@ static int sh_qspi_probe(struct flash_bank *bank)
}
bank->sectors = sectors;
- info->probed = 1;
+ info->probed = true;
return ERROR_OK;
}
commit 37196876f622d6180066f5d167061bb592b2932c
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:26:12 2020 +0200
flash/nor/pic32mx: Use 'bool' data type
Change-Id: I9a0b60bc07781401f26df31303b8c04822b7ddc2
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5747
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/pic32mx.c b/src/flash/nor/pic32mx.c
index 570a2cfb2..99b841991 100644
--- a/src/flash/nor/pic32mx.c
+++ b/src/flash/nor/pic32mx.c
@@ -95,7 +95,7 @@
#define MX_17x_27x 2 /* PIC32mx17x/27x */
struct pic32mx_flash_bank {
- int probed;
+ bool probed;
int dev_type; /* Default 0. 1 for Pic32MX1XX/2XX variant */
};
@@ -211,7 +211,7 @@ FLASH_BANK_COMMAND_HANDLER(pic32mx_flash_bank_command)
pic32mx_info = malloc(sizeof(struct pic32mx_flash_bank));
bank->driver_priv = pic32mx_info;
- pic32mx_info->probed = 0;
+ pic32mx_info->probed = false;
pic32mx_info->dev_type = 0;
return ERROR_OK;
@@ -700,7 +700,7 @@ static int pic32mx_probe(struct flash_bank *bank)
uint32_t device_id;
int page_size;
- pic32mx_info->probed = 0;
+ pic32mx_info->probed = false;
device_id = ejtag_info->idcode;
LOG_INFO("device id = 0x%08" PRIx32 " (manuf 0x%03x dev 0x%04x, ver 0x%02x)",
@@ -792,7 +792,7 @@ static int pic32mx_probe(struct flash_bank *bank)
bank->sectors[i].is_protected = 1;
}
- pic32mx_info->probed = 1;
+ pic32mx_info->probed = true;
return ERROR_OK;
}
commit ad8e1507eba8891c36e97e081e43e639642436ef
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:25:45 2020 +0200
flash/nor/mrvlqspi: Use 'bool' data type
Change-Id: Icc64d9ba56841ff6eb96efcbdc9545938ebb7347
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5746
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/mrvlqspi.c b/src/flash/nor/mrvlqspi.c
index 57461be18..f21cc6ff0 100644
--- a/src/flash/nor/mrvlqspi.c
+++ b/src/flash/nor/mrvlqspi.c
@@ -73,7 +73,7 @@
#define DINCNT 0x20
struct mrvlqspi_flash_bank {
- int probed;
+ bool probed;
uint32_t reg_base;
uint32_t bank_num;
const struct flash_device *dev;
@@ -844,7 +844,7 @@ static int mrvlqspi_probe(struct flash_bank *bank)
return ERROR_TARGET_NOT_HALTED;
}
- mrvlqspi_info->probed = 0;
+ mrvlqspi_info->probed = false;
mrvlqspi_info->bank_num = bank->bank_number;
/* Read flash JEDEC ID */
@@ -895,7 +895,7 @@ static int mrvlqspi_probe(struct flash_bank *bank)
}
bank->sectors = sectors;
- mrvlqspi_info->probed = 1;
+ mrvlqspi_info->probed = true;
return ERROR_OK;
}
@@ -947,7 +947,7 @@ FLASH_BANK_COMMAND_HANDLER(mrvlqspi_flash_bank_command)
/* Get QSPI controller register map base address */
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], mrvlqspi_info->reg_base);
bank->driver_priv = mrvlqspi_info;
- mrvlqspi_info->probed = 0;
+ mrvlqspi_info->probed = false;
return ERROR_OK;
}
commit 99914f3c04427fe738c2bc3ca160a5e9277a74e5
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:25:27 2020 +0200
flash/nor/mdr: Use 'bool' data type
Change-Id: I1eced61e5cb062445078e05507f6ad1a5a594c8d
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5745
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/mdr.c b/src/flash/nor/mdr.c
index 6e5b7b936..b835f9237 100644
--- a/src/flash/nor/mdr.c
+++ b/src/flash/nor/mdr.c
@@ -62,7 +62,7 @@
#define KEY 0x8AAA5551
struct mdr_flash_bank {
- int probed;
+ bool probed;
unsigned int mem_type;
unsigned int page_count;
unsigned int sec_count;
@@ -79,7 +79,7 @@ FLASH_BANK_COMMAND_HANDLER(mdr_flash_bank_command)
mdr_info = malloc(sizeof(struct mdr_flash_bank));
bank->driver_priv = mdr_info;
- mdr_info->probed = 0;
+ mdr_info->probed = false;
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[6], mdr_info->mem_type);
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[7], mdr_info->page_count);
COMMAND_PARSE_NUMBER(uint, CMD_ARGV[8], mdr_info->sec_count);
@@ -588,7 +588,7 @@ static int mdr_probe(struct flash_bank *bank)
bank->sectors[i].is_protected = 0;
}
- mdr_info->probed = 1;
+ mdr_info->probed = true;
return ERROR_OK;
}
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/mdr.c | 6 +++---
src/flash/nor/mrvlqspi.c | 8 ++++----
src/flash/nor/pic32mx.c | 8 ++++----
src/flash/nor/sh_qspi.c | 6 +++---
src/flash/nor/stm32h7x.c | 2 +-
src/flash/nor/stmsmi.c | 8 ++++----
src/flash/nor/w600.c | 8 ++++----
7 files changed, 23 insertions(+), 23 deletions(-)
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2020-07-08 21:07:03
|
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generated because a ref change was pushed to the repository containing
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- Log -----------------------------------------------------------------
commit 703a893f8ac61f8e4a19105fec8a00b9710a4e70
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:25:07 2020 +0200
flash/nor/max32xxx: Use 'bool' data type
Change-Id: I828cdd6d97a59fd0692eb22ba8fc0a5759029432
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5744
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/max32xxx.c b/src/flash/nor/max32xxx.c
index 20ebbbf4f..65898cd64 100644
--- a/src/flash/nor/max32xxx.c
+++ b/src/flash/nor/max32xxx.c
@@ -70,7 +70,7 @@
static int max32xxx_mass_erase(struct flash_bank *bank);
struct max32xxx_flash_bank {
- int probed;
+ bool probed;
int max326xx;
unsigned int flash_size;
unsigned int flc_base;
@@ -118,7 +118,7 @@ static int get_info(struct flash_bank *bank, char *buf, int buf_size)
int printed;
struct max32xxx_flash_bank *info = bank->driver_priv;
- if (info->probed == 0)
+ if (!info->probed)
return ERROR_FLASH_BANK_NOT_PROBED;
printed = snprintf(buf, buf_size, "\nMaxim Integrated max32xxx flash driver\n");
@@ -211,7 +211,7 @@ static int max32xxx_protect_check(struct flash_bank *bank)
struct target *target = bank->target;
uint32_t temp_reg;
- if (info->probed == 0)
+ if (!info->probed)
return ERROR_FLASH_BANK_NOT_PROBED;
if (!info->max326xx) {
@@ -248,7 +248,7 @@ static int max32xxx_erase(struct flash_bank *bank, unsigned int first,
return ERROR_TARGET_NOT_HALTED;
}
- if (info->probed == 0)
+ if (!info->probed)
return ERROR_FLASH_BANK_NOT_PROBED;
if ((last < first) || (last >= bank->num_sectors))
@@ -333,7 +333,7 @@ static int max32xxx_protect(struct flash_bank *bank, int set,
return ERROR_TARGET_NOT_HALTED;
}
- if (info->probed == 0)
+ if (!info->probed)
return ERROR_FLASH_BANK_NOT_PROBED;
if (!info->max326xx)
@@ -459,7 +459,7 @@ static int max32xxx_write(struct flash_bank *bank, const uint8_t *buffer,
LOG_DEBUG("bank=%p buffer=%p offset=%08" PRIx32 " count=%08" PRIx32 "",
bank, buffer, offset, count);
- if (info->probed == 0)
+ if (!info->probed)
return ERROR_FLASH_BANK_NOT_PROBED;
if (offset & 0x3) {
@@ -689,7 +689,7 @@ static int max32xxx_probe(struct flash_bank *bank)
if (max32xxx_protect_check(bank) == ERROR_FLASH_OPER_UNSUPPORTED)
LOG_WARNING("Flash protection not supported on this device");
- info->probed = 1;
+ info->probed = true;
return ERROR_OK;
}
@@ -708,7 +708,7 @@ static int max32xxx_mass_erase(struct flash_bank *bank)
return ERROR_TARGET_NOT_HALTED;
}
- if (info->probed == 0)
+ if (!info->probed)
return ERROR_FLASH_BANK_NOT_PROBED;
int not_protected = 0;
commit 5ac425365a2b5d1c89f0dc3c5e4a69c483f15938
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:24:53 2020 +0200
flash/nor/lpcspifi: Use 'bool' data type
Change-Id: I0485a7885fe154f983c7a7ce84cbedb0ba32ca31
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5743
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/lpcspifi.c b/src/flash/nor/lpcspifi.c
index 8616c04d0..13bb1f0a1 100644
--- a/src/flash/nor/lpcspifi.c
+++ b/src/flash/nor/lpcspifi.c
@@ -47,7 +47,7 @@
#define SPIFI_INIT_STACK_SIZE 512
struct lpcspifi_flash_bank {
- int probed;
+ bool probed;
uint32_t ssp_base;
uint32_t io_base;
uint32_t ioconfig_base;
@@ -72,7 +72,7 @@ FLASH_BANK_COMMAND_HANDLER(lpcspifi_flash_bank_command)
}
bank->driver_priv = lpcspifi_info;
- lpcspifi_info->probed = 0;
+ lpcspifi_info->probed = false;
return ERROR_OK;
}
@@ -849,7 +849,7 @@ static int lpcspifi_probe(struct flash_bank *bank)
/* If we've already probed, we should be fine to skip this time. */
if (lpcspifi_info->probed)
return ERROR_OK;
- lpcspifi_info->probed = 0;
+ lpcspifi_info->probed = false;
lpcspifi_info->ssp_base = 0x40083000;
lpcspifi_info->io_base = 0x400F4000;
@@ -908,7 +908,7 @@ static int lpcspifi_probe(struct flash_bank *bank)
bank->sectors = sectors;
- lpcspifi_info->probed = 1;
+ lpcspifi_info->probed = true;
return ERROR_OK;
}
commit e6e154e10302051c2170c6c4fc9cdffe1d118129
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:24:35 2020 +0200
flash/nor/jtagspi: Use 'bool' data type
Change-Id: I0e81dd476c6b3ec7fee6c84ab1bfcf9bca90c532
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5742
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/jtagspi.c b/src/flash/nor/jtagspi.c
index ce3f9ca24..20362f384 100644
--- a/src/flash/nor/jtagspi.c
+++ b/src/flash/nor/jtagspi.c
@@ -30,7 +30,7 @@
struct jtagspi_flash_bank {
struct jtag_tap *tap;
const struct flash_device *dev;
- int probed;
+ bool probed;
uint32_t ir;
};
@@ -49,7 +49,7 @@ FLASH_BANK_COMMAND_HANDLER(jtagspi_flash_bank_command)
bank->driver_priv = info;
info->tap = NULL;
- info->probed = 0;
+ info->probed = false;
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], info->ir);
return ERROR_OK;
@@ -170,7 +170,7 @@ static int jtagspi_probe(struct flash_bank *bank)
if (info->probed)
free(bank->sectors);
- info->probed = 0;
+ info->probed = false;
if (bank->target->tap == NULL) {
LOG_ERROR("Target has no JTAG tap");
@@ -224,7 +224,7 @@ static int jtagspi_probe(struct flash_bank *bank)
}
bank->sectors = sectors;
- info->probed = 1;
+ info->probed = true;
return ERROR_OK;
}
commit 20196f86d40c5d51cef19b76212063c323a00eb3
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:24:19 2020 +0200
flash/nor/fm3: Use 'bool' data type
Change-Id: Ic90ab762488063f6958f5e775c1b2fe5f3f1718f
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5741
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/fm3.c b/src/flash/nor/fm3.c
index 1dd9ae546..afeba8e0b 100644
--- a/src/flash/nor/fm3.c
+++ b/src/flash/nor/fm3.c
@@ -61,7 +61,7 @@ enum fm3_flash_type {
struct fm3_flash_bank {
enum fm3_variant variant;
enum fm3_flash_type flashtype;
- int probed;
+ bool probed;
};
FLASH_BANK_COMMAND_HANDLER(fm3_flash_bank_command)
@@ -132,7 +132,7 @@ FLASH_BANK_COMMAND_HANDLER(fm3_flash_bank_command)
return ERROR_FLASH_BANK_INVALID;
}
- fm3_info->probed = 0;
+ fm3_info->probed = false;
return ERROR_OK;
}
@@ -657,7 +657,7 @@ static int fm3_probe(struct flash_bank *bank)
*/
num_pages = 10; /* max number of Flash pages for malloc */
- fm3_info->probed = 0;
+ fm3_info->probed = false;
bank->sectors = malloc(sizeof(struct flash_sector) * num_pages);
bank->base = 0x00000000;
@@ -797,7 +797,7 @@ static int fm3_probe(struct flash_bank *bank)
bank->sectors[9].is_protected = -1;
}
- fm3_info->probed = 1;
+ fm3_info->probed = true;
return ERROR_OK;
}
commit 02fac04b4dee2af77dafeb09df5bb0c70f6bc4a1
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:24:11 2020 +0200
flash/nor/fespi: Use 'bool' data type
Change-Id: I4583b4475b2fa2733db0861bfe8f52f0a514c472
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5740
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/fespi.c b/src/flash/nor/fespi.c
index 134fba6e3..4afa1b8fb 100644
--- a/src/flash/nor/fespi.c
+++ b/src/flash/nor/fespi.c
@@ -122,7 +122,7 @@
struct fespi_flash_bank {
- int probed;
+ bool probed;
target_addr_t ctrl_base;
const struct flash_device *dev;
};
@@ -157,7 +157,7 @@ FLASH_BANK_COMMAND_HANDLER(fespi_flash_bank_command)
}
bank->driver_priv = fespi_info;
- fespi_info->probed = 0;
+ fespi_info->probed = false;
fespi_info->ctrl_base = 0;
if (CMD_ARGC >= 7) {
COMMAND_PARSE_ADDRESS(CMD_ARGV[6], fespi_info->ctrl_base);
@@ -916,7 +916,7 @@ static int fespi_probe(struct flash_bank *bank)
if (fespi_info->probed)
free(bank->sectors);
- fespi_info->probed = 0;
+ fespi_info->probed = false;
if (fespi_info->ctrl_base == 0) {
for (target_device = target_devices ; target_device->name ; ++target_device)
@@ -999,7 +999,7 @@ static int fespi_probe(struct flash_bank *bank)
}
bank->sectors = sectors;
- fespi_info->probed = 1;
+ fespi_info->probed = true;
return ERROR_OK;
}
commit 19e1a30991cc892b35c3b52e25eb24fd90c14b7a
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:23:59 2020 +0200
flash/nor/em357: Use 'bool' data type
Change-Id: I251b62275d204fdc315cd167685799c15d4e7cf4
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5739
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/em357.c b/src/flash/nor/em357.c
index a93c81e29..4e40e6b6b 100644
--- a/src/flash/nor/em357.c
+++ b/src/flash/nor/em357.c
@@ -87,7 +87,7 @@ struct em357_options {
struct em357_flash_bank {
struct em357_options option_bytes;
int ppage_size;
- int probed;
+ bool probed;
};
static int em357_mass_erase(struct flash_bank *bank);
@@ -104,7 +104,7 @@ FLASH_BANK_COMMAND_HANDLER(em357_flash_bank_command)
em357_info = malloc(sizeof(struct em357_flash_bank));
bank->driver_priv = em357_info;
- em357_info->probed = 0;
+ em357_info->probed = false;
return ERROR_OK;
}
@@ -680,7 +680,7 @@ static int em357_probe(struct flash_bank *bank)
int page_size;
uint32_t base_address = 0x08000000;
- em357_info->probed = 0;
+ em357_info->probed = false;
switch (bank->size) {
case 0x10000:
@@ -741,7 +741,7 @@ static int em357_probe(struct flash_bank *bank)
bank->sectors[i].is_protected = 1;
}
- em357_info->probed = 1;
+ em357_info->probed = true;
return ERROR_OK;
}
commit f23525e5dd1ed1e0a63f2ecf57bf7927be1a9765
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:23:44 2020 +0200
flash/nor/cfi: Use 'bool' data type
Change-Id: I25198223175c26aded9ad667b802da09883e94ee
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5738
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 19fb6b2c2..9d2a53a6b 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -814,7 +814,7 @@ static int cfi_intel_info(struct flash_bank *bank, char *buf, int buf_size)
int cfi_flash_bank_cmd(struct flash_bank *bank, unsigned int argc, const char **argv)
{
struct cfi_flash_bank *cfi_info;
- int bus_swap = 0;
+ bool bus_swap = false;
if (argc < 6)
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -841,20 +841,20 @@ int cfi_flash_bank_cmd(struct flash_bank *bank, unsigned int argc, const char **
cfi_info->pri_ext = NULL;
bank->driver_priv = cfi_info;
- cfi_info->x16_as_x8 = 0;
- cfi_info->jedec_probe = 0;
- cfi_info->not_cfi = 0;
- cfi_info->data_swap = 0;
+ cfi_info->x16_as_x8 = false;
+ cfi_info->jedec_probe = false;
+ cfi_info->not_cfi = false;
+ cfi_info->data_swap = false;
for (unsigned i = 6; i < argc; i++) {
if (strcmp(argv[i], "x16_as_x8") == 0)
- cfi_info->x16_as_x8 = 1;
+ cfi_info->x16_as_x8 = true;
else if (strcmp(argv[i], "data_swap") == 0)
- cfi_info->data_swap = 1;
+ cfi_info->data_swap = true;
else if (strcmp(argv[i], "bus_swap") == 0)
- bus_swap = 1;
+ bus_swap = true;
else if (strcmp(argv[i], "jedec_probe") == 0)
- cfi_info->jedec_probe = 1;
+ cfi_info->jedec_probe = true;
}
if (bus_swap)
@@ -2661,7 +2661,7 @@ int cfi_probe(struct flash_bank *bank)
/* query only if this is a CFI compatible flash,
* otherwise the relevant info has already been filled in
*/
- if (cfi_info->not_cfi == 0) {
+ if (!cfi_info->not_cfi) {
/* enter CFI query mode
* according to JEDEC Standard No. 68.01,
* a single bus sequence with address = 0x55, data = 0x98 should put
@@ -3011,7 +3011,7 @@ int cfi_get_info(struct flash_bank *bank, char *buf, int buf_size)
return ERROR_OK;
}
- if (cfi_info->not_cfi == 0)
+ if (!cfi_info->not_cfi)
printed = snprintf(buf, buf_size, "\nCFI flash: ");
else
printed = snprintf(buf, buf_size, "\nnon-CFI flash: ");
diff --git a/src/flash/nor/cfi.h b/src/flash/nor/cfi.h
index effa1d5c0..eceb9a4b3 100644
--- a/src/flash/nor/cfi.h
+++ b/src/flash/nor/cfi.h
@@ -23,13 +23,13 @@
#define CFI_STATUS_POLL_MASK_DQ6_DQ7 0xC0 /* DQ6..DQ7 */
struct cfi_flash_bank {
- int x16_as_x8;
- int jedec_probe;
- int not_cfi;
- int probed;
+ bool x16_as_x8;
+ bool jedec_probe;
+ bool not_cfi;
+ bool probed;
enum target_endianness endianness;
- int data_swap;
+ bool data_swap;
uint16_t manufacturer;
uint16_t device_id;
diff --git a/src/flash/nor/non_cfi.c b/src/flash/nor/non_cfi.c
index 851c0ae81..f44adba13 100644
--- a/src/flash/nor/non_cfi.c
+++ b/src/flash/nor/non_cfi.c
@@ -487,7 +487,7 @@ void cfi_fixup_non_cfi(struct flash_bank *bank)
if (!non_cfi->mfr)
return;
- cfi_info->not_cfi = 1;
+ cfi_info->not_cfi = true;
/* fill in defaults for non-critical data */
cfi_info->vcc_min = 0x0;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/cfi.c | 22 +++++++++++-----------
src/flash/nor/cfi.h | 10 +++++-----
src/flash/nor/em357.c | 8 ++++----
src/flash/nor/fespi.c | 8 ++++----
src/flash/nor/fm3.c | 8 ++++----
src/flash/nor/jtagspi.c | 8 ++++----
src/flash/nor/lpcspifi.c | 8 ++++----
src/flash/nor/max32xxx.c | 16 ++++++++--------
src/flash/nor/non_cfi.c | 2 +-
9 files changed, 45 insertions(+), 45 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-07-08 21:06:24
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 46238fabb9d5c9b81de1151312babedb88423fd9 (commit)
via 8375deea2cd37965fff2570e1132607e0a399335 (commit)
via 7e8efccb596d8aee1a4ec5b94970a94af2e296e4 (commit)
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via 8fc00a38bc54ce6f42d0ed1d9dc3588e58bbb73e (commit)
from 70f69f872857fd94ed252088d00e071e57d07b39 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 46238fabb9d5c9b81de1151312babedb88423fd9
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:23:23 2020 +0200
flash/nor/atsamv: Use 'bool' data type
Change-Id: Id4ceaf38dc5eba5b0eb62416fc357fdfc7ea21c0
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5737
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/atsamv.c b/src/flash/nor/atsamv.c
index 13d1d263f..1ad37c1ab 100644
--- a/src/flash/nor/atsamv.c
+++ b/src/flash/nor/atsamv.c
@@ -97,7 +97,7 @@
extern const struct flash_driver atsamv_flash;
struct samv_flash_bank {
- int probed;
+ bool probed;
unsigned size_bytes;
unsigned gpnvm[SAMV_NUM_GPNVM_BITS];
};
@@ -379,7 +379,7 @@ static int samv_probe(struct flash_bank *bank)
struct samv_flash_bank *samv_info = bank->driver_priv;
samv_info->size_bytes = bank->size;
- samv_info->probed = 1;
+ samv_info->probed = true;
bank->base = SAMV_FLASH_BASE;
bank->num_sectors = bank->size / SAMV_SECTOR_SIZE;
commit 8375deea2cd37965fff2570e1132607e0a399335
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:22:37 2020 +0200
flash/nor/ath79: Use 'bool' data type
Change-Id: Iecd29dcfcc1ae983e4e0828025d2d174944c1e9d
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5736
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/ath79.c b/src/flash/nor/ath79.c
index 88ebbf23c..c30ddf3c0 100644
--- a/src/flash/nor/ath79.c
+++ b/src/flash/nor/ath79.c
@@ -89,7 +89,7 @@ struct ath79_spi_ctx {
};
struct ath79_flash_bank {
- int probed;
+ bool probed;
int chipselect;
uint32_t io_base;
const struct flash_device *dev;
@@ -777,7 +777,7 @@ static int ath79_probe(struct flash_bank *bank)
free(bank->sectors);
free(ath79_info->spi.page_buf);
}
- ath79_info->probed = 0;
+ ath79_info->probed = false;
for (target_device = target_devices; target_device->name;
++target_device)
@@ -850,7 +850,7 @@ static int ath79_probe(struct flash_bank *bank)
}
bank->sectors = sectors;
- ath79_info->probed = 1;
+ ath79_info->probed = true;
return ERROR_OK;
}
commit 7e8efccb596d8aee1a4ec5b94970a94af2e296e4
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:22:15 2020 +0200
flash/nor/at91sam4: Use 'bool' data type
Change-Id: Iade91ac58a995676c412606a63e62b70337427f1
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5735
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c
index 26cde19bc..f2827496d 100644
--- a/src/flash/nor/at91sam4.c
+++ b/src/flash/nor/at91sam4.c
@@ -166,7 +166,7 @@ struct sam4_cfg {
};
struct sam4_bank_private {
- int probed;
+ bool probed;
/* DANGER: THERE ARE DRAGONS HERE.. */
/* NOTE: If you add more 'ghost' pointers */
/* be aware that you must *manually* update */
@@ -212,7 +212,7 @@ struct sam4_chip_details {
struct sam4_chip {
struct sam4_chip *next;
- int probed;
+ bool probed;
/* this is "initialized" from the global const structure */
struct sam4_chip_details details;
@@ -275,14 +275,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_C32,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 1024 * 1024,
.nsectors = 128,
.sector_size = 8192,
@@ -290,14 +290,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_C32,
.controller_address = 0x400e0c00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 1024 * 1024,
.nsectors = 128,
.sector_size = 8192,
@@ -316,14 +316,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_C32,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 1024 * 1024,
.nsectors = 128,
.sector_size = 8192,
@@ -331,14 +331,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_C32,
.controller_address = 0x400e0c00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 1024 * 1024,
.nsectors = 128,
.sector_size = 8192,
@@ -357,14 +357,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_C,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 1024 * 1024,
.nsectors = 128,
.sector_size = 8192,
@@ -372,8 +372,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -390,14 +390,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_C,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 512 * 1024,
.nsectors = 64,
.sector_size = 8192,
@@ -405,8 +405,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -423,14 +423,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_C,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 256 * 1024,
.nsectors = 32,
.sector_size = 8192,
@@ -438,8 +438,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -458,14 +458,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 1024 * 1024,
.nsectors = 128,
.sector_size = 8192,
@@ -473,8 +473,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -493,14 +493,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 512 * 1024,
.nsectors = 64,
.sector_size = 8192,
@@ -508,8 +508,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -526,14 +526,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 512 * 1024,
.nsectors = 64,
.sector_size = 8192,
@@ -541,8 +541,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -559,14 +559,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 512 * 1024,
.nsectors = 64,
.sector_size = 8192,
@@ -574,8 +574,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -592,14 +592,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 1024 * 1024,
.nsectors = 128,
.sector_size = 8192,
@@ -607,8 +607,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -625,14 +625,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 1024 * 1024,
.nsectors = 128,
.sector_size = 8192,
@@ -640,8 +640,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -660,14 +660,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 1024 * 1024,
.nsectors = 128,
.sector_size = 8192,
@@ -675,8 +675,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -694,14 +694,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 1024 * 1024,
.nsectors = 128,
.sector_size = 8192,
@@ -709,8 +709,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -727,14 +727,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 1024 * 1024,
.nsectors = 128,
.sector_size = 8192,
@@ -742,8 +742,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -760,14 +760,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 1024 * 1024,
.nsectors = 128,
.sector_size = 8192,
@@ -775,8 +775,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -793,14 +793,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 1024 * 1024,
.nsectors = 128,
.sector_size = 8192,
@@ -808,8 +808,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -826,14 +826,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 512 * 1024,
.nsectors = 64,
.sector_size = 8192,
@@ -841,8 +841,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -859,14 +859,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 512 * 1024,
.nsectors = 64,
.sector_size = 8192,
@@ -874,8 +874,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -892,14 +892,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 512 * 1024,
.nsectors = 64,
.sector_size = 8192,
@@ -907,8 +907,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -926,14 +926,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 256 * 1024,
.nsectors = 32,
.sector_size = 8192,
@@ -941,8 +941,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -960,14 +960,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 256 * 1024,
.nsectors = 32,
.sector_size = 8192,
@@ -975,8 +975,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -994,14 +994,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 256 * 1024,
.nsectors = 32,
.sector_size = 8192,
@@ -1009,8 +1009,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -1028,14 +1028,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 128 * 1024,
.nsectors = 16,
.sector_size = 8192,
@@ -1043,8 +1043,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -1062,14 +1062,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 128 * 1024,
.nsectors = 16,
.sector_size = 8192,
@@ -1077,8 +1077,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -1096,14 +1096,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = {*/
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 128 * 1024,
.nsectors = 16,
.sector_size = 8192,
@@ -1111,8 +1111,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -1131,14 +1131,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 1024 * 1024,
.nsectors = 128,
.sector_size = 8192,
@@ -1147,14 +1147,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_2048K_SD,
.controller_address = 0x400e0c00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 1024 * 1024,
.nsectors = 128,
.sector_size = 8192,
@@ -1175,14 +1175,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 1024 * 1024,
.nsectors = 128,
.sector_size = 8192,
@@ -1191,14 +1191,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_2048K_SD,
.controller_address = 0x400e0c00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 1024 * 1024,
.nsectors = 128,
.sector_size = 8192,
@@ -1219,14 +1219,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 512 * 1024,
.nsectors = 64,
.sector_size = 8192,
@@ -1235,14 +1235,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_1024K_SD,
.controller_address = 0x400e0c00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 512 * 1024,
.nsectors = 64,
.sector_size = 8192,
@@ -1263,14 +1263,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK0_BASE_SD,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 512 * 1024,
.nsectors = 64,
.sector_size = 8192,
@@ -1279,14 +1279,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
.base_address = FLASH_BANK1_BASE_1024K_SD,
.controller_address = 0x400e0c00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 512 * 1024,
.nsectors = 64,
.sector_size = 8192,
@@ -1307,14 +1307,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
/* .bank[0] = {*/
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 512 * 1024,
.nsectors = 64,
.sector_size = 8192,
@@ -1322,8 +1322,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = {*/
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
@@ -1342,14 +1342,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 512 * 1024,
.nsectors = 64,
.sector_size = 8192,
@@ -1357,8 +1357,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = */
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
}
@@ -1376,14 +1376,14 @@ static const struct sam4_chip_details all_sam4_details[] = {
{
/* .bank[0] = */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
.base_address = FLASH_BANK_BASE_S,
.controller_address = 0x400e0a00,
.flash_wait_states = 5,
- .present = 1,
+ .present = true,
.size_bytes = 512 * 1024,
.nsectors = 64,
.sector_size = 8192,
@@ -1391,8 +1391,8 @@ static const struct sam4_chip_details all_sam4_details[] = {
},
/* .bank[1] = */
{
- .present = 0,
- .probed = 0,
+ .present = false,
+ .probed = false,
.bank_number = 1,
},
}
@@ -2472,7 +2472,7 @@ FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
pChip->target = bank->target;
/* assumption is this runs at 32khz */
pChip->cfg.slow_freq = 32768;
- pChip->probed = 0;
+ pChip->probed = false;
}
switch (bank->base) {
@@ -2664,7 +2664,7 @@ static int sam4_probe(struct flash_bank *bank)
}
}
- pPrivate->probed = 1;
+ pPrivate->probed = true;
r = sam4_protect_check(bank);
if (r != ERROR_OK)
commit 6a1de20a7c8c8fa0057a914a1cdf3f0b514cf7c3
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:21:52 2020 +0200
flash/nor/at91sam3: Use 'bool' data type
Change-Id: Ibaf599a4ab88ea36a84b3389e2f704554d465434
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5734
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index 415f3932c..434891112 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -187,7 +187,7 @@ struct sam3_cfg {
*/
struct sam3_bank_private {
- int probed;
+ bool probed;
/* DANGER: THERE ARE DRAGONS HERE.. */
/* NOTE: If you add more 'ghost' pointers */
/* be aware that you must *manually* update */
@@ -233,7 +233,7 @@ struct sam3_chip_details {
struct sam3_chip {
struct sam3_chip *next;
- int probed;
+ bool probed;
/* this is "initialized" from the global const structure */
struct sam3_chip_details details;
@@ -306,7 +306,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -322,7 +322,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
@@ -357,7 +357,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -373,7 +373,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
},
@@ -399,7 +399,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -416,7 +416,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
},
@@ -448,7 +448,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
{
/* .bank[0] = { */
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -463,7 +463,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
},
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
@@ -498,7 +498,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -514,7 +514,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
},
@@ -540,7 +540,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -556,7 +556,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
@@ -578,7 +578,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -594,7 +594,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
@@ -611,7 +611,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -627,7 +627,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
@@ -643,7 +643,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -659,7 +659,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
@@ -675,7 +675,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -691,7 +691,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
@@ -707,7 +707,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -723,7 +723,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
@@ -739,7 +739,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -754,7 +754,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
},
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
@@ -779,7 +779,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -794,7 +794,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
},
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
@@ -819,7 +819,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -834,7 +834,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
},
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
@@ -859,7 +859,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -875,7 +875,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
@@ -891,7 +891,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -907,7 +907,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
@@ -923,7 +923,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -939,7 +939,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
@@ -955,7 +955,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -971,7 +971,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
@@ -987,7 +987,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1003,7 +1003,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
@@ -1019,7 +1019,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1035,7 +1035,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
@@ -1051,7 +1051,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1067,7 +1067,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
@@ -1101,7 +1101,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1118,7 +1118,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
},
@@ -1150,7 +1150,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1167,7 +1167,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
},
@@ -1199,7 +1199,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1216,7 +1216,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
},
@@ -1248,7 +1248,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1265,7 +1265,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
},
@@ -1297,7 +1297,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1314,7 +1314,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
},
@@ -1346,7 +1346,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1363,7 +1363,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
},
@@ -1395,7 +1395,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1412,7 +1412,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
},
@@ -1444,7 +1444,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1461,7 +1461,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
},
@@ -1493,7 +1493,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1510,7 +1510,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
},
@@ -1527,7 +1527,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1544,7 +1544,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
},
@@ -1561,7 +1561,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1578,7 +1578,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
},
@@ -1595,7 +1595,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1612,7 +1612,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
},
@@ -1629,7 +1629,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[0] = { */
{
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1646,7 +1646,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
/* .bank[1] = { */
{
.present = 0,
- .probed = 0,
+ .probed = false,
.bank_number = 1,
},
},
@@ -1680,7 +1680,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1695,7 +1695,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
},
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
@@ -1721,7 +1721,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1736,7 +1736,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
},
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
@@ -1780,7 +1780,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1795,7 +1795,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
},
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
@@ -1822,7 +1822,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1837,7 +1837,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
},
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
@@ -1863,7 +1863,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1878,7 +1878,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
},
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
@@ -1904,7 +1904,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1919,7 +1919,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
},
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
@@ -1945,7 +1945,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -1960,7 +1960,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
},
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
@@ -1986,7 +1986,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
{
/* .bank[0] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 0,
@@ -2001,7 +2001,7 @@ static const struct sam3_chip_details all_sam3_details[] = {
},
/* .bank[1] = { */
{
- .probed = 0,
+ .probed = false,
.pChip = NULL,
.pBank = NULL,
.bank_number = 1,
@@ -3051,7 +3051,7 @@ FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
pChip->target = bank->target;
/* assumption is this runs at 32khz */
pChip->cfg.slow_freq = 32768;
- pChip->probed = 0;
+ pChip->probed = false;
}
switch (bank->base) {
@@ -3224,7 +3224,7 @@ static int _sam3_probe(struct flash_bank *bank, int noise)
}
}
- pPrivate->probed = 1;
+ pPrivate->probed = true;
r = sam3_protect_check(bank);
if (r != ERROR_OK)
commit 8fc00a38bc54ce6f42d0ed1d9dc3588e58bbb73e
Author: Marc Schink <de...@za...>
Date: Wed Jul 1 10:21:06 2020 +0200
flash/nor/ambiqmicro: Use 'bool' data type
Change-Id: Ia8492905dc506d518266343d699c3245efbc1ab1
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5733
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/ambiqmicro.c b/src/flash/nor/ambiqmicro.c
index 1e2a4b176..622943d28 100644
--- a/src/flash/nor/ambiqmicro.c
+++ b/src/flash/nor/ambiqmicro.c
@@ -92,7 +92,7 @@ static const uint32_t apollo_sram_size[] = {
struct ambiqmicro_flash_bank {
/* chip id register */
- uint32_t probed;
+ bool probed;
const char *target_name;
uint8_t target_class;
@@ -156,7 +156,7 @@ FLASH_BANK_COMMAND_HANDLER(ambiqmicro_flash_bank_command)
ambiqmicro_info->target_name = "Unknown target";
/* part wasn't probed yet */
- ambiqmicro_info->probed = 0;
+ ambiqmicro_info->probed = false;
return ERROR_OK;
}
@@ -167,7 +167,7 @@ static int get_ambiqmicro_info(struct flash_bank *bank, char *buf, int buf_size)
int printed;
char *classname;
- if (ambiqmicro_info->probed == 0) {
+ if (!ambiqmicro_info->probed) {
LOG_ERROR("Target not probed");
return ERROR_FLASH_BANK_NOT_PROBED;
}
@@ -280,7 +280,7 @@ static int ambiqmicro_protect_check(struct flash_bank *bank)
uint32_t i;
- if (ambiqmicro->probed == 0) {
+ if (!ambiqmicro->probed) {
LOG_ERROR("Target not probed");
return ERROR_FLASH_BANK_NOT_PROBED;
}
@@ -371,7 +371,7 @@ static int ambiqmicro_mass_erase(struct flash_bank *bank)
return ERROR_TARGET_NOT_HALTED;
}
- if (ambiqmicro_info->probed == 0) {
+ if (!ambiqmicro_info->probed) {
LOG_ERROR("Target not probed");
return ERROR_FLASH_BANK_NOT_PROBED;
}
@@ -439,7 +439,7 @@ static int ambiqmicro_erase(struct flash_bank *bank, unsigned int first,
return ERROR_TARGET_NOT_HALTED;
}
- if (ambiqmicro_info->probed == 0) {
+ if (!ambiqmicro_info->probed) {
LOG_ERROR("Target not probed");
return ERROR_FLASH_BANK_NOT_PROBED;
}
@@ -659,7 +659,7 @@ static int ambiqmicro_probe(struct flash_bank *bank)
/* If this is a ambiqmicro chip, it has flash; probe() is just
* to figure out how much is present. Only do it once.
*/
- if (ambiqmicro_info->probed == 1) {
+ if (ambiqmicro_info->probed) {
LOG_INFO("Target already probed");
return ERROR_OK;
}
@@ -691,7 +691,7 @@ static int ambiqmicro_probe(struct flash_bank *bank)
/*
* Part has been probed.
*/
- ambiqmicro_info->probed = 1;
+ ambiqmicro_info->probed = true;
return retval;
}
@@ -711,7 +711,7 @@ static int ambiqmicro_otp_program(struct flash_bank *bank,
return ERROR_TARGET_NOT_HALTED;
}
- if (ambiqmicro_info->probed == 0) {
+ if (!ambiqmicro_info->probed) {
LOG_ERROR("Target not probed");
return ERROR_FLASH_BANK_NOT_PROBED;
}
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/ambiqmicro.c | 18 ++--
src/flash/nor/at91sam3.c | 176 +++++++++++++++---------------
src/flash/nor/at91sam4.c | 264 ++++++++++++++++++++++-----------------------
src/flash/nor/ath79.c | 6 +-
src/flash/nor/atsamv.c | 4 +-
5 files changed, 234 insertions(+), 234 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-07-08 21:05:50
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 70f69f872857fd94ed252088d00e071e57d07b39 (commit)
from ef14384b681af4f731f768bb866457832af6925f (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 70f69f872857fd94ed252088d00e071e57d07b39
Author: Mikhail Rasputin <mik...@ya...>
Date: Wed Jun 24 19:21:31 2020 +0300
jtag/tcl: fix a double free of jim object
The Jim_SetResultFormatted() frees jim object earlier and the
Jim_FreeNewObj() does it second time. It breaks the memory heap.
To avoid it the Jim_IncrRefCount() + Jim_DecrRefCount() should be used
instead of the Jim_FreeNewObj() call.
Change-Id: Ifa5f38009b2d617624b5f27e916720888a3dbad9
Signed-off-by: Mikhail Rasputin <mik...@ya...>
Reviewed-on: http://openocd.zylin.com/5724
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index d2f1f0db5..8b76bff07 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -689,8 +689,9 @@ static int jim_jtag_arp_init(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
int e = jtag_init_inner(context);
if (e != ERROR_OK) {
Jim_Obj *eObj = Jim_NewIntObj(goi.interp, e);
+ Jim_IncrRefCount(eObj);
Jim_SetResultFormatted(goi.interp, "error: %#s", eObj);
- Jim_FreeNewObj(goi.interp, eObj);
+ Jim_DecrRefCount(goi.interp, eObj);
return JIM_ERR;
}
return JIM_OK;
@@ -713,8 +714,9 @@ static int jim_jtag_arp_init_reset(Jim_Interp *interp, int argc, Jim_Obj *const
if (e != ERROR_OK) {
Jim_Obj *eObj = Jim_NewIntObj(goi.interp, e);
+ Jim_IncrRefCount(eObj);
Jim_SetResultFormatted(goi.interp, "error: %#s", eObj);
- Jim_FreeNewObj(goi.interp, eObj);
+ Jim_DecrRefCount(goi.interp, eObj);
return JIM_ERR;
}
return JIM_OK;
-----------------------------------------------------------------------
Summary of changes:
src/jtag/tcl.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-07-07 04:24:44
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via ef14384b681af4f731f768bb866457832af6925f (commit)
from a2e6982a1816a0229bd5644156f3025a0e8cb6ce (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit ef14384b681af4f731f768bb866457832af6925f
Author: Marc Schink <de...@za...>
Date: Sun Jun 7 17:00:13 2020 +0200
flash/nor: Use proper data types in driver API
Use 'unsigned int' and 'bool' instead of 'int' where appropriate.
While at it, fix some coding style issues.
No new Clang analyzer warnings.
Change-Id: I700802c9ee81c3c7ae73108f0f8f06b15a4345f8
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/4929
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/aduc702x.c b/src/flash/nor/aduc702x.c
index b6e19376c..b7d2299f7 100644
--- a/src/flash/nor/aduc702x.c
+++ b/src/flash/nor/aduc702x.c
@@ -57,13 +57,12 @@ static int aduc702x_build_sector_list(struct flash_bank *bank)
{
/* aduc7026_struct flash_bank *aduc7026_info = bank->driver_priv; */
- int i = 0;
uint32_t offset = 0;
/* sector size is 512 */
bank->num_sectors = bank->size / 512;
bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
- for (i = 0; i < bank->num_sectors; ++i) {
+ for (unsigned int i = 0; i < bank->num_sectors; ++i) {
bank->sectors[i].offset = offset;
bank->sectors[i].size = 512;
offset += bank->sectors[i].size;
@@ -74,7 +73,8 @@ static int aduc702x_build_sector_list(struct flash_bank *bank)
return ERROR_OK;
}
-static int aduc702x_erase(struct flash_bank *bank, int first, int last)
+static int aduc702x_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
/* int res; */
int x;
diff --git a/src/flash/nor/aducm360.c b/src/flash/nor/aducm360.c
index 7c5596d48..5e0a666ea 100644
--- a/src/flash/nor/aducm360.c
+++ b/src/flash/nor/aducm360.c
@@ -85,13 +85,12 @@ FLASH_BANK_COMMAND_HANDLER(aducm360_flash_bank_command)
/* ----------------------------------------------------------------------- */
static int aducm360_build_sector_list(struct flash_bank *bank)
{
- int i = 0;
uint32_t offset = 0;
/* sector size is 512 */
bank->num_sectors = bank->size / FLASH_SECTOR_SIZE;
bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
- for (i = 0; i < bank->num_sectors; ++i) {
+ for (unsigned i = 0; i < bank->num_sectors; ++i) {
bank->sectors[i].offset = offset;
bank->sectors[i].size = FLASH_SECTOR_SIZE;
offset += bank->sectors[i].size;
@@ -164,7 +163,8 @@ static int aducm360_page_erase(struct target *target, uint32_t padd)
}
/* ----------------------------------------------------------------------- */
-static int aducm360_erase(struct flash_bank *bank, int first, int last)
+static int aducm360_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
int res = ERROR_OK;
int i;
diff --git a/src/flash/nor/ambiqmicro.c b/src/flash/nor/ambiqmicro.c
index b41b15c07..1e2a4b176 100644
--- a/src/flash/nor/ambiqmicro.c
+++ b/src/flash/nor/ambiqmicro.c
@@ -427,7 +427,8 @@ static int ambiqmicro_mass_erase(struct flash_bank *bank)
}
-static int ambiqmicro_erase(struct flash_bank *bank, int first, int last)
+static int ambiqmicro_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
struct target *target = bank->target;
@@ -447,14 +448,14 @@ static int ambiqmicro_erase(struct flash_bank *bank, int first, int last)
* Check pages.
* Fix num_pages for the device.
*/
- if ((first < 0) || (last < first) || (last >= (int)ambiqmicro_info->num_pages))
+ if ((last < first) || (last >= ambiqmicro_info->num_pages))
return ERROR_FLASH_SECTOR_INVALID;
/*
* Just Mass Erase if all pages are given.
* TODO: Fix num_pages for the device
*/
- if ((first == 0) && (last == ((int)ambiqmicro_info->num_pages-1)))
+ if ((first == 0) && (last == (ambiqmicro_info->num_pages - 1)))
return ambiqmicro_mass_erase(bank);
/*
@@ -502,7 +503,7 @@ static int ambiqmicro_erase(struct flash_bank *bank, int first, int last)
/*
* Erase the pages.
*/
- LOG_INFO("Erasing pages %d to %d on bank %d", first, last, bank->bank_number);
+ LOG_INFO("Erasing pages %u to %u on bank %u", first, last, bank->bank_number);
/*
* passed pc, addr = ROM function, handle breakpoints, not debugging.
@@ -512,7 +513,7 @@ static int ambiqmicro_erase(struct flash_bank *bank, int first, int last)
if (retval != ERROR_OK)
return retval;
- LOG_INFO("%d pages erased!", 1+(last-first));
+ LOG_INFO("%u pages erased!", 1+(last-first));
if (first == 0) {
/*
@@ -527,7 +528,8 @@ static int ambiqmicro_erase(struct flash_bank *bank, int first, int last)
return retval;
}
-static int ambiqmicro_protect(struct flash_bank *bank, int set, int first, int last)
+static int ambiqmicro_protect(struct flash_bank *bank, int set,
+ unsigned int first, unsigned int last)
{
/* struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
* struct target *target = bank->target; */
@@ -679,7 +681,7 @@ static int ambiqmicro_probe(struct flash_bank *bank)
bank->size = ambiqmicro_info->pagesize * ambiqmicro_info->num_pages;
bank->num_sectors = ambiqmicro_info->num_pages;
bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
- for (int i = 0; i < bank->num_sectors; i++) {
+ for (unsigned int i = 0; i < bank->num_sectors; i++) {
bank->sectors[i].offset = i * ambiqmicro_info->pagesize;
bank->sectors[i].size = ambiqmicro_info->pagesize;
bank->sectors[i].is_erased = -1;
@@ -775,8 +777,6 @@ static int ambiqmicro_otp_program(struct flash_bank *bank,
COMMAND_HANDLER(ambiqmicro_handle_mass_erase_command)
{
- int i;
-
if (CMD_ARGC < 1)
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -787,7 +787,7 @@ COMMAND_HANDLER(ambiqmicro_handle_mass_erase_command)
if (ambiqmicro_mass_erase(bank) == ERROR_OK) {
/* set all sectors as erased */
- for (i = 0; i < bank->num_sectors; i++)
+ for (unsigned int i = 0; i < bank->num_sectors; i++)
bank->sectors[i].is_erased = 1;
command_print(CMD, "ambiqmicro mass erase complete");
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index c9ffa653b..415f3932c 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -3171,12 +3171,11 @@ static int sam3_GetDetails(struct sam3_bank_private *pPrivate)
static int _sam3_probe(struct flash_bank *bank, int noise)
{
- unsigned x;
int r;
struct sam3_bank_private *pPrivate;
- LOG_DEBUG("Begin: Bank: %d, Noise: %d", bank->bank_number, noise);
+ LOG_DEBUG("Begin: Bank: %u, Noise: %d", bank->bank_number, noise);
if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
@@ -3201,7 +3200,7 @@ static int _sam3_probe(struct flash_bank *bank, int noise)
return r;
/* update the flash bank size */
- for (x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
+ for (unsigned int x = 0; x < SAM3_MAX_FLASH_BANKS; x++) {
if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
bank->size = pPrivate->pChip->details.bank[x].size_bytes;
break;
@@ -3216,7 +3215,7 @@ static int _sam3_probe(struct flash_bank *bank, int noise)
}
bank->num_sectors = pPrivate->nsectors;
- for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
+ for (unsigned int x = 0; x < bank->num_sectors; x++) {
bank->sectors[x].size = pPrivate->sector_size;
bank->sectors[x].offset = x * (pPrivate->sector_size);
/* mark as unknown */
@@ -3252,7 +3251,8 @@ static int sam3_auto_probe(struct flash_bank *bank)
return _sam3_probe(bank, 0);
}
-static int sam3_erase(struct flash_bank *bank, int first, int last)
+static int sam3_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct sam3_bank_private *pPrivate;
int r;
@@ -3273,7 +3273,7 @@ static int sam3_erase(struct flash_bank *bank, int first, int last)
if (!(pPrivate->probed))
return ERROR_FLASH_BANK_NOT_PROBED;
- if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
+ if ((first == 0) && ((last + 1) == pPrivate->nsectors)) {
/* whole chip */
LOG_DEBUG("Here");
return FLASHD_EraseEntireBank(pPrivate);
@@ -3282,7 +3282,8 @@ static int sam3_erase(struct flash_bank *bank, int first, int last)
return ERROR_OK;
}
-static int sam3_protect(struct flash_bank *bank, int set, int first, int last)
+static int sam3_protect(struct flash_bank *bank, int set, unsigned int first,
+ unsigned int last)
{
struct sam3_bank_private *pPrivate;
int r;
@@ -3298,9 +3299,9 @@ static int sam3_protect(struct flash_bank *bank, int set, int first, int last)
return ERROR_FLASH_BANK_NOT_PROBED;
if (set)
- r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
+ r = FLASHD_Lock(pPrivate, first, last);
else
- r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
+ r = FLASHD_Unlock(pPrivate, first, last);
LOG_DEBUG("End: r=%d", r);
return r;
diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c
index 5b56c4241..26cde19bc 100644
--- a/src/flash/nor/at91sam4.c
+++ b/src/flash/nor/at91sam4.c
@@ -2608,12 +2608,11 @@ static int sam4_info(struct flash_bank *bank, char *buf, int buf_size)
static int sam4_probe(struct flash_bank *bank)
{
- unsigned x;
int r;
struct sam4_bank_private *pPrivate;
- LOG_DEBUG("Begin: Bank: %d", bank->bank_number);
+ LOG_DEBUG("Begin: Bank: %u", bank->bank_number);
if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
@@ -2638,7 +2637,7 @@ static int sam4_probe(struct flash_bank *bank)
return r;
/* update the flash bank size */
- for (x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
+ for (unsigned int x = 0; x < SAM4_MAX_FLASH_BANKS; x++) {
if (bank->base == pPrivate->pChip->details.bank[x].base_address) {
bank->size = pPrivate->pChip->details.bank[x].size_bytes;
LOG_DEBUG("SAM4 Set flash bank to " TARGET_ADDR_FMT " - "
@@ -2656,7 +2655,7 @@ static int sam4_probe(struct flash_bank *bank)
}
bank->num_sectors = pPrivate->nsectors;
- for (x = 0; ((int)(x)) < bank->num_sectors; x++) {
+ for (unsigned int x = 0; x < bank->num_sectors; x++) {
bank->sectors[x].size = pPrivate->sector_size;
bank->sectors[x].offset = x * (pPrivate->sector_size);
/* mark as unknown */
@@ -2693,11 +2692,11 @@ static int sam4_auto_probe(struct flash_bank *bank)
return sam4_probe(bank);
}
-static int sam4_erase(struct flash_bank *bank, int first, int last)
+static int sam4_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct sam4_bank_private *pPrivate;
int r;
- int i;
int pageCount;
/*16 pages equals 8KB - Same size as a lock region*/
pageCount = 16;
@@ -2719,26 +2718,26 @@ static int sam4_erase(struct flash_bank *bank, int first, int last)
if (!(pPrivate->probed))
return ERROR_FLASH_BANK_NOT_PROBED;
- if ((first == 0) && ((last + 1) == ((int)(pPrivate->nsectors)))) {
+ if ((first == 0) && ((last + 1) == pPrivate->nsectors)) {
/* whole chip */
LOG_DEBUG("Here");
return FLASHD_EraseEntireBank(pPrivate);
}
LOG_INFO("sam4 does not auto-erase while programming (Erasing relevant sectors)");
- LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", (unsigned int)(first), (unsigned int)(last));
- for (i = first; i <= last; i++) {
+ LOG_INFO("sam4 First: 0x%08x Last: 0x%08x", first, last);
+ for (unsigned int i = first; i <= last; i++) {
/*16 pages equals 8KB - Same size as a lock region*/
r = FLASHD_ErasePages(pPrivate, (i * pageCount), pageCount, &status);
- LOG_INFO("Erasing sector: 0x%08x", (unsigned int)(i));
+ LOG_INFO("Erasing sector: 0x%08x", i);
if (r != ERROR_OK)
- LOG_ERROR("SAM4: Error performing Erase page @ lock region number %d",
- (unsigned int)(i));
+ LOG_ERROR("SAM4: Error performing Erase page @ lock region number %u",
+ i);
if (status & (1 << 2)) {
- LOG_ERROR("SAM4: Lock Region %d is locked", (unsigned int)(i));
+ LOG_ERROR("SAM4: Lock Region %u is locked", i);
return ERROR_FAIL;
}
if (status & (1 << 1)) {
- LOG_ERROR("SAM4: Flash Command error @lock region %d", (unsigned int)(i));
+ LOG_ERROR("SAM4: Flash Command error @lock region %u", i);
return ERROR_FAIL;
}
}
@@ -2746,7 +2745,8 @@ static int sam4_erase(struct flash_bank *bank, int first, int last)
return ERROR_OK;
}
-static int sam4_protect(struct flash_bank *bank, int set, int first, int last)
+static int sam4_protect(struct flash_bank *bank, int set, unsigned int first,
+ unsigned int last)
{
struct sam4_bank_private *pPrivate;
int r;
@@ -2762,9 +2762,9 @@ static int sam4_protect(struct flash_bank *bank, int set, int first, int last)
return ERROR_FLASH_BANK_NOT_PROBED;
if (set)
- r = FLASHD_Lock(pPrivate, (unsigned)(first), (unsigned)(last));
+ r = FLASHD_Lock(pPrivate, first, last);
else
- r = FLASHD_Unlock(pPrivate, (unsigned)(first), (unsigned)(last));
+ r = FLASHD_Unlock(pPrivate, first, last);
LOG_DEBUG("End: r=%d", r);
return r;
diff --git a/src/flash/nor/at91sam4l.c b/src/flash/nor/at91sam4l.c
index d4bfe5310..4ee4ff853 100644
--- a/src/flash/nor/at91sam4l.c
+++ b/src/flash/nor/at91sam4l.c
@@ -125,7 +125,7 @@ struct sam4l_info {
uint32_t page_size;
int num_pages;
int sector_size;
- int pages_per_sector;
+ unsigned int pages_per_sector;
bool probed;
struct target *target;
@@ -335,7 +335,7 @@ static int sam4l_probe(struct flash_bank *bank)
/* Fill out the sector information: all SAM4L sectors are the same size and
* there is always a fixed number of them. */
- for (int i = 0; i < bank->num_sectors; i++) {
+ for (unsigned int i = 0; i < bank->num_sectors; i++) {
bank->sectors[i].size = chip->sector_size;
bank->sectors[i].offset = i * chip->sector_size;
/* mark as unknown */
@@ -375,13 +375,14 @@ static int sam4l_protect_check(struct flash_bank *bank)
return res;
st >>= 16; /* There are 16 lock region bits in the upper half word */
- for (int i = 0; i < bank->num_sectors; i++)
- bank->sectors[i].is_protected = !!(st & (1<<i));
+ for (unsigned int i = 0; i < bank->num_sectors; i++)
+ bank->sectors[i].is_protected = !!(st & (1<<i));
return ERROR_OK;
}
-static int sam4l_protect(struct flash_bank *bank, int set, int first, int last)
+static int sam4l_protect(struct flash_bank *bank, int set, unsigned int first,
+ unsigned int last)
{
struct sam4l_info *chip = (struct sam4l_info *)bank->driver_priv;
@@ -398,7 +399,7 @@ static int sam4l_protect(struct flash_bank *bank, int set, int first, int last)
/* Make sure the pages make sense. */
if (first >= bank->num_sectors || last >= bank->num_sectors) {
- LOG_ERROR("Protect range %d - %d not valid (%d sectors total)", first, last,
+ LOG_ERROR("Protect range %u - %u not valid (%u sectors total)", first, last,
bank->num_sectors);
return ERROR_FAIL;
}
@@ -406,7 +407,7 @@ static int sam4l_protect(struct flash_bank *bank, int set, int first, int last)
/* Try to lock or unlock each sector in the range. This is done by locking
* a region containing one page in that sector, we arbitrarily choose the 0th
* page in the sector. */
- for (int i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
int res;
res = sam4l_flash_command(bank->target,
@@ -420,7 +421,8 @@ static int sam4l_protect(struct flash_bank *bank, int set, int first, int last)
return ERROR_OK;
}
-static int sam4l_erase(struct flash_bank *bank, int first, int last)
+static int sam4l_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
int ret;
struct sam4l_info *chip = (struct sam4l_info *)bank->driver_priv;
@@ -438,7 +440,7 @@ static int sam4l_erase(struct flash_bank *bank, int first, int last)
/* Make sure the pages make sense. */
if (first >= bank->num_sectors || last >= bank->num_sectors) {
- LOG_ERROR("Erase range %d - %d not valid (%d sectors total)", first, last,
+ LOG_ERROR("Erase range %u - %u not valid (%u sectors total)", first, last,
bank->num_sectors);
return ERROR_FAIL;
}
@@ -453,19 +455,19 @@ static int sam4l_erase(struct flash_bank *bank, int first, int last)
return ret;
}
} else {
- LOG_DEBUG("Erasing sectors %d through %d...\n", first, last);
+ LOG_DEBUG("Erasing sectors %u through %u...\n", first, last);
/* For each sector... */
- for (int i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
/* For each page in that sector... */
- for (int j = 0; j < chip->pages_per_sector; j++) {
- int pn = i * chip->pages_per_sector + j;
+ for (unsigned int j = 0; j < chip->pages_per_sector; j++) {
+ unsigned int pn = i * chip->pages_per_sector + j;
bool is_erased = false;
/* Issue the page erase */
ret = sam4l_flash_command(bank->target, SAM4L_FCMD_EP, pn);
if (ret != ERROR_OK) {
- LOG_ERROR("Erasing page %d failed", pn);
+ LOG_ERROR("Erasing page %u failed", pn);
return ret;
}
@@ -474,7 +476,7 @@ static int sam4l_erase(struct flash_bank *bank, int first, int last)
return ret;
if (!is_erased) {
- LOG_DEBUG("Page %d was not erased.", pn);
+ LOG_DEBUG("Page %u was not erased.", pn);
return ERROR_FAIL;
}
}
diff --git a/src/flash/nor/at91sam7.c b/src/flash/nor/at91sam7.c
index 039746c16..7dfdf0d29 100644
--- a/src/flash/nor/at91sam7.c
+++ b/src/flash/nor/at91sam7.c
@@ -702,17 +702,15 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
uint32_t bank_size;
uint32_t ext_freq = 0;
- int chip_width;
- int bus_width;
- int banks_num;
- int num_sectors;
+ unsigned int chip_width;
+ unsigned int bus_width;
+ unsigned int banks_num;
+ unsigned int num_sectors;
uint16_t pages_per_sector;
uint16_t page_size;
uint16_t num_nvmbits;
- int bnk, sec;
-
at91sam7_info = malloc(sizeof(struct at91sam7_flash_bank));
t_bank->driver_priv = at91sam7_info;
@@ -729,11 +727,11 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], base_address);
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[3], chip_width);
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[4], bus_width);
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[3], chip_width);
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[4], bus_width);
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[8], banks_num);
- COMMAND_PARSE_NUMBER(int, CMD_ARGV[9], num_sectors);
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[8], banks_num);
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[9], num_sectors);
COMMAND_PARSE_NUMBER(u16, CMD_ARGV[10], pages_per_sector);
COMMAND_PARSE_NUMBER(u16, CMD_ARGV[11], page_size);
COMMAND_PARSE_NUMBER(u16, CMD_ARGV[12], num_nvmbits);
@@ -754,7 +752,7 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
/* calculate bank size */
bank_size = num_sectors * pages_per_sector * page_size;
- for (bnk = 0; bnk < banks_num; bnk++) {
+ for (unsigned int bnk = 0; bnk < banks_num; bnk++) {
if (bnk > 0) {
if (!t_bank->next) {
/* create a new bank element */
@@ -780,7 +778,7 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
/* allocate sectors */
t_bank->sectors = malloc(num_sectors * sizeof(struct flash_sector));
- for (sec = 0; sec < num_sectors; sec++) {
+ for (unsigned int sec = 0; sec < num_sectors; sec++) {
t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
t_bank->sectors[sec].size = pages_per_sector * page_size;
t_bank->sectors[sec].is_erased = -1;
@@ -801,10 +799,10 @@ FLASH_BANK_COMMAND_HANDLER(at91sam7_flash_bank_command)
return ERROR_OK;
}
-static int at91sam7_erase(struct flash_bank *bank, int first, int last)
+static int at91sam7_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
- int sec;
uint32_t nbytes, pos;
uint8_t *buffer;
uint8_t erase_all;
@@ -817,7 +815,7 @@ static int at91sam7_erase(struct flash_bank *bank, int first, int last)
return ERROR_TARGET_NOT_HALTED;
}
- if ((first < 0) || (last < first) || (last >= bank->num_sectors))
+ if ((last < first) || (last >= bank->num_sectors))
return ERROR_FLASH_SECTOR_INVALID;
erase_all = 0;
@@ -847,16 +845,16 @@ static int at91sam7_erase(struct flash_bank *bank, int first, int last)
}
/* mark erased sectors */
- for (sec = first; sec <= last; sec++)
+ for (unsigned int sec = first; sec <= last; sec++)
bank->sectors[sec].is_erased = 1;
return ERROR_OK;
}
-static int at91sam7_protect(struct flash_bank *bank, int set, int first, int last)
+static int at91sam7_protect(struct flash_bank *bank, int set,
+ unsigned int first, unsigned int last)
{
uint32_t cmd;
- int sector;
uint32_t pagen;
struct at91sam7_flash_bank *at91sam7_info = bank->driver_priv;
@@ -869,14 +867,14 @@ static int at91sam7_protect(struct flash_bank *bank, int set, int first, int las
return ERROR_TARGET_NOT_HALTED;
}
- if ((first < 0) || (last < first) || (last >= bank->num_sectors))
+ if ((last < first) || (last >= bank->num_sectors))
return ERROR_FLASH_SECTOR_INVALID;
/* Configure the flash controller timing */
at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
- for (sector = first; sector <= last; sector++) {
+ for (unsigned int sector = first; sector <= last; sector++) {
if (set)
cmd = SLB;
else
@@ -956,7 +954,7 @@ static int at91sam7_write(struct flash_bank *bank, const uint8_t *buffer, uint32
/* Send Write Page command to Flash Controller */
if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)
return ERROR_FLASH_OPERATION_FAILED;
- LOG_DEBUG("Write flash bank:%i page number:%" PRIi32 "", bank->bank_number, pagen);
+ LOG_DEBUG("Write flash bank:%u page number:%" PRIi32 "", bank->bank_number, pagen);
}
return ERROR_OK;
@@ -1018,7 +1016,7 @@ static int get_at91sam7_info(struct flash_bank *bank, char *buf, int buf_size)
printed = snprintf(buf,
buf_size,
- " Pagesize: %i bytes | Lockbits(%i): %i 0x%4.4x | Pages in lock region: %i\n",
+ " Pagesize: %i bytes | Lockbits(%u): %i 0x%4.4x | Pages in lock region: %i\n",
at91sam7_info->pagesize,
bank->num_sectors,
at91sam7_info->num_lockbits_on,
diff --git a/src/flash/nor/at91samd.c b/src/flash/nor/at91samd.c
index 6e89099ab..0bd5f5995 100644
--- a/src/flash/nor/at91samd.c
+++ b/src/flash/nor/at91samd.c
@@ -398,7 +398,7 @@ static const struct samd_part *samd_find_part(uint32_t id)
static int samd_protect_check(struct flash_bank *bank)
{
- int res, prot_block;
+ int res;
uint16_t lock;
res = target_read_u16(bank->target,
@@ -407,7 +407,7 @@ static int samd_protect_check(struct flash_bank *bank)
return res;
/* Lock bits are active-low */
- for (prot_block = 0; prot_block < bank->num_prot_blocks; prot_block++)
+ for (unsigned int prot_block = 0; prot_block < bank->num_prot_blocks; prot_block++)
bank->prot_blocks[prot_block].is_protected = !(lock & (1u<<prot_block));
return ERROR_OK;
@@ -725,10 +725,10 @@ static int samd_modify_user_row(struct target *target, uint64_t value,
return samd_modify_user_row_masked(target, value << startb, mask);
}
-static int samd_protect(struct flash_bank *bank, int set, int first_prot_bl, int last_prot_bl)
+static int samd_protect(struct flash_bank *bank, int set,
+ unsigned int first, unsigned int last)
{
int res = ERROR_OK;
- int prot_block;
/* We can issue lock/unlock region commands with the target running but
* the settings won't persist unless we're able to modify the LOCK regions
@@ -738,7 +738,7 @@ static int samd_protect(struct flash_bank *bank, int set, int first_prot_bl, int
return ERROR_TARGET_NOT_HALTED;
}
- for (prot_block = first_prot_bl; prot_block <= last_prot_bl; prot_block++) {
+ for (unsigned int prot_block = first; prot_block <= last; prot_block++) {
if (set != bank->prot_blocks[prot_block].is_protected) {
/* Load an address that is within this protection block (we use offset 0) */
res = target_write_u32(bank->target,
@@ -763,7 +763,7 @@ static int samd_protect(struct flash_bank *bank, int set, int first_prot_bl, int
res = samd_modify_user_row(bank->target,
set ? (uint64_t)0 : (uint64_t)UINT64_MAX,
- 48 + first_prot_bl, 48 + last_prot_bl);
+ 48 + first, 48 + last);
if (res != ERROR_OK)
LOG_WARNING("SAMD: protect settings were not made persistent!");
@@ -775,9 +775,10 @@ exit:
return res;
}
-static int samd_erase(struct flash_bank *bank, int first_sect, int last_sect)
+static int samd_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
- int res, s;
+ int res;
struct samd_info *chip = (struct samd_info *)bank->driver_priv;
if (bank->target->state != TARGET_HALTED) {
@@ -792,7 +793,7 @@ static int samd_erase(struct flash_bank *bank, int first_sect, int last_sect)
}
/* For each sector to be erased */
- for (s = first_sect; s <= last_sect; s++) {
+ for (unsigned int s = first; s <= last; s++) {
res = samd_erase_row(bank->target, bank->sectors[s].offset);
if (res != ERROR_OK) {
LOG_ERROR("SAMD: failed to erase sector %d at 0x%08" PRIx32, s, bank->sectors[s].offset);
diff --git a/src/flash/nor/ath79.c b/src/flash/nor/ath79.c
index c551f2722..88ebbf23c 100644
--- a/src/flash/nor/ath79.c
+++ b/src/flash/nor/ath79.c
@@ -498,21 +498,21 @@ static int ath79_erase_sector(struct flash_bank *bank, int sector)
return wait_till_ready(bank, ATH79_MAX_TIMEOUT);
}
-static int ath79_erase(struct flash_bank *bank, int first, int last)
+static int ath79_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
struct ath79_flash_bank *ath79_info = bank->driver_priv;
int retval = ERROR_OK;
- int sector;
- LOG_DEBUG("%s: from sector %d to sector %d", __func__, first, last);
+ LOG_DEBUG("%s: from sector %u to sector %u", __func__, first, last);
if (target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
- if ((first < 0) || (last < first) || (last >= bank->num_sectors)) {
+ if ((last < first) || (last >= bank->num_sectors)) {
LOG_ERROR("Flash sector invalid");
return ERROR_FLASH_SECTOR_INVALID;
}
@@ -525,14 +525,14 @@ static int ath79_erase(struct flash_bank *bank, int first, int last)
if (ath79_info->dev->erase_cmd == 0x00)
return ERROR_FLASH_OPER_UNSUPPORTED;
- for (sector = first; sector <= last; sector++) {
+ for (unsigned sector = first; sector <= last; sector++) {
if (bank->sectors[sector].is_protected) {
- LOG_ERROR("Flash sector %d protected", sector);
+ LOG_ERROR("Flash sector %u protected", sector);
return ERROR_FAIL;
}
}
- for (sector = first; sector <= last; sector++) {
+ for (unsigned int sector = first; sector <= last; sector++) {
retval = ath79_erase_sector(bank, sector);
if (retval != ERROR_OK)
break;
@@ -542,12 +542,10 @@ static int ath79_erase(struct flash_bank *bank, int first, int last)
return retval;
}
-static int ath79_protect(struct flash_bank *bank, int set,
- int first, int last)
+static int ath79_protect(struct flash_bank *bank, int set, unsigned int first,
+ unsigned int last)
{
- int sector;
-
- for (sector = first; sector <= last; sector++)
+ for (unsigned int sector = first; sector <= last; sector++)
bank->sectors[sector].is_protected = set;
return ERROR_OK;
}
@@ -648,7 +646,6 @@ static int ath79_write(struct flash_bank *bank, const uint8_t *buffer,
uint32_t offset, uint32_t count)
{
struct target *target = bank->target;
- int sector;
LOG_DEBUG("%s: offset=0x%08" PRIx32 " count=0x%08" PRIx32,
__func__, offset, count);
@@ -664,7 +661,7 @@ static int ath79_write(struct flash_bank *bank, const uint8_t *buffer,
}
/* Check sector protection */
- for (sector = 0; sector < bank->num_sectors; sector++) {
+ for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
/* Start offset in or before this sector? */
/* End offset in or behind this sector? */
struct flash_sector *bs = &bank->sectors[sector];
@@ -672,7 +669,7 @@ static int ath79_write(struct flash_bank *bank, const uint8_t *buffer,
if ((offset < (bs->offset + bs->size)) &&
((offset + count - 1) >= bs->offset) &&
bs->is_protected) {
- LOG_ERROR("Flash sector %d protected", sector);
+ LOG_ERROR("Flash sector %u protected", sector);
return ERROR_FAIL;
}
}
@@ -845,7 +842,7 @@ static int ath79_probe(struct flash_bank *bank)
return ERROR_FAIL;
}
- for (int sector = 0; sector < bank->num_sectors; sector++) {
+ for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
sectors[sector].offset = sector * sectorsize;
sectors[sector].size = sectorsize;
sectors[sector].is_erased = 0;
diff --git a/src/flash/nor/atsame5.c b/src/flash/nor/atsame5.c
index baa86acd0..ab79e8cf7 100644
--- a/src/flash/nor/atsame5.c
+++ b/src/flash/nor/atsame5.c
@@ -231,7 +231,7 @@ static const struct samd_part *samd_find_part(uint32_t id)
static int same5_protect_check(struct flash_bank *bank)
{
- int res, prot_block;
+ int res;
uint32_t lock;
res = target_read_u32(bank->target,
@@ -240,7 +240,7 @@ static int same5_protect_check(struct flash_bank *bank)
return res;
/* Lock bits are active-low */
- for (prot_block = 0; prot_block < bank->num_prot_blocks; prot_block++)
+ for (unsigned int prot_block = 0; prot_block < bank->num_prot_blocks; prot_block++)
bank->prot_blocks[prot_block].is_protected = !(lock & (1u<<prot_block));
return ERROR_OK;
@@ -569,10 +569,10 @@ static int same5_modify_user_row(struct target *target, uint32_t value,
buf_val, buf_mask, 0, 8);
}
-static int same5_protect(struct flash_bank *bank, int set, int first_prot_bl, int last_prot_bl)
+static int same5_protect(struct flash_bank *bank, int set, unsigned int first,
+ unsigned int last)
{
int res = ERROR_OK;
- int prot_block;
/* We can issue lock/unlock region commands with the target running but
* the settings won't persist unless we're able to modify the LOCK regions
@@ -582,7 +582,7 @@ static int same5_protect(struct flash_bank *bank, int set, int first_prot_bl, in
return ERROR_TARGET_NOT_HALTED;
}
- for (prot_block = first_prot_bl; prot_block <= last_prot_bl; prot_block++) {
+ for (unsigned int prot_block = first; prot_block <= last; prot_block++) {
if (set != bank->prot_blocks[prot_block].is_protected) {
/* Load an address that is within this protection block (we use offset 0) */
res = target_write_u32(bank->target,
@@ -606,7 +606,7 @@ static int same5_protect(struct flash_bank *bank, int set, int first_prot_bl, in
const uint8_t unlock[4] = { 0xff, 0xff, 0xff, 0xff };
uint8_t mask[4] = { 0, 0, 0, 0 };
- buf_set_u32(mask, first_prot_bl, last_prot_bl + 1 - first_prot_bl, 0xffffffff);
+ buf_set_u32(mask, first, last + 1 - first, 0xffffffff);
res = same5_modify_user_row_masked(bank->target,
set ? lock : unlock, mask, 8, 4);
@@ -621,9 +621,10 @@ exit:
return res;
}
-static int same5_erase(struct flash_bank *bank, int first_sect, int last_sect)
+static int same5_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
- int res, s;
+ int res;
struct samd_info *chip = (struct samd_info *)bank->driver_priv;
if (bank->target->state != TARGET_HALTED) {
@@ -636,7 +637,7 @@ static int same5_erase(struct flash_bank *bank, int first_sect, int last_sect)
return ERROR_FLASH_BANK_NOT_PROBED;
/* For each sector to be erased */
- for (s = first_sect; s <= last_sect; s++) {
+ for (unsigned int s = first; s <= last; s++) {
res = same5_erase_block(bank->target, bank->sectors[s].offset);
if (res != ERROR_OK) {
LOG_ERROR("SAM: failed to erase sector %d at 0x%08" PRIx32, s, bank->sectors[s].offset);
diff --git a/src/flash/nor/atsamv.c b/src/flash/nor/atsamv.c
index 9a53369a7..13d1d263f 100644
--- a/src/flash/nor/atsamv.c
+++ b/src/flash/nor/atsamv.c
@@ -328,7 +328,7 @@ static int samv_protect_check(struct flash_bank *bank)
if (r != ERROR_OK)
return r;
- for (int x = 0; x < bank->num_sectors; x++)
+ for (unsigned int x = 0; x < bank->num_sectors; x++)
bank->sectors[x].is_protected = (!!(v[x >> 5] & (1 << (x % 32))));
return ERROR_OK;
}
@@ -384,7 +384,7 @@ static int samv_probe(struct flash_bank *bank)
bank->base = SAMV_FLASH_BASE;
bank->num_sectors = bank->size / SAMV_SECTOR_SIZE;
bank->sectors = calloc(bank->num_sectors, sizeof(struct flash_sector));
- for (int s = 0; s < (int)bank->num_sectors; s++) {
+ for (unsigned int s = 0; s < bank->num_sectors; s++) {
bank->sectors[s].size = SAMV_SECTOR_SIZE;
bank->sectors[s].offset = s * SAMV_SECTOR_SIZE;
bank->sectors[s].is_erased = -1;
@@ -406,7 +406,8 @@ static int samv_auto_probe(struct flash_bank *bank)
return samv_probe(bank);
}
-static int samv_erase(struct flash_bank *bank, int first, int last)
+static int samv_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
const int page_count = 32; /* 32 pages equals 16 KB lock region */
@@ -420,31 +421,31 @@ static int samv_erase(struct flash_bank *bank, int first, int last)
return r;
/* easy case: we've been requested to erase the entire flash */
- if ((first == 0) && ((last + 1) == (int)(bank->num_sectors)))
+ if ((first == 0) && ((last + 1) == bank->num_sectors))
return samv_efc_perform_command(bank->target, SAMV_EFC_FCMD_EA, 0, NULL);
- LOG_INFO("erasing lock regions %d-%d...", first, last);
+ LOG_INFO("erasing lock regions %u-%u...", first, last);
- for (int i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
uint32_t status;
r = samv_erase_pages(bank->target, (i * page_count), page_count, &status);
- LOG_INFO("erasing lock region %d", i);
+ LOG_INFO("erasing lock region %u", i);
if (r != ERROR_OK)
- LOG_ERROR("error performing erase page @ lock region number %d",
- (unsigned int)(i));
+ LOG_ERROR("error performing erase page @ lock region number %u", i);
if (status & (1 << 2)) {
- LOG_ERROR("lock region %d is locked", (unsigned int)(i));
+ LOG_ERROR("lock region %u is locked", i);
return ERROR_FAIL;
}
if (status & (1 << 1)) {
- LOG_ERROR("flash command error @lock region %d", (unsigned int)(i));
+ LOG_ERROR("flash command error @lock region %u", i);
return ERROR_FAIL;
}
}
return ERROR_OK;
}
-static int samv_protect(struct flash_bank *bank, int set, int first, int last)
+static int samv_protect(struct flash_bank *bank, int set, unsigned int first,
+ unsigned int last)
{
if (bank->target->state != TARGET_HALTED) {
LOG_ERROR("Target not halted");
@@ -453,9 +454,9 @@ static int samv_protect(struct flash_bank *bank, int set, int first, int last)
int r;
if (set)
- r = samv_flash_lock(bank->target, (unsigned)(first), (unsigned)(last));
+ r = samv_flash_lock(bank->target, first, last);
else
- r = samv_flash_unlock(bank->target, (unsigned)(first), (unsigned)(last));
+ r = samv_flash_unlock(bank->target, first, last);
return r;
}
diff --git a/src/flash/nor/avrf.c b/src/flash/nor/avrf.c
index 93f6872bd..4ec1161af 100644
--- a/src/flash/nor/avrf.c
+++ b/src/flash/nor/avrf.c
@@ -218,7 +218,8 @@ FLASH_BANK_COMMAND_HANDLER(avrf_flash_bank_command)
return ERROR_OK;
}
-static int avrf_erase(struct flash_bank *bank, int first, int last)
+static int avrf_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
struct avr_common *avr = target->arch_info;
@@ -442,7 +443,7 @@ COMMAND_HANDLER(avrf_handle_mass_erase_command)
if (avrf_mass_erase(bank) == ERROR_OK) {
/* set all sectors as erased */
- for (int i = 0; i < bank->num_sectors; i++)
+ for (unsigned int i = 0; i < bank->num_sectors; i++)
bank->sectors[i].is_erased = 1;
command_print(CMD, "avr mass erase complete");
diff --git a/src/flash/nor/bluenrg-x.c b/src/flash/nor/bluenrg-x.c
index fbce20d55..232f6ba0a 100644
--- a/src/flash/nor/bluenrg-x.c
+++ b/src/flash/nor/bluenrg-x.c
@@ -123,12 +123,13 @@ static inline int bluenrgx_write_flash_reg(struct flash_bank *bank, uint32_t reg
return target_write_u32(bank->target, bluenrgx_get_flash_reg(bank, reg_offset), value);
}
-static int bluenrgx_erase(struct flash_bank *bank, int first, int last)
+static int bluenrgx_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
int retval = ERROR_OK;
struct bluenrgx_flash_bank *bluenrgx_info = bank->driver_priv;
- int num_sectors = (last - first + 1);
- int mass_erase = (num_sectors == bank->num_sectors);
+ unsigned int num_sectors = (last - first + 1);
+ const bool mass_erase = (num_sectors == bank->num_sectors);
struct target *target = bank->target;
uint32_t address, command;
@@ -181,9 +182,9 @@ static int bluenrgx_erase(struct flash_bank *bank, int first, int last)
} else {
command = FLASH_CMD_ERASE_PAGE;
- for (int i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
address = bank->base+i*FLASH_PAGE_SIZE(bluenrgx_info);
- LOG_DEBUG("address = %08x, index = %d", address, i);
+ LOG_DEBUG("address = %08x, index = %u", address, i);
if (bluenrgx_write_flash_reg(bank, FLASH_REG_IRQRAW, 0x3f) != ERROR_OK) {
LOG_ERROR("Register write failed");
@@ -399,7 +400,7 @@ static int bluenrgx_probe(struct flash_bank *bank)
bank->num_sectors = bank->size/FLASH_PAGE_SIZE(bluenrgx_info);
bank->sectors = realloc(bank->sectors, sizeof(struct flash_sector) * bank->num_sectors);
- for (int i = 0; i < bank->num_sectors; i++) {
+ for (unsigned int i = 0; i < bank->num_sectors; i++) {
bank->sectors[i].offset = i * FLASH_PAGE_SIZE(bluenrgx_info);
bank->sectors[i].size = FLASH_PAGE_SIZE(bluenrgx_info);
bank->sectors[i].is_erased = -1;
diff --git a/src/flash/nor/cc26xx.c b/src/flash/nor/cc26xx.c
index 176211a07..f0a855074 100644
--- a/src/flash/nor/cc26xx.c
+++ b/src/flash/nor/cc26xx.c
@@ -264,7 +264,8 @@ FLASH_BANK_COMMAND_HANDLER(cc26xx_flash_bank_command)
return ERROR_OK;
}
-static int cc26xx_erase(struct flash_bank *bank, int first, int last)
+static int cc26xx_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
struct cc26xx_bank *cc26xx_bank = bank->driver_priv;
diff --git a/src/flash/nor/cc3220sf.c b/src/flash/nor/cc3220sf.c
index c8de7d002..5e88aa61b 100644
--- a/src/flash/nor/cc3220sf.c
+++ b/src/flash/nor/cc3220sf.c
@@ -106,7 +106,8 @@ FLASH_BANK_COMMAND_HANDLER(cc3220sf_flash_bank_command)
return ERROR_OK;
}
-static int cc3220sf_erase(struct flash_bank *bank, int first, int last)
+static int cc3220sf_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct target *target = bank->target;
bool done;
@@ -129,7 +130,7 @@ static int cc3220sf_erase(struct flash_bank *bank, int first, int last)
}
/* Erase requested sectors one by one */
- for (int i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
/* Determine address of sector to erase */
address = FLASH_BASE_ADDR + i * FLASH_SECTOR_SIZE;
@@ -431,7 +432,7 @@ static int cc3220sf_probe(struct flash_bank *bank)
uint32_t base;
uint32_t size;
- int num_sectors;
+ unsigned int num_sectors;
base = FLASH_BASE_ADDR;
size = FLASH_NUM_SECTORS * FLASH_SECTOR_SIZE;
@@ -452,7 +453,7 @@ static int cc3220sf_probe(struct flash_bank *bank)
bank->write_end_alignment = 0;
bank->num_sectors = num_sectors;
- for (int i = 0; i < num_sectors; i++) {
+ for (unsigned int i = 0; i < num_sectors; i++) {
bank->sectors[i].offset = i * FLASH_SECTOR_SIZE;
bank->sectors[i].size = FLASH_SECTOR_SIZE;
bank->sectors[i].is_erased = -1;
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 50ab207c1..19fb6b2c2 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -162,10 +162,10 @@ static void cfi_command(struct flash_bank *bank, uint8_t cmd, uint8_t *cmd_buf)
cmd_buf[i] = 0;
if (cfi_info->endianness == TARGET_LITTLE_ENDIAN) {
- for (int i = bank->bus_width; i > 0; i--)
+ for (unsigned int i = bank->bus_width; i > 0; i--)
*cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
} else {
- for (int i = 1; i <= bank->bus_width; i++)
+ for (unsigned int i = 1; i <= bank->bus_width; i++)
*cmd_buf++ = (i & (bank->chip_width - 1)) ? 0x0 : cmd;
}
}
@@ -217,13 +217,13 @@ static int cfi_get_u8(struct flash_bank *bank, int sector, uint32_t offset, uint
return retval;
if (cfi_info->endianness == TARGET_LITTLE_ENDIAN) {
- for (int i = 0; i < bank->bus_width / bank->chip_width; i++)
+ for (unsigned int i = 0; i < bank->bus_width / bank->chip_width; i++)
data[0] |= data[i];
*val = data[0];
} else {
uint8_t value = 0;
- for (int i = 0; i < bank->bus_width / bank->chip_width; i++)
+ for (unsigned int i = 0; i < bank->bus_width / bank->chip_width; i++)
value |= data[bank->bus_width - 1 - i];
*val = value;
@@ -877,14 +877,15 @@ FLASH_BANK_COMMAND_HANDLER(cfi_flash_bank_command)
return cfi_flash_bank_cmd(bank, CMD_ARGC, CMD_ARGV);
}
-static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
+static int cfi_intel_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
cfi_intel_clear_status_register(bank);
- for (int i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
retval = cfi_send_command(bank, 0x20, cfi_flash_address(bank, i, 0x0));
if (retval != ERROR_OK)
return retval;
@@ -905,7 +906,7 @@ static int cfi_intel_erase(struct flash_bank *bank, int first, int last)
if (retval != ERROR_OK)
return retval;
- LOG_ERROR("couldn't erase block %i of flash bank at base "
+ LOG_ERROR("couldn't erase block %u of flash bank at base "
TARGET_ADDR_FMT, i, bank->base);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -931,13 +932,14 @@ int cfi_spansion_unlock_seq(struct flash_bank *bank)
return ERROR_OK;
}
-static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
+static int cfi_spansion_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
- for (int i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
retval = cfi_spansion_unlock_seq(bank);
if (retval != ERROR_OK)
return retval;
@@ -970,7 +972,8 @@ static int cfi_spansion_erase(struct flash_bank *bank, int first, int last)
return cfi_send_command(bank, 0xf0, cfi_flash_address(bank, 0, 0x0));
}
-int cfi_erase(struct flash_bank *bank, int first, int last)
+int cfi_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
@@ -979,7 +982,7 @@ int cfi_erase(struct flash_bank *bank, int first, int last)
return ERROR_TARGET_NOT_HALTED;
}
- if ((first < 0) || (last < first) || (last >= bank->num_sectors))
+ if ((last < first) || (last >= bank->num_sectors))
return ERROR_FLASH_SECTOR_INVALID;
if (cfi_info->qry[0] != 'Q')
@@ -999,7 +1002,8 @@ int cfi_erase(struct flash_bank *bank, int first, int last)
return ERROR_OK;
}
-static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int last)
+static int cfi_intel_protect(struct flash_bank *bank, int set,
+ unsigned int first, unsigned int last)
{
int retval;
struct cfi_flash_bank *cfi_info = bank->driver_priv;
@@ -1016,7 +1020,7 @@ static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int la
cfi_intel_clear_status_register(bank);
- for (int i = first; i <= last; i++) {
+ for (unsigned int i = first; i <= last; i++) {
retval = cfi_send_command(bank, 0x60, cfi_flash_address(bank, i, 0x0));
if (retval != ERROR_OK)
return retval;
@@ -1087,7 +1091,7 @@ static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int la
* 3. re-protect what should be protected.
*
*/
- for (int i = 0; i < bank->num_sectors; i++) {
+ for (unsigned int i = 0; i < bank->num_sectors; i++) {
if (bank->sectors[i].is_protected == 1) {
cfi_intel_clear_status_register(bank);
@@ -1110,7 +1114,8 @@ static int cfi_intel_protect(struct flash_bank *bank, int set, int first, int la
return cfi_send_command(bank, 0xff, cfi_flash_address(bank, 0, 0x0));
}
-int cfi_protect(struct flash_bank *bank, int set, int first, int last)
+int cfi_protect(struct flash_bank *bank, int set, unsigned int first,
+ unsigned int last)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
@@ -1146,7 +1151,7 @@ static uint32_t cfi_command_val(struct flash_bank *bank, uint8_t cmd)
case 4:
return target_buffer_get_u32(target, buf);
default:
- LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes",
+ LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes",
bank->bus_width);
return 0;
}
@@ -1266,7 +1271,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
target_code_size = sizeof(word_32_code);
break;
default:
- LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes",
+ LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes",
bank->bus_width);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
@@ -1502,7 +1507,7 @@ static int cfi_spansion_write_block_mips(struct flash_bank *bank, const uint8_t
}
break;
default:
- LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes",
+ LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes",
bank->bus_width);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
@@ -1881,7 +1886,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, const uint8_t *buff
target_code_size = sizeof(armv4_5_word_32_code);
break;
default:
- LOG_ERROR("Unsupported bank buswidth %d, can't do block memory writes",
+ LOG_ERROR("Unsupported bank buswidth %u, can't do block memory writes",
bank->bus_width);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
@@ -2286,7 +2291,7 @@ static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, u
return retval;
/* take only bytes we need */
- for (int i = align; (i < bank->bus_width) && (count > 0); i++, count--)
+ for (unsigned int i = align; (i < bank->bus_width) && (count > 0); i++, count--)
*buffer++ = current_word[i];
read_p += bank->bus_width;
@@ -2312,7 +2317,7 @@ static int cfi_read(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, u
return retval;
/* take only bytes we need */
- for (int i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
+ for (unsigned int i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
*buffer++ = current_word[i];
}
@@ -2355,9 +2360,7 @@ static int cfi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of
return retval;
/* replace only bytes that must be written */
- for (int i = align;
- (i < bank->bus_width) && (count > 0);
- i++, count--)
+ for (unsigned int i = align; (i < bank->bus_width) && (count > 0); i++, count--)
if (cfi_info->data_swap)
/* data bytes are swapped (reverse endianness) */
current_word[bank->bus_width - i] = *buffer++;
@@ -2440,7 +2443,7 @@ static int cfi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of
}
/* try the slow way? */
if (fallback) {
- for (int i = 0; i < bank->bus_width; i++)
+ for (unsigned int i = 0; i < bank->bus_width; i++)
current_word[i] = *buffer++;
retval = cfi_write_word(bank, current_word, write_p);
@@ -2475,7 +2478,7 @@ static int cfi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of
return retval;
/* replace only bytes that must be written */
- for (int i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
+ for (unsigned int i = 0; (i < bank->bus_width) && (count > 0); i++, count--)
if (cfi_info->data_swap)
/* data bytes are swapped (reverse endianness) */
current_word[bank->bus_width - i] = *buffer++;
@@ -2576,7 +2579,7 @@ int cfi_probe(struct flash_bank *bank)
{
struct cfi_flash_bank *cfi_info = bank->driver_priv;
struct target *target = bank->target;
- int num_sectors = 0;
+ unsigned int num_sectors = 0;
int sector = 0;
uint32_t unlock1 = 0x555;
uint32_t unlock2 = 0x2aa;
@@ -2640,7 +2643,7 @@ int cfi_probe(struct flash_bank *bank)
cfi_info->device_id = target_buffer_get_u32(target, value_buf1);
break;
default:
- LOG_ERROR("Unsupported bank chipwidth %d, can't probe memory",
+ LOG_ERROR("Unsupported bank chipwidth %u, can't probe memory",
bank->chip_width);
return ERROR_FLASH_OPERATION_FAILED;
}
@@ -2928,7 +2931,7 @@ static int cfi_intel_protect_check(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
- for (int i = 0; i < bank->num_sectors; i++) {
+ for (unsigned int i = 0; i < bank->num_sectors; i++) {
uint8_t block_status;
retval = cfi_get_u8(bank, i, 0x2, &block_status);
if (retval != ERROR_OK)
@@ -2957,7 +2960,7 @@ static int cfi_spansion_protect_check(struct flash_bank *bank)
if (retval != ERROR_OK)
return retval;
- for (int i = 0; i < bank->num_sectors; i++) {
+ for (unsigned int i = 0; i < bank->num_sectors; i++) {
uint8_t block_status;
retval = cfi_get_u8(bank, i, 0x2, &block_status);
if (retval != ERROR_OK)
diff --git a/src/flash/nor/cfi.h b/src/flash/nor/cfi.h
index aef7a04f9..effa1d5c0 100644
--- a/src/flash/nor/cfi.h
+++ b/src/flash/nor/cfi.h
@@ -154,8 +154,9 @@ struct cfi_fixup {
const void *param;
};
-int cfi_erase(struct flash_bank *bank, int first, int last);
-int cfi_protect(struct flash_bank *bank, int set, int first, int last);
+int cfi_erase(struct flash_bank *bank, unsigned int first, unsigned int last);
+int cfi_protect(struct flash_bank *bank, int set, unsigned int first,
+ unsigned int last);
int cfi_probe(struct flash_bank *bank);
int cfi_auto_probe(struct flash_bank *bank);
int cfi_protect_check(struct flash_bank *bank);
diff --git a/src/flash/nor/core.c b/src/flash/nor/core.c
index 043ff13c8..b1a36623d 100644
--- a/src/flash/nor/core.c
+++ b/src/flash/nor/core.c
@@ -37,21 +37,23 @@
static struct flash_bank *flash_banks;
-int flash_driver_erase(struct flash_bank *bank, int first, int last)
+int flash_driver_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
int retval;
retval = bank->driver->erase(bank, first, last);
if (retval != ERROR_OK)
- LOG_ERROR("failed erasing sectors %d to %d", first, last);
+ LOG_ERROR("failed erasing sectors %u to %u", first, last);
return retval;
}
-int flash_driver_protect(struct flash_bank *bank, int set, int first, int last)
+int flash_driver_protect(struct flash_bank *bank, int set, unsigned int first,
+ unsigned int last)
{
int retval;
- int num_blocks;
+ unsigned int num_blocks;
if (bank->num_prot_blocks)
num_blocks = bank->num_prot_blocks;
@@ -60,7 +62,7 @@ int flash_driver_protect(struct flash_bank *bank, int set, int first, int last)
/* callers may not supply illegal parameters ... */
- if (first < 0 || first > last || last >= num_blocks) {
+ if (first > last || last >= num_blocks) {
LOG_ERROR("illegal protection block range");
return ERROR_FAIL;
}
@@ -86,7 +88,7 @@ int flash_driver_protect(struct flash_bank *bank, int set, int first, int last)
*/
retval = bank->driver->protect(bank, set, first, last);
if (retval != ERROR_OK)
- LOG_ERROR("failed setting protection for blocks %d to %d", first, last);
+ LOG_ERROR("failed setting protection for blocks %u to %u", first, last);
return retval;
}
@@ -157,10 +159,10 @@ struct flash_bank *flash_bank_list(void)
return flash_banks;
}
-struct flash_bank *get_flash_bank_by_num_noprobe(int num)
+struct flash_bank *get_flash_bank_by_num_noprobe(unsigned int num)
{
struct flash_bank *p;
- int i = 0;
+ unsigned int i = 0;
for (p = flash_banks; p; p = p->next) {
if (i++ == num)
@@ -170,10 +172,10 @@ struct flash_bank *get_flash_bank_by_num_noprobe(int num)
return NULL;
}
-int flash_get_bank_count(void)
+unsigned int flash_get_bank_count(void)
{
struct flash_bank *p;
- int i = 0;
+ unsigned int i = 0;
for (p = flash_banks; p; p = p->next)
i++;
return i;
@@ -249,7 +251,7 @@ int get_flash_bank_by_name(const char *name, struct flash_bank **bank_result)
return ERROR_OK;
}
-int get_flash_bank_by_num(int num, struct flash_bank **bank)
+int get_flash_bank_by_num(unsigned int num, struct flash_bank **bank)
{
struct flash_bank *p = get_flash_bank_by_num_noprobe(num);
int retval;
@@ -306,7 +308,6 @@ static int default_flash_mem_blank_check(struct flash_bank *bank)
{
struct target *target = bank->target;
const int buffer_size = 1024;
- int i;
uint32_t nBytes;
int retval = ERROR_OK;
@@ -317,7 +318,7 @@ static int default_flash_mem_blank_check(struct flash_bank *bank)
uint8_t *buffer = malloc(buffer_size);
- for (i = 0; i < bank->num_sectors; i++) {
+ for (unsigned int i = 0; i < bank->num_sectors; i++) {
uint32_t j;
bank->sectors[i].is_erased = 1;
@@ -353,7 +354,6 @@ done:
int default_flash_blank_check(struct flash_bank *bank)
{
struct target *target = bank->target;
- int i;
int retval;
if (bank->target->state != TARGET_HALTED) {
@@ -366,14 +366,14 @@ int default_flash_blank_check(struct flash_bank *bank)
if (block_array == NULL)
return default_flash_mem_blank_check(bank);
- for (i = 0; i < bank->num_sectors; i++) {
+ for (unsigned int i = 0; i < bank->num_sectors; i++) {
block_array[i].address = bank->base + bank->sectors[i].offset;
block_array[i].size = bank->sectors[i].size;
block_array[i].result = UINT32_MAX; /* erase state unknown */
}
bool fast_check = true;
- for (i = 0; i < bank->num_sectors; ) {
+ for (unsigned int i = 0; i < bank->num_sectors; ) {
retval = target_blank_check_memory(target,
block_array + i, bank->num_sectors - i,
bank->erased_value);
@@ -388,7 +388,7 @@ int default_flash_blank_check(struct flash_bank *bank)
}
if (fast_check) {
- for (i = 0; i < bank->num_sectors; i++)
+ for (unsigned int i = 0; i < bank->num_sectors; i++)
bank->sectors[i].is_erased = block_array[i].result;
retval = ERROR_OK;
} else {
@@ -418,7 +418,8 @@ int default_flash_blank_check(struct flash_bank *bank)
static int flash_iterate_address_range_inner(struct target *target,
char *pad_reason, target_addr_t addr, uint32_t length,
bool iterate_protect_blocks,
- int (*callback)(struct flash_bank *bank, int first, int last))
+ int (*callback)(struct flash_bank *bank, unsigned int first,
+ unsigned int last))
{
struct flash_bank *c;
struct flash_sector *block_array;
@@ -547,7 +548,8 @@ static int flash_iterate_address_range_inner(struct target *target,
static int flash_iterate_address_range(struct target *target,
char *pad_reason, target_addr_t addr, uint32_t length,
bool iterate_protect_blocks,
- int (*callback)(struct flash_bank *bank, int first, int last))
+ int (*callback)(struct flash_bank *bank, unsigned int first,
+ unsigned int last))
{
struct flash_bank *c;
int retval = ERROR_OK;
@@ -585,7 +587,8 @@ int flash_erase_address_range(struct target *target,
addr, length, false, &flash_driver_erase);
}
-static int flash_driver_unprotect(struct flash_bank *bank, int first, int last)
+static int flash_driver_unprotect(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
return flash_driver_protect(bank, 0, first, last);
}
@@ -627,8 +630,7 @@ target_addr_t flash_write_align_start(struct flash_bank *bank, target_addr_t add
if (bank->write_start_alignment == FLASH_WRITE_ALIGN_SECTOR) {
uint32_t offset = addr - bank->base;
uint32_t aligned = 0;
- int sect;
- for (sect = 0; sect < bank->num_sectors; sect++) {
+ for (unsigned int sect = 0; sect < bank->num_sectors; sect++) {
if (bank->sectors[sect].offset > offset)
break;
@@ -652,8 +654,7 @@ target_addr_t flash_write_align_end(struct flash_bank *bank, target_addr_t addr)
if (bank->write_end_alignment == FLASH_WRITE_ALIGN_SECTOR) {
uint32_t offset = addr - bank->base;
uint32_t aligned = 0;
- int sect;
- for (sect = 0; sect < bank->num_sectors; sect++) {
+ for (unsigned int sect = 0; sect < bank->num_sectors; sect++) {
aligned = bank->sectors[sect].offset + bank->sectors[sect].size - 1;
if (aligned >= offset)
break;
@@ -676,7 +677,7 @@ static bool flash_write_check_gap(struct flash_bank *bank,
return false;
if (bank->minimal_write_gap == FLASH_WRITE_GAP_SECTOR) {
- int sect;
+ unsigned int sect;
uint32_t offset1 = addr1 - bank->base;
/* find the sector following the one containing addr1 */
for (sect = 0; sect < bank->num_sectors; sect++) {
@@ -697,7 +698,7 @@ static bool flash_write_check_gap(struct flash_bank *bank,
int flash_write_unlock(struct target *target, struct image *image,
- uint32_t *written, int erase, bool unlock)
+ uint32_t *written, bool erase, bool unlock)
{
int retval = ERROR_OK;
@@ -847,12 +848,11 @@ int flash_write_unlock(struct target *target, struct image *image,
/* If we're applying any sector automagic, then pad this
* (maybe-combined) segment to the end of its last sector.
*/
- int sector;
uint32_t offset_start = run_address - c->base;
uint32_t offset_end = offset_start + run_size;
uint32_t end = offset_end, delta;
- for (sector = 0; sector < c->num_sectors; sector++) {
+ for (unsigned int sector = 0; sector < c->num_sectors; sector++) {
end = c->sectors[sector].offset
+ c->sectors[sector].size;
if (offset_end <= end)
@@ -955,20 +955,19 @@ done:
}
int flash_write(struct target *target, struct image *image,
- uint32_t *written, int erase)
+ uint32_t *written, bool erase)
{
return flash_write_unlock(target, image, written, erase, false);
}
-struct flash_sector *alloc_block_array(uint32_t offset, uint32_t size, int num_blocks)
+struct flash_sector *alloc_block_array(uint32_t offset, uint32_t size,
+ unsigned int num_blocks)
{
- int i;
-
struct flash_sector *array = calloc(num_blocks, sizeof(struct flash_sector));
if (array == NULL)
return NULL;
- for (i = 0; i < num_blocks; i++) {
+ for (unsigned int i = 0; i < num_blocks; i++) {
array[i].offset = offset;
array[i].size = size;
array[i].is_erased = -1;
diff --git a/src/flash/nor/core.h b/src/flash/nor/core.h
index ff5cb60c4..9f897e3e2 100644
--- a/src/flash/nor/core.h
+++ b/src/flash/nor/core.h
@@ -93,12 +93,12 @@ struct flash_bank {
const struct flash_driver *driver; /**< Driver for this bank. */
void *driver_priv; /**< Private driver storage pointer */
- int bank_number; /**< The 'bank' (or chip number) of this instance. */
+ unsigned int bank_number; /**< The 'bank' (or chip number) of this instance. */
target_addr_t base; /**< The base address of this bank */
uint32_t size; /**< The size of this chip bank, in bytes */
- int chip_width; /**< Width of the chip in bytes (1,2,4 bytes) */
- int bus_width; /**< Maximum bus width, in bytes (1,2,4 bytes) */
+ unsigned int chip_width; /**< Width of the chip in bytes (1,2,4 bytes) */
+ unsigned int bus_width; /**< Maximum bus width, in bytes (1,2,4 bytes) */
/** Erased value. Defaults to 0xFF. */
uint8_t erased_value;
@@ -124,7 +124,7 @@ struct flash_bank {
* be set initially to 0, and the flash driver must set this to
* some non-zero value during "probe()" or "auto_probe()".
*/
- int num_sectors;
+ unsigned int num_sectors;
/** Array of sectors, allocated and initialized by the flash driver */
struct flash_sector *sectors;
@@ -134,7 +134,7 @@ struct flash_bank {
* Driver probe can set protection blocks array to work with
* protection granularity different than sector size.
*/
- int num_prot_blocks;
+ unsigned int num_prot_blocks;
/*...
[truncated message content] |
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-07-07 04:19:03
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via a2e6982a1816a0229bd5644156f3025a0e8cb6ce (commit)
from 7c88e76a76588fa0e3ab645adfc46e8baff6a3e4 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit a2e6982a1816a0229bd5644156f3025a0e8cb6ce
Author: Michael Hope <ml...@go...>
Date: Fri May 29 22:30:44 2020 +0200
flash/nor/atsame5: Fix a timeout when erasing
According to the datasheet, erasing a block can take up to 200 ms.
When using a Segger J-Link with a 2 MHz clock the current loop
finishes after < 50 ms, ignores the timeout, and then fails when
erasing the next block.
Switch to a time based check, add an explicit yield, and report an
error on timeout.
Change-Id: I8255401d1e59f427a08d2cccb8a66143dcdbb324
Signed-off-by: Michael Hope <ml...@go...>
Reviewed-on: http://openocd.zylin.com/5706
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/flash/nor/atsame5.c b/src/flash/nor/atsame5.c
index eac7847dc..baa86acd0 100644
--- a/src/flash/nor/atsame5.c
+++ b/src/flash/nor/atsame5.c
@@ -27,6 +27,7 @@
#include "imp.h"
#include "helper/binarybuffer.h"
+#include <helper/time_support.h>
#include <target/cortex_m.h>
/* A note to prefixing.
@@ -338,19 +339,28 @@ static int same5_probe(struct flash_bank *bank)
static int same5_wait_and_check_error(struct target *target)
{
int ret, ret2;
- int rep_cnt = 100;
+ /* Table 54-40 lists the maximum erase block time as 200 ms.
+ * Include some margin.
+ */
+ int timeout_ms = 200 * 5;
+ int64_t ts_start = timeval_ms();
uint16_t intflag;
do {
ret = target_read_u16(target,
SAMD_NVMCTRL + SAME5_NVMCTRL_INTFLAG, &intflag);
- if (ret == ERROR_OK && intflag & SAME5_NVMCTRL_INTFLAG_DONE)
+ if (ret != ERROR_OK) {
+ LOG_ERROR("SAM: error reading the NVMCTRL_INTFLAG register");
+ return ret;
+ }
+ if (intflag & SAME5_NVMCTRL_INTFLAG_DONE)
break;
- } while (--rep_cnt);
+ keep_alive();
+ } while (timeval_ms() - ts_start < timeout_ms);
- if (ret != ERROR_OK) {
- LOG_ERROR("Can't read NVM INTFLAG");
- return ret;
+ if (!(intflag & SAME5_NVMCTRL_INTFLAG_DONE)) {
+ LOG_ERROR("SAM: NVM programming timed out");
+ ret = ERROR_FLASH_OPERATION_FAILED;
}
#if 0
if (intflag & SAME5_NVMCTRL_INTFLAG_ECCSE)
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/atsame5.c | 22 ++++++++++++++++------
1 file changed, 16 insertions(+), 6 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-06-27 14:35:50
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 7c88e76a76588fa0e3ab645adfc46e8baff6a3e4 (commit)
from 64733434e23d42bfd75932c1e71c39800a5c01e4 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 7c88e76a76588fa0e3ab645adfc46e8baff6a3e4
Author: Antonio Borneo <bor...@gm...>
Date: Tue Jun 2 14:43:29 2020 +0200
target: do not print an error on shutdown in target events
Before commit b3ce5a0ae545 ("target: use LOG_USER to print errors
in events") an error in an event handler was silently lost, while
now the associated message is printed out.
A "shutdown" command in a target event (e.g. in gdb-detach) causes
the event to end with error code ERROR_COMMAND_CLOSE_CONNECTION,
that triggers the error message:
shutdown command invoked
Error executing event <event-name> on target <target-name>:
The error code returned by the command "shutdown" is required to
stop the execution in a script/proc and avoid executing any
further command in the script/proc.
It is then normal to get an error code from the "shutdown" command
and it should not be printed out.
Intercept the return code of the event in case of "shutdown", then
skip scheduling other target events and return without printing
the incorrect error message.
Change-Id: Ia3085fb46beacb90a5e4bf0abf7c6e28bb9e6a9b
Signed-off-by: Antonio Borneo <bor...@gm...>
Reported-by: Laurent Lemele <lau...@st...>
Reviewed-on: http://openocd.zylin.com/5710
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
Tested-by: jenkins
diff --git a/src/target/target.c b/src/target/target.c
index c0953a3f1..2ea1e206c 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -4582,8 +4582,14 @@ void target_handle_event(struct target *target, enum target_event e)
struct command_context *cmd_ctx = current_command_context(teap->interp);
struct target *saved_target_override = cmd_ctx->current_target_override;
cmd_ctx->current_target_override = target;
+
retval = Jim_EvalObj(teap->interp, teap->body);
+ cmd_ctx->current_target_override = saved_target_override;
+
+ if (retval == ERROR_COMMAND_CLOSE_CONNECTION)
+ return;
+
if (retval == JIM_RETURN)
retval = teap->interp->returnCode;
@@ -4596,8 +4602,6 @@ void target_handle_event(struct target *target, enum target_event e)
/* clean both error code and stacktrace before return */
Jim_Eval(teap->interp, "error \"\" \"\"");
}
-
- cmd_ctx->current_target_override = saved_target_override;
}
}
}
-----------------------------------------------------------------------
Summary of changes:
src/target/target.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2020-06-27 14:35:14
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 64733434e23d42bfd75932c1e71c39800a5c01e4 (commit)
via 057aed11a2f80645322ff76c7dd0c7908582d0a4 (commit)
from 2e6904eef5e81e71453168ed8c6f649e3a5c0f6c (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 64733434e23d42bfd75932c1e71c39800a5c01e4
Author: Moritz Fischer <mo...@go...>
Date: Sat Feb 8 16:09:04 2020 -0800
jtag: drivers: xlnx-pcie-xvc: Add support for SWD mode.
Add support for SWD debug to the Xilinx XVC/PCIe driver.
This is possible since the device is essentially a shift-register.
So doing SWD vs JTAG is a matter of wiring things correctly on the
RTL side (use TMS for SWDI, TDO for SWDO).
The clang static checker doesn't find any new problems with this change.
Change-Id: I3959e21440cd1036769e8e56a55e601d3e4aee9a
Signed-off-by: Moritz Fischer <mo...@go...>
Reviewed-on: http://openocd.zylin.com/5447
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 1ddf09ffa..a0ce7e349 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -610,7 +610,7 @@ produced, PDF schematics are easily found and it is easy to make.
@* Link: @url{http://github.com/fjullien/jtag_vpi}
@item @b{xlnx_pcie_xvc}
-@* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG interface.
+@* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
@end itemize
@@ -3149,7 +3149,7 @@ version).
@deffn {Interface Driver} {xlnx_pcie_xvc}
This driver supports the Xilinx Virtual Cable (XVC) over PCI Express.
It is commonly found in Xilinx based PCI Express designs. It allows debugging
-fabric based JTAG devices such as Cortex-M1/M3 microcontrollers. Access to this is
+fabric based JTAG/SWD devices such as Cortex-M1/M3 microcontrollers. Access to this is
exposed via extended capability registers in the PCI Express configuration space.
For more information see Xilinx PG245 (Section on From_PCIE_to_JTAG mode).
diff --git a/src/jtag/drivers/xlnx-pcie-xvc.c b/src/jtag/drivers/xlnx-pcie-xvc.c
index 17438593a..704c1d96b 100644
--- a/src/jtag/drivers/xlnx-pcie-xvc.c
+++ b/src/jtag/drivers/xlnx-pcie-xvc.c
@@ -37,6 +37,9 @@
#define XLNX_XVC_VSEC_ID 0x8
#define XLNX_XVC_MAX_BITS 0x20
+#define MASK_ACK(x) (((x) >> 9) & 0x7)
+#define MASK_PAR(x) ((int)((x) & 0x1))
+
struct xlnx_pcie_xvc {
int fd;
unsigned offset;
@@ -471,17 +474,224 @@ static const struct command_registration xlnx_pcie_xvc_command_handlers[] = {
COMMAND_REGISTRATION_DONE
};
-static struct jtag_interface xlnx_pcie_xvc_interface = {
+static struct jtag_interface xlnx_pcie_xvc_jtag_ops = {
.execute_queue = &xlnx_pcie_xvc_execute_queue,
};
+static int xlnx_pcie_xvc_swd_sequence(const uint8_t *seq, size_t length)
+{
+ size_t left, write;
+ uint32_t send;
+ int err;
+
+ left = length;
+ while (left) {
+ write = MIN(XLNX_XVC_MAX_BITS, left);
+ send = buf_get_u32(seq, 0, write);
+ err = xlnx_pcie_xvc_transact(write, send, 0, NULL);
+ if (err != ERROR_OK)
+ return err;
+ left -= write;
+ seq += sizeof(uint32_t);
+ };
+
+ return ERROR_OK;
+}
+
+static int xlnx_pcie_xvc_swd_switch_seq(enum swd_special_seq seq)
+{
+ switch (seq) {
+ case LINE_RESET:
+ LOG_DEBUG("SWD line reset");
+ return xlnx_pcie_xvc_swd_sequence(swd_seq_line_reset,
+ swd_seq_line_reset_len);
+ case JTAG_TO_SWD:
+ LOG_DEBUG("JTAG-to-SWD");
+ return xlnx_pcie_xvc_swd_sequence(swd_seq_jtag_to_swd,
+ swd_seq_jtag_to_swd_len);
+ case SWD_TO_JTAG:
+ LOG_DEBUG("SWD-to-JTAG");
+ return xlnx_pcie_xvc_swd_sequence(swd_seq_swd_to_jtag,
+ swd_seq_swd_to_jtag_len);
+ default:
+ LOG_ERROR("Sequence %d not supported", seq);
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+static int queued_retval;
+
+static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
+ uint32_t ap_delay_clk);
+
+static void swd_clear_sticky_errors(void)
+{
+ xlnx_pcie_xvc_swd_write_reg(swd_cmd(false, false, DP_ABORT),
+ STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
+}
+
+static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
+ uint32_t ap_delay_clk)
+{
+ uint32_t res, ack, rpar;
+ int err;
+
+ assert(cmd & SWD_CMD_RnW);
+
+ cmd |= SWD_CMD_START | SWD_CMD_PARK;
+ /* cmd + ack */
+ err = xlnx_pcie_xvc_transact(12, cmd, 0, &res);
+ if (err != ERROR_OK)
+ goto err_out;
+
+ ack = MASK_ACK(res);
+
+ /* read data */
+ err = xlnx_pcie_xvc_transact(32, 0, 0, &res);
+ if (err != ERROR_OK)
+ goto err_out;
+
+ /* parity + trn */
+ err = xlnx_pcie_xvc_transact(2, 0, 0, &rpar);
+ if (err != ERROR_OK)
+ goto err_out;
+
+ LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
+ ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ?
+ "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
+ cmd & SWD_CMD_APnDP ? "AP" : "DP",
+ cmd & SWD_CMD_RnW ? "read" : "write",
+ (cmd & SWD_CMD_A32) >> 1,
+ res);
+ switch (ack) {
+ case SWD_ACK_OK:
+ if (MASK_PAR(rpar) != parity_u32(res)) {
+ LOG_DEBUG_IO("Wrong parity detected");
+ queued_retval = ERROR_FAIL;
+ return;
+ }
+ if (value)
+ *value = res;
+ if (cmd & SWD_CMD_APnDP)
+ err = xlnx_pcie_xvc_transact(ap_delay_clk, 0, 0, NULL);
+ queued_retval = err;
+ return;
+ case SWD_ACK_WAIT:
+ LOG_DEBUG_IO("SWD_ACK_WAIT");
+ swd_clear_sticky_errors();
+ return;
+ case SWD_ACK_FAULT:
+ LOG_DEBUG_IO("SWD_ACK_FAULT");
+ queued_retval = ack;
+ return;
+ default:
+ LOG_DEBUG_IO("No valid acknowledge: ack=%02"PRIx32, ack);
+ queued_retval = ack;
+ return;
+ }
+err_out:
+ queued_retval = err;
+}
+
+static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
+ uint32_t ap_delay_clk)
+{
+ uint32_t res, ack;
+ int err;
+
+ assert(!(cmd & SWD_CMD_RnW));
+
+ cmd |= SWD_CMD_START | SWD_CMD_PARK;
+ /* cmd + trn + ack */
+ err = xlnx_pcie_xvc_transact(13, cmd, 0, &res);
+ if (err != ERROR_OK)
+ goto err_out;
+
+ ack = MASK_ACK(res);
+
+ /* write data */
+ err = xlnx_pcie_xvc_transact(32, value, 0, NULL);
+ if (err != ERROR_OK)
+ goto err_out;
+
+ /* parity + trn */
+ err = xlnx_pcie_xvc_transact(2, parity_u32(value), 0, NULL);
+ if (err != ERROR_OK)
+ goto err_out;
+
+ LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
+ ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ?
+ "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
+ cmd & SWD_CMD_APnDP ? "AP" : "DP",
+ cmd & SWD_CMD_RnW ? "read" : "write",
+ (cmd & SWD_CMD_A32) >> 1,
+ value);
+
+ switch (ack) {
+ case SWD_ACK_OK:
+ if (cmd & SWD_CMD_APnDP)
+ err = xlnx_pcie_xvc_transact(ap_delay_clk, 0, 0, NULL);
+ queued_retval = err;
+ return;
+ case SWD_ACK_WAIT:
+ LOG_DEBUG_IO("SWD_ACK_WAIT");
+ swd_clear_sticky_errors();
+ return;
+ case SWD_ACK_FAULT:
+ LOG_DEBUG_IO("SWD_ACK_FAULT");
+ queued_retval = ack;
+ return;
+ default:
+ LOG_DEBUG_IO("No valid acknowledge: ack=%02"PRIx32, ack);
+ queued_retval = ack;
+ return;
+ }
+
+err_out:
+ queued_retval = err;
+}
+
+static int xlnx_pcie_xvc_swd_run_queue(void)
+{
+ int err;
+
+ /* we want at least 8 idle cycles between each transaction */
+ err = xlnx_pcie_xvc_transact(8, 0, 0, NULL);
+ if (err != ERROR_OK)
+ return err;
+
+ err = queued_retval;
+ queued_retval = ERROR_OK;
+ LOG_DEBUG("SWD queue return value: %02x", err);
+
+ return err;
+}
+
+static int xlnx_pcie_xvc_swd_init(void)
+{
+ return ERROR_OK;
+}
+
+static const struct swd_driver xlnx_pcie_xvc_swd_ops = {
+ .init = xlnx_pcie_xvc_swd_init,
+ .switch_seq = xlnx_pcie_xvc_swd_switch_seq,
+ .read_reg = xlnx_pcie_xvc_swd_read_reg,
+ .write_reg = xlnx_pcie_xvc_swd_write_reg,
+ .run = xlnx_pcie_xvc_swd_run_queue,
+};
+
+static const char * const xlnx_pcie_xvc_transports[] = { "jtag", "swd", NULL };
+
struct adapter_driver xlnx_pcie_xvc_adapter_driver = {
.name = "xlnx_pcie_xvc",
- .transports = jtag_only,
+ .transports = xlnx_pcie_xvc_transports,
.commands = xlnx_pcie_xvc_command_handlers,
.init = &xlnx_pcie_xvc_init,
.quit = &xlnx_pcie_xvc_quit,
- .jtag_ops = &xlnx_pcie_xvc_interface,
+ .jtag_ops = &xlnx_pcie_xvc_jtag_ops,
+ .swd_ops = &xlnx_pcie_xvc_swd_ops,
};
commit 057aed11a2f80645322ff76c7dd0c7908582d0a4
Author: Evgeniy Didin <di...@sy...>
Date: Fri May 15 23:04:01 2020 +0300
target/arc: Introduce L1I,L1D,L2 caches support
With this commit we introduce L1 and L2 cache
flush and invalidate operations which are necessary for
getting/setting actual data during memory r/w operations.
We introduce L2 cache support, which is not presented
on currently support EMSK board. But L2 is presented
on HSDK board, which soon will be introduced.
Change-Id: I2fda505a47ecb8833cc9f5ffe24f6a4e22ab6eb0
Signed-off-by: Evgeniy Didin <di...@sy...>
Reviewed-on: http://openocd.zylin.com/5688
Reviewed-by: Oleksij Rempel <li...@re...>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/arc.c b/src/target/arc.c
index 6cf0ec7af..e9709f485 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -86,6 +86,26 @@ struct reg *arc_reg_get_by_name(struct reg_cache *first,
return NULL;
}
+/**
+ * Reset internal states of caches. Must be called when entering debugging.
+ *
+ * @param target Target for which to reset caches states.
+ */
+int arc_reset_caches_states(struct target *target)
+{
+ struct arc_common *arc = target_to_arc(target);
+
+ LOG_DEBUG("Resetting internal variables of caches states");
+
+ /* Reset caches states. */
+ arc->dcache_flushed = false;
+ arc->l2cache_flushed = false;
+ arc->icache_invalidated = false;
+ arc->dcache_invalidated = false;
+ arc->l2cache_invalidated = false;
+
+ return ERROR_OK;
+}
/* Initialize arc_common structure, which passes to openocd target instance */
static int arc_init_arch_info(struct target *target, struct arc_common *arc,
@@ -102,6 +122,15 @@ static int arc_init_arch_info(struct target *target, struct arc_common *arc,
return ERROR_FAIL;
}
+ /* On most ARC targets there is a dcache, so we enable its flushing
+ * by default. If there no dcache, there will be no error, just a slight
+ * performance penalty from unnecessary JTAG operations. */
+ arc->has_dcache = true;
+ arc->has_icache = true;
+ /* L2$ is not available in a target by default. */
+ arc->has_l2cache = false;
+ arc_reset_caches_states(target);
+
/* Add standard GDB data types */
INIT_LIST_HEAD(&arc->reg_data_types);
struct arc_reg_data_type *std_types = calloc(ARRAY_SIZE(standard_gdb_types),
@@ -900,6 +929,7 @@ static int arc_debug_entry(struct target *target)
/* TODO: reset internal indicators of caches states, otherwise D$/I$
* will not be flushed/invalidated when required. */
+ CHECK_RETVAL(arc_reset_caches_states(target));
CHECK_RETVAL(arc_examine_debug_reason(target));
return ERROR_OK;
@@ -1152,6 +1182,11 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
LOG_DEBUG("current:%i, address:0x%08" TARGET_PRIxADDR ", handle_breakpoints(not supported yet):%i,"
" debug_execution:%i", current, address, handle_breakpoints, debug_execution);
+ /* We need to reset ARC cache variables so caches
+ * would be invalidated and actual data
+ * would be fetched from memory. */
+ CHECK_RETVAL(arc_reset_caches_states(target));
+
if (target->state != TARGET_HALTED) {
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
@@ -1396,8 +1431,9 @@ static int arc_set_breakpoint(struct target *target,
LOG_DEBUG("ERROR: setting unknown breakpoint type");
return ERROR_FAIL;
}
- /* core instruction cache is now invalid,
- * TODO: add cache invalidation function here (when implemented). */
+
+ /* core instruction cache is now invalid. */
+ CHECK_RETVAL(arc_cache_invalidate(target));
return ERROR_OK;
}
@@ -1462,8 +1498,8 @@ static int arc_unset_breakpoint(struct target *target,
return ERROR_FAIL;
}
- /* core instruction cache is now invalid.
- * TODO: Add cache invalidation function */
+ /* core instruction cache is now invalid. */
+ CHECK_RETVAL(arc_cache_invalidate(target));
return retval;
}
@@ -1596,6 +1632,176 @@ int arc_step(struct target *target, int current, target_addr_t address,
}
+/* This function invalidates icache. */
+static int arc_icache_invalidate(struct target *target)
+{
+ uint32_t value;
+
+ struct arc_common *arc = target_to_arc(target);
+
+ /* Don't waste time if already done. */
+ if (!arc->has_icache || arc->icache_invalidated)
+ return ERROR_OK;
+
+ LOG_DEBUG("Invalidating I$.");
+
+ value = IC_IVIC_INVALIDATE; /* invalidate I$ */
+ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_IC_IVIC_REG, value));
+
+ arc->icache_invalidated = true;
+
+ return ERROR_OK;
+}
+
+/* This function invalidates dcache */
+static int arc_dcache_invalidate(struct target *target)
+{
+ uint32_t value, dc_ctrl_value;
+
+ struct arc_common *arc = target_to_arc(target);
+
+ if (!arc->has_dcache || arc->dcache_invalidated)
+ return ERROR_OK;
+
+ LOG_DEBUG("Invalidating D$.");
+
+ CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &value));
+ dc_ctrl_value = value;
+ value &= ~DC_CTRL_IM;
+
+ /* set DC_CTRL invalidate mode to invalidate-only (no flushing!!) */
+ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, value));
+ value = DC_IVDC_INVALIDATE; /* invalidate D$ */
+ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_IVDC_REG, value));
+
+ /* restore DC_CTRL invalidate mode */
+ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, dc_ctrl_value));
+
+ arc->dcache_invalidated = true;
+
+ return ERROR_OK;
+}
+
+/* This function invalidates l2 cache. */
+static int arc_l2cache_invalidate(struct target *target)
+{
+ uint32_t value, slc_ctrl_value;
+
+ struct arc_common *arc = target_to_arc(target);
+
+ if (!arc->has_l2cache || arc->l2cache_invalidated)
+ return ERROR_OK;
+
+ LOG_DEBUG("Invalidating L2$.");
+
+ CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
+ slc_ctrl_value = value;
+ value &= ~L2_CTRL_IM;
+
+ /* set L2_CTRL invalidate mode to invalidate-only (no flushing!!) */
+ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, value));
+ /* invalidate L2$ */
+ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_INV, L2_INV_IV));
+
+ /* Wait until invalidate operation ends */
+ do {
+ LOG_DEBUG("Waiting for invalidation end.");
+ CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
+ } while (value & L2_CTRL_BS);
+
+ /* restore L2_CTRL invalidate mode */
+ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, slc_ctrl_value));
+
+ arc->l2cache_invalidated = true;
+
+ return ERROR_OK;
+}
+
+
+int arc_cache_invalidate(struct target *target)
+{
+ CHECK_RETVAL(arc_icache_invalidate(target));
+ CHECK_RETVAL(arc_dcache_invalidate(target));
+ CHECK_RETVAL(arc_l2cache_invalidate(target));
+
+ return ERROR_OK;
+}
+
+/* Flush data cache. This function is cheap to call and return quickly if D$
+ * already has been flushed since target had been halted. JTAG debugger reads
+ * values directly from memory, bypassing cache, so if there are unflushed
+ * lines debugger will read invalid values, which will cause a lot of troubles.
+ * */
+int arc_dcache_flush(struct target *target)
+{
+ uint32_t value, dc_ctrl_value;
+ bool has_to_set_dc_ctrl_im;
+
+ struct arc_common *arc = target_to_arc(target);
+
+ /* Don't waste time if already done. */
+ if (!arc->has_dcache || arc->dcache_flushed)
+ return ERROR_OK;
+
+ LOG_DEBUG("Flushing D$.");
+
+ /* Store current value of DC_CTRL */
+ CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, &dc_ctrl_value));
+
+ /* Set DC_CTRL invalidate mode to flush (if not already set) */
+ has_to_set_dc_ctrl_im = (dc_ctrl_value & DC_CTRL_IM) == 0;
+ if (has_to_set_dc_ctrl_im) {
+ value = dc_ctrl_value | DC_CTRL_IM;
+ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, value));
+ }
+
+ /* Flush D$ */
+ value = DC_IVDC_INVALIDATE;
+ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_IVDC_REG, value));
+
+ /* Restore DC_CTRL invalidate mode (even of flush failed) */
+ if (has_to_set_dc_ctrl_im)
+ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, AUX_DC_CTRL_REG, dc_ctrl_value));
+
+ arc->dcache_flushed = true;
+
+ return ERROR_OK;
+}
+
+/* This function flushes l2cache. */
+static int arc_l2cache_flush(struct target *target)
+{
+ uint32_t value;
+
+ struct arc_common *arc = target_to_arc(target);
+
+ /* Don't waste time if already done. */
+ if (!arc->has_l2cache || arc->l2cache_flushed)
+ return ERROR_OK;
+
+ LOG_DEBUG("Flushing L2$.");
+
+ /* Flush L2 cache */
+ CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_FLUSH, L2_FLUSH_FL));
+
+ /* Wait until flush operation ends */
+ do {
+ LOG_DEBUG("Waiting for flushing end.");
+ CHECK_RETVAL(arc_jtag_read_aux_reg_one(&arc->jtag_info, SLC_AUX_CACHE_CTRL, &value));
+ } while (value & L2_CTRL_BS);
+
+ arc->l2cache_flushed = true;
+
+ return ERROR_OK;
+}
+
+int arc_cache_flush(struct target *target)
+{
+ CHECK_RETVAL(arc_dcache_flush(target));
+ CHECK_RETVAL(arc_l2cache_flush(target));
+
+ return ERROR_OK;
+}
/* ARC v2 target */
struct target_type arcv2_target = {
diff --git a/src/target/arc.h b/src/target/arc.h
index defa3fa97..664141159 100644
--- a/src/target/arc.h
+++ b/src/target/arc.h
@@ -60,6 +60,24 @@
/* ARC 16bits opcodes */
#define ARC_SDBBP_16 0x7FFF /* BRK_S */
+/* Cache registers */
+#define AUX_IC_IVIC_REG 0X10
+#define IC_IVIC_INVALIDATE 0XFFFFFFFF
+
+#define AUX_DC_IVDC_REG 0X47
+#define DC_IVDC_INVALIDATE BIT(0)
+#define AUX_DC_CTRL_REG 0X48
+#define DC_CTRL_IM BIT(6)
+
+/* L2 cache registers */
+#define SLC_AUX_CACHE_CTRL 0x903
+#define L2_CTRL_IM BIT(6)
+#define L2_CTRL_BS BIT(8) /* Busy flag */
+#define SLC_AUX_CACHE_FLUSH 0x904
+#define L2_FLUSH_FL BIT(0)
+#define SLC_AUX_CACHE_INV 0x905
+#define L2_INV_IV BIT(0)
+
struct arc_reg_bitfield {
struct reg_data_type_bitfield bitfield;
char name[REG_TYPE_MAX_NAME_LENGTH];
@@ -109,6 +127,22 @@ struct arc_common {
struct reg_cache *core_and_aux_cache;
struct reg_cache *bcr_cache;
+ /* Cache control */
+ bool has_dcache;
+ bool has_icache;
+ bool has_l2cache;
+ /* If true, then D$ has been already flushed since core has been
+ * halted. */
+ bool dcache_flushed;
+ /* If true, then L2 has been already flushed since core has been
+ * halted. */
+ bool l2cache_flushed;
+ /* If true, then caches have been already flushed since core has been
+ * halted. */
+ bool icache_invalidated;
+ bool dcache_invalidated;
+ bool l2cache_invalidated;
+
/* Indicate if cach was built (for deinit function) */
bool core_aux_cache_built;
bool bcr_cache_built;
@@ -247,4 +281,7 @@ struct reg *arc_reg_get_by_name(struct reg_cache *first,
int arc_reg_get_field(struct target *target, const char *reg_name,
const char *field_name, uint32_t *value_ptr);
+int arc_cache_flush(struct target *target);
+int arc_cache_invalidate(struct target *target);
+
#endif /* OPENOCD_TARGET_ARC_H */
diff --git a/src/target/arc_cmd.c b/src/target/arc_cmd.c
index fad8ca947..59e1645d6 100644
--- a/src/target/arc_cmd.c
+++ b/src/target/arc_cmd.c
@@ -909,10 +909,60 @@ static int jim_arc_get_reg_field(Jim_Interp *interp, int argc, Jim_Obj * const *
return JIM_OK;
}
+COMMAND_HANDLER(arc_l1_cache_disable_auto_cmd)
+{
+ bool value;
+ int retval = 0;
+ struct arc_common *arc = target_to_arc(get_current_target(CMD_CTX));
+ retval = CALL_COMMAND_HANDLER(handle_command_parse_bool,
+ &value, "target has caches enabled");
+ arc->has_l2cache = value;
+ arc->has_dcache = value;
+ arc->has_icache = value;
+ return retval;
+}
+
+COMMAND_HANDLER(arc_l2_cache_disable_auto_cmd)
+{
+ struct arc_common *arc = target_to_arc(get_current_target(CMD_CTX));
+ return CALL_COMMAND_HANDLER(handle_command_parse_bool,
+ &arc->has_l2cache, "target has l2 cache enabled");
+}
+
/* ----- Exported target commands ------------------------------------------ */
+const struct command_registration arc_l2_cache_group_handlers[] = {
+ {
+ .name = "auto",
+ .handler = arc_l2_cache_disable_auto_cmd,
+ .mode = COMMAND_ANY,
+ .usage = "(1|0)",
+ .help = "Disable or enable L2",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+const struct command_registration arc_cache_group_handlers[] = {
+ {
+ .name = "auto",
+ .handler = arc_l1_cache_disable_auto_cmd,
+ .mode = COMMAND_ANY,
+ .help = "Disable or enable L1",
+ .usage = "(1|0)",
+ },
+ {
+ .name = "l2",
+ .mode = COMMAND_ANY,
+ .help = "L2 cache command group",
+ .usage = "",
+ .chain = arc_l2_cache_group_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+
static const struct command_registration arc_core_command_handlers[] = {
-{
+ {
.name = "add-reg-type-flags",
.jim_handler = jim_arc_add_reg_type_flags,
.mode = COMMAND_CONFIG,
@@ -967,6 +1017,13 @@ static const struct command_registration arc_core_command_handlers[] = {
.usage = "",
.chain = arc_jtag_command_group,
},
+ {
+ .name = "cache",
+ .mode = COMMAND_ANY,
+ .help = "cache command group",
+ .usage = "",
+ .chain = arc_cache_group_handlers,
+ },
COMMAND_REGISTRATION_DONE
};
diff --git a/src/target/arc_mem.c b/src/target/arc_mem.c
index e80bfb4e4..866c71fc2 100644
--- a/src/target/arc_mem.c
+++ b/src/target/arc_mem.c
@@ -41,10 +41,18 @@ static int arc_mem_write_block32(struct target *target, uint32_t addr,
/* Check arguments */
assert(!(addr & 3));
+ /* We need to flush the cache since it might contain dirty
+ * lines, so the cache invalidation may cause data inconsistency. */
+ CHECK_RETVAL(arc_cache_flush(target));
+
+
/* No need to flush cache, because we don't read values from memory. */
CHECK_RETVAL(arc_jtag_write_memory(&arc->jtag_info, addr, count,
(uint32_t *)buf));
+ /* Invalidate caches. */
+ CHECK_RETVAL(arc_cache_invalidate(target));
+
return ERROR_OK;
}
@@ -64,6 +72,9 @@ static int arc_mem_write_block16(struct target *target, uint32_t addr,
/* Check arguments */
assert(!(addr & 1));
+ /* We will read data from memory, so we need to flush the cache. */
+ CHECK_RETVAL(arc_cache_flush(target));
+
/* non-word writes are less common, than 4-byte writes, so I suppose we can
* allowe ourselves to write this in a cycle, instead of calling arc_jtag
* with count > 1. */
@@ -97,6 +108,9 @@ static int arc_mem_write_block16(struct target *target, uint32_t addr,
(addr + i * sizeof(uint16_t)) & ~3u, 1, &buffer_he));
}
+ /* Invalidate caches. */
+ CHECK_RETVAL(arc_cache_invalidate(target));
+
return ERROR_OK;
}
@@ -113,6 +127,9 @@ static int arc_mem_write_block8(struct target *target, uint32_t addr,
LOG_DEBUG("Write 1-byte memory block: addr=0x%08" PRIx32 ", count=%" PRIu32,
addr, count);
+ /* We will read data from memory, so we need to flush the cache. */
+ CHECK_RETVAL(arc_cache_flush(target));
+
/* non-word writes are less common, than 4-byte writes, so I suppose we can
* allowe ourselves to write this in a cycle, instead of calling arc_jtag
* with count > 1. */
@@ -128,6 +145,9 @@ static int arc_mem_write_block8(struct target *target, uint32_t addr,
CHECK_RETVAL(arc_jtag_write_memory(&arc->jtag_info, (addr + i) & ~3, 1, &buffer_he));
}
+ /* Invalidate caches. */
+ CHECK_RETVAL(arc_cache_invalidate(target));
+
return ERROR_OK;
}
@@ -205,6 +225,9 @@ static int arc_mem_read_block(struct target *target, target_addr_t addr,
assert(!(addr & 3));
assert(size == 4);
+ /* Flush cache before memory access */
+ CHECK_RETVAL(arc_cache_flush(target));
+
CHECK_RETVAL(arc_jtag_read_memory(&arc->jtag_info, addr, count, buf,
arc_mem_is_slow_memory(arc, addr, size, count)));
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 4 +-
src/jtag/drivers/xlnx-pcie-xvc.c | 216 ++++++++++++++++++++++++++++++++++++++-
src/target/arc.c | 214 +++++++++++++++++++++++++++++++++++++-
src/target/arc.h | 37 +++++++
src/target/arc_cmd.c | 59 ++++++++++-
src/target/arc_mem.c | 23 +++++
6 files changed, 543 insertions(+), 10 deletions(-)
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|
From: OpenOCD-Gerrit <ope...@us...> - 2020-06-27 14:34:41
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 2e6904eef5e81e71453168ed8c6f649e3a5c0f6c (commit)
from 8833c889da07eae750bcbc11215cc84323de9b74 (commit)
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- Log -----------------------------------------------------------------
commit 2e6904eef5e81e71453168ed8c6f649e3a5c0f6c
Author: Lucas <pu...@x3...>
Date: Sun May 17 16:42:39 2020 +0100
aarch64: Add support for debugging in HYP mode on ARMv8-A cores
When debugging an ARMv8-A/AArch32 target running HYP mode, OpenOCD would
throw the following error to GDB on most operations (step, set breakpoint):
cannot read system control register in this mode
The mode in question is 0x1A, a privilege level 2 mode available on cores
that have the virtualization extensions (such as the Raspi 3).
Note: this mode is only used when running in AArch32 compatibility mode.
Signed-off-by: Lucas Jenss <pu...@x3...>
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Change-Id: Ia8673ff34c5b3eed60e24d8da57c3ca8197a60c2
Reviewed-on: http://openocd.zylin.com/5255
Tested-by: jenkins
Reviewed-by: Lucas Jenà <luc...@gm...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 87176f638..01d0e9462 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -99,12 +99,14 @@ static int aarch64_restore_system_control_reg(struct target *target)
case ARM_MODE_ABT:
case ARM_MODE_FIQ:
case ARM_MODE_IRQ:
+ case ARM_MODE_HYP:
case ARM_MODE_SYS:
instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
break;
default:
- LOG_INFO("cannot read system control register in this mode");
+ LOG_ERROR("cannot read system control register in this mode: (%s : 0x%" PRIx32 ")",
+ armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode);
return ERROR_FAIL;
}
@@ -172,6 +174,7 @@ static int aarch64_mmu_modify(struct target *target, int enable)
case ARM_MODE_ABT:
case ARM_MODE_FIQ:
case ARM_MODE_IRQ:
+ case ARM_MODE_HYP:
case ARM_MODE_SYS:
instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
break;
@@ -1033,12 +1036,14 @@ static int aarch64_post_debug_entry(struct target *target)
case ARM_MODE_ABT:
case ARM_MODE_FIQ:
case ARM_MODE_IRQ:
+ case ARM_MODE_HYP:
case ARM_MODE_SYS:
instr = ARMV4_5_MRC(15, 0, 0, 1, 0, 0);
break;
default:
- LOG_INFO("cannot read system control register in this mode");
+ LOG_ERROR("cannot read system control register in this mode: (%s : 0x%" PRIx32 ")",
+ armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode);
return ERROR_FAIL;
}
diff --git a/src/target/armv8.c b/src/target/armv8.c
index 61f11f24a..0c8508661 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -73,6 +73,10 @@ static const struct {
.name = "ABT",
.psr = ARM_MODE_ABT,
},
+ {
+ .name = "HYP",
+ .psr = ARM_MODE_HYP,
+ },
{
.name = "SYS",
.psr = ARM_MODE_SYS,
diff --git a/src/target/armv8.h b/src/target/armv8.h
index 1a611455d..c5ee5fd87 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -330,6 +330,7 @@ static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
}
}
+const char *armv8_mode_name(unsigned psr_mode);
void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);
-----------------------------------------------------------------------
Summary of changes:
src/target/aarch64.c | 9 +++++++--
src/target/armv8.c | 4 ++++
src/target/armv8.h | 1 +
3 files changed, 12 insertions(+), 2 deletions(-)
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2020-06-23 17:56:43
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 8833c889da07eae750bcbc11215cc84323de9b74 (commit)
from 5a79481d3b17c4134a43052cea9a7902bbf0accf (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 8833c889da07eae750bcbc11215cc84323de9b74
Author: Marc Schink <de...@za...>
Date: Sun Jun 14 21:57:35 2020 +0200
libjaylink: Update to latest Git version
This update is for testing the upcoming 0.2.0 release.
Change-Id: I400b09eb3ead4306c83c7980c621124101aaef7e
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5723
Tested-by: jenkins
Reviewed-by: Paul Fertser <fer...@gm...>
diff --git a/src/jtag/drivers/libjaylink b/src/jtag/drivers/libjaylink
index f73ad5e66..dce11b89e 160000
--- a/src/jtag/drivers/libjaylink
+++ b/src/jtag/drivers/libjaylink
@@ -1 +1 @@
-Subproject commit f73ad5e667ae8b26a52b847c603fdadaabf302a6
+Subproject commit dce11b89e85179a92a0fe3a90d2693ca891ed646
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/libjaylink | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
hooks/post-receive
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2020-06-18 09:11:53
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 5a79481d3b17c4134a43052cea9a7902bbf0accf (commit)
from 11116ef6ad875055a43cf9af1f228991349f2ba1 (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 5a79481d3b17c4134a43052cea9a7902bbf0accf
Author: Marc Schink <de...@za...>
Date: Sun Apr 26 19:28:15 2020 +0200
target/armv7m_trace: Calculate prescaler for external capture devices
This fixes a regression introduced in "2dc88e1479f29ef0141b05bfcd907ad9a3e2d54c"
Change-Id: I04dc19ed30118a4c499b83732700b2ee0fdb67b6
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: http://openocd.zylin.com/5610
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <and...@gm...>
diff --git a/src/jtag/drivers/jlink.c b/src/jtag/drivers/jlink.c
index 80202ed29..1baf3454e 100644
--- a/src/jtag/drivers/jlink.c
+++ b/src/jtag/drivers/jlink.c
@@ -1324,18 +1324,16 @@ static int config_trace(bool enabled, enum tpiu_pin_protocol pin_protocol,
uint32_t min_freq;
uint32_t max_freq;
+ trace_enabled = enabled;
+
if (!jaylink_has_cap(caps, JAYLINK_DEV_CAP_SWO)) {
- LOG_ERROR("Trace capturing is not supported by the device.");
- return ERROR_FAIL;
- }
+ if (!enabled)
+ return ERROR_OK;
- if (pin_protocol != TPIU_PIN_PROTOCOL_ASYNC_UART) {
- LOG_ERROR("Selected pin protocol is not supported.");
+ LOG_ERROR("Trace capturing is not supported by the device.");
return ERROR_FAIL;
}
- trace_enabled = enabled;
-
ret = jaylink_swo_stop(devh);
if (ret != JAYLINK_OK) {
@@ -1354,6 +1352,11 @@ static int config_trace(bool enabled, enum tpiu_pin_protocol pin_protocol,
return ERROR_OK;
}
+ if (pin_protocol != TPIU_PIN_PROTOCOL_ASYNC_UART) {
+ LOG_ERROR("Selected pin protocol is not supported.");
+ return ERROR_FAIL;
+ }
+
buffer_size = calculate_trace_buffer_size();
if (!buffer_size) {
diff --git a/src/target/armv7m_trace.c b/src/target/armv7m_trace.c
index 853362f7e..6b368f7a0 100644
--- a/src/target/armv7m_trace.c
+++ b/src/target/armv7m_trace.c
@@ -68,6 +68,22 @@ int armv7m_trace_tpiu_config(struct target *target)
if (retval != ERROR_OK)
return retval;
+ if (trace_config->config_type == TRACE_CONFIG_TYPE_EXTERNAL) {
+ prescaler = trace_config->traceclkin_freq / trace_config->trace_freq;
+
+ if (trace_config->traceclkin_freq % trace_config->trace_freq) {
+ prescaler++;
+
+ int trace_freq = trace_config->traceclkin_freq / prescaler;
+ LOG_INFO("Can not obtain %u trace port frequency from %u "
+ "TRACECLKIN frequency, using %u instead",
+ trace_config->trace_freq, trace_config->traceclkin_freq,
+ trace_freq);
+
+ trace_config->trace_freq = trace_freq;
+ }
+ }
+
if (!trace_config->trace_freq) {
LOG_ERROR("Trace port frequency is 0, can't enable TPIU");
return ERROR_FAIL;
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/jlink.c | 17 ++++++++++-------
src/target/armv7m_trace.c | 16 ++++++++++++++++
2 files changed, 26 insertions(+), 7 deletions(-)
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2020-06-14 13:26:12
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- Log -----------------------------------------------------------------
commit 11116ef6ad875055a43cf9af1f228991349f2ba1
Author: Edward Fewell <ef...@ti...>
Date: Wed Jun 3 14:55:07 2020 -0500
target/icepick.cfg: Add support for Test TAPs in ICEPick C
In addition to the debug TAPs, the ICEPick C also supports
a bank of Test TAPs (limited functionality intended for
non-debuggable targets). Added support for Test TAPs to
the icepick_c_tapenable routine. Port numbers of 0 to 15
will continue to be handled as a debug TAP number. Test
TAPs will be port numbers of 16 to 31.
This functionality will be needed for doing a flash
mass erase on CC26xx/CC13xx targets. It is possible
for user application to block even adding the Cortex M
TAP to the scan chain, so the only way to unbrick the
target and erase the flash is using a component on a
test TAP of the device's ICEPick router.
Change-Id: I0aa52a08d43a00cbd396efdeadd504fc31c98510
Signed-off-by: Edward Fewell <ef...@ti...>
Reviewed-on: http://openocd.zylin.com/5715
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/icepick.cfg b/tcl/target/icepick.cfg
index 36b0b7033..d1250711b 100644
--- a/tcl/target/icepick.cfg
+++ b/tcl/target/icepick.cfg
@@ -75,9 +75,22 @@ proc icepick_c_setup {jrc} {
}
# jrc == TAP name for the ICEpick
-# port == a port number, 0..15
+# port == a port number, 0..15 for debug tap, 16..31 for test tap
proc icepick_c_tapenable {jrc port} {
+ if { ($port >= 0) && ($port < 16) } {
+ # Debug tap"
+ set tap $port
+ set block 0x2
+ } elseif { $port < 32 } {
+ # Test tap
+ set tap [expr ($port - 16)]
+ set block 0x1
+ } else {
+ echo "ERROR: Invalid ICEPick C port number: $port"
+ return
+ }
+
# First CONNECT to the ICEPick
# echo "Connecting to ICEPick"
icepick_c_connect $jrc
@@ -90,18 +103,18 @@ proc icepick_c_tapenable {jrc port} {
# And never to enter RESET, which will disable the TAPs.
# first enable power and clock for TAP
- icepick_c_router $jrc 1 0x2 $port 0x110048
+ icepick_c_router $jrc 1 $block $tap 0x110048
# TRM states that the register should be read back here, skipped for now
# enable debug "default" mode
- icepick_c_router $jrc 1 0x2 $port 0x112048
+ icepick_c_router $jrc 1 $block $tap 0x112048
# TRM states that debug enable and debug mode should be read back and
# confirmed - skipped for now
# Finally select the tap
- icepick_c_router $jrc 1 0x2 $port 0x112148
+ icepick_c_router $jrc 1 $block $tap 0x112148
# Enter the bypass state
irscan $jrc [CONST IR_BYPASS] -endstate RUN/IDLE
@@ -119,6 +132,7 @@ proc icepick_d_set_core_control {jrc coreid value } {
# Follow the sequence described in
# http://processors.wiki.ti.com/images/f/f6/Router_Scan_Sequence-ICEpick-D.pdf
proc icepick_d_tapenable {jrc port coreid { value 0x2008 } } {
+
# First CONNECT to the ICEPick
icepick_c_connect $jrc
icepick_c_setup $jrc
-----------------------------------------------------------------------
Summary of changes:
tcl/target/icepick.cfg | 22 ++++++++++++++++++----
1 file changed, 18 insertions(+), 4 deletions(-)
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