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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1382-gd88765a7e

From: OpenOCD-Gerrit <ope...@us...> - 2020-08-16 10:50:23

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the project "Main OpenOCD repository".

The branch, master has been updated
       via  d88765a7e2997c987ea7e5391378b3ae8b4fb59b (commit)
       via  401086186f2560b7c45ea53c200a0558f84437be (commit)
      from  105f8386ad92d27f0171d748f9b2a804a5317fd9 (commit)

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- Log -----------------------------------------------------------------
commit d88765a7e2997c987ea7e5391378b3ae8b4fb59b
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Apr 24 00:28:49 2020 +0200

    log: handle LOG_*() before calling to log_init()
    
    There are cases where LOG_*() functions are called before the logs
    are initialized with log_init().
    E.g. in transport_register() that is executed in gcc constructors,
    thus called even before main().
    With debug_level set to LOG_LVL_USER=-1 all the LOG_ERROR() get
    dropped.
    Properly initializing debug_level cause segmentation fault due to
    log_output still not initialized.
    
    Initialize debug_level to LOG_LVL_INFO so errors get printed.
    Handle separately the case of log_output still NULL, meaning that
    log_init() is not called yet.
    
    Change-Id: I2ea32c87a4955fb44e79b38131c456e25dfbc327
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5602
    Tested-by: jenkins

diff --git a/src/helper/log.c b/src/helper/log.c
index 31122554e..b05850df0 100644
--- a/src/helper/log.c
+++ b/src/helper/log.c
@@ -40,7 +40,7 @@
 #endif
 #endif
 
-int debug_level = -1;
+int debug_level = LOG_LVL_INFO;
 
 static FILE *log_output;
 static struct log_callback *log_callbacks;
@@ -91,6 +91,14 @@ static void log_puts(enum log_levels level,
 	const char *string)
 {
 	char *f;
+
+	if (!log_output) {
+		/* log_init() not called yet; print on stderr */
+		fputs(string, stderr);
+		fflush(stderr);
+		return;
+	}
+
 	if (level == LOG_LVL_OUTPUT) {
 		/* do not prepend any headers, just print out what we were given and return */
 		fputs(string, log_output);
@@ -277,9 +285,6 @@ void log_init(void)
 {
 	/* set defaults for daemon configuration,
 	 * if not set by cmdline or cfgfile */
-	if (debug_level == -1)
-		debug_level = LOG_LVL_INFO;
-
 	char *debug_env = getenv("OPENOCD_DEBUG_LEVEL");
 	if (NULL != debug_env) {
 		int value;

commit 401086186f2560b7c45ea53c200a0558f84437be
Author: Christopher Head <ch...@za...>
Date:   Mon Aug 10 11:09:02 2020 -0700

    server/gdb_server: fix incorrect condition check
    
    The warning message should be printed if the target is NOT halted, not
    if it IS halted.
    
    Change-Id: I0a38292a8a2e20e4a4a5ada92b475d551d4cbf38
    Signed-off-by: Christopher Head <ch...@za...>
    Reviewed-on: http://openocd.zylin.com/5794
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 61d7686c4..f94b72817 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -1025,7 +1025,7 @@ static int gdb_new_connection(struct connection *connection)
 		return ERROR_TARGET_NOT_EXAMINED;
 	}
 
-	if (target->state == TARGET_HALTED)
+	if (target->state != TARGET_HALTED)
 		LOG_WARNING("GDB connection %d on target %s not halted",
 					gdb_actual_connections, target_name(target));
 

-----------------------------------------------------------------------

Summary of changes:
 src/helper/log.c        | 13 +++++++++----
 src/server/gdb_server.c |  2 +-
 2 files changed, 10 insertions(+), 5 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1380-g105f8386a

From: OpenOCD-Gerrit <ope...@us...> - 2020-08-16 10:49:37

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- Log -----------------------------------------------------------------
commit 105f8386ad92d27f0171d748f9b2a804a5317fd9
Author: Hellosun Wu <wuj...@gm...>
Date:   Tue Oct 29 13:36:31 2019 +0800

    tcl: Add support for NDS V5 target and xc7/Corvette-F1
    
    The "Corvette-F1" is an Arduino-compatible evaluation platform,
    which fully supports AndesCore. The board has FTDI FT2232 to
    connected to FPGA's JTAG interface.
    
    The "ADP-XC7KFF676" is a development and prototyping board that
    provides capacity for evaluation of AndesCore processors.
    It works with AICE in-circuit debugging tools.
    
    This patch also include target/nds32v5.cfg to support AndesCore
    N22/N25F and AndeShape Platform AE250.
    
    Change-Id: I144d5063d5086d00ec44634a5028b5ea5d2eba33
    Signed-off-by: Hellosun Wu <wuj...@gm...>
    Reviewed-on: http://openocd.zylin.com/5338
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/board/nds32_corvettef1.cfg b/tcl/board/nds32_corvettef1.cfg
new file mode 100644
index 000000000..1a3782c68
--- /dev/null
+++ b/tcl/board/nds32_corvettef1.cfg
@@ -0,0 +1,18 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# ADP-Corvette-F1 R1.0
+# http://www.andestech.com/en/products-solutions/andeshape-platforms/corvette-f1-r1/
+# ADP-Corvette-F1 R2.0
+# http://www.andestech.com/en/products-solutions/andeshape-platforms/corvette-f1-r2/
+
+adapter_khz     10000
+
+adapter driver ftdi
+ftdi_device_desc "Dual RS232-HS"
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0c08 0x0f1b
+ftdi_layout_signal nTRST -data 0x0100 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0200 -noe 0x0800
+reset_config srst_only
+
+source [find target/nds32v5.cfg]
diff --git a/tcl/board/nds32_xc7.cfg b/tcl/board/nds32_xc7.cfg
new file mode 100644
index 000000000..82c00acd7
--- /dev/null
+++ b/tcl/board/nds32_xc7.cfg
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# ADP-XC7K160/410
+# http://www.andestech.com/en/products-solutions/andeshape-platforms/adp-xc7k160-410/
+
+source [find target/nds32v5.cfg]
diff --git a/tcl/target/nds32v5.cfg b/tcl/target/nds32v5.cfg
new file mode 100644
index 000000000..56b5fedfe
--- /dev/null
+++ b/tcl/target/nds32v5.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Andes Core
+#
+# http://www.andestech.com
+#
+
+set _CHIPNAME nds
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563D
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/nds32_corvettef1.cfg | 18 ++++++++++++++++++
 tcl/board/nds32_xc7.cfg        |  5 +++++
 tcl/target/nds32v5.cfg         | 12 ++++++++++++
 3 files changed, 35 insertions(+)
 create mode 100644 tcl/board/nds32_corvettef1.cfg
 create mode 100644 tcl/board/nds32_xc7.cfg
 create mode 100644 tcl/target/nds32v5.cfg


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1379-g6ec2ec4d3

From: OpenOCD-Gerrit <ope...@us...> - 2020-08-09 14:31:00

This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
       via  6ec2ec4d32e554a97c057e3f2f0839679f7e6291 (commit)
       via  37eac2dfbccf1a32ef598c1cf9e0e485147f9f71 (commit)
      from  998e60e9172863a949595c9cc529c78b345bffac (commit)

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- Log -----------------------------------------------------------------
commit 6ec2ec4d32e554a97c057e3f2f0839679f7e6291
Author: Christopher Head <ch...@za...>
Date:   Fri Jul 17 14:44:35 2020 -0700

    src/flash/nor/virtual: handle null pointers
    
    Either of protect and protect_check driver callbacks can be NULL. In
    virtual_protect, reuse flash_driver_protect which checks for that case
    and generates a nice error message and return code. In
    virtual_protect_check, there is no corresponding flash_driver_*
    function, so add the NULL check directly.
    
    Change-Id: Ia63d85ede640a8382cf5cad0760f5d1ffe4d7cfe
    Signed-off-by: Christopher Head <ch...@za...>
    Reviewed-on: http://openocd.zylin.com/5782
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/virtual.c b/src/flash/nor/virtual.c
index c9e1942ac..1aa12fecd 100644
--- a/src/flash/nor/virtual.c
+++ b/src/flash/nor/virtual.c
@@ -79,33 +79,25 @@ static int virtual_protect(struct flash_bank *bank, int set, unsigned int first,
 		unsigned int last)
 {
 	struct flash_bank *master_bank = virtual_get_master_bank(bank);
-	int retval;
 
 	if (master_bank == NULL)
 		return ERROR_FLASH_OPERATION_FAILED;
 
-	/* call master handler */
-	retval = master_bank->driver->protect(master_bank, set, first, last);
-	if (retval != ERROR_OK)
-		return retval;
-
-	return ERROR_OK;
+	return flash_driver_protect(master_bank, set, first, last);
 }
 
 static int virtual_protect_check(struct flash_bank *bank)
 {
 	struct flash_bank *master_bank = virtual_get_master_bank(bank);
-	int retval;
 
 	if (master_bank == NULL)
 		return ERROR_FLASH_OPERATION_FAILED;
 
-	/* call master handler */
-	retval = master_bank->driver->protect_check(master_bank);
-	if (retval != ERROR_OK)
-		return retval;
+	if (master_bank->driver->protect_check == NULL)
+		return ERROR_FLASH_OPER_UNSUPPORTED;
 
-	return ERROR_OK;
+	/* call master handler */
+	return master_bank->driver->protect_check(master_bank);
 }
 
 static int virtual_erase(struct flash_bank *bank, unsigned int first,

commit 37eac2dfbccf1a32ef598c1cf9e0e485147f9f71
Author: Christopher Head <ch...@za...>
Date:   Fri Jul 17 11:17:52 2020 -0700

    flash/nor/stm32f2x: clean up data types
    
    Change-Id: I677bc4487fc2eff2c32e14ca2db5470fddaa63b5
    Signed-off-by: Christopher Head <ch...@za...>
    Reviewed-on: http://openocd.zylin.com/5778
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c
index 6510e75dc..52bad4b0d 100644
--- a/src/flash/nor/stm32f2x.c
+++ b/src/flash/nor/stm32f2x.c
@@ -204,7 +204,7 @@ struct stm32x_flash_bank {
 	bool has_extra_options; /* F42x/43x/469/479/7xx */
 	bool has_boot_addr;     /* F7xx */
 	bool has_optcr2_pcrop;	/* F72x/73x */
-	int protection_bits;	/* F413/423 */
+	unsigned int protection_bits; /* F413/423 */
 	uint32_t user_bank_size;
 };
 
@@ -571,7 +571,7 @@ static int stm32x_protect_check(struct flash_bank *bank)
 {
 	struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 	struct flash_sector *prot_blocks;
-	int num_prot_blocks;
+	unsigned int num_prot_blocks;
 	int retval;
 
 	/* if it's the OTP bank, look at the lock bits there */
@@ -593,7 +593,7 @@ static int stm32x_protect_check(struct flash_bank *bank)
 		prot_blocks = bank->sectors;
 	}
 
-	for (int i = 0; i < num_prot_blocks; i++)
+	for (unsigned int i = 0; i < num_prot_blocks; i++)
 		prot_blocks[i].is_protected =
 			~(stm32x_info->option_bytes.protection >> i) & 1;
 
@@ -906,9 +906,8 @@ static void setup_sector(struct flash_bank *bank, unsigned int i,
 	LOG_DEBUG("sector %u: %ukBytes", i, size >> 10);
 }
 
-static uint16_t sector_size_in_kb(int i, uint16_t max_sector_size_in_kb)
+static uint16_t sector_size_in_kb(unsigned int i, uint16_t max_sector_size_in_kb)
 {
-	assert(i >= 0);
 	if (i < 4)
 		return max_sector_size_in_kb / 8;
 	if (i == 4)
@@ -916,13 +915,13 @@ static uint16_t sector_size_in_kb(int i, uint16_t max_sector_size_in_kb)
 	return max_sector_size_in_kb;
 }
 
-static int calculate_number_of_sectors(struct flash_bank *bank,
+static unsigned int calculate_number_of_sectors(struct flash_bank *bank,
 		uint16_t flash_size_in_kb,
 		uint16_t max_sector_size_in_kb)
 {
 	struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
 	uint16_t remaining_flash_size_in_kb = flash_size_in_kb;
-	int nr_sectors;
+	unsigned int nr_sectors;
 
 	/* Dual Bank Flash has two identically-arranged banks of sectors. */
 	if (stm32x_info->has_large_mem)
@@ -943,11 +942,11 @@ static int calculate_number_of_sectors(struct flash_bank *bank,
 	return stm32x_info->has_large_mem ? nr_sectors*2 : nr_sectors;
 }
 
-static void setup_bank(struct flash_bank *bank, int start,
+static void setup_bank(struct flash_bank *bank, unsigned int start,
 	uint16_t flash_size_in_kb, uint16_t max_sector_size_in_kb)
 {
 	uint16_t remaining_flash_size_in_kb = flash_size_in_kb;
-	int sector_index = 0;
+	unsigned int sector_index = 0;
 	while (remaining_flash_size_in_kb > 0) {
 		uint16_t size_in_kb = sector_size_in_kb(sector_index, max_sector_size_in_kb);
 		if (size_in_kb > remaining_flash_size_in_kb) {
@@ -996,7 +995,7 @@ static int stm32x_probe(struct flash_bank *bank)
 {
 	struct target *target = bank->target;
 	struct stm32x_flash_bank *stm32x_info = bank->driver_priv;
-	int i, num_prot_blocks, num_sectors;
+	unsigned int num_prot_blocks, num_sectors;
 	uint16_t flash_size_in_kb;
 	uint16_t otp_size_in_b;
 	uint16_t otp_sector_size;
@@ -1049,7 +1048,7 @@ static int stm32x_probe(struct flash_bank *bank)
 		else
 			bank->size = STM32F2_OTP_SIZE;
 
-		for (i = 0; i < num_sectors; i++) {
+		for (unsigned int i = 0; i < num_sectors; i++) {
 			bank->sectors[i].offset = i * otp_sector_size;
 			bank->sectors[i].size = otp_sector_size;
 			bank->sectors[i].is_erased = 1;
@@ -1190,18 +1189,18 @@ static int stm32x_probe(struct flash_bank *bank)
 	}
 
 	/* calculate numbers of pages */
-	int num_pages = calculate_number_of_sectors(
+	unsigned int num_pages = calculate_number_of_sectors(
 			bank, flash_size_in_kb, max_sector_size_in_kb);
 
 	bank->base = base_address;
 	bank->num_sectors = num_pages;
 	bank->sectors = calloc(num_pages, sizeof(struct flash_sector));
-	for (i = 0; i < num_pages; i++) {
+	for (unsigned int i = 0; i < num_pages; i++) {
 		bank->sectors[i].is_erased = -1;
 		bank->sectors[i].is_protected = 0;
 	}
 	bank->size = 0;
-	LOG_DEBUG("allocated %d sectors", num_pages);
+	LOG_DEBUG("allocated %u sectors", num_pages);
 
 	/* F76x/77x in dual bank mode */
 	if ((device_id == 0x451) && stm32x_info->has_large_mem)
@@ -1209,9 +1208,9 @@ static int stm32x_probe(struct flash_bank *bank)
 
 	if (num_prot_blocks) {
 		bank->prot_blocks = malloc(sizeof(struct flash_sector) * num_prot_blocks);
-		for (i = 0; i < num_prot_blocks; i++)
+		for (unsigned int i = 0; i < num_prot_blocks; i++)
 			bank->prot_blocks[i].is_protected = 0;
-		LOG_DEBUG("allocated %d prot blocks", num_prot_blocks);
+		LOG_DEBUG("allocated %u prot blocks", num_prot_blocks);
 	}
 
 	if (stm32x_info->has_large_mem) {
@@ -1222,7 +1221,7 @@ static int stm32x_probe(struct flash_bank *bank)
 
 		/* F767x/F77x in dual mode, one protection bit refers to two adjacent sectors */
 		if (device_id == 0x451) {
-			for (i = 0; i < num_prot_blocks; i++) {
+			for (unsigned int i = 0; i < num_prot_blocks; i++) {
 				bank->prot_blocks[i].offset = bank->sectors[i << 1].offset;
 				bank->prot_blocks[i].size = bank->sectors[i << 1].size
 						+ bank->sectors[(i << 1) + 1].size;
@@ -1234,7 +1233,7 @@ static int stm32x_probe(struct flash_bank *bank)
 
 		/* F413/F423, sectors 14 and 15 share one common protection bit */
 		if (device_id == 0x463) {
-			for (i = 0; i < num_prot_blocks; i++) {
+			for (unsigned int i = 0; i < num_prot_blocks; i++) {
 				bank->prot_blocks[i].offset = bank->sectors[i].offset;
 				bank->prot_blocks[i].size = bank->sectors[i].size;
 			}

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/stm32f2x.c | 35 +++++++++++++++++------------------
 src/flash/nor/virtual.c  | 18 +++++-------------
 2 files changed, 22 insertions(+), 31 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1377-g998e60e91

From: OpenOCD-Gerrit <ope...@us...> - 2020-08-09 14:30:32

This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
       via  998e60e9172863a949595c9cc529c78b345bffac (commit)
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- Log -----------------------------------------------------------------
commit 998e60e9172863a949595c9cc529c78b345bffac
Author: Christopher Head <ch...@za...>
Date:   Fri Jul 17 14:54:46 2020 -0700

    src/flash/nor/stm32h7x: fix format strings
    
    * use proper type codes
    * add 0x in front of hex values
    * remove some concatenated empty strings
    
    Change-Id: I06a8344d0ed62de7a0f3e2dd8fba69b17eeb3626
    Signed-off-by: Christopher Head <ch...@za...>
    Reviewed-on: http://openocd.zylin.com/5783
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c
index 72bfa5f5e..9f456b29d 100644
--- a/src/flash/nor/stm32h7x.c
+++ b/src/flash/nor/stm32h7x.c
@@ -262,7 +262,7 @@ static int stm32x_wait_flash_op_queue(struct flash_bank *bank, int timeout)
 			break;
 
 		if (timeout-- <= 0) {
-			LOG_ERROR("wait_flash_op_queue, time out expired, status: 0x%" PRIx32 "", status);
+			LOG_ERROR("wait_flash_op_queue, time out expired, status: 0x%" PRIx32, status);
 			return ERROR_FAIL;
 		}
 		alive_sleep(1);
@@ -311,7 +311,7 @@ static int stm32x_unlock_reg(struct flash_bank *bank)
 		return retval;
 
 	if (ctrl & FLASH_LOCK) {
-		LOG_ERROR("flash not unlocked STM32_FLASH_CRx: %" PRIx32, ctrl);
+		LOG_ERROR("flash not unlocked STM32_FLASH_CRx: 0x%" PRIx32, ctrl);
 		return ERROR_TARGET_FAILURE;
 	}
 	return ERROR_OK;
@@ -342,7 +342,7 @@ static int stm32x_unlock_option_reg(struct flash_bank *bank)
 		return retval;
 
 	if (ctrl & OPT_LOCK) {
-		LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: %" PRIx32, ctrl);
+		LOG_ERROR("options not unlocked STM32_FLASH_OPTCR: 0x%" PRIx32, ctrl);
 		return ERROR_TARGET_FAILURE;
 	}
 
@@ -396,7 +396,7 @@ static int stm32x_write_option(struct flash_bank *bank, uint32_t reg_offset, uin
 			break;
 
 		if (timeout-- <= 0) {
-			LOG_ERROR("waiting for OBL launch, time out expired, OPTSR: 0x%" PRIx32 "", status);
+			LOG_ERROR("waiting for OBL launch, time out expired, OPTSR: 0x%" PRIx32, status);
 			retval = ERROR_FAIL;
 			goto flash_options_lock;
 		}
@@ -626,7 +626,7 @@ static int stm32x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 			LOG_ERROR("flash memory write protected");
 
 		if ((flash_sr & FLASH_ERROR) != 0) {
-			LOG_ERROR("flash write failed, FLASH_SR = %08" PRIx32, flash_sr);
+			LOG_ERROR("flash write failed, FLASH_SR = 0x%08" PRIx32, flash_sr);
 			/* Clear error + EOP flags but report errors */
 			stm32x_write_flash_reg(bank, FLASH_CCR, flash_sr);
 			retval = ERROR_FAIL;
@@ -747,7 +747,7 @@ static int stm32x_probe(struct flash_bank *bank)
 	if (retval != ERROR_OK)
 		return retval;
 
-	LOG_DEBUG("device id = 0x%08" PRIx32 "", stm32x_info->idcode);
+	LOG_DEBUG("device id = 0x%08" PRIx32, stm32x_info->idcode);
 
 	device_id = stm32x_info->idcode & 0xfff;
 
@@ -779,7 +779,7 @@ static int stm32x_probe(struct flash_bank *bank)
 		/* read error when device has invalid value, set max flash size */
 		flash_size_in_kb = stm32x_info->part_info->max_flash_size_kb;
 	} else
-		LOG_INFO("flash size probed value %d", flash_size_in_kb);
+		LOG_INFO("flash size probed value %" PRIu16, flash_size_in_kb);
 
 
 
@@ -830,8 +830,8 @@ static int stm32x_probe(struct flash_bank *bank)
 		}
 	}
 
-	LOG_INFO("Bank (%u) size is %d kb, base address is 0x%" PRIx32,
-		bank->bank_number, flash_size_in_kb, (uint32_t) bank->base);
+	LOG_INFO("Bank (%u) size is %" PRIu16 " kb, base address is " TARGET_ADDR_FMT,
+		bank->bank_number, flash_size_in_kb, bank->base);
 
 	/* if the user sets the size manually then ignore the probed value
 	 * this allows us to work around devices that have an invalid flash size register value */
@@ -923,7 +923,7 @@ static int stm32x_get_info(struct flash_bank *bank, char *buf, int buf_size)
 				stm32x_info->part_info->device_str, rev_str);
 		} else {
 			snprintf(buf, buf_size,
-				 "%s - Rev: unknown (0x%04x)",
+				 "%s - Rev: unknown (0x%04" PRIx16 ")",
 				stm32x_info->part_info->device_str, rev_id);
 		}
 	} else {
@@ -1100,7 +1100,7 @@ COMMAND_HANDLER(stm32x_handle_option_read_command)
 	if (ERROR_OK != retval)
 		return retval;
 
-	command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "",
+	command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32,
 			stm32x_get_flash_reg(bank, reg_offset), value);
 
 	return retval;

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/stm32h7x.c | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)


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From: OpenOCD-Gerrit <ope...@us...> - 2020-08-08 21:18:35

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- Log -----------------------------------------------------------------
commit cd06642314c5b9b4b4c12b066fb3c17958afbe1f
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jul 11 16:37:28 2020 +0200

    target: fix memory leaks on target_create() fail
    
    There are failure cases of target_create() that are not checked.
    Plus, in case of failure the memory allocated in not properly
    released before returning error.
    
    Check all the possible failure in target_create().
    Change current_target only when target is successfully created.
    Add the new target to all_targets list only when target is
    successfully created.
    Release all the allocated memory before quit on failure.
    Use malloc() instead of calloc() for target->type, because the
    struct will be fully populated with memcpy().
    
    Change-Id: Ib6f91cbb50c28878e7c73dc070b17b8d7d4e902f
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5776
    Tested-by: jenkins

diff --git a/src/target/target.c b/src/target/target.c
index 5efa088b2..4ef5ee19e 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -344,6 +344,15 @@ static int new_target_number(void)
 	return x + 1;
 }
 
+static void append_to_list_all_targets(struct target *target)
+{
+	struct target **t = &all_targets;
+
+	while (*t)
+		t = &((*t)->next);
+	*t = target;
+}
+
 /* read a uint64_t from a buffer in target memory endianness */
 uint64_t target_buffer_get_u64(struct target *target, const uint8_t *buffer)
 {
@@ -5487,12 +5496,21 @@ static int target_create(Jim_GetOptInfo *goi)
 
 	/* Create it */
 	target = calloc(1, sizeof(struct target));
+	if (!target) {
+		LOG_ERROR("Out of memory");
+		return JIM_ERR;
+	}
+
 	/* set target number */
 	target->target_number = new_target_number();
-	cmd_ctx->current_target = target;
 
 	/* allocate memory for each unique target type */
-	target->type = calloc(1, sizeof(struct target_type));
+	target->type = malloc(sizeof(struct target_type));
+	if (!target->type) {
+		LOG_ERROR("Out of memory");
+		free(target);
+		return JIM_ERR;
+	}
 
 	memcpy(target->type, target_types[x], sizeof(struct target_type));
 
@@ -5521,6 +5539,12 @@ static int target_create(Jim_GetOptInfo *goi)
 
 	/* initialize trace information */
 	target->trace_info = calloc(1, sizeof(struct trace));
+	if (!target->trace_info) {
+		LOG_ERROR("Out of memory");
+		free(target->type);
+		free(target);
+		return JIM_ERR;
+	}
 
 	target->dbgmsg          = NULL;
 	target->dbg_msg_enabled = 0;
@@ -5554,7 +5578,9 @@ static int target_create(Jim_GetOptInfo *goi)
 	}
 
 	if (e != JIM_OK) {
+		rtos_destroy(target);
 		free(target->gdb_port_override);
+		free(target->trace_info);
 		free(target->type);
 		free(target);
 		return e;
@@ -5567,14 +5593,25 @@ static int target_create(Jim_GetOptInfo *goi)
 
 	cp = Jim_GetString(new_cmd, NULL);
 	target->cmd_name = strdup(cp);
+	if (!target->cmd_name) {
+		LOG_ERROR("Out of memory");
+		rtos_destroy(target);
+		free(target->gdb_port_override);
+		free(target->trace_info);
+		free(target->type);
+		free(target);
+		return JIM_ERR;
+	}
 
 	if (target->type->target_create) {
 		e = (*(target->type->target_create))(target, goi->interp);
 		if (e != ERROR_OK) {
 			LOG_DEBUG("target_create failed");
+			free(target->cmd_name);
+			rtos_destroy(target);
 			free(target->gdb_port_override);
+			free(target->trace_info);
 			free(target->type);
-			free(target->cmd_name);
 			free(target);
 			return JIM_ERR;
 		}
@@ -5587,15 +5624,6 @@ static int target_create(Jim_GetOptInfo *goi)
 			LOG_ERROR("unable to register '%s' commands", cp);
 	}
 
-	/* append to end of list */
-	{
-		struct target **tpp;
-		tpp = &(all_targets);
-		while (*tpp)
-			tpp = &((*tpp)->next);
-		*tpp = target;
-	}
-
 	/* now - create the new target name command */
 	const struct command_registration target_subcommands[] = {
 		{
@@ -5617,14 +5645,27 @@ static int target_create(Jim_GetOptInfo *goi)
 		COMMAND_REGISTRATION_DONE
 	};
 	e = register_commands(cmd_ctx, NULL, target_commands);
-	if (ERROR_OK != e)
+	if (e != ERROR_OK) {
+		if (target->type->deinit_target)
+			target->type->deinit_target(target);
+		free(target->cmd_name);
+		rtos_destroy(target);
+		free(target->gdb_port_override);
+		free(target->trace_info);
+		free(target->type);
+		free(target);
 		return JIM_ERR;
+	}
 
 	struct command *c = command_find_in_context(cmd_ctx, cp);
 	assert(c);
 	command_set_handler_data(c, target);
 
-	return (ERROR_OK == e) ? JIM_OK : JIM_ERR;
+	/* append to end of list */
+	append_to_list_all_targets(target);
+
+	cmd_ctx->current_target = target;
+	return JIM_OK;
 }
 
 static int jim_target_current(Jim_Interp *interp, int argc, Jim_Obj *const *argv)

-----------------------------------------------------------------------

Summary of changes:
 src/target/target.c | 69 ++++++++++++++++++++++++++++++++++++++++++-----------
 1 file changed, 55 insertions(+), 14 deletions(-)


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From: OpenOCD-Gerrit <ope...@us...> - 2020-08-08 21:18:07

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       via  6d45e485f98bb1712c0ec2f48c879ceaf6fd06ac (commit)
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- Log -----------------------------------------------------------------
commit 2f92598f0d6d8304a9c15f7050c9e888279cd2fa
Author: Antonio Borneo <bor...@gm...>
Date:   Tue Jun 4 12:06:44 2019 +0200

    gdb_server: refuse gdb connection if target is not examined
    
    If the target is not examined, many internal data required for the
    gdb connections are not ready nor allocated. This causes OpenOCD
    to hit a segmentation fault.
    
    After the execution of the gdb-attach event handler, check if
    target has been examined and eventually return error to refuse the
    gdb connection.
    
    Plus, since OpenOCD does not implements non-stop mode yet, gdb
    expects the target to be halted by the inferior when the
    connection is established.
    Print a warning to inform the user in case the target is not
    halted, but still accept the gdb connection to permit the
    non-intrusive memory inspection with gdb, as explained in
    http://openocd.org/doc/html/GDB-and-OpenOCD.html#gdbmeminspect
    
    Change-Id: If727d68f683c3a94e4826e8c62977de41274ceff
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5201
    Tested-by: jenkins

diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 327d96b17..61d7686c4 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -1018,6 +1018,17 @@ static int gdb_new_connection(struct connection *connection)
 			target_name(target),
 			target_state_name(target));
 
+	if (!target_was_examined(target)) {
+		LOG_ERROR("Target %s not examined yet, refuse gdb connection %d!",
+				  target_name(target), gdb_actual_connections);
+		gdb_actual_connections--;
+		return ERROR_TARGET_NOT_EXAMINED;
+	}
+
+	if (target->state == TARGET_HALTED)
+		LOG_WARNING("GDB connection %d on target %s not halted",
+					gdb_actual_connections, target_name(target));
+
 	/* DANGER! If we fail subsequently, we must remove this handler,
 	 * otherwise we occasionally see crashes as the timer can invoke the
 	 * callback fn.

commit 6d45e485f98bb1712c0ec2f48c879ceaf6fd06ac
Author: Mikhail Rasputin <mik...@ya...>
Date:   Sat Jun 27 23:30:42 2020 +0300

    target: fix registers reading from non examined target
    
    If a target is not examined when the debugger tries to connect to it
    then it can lead to undesired/undefined behavior.
    
    In particular it leads to a zero pointer dereference on the aarch64.
    
    
    Change-Id: I67f2b714ab8b2727fd36f3de16d7f9017b4c55fe
    Signed-off-by: Mikhail Rasputin <mik...@ya...>
    Reviewed-on: http://openocd.zylin.com/5727
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/target.c b/src/target/target.c
index b39254826..5efa088b2 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -1224,8 +1224,17 @@ int target_get_gdb_reg_list(struct target *target,
 		struct reg **reg_list[], int *reg_list_size,
 		enum target_register_class reg_class)
 {
-	int result = target->type->get_gdb_reg_list(target, reg_list,
+	int result = ERROR_FAIL;
+
+	if (!target_was_examined(target)) {
+		LOG_ERROR("Target not examined yet");
+		goto done;
+	}
+
+	result = target->type->get_gdb_reg_list(target, reg_list,
 			reg_list_size, reg_class);
+
+done:
 	if (result != ERROR_OK) {
 		*reg_list = NULL;
 		*reg_list_size = 0;

-----------------------------------------------------------------------

Summary of changes:
 src/server/gdb_server.c | 11 +++++++++++
 src/target/target.c     | 11 ++++++++++-
 2 files changed, 21 insertions(+), 1 deletion(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1373-g86777768e

From: OpenOCD-Gerrit <ope...@us...> - 2020-08-08 21:17:34

This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
       via  86777768ebef236f1f90a4abb6a6e1487884d753 (commit)
      from  fa9a4d4db5cfe44b7aadb1b8ef220f94423742a1 (commit)

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- Log -----------------------------------------------------------------
commit 86777768ebef236f1f90a4abb6a6e1487884d753
Author: R. Diez <rdi...@ya...>
Date:   Thu Apr 30 16:28:28 2020 +0200

    Fix 2 warnings about obsolete Autoconf macros.
    
    Those changes were automatically suggested by tool "autoupdate".
    
    Change-Id: Id70bdeacc3c80816f3f5c65d1abceabb5cdf3873
    Signed-off-by: R. Diez <rdi...@ya...>
    Reviewed-on: http://openocd.zylin.com/5638
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/configure.ac b/configure.ac
index 8bdeacdd7..90ac2a98c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -22,7 +22,7 @@ AH_BOTTOM([
 #include <helper/replacements.h>
 ])
 
-AC_LANG_C
+AC_LANG([C])
 AC_PROG_CC
 AC_PROG_CC_C99
 AM_PROG_CC_C_O
@@ -34,7 +34,7 @@ m4_defun([_LT_AC_LANG_CXX_CONFIG], [:])
 m4_defun([_LT_AC_LANG_F77_CONFIG], [:])
 m4_defun([_LT_AC_LANG_GCJ_CONFIG], [:])
 AC_DISABLE_SHARED
-AC_PROG_LIBTOOL
+LT_INIT
 AC_SUBST([LIBTOOL_DEPS])
 
 dnl configure checks required for Jim files (these are obsolete w/ C99)

-----------------------------------------------------------------------

Summary of changes:
 configure.ac | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


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From: OpenOCD-Gerrit <ope...@us...> - 2020-08-02 09:50:40

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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit fa9a4d4db5cfe44b7aadb1b8ef220f94423742a1
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Jul 27 00:29:50 2020 +0200

    tcl/interface: snps_sdp: fix minor typo s/similiar/similar/
    
    Change-Id: I4fd6af560278b3e114cc5d8ee1b49b5c4521d8be
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Fixes: b2821b607460 ("Introduce tcl config files for Synopsys HSDK board")
    Reviewed-on: http://openocd.zylin.com/5788
    Tested-by: jenkins
    Reviewed-by: Evgeniy Didin <di...@sy...>

diff --git a/tcl/interface/ftdi/snps_sdp.cfg b/tcl/interface/ftdi/snps_sdp.cfg
index 8d91c6d3c..3aed2ae20 100644
--- a/tcl/interface/ftdi/snps_sdp.cfg
+++ b/tcl/interface/ftdi/snps_sdp.cfg
@@ -5,7 +5,7 @@
 #  SPDX-License-Identifier: GPL-2.0-or-later
 
 #
-# Synopsys SDP Mainboard has embdded FT2232 chip, which is similiar to Digilent
+# Synopsys SDP Mainboard has embdded FT2232 chip, which is similar to Digilent
 # HS-1, except that it uses channel B for JTAG communication, instead of
 # channel A.
 #

-----------------------------------------------------------------------

Summary of changes:
 tcl/interface/ftdi/snps_sdp.cfg | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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From: OpenOCD-Gerrit <ope...@us...> - 2020-08-02 09:49:57

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- Log -----------------------------------------------------------------
commit e0c16c4c8f7aea03b9e2a4b453c6fbda165dec71
Author: Antonio Borneo <bor...@gm...>
Date:   Wed Jul 22 12:10:26 2020 +0200

    tcl/target/armada370: remove useless 'init' command
    
    As the comment states, the 'init' command is issued before the
    command 'dap apsel', otherwise it fails.
    This dependency has been already fixed in commit e48690cb26e4
    ("target/arm_adi_v5: allow commands apsel and apcsw during init
    phase"), so the command 'dap apsel' can now be issued directly.
    
    Remove both the unneeded 'init' command and the comment that
    documents and justify its presence.
    
    Change-Id: I50f0a820fa7ead6f5a3bd9cc5180d521070822c9
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5786
    Tested-by: jenkins

diff --git a/tcl/target/armada370.cfg b/tcl/target/armada370.cfg
index 3b4be9f08..71652748f 100644
--- a/tcl/target/armada370.cfg
+++ b/tcl/target/armada370.cfg
@@ -28,6 +28,4 @@ proc armada370_dbginit {target} {
 
 $_TARGETNAME configure -event reset-assert-post "armada370_dbginit $_TARGETNAME"
 
-# We need to init now, so we can run the apsel command.
-init
 dap apsel 1

commit 7c66df13ef5e45c085786206ef061047b522c18e
Author: Antonio Borneo <bor...@gm...>
Date:   Mon May 25 12:04:17 2020 +0200

    target/arm11: fix memory leaks, including register cache
    
    There is no deinit_target method, so few memory allocations leak
    at openocd exit.
    Issue identified by tracking all calls to arm_dpm_setup().
    
    Implement the method arm11_dpm_deinit() to free all the memory
    allocated in arm11_dpm_init() and call it in the new
    arm11_deinit_target().
    
    NOT TESTED on real HW.
    
    Change-Id: Icab86e290fc2db14f70eb84c8286357aadb02a35
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5694
    Tested-by: jenkins

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 10a1d6de5..68d4e1894 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -1131,6 +1131,14 @@ static int arm11_init_target(struct command_context *cmd_ctx,
 	return ERROR_OK;
 }
 
+static void arm11_deinit_target(struct target *target)
+{
+	struct arm11_common *arm11 = target_to_arm11(target);
+
+	arm11_dpm_deinit(arm11);
+	free(arm11);
+}
+
 /* talk to the target and set things up */
 static int arm11_examine(struct target *target)
 {
@@ -1379,5 +1387,6 @@ struct target_type arm11_target = {
 	.commands = arm11_command_handlers,
 	.target_create = arm11_target_create,
 	.init_target = arm11_init_target,
+	.deinit_target = arm11_deinit_target,
 	.examine = arm11_examine,
 };
diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index a758db58f..60be0096f 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -1193,3 +1193,13 @@ int arm11_dpm_init(struct arm11_common *arm11, uint32_t didr)
 
 	return arm11_bpwp_flush(arm11);
 }
+
+void arm11_dpm_deinit(struct arm11_common *arm11)
+{
+	struct arm_dpm *dpm = &arm11->dpm;
+
+	free(arm11->bpwp_actions);
+	arm_free_reg_cache(dpm->arm);
+	free(dpm->dbp);
+	free(dpm->dwp);
+}
diff --git a/src/target/arm11_dbgtap.h b/src/target/arm11_dbgtap.h
index 541434edc..be0248411 100644
--- a/src/target/arm11_dbgtap.h
+++ b/src/target/arm11_dbgtap.h
@@ -78,6 +78,7 @@ int arm11_read_memory_word(struct arm11_common *arm11,
 		uint32_t address, uint32_t *result);
 
 int arm11_dpm_init(struct arm11_common *arm11, uint32_t didr);
+void arm11_dpm_deinit(struct arm11_common *arm11);
 int arm11_bpwp_flush(struct arm11_common *arm11);
 
 #endif /* OPENOCD_TARGET_ARM11_DBGTAP_H */

commit 768502403ee0513d0e289c22b27c7296300fe39d
Author: Antonio Borneo <bor...@gm...>
Date:   Tue May 19 16:41:17 2020 +0200

    target: use one second timeout while halting target at gdb attach
    
    By default GDB timeouts after 2 seconds, even if this value can be
    modified with GDB command "set remotetimeout".
    On OpenOCD side, the default event for GDB attach is to halt the
    target and wait it to halt. But here the default timeout of the
    halt command is 5 seconds!
    If the target cannot be halted (e.g. it's kept in reset by another
    core or the debugger doesn't have enough privileges) then GDB will
    timeout while OpenOCD is still waiting and is unable to
    communicate with GDB.
    
    Decrease the halt timeout to 1 second in the default GDB attach
    event handler.
    
    Change-Id: I231c740816bb6a0d74b0bc679a368a6cbfb34824
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5687
    Tested-by: jenkins

diff --git a/src/target/startup.tcl b/src/target/startup.tcl
index 93e46b5f8..ca39b1816 100644
--- a/src/target/startup.tcl
+++ b/src/target/startup.tcl
@@ -205,7 +205,7 @@ proc init_target_events {} {
 	foreach t $targets {
 		set_default_target_event $t gdb-flash-erase-start "reset init"
 		set_default_target_event $t gdb-flash-write-end "reset halt"
-		set_default_target_event $t gdb-attach "halt"
+		set_default_target_event $t gdb-attach "halt 1000"
 	}
 }
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm11.c        |  9 +++++++++
 src/target/arm11_dbgtap.c | 10 ++++++++++
 src/target/arm11_dbgtap.h |  1 +
 src/target/startup.tcl    |  2 +-
 tcl/target/armada370.cfg  |  2 --
 5 files changed, 21 insertions(+), 3 deletions(-)


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- Log -----------------------------------------------------------------
commit 33b52174e6a0fc7513059e27dea18dee7b105781
Author: Antonio Borneo <bor...@gm...>
Date:   Thu Jun 11 23:55:18 2020 +0200

    nulink: add minimal support for Nu-Link2
    
    Implementation largely taken from Nuvoton github
            https://github.com/OpenNuvoton/OpenOCD-Nuvoton
    
    Reset is still not fully compatible with OpenOCD framework.
    Adapted to hidapi.
    
    Change-Id: Ieb1791b1b7f0b444c15c9668f8f2bcf34975d48f
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Signed-off-by: Zale Yu <cy...@nu...>
    Reviewed-on: http://openocd.zylin.com/5720
    Tested-by: jenkins
    Reviewed-by: Saravanan Sekar <sar...@li...>
    Reviewed-by: Marc Schink <de...@za...>

diff --git a/contrib/60-openocd.rules b/contrib/60-openocd.rules
index be27590ba..53f97dd83 100644
--- a/contrib/60-openocd.rules
+++ b/contrib/60-openocd.rules
@@ -59,6 +59,8 @@ ATTRS{idVendor}=="0403", ATTRS{idProduct}=="cff8", MODE="660", GROUP="plugdev",
 ATTRS{idVendor}=="0416", ATTRS{idProduct}=="511b", MODE="660", GROUP="plugdev", TAG+="uaccess"
 ATTRS{idVendor}=="0416", ATTRS{idProduct}=="511c", MODE="660", GROUP="plugdev", TAG+="uaccess"
 ATTRS{idVendor}=="0416", ATTRS{idProduct}=="511d", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0416", ATTRS{idProduct}=="5200", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0416", ATTRS{idProduct}=="5201", MODE="660", GROUP="plugdev", TAG+="uaccess"
 
 # TI ICDI
 ATTRS{idVendor}=="0451", ATTRS{idProduct}=="c32a", MODE="660", GROUP="plugdev", TAG+="uaccess"
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 958cde49e..8c99228c3 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -509,7 +509,7 @@ evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
 Nuvoton has an adapter called @b{Nu-Link}.
 It is available either as stand-alone dongle and embedded on development boards.
 It supports SWD, serial port bridge and mass storage for firmware update.
-Only Nu-Link v1 is currently supported.
+Both Nu-Link v1 and v2 are supported.
 
 @section USB CMSIS-DAP based
 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
diff --git a/src/jtag/drivers/nulink_usb.c b/src/jtag/drivers/nulink_usb.c
index 3b0885b7a..5fdbed3fc 100644
--- a/src/jtag/drivers/nulink_usb.c
+++ b/src/jtag/drivers/nulink_usb.c
@@ -35,18 +35,27 @@
 #define NULINK_READ_TIMEOUT  1000
 
 #define NULINK_HID_MAX_SIZE   (64)
+#define NULINK2_HID_MAX_SIZE   (1024)
 #define V6M_MAX_COMMAND_LENGTH (NULINK_HID_MAX_SIZE - 2)
+#define V7M_MAX_COMMAND_LENGTH (NULINK_HID_MAX_SIZE - 3)
+
+#define NULINK2_USB_PID1  (0x5200)
+#define NULINK2_USB_PID2  (0x5201)
 
 struct nulink_usb_handle_s {
 	hid_device *dev_handle;
 	uint16_t max_packet_size;
 	uint8_t usbcmdidx;
 	uint8_t cmdidx;
-	uint8_t cmdbuf[NULINK_HID_MAX_SIZE + 1];
-	uint8_t tempbuf[NULINK_HID_MAX_SIZE];
-	uint8_t databuf[NULINK_HID_MAX_SIZE];
+	uint8_t cmdsize;
+	uint8_t cmdbuf[NULINK2_HID_MAX_SIZE + 1];
+	uint8_t tempbuf[NULINK2_HID_MAX_SIZE];
+	uint8_t databuf[NULINK2_HID_MAX_SIZE];
 	uint32_t max_mem_packet;
 	uint16_t hardware_config; /* bit 0: 1:Nu-Link-Pro, 0:Nu-Link */
+
+	int (*xfer)(void *handle, uint8_t *buf, int size);
+	void (*init_buffer)(void *handle, uint32_t size);
 };
 
 /* ICE Command */
@@ -65,6 +74,7 @@ struct nulink_usb_handle_s {
 #define ARM_SRAM_BASE				0x20000000UL
 
 #define HARDWARE_CONFIG_NULINKPRO	1
+#define HARDWARE_CONFIG_NULINK2		2
 
 enum nulink_reset {
 	RESET_AUTO = 0,
@@ -103,7 +113,7 @@ static int nulink_usb_xfer_rw(void *handle, uint8_t *buf)
 	return ERROR_OK;
 }
 
-static int nulink_usb_xfer(void *handle, uint8_t *buf, int size)
+static int nulink1_usb_xfer(void *handle, uint8_t *buf, int size)
 {
 	struct nulink_usb_handle_s *h = handle;
 
@@ -116,7 +126,20 @@ static int nulink_usb_xfer(void *handle, uint8_t *buf, int size)
 	return err;
 }
 
-static void nulink_usb_init_buffer(void *handle, uint32_t size)
+static int nulink2_usb_xfer(void *handle, uint8_t *buf, int size)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	assert(handle);
+
+	int err = nulink_usb_xfer_rw(h, h->tempbuf);
+
+	memcpy(buf, h->tempbuf + 3, V7M_MAX_COMMAND_LENGTH);
+
+	return err;
+}
+
+static void nulink1_usb_init_buffer(void *handle, uint32_t size)
 {
 	struct nulink_usb_handle_s *h = handle;
 
@@ -132,6 +155,40 @@ static void nulink_usb_init_buffer(void *handle, uint32_t size)
 	h->cmdidx += 3;
 }
 
+static void nulink2_usb_init_buffer(void *handle, uint32_t size)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	h->cmdidx = 0;
+
+	memset(h->cmdbuf, 0, h->max_packet_size + 1);
+	memset(h->tempbuf, 0, h->max_packet_size);
+	memset(h->databuf, 0, h->max_packet_size);
+
+	h->cmdbuf[0] = 0; /* report number */
+	h->cmdbuf[1] = ++h->usbcmdidx & 0x7F;
+	h_u16_to_le(h->cmdbuf + 2, size);
+	h->cmdidx += 4;
+}
+
+static inline int nulink_usb_xfer(void *handle, uint8_t *buf, int size)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	assert(handle);
+
+	return h->xfer(handle, buf, size);
+}
+
+static inline void nulink_usb_init_buffer(void *handle, uint32_t size)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	assert(handle);
+
+	h->init_buffer(handle, size);
+}
+
 static int nulink_usb_version(void *handle)
 {
 	struct nulink_usb_handle_s *h = handle;
@@ -146,7 +203,7 @@ static int nulink_usb_version(void *handle)
 	h->cmdbuf[h->cmdidx + 4] = 0xA1; /* host_rev_num: 6561 */;
 	h->cmdbuf[h->cmdidx + 5] = 0x19;
 
-	int res = nulink_usb_xfer(handle, h->databuf, 4 * 5);
+	int res = nulink_usb_xfer(handle, h->databuf, h->cmdsize);
 	if (res != ERROR_OK)
 		return res;
 
@@ -1054,13 +1111,33 @@ static int nulink_usb_open(struct hl_interface_param_s *param, void **fd)
 
 	h->dev_handle = dev;
 	h->usbcmdidx = 0;
-	h->hardware_config = 0;
-	h->max_packet_size = NULINK_HID_MAX_SIZE;
+
+	switch (target_pid) {
+	case NULINK2_USB_PID1:
+	case NULINK2_USB_PID2:
+		h->hardware_config = HARDWARE_CONFIG_NULINK2;
+		h->max_packet_size = NULINK2_HID_MAX_SIZE;
+		h->init_buffer = nulink2_usb_init_buffer;
+		h->xfer = nulink2_usb_xfer;
+		break;
+	default:
+		h->hardware_config = 0;
+		h->max_packet_size = NULINK_HID_MAX_SIZE;
+		h->init_buffer = nulink1_usb_init_buffer;
+		h->xfer = nulink1_usb_xfer;
+		break;
+	}
 
 	/* get the device version */
+	h->cmdsize = 4 * 5;
 	int err = nulink_usb_version(h);
-	if (err != ERROR_OK)
-		goto error_open;
+	if (err != ERROR_OK) {
+		LOG_DEBUG("nulink_usb_version failed with cmdSize(4 * 5)");
+		h->cmdsize = 4 * 6;
+		err = nulink_usb_version(h);
+		if (err != ERROR_OK)
+			LOG_DEBUG("nulink_usb_version failed with cmdSize(4 * 6)");
+	}
 
 	/* SWD clock rate : 1MHz */
 	nulink_speed(h, 1000, false);
diff --git a/tcl/interface/nulink.cfg b/tcl/interface/nulink.cfg
index 08c8216c6..e49b36cda 100644
--- a/tcl/interface/nulink.cfg
+++ b/tcl/interface/nulink.cfg
@@ -5,7 +5,7 @@
 adapter driver hla
 hla_layout nulink
 hla_device_desc "Nu-Link"
-hla_vid_pid 0x0416 0x511b 0x0416 0x511c 0x0416 0x511d
+hla_vid_pid 0x0416 0x511b 0x0416 0x511c 0x0416 0x511d 0x0416 0x5200 0x0416 0x5201
 
 # Only swd is supported
 transport select hla_swd

-----------------------------------------------------------------------

Summary of changes:
 contrib/60-openocd.rules      |  2 +
 doc/openocd.texi              |  2 +-
 src/jtag/drivers/nulink_usb.c | 97 ++++++++++++++++++++++++++++++++++++++-----
 tcl/interface/nulink.cfg      |  2 +-
 4 files changed, 91 insertions(+), 12 deletions(-)


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From: OpenOCD-Gerrit <ope...@us...> - 2020-08-02 09:48:20

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- Log -----------------------------------------------------------------
commit c6a2621f9f2d6adab043c796b7a91410ebe25b65
Author: Michael Betz <mic...@gm...>
Date:   Sun Jul 26 13:51:06 2020 -0700

    nor/spi.c: add N25Q032A flash chip
    
    this flash is used on the Digilent CMODA7 FPGA board
    
    Change-Id: I6749ca3fbebf2e384051a26a3fd253da5d6e25fb
    Signed-off-by: Michael Betz <mic...@gm...>
    Reviewed-on: http://openocd.zylin.com/5787
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/spi.c b/src/flash/nor/spi.c
index 54ee57e66..937c194e6 100644
--- a/src/flash/nor/spi.c
+++ b/src/flash/nor/spi.c
@@ -89,6 +89,7 @@ const struct flash_device flash_devices[] = {
 	FLASH_ID("mac 25r3235f",        0x03, 0x00, 0x02, 0xd8, 0xc7, 0x001628c2, 0x100, 0x10000, 0x400000),
 	FLASH_ID("mac 25r6435f",        0x03, 0x00, 0x02, 0xd8, 0xc7, 0x001728c2, 0x100, 0x10000, 0x800000),
 	FLASH_ID("mac 25u1635e",        0x03, 0xeb, 0x02, 0x20, 0xc7, 0x003525c2, 0x100, 0x1000,  0x100000),
+	FLASH_ID("micron n25q032",      0x03, 0xeb, 0x02, 0xd8, 0xc7, 0x0016ba20, 0x100, 0x10000, 0x400000),
 	FLASH_ID("micron n25q064",      0x03, 0xeb, 0x02, 0xd8, 0xc7, 0x0017ba20, 0x100, 0x10000, 0x800000),
 	FLASH_ID("micron n25q128",      0x03, 0xeb, 0x02, 0xd8, 0xc7, 0x0018ba20, 0x100, 0x10000, 0x1000000),
 	FLASH_ID("micron n25q256 3v",   0x13, 0xec, 0x12, 0xdc, 0xc7, 0x0019ba20, 0x100, 0x10000, 0x2000000),

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/spi.c | 1 +
 1 file changed, 1 insertion(+)


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commit b12fca236d191b0f280aaea0b63a5789480b5e05
Author: Zale Yu <cy...@nu...>
Date:   Wed Apr 29 16:53:52 2020 +0200

    jtag/drivers: add support for Nu-Link (Nuvoton ICE) over usb
    
    Add support for Nu-Link1 over usb hidapi and config file.
    
    The original work is fetched from Nuvoton github.
    Code cleanup, fix merge conflicts, compile and runtime issues.
    Switch the code from libusb to hidapi, being the device HID based.
    Add documentation.
    Merge fixes for multi-word memory read.
    
    Reset is not fully compatible with openocd framework; currently
    the target is reset and then halt at openocd start.
    
    Change-Id: I9738de4e26783ba462ea3e39ec32069fd5bb7d94
    Signed-off-by: Zale Yu <cy...@nu...>
    Signed-off-by: Saravanan Sekar <sar...@li...>
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5635
    Tested-by: jenkins
    Reviewed-by: Marc Schink <de...@za...>

diff --git a/configure.ac b/configure.ac
index 4d8c91635..8bdeacdd7 100644
--- a/configure.ac
+++ b/configure.ac
@@ -127,7 +127,8 @@ m4_define([USB0_ADAPTERS],
 	[[armjtagew], [Olimex ARM-JTAG-EW Programmer], [ARMJTAGEW]]])
 
 m4_define([HIDAPI_ADAPTERS],
-	[[[cmsis_dap], [CMSIS-DAP Compliant Debugger], [CMSIS_DAP]]])
+	[[[cmsis_dap], [CMSIS-DAP Compliant Debugger], [CMSIS_DAP]],
+	[[nulink], [Nu-Link Programmer], [HLADAPTER_NULINK]]])
 
 m4_define([HIDAPI_USB1_ADAPTERS],
 	[[[kitprog], [Cypress KitProg Programmer], [KITPROG]]])
@@ -696,7 +697,7 @@ AS_IF([test "x$enable_linuxgpiod" != "xno"], [
   build_bitbang=yes
 ])
 
-AS_IF([test "x$enable_stlink" != "xno" -o "x$enable_ti_icdi" != "xno"], [
+AS_IF([test "x$enable_stlink" != "xno" -o "x$enable_ti_icdi" != "xno" -o "x$enable_nulink" != "xno"], [
 	AC_DEFINE([BUILD_HLADAPTER], [1], [1 if you want the High Level JTAG driver.])
 	AM_CONDITIONAL([HLADAPTER], [true])
 ], [
@@ -705,6 +706,7 @@ AS_IF([test "x$enable_stlink" != "xno" -o "x$enable_ti_icdi" != "xno"], [
 ])
 AM_CONDITIONAL([HLADAPTER_STLINK], [test "x$enable_stlink" != "xno"])
 AM_CONDITIONAL([HLADAPTER_ICDI], [test "x$enable_ti_icdi" != "xno"])
+AM_CONDITIONAL([HLADAPTER_NULINK], [test "x$enable_nulink" != "xno"])
 
 AS_IF([test "x$enable_jlink" != "xno"], [
   AS_IF([test "x$use_internal_libjaylink" = "xyes"], [
diff --git a/contrib/60-openocd.rules b/contrib/60-openocd.rules
index 74fc84da6..be27590ba 100644
--- a/contrib/60-openocd.rules
+++ b/contrib/60-openocd.rules
@@ -55,6 +55,11 @@ ATTRS{idVendor}=="0403", ATTRS{idProduct}=="c141", MODE="660", GROUP="plugdev",
 # Amontec JTAGkey and JTAGkey-tiny
 ATTRS{idVendor}=="0403", ATTRS{idProduct}=="cff8", MODE="660", GROUP="plugdev", TAG+="uaccess"
 
+# Nuvoton NuLink
+ATTRS{idVendor}=="0416", ATTRS{idProduct}=="511b", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0416", ATTRS{idProduct}=="511c", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="0416", ATTRS{idProduct}=="511d", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
 # TI ICDI
 ATTRS{idVendor}=="0451", ATTRS{idProduct}=="c32a", MODE="660", GROUP="plugdev", TAG+="uaccess"
 
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 7a9b090d0..958cde49e 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -505,6 +505,12 @@ Texas Instruments has an adapter called @b{ICDI}.
 It is not to be confused with the FTDI based adapters that were originally fitted to their
 evaluation boards. This is the adapter fitted to the Stellaris LaunchPad.
 
+@section USB Nuvoton Nu-Link
+Nuvoton has an adapter called @b{Nu-Link}.
+It is available either as stand-alone dongle and embedded on development boards.
+It supports SWD, serial port bridge and mass storage for firmware update.
+Only Nu-Link v1 is currently supported.
+
 @section USB CMSIS-DAP based
 ARM has released a interface standard called CMSIS-DAP that simplifies connecting
 debuggers to ARM Cortex based targets @url{http://www.keil.com/support/man/docs/dapdebug/dapdebug_introduction.htm}.
@@ -3064,7 +3070,8 @@ This is a driver that supports multiple High Level Adapters.
 This type of adapter does not expose some of the lower level api's
 that OpenOCD would normally use to access the target.
 
-Currently supported adapters include the STMicroelectronics ST-LINK and TI ICDI.
+Currently supported adapters include the STMicroelectronics ST-LINK, TI ICDI
+and Nuvoton Nu-Link.
 ST-LINK firmware version >= V2.J21.S4 recommended due to issues with earlier
 versions of firmware where serial number is reset after first use.  Suggest
 using ST firmware update utility to upgrade ST-LINK firmware even if current
@@ -3078,7 +3085,7 @@ Currently Not Supported.
 Specifies the serial number of the adapter.
 @end deffn
 
-@deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi})
+@deffn {Config Command} {hla_layout} (@option{stlink}|@option{icdi}|@option{nulink})
 Specifies the adapter layout to use.
 @end deffn
 
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index 77d6fb2af..c860833b3 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -143,6 +143,9 @@ endif
 if HLADAPTER_ICDI
 DRIVERFILES += %D%/ti_icdi_usb.c
 endif
+if HLADAPTER_NULINK
+DRIVERFILES += %D%/nulink_usb.c
+endif
 if RSHIM
 DRIVERFILES += %D%/rshim.c
 endif
diff --git a/src/jtag/drivers/nulink_usb.c b/src/jtag/drivers/nulink_usb.c
new file mode 100644
index 000000000..3b0885b7a
--- /dev/null
+++ b/src/jtag/drivers/nulink_usb.c
@@ -0,0 +1,1104 @@
+/***************************************************************************
+ *   Copyright (C) 2016-2017 by Nuvoton                                    *
+ *   Zale Yu <cy...@nu...>                                            *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+/* project specific includes */
+#include <helper/binarybuffer.h>
+#include <jtag/interface.h>
+#include <jtag/hla/hla_layout.h>
+#include <jtag/hla/hla_transport.h>
+#include <jtag/hla/hla_interface.h>
+#include <target/target.h>
+
+#include <target/cortex_m.h>
+
+#include <hidapi.h>
+
+#define NULINK_READ_TIMEOUT  1000
+
+#define NULINK_HID_MAX_SIZE   (64)
+#define V6M_MAX_COMMAND_LENGTH (NULINK_HID_MAX_SIZE - 2)
+
+struct nulink_usb_handle_s {
+	hid_device *dev_handle;
+	uint16_t max_packet_size;
+	uint8_t usbcmdidx;
+	uint8_t cmdidx;
+	uint8_t cmdbuf[NULINK_HID_MAX_SIZE + 1];
+	uint8_t tempbuf[NULINK_HID_MAX_SIZE];
+	uint8_t databuf[NULINK_HID_MAX_SIZE];
+	uint32_t max_mem_packet;
+	uint16_t hardware_config; /* bit 0: 1:Nu-Link-Pro, 0:Nu-Link */
+};
+
+/* ICE Command */
+#define CMD_READ_REG				0xB5UL
+#define CMD_READ_RAM				0xB1UL
+#define CMD_WRITE_REG				0xB8UL
+#define CMD_WRITE_RAM				0xB9UL
+#define CMD_CHECK_ID				0xA3UL
+#define CMD_MCU_RESET				0xE2UL
+#define CMD_CHECK_MCU_STOP			0xD8UL
+#define CMD_MCU_STEP_RUN			0xD1UL
+#define CMD_MCU_STOP_RUN			0xD2UL
+#define CMD_MCU_FREE_RUN			0xD3UL
+#define CMD_SET_CONFIG				0xA2UL
+
+#define ARM_SRAM_BASE				0x20000000UL
+
+#define HARDWARE_CONFIG_NULINKPRO	1
+
+enum nulink_reset {
+	RESET_AUTO = 0,
+	RESET_HW = 1,
+	RESET_SYSRESETREQ = 2,
+	RESET_VECTRESET = 3,
+	RESET_FAST_RESCUE = 4, /* Rescue and erase the chip, need very fast speed */
+};
+
+enum nulink_connect {
+	CONNECT_NORMAL = 0,      /* Support all reset method */
+	CONNECT_PRE_RESET = 1,   /* Support all reset method */
+	CONNECT_UNDER_RESET = 2, /* Support all reset method */
+	CONNECT_NONE = 3,        /* Support RESET_HW, (RESET_AUTO = RESET_HW) */
+	CONNECT_DISCONNECT = 4,  /* Support RESET_NONE, (RESET_AUTO = RESET_NONE) */
+	CONNECT_ICP_MODE = 5     /* Support NUC505 ICP mode*/
+};
+
+static int nulink_usb_xfer_rw(void *handle, uint8_t *buf)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	assert(handle);
+
+	int ret = hid_write(h->dev_handle, h->cmdbuf, h->max_packet_size + 1);
+	if (ret < 0) {
+		LOG_ERROR("hid_write");
+		return ERROR_FAIL;
+	}
+
+	ret = hid_read_timeout(h->dev_handle, buf, h->max_packet_size, NULINK_READ_TIMEOUT);
+	if (ret < 0) {
+		LOG_ERROR("hid_read_timeout");
+		return ERROR_FAIL;
+	}
+	return ERROR_OK;
+}
+
+static int nulink_usb_xfer(void *handle, uint8_t *buf, int size)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	assert(handle);
+
+	int err = nulink_usb_xfer_rw(h, h->tempbuf);
+
+	memcpy(buf, h->tempbuf + 2, V6M_MAX_COMMAND_LENGTH);
+
+	return err;
+}
+
+static void nulink_usb_init_buffer(void *handle, uint32_t size)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	h->cmdidx = 0;
+
+	memset(h->cmdbuf, 0, h->max_packet_size + 1);
+	memset(h->tempbuf, 0, h->max_packet_size);
+	memset(h->databuf, 0, h->max_packet_size);
+
+	h->cmdbuf[0] = 0; /* report number */
+	h->cmdbuf[1] = ++h->usbcmdidx & 0x7F;
+	h->cmdbuf[2] = size;
+	h->cmdidx += 3;
+}
+
+static int nulink_usb_version(void *handle)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	LOG_DEBUG("nulink_usb_version");
+
+	assert(handle);
+
+	nulink_usb_init_buffer(handle, V6M_MAX_COMMAND_LENGTH);
+
+	memset(h->cmdbuf + h->cmdidx, 0xFF, V6M_MAX_COMMAND_LENGTH);
+	h->cmdbuf[h->cmdidx + 4] = 0xA1; /* host_rev_num: 6561 */;
+	h->cmdbuf[h->cmdidx + 5] = 0x19;
+
+	int res = nulink_usb_xfer(handle, h->databuf, 4 * 5);
+	if (res != ERROR_OK)
+		return res;
+
+	LOG_INFO("Nu-Link firmware_version %" PRIu32 ", product_id (0x%08" PRIx32 ")",
+			 le_to_h_u32(h->databuf),
+			 le_to_h_u32(h->databuf + 4 * 1));
+
+	const bool is_nulinkpro = !!(le_to_h_u32(h->databuf + 4 * 2) & 1);
+	if (is_nulinkpro) {
+		LOG_INFO("Adapter is Nu-Link-Pro, target_voltage_mv(%" PRIu16 "), usb_voltage_mv(%" PRIu16 ")",
+				 le_to_h_u16(h->databuf + 4 * 3 + 0),
+				 le_to_h_u16(h->databuf + 4 * 3 + 2));
+
+		h->hardware_config |= HARDWARE_CONFIG_NULINKPRO;
+	} else {
+		LOG_INFO("Adapter is Nu-Link");
+	}
+
+	return ERROR_OK;
+}
+
+static int nulink_usb_idcode(void *handle, uint32_t *idcode)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	LOG_DEBUG("nulink_usb_idcode");
+
+	assert(handle);
+
+	nulink_usb_init_buffer(handle, 4 * 1);
+	/* set command ID */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, CMD_CHECK_ID);
+	h->cmdidx += 4;
+
+	int res = nulink_usb_xfer(handle, h->databuf, 4 * 2);
+	if (res != ERROR_OK)
+		return res;
+
+	*idcode = le_to_h_u32(h->databuf + 4 * 1);
+
+	LOG_INFO("IDCODE: 0x%08" PRIX32, *idcode);
+
+	return ERROR_OK;
+}
+
+static int nulink_usb_write_debug_reg(void *handle, uint32_t addr, uint32_t val)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	LOG_DEBUG("nulink_usb_write_debug_reg 0x%08" PRIX32 "0x%08" PRIX32, addr, val);
+
+	nulink_usb_init_buffer(handle, 8 + 12 * 1);
+	/* set command ID */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, CMD_WRITE_RAM);
+	h->cmdidx += 4;
+	/* Count of registers */
+	h->cmdbuf[h->cmdidx] = 1;
+	h->cmdidx += 1;
+	/* Array of bool value (u8ReadOld) */
+	h->cmdbuf[h->cmdidx] = 0x00;
+	h->cmdidx += 1;
+	/* Array of bool value (u8Verify) */
+	h->cmdbuf[h->cmdidx] = 0x00;
+	h->cmdidx += 1;
+	/* ignore */
+	h->cmdbuf[h->cmdidx] = 0;
+	h->cmdidx += 1;
+	/* u32Addr */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, addr);
+	h->cmdidx += 4;
+	/* u32Data */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, val);
+	h->cmdidx += 4;
+	/* u32Mask */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, 0x00000000UL);
+	h->cmdidx += 4;
+
+	return nulink_usb_xfer(handle, h->databuf, 4 * 2);
+}
+
+static enum target_state nulink_usb_state(void *handle)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	assert(handle);
+
+	nulink_usb_init_buffer(handle, 4 * 1);
+	/* set command ID */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, CMD_CHECK_MCU_STOP);
+	h->cmdidx += 4;
+
+	int res = nulink_usb_xfer(handle, h->databuf, 4 * 4);
+	if (res != ERROR_OK)
+		return TARGET_UNKNOWN;
+
+	if (!le_to_h_u32(h->databuf + 4 * 2))
+		return TARGET_HALTED;
+	else
+		return TARGET_RUNNING;
+}
+
+static int nulink_usb_assert_srst(void *handle, int srst)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	LOG_DEBUG("nulink_usb_assert_srst");
+
+	assert(handle);
+
+	nulink_usb_init_buffer(handle, 4 * 4);
+	/* set command ID */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, CMD_MCU_RESET);
+	h->cmdidx += 4;
+	/* set reset type */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, RESET_SYSRESETREQ);
+	h->cmdidx += 4;
+	/* set connect type */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, CONNECT_NORMAL);
+	h->cmdidx += 4;
+	/* set extMode */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, 0);
+	h->cmdidx += 4;
+
+	return nulink_usb_xfer(handle, h->databuf, 4 * 4);
+}
+
+static int nulink_usb_reset(void *handle)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	LOG_DEBUG("nulink_usb_reset");
+
+	assert(handle);
+
+	nulink_usb_init_buffer(handle, 4 * 4);
+	/* set command ID */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, CMD_MCU_RESET);
+	h->cmdidx += 4;
+	/* set reset type */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, RESET_HW);
+	h->cmdidx += 4;
+	/* set connect type */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, CONNECT_NORMAL);
+	h->cmdidx += 4;
+	/* set extMode */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, 0);
+	h->cmdidx += 4;
+
+	return nulink_usb_xfer(handle, h->databuf, 4 * 4);
+}
+
+static int nulink_usb_run(void *handle)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	LOG_DEBUG("nulink_usb_run");
+
+	assert(handle);
+
+	nulink_usb_init_buffer(handle, 4 * 1);
+	/* set command ID */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, CMD_MCU_FREE_RUN);
+	h->cmdidx += 4;
+
+	return nulink_usb_xfer(handle, h->databuf, 4 * 4);
+}
+
+static int nulink_usb_halt(void *handle)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	LOG_DEBUG("nulink_usb_halt");
+
+	assert(handle);
+
+	nulink_usb_init_buffer(handle, 4 * 1);
+	/* set command ID */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, CMD_MCU_STOP_RUN);
+	h->cmdidx += 4;
+
+	int res = nulink_usb_xfer(handle, h->databuf, 4 * 4);
+
+	LOG_DEBUG("Nu-Link stop_pc 0x%08" PRIx32, le_to_h_u32(h->databuf + 4));
+
+	return res;
+}
+
+static int nulink_usb_step(void *handle)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	LOG_DEBUG("nulink_usb_step");
+
+	assert(handle);
+
+	nulink_usb_init_buffer(handle, 4 * 1);
+	/* set command ID */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, CMD_MCU_STEP_RUN);
+	h->cmdidx += 4;
+
+	int res = nulink_usb_xfer(handle, h->databuf, 4 * 4);
+
+	LOG_DEBUG("Nu-Link pc 0x%08" PRIx32, le_to_h_u32(h->databuf + 4));
+
+	return res;
+}
+
+static int nulink_usb_read_reg(void *handle, int num, uint32_t *val)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	assert(handle);
+
+	nulink_usb_init_buffer(handle, 8 + 12 * 1);
+	/* set command ID */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, CMD_WRITE_REG);
+	h->cmdidx += 4;
+	/* Count of registers */
+	h->cmdbuf[h->cmdidx] = 1;
+	h->cmdidx += 1;
+	/* Array of bool value (u8ReadOld) */
+	h->cmdbuf[h->cmdidx] = 0xFF;
+	h->cmdidx += 1;
+	/* Array of bool value (u8Verify) */
+	h->cmdbuf[h->cmdidx] = 0x00;
+	h->cmdidx += 1;
+	/* ignore */
+	h->cmdbuf[h->cmdidx] = 0;
+	h->cmdidx += 1;
+	/* u32Addr */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, num);
+	h->cmdidx += 4;
+	/* u32Data */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, 0);
+	h->cmdidx += 4;
+	/* u32Mask */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, 0xFFFFFFFFUL);
+	h->cmdidx += 4;
+
+	int res = nulink_usb_xfer(handle, h->databuf, 4 * 2);
+
+	*val = le_to_h_u32(h->databuf + 4 * 1);
+
+	return res;
+}
+
+static int nulink_usb_write_reg(void *handle, int num, uint32_t val)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	assert(handle);
+
+	nulink_usb_init_buffer(handle, 8 + 12 * 1);
+	/* set command ID */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, CMD_WRITE_REG);
+	h->cmdidx += 4;
+	/* Count of registers */
+	h->cmdbuf[h->cmdidx] = 1;
+	h->cmdidx += 1;
+	/* Array of bool value (u8ReadOld) */
+	h->cmdbuf[h->cmdidx] = 0x00;
+	h->cmdidx += 1;
+	/* Array of bool value (u8Verify) */
+	h->cmdbuf[h->cmdidx] = 0x00;
+	h->cmdidx += 1;
+	/* ignore */
+	h->cmdbuf[h->cmdidx] = 0;
+	h->cmdidx += 1;
+	/* u32Addr */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, num);
+	h->cmdidx += 4;
+	/* u32Data */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, val);
+	h->cmdidx += 4;
+	/* u32Mask */
+	h_u32_to_le(h->cmdbuf + h->cmdidx, 0x00000000UL);
+	h->cmdidx += 4;
+
+	return nulink_usb_xfer(handle, h->databuf, 4 * 2);
+}
+
+static int nulink_usb_read_mem8(void *handle, uint32_t addr, uint16_t len,
+		uint8_t *buffer)
+{
+	int res = ERROR_OK;
+	uint32_t offset = 0;
+	uint32_t bytes_remaining = 12;
+	struct nulink_usb_handle_s *h = handle;
+
+	LOG_DEBUG("nulink_usb_read_mem8: addr 0x%08" PRIx32 ", len %" PRId16, addr, len);
+
+	assert(handle);
+
+	/* check whether data is word aligned */
+	if (addr % 4) {
+		uint32_t aligned_addr = addr / 4;
+		aligned_addr = aligned_addr * 4;
+		offset = addr - aligned_addr;
+		LOG_DEBUG("nulink_usb_read_mem8: unaligned address addr 0x%08" PRIx32
+				"/aligned addr 0x%08" PRIx32 "offset %" PRIu32,
+				addr, aligned_addr, offset);
+
+		addr = aligned_addr;
+	}
+
+	while (len) {
+		unsigned int count;
+
+		if (len < bytes_remaining)
+			bytes_remaining = len;
+
+		if (len < 4)
+			count = 1;
+		else
+			count = 2;
+
+		nulink_usb_init_buffer(handle, 8 + 12 * count);
+		/* set command ID */
+		h_u32_to_le(h->cmdbuf + h->cmdidx, CMD_WRITE_RAM);
+		h->cmdidx += 4;
+		/* Count of registers */
+		h->cmdbuf[h->cmdidx] = count;
+		h->cmdidx += 1;
+		/* Array of bool value (u8ReadOld) */
+		h->cmdbuf[h->cmdidx] = 0xFF;
+		h->cmdidx += 1;
+		/* Array of bool value (u8Verify) */
+		h->cmdbuf[h->cmdidx] = 0x00;
+		h->cmdidx += 1;
+		/* ignore */
+		h->cmdbuf[h->cmdidx] = 0;
+		h->cmdidx += 1;
+
+		for (unsigned int i = 0; i < count; i++) {
+			/* u32Addr */
+			h_u32_to_le(h->cmdbuf + h->cmdidx, addr);
+			h->cmdidx += 4;
+			/* u32Data */
+			h_u32_to_le(h->cmdbuf + h->cmdidx, 0);
+			h->cmdidx += 4;
+			/* u32Mask */
+			h_u32_to_le(h->cmdbuf + h->cmdidx, 0xFFFFFFFFUL);
+			h->cmdidx += 4;
+			/* proceed to the next one  */
+			addr += 4;
+		}
+
+		res = nulink_usb_xfer(handle, h->databuf, 4 * count * 2);
+		if (res != ERROR_OK)
+			break;
+
+		/* fill in the output buffer */
+		for (unsigned int i = 0; i < count; i++) {
+			if (i == 0)
+				memcpy(buffer, h->databuf + 4 + offset, len);
+			else
+				memcpy(buffer + 2 * i, h->databuf + 4 * (2 * i + 1), len - 2);
+		}
+
+		if (len >= bytes_remaining)
+			len -= bytes_remaining;
+	}
+
+	return res;
+}
+
+static int nulink_usb_write_mem8(void *handle, uint32_t addr, uint16_t len,
+		const uint8_t *buffer)
+{
+	int res = ERROR_OK;
+	uint32_t offset = 0;
+	uint32_t bytes_remaining = 12;
+	struct nulink_usb_handle_s *h = handle;
+
+	LOG_DEBUG("nulink_usb_write_mem8: addr 0x%08" PRIx32 ", len %" PRIu16, addr, len);
+
+	assert(handle);
+
+	/* check whether data is word aligned */
+	if (addr % 4) {
+		uint32_t aligned_addr = addr / 4;
+		aligned_addr = aligned_addr * 4;
+		offset = addr - aligned_addr;
+		LOG_DEBUG("nulink_usb_write_mem8: address not aligned. addr(0x%08" PRIx32
+				")/aligned_addr(0x%08" PRIx32 ")/offset(%" PRIu32 ")",
+				addr, aligned_addr, offset);
+
+		addr = aligned_addr;
+	}
+
+	while (len) {
+		unsigned int count;
+
+		if (len < bytes_remaining)
+			bytes_remaining = len;
+
+		if (len < 4)
+			count = 1;
+		else
+			count = 2;
+
+		nulink_usb_init_buffer(handle, 8 + 12 * count);
+		/* set command ID */
+		h_u32_to_le(h->cmdbuf + h->cmdidx, CMD_WRITE_RAM);
+		h->cmdidx += 4;
+		/* Count of registers */
+		h->cmdbuf[h->cmdidx] = count;
+		h->cmdidx += 1;
+		/* Array of bool value (u8ReadOld) */
+		h->cmdbuf[h->cmdidx] = 0x00;
+		h->cmdidx += 1;
+		/* Array of bool value (u8Verify) */
+		h->cmdbuf[h->cmdidx] = 0x00;
+		h->cmdidx += 1;
+		/* ignore */
+		h->cmdbuf[h->cmdidx] = 0;
+		h->cmdidx += 1;
+
+		for (unsigned int i = 0; i < count; i++) {
+			/* u32Addr */
+			h_u32_to_le(h->cmdbuf + h->cmdidx, addr);
+			h->cmdidx += 4;
+			/* u32Data */
+			uint32_t u32buffer = buf_get_u32(buffer, 0, len * 8);
+			u32buffer = (u32buffer << offset * 8);
+			h_u32_to_le(h->cmdbuf + h->cmdidx, u32buffer);
+			h->cmdidx += 4;
+			/* u32Mask */
+			if (i == 0) {
+				if (offset == 0) {
+					if (len == 1) {
+						h_u32_to_le(h->cmdbuf + h->cmdidx, 0xFFFFFF00UL);
+						LOG_DEBUG("nulink_usb_write_mem8: count(%u), mask: 0xFFFFFF00", i);
+					} else {
+						h_u32_to_le(h->cmdbuf + h->cmdidx, 0xFFFF0000UL);
+						LOG_DEBUG("nulink_usb_write_mem8: count(%u), mask: 0xFFFF0000", i);
+					}
+				} else {
+					if (len == 1) {
+						h_u32_to_le(h->cmdbuf + h->cmdidx, 0xFF00FFFFUL);
+						LOG_DEBUG("nulink_usb_write_mem8: count(%u), mask: 0xFF00FFFF", i);
+
+					} else {
+						h_u32_to_le(h->cmdbuf + h->cmdidx, 0x0000FFFFUL);
+						LOG_DEBUG("nulink_usb_write_mem8: count(%u), mask: 0x0000FFFF", i);
+					}
+				}
+			} else {
+				if (len == 4) {
+					h_u32_to_le(h->cmdbuf + h->cmdidx, 0xFFFF0000UL);
+					LOG_DEBUG("nulink_usb_write_mem8: count(%u), mask: 0xFFFF0000", i);
+				} else {
+					h_u32_to_le(h->cmdbuf + h->cmdidx, 0x00000000UL);
+					LOG_DEBUG("nulink_usb_write_mem8: count(%u), mask: 0x00000000", i);
+				}
+			}
+			h->cmdidx += 4;
+
+			/* proceed to the next one */
+			addr += 4;
+			buffer += 4;
+		}
+
+		res = nulink_usb_xfer(handle, h->databuf, 4 * count * 2);
+		if (res != ERROR_OK)
+			break;
+
+		if (len >= bytes_remaining)
+			len -= bytes_remaining;
+	}
+
+	return res;
+}
+
+static int nulink_usb_read_mem32(void *handle, uint32_t addr, uint16_t len,
+		uint8_t *buffer)
+{
+	int res = ERROR_OK;
+	uint32_t bytes_remaining = 12;
+	struct nulink_usb_handle_s *h = handle;
+
+	assert(handle);
+
+	/* data must be a multiple of 4 and word aligned */
+	if (len % 4 || addr % 4) {
+		LOG_ERROR("Invalid data alignment");
+		return ERROR_TARGET_UNALIGNED_ACCESS;
+	}
+
+	while (len) {
+		if (len < bytes_remaining)
+			bytes_remaining = len;
+
+		unsigned int count = bytes_remaining / 4;
+
+		nulink_usb_init_buffer(handle, 8 + 12 * count);
+		/* set command ID */
+		h_u32_to_le(h->cmdbuf + h->cmdidx, CMD_WRITE_RAM);
+		h->cmdidx += 4;
+		/* Count of registers */
+		h->cmdbuf[h->cmdidx] = count;
+		h->cmdidx += 1;
+		/* Array of bool value (u8ReadOld) */
+		h->cmdbuf[h->cmdidx] = 0xFF;
+		h->cmdidx += 1;
+		/* Array of bool value (u8Verify) */
+		h->cmdbuf[h->cmdidx] = 0x00;
+		h->cmdidx += 1;
+		/* ignore */
+		h->cmdbuf[h->cmdidx] = 0;
+		h->cmdidx += 1;
+
+		for (unsigned int i = 0; i < count; i++) {
+			/* u32Addr */
+			h_u32_to_le(h->cmdbuf + h->cmdidx, addr);
+			h->cmdidx += 4;
+			/* u32Data */
+			h_u32_to_le(h->cmdbuf + h->cmdidx, 0);
+			h->cmdidx += 4;
+			/* u32Mask */
+			h_u32_to_le(h->cmdbuf + h->cmdidx, 0xFFFFFFFFUL);
+			h->cmdidx += 4;
+			/* proceed to the next one  */
+			addr += 4;
+		}
+
+		res = nulink_usb_xfer(handle, h->databuf, 4 * count * 2);
+
+		/* fill in the output buffer */
+		for (unsigned int i = 0; i < count; i++) {
+			memcpy(buffer, h->databuf + 4 * (2 * i + 1), 4);
+			buffer += 4;
+		}
+
+		if (len >= bytes_remaining)
+			len -= bytes_remaining;
+		else
+			len = 0;
+	}
+
+	return res;
+}
+
+static int nulink_usb_write_mem32(void *handle, uint32_t addr, uint16_t len,
+		const uint8_t *buffer)
+{
+	int res = ERROR_OK;
+	uint32_t bytes_remaining = 12;
+	struct nulink_usb_handle_s *h = handle;
+
+	assert(handle);
+
+	/* data must be a multiple of 4 and word aligned */
+	if (len % 4 || addr % 4) {
+		LOG_ERROR("Invalid data alignment");
+		return ERROR_TARGET_UNALIGNED_ACCESS;
+	}
+
+	while (len) {
+		if (len < bytes_remaining)
+			bytes_remaining = len;
+
+		unsigned int count = bytes_remaining / 4;
+
+		nulink_usb_init_buffer(handle, 8 + 12 * count);
+		/* set command ID */
+		h_u32_to_le(h->cmdbuf + h->cmdidx, CMD_WRITE_RAM);
+		h->cmdidx += 4;
+		/* Count of registers */
+		h->cmdbuf[h->cmdidx] = count;
+		h->cmdidx += 1;
+		/* Array of bool value (u8ReadOld) */
+		h->cmdbuf[h->cmdidx] = 0x00;
+		h->cmdidx += 1;
+		/* Array of bool value (u8Verify) */
+		h->cmdbuf[h->cmdidx] = 0x00;
+		h->cmdidx += 1;
+		/* ignore */
+		h->cmdbuf[h->cmdidx] = 0;
+		h->cmdidx += 1;
+
+		for (unsigned int i = 0; i < count; i++) {
+			/* u32Addr */
+			h_u32_to_le(h->cmdbuf + h->cmdidx, addr);
+			h->cmdidx += 4;
+			/* u32Data */
+			uint32_t u32buffer = buf_get_u32(buffer, 0, 32);
+			h_u32_to_le(h->cmdbuf + h->cmdidx, u32buffer);
+			h->cmdidx += 4;
+			/* u32Mask */
+			h_u32_to_le(h->cmdbuf + h->cmdidx, 0x00000000);
+			h->cmdidx += 4;
+
+			/* proceed to the next one */
+			addr += 4;
+			buffer += 4;
+		}
+
+		res = nulink_usb_xfer(handle, h->databuf, 4 * count * 2);
+
+		if (len >= bytes_remaining)
+			len -= bytes_remaining;
+		else
+			len = 0;
+	}
+
+	return res;
+}
+
+static uint32_t nulink_max_block_size(uint32_t tar_autoincr_block, uint32_t address)
+{
+	uint32_t max_tar_block = (tar_autoincr_block - ((tar_autoincr_block - 1) & address));
+
+	if (max_tar_block == 0)
+		max_tar_block = 4;
+
+	return max_tar_block;
+}
+
+static int nulink_usb_read_mem(void *handle, uint32_t addr, uint32_t size,
+		uint32_t count, uint8_t *buffer)
+{
+	int retval = ERROR_OK;
+	struct nulink_usb_handle_s *h = handle;
+
+	/* calculate byte count */
+	count *= size;
+
+	while (count) {
+		uint32_t bytes_remaining = nulink_max_block_size(h->max_mem_packet, addr);
+
+		if (count < bytes_remaining)
+			bytes_remaining = count;
+
+		if (bytes_remaining >= 4)
+			size = 4;
+
+		/* the nulink only supports 8/32bit memory read/writes
+		 * honour 32bit, all others will be handled as 8bit access */
+		if (size == 4) {
+			/* When in jtag mode the nulink uses the auto-increment functinality.
+			 * However it expects us to pass the data correctly, this includes
+			 * alignment and any page boundaries. We already do this as part of the
+			 * adi_v5 implementation, but the nulink is a hla adapter and so this
+			 * needs implementiong manually.
+			 * currently this only affects jtag mode, they do single
+			 * access in SWD mode - but this may change and so we do it for both modes */
+
+			/* we first need to check for any unaligned bytes */
+			if (addr % 4) {
+				uint32_t head_bytes = 4 - (addr % 4);
+				retval = nulink_usb_read_mem8(handle, addr, head_bytes, buffer);
+				if (retval != ERROR_OK)
+					return retval;
+				buffer += head_bytes;
+				addr += head_bytes;
+				count -= head_bytes;
+				bytes_remaining -= head_bytes;
+			}
+
+			if (bytes_remaining % 4)
+				retval = nulink_usb_read_mem(handle, addr, 1, bytes_remaining, buffer);
+			else
+				retval = nulink_usb_read_mem32(handle, addr, bytes_remaining, buffer);
+		} else {
+			retval = nulink_usb_read_mem8(handle, addr, bytes_remaining, buffer);
+		}
+
+		if (retval != ERROR_OK)
+			return retval;
+
+		buffer += bytes_remaining;
+		addr += bytes_remaining;
+		count -= bytes_remaining;
+	}
+
+	return retval;
+}
+
+static int nulink_usb_write_mem(void *handle, uint32_t addr, uint32_t size,
+		uint32_t count, const uint8_t *buffer)
+{
+	int retval = ERROR_OK;
+	struct nulink_usb_handle_s *h = handle;
+
+	if (addr < ARM_SRAM_BASE) {
+		LOG_DEBUG("nulink_usb_write_mem: address below ARM_SRAM_BASE, not supported.\n");
+		return retval;
+	}
+
+	/* calculate byte count */
+	count *= size;
+
+	while (count) {
+		uint32_t bytes_remaining = nulink_max_block_size(h->max_mem_packet, addr);
+
+		if (count < bytes_remaining)
+			bytes_remaining = count;
+
+		if (bytes_remaining >= 4)
+			size = 4;
+
+		/* the nulink only supports 8/32bit memory read/writes
+		 * honour 32bit, all others will be handled as 8bit access */
+		if (size == 4) {
+			/* When in jtag mode the nulink uses the auto-increment functinality.
+			 * However it expects us to pass the data correctly, this includes
+			 * alignment and any page boundaries. We already do this as part of the
+			 * adi_v5 implementation, but the nulink is a hla adapter and so this
+			 * needs implementiong manually.
+			 * currently this only affects jtag mode, do single
+			 * access in SWD mode - but this may change and so we do it for both modes */
+
+			/* we first need to check for any unaligned bytes */
+			if (addr % 4) {
+				uint32_t head_bytes = 4 - (addr % 4);
+				retval = nulink_usb_write_mem8(handle, addr, head_bytes, buffer);
+				if (retval != ERROR_OK)
+					return retval;
+				buffer += head_bytes;
+				addr += head_bytes;
+				count -= head_bytes;
+				bytes_remaining -= head_bytes;
+			}
+
+			if (bytes_remaining % 4)
+				retval = nulink_usb_write_mem(handle, addr, 1, bytes_remaining, buffer);
+			else
+				retval = nulink_usb_write_mem32(handle, addr, bytes_remaining, buffer);
+
+		} else {
+			retval = nulink_usb_write_mem8(handle, addr, bytes_remaining, buffer);
+		}
+
+		if (retval != ERROR_OK)
+			return retval;
+
+		buffer += bytes_remaining;
+		addr += bytes_remaining;
+		count -= bytes_remaining;
+	}
+
+	return retval;
+}
+
+static int nulink_usb_override_target(const char *targetname)
+{
+	LOG_DEBUG("nulink_usb_override_target");
+
+	return !strcmp(targetname, "cortex_m");
+}
+
+static int nulink_speed(void *handle, int khz, bool query)
+{
+	struct nulink_usb_handle_s *h = handle;
+	unsigned long max_ice_clock = khz;
+
+	LOG_DEBUG("nulink_speed: query %s", query ? "yes" : "no");
+
+	if (max_ice_clock > 12000)
+		max_ice_clock = 12000;
+	else if ((max_ice_clock == 3 * 512) || (max_ice_clock == 1500))
+		max_ice_clock = 1500;
+	else if (max_ice_clock >= 1000)
+		max_ice_clock = max_ice_clock / 1000 * 1000;
+	else
+		max_ice_clock = max_ice_clock / 100 * 100;
+
+	LOG_DEBUG("Nu-Link nulink_speed: %lu", max_ice_clock);
+
+	if (!query) {
+		nulink_usb_init_buffer(handle, 4 * 6);
+		/* set command ID */
+		h_u32_to_le(h->cmdbuf + h->cmdidx, CMD_SET_CONFIG);
+		h->cmdidx += 4;
+		/* set max SWD clock */
+		h_u32_to_le(h->cmdbuf + h->cmdidx, max_ice_clock);
+		h->cmdidx += 4;
+		/* chip type: NUC_CHIP_TYPE_GENERAL_V6M */
+		h_u32_to_le(h->cmdbuf + h->cmdidx, 0);
+		h->cmdidx += 4;
+		/* IO voltage */
+		h_u32_to_le(h->cmdbuf + h->cmdidx, 5000);
+		h->cmdidx += 4;
+		/* If supply voltage to target or not */
+		h_u32_to_le(h->cmdbuf + h->cmdidx, 0);
+		h->cmdidx += 4;
+		/* USB_FUNC_E: USB_FUNC_HID_BULK */
+		h_u32_to_le(h->cmdbuf + h->cmdidx, 2);
+		h->cmdidx += 4;
+
+		nulink_usb_xfer(handle, h->databuf, 4 * 3);
+
+		LOG_DEBUG("nulink_speed: h->hardware_config(%" PRId16 ")", h->hardware_config);
+		if (h->hardware_config & HARDWARE_CONFIG_NULINKPRO)
+			LOG_INFO("Nu-Link target_voltage_mv[0](%04" PRIx16 "), target_voltage_mv[1](%04" PRIx16
+				"), target_voltage_mv[2](%04" PRIx16 "), if_target_power_supplied(%d)",
+				le_to_h_u16(h->databuf + 4 * 1 + 0),
+				le_to_h_u16(h->databuf + 4 * 1 + 2),
+				le_to_h_u16(h->databuf + 4 * 2 + 0),
+				le_to_h_u16(h->databuf + 4 * 2 + 2) & 1);
+	}
+
+	return max_ice_clock;
+}
+
+static int nulink_usb_close(void *handle)
+{
+	struct nulink_usb_handle_s *h = handle;
+
+	LOG_DEBUG("nulink_usb_close");
+
+	if (h && h->dev_handle)
+		hid_close(h->dev_handle);
+
+	free(h);
+
+	hid_exit();
+
+	return ERROR_OK;
+}
+
+static int nulink_usb_open(struct hl_interface_param_s *param, void **fd)
+{
+	struct hid_device_info *devs, *cur_dev;
+	uint16_t target_vid = 0;
+	uint16_t target_pid = 0;
+	wchar_t *target_serial = NULL;
+
+	LOG_DEBUG("nulink_usb_open");
+
+	if (param->transport != HL_TRANSPORT_SWD)
+		return TARGET_UNKNOWN;
+
+	if (!param->vid[0] && !param->pid[0]) {
+		LOG_ERROR("Missing vid/pid");
+		return ERROR_FAIL;
+	}
+
+	if (hid_init() != 0) {
+		LOG_ERROR("unable to open HIDAPI");
+		return ERROR_FAIL;
+	}
+
+	struct nulink_usb_handle_s *h = calloc(1, sizeof(*h));
+	if (!h) {
+		LOG_ERROR("Out of memory");
+		goto error_open;
+	}
+
+	if (param->serial) {
+		size_t len = mbstowcs(NULL, param->serial, 0);
+
+		target_serial = calloc(len + 1, sizeof(wchar_t));
+		if (!target_serial) {
+			LOG_ERROR("Out of memory");
+			goto error_open;
+		}
+
+		if (mbstowcs(target_serial, param->serial, len + 1) == (size_t)(-1)) {
+			LOG_WARNING("unable to convert serial");
+			free(target_serial);
+			target_serial = NULL;
+		}
+	}
+
+	devs = hid_enumerate(0, 0);
+	cur_dev = devs;
+	while (cur_dev) {
+		bool found = false;
+
+		for (unsigned int i = 0; param->vid[i] || param->pid[i]; i++) {
+			if (param->vid[i] == cur_dev->vendor_id && param->pid[i] == cur_dev->product_id) {
+				found = true;
+				break;
+			}
+		}
+
+		if (found) {
+			if (!target_serial)
+				break;
+			if (cur_dev->serial_number && wcscmp(target_serial, cur_dev->serial_number) == 0)
+				break;
+		}
+
+		cur_dev = cur_dev->next;
+	}
+	if (cur_dev) {
+		target_vid = cur_dev->vendor_id;
+		target_pid = cur_dev->product_id;
+	}
+
+	hid_free_enumeration(devs);
+
+	if (target_vid == 0 && target_pid == 0) {
+		LOG_ERROR("unable to find Nu-Link");
+		goto error_open;
+	}
+
+	hid_device *dev = hid_open(target_vid, target_pid, target_serial);
+	if (!dev) {
+		LOG_ERROR("unable to open Nu-Link device 0x%" PRIx16 ":0x%" PRIx16, target_vid, target_pid);
+		goto error_open;
+	}
+
+	h->dev_handle = dev;
+	h->usbcmdidx = 0;
+	h->hardware_config = 0;
+	h->max_packet_size = NULINK_HID_MAX_SIZE;
+
+	/* get the device version */
+	int err = nulink_usb_version(h);
+	if (err != ERROR_OK)
+		goto error_open;
+
+	/* SWD clock rate : 1MHz */
+	nulink_speed(h, 1000, false);
+
+	/* get cpuid, so we can determine the max page size
+	 * start with a safe default */
+	h->max_mem_packet = (1 << 10);
+
+	LOG_DEBUG("nulink_usb_open: we manually perform nulink_usb_reset");
+	nulink_usb_reset(h);
+
+	*fd = h;
+
+	free(target_serial);
+	return ERROR_OK;
+
+error_open:
+	nulink_usb_close(h);
+	free(target_serial);
+
+	return ERROR_FAIL;
+}
+
+struct hl_layout_api_s nulink_usb_layout_api = {
+	.open = nulink_usb_open,
+	.close = nulink_usb_close,
+	.idcode = nulink_usb_idcode,
+	.state = nulink_usb_state,
+	.reset = nulink_usb_reset,
+	.assert_srst = nulink_usb_assert_srst,
+	.run = nulink_usb_run,
+	.halt = nulink_usb_halt,
+	.step = nulink_usb_step,
+	.read_reg = nulink_usb_read_reg,
+	.write_reg = nulink_usb_write_reg,
+	.read_mem = nulink_usb_read_mem,
+	.write_mem = nulink_usb_write_mem,
+	.write_debug_reg = nulink_usb_write_debug_reg,
+	.override_target = nulink_usb_override_target,
+	.speed = nulink_speed,
+};
diff --git a/src/jtag/hla/hla_layout.c b/src/jtag/hla/hla_layout.c
index 686e6f5b2..cf51a6713 100644
--- a/src/jtag/hla/hla_layout.c
+++ b/src/jtag/hla/hla_layout.c
@@ -72,6 +72,14 @@ static const struct hl_layout hl_layouts[] = {
 	 .close = hl_layout_close,
 	 .api = &icdi_usb_layout_api,
 	},
+#endif
+#if BUILD_HLADAPTER_NULINK
+	{
+	 .name = "nulink",
+	 .open = hl_layout_open,
+	 .close = hl_layout_close,
+	 .api = &nulink_usb_layout_api,
+	},
 #endif
 	{.name = NULL, /* END OF TABLE */ },
 };
diff --git a/src/jtag/hla/hla_layout.h b/src/jtag/hla/hla_layout.h
index 68052952f..e0bbd0fed 100644
--- a/src/jtag/hla/hla_layout.h
+++ b/src/jtag/hla/hla_layout.h
@@ -31,6 +31,7 @@ struct hl_interface_param_s;
 /** */
 extern struct hl_layout_api_s stlink_usb_layout_api;
 extern struct hl_layout_api_s icdi_usb_layout_api;
+extern struct hl_layout_api_s nulink_usb_layout_api;
 
 /** */
 struct hl_layout_api_s {
diff --git a/tcl/interface/nulink.cfg b/tcl/interface/nulink.cfg
new file mode 100644
index 000000000..08c8216c6
--- /dev/null
+++ b/tcl/interface/nulink.cfg
@@ -0,0 +1,11 @@
+#
+# Nuvoton Nu-Link in-circuit debugger/programmer
+#
+
+adapter driver hla
+hla_layout nulink
+hla_device_desc "Nu-Link"
+hla_vid_pid 0x0416 0x511b 0x0416 0x511c 0x0416 0x511d
+
+# Only swd is supported
+transport select hla_swd

-----------------------------------------------------------------------

Summary of changes:
 configure.ac                  |    6 +-
 contrib/60-openocd.rules      |    5 +
 doc/openocd.texi              |   11 +-
 src/jtag/drivers/Makefile.am  |    3 +
 src/jtag/drivers/nulink_usb.c | 1104 +++++++++++++++++++++++++++++++++++++++++
 src/jtag/hla/hla_layout.c     |    8 +
 src/jtag/hla/hla_layout.h     |    1 +
 tcl/interface/nulink.cfg      |   11 +
 8 files changed, 1145 insertions(+), 4 deletions(-)
 create mode 100644 src/jtag/drivers/nulink_usb.c
 create mode 100644 tcl/interface/nulink.cfg


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1365-g583a65644

From: OpenOCD-Gerrit <ope...@us...> - 2020-07-30 11:27:18

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  583a65644b5b69f5c197322b09a577b3c90ca781 (commit)
      from  fb739651c79722b4bc57c31b3d26bb48840b9118 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 583a65644b5b69f5c197322b09a577b3c90ca781
Author: R. Diez <rdi...@ya...>
Date:   Thu Apr 30 16:31:26 2020 +0200

    Make autotools warnings visible.
    
    Change-Id: Ibcdac7100faca7a66d9b3440431e74a8a8c5f042
    Signed-off-by: R. Diez <rdi...@ya...>
    Reviewed-on: http://openocd.zylin.com/5639
    Tested-by: jenkins
    Reviewed-by: Andreas Fritiofson <and...@gm...>

diff --git a/bootstrap b/bootstrap
index ad5e7bdd2..e81ba4d02 100755
--- a/bootstrap
+++ b/bootstrap
@@ -24,11 +24,12 @@ fi
 # bootstrap the autotools
 (
 set -x
-aclocal
+aclocal --warnings=all
+# Apparently, not all versions of libtoolize support option --warnings=all .
 ${libtoolize} --automake --copy
-autoconf
-autoheader
-automake --gnu --add-missing --copy
+autoconf --warnings=all
+autoheader --warnings=all
+automake --warnings=all --gnu --add-missing --copy
 )
 
 if [ -n "$SKIP_SUBMODULE" ]; then

-----------------------------------------------------------------------

Summary of changes:
 bootstrap | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)


hooks/post-receive
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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1364-gfb739651c

From: OpenOCD-Gerrit <ope...@us...> - 2020-07-30 11:17:14

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- Log -----------------------------------------------------------------
commit fb739651c79722b4bc57c31b3d26bb48840b9118
Author: Michal Potrzebicz <mi...@el...>
Date:   Fri Jul 10 22:13:15 2020 +0100

    cmsis_dap_usb: Support for Microchip's nEDBG CMSIS-DAP interface
    
    This commit fixes support for the nEDBG CMSIS-DAP interface
    which is used ie. on the Curiosity Nano SAMD21 board.
    nEDBG, similarily to mEDBG, does not support 512 byte HID packets.
    This patch adds its USB PID to the exclusion list to make sure that
    we stick with the default 64 bytes.
    
    Change-Id: I9010b0cf77c0b1347269a759b5d16ee5155abb16
    Signed-off-by: Michal Potrzebicz <mi...@el...>
    Reviewed-on: http://openocd.zylin.com/5756
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/jtag/drivers/cmsis_dap_usb.c b/src/jtag/drivers/cmsis_dap_usb.c
index efd039af6..6d55392d5 100644
--- a/src/jtag/drivers/cmsis_dap_usb.c
+++ b/src/jtag/drivers/cmsis_dap_usb.c
@@ -333,7 +333,7 @@ static int cmsis_dap_usb_open(void)
 	 * board */
 	/* TODO: HID report descriptor should be parsed instead of
 	 * hardcoding a match by VID */
-	if (target_vid == 0x03eb && target_pid != 0x2145)
+	if (target_vid == 0x03eb && target_pid != 0x2145 && target_pid != 0x2175)
 		packet_size = 512 + 1;
 
 	cmsis_dap_handle->packet_buffer = malloc(packet_size);

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/cmsis_dap_usb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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- Log -----------------------------------------------------------------
commit 480ba8ca88e3f12bb60498b35de5fc4b74d0511d
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jul 12 20:25:00 2020 +0200

    target: fix minor typos and duplicated words
    
    Change-Id: I8deb0017dc66a243e3dd51e285aa086db500decd
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5766
    Tested-by: jenkins

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 01d0e9462..e6b1cc007 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -2497,7 +2497,7 @@ static int aarch64_jim_configure(struct target *target, Jim_GetOptInfo *goi)
 	 * Call adiv5_jim_configure() to parse the common DAP options
 	 * It will return JIM_CONTINUE if it didn't find any known
 	 * options, JIM_OK if it correctly parsed the topmost option
-	 * and JIM_ERR if an error occured during parameter evaluation.
+	 * and JIM_ERR if an error occurred during parameter evaluation.
 	 * For JIM_CONTINUE, we check our own params.
 	 */
 	e = adiv5_jim_configure(target, goi);
diff --git a/src/target/arc.c b/src/target/arc.c
index db338031f..ba8903d48 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -33,7 +33,7 @@
  * unexisting register is safe RAZ, rather then an error.
  * Note, core registers cannot be BCR.
  *
- * In arc/cpu/ tcl files all regiters are defined as core, non-BCR aux
+ * In arc/cpu/ tcl files all registers are defined as core, non-BCR aux
  * and BCR aux, in "add-reg" command they are passed to three lists
  * respectively:  core_reg_descriptions, aux_reg_descriptions,
  * bcr_reg_descriptions.
@@ -286,7 +286,7 @@ const struct reg_arch_type arc_reg_type = {
 	.set = arc_set_register,
 };
 
-/* GDB register groups. For now we suport only general and "empty" */
+/* GDB register groups. For now we support only general and "empty" */
 static const char * const reg_group_general = "general";
 static const char * const reg_group_other = "";
 
@@ -548,7 +548,7 @@ int arc_reg_get_field(struct target *target, const char *reg_name,
 	struct reg *reg = arc_reg_get_by_name(target->reg_cache, reg_name, true);
 
 	if (!reg) {
-		LOG_ERROR("Requested register `%s' doens't exist.", reg_name);
+		LOG_ERROR("Requested register `%s' doesn't exist.", reg_name);
 		return ERROR_ARC_REGISTER_NOT_FOUND;
 	}
 
@@ -575,7 +575,7 @@ int arc_reg_get_field(struct target *target, const char *reg_name,
 	if (!reg->valid)
 		CHECK_RETVAL(reg->type->get(reg));
 
-	/* First do endiannes-safe read of register value
+	/* First do endianness-safe read of register value
 	 * then convert it to binary buffer for further
 	 * field extraction */
 
@@ -1396,7 +1396,7 @@ static int arc_target_create(struct target *target, Jim_Interp *interp)
  * Write 4-byte instruction to memory. This is like target_write_u32, however
  * in case of little endian ARC instructions are in middle endian format, not
  * little endian, so different type of conversion should be done.
- * Middle endinan: instruction "aabbccdd", stored as "bbaaddcc"
+ * Middle endian: instruction "aabbccdd", stored as "bbaaddcc"
  */
 int arc_write_instruction_u32(struct target *target, uint32_t address,
 	uint32_t instr)
@@ -1800,7 +1800,7 @@ int arc_remove_auxreg_actionpoint(struct target *target, uint32_t auxreg_addr)
 	return retval;
 }
 
-/* Helper function which swiches core to single_step mode by
+/* Helper function which switches core to single_step mode by
  * doing aux r/w operations.  */
 int arc_config_step(struct target *target, int enable_step)
 {
@@ -2081,7 +2081,7 @@ struct target_type arcv2_target = {
 
 	.arch_state = arc_arch_state,
 
-	/* TODO That seems like something similiar to metaware hostlink, so perhaps
+	/* TODO That seems like something similar to metaware hostlink, so perhaps
 	 * we can exploit this in the future. */
 	.target_request_data = NULL,
 
diff --git a/src/target/arc_cmd.c b/src/target/arc_cmd.c
index a1d5a0936..36babc768 100644
--- a/src/target/arc_cmd.c
+++ b/src/target/arc_cmd.c
@@ -86,7 +86,7 @@ static int jim_arc_read_reg_type_field(Jim_GetOptInfo *goi, const char **field_n
 		int e = JIM_OK;
 		if ((type == CFG_ADD_REG_TYPE_STRUCT && goi->argc < 3) ||
 		 (type == CFG_ADD_REG_TYPE_FLAG && goi->argc < 2)) {
-			Jim_SetResultFormatted(goi->interp, "Not enough argmunets after -flag/-bitfield");
+			Jim_SetResultFormatted(goi->interp, "Not enough arguments after -flag/-bitfield");
 			return JIM_ERR;
 		}
 
@@ -101,7 +101,7 @@ static int jim_arc_read_reg_type_field(Jim_GetOptInfo *goi, const char **field_n
 
 		end_pos = start_pos;
 
-		/* Check if any argnuments remain,
+		/* Check if any arguments remain,
 		 * set bitfields[cur_field].end if flag is multibit */
 		if (goi->argc > 0)
 			/* Check current argv[0], if it is equal to "-flag",
@@ -143,9 +143,9 @@ static int jim_arc_add_reg_type_flags(Jim_Interp *interp, int argc,
 
 	int e = JIM_OK;
 
-	/* Check if the amount of argnuments is not zero */
+	/* Check if the amount of arguments is not zero */
 	if (goi.argc <= 0) {
-		Jim_SetResultFormatted(goi.interp, "The command has no argnuments");
+		Jim_SetResultFormatted(goi.interp, "The command has no arguments");
 		return JIM_ERR;
 	}
 
@@ -154,7 +154,7 @@ static int jim_arc_add_reg_type_flags(Jim_Interp *interp, int argc,
 	unsigned int fields_sz = (goi.argc - 2) / 3;
 	unsigned int cur_field = 0;
 
-	/* Tha maximum amount of bitfilds is 32 */
+	/* The maximum amount of bitfields is 32 */
 	if (fields_sz > 32) {
 		Jim_SetResultFormatted(goi.interp, "The amount of bitfields exceed 32");
 		return JIM_ERR;
@@ -509,9 +509,9 @@ static int jim_arc_add_reg_type_struct(Jim_Interp *interp, int argc,
 
 	int e = JIM_OK;
 
-	/* Check if the amount of argnuments is not zero */
+	/* Check if the amount of arguments is not zero */
 	if (goi.argc <= 0) {
-		Jim_SetResultFormatted(goi.interp, "The command has no argnuments");
+		Jim_SetResultFormatted(goi.interp, "The command has no arguments");
 		return JIM_ERR;
 	}
 
@@ -520,7 +520,7 @@ static int jim_arc_add_reg_type_struct(Jim_Interp *interp, int argc,
 	unsigned int fields_sz = (goi.argc - 2) / 4;
 	unsigned int cur_field = 0;
 
-	/* Tha maximum amount of bitfilds is 32 */
+	/* The maximum amount of bitfields is 32 */
 	if (fields_sz > 32) {
 			Jim_SetResultFormatted(goi.interp, "The amount of bitfields exceed 32");
 			return JIM_ERR;
@@ -672,19 +672,19 @@ static int jim_arc_add_reg(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
 	}
 
 	/* There is no architecture number that we could treat as invalid, so
-	 * separate variable requried to ensure that arch num has been set. */
+	 * separate variable required to ensure that arch num has been set. */
 	bool arch_num_set = false;
 	const char *type_name = "int"; /* Default type */
 	int type_name_len = strlen(type_name);
 	int e = ERROR_OK;
 
 	/* At least we need to specify 4 parameters: name, number and gdb_feature,
-	 * which means there should be 6 arguments. Also there can be additional paramters
+	 * which means there should be 6 arguments. Also there can be additional parameters
 	 * "-type <type>", "-g" and  "-core" or "-bcr" which makes maximum 10 parameters. */
 	if (goi.argc < 6 || goi.argc > 10) {
 		free_reg_desc(reg);
 		Jim_SetResultFormatted(goi.interp,
-			"Should be at least 6 argnuments and not greater than 10: "
+			"Should be at least 6 arguments and not greater than 10: "
 			" -name <name> -num <num> -feature <gdb_feature> "
 			" [-type <type_name>] [-core|-bcr] [-g].");
 		return JIM_ERR;
@@ -1035,7 +1035,7 @@ static const struct command_registration arc_core_command_handlers[] = {
 		.usage = "arc add-reg -name <string> -num <int> -feature <string> [-gdbnum <int>] "
 			"[-core|-bcr] [-type <type_name>] [-g]",
 		.help = "Add new register. Name, architectural number and feature name "
-			"are requried options. GDB regnum will default to previous register "
+			"are required options. GDB regnum will default to previous register "
 			"(gdbnum + 1) and shouldn't be specified in most cases. Type "
 			"defaults to default GDB 'int'.",
 	},
diff --git a/src/target/arc_jtag.c b/src/target/arc_jtag.c
index e85167a6f..fd77b37f2 100644
--- a/src/target/arc_jtag.c
+++ b/src/target/arc_jtag.c
@@ -158,7 +158,7 @@ static void arc_jtag_enque_status_read(struct arc_jtag * const jtag_info,
 	assert(jtag_info->tap);
 	assert(buffer);
 
-  /* first writin code(0x8) of jtag status register in IR */
+	/* first writing code(0x8) of jtag status register in IR */
 	arc_jtag_enque_write_ir(jtag_info, ARC_JTAG_STATUS_REG);
 	/* Now reading dr performs jtag status register read */
 	arc_jtag_enque_read_dr(jtag_info, buffer, TAP_IDLE);
@@ -223,7 +223,7 @@ static void arc_jtag_enque_register_rw(struct arc_jtag *jtag_info, uint32_t *add
 		else
 			arc_jtag_enque_read_dr(jtag_info, read_buffer + i * 4, TAP_IDLE);
 	}
-	/* To prevent pollution of next regiter due to optimization it is necessary *
+	/* To prevent pollution of next register due to optimization it is necessary *
 	 * to reset transaction */
 	arc_jtag_enque_reset_transaction(jtag_info);
 }
diff --git a/src/target/arc_mem.c b/src/target/arc_mem.c
index 866c71fc2..96762690f 100644
--- a/src/target/arc_mem.c
+++ b/src/target/arc_mem.c
@@ -75,8 +75,8 @@ static int arc_mem_write_block16(struct target *target, uint32_t addr,
 	/* We will read data from memory, so we need to flush the cache. */
 	CHECK_RETVAL(arc_cache_flush(target));
 
-	/* non-word writes are less common, than 4-byte writes, so I suppose we can
-	 * allowe ourselves to write this in a cycle, instead of calling arc_jtag
+	/* non-word writes are less common than 4-byte writes, so I suppose we can
+	 * allow ourselves to write this in a cycle, instead of calling arc_jtag
 	 * with count > 1. */
 	for (i = 0; i < count; i++) {
 		/* We can read only word at word-aligned address. Also *jtag_read_memory
@@ -130,8 +130,8 @@ static int arc_mem_write_block8(struct target *target, uint32_t addr,
 	/* We will read data from memory, so we need to flush the cache. */
 	CHECK_RETVAL(arc_cache_flush(target));
 
-	/* non-word writes are less common, than 4-byte writes, so I suppose we can
-	 * allowe ourselves to write this in a cycle, instead of calling arc_jtag
+	/* non-word writes are less common than 4-byte writes, so I suppose we can
+	 * allow ourselves to write this in a cycle, instead of calling arc_jtag
 	 * with count > 1. */
 	for (i = 0; i < count; i++) {
 		/* See comment in arc_mem_write_block16 for details. Since it is a byte
@@ -173,7 +173,7 @@ int arc_mem_write(struct target *target, target_addr_t address, uint32_t size,
 	if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 		return ERROR_TARGET_UNALIGNED_ACCESS;
 
-	/* correct endianess if we have word or hword access */
+	/* correct endianness if we have word or hword access */
 	if (size > 1) {
 		/*
 		 * arc_..._write_mem with size 4/2 requires uint32_t/uint16_t
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 28fefc5aa..b1b9aedd5 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -55,8 +55,8 @@
  * shadowed registers, and support for the Thumb instruction set.
  *
  * Processor differences include things like presence or absence of MMU
- * and cache, pipeline sizes, use of a modified Harvard Architecure
- * (with separate instruction and data busses from the CPU), support
+ * and cache, pipeline sizes, use of a modified Harvard Architecture
+ * (with separate instruction and data buses from the CPU), support
  * for cpu clock gating during idle, and more.
  */
 
@@ -1009,7 +1009,7 @@ int arm7_9_deassert_reset(struct target *target)
 
 /**
  * Clears the halt condition for an ARM7/9 target.  If it isn't coming out of
- * reset and if DBGRQ is used, it is progammed to be deasserted.  If the reset
+ * reset and if DBGRQ is used, it is programmed to be deasserted.  If the reset
  * vector catch was used, it is restored.  Otherwise, the control value is
  * restored and the watchpoint unit is restored if it was in use.
  *
diff --git a/src/target/arm946e.c b/src/target/arm946e.c
index 6b187f3ff..33da4a4f3 100644
--- a/src/target/arm946e.c
+++ b/src/target/arm946e.c
@@ -45,7 +45,7 @@
 /**
  * flag to give info about cache manipulation during debug :
  * "0"	-	cache lines are invalidated "on the fly", for affected addresses.
- *			This is prefered from performance point of view.
+ *			This is preferred from performance point of view.
  * "1"	-	cache is invalidated and switched off on debug_entry, and switched back on on restore.
  *			It is kept off during debugging.
  */
@@ -261,7 +261,7 @@ uint32_t arm946e_invalidate_whole_dcache(struct target *target)
 	 */
 	int nb_idx = (csize / (4*8*NB_CACHE_WAYS));	/* gives nb of lines (indexes) in the cache */
 
-	/* Loop for all segmentde (i.e. ways) */
+	/* Loop for all segments (i.e. ways) */
 	uint32_t seg;
 	for (seg = 0; seg < NB_CACHE_WAYS; seg++) {
 		/* Loop for all indexes */
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 11bf18549..058484471 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -51,7 +51,7 @@
  * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
  * further AP operations will fail.  There are two basic methods to avoid
  * such overrun errors.  One involves polling for status instead of using
- * transaction piplining.  The other involves adding delays to ensure the
+ * transaction pipelining.  The other involves adding delays to ensure the
  * AP has enough time to complete one operation before starting the next
  * one.  (For JTAG these delays are controlled by memaccess_tck.)
  */
@@ -872,7 +872,7 @@ int dap_find_ap(struct adiv5_dap *dap, enum ap_type type_to_find, struct adiv5_a
 		 *  3-0  : AP Type (0=JTAG-AP 1=AHB-AP 2=APB-AP 4=AXI-AP)
 		 */
 
-		/* Reading register for a non-existant AP should not cause an error,
+		/* Reading register for a non-existent AP should not cause an error,
 		 * but just to be sure, try to continue searching if an error does happen.
 		 */
 		if ((retval == ERROR_OK) &&                  /* Register read success */
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index da8aee28b..59c0537b7 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -92,8 +92,8 @@
  * the Cortex-M implementations).
  */
 
-/* textual represenation of the condition field
- * ALways (default) is ommitted (empty string) */
+/* textual representation of the condition field
+ * ALways (default) is omitted (empty string) */
 static const char *arm_condition_strings[] = {
 	"EQ", "NE", "CS", "CC", "MI", "PL", "VS", "VC", "HI", "LS", "GE", "LT", "GT", "LE", "", "NV"
 };
@@ -2896,7 +2896,7 @@ int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, struct arm_instruct
 	instruction->instruction_size = 2;
 
 	if ((opcode & 0xe000) == 0x0000) {
-		/* add/substract register or immediate */
+		/* add/subtract register or immediate */
 		if ((opcode & 0x1800) == 0x1800)
 			return evaluate_add_sub_thumb(opcode, address, instruction);
 		/* shift by immediate */
@@ -2904,7 +2904,7 @@ int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, struct arm_instruct
 			return evaluate_shift_imm_thumb(opcode, address, instruction);
 	}
 
-	/* Add/substract/compare/move immediate */
+	/* Add/subtract/compare/move immediate */
 	if ((opcode & 0xe000) == 0x2000)
 		return evaluate_data_proc_imm_thumb(opcode, address, instruction);
 
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 72215f90b..6bfe355ba 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -206,7 +206,7 @@ int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 					LOG_WARNING("Jazelle PC adjustment unknown");
 					break;
 				default:
-					LOG_WARNING("unknow core state");
+					LOG_WARNING("unknown core state");
 					break;
 			}
 			break;
@@ -335,7 +335,7 @@ static int dpm_write_pc_core_state(struct arm_dpm *dpm, struct reg *r)
 }
 
 /**
- * Read basic registers of the the current context:  R0 to R15, and CPSR;
+ * Read basic registers of the current context:  R0 to R15, and CPSR;
  * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
  * In normal operation this is called on entry to halting debug state,
  * possibly after some other operations supporting restore of debug state
diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h
index e94e8333b..90f841600 100644
--- a/src/target/arm_opcodes.h
+++ b/src/target/arm_opcodes.h
@@ -38,7 +38,7 @@
 /* Store multiple increment after
  * Rn: base register
  * List: for each bit in list: store register
- * S: in priviledged mode: store user-mode registers
+ * S: in privileged mode: store user-mode registers
  * W = 1: update the base register. W = 0: leave the base register untouched
  */
 #define ARMV4_5_STMIA(Rn, List, S, W) \
@@ -47,7 +47,7 @@
 /* Load multiple increment after
  * Rn: base register
  * List: for each bit in list: store register
- * S: in priviledged mode: store user-mode registers
+ * S: in privileged mode: store user-mode registers
  * W = 1: update the base register. W = 0: leave the base register untouched
  */
 #define ARMV4_5_LDMIA(Rn, List, S, W) \
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 2be70b78b..09dee9151 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -160,7 +160,7 @@ int armv7a_read_ttbcr(struct target *target)
 	}
 
 	/*
-	 * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
+	 * ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
 	 * document # ARM DDI 0406C
 	 */
 	armv7a->armv7a_mmu.ttbr_range[0]  = 0xffffffff >> ttbcr_n;
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 3d88c8679..7b6219821 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -48,7 +48,7 @@ struct armv7a_l2x_cache {
 };
 
 struct armv7a_cachesize {
-	/*  cache dimensionning */
+	/*  cache dimensioning */
 	uint32_t linelen;
 	uint32_t associativity;
 	uint32_t nsets;
diff --git a/src/target/armv7a_cache.c b/src/target/armv7a_cache.c
index 921ba9be9..e5f1fb060 100644
--- a/src/target/armv7a_cache.c
+++ b/src/target/armv7a_cache.c
@@ -409,7 +409,7 @@ int armv7a_cache_flush_virt(struct target *target, uint32_t virt,
  * We assume that target core was chosen correctly. It means if same data
  * was handled by two cores, other core will loose the changes. Since it
  * is impossible to know (FIXME) which core has correct data, keep in mind
- * that some kind of data lost or korruption is possible.
+ * that some kind of data lost or corruption is possible.
  * Possible scenario:
  *  - core1 loaded and changed data on 0x12345678
  *  - we halted target and modified same data on core0
@@ -577,7 +577,7 @@ const struct command_registration arm7a_l1_di_cache_group_handlers[] = {
 		.name = "info",
 		.handler = arm7a_l1_cache_info_cmd,
 		.mode = COMMAND_ANY,
-		.help = "print cache realted information",
+		.help = "print cache related information",
 		.usage = "",
 	},
 	{
diff --git a/src/target/armv7a_cache_l2x.c b/src/target/armv7a_cache_l2x.c
index 72e12b42b..3b20fd870 100644
--- a/src/target/armv7a_cache_l2x.c
+++ b/src/target/armv7a_cache_l2x.c
@@ -332,7 +332,7 @@ static const struct command_registration arm7a_l2x_cache_commands[] = {
 		.name = "info",
 		.handler = arm7a_l2x_cache_info_command,
 		.mode = COMMAND_ANY,
-		.help = "print cache realted information",
+		.help = "print cache related information",
 		.usage = "",
 	},
 	{
diff --git a/src/target/armv7m_trace.h b/src/target/armv7m_trace.h
index c63f36dea..e5879fb08 100644
--- a/src/target/armv7m_trace.h
+++ b/src/target/armv7m_trace.h
@@ -56,7 +56,7 @@ struct armv7m_trace_config {
 	/** Synchronous output port width */
 	uint32_t port_size;
 
-	/** Bitmask of currenty enabled ITM stimuli */
+	/** Bitmask of currently enabled ITM stimuli */
 	uint32_t itm_ter[8];
 	/** Identifier for multi-source trace stream formatting */
 	unsigned int trace_bus_id;
diff --git a/src/target/armv8.c b/src/target/armv8.c
index 4f1ebce88..e47f6599a 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -795,7 +795,7 @@ static uint8_t armv8_pa_size(uint32_t ps)
 			ret = 48;
 			break;
 		default:
-			LOG_INFO("Unknow physicall address size");
+			LOG_INFO("Unknown physical address size");
 			break;
 	}
 	return ret;
@@ -822,7 +822,7 @@ static __attribute__((unused)) int armv8_read_ttbcr32(struct target *target)
 	armv8->armv8_mmu.ttbcr = ttbcr;
 
 	/*
-	 * ARM Architecture Reference Manual (ARMv7-A and ARMv7-Redition),
+	 * ARM Architecture Reference Manual (ARMv7-A and ARMv7-R edition),
 	 * document # ARM DDI 0406C
 	 */
 	armv8->armv8_mmu.ttbr_range[0]  = 0xffffffff >> ttbcr_n;
@@ -852,7 +852,7 @@ static __attribute__((unused)) int armv8_read_ttbcr(struct target *target)
 	if (retval != ERROR_OK)
 		goto done;
 
-	/* claaer ttrr1_used and ttbr0_mask */
+	/* clear ttrr1_used and ttbr0_mask */
 	memset(&armv8->armv8_mmu.ttbr1_used, 0, sizeof(armv8->armv8_mmu.ttbr1_used));
 	memset(&armv8->armv8_mmu.ttbr0_mask, 0, sizeof(armv8->armv8_mmu.ttbr0_mask));
 
@@ -902,7 +902,7 @@ static __attribute__((unused)) int armv8_read_ttbcr(struct target *target)
 			goto done;
 		break;
 	default:
-		LOG_ERROR("unknow core state");
+		LOG_ERROR("unknown core state");
 		retval = ERROR_FAIL;
 		break;
 	}
diff --git a/src/target/armv8.h b/src/target/armv8.h
index c5ee5fd87..978b2ad4a 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -139,7 +139,7 @@ struct armv8_l2x_cache {
 
 struct armv8_cachesize {
 	uint32_t level_num;
-	/*  cache dimensionning */
+	/*  cache dimensioning */
 	uint32_t linelen;
 	uint32_t associativity;
 	uint32_t nsets;
diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index a3edb7f47..90cf4e059 100644
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -731,7 +731,7 @@ static int dpmv8_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 }
 
 /**
- * Read basic registers of the the current context:  R0 to R15, and CPSR;
+ * Read basic registers of the current context:  R0 to R15, and CPSR;
  * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
  * In normal operation this is called on entry to halting debug state,
  * possibly after some other operations supporting restore of debug state
diff --git a/src/target/avrt.c b/src/target/avrt.c
index 9cb6f2f34..eb8d000c4 100644
--- a/src/target/avrt.c
+++ b/src/target/avrt.c
@@ -195,7 +195,7 @@ static int mcu_write_ir_u8(struct jtag_tap *tap, uint8_t *ir_in,
 		uint8_t ir_out, int ir_len, int rti)
 {
 	if (ir_len > 8) {
-		LOG_ERROR("ir_len overflow, maxium is 8");
+		LOG_ERROR("ir_len overflow, maximum is 8");
 		return ERROR_FAIL;
 	}
 
@@ -208,7 +208,7 @@ static int mcu_write_dr_u32(struct jtag_tap *tap, uint32_t *dr_in,
 		uint32_t dr_out, int dr_len, int rti)
 {
 	if (dr_len > 32) {
-		LOG_ERROR("dr_len overflow, maxium is 32");
+		LOG_ERROR("dr_len overflow, maximum is 32");
 		return ERROR_FAIL;
 	}
 
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index f562a7614..aeeb11626 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -841,7 +841,7 @@ static int cortex_a_internal_restore(struct target *target, int current,
 			LOG_ERROR("How do I resume into Jazelle state??");
 			return ERROR_FAIL;
 		case ARM_STATE_AARCH64:
-			LOG_ERROR("Shoudn't be in AARCH64 state");
+			LOG_ERROR("Shouldn't be in AARCH64 state");
 			return ERROR_FAIL;
 	}
 	LOG_DEBUG("resume pc = 0x%08" PRIx32, resume_pc);
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index d9bee0e53..5ea928a32 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -113,7 +113,7 @@ static int cortexm_dap_write_coreregister_u32(struct target *target,
 		return retval;
 
 	if (target->dbg_msg_enabled) {
-		/* restore DCB_DCRDR - this needs to be in a seperate
+		/* restore DCB_DCRDR - this needs to be in a separate
 		 * transaction otherwise the emulated DCC channel breaks */
 		if (retval == ERROR_OK)
 			retval = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DCRDR, dcrdr);
@@ -951,7 +951,7 @@ static int cortex_m_step(struct target *target, int current,
 			 * just step over the instruction with interrupts disabled.
 			 *
 			 * The documentation has no information about this, it was found by observation
-			 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 dosen't seem to
+			 * on STM32F1 and STM32F2. Proper explanation welcome. STM32F0 doesn't seem to
 			 * suffer from this problem.
 			 *
 			 * To add some confusion: pc_value has bit 0 always set, while the breakpoint
diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c
index 6a5c8683e..3d4c61ae6 100644
--- a/src/target/dsp563xx.c
+++ b/src/target/dsp563xx.c
@@ -322,7 +322,7 @@ enum watchpoint_condition {
 #define INSTR_JUMP      0x0AF080
 /* Effective Addressing Mode Encoding */
 #define EAME_R0         0x10
-/* instrcution encoder */
+/* instruction encoder */
 /* movep
  * s - peripheral space X/Y (X=0,Y=1)
  * w - write/read
@@ -1359,7 +1359,7 @@ static int dsp563xx_deassert_reset(struct target *target)
 		if (target->state == TARGET_HALTED) {
 			/* after a reset the cpu jmp to the
 			 * reset vector and need 2 cycles to fill
-			 * the cache (fetch,decode,excecute)
+			 * the cache (fetch,decode,execute)
 			 */
 			err = dsp563xx_step_ex(target, 1, 0, 1, 1);
 			if (err != ERROR_OK)
diff --git a/src/target/dsp5680xx.c b/src/target/dsp5680xx.c
index c74a41846..d6107abc6 100644
--- a/src/target/dsp5680xx.c
+++ b/src/target/dsp5680xx.c
@@ -93,7 +93,7 @@ static int dsp5680xx_drscan(struct target *target, uint8_t *d_in,
 	if (len > 32) {
 		retval = ERROR_FAIL;
 		err_check(retval, DSP5680XX_ERROR_JTAG_DR_LEN_OVERFLOW,
-			  "dr_len overflow, maxium is 32");
+			  "dr_len overflow, maximum is 32");
 	}
 	/* TODO what values of len are valid for jtag_add_plain_dr_scan? */
 	/* can i send as many bits as i want? */
@@ -638,7 +638,7 @@ static int switch_tap(struct target *target, struct jtag_tap *master_tap,
  * more complicated routine, which is guaranteed to work, but requires
  * a reset. This will complicate comm with the flash module, since
  * after a reset clock divisors must be set again.
- * This implementation works most of the time, and is not accesible to the
+ * This implementation works most of the time, and is not accessible to the
  * user.
  *
  * @param target
@@ -1795,7 +1795,7 @@ static int set_fm_ck_div(struct target *target)
  * Executes the FM calculate signature command. The FM will calculate over the
  * data from @address to @address + @words -1. The result is written to a
  * register, then read out by this function and returned in @signature. The
- * value @signature may be compared to the the one returned by perl_crc to
+ * value @signature may be compared to the one returned by perl_crc to
  * verify the flash was written correctly.
  *
  * @param target
diff --git a/src/target/esirisc_regs.h b/src/target/esirisc_regs.h
index ad3385819..a946a2ecc 100644
--- a/src/target/esirisc_regs.h
+++ b/src/target/esirisc_regs.h
@@ -164,7 +164,7 @@ enum esirisc_reg_num {
 #define CSR_CONFIG_DBG				0x0f	/* Debug Configuration */
 #define CSR_CONFIG_MID				0x10	/* Manufacturer ID */
 #define CSR_CONFIG_REV				0x11	/* Revision Number */
-#define CSR_CONFIG_MPID				0x12	/* Mulitprocessor ID */
+#define CSR_CONFIG_MPID				0x12	/* Multiprocessor ID */
 #define CSR_CONFIG_FREQn			0x13	/* Frequency [0..2] */
 #define CSR_CONFIG_TRACE			0x16	/* Trace Configuration */
 
diff --git a/src/target/etm.h b/src/target/etm.h
index 6a78b7564..debe19743 100644
--- a/src/target/etm.h
+++ b/src/target/etm.h
@@ -203,7 +203,7 @@ typedef enum {
 	BR_ENABLE  = 0x1, /* Trace has been enabled */
 	BR_RESTART = 0x2, /* Trace restarted after a FIFO overflow */
 	BR_NODEBUG = 0x3, /* ARM has exited for debug state */
-	BR_PERIOD  = 0x4, /* Peridioc synchronization point (ETM >= v1.2)*/
+	BR_PERIOD  = 0x4, /* Periodic synchronization point (ETM >= v1.2)*/
 	BR_RSVD5   = 0x5, /* reserved */
 	BR_RSVD6   = 0x6, /* reserved */
 	BR_RSVD7   = 0x7, /* reserved */
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index d2b707d44..1d1351bbc 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -37,7 +37,7 @@
  * - asserting DBGRQ doesn't work if target is looping on the undef vector
  *
  * - the EICE version signature in the COMMS_CTL reg is next to the flow bits
- *   not at the top, and rather meaningless due to existing discrepencies
+ *   not at the top, and rather meaningless due to existing discrepancies
  *
  * - the DCC channel is half duplex (only one FIFO for both directions) with
  *   seemingly no proper flow control.
diff --git a/src/target/image.c b/src/target/image.c
index 1003c3bdc..64d4d52c3 100644
--- a/src/target/image.c
+++ b/src/target/image.c
@@ -832,7 +832,7 @@ int image_open(struct image *image, const char *url, const char *type_string)
 		for (section = 0; section < image->num_sections; section++)
 			image->sections[section].base_address += image->base_address;
 											/* we're done relocating. The two statements below are mainly
-											* for documenation purposes: stop anyone from empirically
+											* for documentation purposes: stop anyone from empirically
 											* thinking they should use these values henceforth. */
 		image->base_address = 0;
 		image->base_address_set = 0;
diff --git a/src/target/lakemont.c b/src/target/lakemont.c
index 31882b828..31b521b3a 100644
--- a/src/target/lakemont.c
+++ b/src/target/lakemont.c
@@ -330,7 +330,7 @@ static int restore_context(struct target *t)
 
 /*
  * we keep reg_cache in sync with hardware at halt/resume time, we avoid
- * writing to real hardware here bacause pm_regs reflects the hardware
+ * writing to real hardware here because pm_regs reflects the hardware
  * while we are halted then reg_cache syncs with hw on resume
  * TODO - in order for "reg eip force" to work it assume get/set reads
  * and writes from hardware, may be other reasons also because generally
@@ -363,7 +363,7 @@ static int lakemont_set_core_reg(struct reg *reg, uint8_t *buf)
 }
 
 static const struct reg_arch_type lakemont_reg_type = {
-	/* these get called if reg_cache doesnt have a "valid" value
+	/* these get called if reg_cache doesn't have a "valid" value
 	 * of an individual reg eg "reg eip" but not for "reg" block
 	 */
 	.get = lakemont_get_core_reg,
@@ -649,7 +649,7 @@ static int read_hw_reg(struct target *t, int reg, uint32_t *regval, uint8_t cach
 	struct x86_32_common *x86_32 = target_to_x86_32(t);
 	struct lakemont_core_reg *arch_info;
 	arch_info = x86_32->cache->reg_list[reg].arch_info;
-	x86_32->flush = 0; /* dont flush scans till we have a batch */
+	x86_32->flush = 0; /* don't flush scans till we have a batch */
 	if (submit_reg_pir(t, reg) != ERROR_OK)
 		return ERROR_FAIL;
 	if (submit_instruction_pir(t, SRAMACCESS) != ERROR_OK)
@@ -693,7 +693,7 @@ static int write_hw_reg(struct target *t, int reg, uint32_t regval, uint8_t cach
 			arch_info->op,
 			regval);
 
-	x86_32->flush = 0; /* dont flush scans till we have a batch */
+	x86_32->flush = 0; /* don't flush scans till we have a batch */
 	if (submit_reg_pir(t, reg) != ERROR_OK)
 		return ERROR_FAIL;
 	if (submit_instruction_pir(t, SRAMACCESS) != ERROR_OK)
@@ -943,7 +943,7 @@ int lakemont_poll(struct target *t)
 				if (bp != NULL) {
 					t->debug_reason = DBG_REASON_BREAKPOINT;
 					if (bp->type == BKPT_SOFT) {
-						/* The EIP is now pointing the the next byte after the
+						/* The EIP is now pointing the next byte after the
 						 * breakpoint instruction. This needs to be corrected.
 						 */
 						buf_set_u32(x86_32->cache->reg_list[EIP].value, 0, 32, eip-1);
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 3929a8c99..ef7f2ad26 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -723,7 +723,7 @@ int mips32_read_config_regs(struct target *target)
 				break;	/* no more config registers implemented */
 		}
 	else
-		return ERROR_OK;	/* already succesfully read */
+		return ERROR_OK;	/* already successfully read */
 
 	LOG_DEBUG("read  %"PRId32" config registers", ejtag_info->config_regs);
 
diff --git a/src/target/mips32.h b/src/target/mips32.h
index 4dc164e1b..f107b57d5 100644
--- a/src/target/mips32.h
+++ b/src/target/mips32.h
@@ -42,7 +42,7 @@
 /** Returns the kernel segment base of a given address */
 #define KSEGX(a)		((a) & 0xe0000000)
 
-/** CP0 CONFIG regites fields */
+/** CP0 CONFIG register fields */
 #define MIPS32_CONFIG0_KU_SHIFT 25
 #define MIPS32_CONFIG0_KU_MASK (0x7 << MIPS32_CONFIG0_KU_SHIFT)
 
diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c
index 790c8dc93..81be70d12 100644
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@@ -277,7 +277,7 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ct
 						return ERROR_JTAG_DEVICE_ERROR;
 					}
 				} else
-					if (code_count > 10) {		/* enough, abandone */
+					if (code_count > 10) {		/* enough, abandon */
 						LOG_DEBUG("execution abandoned, store pending: %d", store_pending);
 						return ERROR_JTAG_DEVICE_ERROR;
 					}
@@ -427,7 +427,7 @@ int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_in
 		fetch_addr += 4;
 		scan_count++;
 
-		/* check if previous intrucction is a store instruction at dmesg */
+		/* check if previous instruction is a store instruction at dmesg */
 		if (i > 0 && ctx->pracc_list[i - 1].addr) {
 			uint32_t store_addr = ctx->pracc_list[i - 1].addr;
 			ejtag_ctrl = buf_get_u32(scan_in[scan_count].scan_32.ctrl, 0, 32);
@@ -789,7 +789,7 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int siz
 	 * If we are in the cacheable region and cache is activated,
 	 * we must clean D$ (if Cache Coherency Attribute is set to 3) + invalidate I$ after we did the write,
 	 * so that changes do not continue to live only in D$ (if CCA = 3), but to be
-	 * replicated in I$ also (maybe we wrote the istructions)
+	 * replicated in I$ also (maybe we wrote the instructions)
 	 */
 	uint32_t conf = 0;
 	int cached = 0;
@@ -816,7 +816,7 @@ int mips32_pracc_write_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int siz
 	}
 
 	/**
-	 * Check cachablitiy bits coherency algorithm
+	 * Check cacheability bits coherency algorithm
 	 * is the region cacheable or uncached.
 	 * If cacheable we have to synchronize the cache
 	 */
diff --git a/src/target/mips32_pracc.h b/src/target/mips32_pracc.h
index e31ba63e2..911a69c5b 100644
--- a/src/target/mips32_pracc.h
+++ b/src/target/mips32_pracc.h
@@ -58,7 +58,7 @@ struct pracc_queue_info {
 	int retval;
 	int code_count;
 	int store_count;
-	int max_code;		/* max intstructions with currently allocated memory */
+	int max_code;		/* max instructions with currently allocated memory */
 	pa_list *pracc_list;	/* Code and store addresses at dmseg */
 };
 
@@ -93,7 +93,7 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ct
  * @param[in] cp0_reg Number of copro C0 register we want to read
  * @param[in] cp0_sel Select for the given C0 register
  *
- * @return ERROR_OK on Sucess, ERROR_FAIL otherwise
+ * @return ERROR_OK on Success, ERROR_FAIL otherwise
  */
 int mips32_cp0_read(struct mips_ejtag *ejtag_info,
 		uint32_t *val, uint32_t cp0_reg, uint32_t cp0_sel);
@@ -109,7 +109,7 @@ int mips32_cp0_read(struct mips_ejtag *ejtag_info,
  * @param[in] cp0_reg Number of copro C0 register we want to write to
  * @param[in] cp0_sel Select for the given C0 register
  *
- * @return ERROR_OK on Sucess, ERROR_FAIL otherwise
+ * @return ERROR_OK on Success, ERROR_FAIL otherwise
  */
 int mips32_cp0_write(struct mips_ejtag *ejtag_info,
 		uint32_t val, uint32_t cp0_reg, uint32_t cp0_sel);
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 3735cbb67..7544afe52 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -278,7 +278,7 @@ int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info)
 	return ctx.retval;
 }
 
-/* mips_ejtag_init_mmr - asign Memory-Mapped Registers depending
+/* mips_ejtag_init_mmr - assign Memory-Mapped Registers depending
  *			on EJTAG version.
  */
 static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info)
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index ad27520c8..d1d094520 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -667,7 +667,7 @@ static int mips_m4k_set_breakpoint(struct target *target,
 			if (ejtag_info->endianness && isa_req)
 				sdbbp32_instr = SWAP16(sdbbp32_instr);
 
-			if ((breakpoint->address & 3) == 0) {	/* word alligned */
+			if ((breakpoint->address & 3) == 0) {	/* word aligned */
 
 				retval = target_read_memory(target, bpaddr, bplength, 1, breakpoint->orig_instr);
 				if (retval != ERROR_OK)
@@ -784,9 +784,9 @@ static int mips_m4k_unset_breakpoint(struct target *target,
 				if (retval != ERROR_OK)
 					return retval;
 				/**
-				* target_read_memory() gets us data in _target_ endianess.
+				* target_read_memory() gets us data in _target_ endianness.
 				* If we want to use this data on the host for comparisons with some macros
-				* we must first transform it to _host_ endianess using target_buffer_get_u16().
+				* we must first transform it to _host_ endianness using target_buffer_get_u16().
 				*/
 				if (sdbbp32_instr == target_buffer_get_u32(target, current_instr)) {
 					retval = target_write_memory(target, breakpoint->address, 4, 1,
@@ -794,7 +794,7 @@ static int mips_m4k_unset_breakpoint(struct target *target,
 					if (retval != ERROR_OK)
 						return retval;
 				}
-			} else {	/* 16bit alligned */
+			} else {	/* 16bit aligned */
 				retval = target_read_memory(target, breakpoint->address, 2, 2, current_instr);
 				if (retval != ERROR_OK)
 					return retval;
@@ -1106,7 +1106,7 @@ static int mips_m4k_write_memory(struct target *target, target_addr_t address,
 	if (((size == 4) && (address & 0x3u)) || ((size == 2) && (address & 0x1u)))
 		return ERROR_TARGET_UNALIGNED_ACCESS;
 
-	/** correct endianess if we have word or hword access */
+	/** correct endianness if we have word or hword access */
 	void *t = NULL;
 	if (size > 1) {
 		/* mips32_..._write_mem with size 4/2 requires uint32_t/uint16_t in host */
diff --git a/src/target/nds32_v2.c b/src/target/nds32_v2.c
index 29489a034..392bd6eb9 100644
--- a/src/target/nds32_v2.c
+++ b/src/target/nds32_v2.c
@@ -256,7 +256,7 @@ static int nds32_v2_check_interrupt_stack(struct nds32_v2_common *nds32_v2)
 		aice_write_register(aice, IR2, val_ir2);
 	}
 
-	/* get origianl DT bit and set to current state let debugger has same memory view
+	/* get original DT bit and set to current state let debugger has same memory view
 	   PSW.IT MUST be turned off.  Otherwise, DIM could not operate normally. */
 	aice_read_register(aice, IR1, &val_ir1);
 	modified_psw = val_ir0 | (val_ir1 & 0x80);
diff --git a/src/target/openrisc/or1k.c b/src/target/openrisc/or1k.c
index ec07126f4..aa7b0d332 100644
--- a/src/target/openrisc/or1k.c
+++ b/src/target/openrisc/or1k.c
@@ -632,7 +632,7 @@ static int or1k_is_cpu_running(struct target *target, int *running)
 			LOG_WARNING("Debug IF CPU control reg read failure.");
 			/* Try once to restart the JTAG infrastructure -
 			   quite possibly the board has just been reset. */
-			LOG_WARNING("Resetting JTAG TAP state and reconnectiong to debug IF.");
+			LOG_WARNING("Resetting JTAG TAP state and reconnecting to debug IF.");
 			du_core->or1k_jtag_init(&or1k->jtag);
 
 			LOG_WARNING("...attempt %d of %d", tries, RETRIES_MAX);
@@ -742,7 +742,7 @@ static int or1k_deassert_reset(struct target *target)
 
 	int retval = du_core->or1k_cpu_reset(&or1k->jtag, CPU_NOT_RESET);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("Error while desasserting RESET");
+		LOG_ERROR("Error while deasserting RESET");
 		return retval;
 	}
 
diff --git a/src/target/openrisc/or1k_du_adv.c b/src/target/openrisc/or1k_du_adv.c
index bdd6fc8cb..d5e740d5d 100644
--- a/src/target/openrisc/or1k_du_adv.c
+++ b/src/target/openrisc/or1k_du_adv.c
@@ -995,7 +995,7 @@ int or1k_adv_jtag_jsp_xfer(struct or1k_jtag *jtag_info,
 				  int *out_len, unsigned char *out_buffer,
 				  int *in_len, unsigned char *in_buffer)
 {
-	LOG_DEBUG("JSP transfert");
+	LOG_DEBUG("JSP transfer");
 
 	int retval;
 	if (!jtag_info->or1k_jtag_inited)
diff --git a/src/target/openrisc/or1k_tap_vjtag.c b/src/target/openrisc/or1k_tap_vjtag.c
index db10f103b..3372509c9 100644
--- a/src/target/openrisc/or1k_tap_vjtag.c
+++ b/src/target/openrisc/or1k_tap_vjtag.c
@@ -99,7 +99,7 @@ static int or1k_tap_vjtag_init(struct or1k_jtag *jtag_info)
 
 	/* You can use a custom JTAG controller to discover transactions
 	 * necessary to enumerate all Virtual JTAG megafunction instances
-	 * from your design atruntime. All SLD nodes and the virtual JTAG
+	 * from your design at runtime. All SLD nodes and the virtual JTAG
 	 * registers that they contain are targeted by two Instruction Register
 	 * values, USER0 and USER1.
 	 *
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 4a323e4ee..2f8da5b36 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -3732,10 +3732,10 @@ int riscv013_test_compliance(struct target *target)
 		COMPLIANCE_TEST(ERROR_OK == register_read_direct(target, &testval_read, GDB_REGNO_ZERO + i),
 				"GPR Reads should be supported.");
 		if (riscv_xlen(target) > 32) {
-			/* Dummy comment to satisfy linter, since removing the brances here doesn't actually compile. */
+			/* Dummy comment to satisfy linter, since removing the branches here doesn't actually compile. */
 			COMPLIANCE_TEST(testval == testval_read, "GPR Reads and writes should be supported.");
 		} else {
-			/* Dummy comment to satisfy linter, since removing the brances here doesn't actually compile. */
+			/* Dummy comment to satisfy linter, since removing the branches here doesn't actually compile. */
 			COMPLIANCE_TEST((testval & 0xFFFFFFFF) == testval_read, "GPR Reads and writes should be supported.");
 		}
 	}
diff --git a/src/target/riscv/riscv.h b/src/target/riscv/riscv.h
index 51cf7f928..ba50d2c51 100644
--- a/src/target/riscv/riscv.h
+++ b/src/target/riscv/riscv.h
@@ -215,12 +215,12 @@ int riscv_current_hartid(const struct target *target);
  * without requiring multiple targets.  */
 
 /* When using the RTOS to debug, this selects the hart that is currently being
- * debugged.  This doesn't propogate to the hardware. */
+ * debugged.  This doesn't propagate to the hardware. */
 void riscv_set_all_rtos_harts(struct target *target);
 void riscv_set_rtos_hartid(struct target *target, int hartid);
 
 /* Lists the number of harts in the system, which are assumed to be
- * concecutive and start with mhartid=0. */
+ * consecutive and start with mhartid=0. */
 int riscv_count_harts(struct target *target);
 
 /* Returns TRUE if the target has the given register on the given hart.  */
diff --git a/src/target/semihosting_common.c b/src/target/semihosting_common.c
index a02f2df3f..965055609 100644
--- a/src/target/semihosting_common.c
+++ b/src/target/semihosting_common.c
@@ -145,7 +145,7 @@ int semihosting_common(struct target *target)
 {
 	struct semihosting *semihosting = target->semihosting;
 	if (!semihosting) {
-		/* Silently ignore if the semhosting field was not set. */
+		/* Silently ignore if the semihosting field was not set. */
 		return ERROR_OK;
 	}
 
@@ -345,7 +345,7 @@ int semihosting_common(struct target *target)
 							"semihosting: *** application exited normally ***\n");
 					}
 				} else if (semihosting->param == ADP_STOPPED_RUN_TIME_ERROR) {
-					/* Chosen more or less arbitrarly to have a nicer message,
+					/* Chosen more or less arbitrarily to have a nicer message,
 					 * otherwise all other return the same exit code 1. */
 					if (!gdb_actual_connections)
 						exit(1);
diff --git a/src/target/startup.tcl b/src/target/startup.tcl
index 976cd2af5..93e46b5f8 100644
--- a/src/target/startup.tcl
+++ b/src/target/startup.tcl
@@ -119,7 +119,7 @@ proc ocd_process_reset_inner { MODE } {
 				continue
 			}
 
-			# Wait upto 1 second for target to halt.  Why 1sec? Cause
+			# Wait up to 1 second for target to halt. Why 1sec? Cause
 			# the JTAG tap reset signal might be hooked to a slow
 			# resistor/capacitor circuit - and it might take a while
 			# to charge
diff --git a/src/target/stm8.c b/src/target/stm8.c
index ee3bb31a9..4b93dd1fe 100644
--- a/src/target/stm8.c
+++ b/src/target/stm8.c
@@ -967,7 +967,7 @@ static int stm8_reset_deassert(struct target *target)
 	if (target->reset_halt)
 		return ERROR_OK;
 
-	/* Instead of going thrugh saving context, polling and
+	/* Instead of going through saving context, polling and
 	   then resuming target again just clear stall and proceed. */
 	target->state = TARGET_RUNNING;
 	return stm8_exit_debug(target);
diff --git a/src/target/target.c b/src/target/target.c
index 8c0fd496e..b39254826 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -593,7 +593,7 @@ int target_halt(struct target *target)
  * @param address Optionally used as the program counter.
  * @param handle_breakpoints True iff breakpoints at the resumption PC
  *	should be skipped.  (For example, maybe execution was stopped by
- *	such a breakpoint, in which case it would be counterprodutive to
+ *	such a breakpoint, in which case it would be counterproductive to
  *	let it re-trigger.
  * @param debug_execution False if all working areas allocated by OpenOCD
  *	should be released and/or restored to their original contents.
@@ -709,7 +709,7 @@ static int default_check_reset(struct target *target)
 	return ERROR_OK;
 }
 
-/* Equvivalent Tcl code arp_examine_one is in src/target/startup.tcl
+/* Equivalent Tcl code arp_examine_one is in src/target/startup.tcl
  * Keep in sync */
 int target_examine_one(struct target *target)
 {
@@ -3462,7 +3462,7 @@ COMMAND_HANDLER(handle_load_image_command)
 		uint32_t offset = 0;
 		uint32_t length = buf_cnt;
 
-		/* DANGER!!! beware of unsigned comparision here!!! */
+		/* DANGER!!! beware of unsigned comparison here!!! */
 
 		if ((image.sections[i].base_address + buf_cnt >= min_address) &&
 				(image.sections[i].base_address < max_address)) {
@@ -4686,7 +4686,7 @@ static int target_configure(Jim_GetOptInfo *goi, struct target *target)
 		}
 		switch (n->value) {
 		case TCFG_TYPE:
-			/* not setable */
+			/* not settable */
 			if (goi->isconfigure) {
 				Jim_SetResultFormatted(goi->interp,
 						"not settable: %s", n->name);
@@ -5674,7 +5674,7 @@ static int jim_target_smp(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 	retval = 0;
 	LOG_DEBUG("%d", argc);
 	/* argv[1] = target to associate in smp
-	 * argv[2] = target to assoicate in smp
+	 * argv[2] = target to associate in smp
 	 * argv[3] ...
 	 */
 
@@ -5844,7 +5844,7 @@ COMMAND_HANDLER(handle_fast_load_image_command)
 		uint32_t offset = 0;
 		uint32_t length = buf_cnt;
 
-		/* DANGER!!! beware of unsigned comparision here!!! */
+		/* DANGER!!! beware of unsigned comparison here!!! */
 
 		if ((image.sections[i].base_address + buf_cnt >= min_address) &&
 				(image.sections[i].base_address < max_address)) {
diff --git a/src/target/target_request.c b/src/target/target_request.c
index c1da1a20e..32a907233 100644
--- a/src/target/target_request.c
+++ b/src/target/target_request.c
@@ -261,7 +261,7 @@ COMMAND_HANDLER(handle_target_request_debugmsgs_command)
 		return ERROR_OK;
 	}
 
-	/* see if reciever is already registered */
+	/* see if receiver is already registered */
 	if (find_debug_msg_receiver(CMD_CTX, target) != NULL)
 		receiving = 1;
 
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 1bca96d73..770b3259e 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -824,7 +824,7 @@ static int xscale_poll(struct target *target)
 			retval = xscale_debug_entry(target);
 		} else if (retval != ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 			LOG_USER("error while polling TX register, reset CPU");
-			/* here we "lie" so GDB won't get stuck and a reset can be perfomed */
+			/* here we "lie" so GDB won't get stuck and a reset can be performed */
 			target->state = TARGET_HALTED;
 		}
 
@@ -955,7 +955,7 @@ static int xscale_debug_entry(struct target *target)
 			xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
 			pc -= 4;
 			break;
-		case 0x5:	/* Vector trap occured */
+		case 0x5:	/* Vector trap occurred */
 			target->debug_reason = DBG_REASON_BREAKPOINT;
 			xscale->arch_debug_reason = XSCALE_DBG_REASON_GENERIC;
 			pc -= 4;
@@ -2412,7 +2412,7 @@ static int xscale_get_reg(struct reg *reg)
 	} else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) {
 		/* can't (explicitly) read from TXRXCTRL register */
 		return ERROR_OK;
-	} else {/* Other DBG registers have to be transfered by the debug handler
+	} else {/* Other DBG registers have to be transferred by the debug handler
 		 * send CP read request (command 0x40) */
 		xscale_send_u32(target, 0x40);
 
@@ -2450,7 +2450,7 @@ static int xscale_set_reg(struct reg *reg, uint8_t *buf)
 	} else if (strcmp(reg->name, "XSCALE_TXRXCTRL") == 0) {
 		/* can't (explicitly) write to TXRXCTRL register */
 		return ERROR_OK;
-	} else {/* Other DBG registers have to be transfered by the debug handler
+	} else {/* Other DBG registers have to be transferred by the debug handler
 		 * send CP write request (command 0x41) */
 		xscale_send_u32(target, 0x41);
 
@@ -2809,7 +2809,7 @@ static int xscale_analyze_trace(struct target *target, struct command_invocation
 						current_pc = chkpt_reg;
 					else if (current_pc != chkpt_reg)	/* sanity check */
 						LOG_WARNING("trace is suspect: checkpoint register "
-							"inconsistent with adddress from image");
+							"inconsistent with address from image");
 				}
 
 				if (current_pc == 0)
@@ -2942,7 +2942,7 @@ static int xscale_init_arch_info(struct target *target,
 
 	arm = &xscale->arm;
 
-	/* store architecture specfic data */
+	/* store architecture specific data */
 	xscale->common_magic = XSCALE_COMMON_MAGIC;
 
 	/* PXA3xx with 11 bit IR shifts the JTAG instructions */

-----------------------------------------------------------------------

Summary of changes:
 src/target/aarch64.c                 |  2 +-
 src/target/arc.c                     | 14 +++++++-------
 src/target/arc_cmd.c                 | 24 ++++++++++++------------
 src/target/arc_jtag.c                |  4 ++--
 src/target/arc_mem.c                 | 10 +++++-----
 src/target/arm7_9_common.c           |  6 +++---
 src/target/arm946e.c                 |  4 ++--
 src/target/arm_adi_v5.c              |  4 ++--
 src/target/arm_disassembler.c        |  8 ++++----
 src/target/arm_dpm.c                 |  4 ++--
 src/target/arm_opcodes.h             |  4 ++--
 src/target/armv7a.c                  |  2 +-
 src/target/armv7a.h                  |  2 +-
 src/target/armv7a_cache.c            |  4 ++--
 src/target/armv7a_cache_l2x.c        |  2 +-
 src/target/armv7m_trace.h            |  2 +-
 src/target/armv8.c                   |  8 ++++----
 src/target/armv8.h                   |  2 +-
 src/target/armv8_dpm.c               |  2 +-
 src/target/avrt.c                    |  4 ++--
 src/target/cortex_a.c                |  2 +-
 src/target/cortex_m.c                |  4 ++--
 src/target/dsp563xx.c                |  4 ++--
 src/target/dsp5680xx.c               |  6 +++---
 src/target/esirisc_regs.h            |  2 +-
 src/target/etm.h                     |  2 +-
 src/target/feroceon.c                |  2 +-
 src/target/image.c                   |  2 +-
 src/target/lakemont.c                | 10 +++++-----
 src/target/mips32.c                  |  2 +-
 src/target/mips32.h                  |  2 +-
 src/target/mips32_pracc.c            |  8 ++++----
 src/target/mips32_pracc.h            |  6 +++---
 src/target/mips_ejtag.c              |  2 +-
 src/target/mips_m4k.c                | 10 +++++-----
 src/target/nds32_v2.c                |  2 +-
 src/target/openrisc/or1k.c           |  4 ++--
 src/target/openrisc/or1k_du_adv.c    |  2 +-
 src/target/openrisc/or1k_tap_vjtag.c |  2 +-
 src/target/riscv/riscv-013.c         |  4 ++--
 src/target/riscv/riscv.h             |  4 ++--
 src/target/semihosting_common.c      |  4 ++--
 src/target/startup.tcl               |  2 +-
 src/target/stm8.c                    |  2 +-
 src/target/target.c                  | 12 ++++++------
 src/target/target_request.c          |  2 +-
 src/target/xscale.c                  | 12 ++++++------
 47 files changed, 114 insertions(+), 114 deletions(-)


hooks/post-receive
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Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1362-g3e6f4f8b2

From: OpenOCD-Gerrit <ope...@us...> - 2020-07-26 19:16:51

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  3e6f4f8b213ce2c61b052b16606cfc81ba6d7cc4 (commit)
      from  9b32a06dad0aa6fc9c3896b21d3c32015487a090 (commit)

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- Log -----------------------------------------------------------------
commit 3e6f4f8b213ce2c61b052b16606cfc81ba6d7cc4
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Apr 4 19:47:09 2020 +0200

    drivers/bitbang: blink LED on SWD
    
    The blinking was implemented for JTAG only.
    
    Extend it to SWD.
    There is no error check on SWD exchange. Add a FIXME for further
    fix.
    
    Change-Id: I42a6708c54b1eefaf691e0fe09ca58c42b2764fd
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5771
    Tested-by: jenkins

diff --git a/src/jtag/drivers/bitbang.c b/src/jtag/drivers/bitbang.c
index 4417e1258..2a78fa248 100644
--- a/src/jtag/drivers/bitbang.c
+++ b/src/jtag/drivers/bitbang.c
@@ -394,6 +394,11 @@ static void bitbang_swd_exchange(bool rnw, uint8_t buf[], unsigned int offset, u
 {
 	LOG_DEBUG("bitbang_swd_exchange");
 
+	if (bitbang_interface->blink) {
+		/* FIXME: we should manage errors */
+		bitbang_interface->blink(1);
+	}
+
 	for (unsigned int i = offset; i < bit_cnt + offset; i++) {
 		int bytec = i/8;
 		int bcval = 1 << (i % 8);
@@ -410,6 +415,11 @@ static void bitbang_swd_exchange(bool rnw, uint8_t buf[], unsigned int offset, u
 
 		bitbang_interface->swd_write(1, swdio);
 	}
+
+	if (bitbang_interface->blink) {
+		/* FIXME: we should manage errors */
+		bitbang_interface->blink(0);
+	}
 }
 
 static int bitbang_swd_switch_seq(enum swd_special_seq seq)

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/bitbang.c | 10 ++++++++++
 1 file changed, 10 insertions(+)


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This is an automated email from the git hooks/post-receive script. It was
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the project "Main OpenOCD repository".

The branch, master has been updated
       via  9b32a06dad0aa6fc9c3896b21d3c32015487a090 (commit)
       via  d62b3c51df50e68e7f8f583f337538b1ea510d97 (commit)
      from  02ecd452c219a98b9da910b97755c5a326ab4cad (commit)

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- Log -----------------------------------------------------------------
commit 9b32a06dad0aa6fc9c3896b21d3c32015487a090
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Apr 4 19:46:38 2020 +0200

    drivers/linuxgpiod: add led
    
    Bitbang interface allows having a LED on one of the GPIO.
    
    Let also linuxgpiod driver to specify and use the LED connection.
    
    Change-Id: Id3d8772ee1808b92354fd073ba3947bacd8253ef
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5770
    Tested-by: jenkins

diff --git a/src/jtag/drivers/linuxgpiod.c b/src/jtag/drivers/linuxgpiod.c
index 661a926f5..99422a116 100644
--- a/src/jtag/drivers/linuxgpiod.c
+++ b/src/jtag/drivers/linuxgpiod.c
@@ -27,6 +27,7 @@ static int trst_gpio = -1;
 static int srst_gpio = -1;
 static int swclk_gpio = -1;
 static int swdio_gpio = -1;
+static int led_gpio = -1;
 static int gpiochip = -1;
 
 static struct gpiod_chip *gpiod_chip;
@@ -38,6 +39,7 @@ static struct gpiod_line *gpiod_trst;
 static struct gpiod_line *gpiod_swclk;
 static struct gpiod_line *gpiod_swdio;
 static struct gpiod_line *gpiod_srst;
+static struct gpiod_line *gpiod_led;
 
 static int last_swclk;
 static int last_swdio;
@@ -171,13 +173,26 @@ static int linuxgpiod_swd_write(int swclk, int swdio)
 	return ERROR_OK;
 }
 
+static int linuxgpiod_blink(int on)
+{
+	int retval;
+
+	if (!gpiod_led)
+		return ERROR_OK;
+
+	retval = gpiod_line_set_value(gpiod_led, on);
+	if (retval < 0)
+		LOG_WARNING("Fail set led");
+	return retval;
+}
+
 static struct bitbang_interface linuxgpiod_bitbang = {
 	.read = linuxgpiod_read,
 	.write = linuxgpiod_write,
 	.swdio_read = linuxgpiod_swdio_read,
 	.swdio_drive = linuxgpiod_swdio_drive,
 	.swd_write = linuxgpiod_swd_write,
-	.blink = NULL,
+	.blink = linuxgpiod_blink,
 };
 
 /*
@@ -248,6 +263,7 @@ static inline void helper_release(struct gpiod_line *line)
 
 static int linuxgpiod_quit(void)
 {
+	helper_release(gpiod_led);
 	helper_release(gpiod_srst);
 	helper_release(gpiod_swdio);
 	helper_release(gpiod_swclk);
@@ -370,6 +386,12 @@ static int linuxgpiod_init(void)
 			goto out_error;
 	}
 
+	if (is_gpio_valid(led_gpio)) {
+		gpiod_led = helper_get_output_line("led", led_gpio, 0);
+		if (gpiod_led == NULL)
+			goto out_error;
+	}
+
 	return ERROR_OK;
 
 out_error:
@@ -484,6 +506,15 @@ COMMAND_HANDLER(linuxgpiod_handle_swd_gpionum_swdio)
 	return ERROR_OK;
 }
 
+COMMAND_HANDLER(linuxgpiod_handle_gpionum_led)
+{
+	if (CMD_ARGC == 1)
+		COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], led_gpio);
+
+	command_print(CMD, "LinuxGPIOD num: led = %d", led_gpio);
+	return ERROR_OK;
+}
+
 COMMAND_HANDLER(linuxgpiod_handle_gpiochip)
 {
 	if (CMD_ARGC == 1)
@@ -564,6 +595,13 @@ static const struct command_registration linuxgpiod_command_handlers[] = {
 		.help = "gpio number for swdio.",
 		.usage = "swdio",
 	},
+	{
+		.name = "linuxgpiod_led_num",
+		.handler = linuxgpiod_handle_gpionum_led,
+		.mode = COMMAND_CONFIG,
+		.help = "gpio number for LED.",
+		.usage = "led",
+	},
 	{
 		.name = "linuxgpiod_gpiochip",
 		.handler = linuxgpiod_handle_gpiochip,
diff --git a/tcl/interface/dln-2-gpiod.cfg b/tcl/interface/dln-2-gpiod.cfg
index 1859688be..5407a244e 100644
--- a/tcl/interface/dln-2-gpiod.cfg
+++ b/tcl/interface/dln-2-gpiod.cfg
@@ -11,6 +11,7 @@
 # | TMS/SWDIO | J3.4  (PA3) | 3           |
 # | TDI       | J3.5  (PA4) | 4           |
 # | nTRST     | J3.6  (PA5) | 5           |
+# | LED       | J3.7  (PA6) | 6           |
 # | GND       | J3.12 (GND) |             |
 # +-----------+-------------+-------------+
 
@@ -21,5 +22,6 @@ linuxgpiod_jtag_nums 2 3 4 1
 linuxgpiod_trst_num 5
 linuxgpiod_swd_nums 2 3
 linuxgpiod_srst_num 0
+linuxgpiod_led_num 6
 
 reset_config trst_and_srst separate srst_push_pull

commit d62b3c51df50e68e7f8f583f337538b1ea510d97
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jul 12 00:38:12 2020 +0200

    svf: fix minor typos
    
    Change-Id: I40ac2d01c1feb2771ce96a26c4a4d05a1e816a61
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5761
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/svf/svf.c b/src/svf/svf.c
index 81400c530..010592076 100644
--- a/src/svf/svf.c
+++ b/src/svf/svf.c
@@ -18,11 +18,11 @@
 
 /* The specification for SVF is available here:
  * http://www.asset-intertech.com/support/svf.pdf
- * Below, this document is refered to as the "SVF spec".
+ * Below, this document is referred to as the "SVF spec".
  *
  * The specification for XSVF is available here:
  * http://www.xilinx.com/support/documentation/application_notes/xapp503.pdf
- * Below, this document is refered to as the "XSVF spec".
+ * Below, this document is referred to as the "XSVF spec".
  */
 
 #ifdef HAVE_CONFIG_H
@@ -231,7 +231,7 @@ static int svf_quiet;
 static int svf_nil;
 static int svf_ignore_error;
 
-/* Targetting particular tap */
+/* Targeting particular tap */
 static int svf_tap_is_specified;
 static int svf_set_padding(struct svf_xxr_para *para, int len, unsigned char tdi);
 
@@ -854,7 +854,7 @@ static int svf_copy_hexstring_to_binary(char *str, uint8_t **bin, int orig_bit_l
 
 	/* check validity: we must have consumed everything */
 	if (str_len > 0 || (ch & ~((2 << ((bit_len - 1) % 4)) - 1)) != 0) {
-		LOG_ERROR("value execeeds length");
+		LOG_ERROR("value exceeds length");
 		return ERROR_FAIL;
 	}
 
@@ -1078,7 +1078,7 @@ XXR_common:
 					pbuffer_tmp = &xxr_para_tmp->smask;
 					xxr_para_tmp->data_mask |= XXR_SMASK;
 				} else {
-					LOG_ERROR("unknow parameter: %s", argus[i]);
+					LOG_ERROR("unknown parameter: %s", argus[i]);
 					return ERROR_FAIL;
 				}
 				if (ERROR_OK !=
@@ -1524,7 +1524,7 @@ XXR_common:
 				svf_para.trst_mode = i_tmp;
 				LOG_DEBUG("\ttrst_mode = %s", svf_trst_mode_name[svf_para.trst_mode]);
 			} else {
-				LOG_ERROR("can not accpet TRST command if trst_mode is ABSENT");
+				LOG_ERROR("can not accept TRST command if trst_mode is ABSENT");
 				return ERROR_FAIL;
 			}
 			break;

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/linuxgpiod.c | 40 +++++++++++++++++++++++++++++++++++++++-
 src/svf/svf.c                 | 12 ++++++------
 tcl/interface/dln-2-gpiod.cfg |  2 ++
 3 files changed, 47 insertions(+), 7 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1359-g02ecd452c

From: OpenOCD-Gerrit <ope...@us...> - 2020-07-26 19:15:36

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       via  29a899f3d27f6a18819a6f26c6e3d2c6e2d684c3 (commit)
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- Log -----------------------------------------------------------------
commit 02ecd452c219a98b9da910b97755c5a326ab4cad
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Jul 13 00:37:17 2020 +0200

    flash: fix minor typo s/fifo's/fifos/
    
    Change-Id: I21feee50377b13cd0d48749c19abb12d499fe199
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5769
    Tested-by: jenkins

diff --git a/src/flash/nor/mrvlqspi.c b/src/flash/nor/mrvlqspi.c
index f21cc6ff0..3293e6129 100644
--- a/src/flash/nor/mrvlqspi.c
+++ b/src/flash/nor/mrvlqspi.c
@@ -328,7 +328,7 @@ static int mrvlqspi_flash_busy_status(struct flash_bank *bank, int timeout)
 	uint8_t val;
 	int retval;
 
-	/* Flush read/write fifo's */
+	/* Flush read/write fifos */
 	retval = mrvlqspi_fifo_flush(bank, FIFO_FLUSH_TIMEOUT);
 	if (retval != ERROR_OK)
 		return retval;
@@ -379,7 +379,7 @@ static int mrvlqspi_set_write_status(struct flash_bank *bank, bool mode)
 	int retval;
 	uint32_t instr;
 
-	/* Flush read/write fifo's */
+	/* Flush read/write fifos */
 	retval = mrvlqspi_fifo_flush(bank, FIFO_FLUSH_TIMEOUT);
 	if (retval != ERROR_OK)
 		return retval;
@@ -417,7 +417,7 @@ static int mrvlqspi_read_id(struct flash_bank *bank, uint32_t *id)
 
 	LOG_DEBUG("Getting ID");
 
-	/* Flush read/write fifo's */
+	/* Flush read/write fifos */
 	retval = mrvlqspi_fifo_flush(bank, FIFO_FLUSH_TIMEOUT);
 	if (retval != ERROR_OK)
 		return retval;
@@ -779,7 +779,7 @@ int mrvlqspi_flash_read(struct flash_bank *bank, uint8_t *buffer,
 		return ERROR_FLASH_BANK_NOT_PROBED;
 	}
 
-	/* Flush read/write fifo's */
+	/* Flush read/write fifos */
 	retval = mrvlqspi_fifo_flush(bank, FIFO_FLUSH_TIMEOUT);
 	if (retval != ERROR_OK)
 		return retval;

commit 29a899f3d27f6a18819a6f26c6e3d2c6e2d684c3
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Jul 13 00:32:49 2020 +0200

    contrib: fix minor typos
    
    While there, replace s/return(0)/return 0/ that causes checkpatch
    to fail.
    
    Change-Id: I5ad54cffca629475563c471114a9f77301a9e4f8
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5768
    Tested-by: jenkins

diff --git a/contrib/coresight-trace.txt b/contrib/coresight-trace.txt
index c093c205a..517119b6f 100644
--- a/contrib/coresight-trace.txt
+++ b/contrib/coresight-trace.txt
@@ -62,7 +62,7 @@ Clearly some of that data would be valuable for interactive debugging.
 +In any case, OpenOCD is not currently GUI-oriented.  Accordingly, we now
 +expect any such graphics to come from postprocessing.
 
- measurments for RTOS event timings should also be easy to collect.
+ measurements for RTOS event timings should also be easy to collect.
 +Examples include context and message switch times, as well as times
 for application interactions.
 +
diff --git a/contrib/cross-build.sh b/contrib/cross-build.sh
index 74ab0f4f5..d508bed47 100755
--- a/contrib/cross-build.sh
+++ b/contrib/cross-build.sh
@@ -16,7 +16,7 @@
 # This script is probably more useful as a reference than as a complete build
 # tool but for some configurations it may be usable as-is. It only cross-
 # builds libusb-1.0 from source, but the script can be extended to build other
-# prerequisities in a similar manner.
+# prerequisites in a similar manner.
 #
 # Usage:
 # export LIBUSB1_SRC=/path/to/libusb-1.0
diff --git a/contrib/itmdump.c b/contrib/itmdump.c
index 896389416..24aa34f32 100644
--- a/contrib/itmdump.c
+++ b/contrib/itmdump.c
@@ -325,7 +325,7 @@ static void show_timestamp(FILE *f, int c)
 		delayed = true;
 		break;
 	case 0xf:
-		label = ", packet and timetamp delayed";
+		label = ", packet and timestamp delayed";
 		delayed = true;
 		break;
 	}
diff --git a/contrib/loaders/flash/at91sam7x/crt.s b/contrib/loaders/flash/at91sam7x/crt.s
index 2e434bbe7..94ed66d73 100644
--- a/contrib/loaders/flash/at91sam7x/crt.s
+++ b/contrib/loaders/flash/at91sam7x/crt.s
@@ -46,7 +46,7 @@
    ARM_MODE_SVC   = 0x13      /* Supervisor Interrupts Mode                   */
    ARM_MODE_ABORT = 0x17      /* Abort Processing memory Faults Mode          */
    ARM_MODE_UNDEF = 0x1B      /* Undefined Instructions Mode                  */
-   ARM_MODE_SYS   = 0x1F      /* System Running in Priviledged Operating Mode */
+   ARM_MODE_SYS   = 0x1F      /* System Running in Privileged Operating Mode  */
    ARM_MODE_MASK  = 0x1F
 
    I_BIT          = 0x80      /* disable IRQ when I bit is set */
diff --git a/contrib/loaders/flash/at91sam7x/dcc.c b/contrib/loaders/flash/at91sam7x/dcc.c
index 04a7f7a4d..a5c32e7e6 100644
--- a/contrib/loaders/flash/at91sam7x/dcc.c
+++ b/contrib/loaders/flash/at91sam7x/dcc.c
@@ -39,7 +39,7 @@ int dcc_wr(uint32 data)
 
 	do {
 		asm volatile ("mrc p14, 0, %0, C0, C0" : "=r" (dcc_reg) :);
-		/* operation controled by master, cancel operation
+		/* operation controlled by master, cancel operation
 			 upon reception of data for immediate response */
 		if (dcc_reg&1) return -1;
 	} while (dcc_reg&2);
diff --git a/contrib/loaders/flash/at91sam7x/main.c b/contrib/loaders/flash/at91sam7x/main.c
index 831e03f14..47c944082 100644
--- a/contrib/loaders/flash/at91sam7x/main.c
+++ b/contrib/loaders/flash/at91sam7x/main.c
@@ -101,5 +101,5 @@ int main (void)
 		}
 	}
 
-	return(0); /* we shall never get here, just to supress compiler warning */
+	return 0; /* we shall never get here, just to suppress compiler warning */
 }
diff --git a/contrib/loaders/flash/at91sam7x/ocl.h b/contrib/loaders/flash/at91sam7x/ocl.h
index ef30c33f4..bd8a5f7a0 100644
--- a/contrib/loaders/flash/at91sam7x/ocl.h
+++ b/contrib/loaders/flash/at91sam7x/ocl.h
@@ -21,7 +21,7 @@
 /* command/response mask */
 #define OCL_CMD_MASK 0xFFFF0000L
 
-/* commads */
+/* commands */
 #define OCL_FLASH_BLOCK 0x0CFB0000L
 #define OCL_ERASE_BLOCK 0x0CEB0000L
 #define OCL_ERASE_ALL 0x0CEA0000L
diff --git a/contrib/loaders/flash/cc26xx/flash.h b/contrib/loaders/flash/cc26xx/flash.h
index ec1c24fc5..dd0a3745a 100644
--- a/contrib/loaders/flash/cc26xx/flash.h
+++ b/contrib/loaders/flash/cc26xx/flash.h
@@ -108,7 +108,7 @@ extern "C"
 
 /******************************************************************************
 *
-* Define for the clock frequencey input to the flash module in number of MHz
+* Define for the clock frequency input to the flash module in number of MHz
 *
 ******************************************************************************/
 #define FLASH_MODULE_CLK_FREQ 48
@@ -279,7 +279,7 @@ static inline uint32_t flash_check_fsm_for_ready(void)
 * This function will erase the specified flash sector. The function will
 * not return until the flash sector has been erased or an error condition
 * occurred. If flash top sector is erased the function will program the
-* the device security data bytes with default values. The device security
+* device security data bytes with default values. The device security
 * data located in the customer configuration area of the flash top sector,
 * must have valid values at all times. These values affect the configuration
 * of the device during boot.
@@ -305,7 +305,7 @@ extern uint32_t flash_sector_erase(uint32_t sector_address);
 *
 * This function will erase all unprotected flash sectors. The function will
 * not return until the flash sectors has been erased or an error condition
-* occurred. Since the flash top sector is erased the function will program the
+* occurred. Since the flash top sector is erased the function will program
 * the device security data bytes with default values. The device security
 * data located in the customer configuration area of the flash top sector,
 * must have valid values at all times. These values affect the configuration
diff --git a/contrib/loaders/flash/cc26xx/startup.c b/contrib/loaders/flash/cc26xx/startup.c
index 70fd83650..53d8ea8c7 100644
--- a/contrib/loaders/flash/cc26xx/startup.c
+++ b/contrib/loaders/flash/cc26xx/startup.c
@@ -52,7 +52,7 @@ const uint32_t stack_pntr = (uint32_t)stack + sizeof(stack);
 
 /******************************************************************************
 *
-* The following are constructs created by the linker indicating where the
+* The following are constructs created by the linker indicating where
 * the "bss" and "ebss" segments reside in memory.
 *
 ******************************************************************************/
diff --git a/contrib/loaders/flash/mrvlqspi_write.S b/contrib/loaders/flash/mrvlqspi_write.S
index 064192c9c..e1088e38d 100644
--- a/contrib/loaders/flash/mrvlqspi_write.S
+++ b/contrib/loaders/flash/mrvlqspi_write.S
@@ -81,7 +81,7 @@ find_next_page_boundary:
 	/* If we have not reached the next page boundary after the target address, keep going */
 	bls 	find_next_page_boundary
 write_enable:
-	/* Flush read/write fifo's */
+	/* Flush read/write fifos */
 	bl 	flush_fifo
 
 	/* Instruction byte 1 */
@@ -134,7 +134,7 @@ write_wait:
 	bl 	stop_tx		/* Otherwise, end the command and keep going w/ the next page */
 	add 	r10, r4 	/* Move up the end-of-page address by the page size*/
 check_flash_busy:		/* Wait for the flash to finish the previous page write */
-	/* Flush read/write fifo's */
+	/* Flush read/write fifos */
 	bl 	flush_fifo
 	/* Instruction byte 1 */
 	movs 	r8, #0x1
diff --git a/contrib/loaders/flash/msp432/driverlib.c b/contrib/loaders/flash/msp432/driverlib.c
index a4f541619..ac6dfd454 100644
--- a/contrib/loaders/flash/msp432/driverlib.c
+++ b/contrib/loaders/flash/msp432/driverlib.c
@@ -367,7 +367,7 @@ bool pcm_shutdown_device(uint32_t shutdown_mode)
 	uint32_t shutdown_mode_bits = (shutdown_mode == PCM_LPM45) ?
 		PCM_CTL0_LPMR_12 : PCM_CTL0_LPMR_10;
 
-	/* If a power transition is occuring, return false */
+	/* If a power transition is occurring, return false */
 	if (BITBAND_PERI(PCM->CTL1, PCM_CTL1_PMR_BUSY_OFS))
 		return false;
 
diff --git a/contrib/loaders/flash/msp432/startup_msp432e4.c b/contrib/loaders/flash/msp432/startup_msp432e4.c
index 8adce8356..494da46e7 100644
--- a/contrib/loaders/flash/msp432/startup_msp432e4.c
+++ b/contrib/loaders/flash/msp432/startup_msp432e4.c
@@ -71,9 +71,9 @@ void (* const intr_vectors[])(void) __attribute__((section(".intvecs"))) = {
 };
 
 /*
- * The following are constructs created by the linker, indicating where the
- * the "data" and "bss" segments reside in memory.  The initializers for the
- * for the "data" segment resides immediately following the "text" segment.
+ * The following are constructs created by the linker, indicating where
+ * the "data" and "bss" segments reside in memory.  The initializers for
+ * the "data" segment resides immediately following the "text" segment.
  */
 extern uint32_t __bss_start__;
 extern uint32_t __bss_end__;
diff --git a/contrib/loaders/flash/msp432/startup_msp432p4.c b/contrib/loaders/flash/msp432/startup_msp432p4.c
index ed7ea10a9..09103b0e4 100644
--- a/contrib/loaders/flash/msp432/startup_msp432p4.c
+++ b/contrib/loaders/flash/msp432/startup_msp432p4.c
@@ -71,9 +71,9 @@ void (* const intr_vectors[])(void) __attribute__((section(".intvecs"))) = {
 };
 
 /*
- * The following are constructs created by the linker, indicating where the
- * the "data" and "bss" segments reside in memory.  The initializers for the
- * for the "data" segment resides immediately following the "text" segment.
+ * The following are constructs created by the linker, indicating where
+ * the "data" and "bss" segments reside in memory.  The initializers for
+ * the "data" segment resides immediately following the "text" segment.
  */
 extern uint32_t __bss_start__;
 extern uint32_t __bss_end__;
diff --git a/contrib/loaders/flash/stm32/stm32h7x.S b/contrib/loaders/flash/stm32/stm32h7x.S
index 99e416753..8ef42a4cf 100644
--- a/contrib/loaders/flash/stm32/stm32h7x.S
+++ b/contrib/loaders/flash/stm32/stm32h7x.S
@@ -25,7 +25,7 @@
  * Code limitations:
  * The workarea must have size multiple of 4 bytes, since R/W
  * operations are all at 32 bits.
- * The workarea must be big enough to contain rp, wp and data, thus the minumum
+ * The workarea must be big enough to contain rp, wp and data, thus the minimum
  * workarea size is: min_wa_size = sizeof(rp, wp, data) = 4 + 4 + sizeof(data).
  *  - for 0x450 devices: sizeof(data) = 32 bytes, thus min_wa_size = 40 bytes.
  *  - for 0x480 devices: sizeof(data) = 16 bytes, thus min_wa_size = 24 bytes.
@@ -78,7 +78,7 @@ wait_fifo:
 	str		r7, [r5, #STM32_FLASH_CR_OFFSET]
 
 	mov		r8, #4
-	udiv	r8, r4, r8			/* number of words is size of write word devided by 4*/
+	udiv	r8, r4, r8			/* number of words is size of write word divided by 4*/
 write_flash:
 	dsb
 	ldr		r7, [r6], #0x04		/* read one word from src, increment ptr */
diff --git a/contrib/loaders/flash/str7x.s b/contrib/loaders/flash/str7x.s
index a163ee674..cd19013be 100644
--- a/contrib/loaders/flash/str7x.s
+++ b/contrib/loaders/flash/str7x.s
@@ -51,7 +51,7 @@ busy:
 	tsteq	r4, #0x100			/* write protection set */
 	bne		exit
 	add		r1, r1, #0x8			/* next 8 bytes */
-	subs	r3, r3, #1				/* decremment dword count */
+	subs	r3, r3, #1				/* decrement dword count */
 	bne		write
 exit:
 	b		exit
diff --git a/contrib/loaders/flash/str9x.s b/contrib/loaders/flash/str9x.s
index 4daac7731..279b17503 100644
--- a/contrib/loaders/flash/str9x.s
+++ b/contrib/loaders/flash/str9x.s
@@ -48,7 +48,7 @@ busy:
 	strh	r5, [r4, #0]
 	tst		r3, #0x12
 	bne		exit
-	subs 	r2, r2, #1			/* decremment word count */
+	subs 	r2, r2, #1			/* decrement word count */
 	bne 	write
 exit:
 	bkpt	#0
diff --git a/contrib/rpc_examples/ocd_rpc_example.py b/contrib/rpc_examples/ocd_rpc_example.py
index 9d17e7695..3470d848b 100755
--- a/contrib/rpc_examples/ocd_rpc_example.py
+++ b/contrib/rpc_examples/ocd_rpc_example.py
@@ -125,7 +125,7 @@ if __name__ == "__main__":
         show(ocd.send("capture { echo \"echo says hi!\" }")[:-1])
         show(ocd.send("capture \"halt\"")[:-1])
 
-        # Read the first few words at the RAM region (put starting adress of RAM
+        # Read the first few words at the RAM region (put starting address of RAM
         # region into 'addr')
         addr = 0x10000000
 

-----------------------------------------------------------------------

Summary of changes:
 contrib/coresight-trace.txt                     | 2 +-
 contrib/cross-build.sh                          | 2 +-
 contrib/itmdump.c                               | 2 +-
 contrib/loaders/flash/at91sam7x/crt.s           | 2 +-
 contrib/loaders/flash/at91sam7x/dcc.c           | 2 +-
 contrib/loaders/flash/at91sam7x/main.c          | 2 +-
 contrib/loaders/flash/at91sam7x/ocl.h           | 2 +-
 contrib/loaders/flash/cc26xx/flash.h            | 6 +++---
 contrib/loaders/flash/cc26xx/startup.c          | 2 +-
 contrib/loaders/flash/mrvlqspi_write.S          | 4 ++--
 contrib/loaders/flash/msp432/driverlib.c        | 2 +-
 contrib/loaders/flash/msp432/startup_msp432e4.c | 6 +++---
 contrib/loaders/flash/msp432/startup_msp432p4.c | 6 +++---
 contrib/loaders/flash/stm32/stm32h7x.S          | 4 ++--
 contrib/loaders/flash/str7x.s                   | 2 +-
 contrib/loaders/flash/str9x.s                   | 2 +-
 contrib/rpc_examples/ocd_rpc_example.py         | 2 +-
 src/flash/nor/mrvlqspi.c                        | 8 ++++----
 18 files changed, 29 insertions(+), 29 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1357-g4c8753a83

From: OpenOCD-Gerrit <ope...@us...> - 2020-07-26 19:15:07

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  4c8753a83c96d8911140b28d893d9f9c0424dd97 (commit)
       via  890048eec4f955c43284626e9c8841441e85f4fc (commit)
       via  fbaa134edaa186345ee5dd7c884c58b013525d2e (commit)
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- Log -----------------------------------------------------------------
commit 4c8753a83c96d8911140b28d893d9f9c0424dd97
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jul 12 23:40:41 2020 +0200

    jtag: fix minor typos
    
    Change-Id: I3a3370db438f8fd045fb22e7c9fff4e83794a3b7
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5767
    Tested-by: jenkins

diff --git a/src/jtag/drivers/OpenULINK/include/io.h b/src/jtag/drivers/OpenULINK/include/io.h
index a4a8b8acd..497c235a2 100644
--- a/src/jtag/drivers/OpenULINK/include/io.h
+++ b/src/jtag/drivers/OpenULINK/include/io.h
@@ -74,7 +74,7 @@
 #define PIN_RXD0      PINC0
 #define PIN_TXD0      OUTC1
 #define PIN_RESET_2   PINC2
-/* PC3 Not Connecte */
+/* PC3 Not Connected */
 /* PC4 Not Connected */
 #define PIN_RTCK      PINC5
 #define PIN_WR        OUTC6
diff --git a/src/jtag/drivers/OpenULINK/src/jtag.c b/src/jtag/drivers/OpenULINK/src/jtag.c
index 413945566..ecf98a08c 100644
--- a/src/jtag/drivers/OpenULINK/src/jtag.c
+++ b/src/jtag/drivers/OpenULINK/src/jtag.c
@@ -208,7 +208,7 @@ void jtag_slow_scan_in(uint8_t out_offset, uint8_t in_offset)
  *
  * Data stored in EP2 OUT buffer is shifted into the JTAG chain via TDI, TDO
  * data is not sampled.
- * The TAP-FSM state is alyways left in the PAUSE-DR/PAUSE-IR state.
+ * The TAP-FSM state is always left in the PAUSE-DR/PAUSE-IR state.
  *
  * Maximum achievable TCK frequency is 142 kHz for ULINK clocked at 24 MHz.
  *
@@ -283,7 +283,7 @@ void jtag_scan_out(uint8_t out_offset)
  *
  * Data stored in EP2 OUT buffer is shifted into the JTAG chain via TDI, TDO
  * data is not sampled.
- * The TAP-FSM state is alyways left in the PAUSE-DR/PAUSE-IR state.
+ * The TAP-FSM state is always left in the PAUSE-DR/PAUSE-IR state.
  *
  * Maximum achievable TCK frequency is 97 kHz for ULINK clocked at 24 MHz.
  *
@@ -368,7 +368,7 @@ void jtag_slow_scan_out(uint8_t out_offset)
  *
  * Data stored in EP2 OUT buffer is shifted into the JTAG chain via TDI, TDO
  * data is sampled and stored in the EP2 IN buffer.
- * The TAP-FSM state is alyways left in the PAUSE-DR/PAUSE-IR state.
+ * The TAP-FSM state is always left in the PAUSE-DR/PAUSE-IR state.
  *
  * Maximum achievable TCK frequency is 100 kHz for ULINK clocked at 24 MHz.
  *
@@ -460,7 +460,7 @@ void jtag_scan_io(uint8_t out_offset, uint8_t in_offset)
  *
  * Data stored in EP2 OUT buffer is shifted into the JTAG chain via TDI, TDO
  * data is sampled and stored in the EP2 IN buffer.
- * The TAP-FSM state is alyways left in the PAUSE-DR/PAUSE-IR state.
+ * The TAP-FSM state is always left in the PAUSE-DR/PAUSE-IR state.
  *
  * Maximum achievable TCK frequency is 78 kHz for ULINK clocked at 24 MHz.
  *
@@ -562,7 +562,7 @@ void jtag_slow_scan_io(uint8_t out_offset, uint8_t in_offset)
  *
  * Maximum achievable TCK frequency is 375 kHz for ULINK clocked at 24 MHz.
  *
- * @param count number of TCK clock cyclces to generate.
+ * @param count number of TCK clock cycles to generate.
  */
 void jtag_clock_tck(uint16_t count)
 {
@@ -578,9 +578,9 @@ void jtag_clock_tck(uint16_t count)
 /**
  * Generate TCK clock cycles at variable frequency.
  *
- * Maximum achieveable TCK frequency is 166.6 kHz for ULINK clocked at 24 MHz.
+ * Maximum achievable TCK frequency is 166.6 kHz for ULINK clocked at 24 MHz.
  *
- * @param count number of TCK clock cyclces to generate.
+ * @param count number of TCK clock cycles to generate.
  */
 void jtag_slow_clock_tck(uint16_t count)
 {
diff --git a/src/jtag/drivers/OpenULINK/src/protocol.c b/src/jtag/drivers/OpenULINK/src/protocol.c
index 901f52482..f8f84ed48 100644
--- a/src/jtag/drivers/OpenULINK/src/protocol.c
+++ b/src/jtag/drivers/OpenULINK/src/protocol.c
@@ -86,7 +86,7 @@ bool execute_command(void)
 
 	/* Most commands do not transfer IN data. To save code space, we write 0 to
 	 * usb_in_bytecount here, then modify it in the switch statement below where
-	 * neccessary */
+	 * necessary */
 	usb_in_bytecount = 0;
 
 	switch (OUT2BUF[cmd_id_index] /* Command ID */) {
diff --git a/src/jtag/drivers/OpenULINK/src/usb.c b/src/jtag/drivers/OpenULINK/src/usb.c
index fb77f6482..032b23b57 100644
--- a/src/jtag/drivers/OpenULINK/src/usb.c
+++ b/src/jtag/drivers/OpenULINK/src/usb.c
@@ -38,7 +38,7 @@ volatile bool EP2_in;
 volatile __xdata __at 0x7FE8 struct setup_data setup_data;
 
 /* Define number of endpoints (except Control Endpoint 0) in a central place.
- * Be sure to include the neccessary endpoint descriptors! */
+ * Be sure to include the necessary endpoint descriptors! */
 #define NUM_ENDPOINTS 2
 
 __code struct usb_device_descriptor device_descriptor = {
diff --git a/src/jtag/drivers/bitq.c b/src/jtag/drivers/bitq.c
index 9b4eeed72..2241c13a3 100644
--- a/src/jtag/drivers/bitq.c
+++ b/src/jtag/drivers/bitq.c
@@ -245,7 +245,7 @@ int bitq_execute_queue(void)
 		case JTAG_TLR_RESET:
 			LOG_DEBUG_IO("statemove end in %i", cmd->cmd.statemove->end_state);
 			bitq_end_state(cmd->cmd.statemove->end_state);
-			bitq_state_move(tap_get_end_state());   /* uncoditional TAP move */
+			bitq_state_move(tap_get_end_state());   /* unconditional TAP move */
 			break;
 
 		case JTAG_PATHMOVE:
diff --git a/src/jtag/drivers/buspirate.c b/src/jtag/drivers/buspirate.c
index 020c4ce39..a6ffe35f5 100644
--- a/src/jtag/drivers/buspirate.c
+++ b/src/jtag/drivers/buspirate.c
@@ -1049,7 +1049,7 @@ static void buspirate_jtag_reset(int fd)
 	tmp[0] = 0x00; /* exit OCD1 mode */
 	buspirate_serial_write(fd, tmp, 1);
 	usleep(10000);
-	/* We ignore the return value here purposly, nothing we can do */
+	/* We ignore the return value here on purpose, nothing we can do */
 	buspirate_serial_read(fd, tmp, 5);
 	if (strncmp((char *)tmp, "BBIO1", 5) == 0) {
 		tmp[0] = 0x0F; /*  reset BP */
diff --git a/src/jtag/drivers/cmsis_dap_usb.c b/src/jtag/drivers/cmsis_dap_usb.c
index d87d0c9a5..efd039af6 100644
--- a/src/jtag/drivers/cmsis_dap_usb.c
+++ b/src/jtag/drivers/cmsis_dap_usb.c
@@ -1003,7 +1003,7 @@ static int cmsis_dap_init(void)
 		LOG_INFO("CMSIS-DAP: Interface Initialised (JTAG)");
 	}
 
-	/* Be conservative and supress submiting multiple HID requests
+	/* Be conservative and suppress submitting multiple HID requests
 	 * until we get packet count info from the adaptor */
 	cmsis_dap_handle->packet_count = 1;
 	pending_queue_len = 12;
diff --git a/src/jtag/drivers/jlink.c b/src/jtag/drivers/jlink.c
index 1baf3454e..91ecf56e1 100644
--- a/src/jtag/drivers/jlink.c
+++ b/src/jtag/drivers/jlink.c
@@ -1807,7 +1807,7 @@ COMMAND_HANDLER(jlink_handle_emucom_read_command)
 		return ERROR_FAIL;
 	} else if (ret == JAYLINK_ERR_DEV_NOT_AVAILABLE) {
 		LOG_ERROR("Channel is not available for the requested amount of data. "
-			"%" PRIu32 " bytes are avilable.", length);
+			"%" PRIu32 " bytes are available.", length);
 		free(buf);
 		return ERROR_FAIL;
 	} else if (ret != JAYLINK_OK) {
diff --git a/src/jtag/drivers/jtag_vpi.c b/src/jtag/drivers/jtag_vpi.c
index a5a95a5a3..a5f441cc7 100644
--- a/src/jtag/drivers/jtag_vpi.c
+++ b/src/jtag/drivers/jtag_vpi.c
@@ -227,7 +227,7 @@ static int jtag_vpi_reset(int trst, int srst)
  * @bits: TMS bits to be written (bit0, bit1 .. bitN)
  * @nb_bits: number of TMS bits (between 1 and 8)
  *
- * Write a serie of TMS transitions, where each transition consists in :
+ * Write a series of TMS transitions, where each transition consists in :
  *  - writing out TCK=0, TMS=<new_state>, TDI=<???>
  *  - writing out TCK=1, TMS=<new_state>, TDI=<???> which triggers the transition
  * The function ensures that at the end of the sequence, the clock (TCK) is put
@@ -253,7 +253,7 @@ static int jtag_vpi_tms_seq(const uint8_t *bits, int nb_bits)
  * jtag_vpi_path_move - ask a TMS sequence transition to JTAG
  * @cmd: path transition
  *
- * Write a serie of TMS transitions, where each transition consists in :
+ * Write a series of TMS transitions, where each transition consists in :
  *  - writing out TCK=0, TMS=<new_state>, TDI=<???>
  *  - writing out TCK=1, TMS=<new_state>, TDI=<???> which triggers the transition
  * The function ensures that at the end of the sequence, the clock (TCK) is put
@@ -392,7 +392,7 @@ static int jtag_vpi_clock_tms(int tms)
  *
  * Launch a JTAG IR-scan or DR-scan
  *
- * Returns ERROR_OK if OK, ERROR_xxx if a read/write error occured.
+ * Returns ERROR_OK if OK, ERROR_xxx if a read/write error occurred.
  */
 static int jtag_vpi_scan(struct scan_command *cmd)
 {
@@ -558,7 +558,7 @@ static int jtag_vpi_init(void)
 	serv_addr.sin_addr.s_addr = inet_addr(server_address);
 
 	if (serv_addr.sin_addr.s_addr == INADDR_NONE) {
-		LOG_ERROR("inet_addr error occured");
+		LOG_ERROR("inet_addr error occurred");
 		return ERROR_FAIL;
 	}
 
@@ -569,7 +569,7 @@ static int jtag_vpi_init(void)
 	}
 
 	if (serv_addr.sin_addr.s_addr == htonl(INADDR_LOOPBACK)) {
-		/* This increases performance drematically for local
+		/* This increases performance dramatically for local
 		 * connections, which is the most likely arrangement
 		 * for a VPI connection. */
 		setsockopt(sockfd, IPPROTO_TCP, TCP_NODELAY, (char *)&flag, sizeof(int));
diff --git a/src/jtag/drivers/kitprog.c b/src/jtag/drivers/kitprog.c
index efb8da2cd..4f38d195d 100644
--- a/src/jtag/drivers/kitprog.c
+++ b/src/jtag/drivers/kitprog.c
@@ -606,7 +606,7 @@ static int kitprog_generic_acquire(void)
 		for (uint8_t j = 0; j < sizeof(devices) && acquire_count == i; j++) {
 			retval = kitprog_acquire_psoc(devices[j], ACQUIRE_MODE_RESET, 3);
 			if (retval != ERROR_OK) {
-				LOG_DEBUG("Aquisition function failed for device 0x%02x.", devices[j]);
+				LOG_DEBUG("Acquisition function failed for device 0x%02x.", devices[j]);
 				return retval;
 			}
 
@@ -746,7 +746,7 @@ static int kitprog_swd_run_queue(void)
 		 * size (64 bytes) as required by the USB specification.
 		 * Therefore libusb would wait for continuation of transmission.
 		 * Workaround: Limit bulk read size to expected number of bytes
-		 * for problematic tranfer sizes. Otherwise use the maximum buffer
+		 * for problematic transfer sizes. Otherwise use the maximum buffer
 		 * size here because the KitProg sometimes doesn't like bulk reads
 		 * of fewer than 62 bytes. (?!?!)
 		 */
diff --git a/src/jtag/drivers/osbdm.c b/src/jtag/drivers/osbdm.c
index dc236660e..5c43d3244 100644
--- a/src/jtag/drivers/osbdm.c
+++ b/src/jtag/drivers/osbdm.c
@@ -274,7 +274,7 @@ static int osbdm_swap(struct osbdm *osbdm, void *tms, void *tdi,
 		return ERROR_FAIL;
 	}
 
-	/* Copy TDO responce
+	/* Copy TDO response
 	 */
 	uint8_t *buffer = osbdm->buffer + 4;
 	for (int bit_idx = 0; bit_idx < length; ) {
diff --git a/src/jtag/drivers/presto.c b/src/jtag/drivers/presto.c
index 3849a27f9..4046b22dd 100644
--- a/src/jtag/drivers/presto.c
+++ b/src/jtag/drivers/presto.c
@@ -351,7 +351,7 @@ static int presto_bitq_out(int tms, int tdi, int tdo_req)
 	unsigned char cmd;
 
 	if (presto->jtag_tck == 0)
-		presto_sendbyte(0xA4);	/* LED idicator - JTAG active */
+		presto_sendbyte(0xA4);	/* LED indicator - JTAG active */
 	else if (presto->jtag_speed == 0 && !tdo_req && tms == presto->jtag_tms) {
 		presto->jtag_tdi_data |= (tdi != 0) << presto->jtag_tdi_count;
 
@@ -392,7 +392,7 @@ static int presto_bitq_flush(void)
 	presto_tdi_flush();
 	presto_tck_idle();
 
-	presto_sendbyte(0xA0);	/* LED idicator - JTAG idle */
+	presto_sendbyte(0xA0);	/* LED indicator - JTAG idle */
 
 	return presto_flush();
 }
diff --git a/src/jtag/drivers/rlink.c b/src/jtag/drivers/rlink.c
index e0533997c..284356466 100644
--- a/src/jtag/drivers/rlink.c
+++ b/src/jtag/drivers/rlink.c
@@ -564,7 +564,7 @@ static struct {
 } dtc_queue;
 
 /*
- * The tap state queue is for accumulating TAP state changes wiithout needlessly
+ * The tap state queue is for accumulating TAP state changes without needlessly
  * flushing the dtc_queue.  When it fills or is run, it adds the accumulated bytes to
  * the dtc_queue.
  */
@@ -1358,7 +1358,7 @@ static int rlink_execute_queue(void)
 		retval = tmp_retval;
 
 #ifndef AUTOMATIC_BUSY_LED
-	/* turn LED onff */
+	/* turn LED off */
 	ep1_generic_commandl(pHDev, 2,
 		EP1_CMD_SET_PORTD_LEDS,
 		~0
diff --git a/src/jtag/drivers/rshim.c b/src/jtag/drivers/rshim.c
index c718af5d2..246e931c2 100644
--- a/src/jtag/drivers/rshim.c
+++ b/src/jtag/drivers/rshim.c
@@ -409,7 +409,7 @@ static int rshim_connect(struct adiv5_dap *dap)
 	}
 
 	/*
-	 * Set read/write operation via the device file. Funtion pointers
+	 * Set read/write operation via the device file. Function pointers
 	 * are used here so more ways like remote accessing via socket could
 	 * be added later.
 	 */
diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c
index 72975d5ac..6ae9e3e81 100644
--- a/src/jtag/drivers/stlink_usb.c
+++ b/src/jtag/drivers/stlink_usb.c
@@ -218,7 +218,7 @@ struct stlink_usb_handle_s {
 	uint32_t address
 
 	STLINK_SWIM_RESET
-	send syncronization seq (16us low, response 64 clocks low)
+	send synchronization seq (16us low, response 64 clocks low)
 */
 #define STLINK_SWIM_ENTER                  0x00
 #define STLINK_SWIM_EXIT                   0x01
@@ -1465,7 +1465,7 @@ static int stlink_swim_status(void *handle)
 }
 /*
 	the purpose of this function is unknown...
-	capabilites? anyway for swim v6 it returns
+	capabilities? anyway for swim v6 it returns
 	0001020600000000
 */
 __attribute__((unused))
@@ -1559,7 +1559,7 @@ static int stlink_swim_generate_rst(void *handle)
 }
 
 /*
-	send resyncronize sequence
+	send resynchronize sequence
 	swim is pulled low for 16us
 	reply is 64 clks low
 */
diff --git a/src/jtag/drivers/sysfsgpio.c b/src/jtag/drivers/sysfsgpio.c
index e16076942..78a4c5b77 100644
--- a/src/jtag/drivers/sysfsgpio.c
+++ b/src/jtag/drivers/sysfsgpio.c
@@ -29,7 +29,7 @@
  *
  * A gpio is required for tck, tms, tdi and tdo. One or both of srst and trst
  * must be also be specified. The required jtag gpios are specified via the
- * sysfsgpio_jtag_nums command or the relevant sysfsgpio_XXX_num commang.
+ * sysfsgpio_jtag_nums command or the relevant sysfsgpio_XXX_num commands.
  * The srst and trst gpios are set via the sysfsgpio_srst_num and
  * sysfsgpio_trst_num respectively. GPIO numbering follows the kernel
  * convention of starting from 0.
diff --git a/src/jtag/drivers/ulink.c b/src/jtag/drivers/ulink.c
index 242c04fe3..68249dcfe 100644
--- a/src/jtag/drivers/ulink.c
+++ b/src/jtag/drivers/ulink.c
@@ -1271,7 +1271,7 @@ int ulink_append_test_cmd(struct ulink *device)
  *   1. Maximum possible frequency without any artificial delay
  *   2. Variable frequency with artificial linear delay loop
  *
- * To set the ULINK to maximum frequency, it is only neccessary to use the
+ * To set the ULINK to maximum frequency, it is only necessary to use the
  * corresponding command IDs. To set the ULINK to a lower frequency, the
  * delay loop top values have to be calculated first. Then, a
  * CMD_CONFIGURE_TCK_FREQ command needs to be sent to the ULINK device.
diff --git a/src/jtag/drivers/usb_blaster/README.CheapClone b/src/jtag/drivers/usb_blaster/README.CheapClone
index 983a441a1..bd048d5ca 100644
--- a/src/jtag/drivers/usb_blaster/README.CheapClone
+++ b/src/jtag/drivers/usb_blaster/README.CheapClone
@@ -47,11 +47,11 @@ Pinout
 
 Throughput considerations
 =========================
-Mesurements on a scope reveal that :
- - for bitbang mode, the throughtput is 56.5 kbits/s
-   (as each clock transition is mesured at 17.7us)
+Measurements on a scope reveal that :
+ - for bitbang mode, the throughput is 56.5 kbits/s
+   (as each clock transition is measured at 17.7us)
  - for byteshift mode, the throughput is 107.7 kbits/s
-   (as 63 bits TDI transmission is mesured in 585 us)
+   (as 63 bits TDI transmission is measured in 585 us)
 
 Let's suppose that to upload a 32 bits value, it is necessary to :
  - move from IDLE to DR-SHIFT : 3 bitbang (3 TMS transitions)
@@ -62,8 +62,8 @@ So for this 32 bits of data, the time would be :
  = 53.1us + 222us + 88.5us
  = 363us
 
-Throughtput in bit/s: 32 * (1 / 363E-6) = 88000 bits/s
-Throughtput in bytes/s: 11kBytes/s
+Throughput in bit/s: 32 * (1 / 363E-6) = 88000 bits/s
+Throughput in bytes/s: 11kBytes/s
 
 Conclusion
 ==========
diff --git a/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c b/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c
index e2556cec0..f8ff66e2f 100644
--- a/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c
+++ b/src/jtag/drivers/usb_blaster/ublast2_access_libusb.c
@@ -219,7 +219,7 @@ static int ublast2_libusb_init(struct ublast_lowlevel *low)
 		while (jtag_libusb_open(vids_renum, pids_renum, NULL,
 				&low->libusb_dev, NULL) != ERROR_OK && retry--) {
 			usleep(1000000);
-			LOG_INFO("Waiting for renumerate...");
+			LOG_INFO("Waiting for reenumerate...");
 		}
 
 		if (!retry) {
diff --git a/src/jtag/drivers/usb_blaster/usb_blaster.c b/src/jtag/drivers/usb_blaster/usb_blaster.c
index d30483b63..b5f252164 100644
--- a/src/jtag/drivers/usb_blaster/usb_blaster.c
+++ b/src/jtag/drivers/usb_blaster/usb_blaster.c
@@ -366,10 +366,10 @@ static void ublast_idle_clock(void)
  * Output a TDI bit and assert clock to push it into the JTAG device :
  *  - writing out TCK=0, TMS=<old_state>=0, TDI=<tdi>
  * - writing out TCK=1, TMS=<new_state>, TDI=<tdi> which triggers the JTAG
- *    device aquiring the data.
+ *    device acquiring the data.
  *
  * If a TDO is to be read back, the required read is requested (bitbang mode),
- * and the USB Blaster will send back a byte with bit0 reprensenting the TDO.
+ * and the USB Blaster will send back a byte with bit0 representing the TDO.
  */
 static void ublast_clock_tdi(int tdi, enum scan_type type)
 {
@@ -391,7 +391,7 @@ static void ublast_clock_tdi(int tdi, enum scan_type type)
  * @type: scan type (ie. does a readback of TDO is required)
  *
  * This function is the same as ublast_clock_tdi(), but it changes also the TMS
- * while outputing the TDI. This should be the last TDI output of a TDI
+ * while output the TDI. This should be the last TDI output of a TDI
  * sequence, which will change state from :
  *   - IRSHIFT -> IREXIT1
  *   - or DRSHIFT -> DREXIT1
@@ -447,7 +447,7 @@ static void ublast_queue_bytes(uint8_t *bytes, int nb_bytes)
  * @nb_bits: number of TMS bits (between 1 and 8)
  * @skip: number of TMS bits to skip at the beginning of the series
  *
- * Write a serie of TMS transitions, where each transition consists in :
+ * Write a series of TMS transitions, where each transition consists in :
  *  - writing out TCK=0, TMS=<new_state>, TDI=<???>
  *  - writing out TCK=1, TMS=<new_state>, TDI=<???> which triggers the transition
  * The function ensures that at the end of the sequence, the clock (TCK) is put
@@ -477,7 +477,7 @@ static void ublast_tms(struct tms_command *cmd)
  * ublast_path_move - write a TMS sequence transition to JTAG
  * @cmd: path transition
  *
- * Write a serie of TMS transitions, where each transition consists in :
+ * Write a series of TMS transitions, where each transition consists in :
  *  - writing out TCK=0, TMS=<new_state>, TDI=<???>
  *  - writing out TCK=1, TMS=<new_state>, TDI=<???> which triggers the transition
  * The function ensures that at the end of the sequence, the clock (TCK) is put
@@ -534,7 +534,7 @@ static void ublast_state_move(tap_state_t state, int skip)
  * bit0), second bit in (byte0, bit1), ...), which is what we want to return,
  * simply read bytes from USB interface and store them.
  *
- * Returns ERROR_OK if OK, ERROR_xxx if a read error occured
+ * Returns ERROR_OK if OK, ERROR_xxx if a read error occurred
  */
 static int ublast_read_byteshifted_tdos(uint8_t *buf, int nb_bytes)
 {
@@ -564,7 +564,7 @@ static int ublast_read_byteshifted_tdos(uint8_t *buf, int nb_bytes)
  *  - ninth bit is sotred in byte1, bit 0
  *  - etc ...
  *
- * Returns ERROR_OK if OK, ERROR_xxx if a read error occured
+ * Returns ERROR_OK if OK, ERROR_xxx if a read error occurred
  */
 static int ublast_read_bitbang_tdos(uint8_t *buf, int nb_bits)
 {
@@ -596,7 +596,7 @@ static int ublast_read_bitbang_tdos(uint8_t *buf, int nb_bits)
  * @nb_bits: number of bits
  * @scan: scan type (ie. if TDO read back is required or not)
  *
- * Outputs a serie of TDI bits on TDI.
+ * Outputs a series of TDI bits on TDI.
  * As a side effect, the last TDI bit is sent along a TMS=1, and triggers a JTAG
  * TAP state shift if input bits were non NULL.
  *
@@ -707,7 +707,7 @@ static void ublast_stableclocks(int cycles)
  *
  * Launch a JTAG IR-scan or DR-scan
  *
- * Returns ERROR_OK if OK, ERROR_xxx if a read/write error occured.
+ * Returns ERROR_OK if OK, ERROR_xxx if a read/write error occurred.
  */
 static int ublast_scan(struct scan_command *cmd)
 {
diff --git a/src/jtag/drivers/usbprog.c b/src/jtag/drivers/usbprog.c
index 7b27eaff2..67cad58f4 100644
--- a/src/jtag/drivers/usbprog.c
+++ b/src/jtag/drivers/usbprog.c
@@ -403,11 +403,11 @@ static void usbprog_jtag_init(struct usbprog_jtag *usbprog_jtag)
 
 static void usbprog_jtag_write_and_read(struct usbprog_jtag *usbprog_jtag, char *buffer, int size)
 {
-	char tmp[64];	/* fastes packet size for usb controller */
+	char tmp[64];	/* fastest packet size for usb controller */
 	int send_bits, bufindex = 0, fillindex = 0, i, loops;
 
 	char swap;
-	/* 61 byte can be transfered (488 bit) */
+	/* 61 byte can be transferred (488 bit) */
 
 	while (size > 0) {
 		if (size > 488) {
@@ -449,11 +449,11 @@ static void usbprog_jtag_write_and_read(struct usbprog_jtag *usbprog_jtag, char
 
 static void usbprog_jtag_read_tdo(struct usbprog_jtag *usbprog_jtag, char *buffer, int size)
 {
-	char tmp[64];	/* fastes packet size for usb controller */
+	char tmp[64];	/* fastest packet size for usb controller */
 	int send_bits, fillindex = 0, i, loops;
 
 	char swap;
-	/* 61 byte can be transfered (488 bit) */
+	/* 61 byte can be transferred (488 bit) */
 
 	while (size > 0) {
 		if (size > 488) {
@@ -490,10 +490,10 @@ static void usbprog_jtag_read_tdo(struct usbprog_jtag *usbprog_jtag, char *buffe
 
 static void usbprog_jtag_write_tdi(struct usbprog_jtag *usbprog_jtag, char *buffer, int size)
 {
-	char tmp[64];	/* fastes packet size for usb controller */
+	char tmp[64];	/* fastest packet size for usb controller */
 	int send_bits, bufindex = 0, i, loops;
 
-	/* 61 byte can be transfered (488 bit) */
+	/* 61 byte can be transferred (488 bit) */
 	while (size > 0) {
 		if (size > 488) {
 			send_bits = 488;
diff --git a/src/jtag/drivers/versaloon/usbtoxxx/usbtoxxx_internal.h b/src/jtag/drivers/versaloon/usbtoxxx/usbtoxxx_internal.h
index e40667e91..36988869a 100644
--- a/src/jtag/drivers/versaloon/usbtoxxx/usbtoxxx_internal.h
+++ b/src/jtag/drivers/versaloon/usbtoxxx/usbtoxxx_internal.h
@@ -76,7 +76,7 @@
 #define USB_TO_POLL_CHECKFAIL                   0x03
 #define USB_TO_POLL_VERIFYBUFF                  0x04
 
-/* USB_TO_XXX Replys */
+/* USB_TO_XXX Replies */
 #define USB_TO_XXX_OK                           0x00
 #define USB_TO_XXX_FAILED                       0x01
 #define USB_TO_XXX_TIME_OUT                     0x02
diff --git a/src/jtag/drivers/versaloon/versaloon.c b/src/jtag/drivers/versaloon/versaloon.c
index 146383961..35a0deff5 100644
--- a/src/jtag/drivers/versaloon/versaloon.c
+++ b/src/jtag/drivers/versaloon/versaloon.c
@@ -248,7 +248,7 @@ RESULT versaloon_init(void)
 
 	/* connect to versaloon */
 	timeout_tmp = versaloon_usb_to;
-	/* not output error message when connectting */
+	/* not output error message when connecting */
 	/* 100ms delay when connect */
 	versaloon_usb_to = 100;
 	for (retry = 0; retry < VERSALOON_RETRY_CNT; retry++) {
diff --git a/src/jtag/drivers/versaloon/versaloon_include.h b/src/jtag/drivers/versaloon/versaloon_include.h
index 089056d02..901402520 100644
--- a/src/jtag/drivers/versaloon/versaloon_include.h
+++ b/src/jtag/drivers/versaloon/versaloon_include.h
@@ -41,7 +41,7 @@
 #define ERRMSG_INVALID_USAGE				"Invalid usage of %s"
 #define ERRMSG_INVALID_TARGET				"Invalid %s"
 #define ERRMSG_INVALID_PARAMETER			"Invalid parameter of %s."
-#define ERRMSG_INVALID_INTERFACE_NUM		"invalid inteface %d"
+#define ERRMSG_INVALID_INTERFACE_NUM		"invalid interface %d"
 #define ERRMSG_INVALID_BUFFER				"Buffer %s is not valid."
 #define ERRCODE_INVALID_BUFFER				ERROR_FAIL
 #define ERRCODE_INVALID_PARAMETER			ERROR_FAIL
diff --git a/src/jtag/drivers/xds110.c b/src/jtag/drivers/xds110.c
index 5e4df93c2..67c4a3b12 100644
--- a/src/jtag/drivers/xds110.c
+++ b/src/jtag/drivers/xds110.c
@@ -1129,7 +1129,7 @@ static int xds110_swd_switch_seq(enum swd_special_seq seq)
 		xds110.is_cmapi_acquired = false;
 		/* Run sequence to put target in SWD mode */
 		success = swd_connect();
-		/* Re-iniitialize CMAPI API for DAP access */
+		/* Re-initialize CMAPI API for DAP access */
 		if (success) {
 			xds110.is_swd_mode = true;
 			success = cmapi_connect(&idcode);
diff --git a/src/jtag/drivers/xlnx-pcie-xvc.c b/src/jtag/drivers/xlnx-pcie-xvc.c
index 704c1d96b..43993c897 100644
--- a/src/jtag/drivers/xlnx-pcie-xvc.c
+++ b/src/jtag/drivers/xlnx-pcie-xvc.c
@@ -54,7 +54,7 @@ static int xlnx_pcie_xvc_read_reg(const int offset, uint32_t *val)
 	uint32_t res;
 	int err;
 
-	/* Note: This should be ok endianess-wise because by going
+	/* Note: This should be ok endianness-wise because by going
 	 * through sysfs the kernel does the conversion in the config
 	 * space accessor functions
 	 */
@@ -75,7 +75,7 @@ static int xlnx_pcie_xvc_write_reg(const int offset, const uint32_t val)
 {
 	int err;
 
-	/* Note: This should be ok endianess-wise because by going
+	/* Note: This should be ok endianness-wise because by going
 	 * through sysfs the kernel does the conversion in the config
 	 * space accessor functions
 	 */
diff --git a/src/jtag/hla/hla_interface.c b/src/jtag/hla/hla_interface.c
index 6d5cdc5e7..7be9b2dea 100644
--- a/src/jtag/hla/hla_interface.c
+++ b/src/jtag/hla/hla_interface.c
@@ -312,7 +312,7 @@ static const struct command_registration hl_interface_command_handlers[] = {
 	 .name = "hla_device_desc",
 	 .handler = &hl_interface_handle_device_desc_command,
 	 .mode = COMMAND_CONFIG,
-	 .help = "set the a device description of the adapter",
+	 .help = "set the device description of the adapter",
 	 .usage = "description_string",
 	 },
 	{
diff --git a/src/jtag/interface.h b/src/jtag/interface.h
index 42598c1ae..0884868a8 100644
--- a/src/jtag/interface.h
+++ b/src/jtag/interface.h
@@ -273,7 +273,7 @@ struct adapter_driver {
 	int (*speed)(int speed);
 
 	/**
-	 * Returns JTAG maxium speed for KHz. 0 = RTCK. The function returns
+	 * Returns JTAG maximum speed for KHz. 0 = RTCK. The function returns
 	 *  a failure if it can't support the KHz/RTCK.
 	 *
 	 *  WARNING!!!! if RTCK is *slow* then think carefully about
diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h
index 9350642ff..2fa580223 100644
--- a/src/jtag/jtag.h
+++ b/src/jtag/jtag.h
@@ -210,11 +210,11 @@ struct jtag_tap_event_action {
 };
 
 /**
- * Defines the function signature requide for JTAG event callback
+ * Defines the function signature required for JTAG event callback
  * functions, which are added with jtag_register_event_callback()
  * and removed jtag_unregister_event_callback().
  * @param event The event to handle.
- * @param prive A pointer to data that was passed to
+ * @param priv A pointer to data that was passed to
  *	jtag_register_event_callback().
  * @returns Must return ERROR_OK on success, or an error code on failure.
  *
@@ -249,7 +249,7 @@ int jtag_config_khz(unsigned khz);
  */
 int jtag_config_rclk(unsigned fallback_speed_khz);
 
-/** Retreives the clock speed of the JTAG interface in KHz. */
+/** Retrieves the clock speed of the JTAG interface in KHz. */
 unsigned jtag_get_speed_khz(void);
 
 enum reset_types {
@@ -407,7 +407,7 @@ void jtag_add_callback(jtag_callback1_t f, jtag_callback_data_t data0);
  * assumptions about what the callback does or what its arguments are.
  * These callbacks are typically executed *after* the *entire* JTAG
  * queue has been executed for e.g. USB interfaces, and they are
- * guaranteeed to be invoked in the order that they were queued.
+ * guaranteed to be invoked in the order that they were queued.
  *
  * If the execution of the queue fails before the callbacks, then --
  * depending on driver implementation -- the callbacks may or may not be
@@ -457,7 +457,7 @@ void jtag_add_tlr(void);
  * path when transitioning to/from end
  * state.
  *
- * A list of unambigious single clock state transitions, not
+ * A list of unambiguous single clock state transitions, not
  * all drivers can support this, but it is required for e.g.
  * XScale and Xilinx support
  *
diff --git a/src/jtag/minidriver.h b/src/jtag/minidriver.h
index 688c39630..ad830cc13 100644
--- a/src/jtag/minidriver.h
+++ b/src/jtag/minidriver.h
@@ -74,7 +74,7 @@ int interface_add_tms_seq(unsigned num_bits,
  * trst.
  *
  * the higher level jtag_add_reset will invoke jtag_add_tlr() if
- * approperiate
+ * appropriate
  */
 int interface_jtag_add_reset(int trst, int srst);
 int interface_jtag_add_sleep(uint32_t us);
diff --git a/src/jtag/startup.tcl b/src/jtag/startup.tcl
index f8c4ca0bf..90b675f18 100644
--- a/src/jtag/startup.tcl
+++ b/src/jtag/startup.tcl
@@ -115,7 +115,7 @@ proc jtag_ntrst_assert_width args {
 
 # BEGIN MIGRATION AIDS ...  these adapter operations originally had
 # JTAG-specific names despite the fact that the operations were not
-# specific to JTAG, or otherewise had troublesome/misleading names.
+# specific to JTAG, or otherwise had troublesome/misleading names.
 #
 # FIXME phase these aids out after about April 2011
 #

commit 890048eec4f955c43284626e9c8841441e85f4fc
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jul 12 00:45:23 2020 +0200

    xsvf: fix minor typos
    
    Change-Id: Ib36b2178eacf79dd26ebd2e15ba385853825c198
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5765
    Tested-by: jenkins

diff --git a/src/xsvf/xsvf.c b/src/xsvf/xsvf.c
index bec32f21e..53779bb1c 100644
--- a/src/xsvf/xsvf.c
+++ b/src/xsvf/xsvf.c
@@ -27,11 +27,11 @@
 
 /* The specification for SVF is available here:
  * http://www.asset-intertech.com/support/svf.pdf
- * Below, this document is refered to as the "SVF spec".
+ * Below, this document is referred to as the "SVF spec".
  *
  * The specification for XSVF is available here:
  * http://www.xilinx.com/support/documentation/application_notes/xapp503.pdf
- * Below, this document is refered to as the "XSVF spec".
+ * Below, this document is referred to as the "XSVF spec".
  */
 
 #ifdef HAVE_CONFIG_H
@@ -230,7 +230,7 @@ COMMAND_HANDLER(handle_xsvf_command)
 	unsigned pathlen = 0;
 
 	/* a flag telling whether to clock TCK during waits,
-	 * or simply sleep, controled by virt2
+	 * or simply sleep, controlled by virt2
 	 */
 	int runtest_requires_tck = 0;
 
@@ -456,7 +456,7 @@ COMMAND_HANDLER(handle_xsvf_command)
 
 					if (attempt > 0) {
 						/* perform the XC9500 exception handling sequence shown in xapp067.pdf and
-						 * illustrated in psuedo code at end of this file.  We start from state
+						 * illustrated in pseudo code at end of this file.  We start from state
 						 * DRPAUSE:
 						 * go to Exit2-DR
 						 * go to Shift-DR

commit fbaa134edaa186345ee5dd7c884c58b013525d2e
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jul 12 00:42:08 2020 +0200

    transport: fix minor typos
    
    Change-Id: I481d69f9953e04c881124b2da4d092213591e4ae
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5764
    Tested-by: jenkins

diff --git a/src/transport/transport.c b/src/transport/transport.c
index 010ea7c44..9214dcd77 100644
--- a/src/transport/transport.c
+++ b/src/transport/transport.c
@@ -122,9 +122,9 @@ int allow_transports(struct command_context *ctx, const char * const *vector)
 }
 
 /**
- * Used to verify corrrect adapter driver initialization.
+ * Used to verify correct adapter driver initialization.
  *
- * @returns true iff the adapter declared one or more transports.
+ * @returns true if the adapter declares one or more transports.
  */
 bool transports_are_declared(void)
 {
@@ -139,7 +139,7 @@ bool transports_are_declared(void)
  * Code implementing a transport needs to register it before it can
  * be selected and then activated.  This is a dynamic process, so
  * that chips (and families) can define transports as needed (without
- * nneeding error-prone static tables).
+ * needing error-prone static tables).
  *
  * @param new_transport the transport being registered.  On a
  * successful return, this memory is owned by the transport framework.

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/OpenULINK/include/io.h                |  2 +-
 src/jtag/drivers/OpenULINK/src/jtag.c                  | 14 +++++++-------
 src/jtag/drivers/OpenULINK/src/protocol.c              |  2 +-
 src/jtag/drivers/OpenULINK/src/usb.c                   |  2 +-
 src/jtag/drivers/bitq.c                                |  2 +-
 src/jtag/drivers/buspirate.c                           |  2 +-
 src/jtag/drivers/cmsis_dap_usb.c                       |  2 +-
 src/jtag/drivers/jlink.c                               |  2 +-
 src/jtag/drivers/jtag_vpi.c                            | 10 +++++-----
 src/jtag/drivers/kitprog.c                             |  4 ++--
 src/jtag/drivers/osbdm.c                               |  2 +-
 src/jtag/drivers/presto.c                              |  4 ++--
 src/jtag/drivers/rlink.c                               |  4 ++--
 src/jtag/drivers/rshim.c                               |  2 +-
 src/jtag/drivers/stlink_usb.c                          |  6 +++---
 src/jtag/drivers/sysfsgpio.c                           |  2 +-
 src/jtag/drivers/ulink.c                               |  2 +-
 src/jtag/drivers/usb_blaster/README.CheapClone         | 12 ++++++------
 src/jtag/drivers/usb_blaster/ublast2_access_libusb.c   |  2 +-
 src/jtag/drivers/usb_blaster/usb_blaster.c             | 18 +++++++++---------
 src/jtag/drivers/usbprog.c                             | 12 ++++++------
 .../drivers/versaloon/usbtoxxx/usbtoxxx_internal.h     |  2 +-
 src/jtag/drivers/versaloon/versaloon.c                 |  2 +-
 src/jtag/drivers/versaloon/versaloon_include.h         |  2 +-
 src/jtag/drivers/xds110.c                              |  2 +-
 src/jtag/drivers/xlnx-pcie-xvc.c                       |  4 ++--
 src/jtag/hla/hla_interface.c                           |  2 +-
 src/jtag/interface.h                                   |  2 +-
 src/jtag/jtag.h                                        | 10 +++++-----
 src/jtag/minidriver.h                                  |  2 +-
 src/jtag/startup.tcl                                   |  2 +-
 src/transport/transport.c                              |  6 +++---
 src/xsvf/xsvf.c                                        |  8 ++++----
 33 files changed, 76 insertions(+), 76 deletions(-)


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From: OpenOCD-Gerrit <ope...@us...> - 2020-07-26 19:14:38

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The branch, master has been updated
       via  1f08ada36681245e53251d3210ec8706391c2fc9 (commit)
       via  e527937779b990aeeaefd5e5224f6f899e2f67a7 (commit)
       via  9db3e9879db3d89984eea80dc6fd9b1c3c269e58 (commit)
      from  f5cc8360fdf4c004c9efa2132645f9319ceef49d (commit)

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- Log -----------------------------------------------------------------
commit 1f08ada36681245e53251d3210ec8706391c2fc9
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jul 12 00:33:29 2020 +0200

    server: fix minor typos
    
    Change-Id: Ibf835dc174a1a160ec0d57000a113c35f2713045
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5760
    Tested-by: jenkins

diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 17042fbf5..327d96b17 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -68,7 +68,7 @@ struct target_desc_format {
 
 /* private connection data for GDB */
 struct gdb_connection {
-	char buffer[GDB_BUFFER_SIZE + 1]; /* Extra byte for nul-termination */
+	char buffer[GDB_BUFFER_SIZE + 1]; /* Extra byte for null-termination */
 	char *buf_p;
 	int buf_cnt;
 	bool ctrl_c;
@@ -3221,7 +3221,7 @@ static void gdb_sig_halted(struct connection *connection)
 static int gdb_input_inner(struct connection *connection)
 {
 	/* Do not allocate this on the stack */
-	static char gdb_packet_buffer[GDB_BUFFER_SIZE + 1]; /* Extra byte for nul-termination */
+	static char gdb_packet_buffer[GDB_BUFFER_SIZE + 1]; /* Extra byte for null-termination */
 
 	struct target *target;
 	char const *packet = gdb_packet_buffer;
@@ -3503,7 +3503,7 @@ static int gdb_target_start(struct target *target, const char *port)
 	ret = add_service("gdb",
 			port, 1, &gdb_new_connection, &gdb_input,
 			&gdb_connection_closed, gdb_service);
-	/* initialialize all targets gdb service with the same pointer */
+	/* initialize all targets gdb service with the same pointer */
 	{
 		struct target_list *head;
 		struct target *curr;
diff --git a/src/server/server.c b/src/server/server.c
index 23a15ef9a..d96f0b6cf 100644
--- a/src/server/server.c
+++ b/src/server/server.c
@@ -325,7 +325,7 @@ int add_service(char *name,
 #endif
 	} else if (c->type == CONNECTION_PIPE) {
 #ifdef _WIN32
-		/* we currenty do not support named pipes under win32
+		/* we currently do not support named pipes under win32
 		 * so exit openocd for now */
 		LOG_ERROR("Named pipes currently not supported under this os");
 		free_service(c);

commit e527937779b990aeeaefd5e5224f6f899e2f67a7
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jul 12 00:25:53 2020 +0200

    rtos: fix minor typos
    
    Change-Id: I9ed4e2150a0a057397538b608d4a72bc48d0d64f
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5759
    Tested-by: jenkins

diff --git a/src/rtos/FreeRTOS.c b/src/rtos/FreeRTOS.c
index c45d9d645..9a51974c5 100644
--- a/src/rtos/FreeRTOS.c
+++ b/src/rtos/FreeRTOS.c
@@ -245,7 +245,7 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 		return ERROR_FAIL;
 	}
 	uint64_t top_used_priority = 0;
-	/* FIXME: endianess error on almost all target_read_buffer(), see also
+	/* FIXME: endianness error on almost all target_read_buffer(), see also
 	 * other rtoses */
 	retval = target_read_buffer(rtos->target,
 			rtos->symbols[FreeRTOS_VAL_uxTopUsedPriority].address,
diff --git a/src/rtos/chromium-ec.c b/src/rtos/chromium-ec.c
index 92ed2cbad..ae12a3bf5 100644
--- a/src/rtos/chromium-ec.c
+++ b/src/rtos/chromium-ec.c
@@ -306,7 +306,7 @@ static int chromium_ec_update_threads(struct rtos *rtos)
 			LOG_ERROR("Failed to get task %d's runtime", t);
 		runtime =  target_buffer_get_u64(rtos->target, runtime_buf);
 
-		/* Priority is simply the positon in the array */
+		/* Priority is simply the position in the array */
 		if (thread_ptr == current_task)
 			snprintf(thread_str_buf, sizeof(thread_str_buf),
 				 "State: Running, Priority: %u, Events: %" PRIx32 ", Runtime: %" PRIu64 "\n",
diff --git a/src/rtos/linux.c b/src/rtos/linux.c
index 63659bb05..cd1ed218a 100644
--- a/src/rtos/linux.c
+++ b/src/rtos/linux.c
@@ -188,7 +188,7 @@ static int linux_os_thread_reg_list(struct rtos *rtos,
 		return ERROR_FAIL;
 	}
 
-	/*  search target to perfom the access  */
+	/*  search target to perform the access  */
 	struct reg **gdb_reg_list;
 	struct target_list *head;
 	head = target->head;
diff --git a/src/rtos/nuttx.c b/src/rtos/nuttx.c
index 322c7d19b..3c9062516 100644
--- a/src/rtos/nuttx.c
+++ b/src/rtos/nuttx.c
@@ -174,7 +174,7 @@ static int rcmd_offset(const char *cmd, const char *name)
 static int nuttx_thread_packet(struct connection *connection,
 	char const *packet, int packet_size)
 {
-	char cmd[GDB_BUFFER_SIZE / 2 + 1] = ""; /* Extra byte for nul-termination */
+	char cmd[GDB_BUFFER_SIZE / 2 + 1] = ""; /* Extra byte for null-termination */
 
 	if (!strncmp(packet, "qRcmd", 5)) {
 		size_t len = unhexify((uint8_t *)cmd, packet + 6, sizeof(cmd));
diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c
index ca31d22a5..97ce255b9 100644
--- a/src/rtos/rtos.c
+++ b/src/rtos/rtos.c
@@ -231,7 +231,7 @@ int rtos_qsymbol(struct connection *connection, char const *packet, int packet_s
 	int rtos_detected = 0;
 	uint64_t addr = 0;
 	size_t reply_len;
-	char reply[GDB_BUFFER_SIZE + 1], cur_sym[GDB_BUFFER_SIZE / 2 + 1] = ""; /* Extra byte for nul-termination */
+	char reply[GDB_BUFFER_SIZE + 1], cur_sym[GDB_BUFFER_SIZE / 2 + 1] = ""; /* Extra byte for null-termination */
 	symbol_table_elem_t *next_sym = NULL;
 	struct target *target = get_target_from_connection(connection);
 	struct rtos *os = target->rtos;

commit 9db3e9879db3d89984eea80dc6fd9b1c3c269e58
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jul 12 00:00:47 2020 +0200

    flash: fix typos and duplicated words
    
    Fix typos and duplicated words in comments and strings.
    
    Change-Id: I64282c7018462deefeeb8e5f4d0d81942425b3fc
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5758
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>
    Reviewed-by: Christopher Head <ch...@za...>

diff --git a/src/flash/nand/driver.h b/src/flash/nand/driver.h
index 2182a7727..690ee91ec 100644
--- a/src/flash/nand/driver.h
+++ b/src/flash/nand/driver.h
@@ -94,7 +94,7 @@ typedef int (*nand_driver_walker_t)(struct nand_flash_controller *c, void *);
  * Walk the list of drivers, encapsulating the data structure type.
  * Application state/context can be passed through the @c x pointer.
  * @param f The callback function to invoke for each function.
- * @param x For use as private data storate, passed directly to @c f.
+ * @param x For use as private data storage, passed directly to @c f.
  * @returns ERROR_OK if successful, or the non-zero return value of @c f.
  * This allows a walker to terminate the loop early.
  */
diff --git a/src/flash/nand/fileio.c b/src/flash/nand/fileio.c
index f65f957bf..1279e45a4 100644
--- a/src/flash/nand/fileio.c
+++ b/src/flash/nand/fileio.c
@@ -206,7 +206,7 @@ int nand_fileio_read(struct nand_device *nand, struct nand_fileio_state *s)
 	} else if (s->oob_format & NAND_OOB_SW_ECC_KW)   {
 		/*
 		 * In this case eccpos is not used as
-		 * the ECC data is always stored contigously
+		 * the ECC data is always stored contiguously
 		 * at the end of the OOB area.  It consists
 		 * of 10 bytes per 512-byte data block.
 		 */
diff --git a/src/flash/nand/lpc3180.c b/src/flash/nand/lpc3180.c
index 389c18ac4..97bd7a351 100644
--- a/src/flash/nand/lpc3180.c
+++ b/src/flash/nand/lpc3180.c
@@ -232,7 +232,7 @@ static int lpc3180_init(struct nand_device *nand)
 		/* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
 		target_write_u32(target, 0x400040c8, 0x05);
 
-		/* after reset set other registers of SLC so reset calling is here at the begining*/
+		/* after reset set other registers of SLC so reset calling is here at the beginning */
 		lpc3180_reset(nand);
 
 		/* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled,
diff --git a/src/flash/nand/lpc32xx.c b/src/flash/nand/lpc32xx.c
index 058d9a50e..d516522f3 100644
--- a/src/flash/nand/lpc32xx.c
+++ b/src/flash/nand/lpc32xx.c
@@ -42,7 +42,7 @@ extern int nand_correct_data(struct nand_device *nand, u_char *dat,
  * read/write data to the SLC controller.
  * - DMA descriptors will be put at start of working area,
  * - Hardware generated ECC will be stored at ECC_OFFS
- * - OOB wil be read/written from/to SPARE_OFFS
+ * - OOB will be read/written from/to SPARE_OFFS
  * - Actual page data will be read from/to DATA_OFFS
  * There are unused holes between the used areas.
  */
@@ -317,7 +317,7 @@ static int lpc32xx_init(struct nand_device *nand)
 		}
 
 		/* after reset set other registers of SLC,
-		 * so reset calling is here at the begining
+		 * so reset calling is here at the beginning
 		 */
 		retval = lpc32xx_reset(nand);
 		if (ERROR_OK != retval)
@@ -769,7 +769,7 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
 	 * 2. Copy generated ECC data from Register to Spare Area
 	 * 3. X'fer next 256 bytes of data from Memory to Flash.
 	 * 4. Copy generated ECC data from Register to Spare Area.
-	 * 5. X'fer 16 byets of Spare area from Memory to Flash.
+	 * 5. X'fer 16 bytes of Spare area from Memory to Flash.
 	 * Read Operation Sequence for Small Block NAND
 	 * ----------------------------------------------------------
 	 * 1. X'fer 256 bytes of data from Flash to Memory.
@@ -779,13 +779,13 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
 	 * 5. X'fer 16 bytes of Spare area from Flash to Memory.
 	 * Write Operation Sequence for Large Block NAND
 	 * ----------------------------------------------------------
-	 * 1. Steps(1-4) of Write Operations repeate for four times
+	 * 1. Steps(1-4) of Write Operations repeated for four times
 	 * which generates 16 DMA descriptors to X'fer 2048 bytes of
 	 * data & 32 bytes of ECC data.
 	 * 2. X'fer 64 bytes of Spare area from Memory to Flash.
 	 * Read Operation Sequence for Large Block NAND
 	 * ----------------------------------------------------------
-	 * 1. Steps(1-4) of Read Operations repeate for four times
+	 * 1. Steps(1-4) of Read Operations repeated for four times
 	 * which generates 16 DMA descriptors to X'fer 2048 bytes of
 	 * data & 32 bytes of ECC data.
 	 * 2. X'fer 64 bytes of Spare area from Flash to Memory.
@@ -842,7 +842,7 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
 	 * 2. Copy generated ECC data from Register to Spare Area
 	 * 3. X'fer next 256 bytes of data from Memory to Flash.
 	 * 4. Copy generated ECC data from Register to Spare Area.
-	 * 5. X'fer 16 byets of Spare area from Memory to Flash.
+	 * 5. X'fer 16 bytes of Spare area from Memory to Flash.
 	 * Read Operation Sequence for Small Block NAND
 	 * ----------------------------------------------------------
 	 * 1. X'fer 256 bytes of data from Flash to Memory.
@@ -852,13 +852,13 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
 	 * 5. X'fer 16 bytes of Spare area from Flash to Memory.
 	 * Write Operation Sequence for Large Block NAND
 	 * ----------------------------------------------------------
-	 * 1. Steps(1-4) of Write Operations repeate for four times
+	 * 1. Steps(1-4) of Write Operations repeated for four times
 	 * which generates 16 DMA descriptors to X'fer 2048 bytes of
 	 * data & 32 bytes of ECC data.
 	 * 2. X'fer 64 bytes of Spare area from Memory to Flash.
 	 * Read Operation Sequence for Large Block NAND
 	 * ----------------------------------------------------------
-	 * 1. Steps(1-4) of Read Operations repeate for four times
+	 * 1. Steps(1-4) of Read Operations repeated for four times
 	 * which generates 16 DMA descriptors to X'fer 2048 bytes of
 	 * data & 32 bytes of ECC data.
 	 * 2. X'fer 64 bytes of Spare area from Flash to Memory.
@@ -1044,7 +1044,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
 
 	target_mem_base = pworking_area->address;
 	/*
-	 * Skip writting page which has all 0xFF data as this will
+	 * Skip writing page which has all 0xFF data as this will
 	 * generate 0x0 value.
 	 */
 	if (data && !oob) {
@@ -1102,7 +1102,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
 			return retval;
 		}
 
-		/* Write first decriptor to DMA controller */
+		/* Write first descriptor to DMA controller */
 		retval = target_write_memory(target, 0x31000100, 4,
 				sizeof(dmac_ll_t) / 4,
 				(uint8_t *)dmalist);
@@ -1159,7 +1159,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
 		return retval;
 	}
 
-	/* Write OOB decriptor to DMA controller */
+	/* Write OOB descriptor to DMA controller */
 	retval = target_write_memory(target, 0x31000100, 4,
 			sizeof(dmac_ll_t) / 4,
 			(uint8_t *)(&dmalist[nll-1]));
@@ -1487,7 +1487,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand,
 		return retval;
 	}
 
-	/* Write first decriptor to DMA controller */
+	/* Write first descriptor to DMA controller */
 	retval = target_write_memory(target, 0x31000100, 4,
 			sizeof(dmac_ll_t) / 4, (uint8_t *)dmalist);
 	if (ERROR_OK != retval) {
diff --git a/src/flash/nand/mx3.c b/src/flash/nand/mx3.c
index da141b742..abeaf159c 100644
--- a/src/flash/nand/mx3.c
+++ b/src/flash/nand/mx3.c
@@ -149,7 +149,7 @@ static int imx31_init(struct nand_device *nand)
 		uint32_t gpr_register_content;
 		target_read_u32(target, MX3_GPR, &gpr_register_content);
 		if (gpr_register_content & 0x00000060) {
-			LOG_ERROR("pins mode overrided by GPR");
+			LOG_ERROR("pins mode overridden by GPR");
 			return ERROR_FAIL;
 		}
 	}
@@ -414,10 +414,10 @@ static int imx31_write_page(struct nand_device *nand, uint32_t page,
 		if (oob) {
 			if (mx3_nf_info->flags.hw_ecc_enabled) {
 				/*
-				 * part of spare block will be overrided by hardware
+				 * part of spare block will be overridden by hardware
 				 * ECC generator
 				 */
-				LOG_DEBUG("part of spare block will be overrided by hardware ECC generator");
+				LOG_DEBUG("part of spare block will be overridden by hardware ECC generator");
 			}
 			target_write_buffer(target, MX3_NF_SPARE_BUFFER0, oob_size, oob);
 		}
@@ -530,7 +530,7 @@ static int initialize_nf_controller(struct nand_device *nand)
 	struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
 	struct target *target = nand->target;
 	/*
-	* resets NAND flash controller in zero time ? I dont know.
+	* resets NAND flash controller in zero time ? I don't know.
 	*/
 	target_write_u16(target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
 	{
@@ -680,18 +680,18 @@ static int do_data_output(struct nand_device *nand)
 				target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
 				switch (ecc_status & 0x000c) {
 				case 1 << 2:
-					LOG_DEBUG("main area readed with 1 (correctable) error");
+					LOG_DEBUG("main area read with 1 (correctable) error");
 					break;
 				case 2 << 2:
-					LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
+					LOG_DEBUG("main area read with more than 1 (incorrectable) error");
 					return ERROR_NAND_OPERATION_FAILED;
 				}
 				switch (ecc_status & 0x0003) {
 				case 1:
-					LOG_DEBUG("spare area readed with 1 (correctable) error");
+					LOG_DEBUG("spare area read with 1 (correctable) error");
 					break;
 				case 2:
-					LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
+					LOG_DEBUG("main area read with more than 1 (incorrectable) error");
 					return ERROR_NAND_OPERATION_FAILED;
 				}
 			}
diff --git a/src/flash/nand/mxc.c b/src/flash/nand/mxc.c
index ee093c056..bc2ae9324 100644
--- a/src/flash/nand/mxc.c
+++ b/src/flash/nand/mxc.c
@@ -136,7 +136,7 @@ NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
 		(nand->target->endianness == TARGET_LITTLE_ENDIAN);
 
 	/*
-	 * should factory bad block indicator be swaped
+	 * should factory bad block indicator be swapped
 	 * as a workaround for how the nfc handles pages.
 	 */
 	if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
@@ -181,7 +181,7 @@ static const struct command_registration mxc_sub_command_handlers[] = {
 		.name = "biswap",
 		.mode = COMMAND_EXEC,
 		.handler = handle_mxc_biswap_command,
-		.help = "Turns on/off bad block information swaping from main area, "
+		.help = "Turns on/off bad block information swapping from main area, "
 			"without parameter query status.",
 		.usage = "bank_id ['enable'|'disable']",
 	},
@@ -400,7 +400,7 @@ static int mxc_command(struct nand_device *nand, uint8_t command)
 			mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 			break;
 		default:
-			/* Ohter command use the default 'One page data out' FDO */
+			/* Other command use the default 'One page data out' FDO */
 			mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
 			break;
 	}
@@ -502,10 +502,10 @@ static int mxc_write_page(struct nand_device *nand, uint32_t page,
 	if (oob) {
 		if (mxc_nf_info->flags.hw_ecc_enabled) {
 			/*
-			 * part of spare block will be overrided by hardware
+			 * part of spare block will be overridden by hardware
 			 * ECC generator
 			 */
-			LOG_DEBUG("part of spare block will be overrided "
+			LOG_DEBUG("part of spare block will be overridden "
 				"by hardware ECC generator");
 		}
 		if (nfc_is_v1())
@@ -710,7 +710,7 @@ static int initialize_nf_controller(struct nand_device *nand)
 	uint16_t work_mode = 0;
 	uint16_t temp;
 	/*
-	 * resets NAND flash controller in zero time ? I dont know.
+	 * resets NAND flash controller in zero time ? I don't know.
 	 */
 	target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
 	if (mxc_nf_info->mxc_version == MXC_VERSION_MX27)
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index c8c4afe1f..1e2a074aa 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -21,7 +21,7 @@
  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
 ****************************************************************************/
 
-/* Some of the the lower level code was based on code supplied by
+/* Some of the lower level code was based on code supplied by
  * ATMEL under this copyright. */
 
 /* BEGIN ATMEL COPYRIGHT */
@@ -3095,7 +3095,7 @@ FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
 }
 
 /**
- * Remove all chips from the internal list without distingushing which one
+ * Remove all chips from the internal list without distinguishing which one
  * is owned by this bank. This simplification works only for one shot
  * deallocation like current flash_free_all_banks()
  */
@@ -3398,7 +3398,7 @@ static int sam3_write(struct flash_bank *bank,
 	struct sam3_bank_private *pPrivate;
 	uint8_t *pagebuffer;
 
-	/* incase we bail further below, set this to null */
+	/* in case we bail further below, set this to null */
 	pagebuffer = NULL;
 
 	/* ignore dumb requests */
diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c
index f2827496d..4be3a5962 100644
--- a/src/flash/nor/at91sam4.c
+++ b/src/flash/nor/at91sam4.c
@@ -22,7 +22,7 @@
  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
 ****************************************************************************/
 
-/* Some of the the lower level code was based on code supplied by
+/* Some of the lower level code was based on code supplied by
  * ATMEL under this copyright. */
 
 /* BEGIN ATMEL COPYRIGHT */
@@ -2509,7 +2509,7 @@ FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
 }
 
 /**
- * Remove all chips from the internal list without distingushing which one
+ * Remove all chips from the internal list without distinguishing which one
  * is owned by this bank. This simplification works only for one shot
  * deallocation like current flash_free_all_banks()
  */
@@ -2873,7 +2873,7 @@ static int sam4_write(struct flash_bank *bank,
 	struct sam4_bank_private *pPrivate;
 	uint8_t *pagebuffer;
 
-	/* incase we bail further below, set this to null */
+	/* in case we bail further below, set this to null */
 	pagebuffer = NULL;
 
 	/* ignore dumb requests */
diff --git a/src/flash/nor/at91sam7.c b/src/flash/nor/at91sam7.c
index 7dfdf0d29..59f5951ae 100644
--- a/src/flash/nor/at91sam7.c
+++ b/src/flash/nor/at91sam7.c
@@ -254,7 +254,7 @@ static void at91sam7_read_clock_info(struct flash_bank *bank)
 		at91sam7_info->mck_freq = tmp;
 }
 
-/* Setup the timimg registers for nvbits or normal flash */
+/* Setup the timing registers for nvbits or normal flash */
 static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode)
 {
 	uint32_t fmr, fmcn = 0, fws = 0;
@@ -377,7 +377,7 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
 			/* re-calculate master clock frequency */
 			at91sam7_read_clock_info(t_bank);
 
-			/* no timming */
+			/* no timing */
 			at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
 
 			/* check protect state */
@@ -415,7 +415,7 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
 			/* calculate master clock frequency */
 			at91sam7_read_clock_info(t_bank);
 
-			/* no timming */
+			/* no timing */
 			at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
 
 			/* check protect state */
@@ -623,7 +623,7 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
 		/* calculate master clock frequency */
 		at91sam7_read_clock_info(t_bank);
 
-		/* no timming */
+		/* no timing */
 		at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
 
 		/* check protect state */
diff --git a/src/flash/nor/at91samd.c b/src/flash/nor/at91samd.c
index 0bd5f5995..63710d3e0 100644
--- a/src/flash/nor/at91samd.c
+++ b/src/flash/nor/at91samd.c
@@ -41,7 +41,7 @@
 #define SAMD_NVMCTRL_CTRLA		0x00	/* NVM control A register */
 #define SAMD_NVMCTRL_CTRLB		0x04	/* NVM control B register */
 #define SAMD_NVMCTRL_PARAM		0x08	/* NVM parameters register */
-#define SAMD_NVMCTRL_INTFLAG	0x18	/* NVM Interupt Flag Status & Clear */
+#define SAMD_NVMCTRL_INTFLAG	0x18	/* NVM Interrupt Flag Status & Clear */
 #define SAMD_NVMCTRL_STATUS		0x18	/* NVM status register */
 #define SAMD_NVMCTRL_ADDR		0x1C	/* NVM address register */
 #define SAMD_NVMCTRL_LOCK		0x20	/* NVM Lock section register */
@@ -52,8 +52,8 @@
 /* NVMCTRL commands.  See Table 20-4 in 42129FâSAMâ10/2013 */
 #define SAMD_NVM_CMD_ER		0x02		/* Erase Row */
 #define SAMD_NVM_CMD_WP		0x04		/* Write Page */
-#define SAMD_NVM_CMD_EAR	0x05		/* Erase Auxilary Row */
-#define SAMD_NVM_CMD_WAP	0x06		/* Write Auxilary Page */
+#define SAMD_NVM_CMD_EAR	0x05		/* Erase Auxiliary Row */
+#define SAMD_NVM_CMD_WAP	0x06		/* Write Auxiliary Page */
 #define SAMD_NVM_CMD_LR		0x40		/* Lock Region */
 #define SAMD_NVM_CMD_UR		0x41		/* Unlock Region */
 #define SAMD_NVM_CMD_SPRM	0x42		/* Set Power Reduction Mode */
diff --git a/src/flash/nor/atsame5.c b/src/flash/nor/atsame5.c
index ab79e8cf7..82306830a 100644
--- a/src/flash/nor/atsame5.c
+++ b/src/flash/nor/atsame5.c
@@ -31,10 +31,10 @@
 #include <target/cortex_m.h>
 
 /* A note to prefixing.
- * Definitions and functions ingerited from at91samd.c without
- * any change retained the original prefix samd_ so they eventualy
+ * Definitions and functions inherited from at91samd.c without
+ * any change retained the original prefix samd_ so they eventually
  * may go to samd_common.h and .c
- * As currently there are olny 3 short functions identical with
+ * As currently there are only 3 short functions identical with
  * the original source, no common file was created. */
 
 #define SAME5_PAGES_PER_BLOCK	16
diff --git a/src/flash/nor/atsamv.c b/src/flash/nor/atsamv.c
index 1ad37c1ab..7db31f140 100644
--- a/src/flash/nor/atsamv.c
+++ b/src/flash/nor/atsamv.c
@@ -25,7 +25,7 @@
  *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
-/* Some of the the lower level code was based on code supplied by
+/* Some of the lower level code was based on code supplied by
  * ATMEL under this copyright. */
 
 /* BEGIN ATMEL COPYRIGHT */
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 9d2a53a6b..887821b79 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -1178,7 +1178,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
 	 * r6: error test pattern
 	 */
 
-	/* see contib/loaders/flash/armv4_5_cfi_intel_32.s for src */
+	/* see contrib/loaders/flash/armv4_5_cfi_intel_32.s for src */
 	static const uint32_t word_32_code[] = {
 		0xe4904004,	/* loop: ldr r4, [r0], #4 */
 		0xe5813000,	/*       str r3, [r1] */
@@ -1196,7 +1196,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
 		0xeafffffe	/* done: b -2 */
 	};
 
-	/* see contib/loaders/flash/armv4_5_cfi_intel_16.s for src */
+	/* see contrib/loaders/flash/armv4_5_cfi_intel_16.s for src */
 	static const uint32_t word_16_code[] = {
 		0xe0d040b2,	/* loop: ldrh r4, [r0], #2 */
 		0xe1c130b0,	/*       strh r3, [r1] */
@@ -1214,7 +1214,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
 		0xeafffffe	/* done:	b -2 */
 	};
 
-	/* see contib/loaders/flash/armv4_5_cfi_intel_8.s for src */
+	/* see contrib/loaders/flash/armv4_5_cfi_intel_8.s for src */
 	static const uint32_t word_8_code[] = {
 		0xe4d04001,	/* loop: ldrb r4, [r0], #1 */
 		0xe5c13000,	/*       strb r3, [r1] */
@@ -1249,7 +1249,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
 
 	cfi_intel_clear_status_register(bank);
 
-	/* If we are setting up the write_algorith, we need target_code_src
+	/* If we are setting up the write_algorithm, we need target_code_src
 	 * if not we only need target_code_size. */
 
 	/* However, we don't want to create multiple code paths, so we
@@ -1364,7 +1364,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
 		if (retval != ERROR_OK) {
 			cfi_intel_clear_status_register(bank);
 			LOG_ERROR(
-				"Execution of flash algorythm failed. Can't fall back. Please report.");
+				"Execution of flash algorithm failed. Can't fall back. Please report.");
 			retval = ERROR_FLASH_OPERATION_FAILED;
 			/* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
 			/* FIXME To allow fall back or recovery, we must save the actual status
@@ -1653,7 +1653,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, const uint8_t *buff
 	 *  R10 = unlock2_addr
 	 *  R11 = unlock2_cmd */
 
-	/* see contib/loaders/flash/armv4_5_cfi_span_32.s for src */
+	/* see contrib/loaders/flash/armv4_5_cfi_span_32.s for src */
 	static const uint32_t armv4_5_word_32_code[] = {
 		/* 00008100 <sp_32_code>:		*/
 		0xe4905004,		/* ldr	r5, [r0], #4			*/
@@ -1685,7 +1685,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, const uint8_t *buff
 		0xeafffffe		/* b	8154 <sp_32_done>		*/
 	};
 
-	/* see contib/loaders/flash/armv4_5_cfi_span_16.s for src */
+	/* see contrib/loaders/flash/armv4_5_cfi_span_16.s for src */
 	static const uint32_t armv4_5_word_16_code[] = {
 		/* 00008158 <sp_16_code>:		*/
 		0xe0d050b2,		/* ldrh	r5, [r0], #2			*/
@@ -2406,7 +2406,7 @@ static int cfi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of
 			break;
 	}
 	if (retval == ERROR_OK) {
-		/* Increment pointers and decrease count on succesful block write */
+		/* Increment pointers and decrease count on successful block write */
 		buffer += blk_count;
 		write_p += blk_count;
 		count -= blk_count;
@@ -2795,7 +2795,7 @@ int cfi_probe(struct flash_bank *bank)
 												 *for
 												 *all
 												 *CFI
-												 *flashs
+												 *flashes
 												 **/
 				cfi_read_0002_pri_ext(bank);
 				break;
diff --git a/src/flash/nor/core.h b/src/flash/nor/core.h
index 9f897e3e2..163e57878 100644
--- a/src/flash/nor/core.h
+++ b/src/flash/nor/core.h
@@ -248,7 +248,7 @@ int get_flash_bank_by_num(unsigned int num, struct flash_bank **bank);
  * @a instance is driver-specific.
  * @param name_index The index to the string in args containing the
  * bank identifier.
- * @param bank On output, contians a pointer to the bank or NULL.
+ * @param bank On output, contains a pointer to the bank or NULL.
  * @returns ERROR_OK on success, or an error indicating the problem.
  */
 COMMAND_HELPER(flash_command_get_bank, unsigned name_index,
diff --git a/src/flash/nor/driver.h b/src/flash/nor/driver.h
index ea8657b08..7f66047fe 100644
--- a/src/flash/nor/driver.h
+++ b/src/flash/nor/driver.h
@@ -120,7 +120,7 @@ struct flash_driver {
 	 *
 	 * @param bank The bank to protect or unprotect.
 	 * @param set If non-zero, enable protection; if 0, disable it.
-	 * @param first The first sector to (un)protect, typicaly 0.
+	 * @param first The first sector to (un)protect, typically 0.
 	 * @param last The last sector to (un)project, typically N-1.
 	 * @returns ERROR_OK if successful; otherwise, an error code.
 	 */
@@ -202,14 +202,14 @@ struct flash_driver {
 	int (*info)(struct flash_bank *bank, char *buf, int buf_size);
 
 	/**
-	 * A more gentle flavor of filash_driver_s::probe, performing
+	 * A more gentle flavor of flash_driver_s::probe, performing
 	 * setup with less noise.  Generally, driver routines should test
 	 * to see if the bank has already been probed; if it has, the
 	 * driver probably should not perform its probe a second time.
 	 *
 	 * This callback is often called from the inside of other
 	 * routines (e.g. GDB flash downloads) to autoprobe the flash as
-	 * it is programing the flash.
+	 * it is programming the flash.
 	 *
 	 * @param bank - the bank to probe
 	 * @returns ERROR_OK if successful; otherwise, an error code.
diff --git a/src/flash/nor/dsp5680xx_flash.c b/src/flash/nor/dsp5680xx_flash.c
index f06f14365..6f1eccfeb 100644
--- a/src/flash/nor/dsp5680xx_flash.c
+++ b/src/flash/nor/dsp5680xx_flash.c
@@ -107,7 +107,7 @@ static int dsp5680xx_flash_protect_check(struct flash_bank *bank)
 }
 
 /**
- * Protection funcionality is not implemented.
+ * Protection functionality is not implemented.
  * The current implementation applies/removes security on the chip.
  * The chip is effectively secured/unsecured after the first reset
  * following the execution of this function.
diff --git a/src/flash/nor/em357.c b/src/flash/nor/em357.c
index 4e40e6b6b..cb4456209 100644
--- a/src/flash/nor/em357.c
+++ b/src/flash/nor/em357.c
@@ -466,7 +466,7 @@ static int em357_write_block(struct flash_bank *bank, const uint8_t *buffer,
 	struct armv7m_algorithm armv7m_info;
 	int retval = ERROR_OK;
 
-	/* see contib/loaders/flash/stm32x.s for src, the same is used here except for
+	/* see contrib/loaders/flash/stm32x.s for src, the same is used here except for
 	 * a modified *_FLASH_BASE */
 
 	static const uint8_t em357_flash_write_code[] = {
diff --git a/src/flash/nor/fm3.c b/src/flash/nor/fm3.c
index afeba8e0b..fef179706 100644
--- a/src/flash/nor/fm3.c
+++ b/src/flash/nor/fm3.c
@@ -276,7 +276,7 @@ static int fm3_erase(struct flash_bank *bank, unsigned int first,
 	if (retval != ERROR_OK)
 		return retval;
 
-	/* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash acccess) */
+	/* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash access) */
 	retval = target_write_u32(target, 0x40000000, 0x0001);
 	if (retval != ERROR_OK)
 		return retval;
@@ -336,7 +336,7 @@ static int fm3_erase(struct flash_bank *bank, unsigned int first,
 	destroy_reg_param(&reg_params[1]);
 	destroy_reg_param(&reg_params[2]);
 
-	/* FASZR = 0x02, Enables CPU Run Mode (32-bit Flash acccess) */
+	/* FASZR = 0x02, Enables CPU Run Mode (32-bit Flash access) */
 	retval = target_write_u32(target, 0x40000000, 0x0002);
 	if (retval != ERROR_OK)
 		return retval;
diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c
index 07c5eac36..43b90f1f0 100644
--- a/src/flash/nor/kinetis.c
+++ b/src/flash/nor/kinetis.c
@@ -79,7 +79,7 @@
  *
  */
 
-/* Addressess */
+/* Addresses */
 #define FCF_ADDRESS	0x00000400
 #define FCF_FPROT	0x8
 #define FCF_FSEC	0xc
@@ -506,7 +506,7 @@ COMMAND_HANDLER(kinetis_mdm_halt)
 		}
 	}
 
-	LOG_DEBUG("MDM: halt succeded after %d attempts.", tries);
+	LOG_DEBUG("MDM: halt succeeded after %d attempts.", tries);
 
 	target_poll(target);
 	/* enable polling in case kinetis_check_flash_security_status disabled it */
@@ -1429,7 +1429,7 @@ static int kinetis_fill_fcf(struct flash_bank *bank, uint8_t *fcf)
 		bank_iter = k_bank->bank;
 
 		if (bank_iter == NULL) {
-			LOG_WARNING("Missing bank %u configuration, FCF protection flags may be incomplette", bank_idx);
+			LOG_WARNING("Missing bank %u configuration, FCF protection flags may be incomplete", bank_idx);
 			continue;
 		}
 
@@ -2850,7 +2850,7 @@ static int kinetis_blank_check(struct flash_bank *bank)
 				if (result == ERROR_OK) {
 					bank->sectors[i].is_erased = !(ftfx_fstat & 0x01);
 				} else {
-					LOG_DEBUG("Ignoring errored PFlash sector blank-check");
+					LOG_DEBUG("Ignoring error on PFlash sector blank-check");
 					kinetis_ftfx_clear_error(bank->target);
 					bank->sectors[i].is_erased = -1;
 				}
diff --git a/src/flash/nor/kinetis_ke.c b/src/flash/nor/kinetis_ke.c
index 206d6f723..6afb3b9e6 100644
--- a/src/flash/nor/kinetis_ke.c
+++ b/src/flash/nor/kinetis_ke.c
@@ -1229,7 +1229,7 @@ static int kinetis_ke_blank_check(struct flash_bank *bank)
 			if (result == ERROR_OK)	{
 				bank->sectors[i].is_erased = !(fstat & (FTMRX_FSTAT_MGSTAT0_MASK | FTMRX_FSTAT_MGSTAT1_MASK));
 			} else {
-				LOG_DEBUG("Ignoring errored PFlash sector blank-check");
+				LOG_DEBUG("Ignoring error on PFlash sector blank-check");
 				bank->sectors[i].is_erased = -1;
 			}
 		}
diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index 6758b43dd..a1aa1df3e 100644
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -1170,7 +1170,7 @@ static int lpc2000_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
 				break;
 		}
 
-		/* Exit if error occured */
+		/* Exit if error occurred */
 		if (retval != ERROR_OK)
 			break;
 
@@ -1212,7 +1212,7 @@ static int lpc2000_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
 				break;
 		}
 
-		/* Exit if error occured */
+		/* Exit if error occurred */
 		if (retval != ERROR_OK)
 			break;
 
diff --git a/src/flash/nor/lpc288x.c b/src/flash/nor/lpc288x.c
index 13450ef82..1c10e5015 100644
--- a/src/flash/nor/lpc288x.c
+++ b/src/flash/nor/lpc288x.c
@@ -398,10 +398,10 @@ static int lpc288x_protect(struct flash_bank *bank, int set, unsigned int first,
 
 	for (unsigned int lockregion = first; lockregion <= last; lockregion++) {
 		if (set) {
-			/* write an odd value to base addy to protect... */
+			/* write an odd value to base address to protect... */
 			value = 0x01;
 		} else {
-			/* write an even value to base addy to unprotect... */
+			/* write an even value to base address to unprotect... */
 			value = 0x00;
 		}
 		target_write_u32(target, bank->sectors[lockregion].offset, value);
diff --git a/src/flash/nor/lpc2900.c b/src/flash/nor/lpc2900.c
index af8bba092..386c8bffe 100644
--- a/src/flash/nor/lpc2900.c
+++ b/src/flash/nor/lpc2900.c
@@ -49,8 +49,8 @@
 #define FTCTR           0x2020000C	/* Flash test control */
 #define FBWST           0x20200010	/* Flash bridge wait-state */
 #define FCRA            0x2020001C	/* Flash clock divider */
-#define FMSSTART        0x20200020	/* Flash Built-In Selft Test start address */
-#define FMSSTOP         0x20200024	/* Flash Built-In Selft Test stop address */
+#define FMSSTART        0x20200020	/* Flash Built-In Self Test start address */
+#define FMSSTOP         0x20200024	/* Flash Built-In Self Test stop address */
 #define FMS16           0x20200028	/* Flash 16-bit signature */
 #define FMSW0           0x2020002C	/* Flash 128-bit signature Word 0 */
 #define FMSW1           0x20200030	/* Flash 128-bit signature Word 1 */
@@ -160,7 +160,7 @@ struct lpc2900_flash_bank {
 
 	/**
 	 * Maximum contiguous block of internal SRAM (bytes).
-	 * Autodetected by the driver. Not the total amount of SRAM, only the
+	 * Autodetected by the driver. Not the total amount of SRAM, only
 	 * the largest \em contiguous block!
 	 */
 	uint32_t max_ram_block;
@@ -1535,7 +1535,7 @@ static int lpc2900_erase_check(struct flash_bank *bank)
 		return status;
 	}
 
-	/* Use the BIST (Built-In Selft Test) to generate a signature of each flash
+	/* Use the BIST (Built-In Self Test) to generate a signature of each flash
 	 * sector. Compare against the expected signature of an empty sector.
 	 */
 	for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
diff --git a/src/flash/nor/max32xxx.c b/src/flash/nor/max32xxx.c
index 65898cd64..c840bd795 100644
--- a/src/flash/nor/max32xxx.c
+++ b/src/flash/nor/max32xxx.c
@@ -80,7 +80,7 @@ struct max32xxx_flash_bank {
 	unsigned int burst_size_bits;
 };
 
-/* see contib/loaders/flash/max32xxx/max32xxx.s for src */
+/* see contrib/loaders/flash/max32xxx/max32xxx.s for src */
 static const uint8_t write_code[] = {
 #include "../../contrib/loaders/flash/max32xxx/max32xxx.inc"
 };
diff --git a/src/flash/nor/niietcm4.c b/src/flash/nor/niietcm4.c
index 085403885..2377e14f7 100644
--- a/src/flash/nor/niietcm4.c
+++ b/src/flash/nor/niietcm4.c
@@ -65,8 +65,8 @@
 #define FCIS_OP_ERROR				(1<<1)				/* Flag operation error */
 
 /*---- FCIC: CLear status register */
-#define FCIC_CLR_OPCMLT				(1<<0)				/* Cleare completion flag in register FCIS */
-#define FCIC_CLR_OPERROR			(1<<1)				/* Cleare error flag in register FCIS */
+#define FCIC_CLR_OPCMLT				(1<<0)				/* Clear completion flag in register FCIS */
+#define FCIC_CLR_OPERROR			(1<<1)				/* Clear error flag in register FCIS */
 
 /*-- USERFLASH ---------------------------------------------------------------*/
 #define USERFLASH_PAGE_SIZE			256
@@ -95,8 +95,8 @@
 #define UFCIS_OP_ERROR				(1<<1)				/* Flag operation error */
 
 /*---- UFCIC: CLear status register */
-#define UFCIC_CLR_OPCMLT			(1<<0)				/* Cleared completion flag in register FCIS */
-#define UFCIC_CLR_OPERROR			(1<<1)				/* Cleared error flag in register FCIS */
+#define UFCIC_CLR_OPCMLT			(1<<0)				/* Clear completion flag in register FCIS */
+#define UFCIC_CLR_OPERROR			(1<<1)				/* Clear error flag in register FCIS */
 
 /*---- In info userflash address space */
 #define INFOWORD0_ADDR				0x00
@@ -1226,7 +1226,7 @@ static int niietcm4_protect(struct flash_bank *bank, int set,
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	LOG_INFO("Plese wait ..."); /* it`s quite a long process */
+	LOG_INFO("Please wait ..."); /* it`s quite a long process */
 	/* chose between main bootflash and info bootflash */
 	if (niietcm4_info->bflash_info_remap) {
 		/* dump */
@@ -1416,7 +1416,7 @@ static int niietcm4_write(struct flash_bank *bank, const uint8_t *buffer,
 		/* if block write failed (no sufficient working area),
 		 * we use normal (slow) single halfword accesses */
 		LOG_WARNING("Can't use block writes, falling back to single memory accesses");
-		LOG_INFO("Plese wait ..."); /* it`s quite a long process */
+		LOG_INFO("Please wait ..."); /* it`s quite a long process */
 
 		/* chose between main bootflash and info bootflash */
 		if (niietcm4_info->bflash_info_remap)
@@ -1588,10 +1588,10 @@ static int niietcm4_probe_k1921vk01t(struct flash_bank *bank)
 		char info_bootflash_addr_str[64];
 		if (niietcm4_info->bflash_info_remap)
 			snprintf(info_bootflash_addr_str, sizeof(info_bootflash_addr_str),
-					TARGET_ADDR_FMT " base adress", bank->base);
+					TARGET_ADDR_FMT " base address", bank->base);
 		else
 			snprintf(info_bootflash_addr_str, sizeof(info_bootflash_addr_str),
-					"not mapped to global adress space");
+					"not mapped to global address space");
 
 		snprintf(niietcm4_info->chip_brief,
 				sizeof(niietcm4_info->chip_brief),
@@ -1600,7 +1600,7 @@ static int niietcm4_probe_k1921vk01t(struct flash_bank *bank)
 				"Bootflash :\n"
 				"    %d kB total\n"
 				"    %d pages %d kB each\n"
-				"    0x%08x base adress\n"
+				"    0x%08x base address\n"
 				"%s"
 				"Info bootflash :\n"
 				"    %d kB total\n"
@@ -1611,18 +1611,18 @@ static int niietcm4_probe_k1921vk01t(struct flash_bank *bank)
 				"    %d kB total\n"
 				"    %d pages %d B each\n"
 				"    %d bit cells\n"
-				"    not maped to global adress space\n"
+				"    not mapped to global address space\n"
 				"Info userflash :\n"
 				"    %d B total\n"
 				"    %d pages of %d B each\n"
 				"    %d bit cells\n"
-				"    not maped to global adress space\n"
+				"    not mapped to global address space\n"
 				"RAM :\n"
 				"    192 kB total\n"
-				"    0x20000000 base adress\n"
+				"    0x20000000 base address\n"
 				"External memory :\n"
 				"    8/16 bit address space\n"
-				"    0x%08x base adress\n"
+				"    0x%08x base address\n"
 				"\n"
 				"INFOWORD STATUS\n"
 				"Bootflash info region remap :\n"
diff --git a/src/flash/nor/non_cfi.c b/src/flash/nor/non_cfi.c
index f44adba13..a817966c6 100644
--- a/src/flash/nor/non_cfi.c
+++ b/src/flash/nor/non_cfi.c
@@ -483,7 +483,7 @@ void cfi_fixup_non_cfi(struct flash_bank *bank)
 			break;
 	}
 
-	/* only fixup jedec flashs found in table */
+	/* only fixup jedec flashes found in table */
 	if (!non_cfi->mfr)
 		return;
 
diff --git a/src/flash/nor/nrf5.c b/src/flash/nor/nrf5.c
index a79aa78b9..0ceb8d754 100644
--- a/src/flash/nor/nrf5.c
+++ b/src/flash/nor/nrf5.c
@@ -89,7 +89,7 @@ enum nrf5_ficr_registers {
 
 enum nrf5_uicr_registers {
 	NRF5_UICR_BASE = 0x10001000, /* User Information
-				       * Configuration Regsters */
+				       * Configuration Registers */
 
 #define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
 
@@ -256,7 +256,7 @@ static const struct nrf5_device_spec nrf5_known_devices_table[] = {
 	NRF51_DEVICE_DEF(0x007A, "51422", "CEAA", "C0",    256),
 	NRF51_DEVICE_DEF(0x0088, "51422", "CFAC", "A0",    256),
 
-	/* The driver fully autodects nRF52 series devices by FICR INFO,
+	/* The driver fully autodetects nRF52 series devices by FICR INFO,
 	 * no need for nRF52xxx HWIDs in this table */
 #if 0
 	/* nRF52810 Devices */
@@ -533,7 +533,7 @@ static int nrf5_protect(struct flash_bank *bank, int set, unsigned int first,
 	}
 
 	if (first != 0) {
-		LOG_ERROR("Code region 0 must start at the begining of the bank");
+		LOG_ERROR("Code region 0 must start at the beginning of the bank");
 		return ERROR_FAIL;
 	}
 
@@ -1363,7 +1363,7 @@ const struct flash_driver nrf5_flash = {
 };
 
 /* We need to retain the flash-driver name as well as the commands
- * for backwards compatability */
+ * for backwards compatibility */
 const struct flash_driver nrf51_flash = {
 	.name			= "nrf51",
 	.commands		= nrf5_command_handlers,
diff --git a/src/flash/nor/ocl.h b/src/flash/nor/ocl.h
index 3e83f76cf..b1fe308f2 100644
--- a/src/flash/nor/ocl.h
+++ b/src/flash/nor/ocl.h
@@ -22,7 +22,7 @@
 /* command/response mask */
 #define OCL_CMD_MASK 0xFFFF0000L
 
-/* commads */
+/* commands */
 #define OCL_FLASH_BLOCK 0x0CFB0000L
 #define OCL_ERASE_BLOCK 0x0CEB0000L
 #define OCL_ERASE_ALL 0x0CEA0000L
diff --git a/src/flash/nor/pic32mx.c b/src/flash/nor/pic32mx.c
index b214642a0..9b9185344 100644
--- a/src/flash/nor/pic32mx.c
+++ b/src/flash/nor/pic32mx.c
@@ -372,7 +372,7 @@ static int pic32mx_protect(struct flash_bank *bank, int set, unsigned int first,
 	return ERROR_OK;
 }
 
-/* see contib/loaders/flash/pic32mx.s for src */
+/* see contrib/loaders/flash/pic32mx.s for src */
 
 static uint32_t pic32mx_flash_write_code[] = {
 					/* write: */
diff --git a/src/flash/nor/psoc4.c b/src/flash/nor/psoc4.c
index be9a886a2..0c656349f 100644
--- a/src/flash/nor/psoc4.c
+++ b/src/flash/nor/psoc4.c
@@ -35,7 +35,7 @@
 #include <target/algorithm.h>
 #include <target/armv7m.h>
 
-/* device documets:
+/* device documents:
 
  PSoC(R) 4: PSoC 4200 Family Datasheet
 	Document Number: 001-87197 Rev. *B  Revised August 29, 2013
@@ -392,7 +392,7 @@ static int psoc4_get_silicon_id(struct flash_bank *bank, uint32_t *silicon_id, u
 	/* build ID as Cypress sw does:
 	 * bit 31..16 silicon ID
 	 * bit 15..8  revision ID (so far 0x11 for all devices)
-	 * bit 7..0   family ID (lowes 8 bits)
+	 * bit 7..0   family ID (lowest 8 bits)
 	 */
 	if (silicon_id)
 			*silicon_id = ((part0 & 0x0000ffff) << 16)
diff --git a/src/flash/nor/psoc5lp.c b/src/flash/nor/psoc5lp.c
index 17cc6d808..25a0ee025 100644
--- a/src/flash/nor/psoc5lp.c
+++ b/src/flash/nor/psoc5lp.c
@@ -47,7 +47,7 @@
 #define PANTHER_DEVICE_ID       0x4008001C
 
 /* NVL is not actually mapped to the Cortex-M address space
- * As we need a base addess different from other banks in the device
+ * As we need a base address different from other banks in the device
  * we use the address of NVL programming data in Cypress images */
 #define NVL_META_BASE			0x90000000
 
diff --git a/src/flash/nor/psoc6.c b/src/flash/nor/psoc6.c
index 3eb2fc26b..c7141738d 100644
--- a/src/flash/nor/psoc6.c
+++ b/src/flash/nor/psoc6.c
@@ -325,7 +325,7 @@ static int ipc_acquire(struct target *target, char ipc_id)
  * @brief Invokes SROM API functions which are responsible for Flash operations
  *
  * @param target current target
- * @param req_and_params requect id of the function to invoke
+ * @param req_and_params request id of the function to invoke
  * @param working_area address of memory buffer in target's memory space for SROM API parameters
  * @param data_out pointer to variable which will be populated with execution status
  * @return ERROR_OK in case of success, ERROR_XXX code otherwise
@@ -475,7 +475,7 @@ static int psoc6_protect(struct flash_bank *bank, int set, unsigned int first,
 /** ***********************************************************************************************
  * @brief Translates Protection status to string
  * @param protection protection value
- * @return pointer to const string describintg protection status
+ * @return pointer to const string describing protection status
  *************************************************************************************************/
 static const char *protection_to_str(uint8_t protection)
 {
@@ -574,7 +574,7 @@ static int psoc6_probe(struct flash_bank *bank)
 
 	int hr = ERROR_OK;
 
-	/* Retrieve data from SPCIF_GEOMATRY */
+	/* Retrieve data from SPCIF_GEOMETRY */
 	uint32_t geom;
 	target_read_u32(target, PSOC6_SPCIF_GEOMETRY, &geom);
 	uint32_t row_sz_lg2 = (geom & 0xF0) >> 4;
@@ -835,7 +835,7 @@ exit:
  * @brief Performs Program operation
  * @param bank current flash bank
  * @param buffer pointer to the buffer with data
- * @param offset starting offset in falsh bank
+ * @param offset starting offset in flash bank
  * @param count number of bytes in buffer
  * @return ERROR_OK in case of success, ERROR_XXX code otherwise
  *************************************************************************************************/
@@ -956,7 +956,7 @@ int handle_reset_halt(struct target *target)
 
 	const struct armv7m_common *cm = target_to_armv7m(target);
 
-	/* PSoC6 reboots immediatelly after issuing SYSRESETREQ / VECTRESET
+	/* PSoC6 reboots immediately after issuing SYSRESETREQ / VECTRESET
 	 * this disables SWD/JTAG pins momentarily and may break communication
 	 * Ignoring return value of mem_ap_write_atomic_u32 seems to be ok here */
 	if (is_cm0) {
diff --git a/src/flash/nor/sim3x.c b/src/flash/nor/sim3x.c
index d2d254e08..21449041c 100644
--- a/src/flash/nor/sim3x.c
+++ b/src/flash/nor/sim3x.c
@@ -250,7 +250,7 @@ static int sim3x_erase_page(struct flash_bank *bank, uint32_t addr)
 			if (ret != ERROR_OK)
 				return ret;
 
-			/* Write the inital unlock value to KEY */
+			/* Write the initial unlock value to KEY */
 			ret = target_write_u32(target, FLASHCTRL0_KEY,
 			FLASHCTRL0_KEY_INITIAL_UNLOCK);
 			if (ret != ERROR_OK)
@@ -490,7 +490,7 @@ static int sim3x_flash_write(struct flash_bank *bank, const uint8_t *buffer, uin
 	sim3x_info = bank->driver_priv;
 
 	if (sim3x_info->flash_locked) {
-		LOG_ERROR("Falsh is locked");
+		LOG_ERROR("Flash is locked");
 		return ERROR_FAIL;
 	}
 
@@ -1032,7 +1032,7 @@ COMMAND_HANDLER(sim3x_lock)
 		ret = target_read_u32(target, CPUID, &val);
 		/* if correct value is read, then it will continue */
 		if (ret != ERROR_OK || (val & CPUID_CHECK_VALUE_MASK) != CPUID_CHECK_VALUE) {
-			/* if correct value is'n read, then it will check SIM3X_AP_INIT_STAT register */
+			/* if correct value isn't read, then it will check SIM3X_AP_INIT_STAT register */
 			ret = ap_read_register(dap, SIM3X_AP_INIT_STAT, &val);
 			if (ret != ERROR_OK)
 				return ret;
diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c
index 9763644c5..34c9c28fe 100644
--- a/src/flash/nor/stellaris.c
+++ b/src/flash/nor/stellaris.c
@@ -487,7 +487,7 @@ static int get_stellaris_info(struct flash_bank *bank, char *buf, int buf_size)
 	if (stellaris_info->did1 == 0)
 		return ERROR_FLASH_BANK_NOT_PROBED;
 
-	/* Read main and master clock freqency register */
+	/* Read main and master clock frequency register */
 	stellaris_read_clock_info(bank);
 
 	printed = snprintf(buf,
@@ -533,7 +533,7 @@ static int get_stellaris_info(struct flash_bank *bank, char *buf, int buf_size)
 *	chip identification and status                                         *
 ***************************************************************************/
 
-/* Set the flash timimg register to match current clocking */
+/* Set the flash timing register to match current clocking */
 static void stellaris_set_flash_timing(struct flash_bank *bank)
 {
 	struct stellaris_flash_bank *stellaris_info = bank->driver_priv;
@@ -886,7 +886,7 @@ static int stellaris_erase(struct flash_bank *bank, unsigned int first,
 			target_read_u32(target, FLASH_FMC, &flash_fmc);
 		} while (flash_fmc & FMC_ERASE);
 
-		/* Check acess violations */
+		/* Check access violations */
 		target_read_u32(target, FLASH_CRIS, &flash_cris);
 		if (flash_cris & (AMASK)) {
 			LOG_WARNING("Error erasing flash page %i,  flash_cris 0x%" PRIx32 "",
@@ -998,7 +998,7 @@ static int stellaris_protect(struct flash_bank *bank, int set,
 	return ERROR_OK;
 }
 
-/* see contib/loaders/flash/stellaris.s for src */
+/* see contrib/loaders/flash/stellaris.s for src */
 
 static const uint8_t stellaris_write_code[] = {
 								/* write: */
@@ -1170,7 +1170,7 @@ static int stellaris_write(struct flash_bank *bank, const uint8_t *buffer,
 			if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 				LOG_DEBUG("writing flash word-at-a-time");
 			} else if (retval == ERROR_FLASH_OPERATION_FAILED) {
-				/* if an error occured, we examine the reason, and quit */
+				/* if an error occurred, we examine the reason, and quit */
 				target_read_u32(target, FLASH_CRIS, &flash_cris);
 
 				LOG_ERROR("flash writing failed with CRIS: 0x%" PRIx32 "", flash_cris);
diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c
index f07f24aae..6510e75dc 100644
--- a/src/flash/nor/stm32f2x.c
+++ b/src/flash/nor/stm32f2x.c
@@ -55,7 +55,7 @@
  * can be very different.
  *
  * To reduce testing complexity and dangers of regressions,
- * a seperate file is used for stm32fx2x.
+ * a separate file is used for stm32fx2x.
  *
  * Sector sizes in kiBytes:
  * 1 MiByte part with 4 x 16, 1 x 64, 7 x 128.
@@ -419,7 +419,7 @@ static int stm32x_read_options(struct flash_bank *bank)
 		if (retval != ERROR_OK)
 			return retval;
 
-		/* FLASH_OPTCR1 has quite diffent meanings ... */
+		/* FLASH_OPTCR1 has quite different meanings ... */
 		if (stm32x_info->has_boot_addr) {
 			/* for F7xx it contains boot0 and boot1 */
 			stm32x_info->option_bytes.boot_addr = optiondata;
@@ -1026,7 +1026,7 @@ static int stm32x_probe(struct flash_bank *bank)
 		bank->prot_blocks = NULL;
 	}
 
-	/* if explicitely called out as OTP bank, short circuit probe */
+	/* if explicitly called out as OTP bank, short circuit probe */
 	if (stm32x_is_otp(bank)) {
 		if (stm32x_otp_is_f7(bank)) {
 			otp_size_in_b = STM32F7_OTP_SIZE;
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index edd013048..c56bd6d60 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -534,7 +534,7 @@ static int stm32l4_protect_check(struct flash_bank *bank)
 		stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2AR, &wrp2ar);
 		stm32l4_read_flash_reg(bank, STM32_FLASH_WRP2BR, &wrp2br);
 	} else {
-		/* prevent unintialized errors */
+		/* prevent uninitialized errors */
 		wrp2ar = 0;
 		wrp2br = 0;
 	}
diff --git a/src/flash/nor/stm32lx.c b/src/flash/nor/stm32lx.c
index 9c817c994..cf5b36040 100644
--- a/src/flash/nor/stm32lx.c
+++ b/src/flash/nor/stm32lx.c
@@ -629,7 +629,7 @@ static int stm32lx_write(struct flash_bank *bank, const uint8_t *buffer,
 	if (retval != ERROR_OK)
 		return retval;
 
-	/* first we need to write any unaligned head bytes upto
+	/* first we need to write any unaligned head bytes up to
 	 * the next 128 byte page */
 
 	if (offset % hp_nb)
diff --git a/src/flash/nor/str7x.c b/src/flash/nor/str7x.c
index dd72f538a..e028c1ffd 100644
--- a/src/flash/nor/str7x.c
+++ b/src/flash/nor/str7x.c
@@ -452,7 +452,7 @@ static int str7x_write_block(struct flash_bank *bank, const uint8_t *buffer,
 	struct arm_algorithm arm_algo;
 	int retval = ERROR_OK;
 
-	/* see contib/loaders/flash/str7x.s for src */
+	/* see contrib/loaders/flash/str7x.s for src */
 
 	static const uint32_t str7x_flash_write_code[] = {
 					/* write:				*/
diff --git a/src/flash/nor/str9x.c b/src/flash/nor/str9x.c
index d49875c5a..87ffec877 100644
--- a/src/flash/nor/str9x.c
+++ b/src/flash/nor/str9x.c
@@ -354,7 +354,7 @@ static int str9x_write_block(struct flash_bank *bank,
 	struct arm_algorithm arm_algo;
 	int retval = ERROR_OK;
 
-	/* see contib/loaders/flash/str9x.s for src */
+	/* see contrib/loaders/flash/str9x.s for src */
 
 	static const uint32_t str9x_flash_write_code[] = {
 					/* write:				*/
diff --git a/src/flash/nor/tms470.c b/src/flash/nor/tms470.c
index 0d3f487d9..4b8d2208a 100644
--- a/src/flash/nor/tms470.c
+++ b/src/flash/nor/tms470.c
@@ -722,7 +722,7 @@ static int tms470_erase_sector(struct flash_bank *bank, int sector)
 	bank->sectors[sector].is_protected = 0;
 
 	/*
-	 * clear status regiser, sent erase command, kickoff erase
+	 * clear status register, sent erase command, kickoff erase
 	 */
 	target_write_u16(target, flashAddr, 0x0040);
 	LOG_DEBUG("write *(uint16_t *)0x%08" PRIx32 "=0x0040", flashAddr);
@@ -865,7 +865,7 @@ static int tms470_protect(struct flash_bank *bank, int set, unsigned int first,
 	target_read_u32(target, 0xFFE8BC04, &fmmac2);
 	target_write_u32(target, 0xFFE8BC04, (fmmac2 & ~7) | tms470_info->ordinal);
 
-	/* get the original sector proection flags for this bank */
+	/* get the original sector protection flags for this bank */
 	target_read_u32(target, 0xFFE88008, &fmbsea);
 	target_read_u32(target, 0xFFE8800C, &fmbseb);
 
diff --git a/src/flash/nor/w600.c b/src/flash/nor/w600.c
index 714b27db2..479082177 100644
--- a/src/flash/nor/w600.c
+++ b/src/flash/nor/w600.c
@@ -347,7 +347,7 @@ static int w600_probe(struct flash_bank *bank)
 		bank->sectors[i].offset = i * W600_FLASH_SECSIZE;
 		bank->sectors[i].size = W600_FLASH_SECSIZE;
 		bank->sectors[i].is_erased = -1;
-		/* offset 0 to W600_FLASH_PROTECT_SIZE shoule be protected */
+		/* offset 0 to W600_FLASH_PROTECT_SIZE should be protected */
 		bank->sectors[i].is_protected = (i < W600_FLASH_PROTECT_SIZE / W600_FLASH_SECSIZE);
 	}
 
diff --git a/src/flash/nor/xmc4xxx.c b/src/flash/nor/xmc4xxx.c
index aa26693ec..a032e4d46 100644
--- a/src/flash/nor/xmc4xxx.c
+++ b/src/flash/nor/xmc4xxx.c
@@ -1197,7 +1197,7 @@ static int xmc4xxx_protect_check(struct flash_bank *bank)
 
 	unsigned int sectors = bank->num_sectors;
 
-	/* On devices with 12 sectors, sectors 10 & 11 are ptected
+	/* On devices with 12 sectors, sectors 10 & 11 are protected
 	 * together instead of individually */
 	if (sectors == 12)
 		sectors--;
@@ -1237,7 +1237,7 @@ static int xmc4xxx_protect_check(struct flash_bank *bank)
 		}
 	}
 
-	/* XMC4xxx also supports read proptection, make a note
+	/* XMC4xxx also supports read protection, make a note
 	 * in the private driver structure */
 	if (protection[0] & PROCON_RPRO_MASK)
 		fb->read_protected = true;

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nand/driver.h         |  2 +-
 src/flash/nand/fileio.c         |  2 +-
 src/flash/nand/lpc3180.c        |  2 +-
 src/flash/nand/lpc32xx.c        | 24 ++++++++++++------------
 src/flash/nand/mx3.c            | 16 ++++++++--------
 src/flash/nand/mxc.c            | 12 ++++++------
 src/flash/nor/at91sam3.c        |  6 +++---
 src/flash/nor/at91sam4.c        |  6 +++---
 src/flash/nor/at91sam7.c        |  8 ++++----
 src/flash/nor/at91samd.c        |  6 +++---
 src/flash/nor/atsame5.c         |  6 +++---
 src/flash/nor/atsamv.c          |  2 +-
 src/flash/nor/cfi.c             | 18 +++++++++---------
 src/flash/nor/core.h            |  2 +-
 src/flash/nor/driver.h          |  6 +++---
 src/flash/nor/dsp5680xx_flash.c |  2 +-
 src/flash/nor/em357.c           |  2 +-
 src/flash/nor/fm3.c             |  4 ++--
 src/flash/nor/kinetis.c         |  8 ++++----
 src/flash/nor/kinetis_ke.c      |  2 +-
 src/flash/nor/lpc2000.c         |  4 ++--
 src/flash/nor/lpc288x.c         |  4 ++--
 src/flash/nor/lpc2900.c         |  8 ++++----
 src/flash/nor/max32xxx.c        |  2 +-
 src/flash/nor/niietcm4.c        | 26 +++++++++++++-------------
 src/flash/nor/non_cfi.c         |  2 +-
 src/flash/nor/nrf5.c            |  8 ++++----
 src/flash/nor/ocl.h             |  2 +-
 src/flash/nor/pic32mx.c         |  2 +-
 src/flash/nor/psoc4.c           |  4 ++--
 src/flash/nor/psoc5lp.c         |  2 +-
 src/flash/nor/psoc6.c           | 10 +++++-----
 src/flash/nor/sim3x.c           |  6 +++---
 src/flash/nor/stellaris.c       | 10 +++++-----
 src/flash/nor/stm32f2x.c        |  6 +++---
 src/flash/nor/stm32l4x.c        |  2 +-
 src/flash/nor/stm32lx.c         |  2 +-
 src/flash/nor/str7x.c           |  2 +-
 src/flash/nor/str9x.c           |  2 +-
 src/flash/nor/tms470.c          |  4 ++--
 src/flash/nor/w600.c            |  2 +-
 src/flash/nor/xmc4xxx.c         |  4 ++--
 src/rtos/FreeRTOS.c             |  2 +-
 src/rtos/chromium-ec.c          |  2 +-
 src/rtos/linux.c                |  2 +-
 src/rtos/nuttx.c                |  2 +-
 src/rtos/rtos.c                 |  2 +-
 src/server/gdb_server.c         |  6 +++---
 src/server/server.c             |  2 +-
 49 files changed, 134 insertions(+), 134 deletions(-)


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From: OpenOCD-Gerrit <ope...@us...> - 2020-07-26 19:14:07

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- Log -----------------------------------------------------------------
commit f5cc8360fdf4c004c9efa2132645f9319ceef49d
Author: Antonio Borneo <bor...@gm...>
Date:   Mon May 25 11:19:07 2020 +0200

    target/arm720t: fix memory leak of register cache
    
    There is no method to free the register cache, allocated in
    arm720t_init_target().
    Issue identified by tracking all calls to arm7tdmi_init_target().
    
    Implement the method arm720t_deinit_target() by calling directly
    arm7tdmi_deinit_target().
    
    NOT TESTED on a real arm720t target.
    Tested on a arm926ejs (SPEAr320) by hacking the target type and
    pretending it is a xscale:
            sed -i s/arm926ejs/arm720t/ tcl/target/spear3xx.cfg
    
    Change-Id: I53c1f46c1a355a710e8df01468b19220671569dc
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5697
    Tested-by: jenkins

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index abe5f1cea..e04cab2e7 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -391,6 +391,11 @@ static int arm720t_init_target(struct command_context *cmd_ctx, struct target *t
 	return arm7tdmi_init_target(cmd_ctx, target);
 }
 
+static void arm720t_deinit_target(struct target *target)
+{
+	arm7tdmi_deinit_target(target);
+}
+
 /* FIXME remove forward decls */
 static int arm720t_mrc(struct target *target, int cpnum,
 		uint32_t op1, uint32_t op2,
@@ -583,6 +588,7 @@ struct target_type arm720t_target = {
 	.commands = arm720t_command_handlers,
 	.target_create = arm720t_target_create,
 	.init_target = arm720t_init_target,
+	.deinit_target = arm720t_deinit_target,
 	.examine = arm7_9_examine,
 	.check_reset = arm7_9_check_reset,
 };

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm720t.c | 6 ++++++
 1 file changed, 6 insertions(+)


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       via  df1dcc27eeb3a42d3dd9708c9518a2230242f746 (commit)
       via  580b8f5da015f49b5ca939ed4fd928b8d941944e (commit)
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Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 19aa77cc7fc369af2da9ca1b1539161284f90286
Author: Antonio Borneo <bor...@gm...>
Date:   Mon May 25 10:58:40 2020 +0200

    target/arm7tdmi: fix memory leak of register cache
    
    There is no method to free the register cache, allocated in
    arm7tdmi_init_target(), so we get a memory leak.
    Issue identified by tracking all calls to arm_build_reg_cache().
    
    Implement the method arm7tdmi_deinit_target() that in turn calls
    arm7tdmi_free_reg_cache().
    
    NOT TESTED on a real arm7tdmi target.
    Tested on a arm926ejs (SPEAr320) by hacking the target type and
    pretending it is a arm7tdmi:
            sed -i s/arm926ejs/arm7tdmi/ tcl/target/spear3xx.cfg
    
    Change-Id: Iad465b708eb4ebb298725d7155fea76357e9045c
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5696
    Tested-by: jenkins

diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index e1e91c3a0..01685ab6a 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -613,6 +613,13 @@ static void arm7tdmi_build_reg_cache(struct target *target)
 	(*cache_p) = arm_build_reg_cache(target, arm);
 }
 
+static void arm7tdmi_free_reg_cache(struct target *target)
+{
+	struct arm *arm = target_to_arm(target);
+
+	arm_free_reg_cache(arm);
+}
+
 int arm7tdmi_init_target(struct command_context *cmd_ctx, struct target *target)
 {
 	arm7tdmi_build_reg_cache(target);
@@ -620,6 +627,11 @@ int arm7tdmi_init_target(struct command_context *cmd_ctx, struct target *target)
 	return ERROR_OK;
 }
 
+void arm7tdmi_deinit_target(struct target *target)
+{
+	arm7tdmi_free_reg_cache(target);
+}
+
 int arm7tdmi_init_arch_info(struct target *target,
 		struct arm7_9_common *arm7_9, struct jtag_tap *tap)
 {
@@ -718,6 +730,7 @@ struct target_type arm7tdmi_target = {
 	.commands  = arm7_9_command_handlers,
 	.target_create  = arm7tdmi_target_create,
 	.init_target = arm7tdmi_init_target,
+	.deinit_target = arm7tdmi_deinit_target,
 	.examine = arm7_9_examine,
 	.check_reset = arm7_9_check_reset,
 };
diff --git a/src/target/arm7tdmi.h b/src/target/arm7tdmi.h
index 053f64df8..3cc3d4a7b 100644
--- a/src/target/arm7tdmi.h
+++ b/src/target/arm7tdmi.h
@@ -28,5 +28,6 @@ int arm7tdmi_init_arch_info(struct target *target,
 		struct arm7_9_common *arm7_9, struct jtag_tap *tap);
 int arm7tdmi_init_target(struct command_context *cmd_ctx,
 		struct target *target);
+void arm7tdmi_deinit_target(struct target *target);
 
 #endif /* OPENOCD_TARGET_ARM7TDMI_H */

commit df1dcc27eeb3a42d3dd9708c9518a2230242f746
Author: Antonio Borneo <bor...@gm...>
Date:   Mon May 25 10:43:53 2020 +0200

    target/xscale: fix memory leak of register cache
    
    There is no method to free the register cache, allocated in
    xscale_build_reg_cache(), so we get a memory leak.
    Issue identified by tracking all calls to arm_build_reg_cache().
    
    Implement the method xscale_deinit_target() that in turn calls the
    new xscale_free_reg_cache().
    Fix leak of struct xscale.
    
    NOT TESTED on a real xscale target.
    Tested on a arm926ejs (SPEAr320) by hacking the target type and
    pretending it is a xscale:
            sed -i s/arm926ejs/xscale/ tcl/target/spear3xx.cfg
    
    Change-Id: Ibb2104c42411b76f4bb77c2fa387d1b85a3d2d5d
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5695
    Tested-by: jenkins

diff --git a/src/target/xscale.c b/src/target/xscale.c
index edab4f9fc..1bca96d73 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -2903,6 +2903,21 @@ static void xscale_build_reg_cache(struct target *target)
 	xscale->reg_cache = (*cache_p);
 }
 
+static void xscale_free_reg_cache(struct target *target)
+{
+	struct xscale_common *xscale = target_to_xscale(target);
+	struct reg_cache *cache = xscale->reg_cache;
+
+	for (unsigned int i = 0; i < ARRAY_SIZE(xscale_reg_arch_info); i++)
+		free(cache->reg_list[i].value);
+
+	free(cache->reg_list[0].arch_info);
+	free(cache->reg_list);
+	free(cache);
+
+	arm_free_reg_cache(&xscale->arm);
+}
+
 static int xscale_init_target(struct command_context *cmd_ctx,
 	struct target *target)
 {
@@ -2910,6 +2925,14 @@ static int xscale_init_target(struct command_context *cmd_ctx,
 	return ERROR_OK;
 }
 
+static void xscale_deinit_target(struct target *target)
+{
+	struct xscale_common *xscale = target_to_xscale(target);
+
+	xscale_free_reg_cache(target);
+	free(xscale);
+}
+
 static int xscale_init_arch_info(struct target *target,
 	struct xscale_common *xscale, struct jtag_tap *tap)
 {
@@ -3725,6 +3748,7 @@ struct target_type xscale_target = {
 	.commands = xscale_command_handlers,
 	.target_create = xscale_target_create,
 	.init_target = xscale_init_target,
+	.deinit_target = xscale_deinit_target,
 
 	.virt2phys = xscale_virt2phys,
 	.mmu = xscale_mmu

commit 580b8f5da015f49b5ca939ed4fd928b8d941944e
Author: Antonio Borneo <bor...@gm...>
Date:   Mon May 25 11:28:22 2020 +0200

    target: fix memory leaks on targets based on arm9tdmi
    
    Similarly to the fix for arm926ejs (also base on arm9tdmi), fix
    the other targets based on arm9tdmi.
    The fix for arm926ejs is tested on SPEAr320 target.
    
    This fix is proposed separately because is not tested on a correct
    target device, but tested on SPEAr320 by hacking the target type
    and pretending it is the correct one, e.g.:
            sed -i s/arm926ejs/arm920t/ tcl/target/spear3xx.cfg
    
    The memory leaks detected and fixed are:
    - arm register cache;
    - EmbeddedICE register cache;
    - arm_jtag_reset_callback internal data;
    - struct <target_type>_common.
    
    Change-Id: I565f9a5bf144a9df78474434d86a64127ef0fbe5
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5699
    Tested-by: jenkins

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 3ddd19888..c96975a77 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -852,6 +852,16 @@ static int arm920t_target_create(struct target *target, Jim_Interp *interp)
 	return arm920t_init_arch_info(target, arm920t, target->tap);
 }
 
+static void arm920t_deinit_target(struct target *target)
+{
+	struct arm *arm = target_to_arm(target);
+	struct arm920t_common *arm920t = target_to_arm920(target);
+
+	arm7_9_deinit(target);
+	arm_free_reg_cache(arm);
+	free(arm920t);
+}
+
 COMMAND_HANDLER(arm920t_handle_read_cache_command)
 {
 	int retval = ERROR_OK;
@@ -1716,6 +1726,7 @@ struct target_type arm920t_target = {
 	.commands = arm920t_command_handlers,
 	.target_create = arm920t_target_create,
 	.init_target = arm9tdmi_init_target,
+	.deinit_target = arm920t_deinit_target,
 	.examine = arm7_9_examine,
 	.check_reset = arm7_9_check_reset,
 };
diff --git a/src/target/arm946e.c b/src/target/arm946e.c
index 4ef167a9d..6b187f3ff 100644
--- a/src/target/arm946e.c
+++ b/src/target/arm946e.c
@@ -99,6 +99,16 @@ static int arm946e_target_create(struct target *target, Jim_Interp *interp)
 	return ERROR_OK;
 }
 
+static void arm946e_deinit_target(struct target *target)
+{
+	struct arm *arm = target_to_arm(target);
+	struct arm946e_common *arm946e = target_to_arm946(target);
+
+	arm7_9_deinit(target);
+	arm_free_reg_cache(arm);
+	free(arm946e);
+}
+
 static int arm946e_verify_pointer(struct command_invocation *cmd,
 	struct arm946e_common *arm946e)
 {
@@ -776,6 +786,7 @@ struct target_type arm946e_target = {
 	.commands = arm946e_command_handlers,
 	.target_create = arm946e_target_create,
 	.init_target = arm9tdmi_init_target,
+	.deinit_target = arm946e_deinit_target,
 	.examine = arm7_9_examine,
 	.check_reset = arm7_9_check_reset,
 };
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index 8462f546e..8ddcb3c79 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -56,6 +56,16 @@ static int arm966e_target_create(struct target *target, Jim_Interp *interp)
 	return arm966e_init_arch_info(target, arm966e, target->tap);
 }
 
+static void arm966e_deinit_target(struct target *target)
+{
+	struct arm *arm = target_to_arm(target);
+	struct arm966e_common *arm966e = target_to_arm966(target);
+
+	arm7_9_deinit(target);
+	arm_free_reg_cache(arm);
+	free(arm966e);
+}
+
 static int arm966e_verify_pointer(struct command_invocation *cmd,
 		struct arm966e_common *arm966e)
 {
@@ -278,6 +288,7 @@ struct target_type arm966e_target = {
 	.commands = arm966e_command_handlers,
 	.target_create = arm966e_target_create,
 	.init_target = arm9tdmi_init_target,
+	.deinit_target = arm966e_deinit_target,
 	.examine = arm7_9_examine,
 	.check_reset = arm7_9_check_reset,
 };
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 6ab06edf9..4810c2b16 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -786,6 +786,16 @@ static int arm9tdmi_target_create(struct target *target, Jim_Interp *interp)
 	return ERROR_OK;
 }
 
+void arm9tdmi_deinit_target(struct target *target)
+{
+	struct arm *arm = target_to_arm(target);
+	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+
+	arm7_9_deinit(target);
+	arm_free_reg_cache(arm);
+	free(arm7_9);
+}
+
 COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
 {
 	struct target *target = get_current_target(CMD_CTX);
@@ -921,6 +931,7 @@ struct target_type arm9tdmi_target = {
 	.commands = arm9tdmi_command_handlers,
 	.target_create = arm9tdmi_target_create,
 	.init_target = arm9tdmi_init_target,
+	.deinit_target = arm9tdmi_deinit_target,
 	.examine = arm7_9_examine,
 	.check_reset = arm7_9_check_reset,
 };
diff --git a/src/target/arm9tdmi.h b/src/target/arm9tdmi.h
index c6f0ccf0f..56946f78a 100644
--- a/src/target/arm9tdmi.h
+++ b/src/target/arm9tdmi.h
@@ -26,6 +26,7 @@
 
 int arm9tdmi_init_target(struct command_context *cmd_ctx,
 		struct target *target);
+void arm9tdmi_deinit_target(struct target *target);
 int arm9tdmi_init_arch_info(struct target *target,
 		struct arm7_9_common *arm7_9, struct jtag_tap *tap);
 extern const struct command_registration arm9tdmi_command_handlers[];
diff --git a/src/target/fa526.c b/src/target/fa526.c
index bb9f7353a..aa9e45043 100644
--- a/src/target/fa526.c
+++ b/src/target/fa526.c
@@ -347,6 +347,16 @@ static int fa526_target_create(struct target *target, Jim_Interp *interp)
 	return fa526_init_arch_info(target, arm920t, target->tap);
 }
 
+static void fa526_deinit_target(struct target *target)
+{
+	struct arm *arm = target_to_arm(target);
+	struct arm920t_common *arm920t = target_to_arm920(target);
+
+	arm7_9_deinit(target);
+	arm_free_reg_cache(arm);
+	free(arm920t);
+}
+
 /** Holds methods for FA526 targets. */
 struct target_type fa526_target = {
 	.name = "fa526",
@@ -383,6 +393,7 @@ struct target_type fa526_target = {
 	.commands = arm920t_command_handlers,
 	.target_create = fa526_target_create,
 	.init_target = arm9tdmi_init_target,
+	.deinit_target = fa526_deinit_target,
 	.examine = arm7_9_examine,
 	.check_reset = arm7_9_check_reset,
 };
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 4a6c6dcf0..d2b707d44 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -593,6 +593,11 @@ static int feroceon_init_target(struct command_context *cmd_ctx,
 	return ERROR_OK;
 }
 
+static void feroceon_deinit_target(struct target *target)
+{
+	arm9tdmi_deinit_target(target);
+}
+
 static void feroceon_common_setup(struct target *target)
 {
 	struct arm *arm = target->arch_info;
@@ -729,6 +734,7 @@ struct target_type feroceon_target = {
 	.commands = arm926ejs_command_handlers,
 	.target_create = feroceon_target_create,
 	.init_target = feroceon_init_target,
+	.deinit_target = feroceon_deinit_target,
 	.examine = feroceon_examine,
 };
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm7tdmi.c | 13 +++++++++++++
 src/target/arm7tdmi.h |  1 +
 src/target/arm920t.c  | 11 +++++++++++
 src/target/arm946e.c  | 11 +++++++++++
 src/target/arm966e.c  | 11 +++++++++++
 src/target/arm9tdmi.c | 11 +++++++++++
 src/target/arm9tdmi.h |  1 +
 src/target/fa526.c    | 11 +++++++++++
 src/target/feroceon.c |  6 ++++++
 src/target/xscale.c   | 24 ++++++++++++++++++++++++
 10 files changed, 100 insertions(+)


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- Log -----------------------------------------------------------------
commit 6a78c8581d81665969f24563faccd220de517961
Author: Daniel Krebs <gi...@da...>
Date:   Mon Oct 5 15:37:57 2015 +0200

    rtos: add support for RIOT
    
    Add threads support for RIOT (https://github.com/RIOT-OS/RIOT).
    Original code is from Daniel Krebs.
    
    Change-Id: I83fe3b91dd75949e800b5aea1015d8fa37b09c61
    Signed-off-by: Daniel Krebs <gi...@da...>
    Signed-off-by: Vincent Dupont <vi...@ot...>
    Signed-off-by: Benjamin Valentin <ben...@go...>
    Reviewed-on: http://openocd.zylin.com/4256
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 6b461a30e..7a9b090d0 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4637,7 +4637,8 @@ The value should normally correspond to a static mapping for the
 @item @code{-rtos} @var{rtos_type} -- enable rtos support for target,
 @var{rtos_type} can be one of @option{auto}, @option{eCos},
 @option{ThreadX}, @option{FreeRTOS}, @option{linux}, @option{ChibiOS},
-@option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx}
+@option{embKernel}, @option{mqx}, @option{uCOS-III}, @option{nuttx},
+@option{RIOT}
 @xref{gdbrtossupport,,RTOS Support}.
 
 @item @code{-defer-examine} -- skip target examination at initial JTAG chain
@@ -10556,6 +10557,7 @@ Currently supported rtos's include:
 @item @option{mqx}
 @item @option{uCOS-III}
 @item @option{nuttx}
+@item @option{RIOT}
 @item @option{hwthread} (This is not an actual RTOS. @xref{usingopenocdsmpwithgdb,,Using OpenOCD SMP with GDB}.)
 @end itemize
 
@@ -10592,6 +10594,8 @@ _mqx_kernel_data, MQX_init_struct.
 OSRunning, OSTCBCurPtr, OSTaskDbgListPtr, OSTaskQty
 @item nuttx symbols
 g_readytorun, g_tasklisttable
+@item RIOT symbols
+sched_threads, sched_num_threads, sched_active_pid, max_threads, _tcb_name_offset
 @end table
 
 For most RTOS supported the above symbols will be exported by default. However for
diff --git a/src/rtos/Makefile.am b/src/rtos/Makefile.am
index 6a2fc1223..de54596cd 100644
--- a/src/rtos/Makefile.am
+++ b/src/rtos/Makefile.am
@@ -7,6 +7,7 @@ noinst_LTLIBRARIES += %D%/librtos.la
 	%D%/rtos_embkernel_stackings.c \
 	%D%/rtos_mqx_stackings.c \
 	%D%/rtos_ucos_iii_stackings.c \
+	%D%/rtos_riot_stackings.c \
 	%D%/FreeRTOS.c \
 	%D%/ThreadX.c \
 	%D%/eCos.c \
@@ -18,6 +19,7 @@ noinst_LTLIBRARIES += %D%/librtos.la
 	%D%/uCOS-III.c \
 	%D%/nuttx.c \
 	%D%/hwthread.c \
+	%D%/riot.c \
 	%D%/rtos.h \
 	%D%/rtos_standard_stackings.h \
 	%D%/rtos_ecos_stackings.h \
@@ -25,6 +27,7 @@ noinst_LTLIBRARIES += %D%/librtos.la
 	%D%/rtos_chibios_stackings.h \
 	%D%/rtos_embkernel_stackings.h \
 	%D%/rtos_mqx_stackings.h \
+	%D%/rtos_riot_stackings.h \
 	%D%/rtos_ucos_iii_stackings.h \
 	%D%/nuttx_header.h
 
diff --git a/src/rtos/riot.c b/src/rtos/riot.c
new file mode 100644
index 000000000..15cbb0f85
--- /dev/null
+++ b/src/rtos/riot.c
@@ -0,0 +1,428 @@
+/***************************************************************************
+ *   Copyright (C) 2015 by Daniel Krebs                                    *
+ *   Daniel Krebs - gi...@da...                                *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <helper/time_support.h>
+#include <jtag/jtag.h>
+#include "target/target.h"
+#include "target/target_type.h"
+#include "rtos.h"
+#include "helper/log.h"
+#include "helper/types.h"
+#include "target/armv7m.h"
+#include "rtos_riot_stackings.h"
+
+static bool riot_detect_rtos(struct target *target);
+static int riot_create(struct target *target);
+static int riot_update_threads(struct rtos *rtos);
+static int riot_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
+	struct rtos_reg **reg_list, int *num_regs);
+static int riot_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[]);
+
+struct riot_thread_state {
+	int value;
+	const char *desc;
+};
+
+/* refer RIOT sched.h */
+static const struct riot_thread_state riot_thread_states[] = {
+	{ 0, "Stopped" },
+	{ 1, "Zombie" },
+	{ 2, "Sleeping" },
+	{ 3, "Blocked mutex" },
+	{ 4, "Blocked receive" },
+	{ 5, "Blocked send" },
+	{ 6, "Blocked reply" },
+	{ 7, "Blocked any flag" },
+	{ 8, "Blocked all flags" },
+	{ 9, "Blocked mbox" },
+	{ 10, "Blocked condition" },
+	{ 11, "Running" },
+	{ 12, "Pending" },
+};
+#define RIOT_NUM_STATES ARRAY_SIZE(riot_thread_states)
+
+struct riot_params {
+	const char *target_name;
+	unsigned char thread_sp_offset;
+	unsigned char thread_status_offset;
+};
+
+static const struct riot_params riot_params_list[] = {
+	{
+		"cortex_m",		/* target_name */
+		0x00,					/* thread_sp_offset */
+		0x04,					/* thread_status_offset */
+	},
+	{	/* STLink */
+		"hla_target",		/* target_name */
+		0x00,			/* thread_sp_offset */
+		0x04,			/* thread_status_offset */
+	}
+};
+#define RIOT_NUM_PARAMS ARRAY_SIZE(riot_params_list)
+
+/* Initialize in riot_create() depending on architecture */
+static const struct rtos_register_stacking *stacking_info;
+
+enum riot_symbol_values {
+	RIOT_THREADS_BASE = 0,
+	RIOT_NUM_THREADS,
+	RIOT_ACTIVE_PID,
+	RIOT_MAX_THREADS,
+	RIOT_NAME_OFFSET,
+};
+
+/* refer RIOT core/sched.c */
+static const char *const riot_symbol_list[] = {
+	"sched_threads",
+	"sched_num_threads",
+	"sched_active_pid",
+	"max_threads",
+	"_tcb_name_offset",
+	NULL
+};
+
+/* Define which symbols are not mandatory */
+static const enum riot_symbol_values riot_optional_symbols[] = {
+	RIOT_NAME_OFFSET,
+};
+
+const struct rtos_type riot_rtos = {
+	.name = "RIOT",
+	.detect_rtos = riot_detect_rtos,
+	.create = riot_create,
+	.update_threads = riot_update_threads,
+	.get_thread_reg_list = riot_get_thread_reg_list,
+	.get_symbol_list_to_lookup = riot_get_symbol_list_to_lookup,
+};
+
+static int riot_update_threads(struct rtos *rtos)
+{
+	int retval;
+	unsigned int tasks_found = 0;
+	const struct riot_params *param;
+
+	if (rtos == NULL)
+		return ERROR_FAIL;
+
+	if (rtos->rtos_specific_params == NULL)
+		return ERROR_FAIL;
+
+	param = (const struct riot_params *)rtos->rtos_specific_params;
+
+	if (rtos->symbols == NULL) {
+		LOG_ERROR("No symbols for RIOT");
+		return ERROR_FAIL;
+	}
+
+	if (rtos->symbols[RIOT_THREADS_BASE].address == 0) {
+		LOG_ERROR("Can't find symbol `%s`",
+			riot_symbol_list[RIOT_THREADS_BASE]);
+		return ERROR_FAIL;
+	}
+
+	/* wipe out previous thread details if any */
+	rtos_free_threadlist(rtos);
+
+	/* Reset values */
+	rtos->current_thread = 0;
+	rtos->thread_count = 0;
+
+	/* read the current thread id */
+	int16_t active_pid = 0;
+	retval = target_read_u16(rtos->target,
+			rtos->symbols[RIOT_ACTIVE_PID].address,
+			(uint16_t *)&active_pid);
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Can't read symbol `%s`",
+			riot_symbol_list[RIOT_ACTIVE_PID]);
+		return retval;
+	}
+	rtos->current_thread = active_pid;
+
+	/* read the current thread count
+	 * It's `int` in RIOT, but this is Cortex M* only anyway */
+	int32_t thread_count = 0;
+	retval = target_read_u16(rtos->target,
+			rtos->symbols[RIOT_NUM_THREADS].address,
+			(uint16_t *)&thread_count);
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Can't read symbol `%s`",
+			riot_symbol_list[RIOT_NUM_THREADS]);
+		return retval;
+	}
+	rtos->thread_count = thread_count;
+
+	/* read the maximum number of threads */
+	uint8_t max_threads = 0;
+	retval = target_read_u8(rtos->target,
+			rtos->symbols[RIOT_MAX_THREADS].address,
+			&max_threads);
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Can't read symbol `%s`",
+			riot_symbol_list[RIOT_MAX_THREADS]);
+		return retval;
+	}
+
+	/* Base address of thread array */
+	uint32_t threads_base = rtos->symbols[RIOT_THREADS_BASE].address;
+
+	/* Try to get the offset of tcb_t::name, if absent RIOT wasn't compiled
+	 * with DEVELHELP, so there are no thread names */
+	uint8_t name_offset = 0;
+	if (rtos->symbols[RIOT_NAME_OFFSET].address != 0) {
+		retval = target_read_u8(rtos->target,
+				rtos->symbols[RIOT_NAME_OFFSET].address,
+				&name_offset);
+		if (retval != ERROR_OK) {
+			LOG_ERROR("Can't read symbol `%s`",
+				riot_symbol_list[RIOT_NAME_OFFSET]);
+			return retval;
+		}
+	}
+
+	/* Allocate memory for thread description */
+	rtos->thread_details = calloc(thread_count, sizeof(struct thread_detail));
+	if (rtos->thread_details == NULL) {
+		LOG_ERROR("RIOT: out of memory");
+		return ERROR_FAIL;
+	}
+
+	/* Buffer for thread names, maximum to display is 32 */
+	char buffer[32];
+
+	for (unsigned int i = 0; i < max_threads; i++) {
+		/* get pointer to tcb_t */
+		uint32_t tcb_pointer = 0;
+		retval = target_read_u32(rtos->target,
+				threads_base + (i * 4),
+				&tcb_pointer);
+		if (retval != ERROR_OK) {
+			LOG_ERROR("Can't parse `%s`", riot_symbol_list[RIOT_THREADS_BASE]);
+			goto error;
+		}
+
+		if (tcb_pointer == 0) {
+			/* PID unused */
+			continue;
+		}
+
+		/* Index is PID */
+		rtos->thread_details[tasks_found].threadid = i;
+
+		/* read thread state */
+		uint8_t status = 0;
+		retval = target_read_u8(rtos->target,
+				tcb_pointer + param->thread_status_offset,
+				&status);
+		if (retval != ERROR_OK) {
+			LOG_ERROR("Can't parse `%s`", riot_symbol_list[RIOT_THREADS_BASE]);
+			goto error;
+		}
+
+		/* Search for state */
+		unsigned int k;
+		for (k = 0; k < RIOT_NUM_STATES; k++) {
+			if (riot_thread_states[k].value == status)
+				break;
+		}
+
+		/* Copy state string */
+		if (k >= RIOT_NUM_STATES) {
+			rtos->thread_details[tasks_found].extra_info_str =
+			strdup("unknown state");
+		} else {
+			rtos->thread_details[tasks_found].extra_info_str =
+			strdup(riot_thread_states[k].desc);
+		}
+
+		if (rtos->thread_details[tasks_found].extra_info_str == NULL) {
+			LOG_ERROR("RIOT: out of memory");
+			retval = ERROR_FAIL;
+			goto error;
+		}
+
+		/* Thread names are only available if compiled with DEVELHELP */
+		if (name_offset != 0) {
+			uint32_t name_pointer = 0;
+			retval = target_read_u32(rtos->target,
+					tcb_pointer + name_offset,
+					&name_pointer);
+			if (retval != ERROR_OK) {
+				LOG_ERROR("Can't parse `%s`",
+					riot_symbol_list[RIOT_THREADS_BASE]);
+				goto error;
+			}
+
+			/* read thread name */
+			retval = target_read_buffer(rtos->target,
+					name_pointer,
+					sizeof(buffer),
+					(uint8_t *)&buffer);
+			if (retval != ERROR_OK) {
+				LOG_ERROR("Can't parse `%s`",
+					riot_symbol_list[RIOT_THREADS_BASE]);
+				goto error;
+			}
+
+			/* Make sure the string in the buffer terminates */
+			if (buffer[sizeof(buffer) - 1] != 0)
+				buffer[sizeof(buffer) - 1] = 0;
+
+			/* Copy thread name */
+			rtos->thread_details[tasks_found].thread_name_str =
+			strdup(buffer);
+
+		} else {
+			rtos->thread_details[tasks_found].thread_name_str =
+			strdup("Enable DEVELHELP to see task names");
+		}
+
+		if (rtos->thread_details[tasks_found].thread_name_str == NULL) {
+			LOG_ERROR("RIOT: out of memory");
+			retval = ERROR_FAIL;
+			goto error;
+		}
+
+		rtos->thread_details[tasks_found].exists = true;
+
+		tasks_found++;
+	}
+
+	return ERROR_OK;
+
+error:
+	rtos_free_threadlist(rtos);
+	return retval;
+}
+
+static int riot_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
+		struct rtos_reg **reg_list, int *num_regs)
+{
+	int retval;
+	const struct riot_params *param;
+
+	if (rtos == NULL)
+		return ERROR_FAIL;
+
+	if (thread_id == 0)
+		return ERROR_FAIL;
+
+	if (rtos->rtos_specific_params == NULL)
+		return ERROR_FAIL;
+
+	param = (const struct riot_params *)rtos->rtos_specific_params;
+
+	/* find the thread with given thread id */
+	uint32_t threads_base = rtos->symbols[RIOT_THREADS_BASE].address;
+	uint32_t tcb_pointer = 0;
+	retval = target_read_u32(rtos->target,
+			threads_base + (thread_id * 4),
+			&tcb_pointer);
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Can't parse `%s`", riot_symbol_list[RIOT_THREADS_BASE]);
+		return retval;
+	}
+
+	/* read stack pointer for that thread */
+	uint32_t stackptr = 0;
+	retval = target_read_u32(rtos->target,
+			tcb_pointer + param->thread_sp_offset,
+			&stackptr);
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Can't parse `%s`", riot_symbol_list[RIOT_THREADS_BASE]);
+		return retval;
+	}
+
+	return rtos_generic_stack_read(rtos->target,
+			stacking_info,
+			stackptr,
+			reg_list,
+			num_regs);
+}
+
+static int riot_get_symbol_list_to_lookup(symbol_table_elem_t *symbol_list[])
+{
+	*symbol_list = calloc(ARRAY_SIZE(riot_symbol_list), sizeof(symbol_table_elem_t));
+
+	if (*symbol_list == NULL) {
+		LOG_ERROR("RIOT: out of memory");
+		return ERROR_FAIL;
+	}
+
+	for (unsigned int i = 0; i < ARRAY_SIZE(riot_symbol_list); i++) {
+		(*symbol_list)[i].symbol_name = riot_symbol_list[i];
+		(*symbol_list)[i].optional = false;
+
+		/* Lookup if symbol is optional */
+		for (unsigned int k = 0; k < sizeof(riot_optional_symbols); k++) {
+			if (i == riot_optional_symbols[k]) {
+				(*symbol_list)[i].optional = true;
+				break;
+			}
+		}
+	}
+
+	return ERROR_OK;
+}
+
+static bool riot_detect_rtos(struct target *target)
+{
+	if ((target->rtos->symbols != NULL) &&
+		(target->rtos->symbols[RIOT_THREADS_BASE].address != 0)) {
+		/* looks like RIOT */
+		return true;
+	}
+	return false;
+}
+
+static int riot_create(struct target *target)
+{
+	unsigned int i = 0;
+
+	/* lookup if target is supported by RIOT */
+	while ((i < RIOT_NUM_PARAMS) &&
+		(0 != strcmp(riot_params_list[i].target_name, target->type->name))) {
+		i++;
+	}
+	if (i >= RIOT_NUM_PARAMS) {
+		LOG_ERROR("Could not find target in RIOT compatibility list");
+		return ERROR_FAIL;
+	}
+
+	target->rtos->rtos_specific_params = (void *)&riot_params_list[i];
+	target->rtos->current_thread = 0;
+	target->rtos->thread_details = NULL;
+
+	/* Stacking is different depending on architecture */
+	struct armv7m_common *armv7m_target = target_to_armv7m(target);
+
+	if (armv7m_target->arm.is_armv6m)
+		stacking_info = &rtos_riot_cortex_m0_stacking;
+	else if (is_armv7m(armv7m_target))
+		stacking_info = &rtos_riot_cortex_m34_stacking;
+	else {
+		LOG_ERROR("No stacking info for architecture");
+		return ERROR_FAIL;
+	}
+	return ERROR_OK;
+}
diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c
index ff0fb9286..ca31d22a5 100644
--- a/src/rtos/rtos.c
+++ b/src/rtos/rtos.c
@@ -38,6 +38,7 @@ extern struct rtos_type mqx_rtos;
 extern struct rtos_type uCOS_III_rtos;
 extern struct rtos_type nuttx_rtos;
 extern struct rtos_type hwthread_rtos;
+extern struct rtos_type riot_rtos;
 
 static struct rtos_type *rtos_types[] = {
 	&ThreadX_rtos,
@@ -50,6 +51,8 @@ static struct rtos_type *rtos_types[] = {
 	&mqx_rtos,
 	&uCOS_III_rtos,
 	&nuttx_rtos,
+	&riot_rtos,
+	/* keep this as last, as it always matches with rtos auto */
 	&hwthread_rtos,
 	NULL
 };
diff --git a/src/rtos/rtos_riot_stackings.c b/src/rtos/rtos_riot_stackings.c
new file mode 100644
index 000000000..23f4d1786
--- /dev/null
+++ b/src/rtos/rtos_riot_stackings.c
@@ -0,0 +1,95 @@
+/***************************************************************************
+ *   Copyright (C) 2015 by Daniel Krebs                                    *
+ *   Daniel Krebs - gi...@da...                                *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "rtos.h"
+#include "target/armv7m.h"
+#include "rtos_standard_stackings.h"
+
+/* This works for the M0 and M34 stackings as xPSR is in a fixed
+ * location
+ */
+static int64_t rtos_riot_cortex_m_stack_align(struct target *target,
+	const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
+	int64_t stack_ptr)
+{
+	const int XPSR_OFFSET = 0x40;
+	return rtos_Cortex_M_stack_align(target, stack_data, stacking,
+		stack_ptr, XPSR_OFFSET);
+}
+
+/* see thread_arch.c */
+static const struct stack_register_offset rtos_riot_cortex_m0_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
+	{ ARMV7M_R0,    0x24, 32 },		/* r0   */
+	{ ARMV7M_R1,    0x28, 32 },		/* r1   */
+	{ ARMV7M_R2,    0x2c, 32 },		/* r2   */
+	{ ARMV7M_R3,    0x30, 32 },		/* r3   */
+	{ ARMV7M_R4,    0x14, 32 },		/* r4   */
+	{ ARMV7M_R5,    0x18, 32 },		/* r5   */
+	{ ARMV7M_R6,    0x1c, 32 },		/* r6   */
+	{ ARMV7M_R7,    0x20, 32 },		/* r7   */
+	{ ARMV7M_R8,    0x04, 32 },		/* r8   */
+	{ ARMV7M_R9,    0x08, 32 },		/* r9   */
+	{ ARMV7M_R10,   0x0c, 32 },		/* r10  */
+	{ ARMV7M_R11,   0x10, 32 },		/* r11  */
+	{ ARMV7M_R12,   0x34, 32 },		/* r12  */
+	{ ARMV7M_R13,   -2,   32 },		/* sp   */
+	{ ARMV7M_R14,   0x38, 32 },		/* lr   */
+	{ ARMV7M_PC,    0x3c, 32 },		/* pc   */
+	{ ARMV7M_xPSR,  0x40, 32 },		/* xPSR */
+};
+
+const struct rtos_register_stacking rtos_riot_cortex_m0_stacking = {
+	0x44,					/* stack_registers_size */
+	-1,						/* stack_growth_direction */
+	ARMV7M_NUM_CORE_REGS,	/* num_output_registers */
+	rtos_riot_cortex_m_stack_align,		/* stack_alignment */
+	rtos_riot_cortex_m0_stack_offsets	/* register_offsets */
+};
+
+/* see thread_arch.c */
+static const struct stack_register_offset rtos_riot_cortex_m34_stack_offsets[ARMV7M_NUM_CORE_REGS] = {
+	{ ARMV7M_R0,    0x24, 32 },	/* r0   */
+	{ ARMV7M_R1,    0x28, 32 },	/* r1   */
+	{ ARMV7M_R2,    0x2c, 32 },	/* r2   */
+	{ ARMV7M_R3,    0x30, 32 },	/* r3   */
+	{ ARMV7M_R4,    0x04, 32 },	/* r4   */
+	{ ARMV7M_R5,    0x08, 32 },	/* r5   */
+	{ ARMV7M_R6,    0x0c, 32 },	/* r6   */
+	{ ARMV7M_R7,    0x10, 32 },	/* r7   */
+	{ ARMV7M_R8,    0x14, 32 },	/* r8   */
+	{ ARMV7M_R9,    0x18, 32 },	/* r9   */
+	{ ARMV7M_R10,   0x1c, 32 },	/* r10  */
+	{ ARMV7M_R11,   0x20, 32 },	/* r11  */
+	{ ARMV7M_R12,   0x34, 32 },	/* r12  */
+	{ ARMV7M_R13,   -2,   32 },	/* sp   */
+	{ ARMV7M_R14,   0x38, 32 },	/* lr   */
+	{ ARMV7M_PC,    0x3c, 32 },	/* pc   */
+	{ ARMV7M_xPSR,  0x40, 32 },	/* xPSR */
+};
+
+const struct rtos_register_stacking rtos_riot_cortex_m34_stacking = {
+	0x44,			/* stack_registers_size */
+	-1,			/* stack_growth_direction */
+	ARMV7M_NUM_CORE_REGS,	/* num_output_registers */
+	rtos_riot_cortex_m_stack_align,	/* stack_alignment */
+	rtos_riot_cortex_m34_stack_offsets	/* register_offsets */
+};
diff --git a/src/rtos/rtos_riot_stackings.h b/src/rtos/rtos_riot_stackings.h
new file mode 100644
index 000000000..c5b8f59e2
--- /dev/null
+++ b/src/rtos/rtos_riot_stackings.h
@@ -0,0 +1,32 @@
+/***************************************************************************
+ *   Copyright (C) 2015 by Daniel Krebs                                    *
+ *   Daniel Krebs - gi...@da...                                *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifndef OPENOCD_RTOS_RTOS_RIOT_STACKINGS_H
+#define OPENOCD_RTOS_RTOS_RIOT_STACKINGS_H
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "rtos.h"
+
+extern const struct rtos_register_stacking rtos_riot_cortex_m0_stacking;
+extern const struct rtos_register_stacking rtos_riot_cortex_m34_stacking;
+
+#endif	/* OPENOCD_RTOS_RTOS_RIOT_STACKINGS_H */
+

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi                                   |   6 +-
 src/rtos/Makefile.am                               |   3 +
 src/rtos/riot.c                                    | 428 +++++++++++++++++++++
 src/rtos/rtos.c                                    |   3 +
 src/rtos/rtos_riot_stackings.c                     |  95 +++++
 ...{rtos_mqx_stackings.h => rtos_riot_stackings.h} |  14 +-
 6 files changed, 542 insertions(+), 7 deletions(-)
 create mode 100644 src/rtos/riot.c
 create mode 100644 src/rtos/rtos_riot_stackings.c
 copy src/rtos/{rtos_mqx_stackings.h => rtos_riot_stackings.h} (75%)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1346-gcf902f703

From: OpenOCD-Gerrit <ope...@us...> - 2020-07-26 19:12:07

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generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  cf902f7034efd8c9db248b631420838679e9a1ed (commit)
       via  c1a3f2ce6ba820be302e5f64914a87329afd4a9b (commit)
      from  a80650ac3c7f0f1de3b5d1e45ce03d0ccc3d288e (commit)

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- Log -----------------------------------------------------------------
commit cf902f7034efd8c9db248b631420838679e9a1ed
Author: Marc Schink <de...@za...>
Date:   Wed Jul 8 15:36:29 2020 +0200

    tcl/target: Add initial GigaDevice GD32VF103 support
    
    There is no flash bank support at the moment.
    
    Change-Id: I52a2bde39425d94d9333cda002e5df0a1ef63c08
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: http://openocd.zylin.com/5755
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/gd32vf103.cfg b/tcl/target/gd32vf103.cfg
new file mode 100644
index 000000000..0f4dcf375
--- /dev/null
+++ b/tcl/target/gd32vf103.cfg
@@ -0,0 +1,26 @@
+#
+# GigaDevice GD32VF103 target
+#
+# https://www.gigadevice.com/products/microcontrollers/gd32/risc-v/
+#
+
+transport select jtag
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME gd32vf103
+}
+
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x800
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0

commit c1a3f2ce6ba820be302e5f64914a87329afd4a9b
Author: Marc Schink <de...@za...>
Date:   Sat Jul 11 16:50:19 2020 +0200

    libjaylink: Update to 0.2.0 release
    
    Change-Id: Ib53a98d0c715f91bdced1df6f157d2a50326fa8c
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: http://openocd.zylin.com/5757
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/jtag/drivers/libjaylink b/src/jtag/drivers/libjaylink
index dce11b89e..9aa7a5957 160000
--- a/src/jtag/drivers/libjaylink
+++ b/src/jtag/drivers/libjaylink
@@ -1 +1 @@
-Subproject commit dce11b89e85179a92a0fe3a90d2693ca891ed646
+Subproject commit 9aa7a5957c07bb6e862fc1a6d3153d109c7407e4

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/libjaylink |  2 +-
 tcl/target/gd32vf103.cfg    | 26 ++++++++++++++++++++++++++
 2 files changed, 27 insertions(+), 1 deletion(-)
 create mode 100644 tcl/target/gd32vf103.cfg


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From: OpenOCD-Gerrit <ope...@us...> - 2020-07-26 19:11:34

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The branch, master has been updated
       via  a80650ac3c7f0f1de3b5d1e45ce03d0ccc3d288e (commit)
       via  2f40d069a16ec6c87cbce76c6d1ac20921d47919 (commit)
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- Log -----------------------------------------------------------------
commit a80650ac3c7f0f1de3b5d1e45ce03d0ccc3d288e
Author: Jiri Kastner <cz1...@gm...>
Date:   Wed Jul 15 11:31:51 2020 +0200

    tcl/target: add Rockchip RK3308 target
    
    Change-Id: Ia8c2cec0761c37623fa8a416bcfc405f2af6a6b3
    Signed-off-by: Jiri Kastner <cz1...@gm...>
    Reviewed-on: http://openocd.zylin.com/5774
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/target/rk3308.cfg b/tcl/target/rk3308.cfg
new file mode 100644
index 000000000..d3d409eaf
--- /dev/null
+++ b/tcl/target/rk3308.cfg
@@ -0,0 +1,69 @@
+# Rockchip RK3308 Target
+# https://rockchip.fr/RK3308%20datasheet%20V1.5.pdf
+# https://dl.radxa.com/rockpis/docs/hw/datasheets/Rockchip%20RK3308TRM%20V1.1%20Part1-20180810.pdf
+
+if { [info exists CHIPNAME] } {
+  set _CHIPNAME $CHIPNAME
+} else {
+  set _CHIPNAME rk3308
+}
+
+#
+# Main DAP
+#
+if { [info exists DAP_TAPID] } {
+   set _DAP_TAPID $DAP_TAPID
+} else {
+   set _DAP_TAPID 0x2ba01477
+}
+
+adapter speed 12000
+
+transport select swd
+
+# declare the one SWD tap to access the DAP
+swd newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID -ignore-version
+
+# create the DAP
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_CHIPNAME.ahb mem_ap -dap $_CHIPNAME.dap -ap-num 0
+
+# declare the 8 main application cores
+set _TARGETNAME $_CHIPNAME.core
+set _smp_command ""
+
+set $_TARGETNAME.base(0) 0x81010000
+set $_TARGETNAME.base(1) 0x81012000
+set $_TARGETNAME.base(2) 0x81014000
+set $_TARGETNAME.base(3) 0x81016000
+
+set $_TARGETNAME.cti(0) 0x81018000
+set $_TARGETNAME.cti(1) 0x81019000
+set $_TARGETNAME.cti(2) 0x8101a000
+set $_TARGETNAME.cti(3) 0x8101b000
+
+set _cores 4
+for { set _core 0 } { $_core < $_cores } { incr _core 1 } {
+
+    cti create cti$_core -dap $_CHIPNAME.dap -ctibase [set $_TARGETNAME.cti($_core)] -ap-num 0
+
+    set _command "target create ${_TARGETNAME}$_core aarch64 \
+                         -dap $_CHIPNAME.dap -coreid $_core -cti cti$_core \
+                         -dbgbase [set $_TARGETNAME.base($_core)]"
+
+    if { $_core != 0 } {
+        set _smp_command "$_smp_command ${_TARGETNAME}$_core"
+    } else {
+        # uncomment to use hardware threads pseudo rtos
+        # set _command "$_command -rtos hwthread"
+        set _command "$_command -work-area-size 0x40000 -work-area-phys 0xfff80000 \
+                                -work-area-backup 0"
+        set _smp_command "target smp ${_TARGETNAME}$_core"
+    }
+
+    eval $_command
+}
+
+eval $_smp_command
+
+targets ${_TARGETNAME}0

commit 2f40d069a16ec6c87cbce76c6d1ac20921d47919
Author: Jiri Kastner <cz1...@gm...>
Date:   Wed Jul 15 11:30:34 2020 +0200

    src/target/arm_adi_v5.c: add Cortex-A35 related entries
    
    ROM Table registers:
    https://developer.arm.com/documentation/100236/0100/debug/rom-table/rom-table-peripheral-identification-registers
    Debug reisters:
    https://developer.arm.com/documentation/100236/0100/debug/memory-mapped-debug-registers/external-debug-peripheral-identification-registers
    PMU registers:
    https://developer.arm.com/documentation/100236/0100/debug/pmu-registers/performance-monitors-peripheral-identification-registers
    CTI registers:
    https://developer.arm.com/documentation/100236/0100/debug/cti-registers/cti-peripheral-identification-registers
    
    Change-Id: Ibd57d91fb9b66bc46929f4e93d0bf23c2a32f11a
    Signed-off-by: Jiri Kastner <cz1...@gm...>
    Reviewed-on: http://openocd.zylin.com/5773
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 241c00b04..11bf18549 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1080,6 +1080,7 @@ static const struct {
 	{ ARM_ID, 0x4a3, "Cortex-A53 ROM",             "(v7 Memory Map ROM Table)", },
 	{ ARM_ID, 0x4a4, "Cortex-A72 ROM",             "(ROM Table)", },
 	{ ARM_ID, 0x4a9, "Cortex-A9 ROM",              "(ROM Table)", },
+	{ ARM_ID, 0x4aa, "Cortex-A35 ROM",             "(v8 Memory Map ROM Table)", },
 	{ ARM_ID, 0x4af, "Cortex-A15 ROM",             "(ROM Table)", },
 	{ ARM_ID, 0x4b5, "Cortex-R5 ROM",              "(ROM Table)", },
 	{ ARM_ID, 0x4c0, "Cortex-M0+ ROM",             "(ROM Table)", },
@@ -1087,6 +1088,7 @@ static const struct {
 	{ ARM_ID, 0x4c4, "Cortex-M4 ROM",              "(ROM Table)", },
 	{ ARM_ID, 0x4c7, "Cortex-M7 PPB ROM",          "(Private Peripheral Bus ROM Table)", },
 	{ ARM_ID, 0x4c8, "Cortex-M7 ROM",              "(ROM Table)", },
+	{ ARM_ID, 0x4e0, "Cortex-A35 ROM",             "(v7 Memory Map ROM Table)", },
 	{ ARM_ID, 0x906, "CoreSight CTI",              "(Cross Trigger)", },
 	{ ARM_ID, 0x907, "CoreSight ETB",              "(Trace Buffer)", },
 	{ ARM_ID, 0x908, "CoreSight CSTF",             "(Trace Funnel)", },
@@ -1129,6 +1131,7 @@ static const struct {
 	{ ARM_ID, 0x9d3, "Cortex-A53 PMU",             "(Performance Monitor Unit)", },
 	{ ARM_ID, 0x9d7, "Cortex-A57 PMU",             "(Performance Monitor Unit)", },
 	{ ARM_ID, 0x9d8, "Cortex-A72 PMU",             "(Performance Monitor Unit)", },
+	{ ARM_ID, 0x9da, "Cortex-A35 PMU/CTI/ETM",     "(Performance Monitor Unit/Cross Trigger/ETM)", },
 	{ ARM_ID, 0xc05, "Cortex-A5 Debug",            "(Debug Unit)", },
 	{ ARM_ID, 0xc07, "Cortex-A7 Debug",            "(Debug Unit)", },
 	{ ARM_ID, 0xc08, "Cortex-A8 Debug",            "(Debug Unit)", },
@@ -1139,6 +1142,7 @@ static const struct {
 	{ ARM_ID, 0xc15, "Cortex-R5 Debug",            "(Debug Unit)", },
 	{ ARM_ID, 0xc17, "Cortex-R7 Debug",            "(Debug Unit)", },
 	{ ARM_ID, 0xd03, "Cortex-A53 Debug",           "(Debug Unit)", },
+	{ ARM_ID, 0xd04, "Cortex-A35 Debug",           "(Debug Unit)", },
 	{ ARM_ID, 0xd07, "Cortex-A57 Debug",           "(Debug Unit)", },
 	{ ARM_ID, 0xd08, "Cortex-A72 Debug",           "(Debug Unit)", },
 	{ 0x097,  0x9af, "MSP432 ROM",                 "(ROM Table)" },

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_adi_v5.c |  4 +++
 tcl/target/rk3308.cfg   | 69 +++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 73 insertions(+)
 create mode 100644 tcl/target/rk3308.cfg


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