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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1425-gb68674a1d

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- Log -----------------------------------------------------------------
commit b68674a1da7249c52b00b511fe0ceb20ace5ae4d
Author: Tim Newsome <ti...@si...>
Date:   Wed Aug 19 13:24:56 2020 -0700

    Upstream tons of RISC-V changes.
    
    These are all the changes from https://github.com/riscv/riscv-openocd
    (approximately 91dc0c0c) made just to src/target/riscv/*. Some of the
    new code is disabled because it requires some other target-independent
    changes which I didn't want to include here.
    
    Built like this, OpenOCD passes:
    * All single-RV32 tests against spike.
    * All single-RV64 tests against spike.
    * Enough HiFive1 tests. (I suspect the failures are due to the test
    suite rotting.)
    * Many dual-RV32 (-rtos hwthread) against spike.
    * Many dual-RV64 (-rtos hwthread) against spike.
    
    I suspect this is an overall improvement compared to what's in mainline
    right now, and it gets me a lot closer to getting all the riscv-openocd
    work upstreamed.
    
    Change-Id: Ide2f80c9397400780ff6780d78a206bc6a6e2f98
    Signed-off-by: Tim Newsome <ti...@si...>
    Reviewed-on: http://openocd.zylin.com/5821
    Tested-by: jenkins
    Reviewed-by: Jan Matyas <ma...@co...>
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Karl Palsson <ka...@tw...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 90b49ee35..dba2a0afa 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -9714,8 +9714,31 @@ This is used to access 64-bit floating point registers on 32-bit targets.
 @end deffn
 
 @deffn Command {riscv set_prefer_sba} on|off
-When on, prefer to use System Bus Access to access memory.  When off, prefer to
-use the Program Buffer to access memory.
+When on, prefer to use System Bus Access to access memory.  When off (default),
+prefer to use the Program Buffer to access memory.
+@end deffn
+
+@deffn Command {riscv set_enable_virtual} on|off
+When on, memory accesses are performed on physical or virtual memory depending
+on the current system configuration. When off (default), all memory accessses are performed
+on physical memory.
+@end deffn
+
+@deffn Command {riscv set_enable_virt2phys} on|off
+When on (default), memory accesses are performed on physical or virtual memory
+depending on the current satp configuration. When off, all memory accessses are
+performed on physical memory.
+@end deffn
+
+@deffn Command {riscv resume_order} normal|reversed
+Some software assumes all harts are executing nearly continuously. Such
+software may be sensitive to the order that harts are resumed in. On harts
+that don't support hasel, this option allows the user to choose the order the
+harts are resumed in. If you are using this option, it's probably masking a
+race condition problem in your code.
+
+Normal order is from lowest hart index to highest. This is the default
+behavior. Reversed order is from highest hart index to lowest.
 @end deffn
 
 @deffn Command {riscv set_ir} (@option{idcode}|@option{dtmcs}|@option{dmi}) [value]
@@ -9729,6 +9752,26 @@ When utilizing version 0.11 of the RISC-V Debug Specification,
 and DBUS registers, respectively.
 @end deffn
 
+@deffn Command {riscv use_bscan_tunnel} value
+Enable or disable use of a BSCAN tunnel to reach DM.  Supply the width of
+the DM transport TAP's instruction register to enable.  Supply a value of 0 to disable.
+@end deffn
+
+@deffn Command {riscv set_ebreakm} on|off
+Control dcsr.ebreakm. When on (default), M-mode ebreak instructions trap to
+OpenOCD. When off, they generate a breakpoint exception handled internally.
+@end deffn
+
+@deffn Command {riscv set_ebreaks} on|off
+Control dcsr.ebreaks. When on (default), S-mode ebreak instructions trap to
+OpenOCD. When off, they generate a breakpoint exception handled internally.
+@end deffn
+
+@deffn Command {riscv set_ebreaku} on|off
+Control dcsr.ebreaku. When on (default), U-mode ebreak instructions trap to
+OpenOCD. When off, they generate a breakpoint exception handled internally.
+@end deffn
+
 @subsection RISC-V Authentication Commands
 
 The following commands can be used to authenticate to a RISC-V system. Eg.  a
@@ -9752,7 +9795,7 @@ Write the 32-bit value to authdata.
 The following commands allow direct access to the Debug Module Interface, which
 can be used to interact with custom debug features.
 
-@deffn Command {riscv dmi_read}
+@deffn Command {riscv dmi_read} address
 Perform a 32-bit DMI read at address, returning the value.
 @end deffn
 
diff --git a/src/helper/log.h b/src/helper/log.h
index 0c6623f01..f2ba0daa6 100644
--- a/src/helper/log.h
+++ b/src/helper/log.h
@@ -154,6 +154,7 @@ extern int debug_level;
 #define ERROR_WAIT						(-5)
 /* ERROR_TIMEOUT is already taken by winerror.h. */
 #define ERROR_TIMEOUT_REACHED			(-6)
+#define ERROR_NOT_IMPLEMENTED			(-7)
 
 
 #endif /* OPENOCD_HELPER_LOG_H */
diff --git a/src/target/riscv/asm.h b/src/target/riscv/asm.h
index d81aa0285..6ceb8c9bd 100644
--- a/src/target/riscv/asm.h
+++ b/src/target/riscv/asm.h
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 #ifndef TARGET__RISCV__ASM_H
 #define TARGET__RISCV__ASM_H
 
diff --git a/src/target/riscv/batch.c b/src/target/riscv/batch.c
index d041ed119..43f2ffb8c 100644
--- a/src/target/riscv/batch.c
+++ b/src/target/riscv/batch.c
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
@@ -9,21 +11,53 @@
 #define get_field(reg, mask) (((reg) & (mask)) / ((mask) & ~((mask) << 1)))
 #define set_field(reg, mask, val) (((reg) & ~(mask)) | (((val) * ((mask) & ~((mask) << 1))) & (mask)))
 
+#define DTM_DMI_MAX_ADDRESS_LENGTH	((1<<DTM_DTMCS_ABITS_LENGTH)-1)
+#define DMI_SCAN_MAX_BIT_LENGTH (DTM_DMI_MAX_ADDRESS_LENGTH + DTM_DMI_DATA_LENGTH + DTM_DMI_OP_LENGTH)
+#define DMI_SCAN_BUF_SIZE (DIV_ROUND_UP(DMI_SCAN_MAX_BIT_LENGTH, 8))
+
 static void dump_field(int idle, const struct scan_field *field);
 
 struct riscv_batch *riscv_batch_alloc(struct target *target, size_t scans, size_t idle)
 {
 	scans += 4;
 	struct riscv_batch *out = calloc(1, sizeof(*out));
+	if (!out)
+		goto error0;
 	out->target = target;
 	out->allocated_scans = scans;
 	out->idle_count = idle;
-	out->data_out = malloc(sizeof(*out->data_out) * (scans) * sizeof(uint64_t));
-	out->data_in  = malloc(sizeof(*out->data_in)  * (scans) * sizeof(uint64_t));
+	out->data_out = malloc(sizeof(*out->data_out) * (scans) * DMI_SCAN_BUF_SIZE);
+	if (!out->data_out)
+		goto error1;
+	out->data_in = malloc(sizeof(*out->data_in) * (scans) * DMI_SCAN_BUF_SIZE);
+	if (!out->data_in)
+		goto error2;
 	out->fields = malloc(sizeof(*out->fields) * (scans));
+	if (!out->fields)
+		goto error3;
+	if (bscan_tunnel_ir_width != 0) {
+		out->bscan_ctxt = malloc(sizeof(*out->bscan_ctxt) * (scans));
+		if (!out->bscan_ctxt)
+			goto error4;
+	}
 	out->last_scan = RISCV_SCAN_TYPE_INVALID;
 	out->read_keys = malloc(sizeof(*out->read_keys) * (scans));
+	if (!out->read_keys)
+		goto error5;
 	return out;
+
+error5:
+	free(out->bscan_ctxt);
+error4:
+	free(out->fields);
+error3:
+	free(out->data_in);
+error2:
+	free(out->data_out);
+error1:
+	free(out);
+error0:
+	return NULL;
 }
 
 void riscv_batch_free(struct riscv_batch *batch)
@@ -31,6 +65,8 @@ void riscv_batch_free(struct riscv_batch *batch)
 	free(batch->data_in);
 	free(batch->data_out);
 	free(batch->fields);
+	free(batch->bscan_ctxt);
+	free(batch->read_keys);
 	free(batch);
 }
 
@@ -51,7 +87,11 @@ int riscv_batch_run(struct riscv_batch *batch)
 	riscv_batch_add_nop(batch);
 
 	for (size_t i = 0; i < batch->used_scans; ++i) {
-		jtag_add_dr_scan(batch->target->tap, 1, batch->fields + i, TAP_IDLE);
+		if (bscan_tunnel_ir_width != 0)
+			riscv_add_bscan_tunneled_scan(batch->target, batch->fields+i, batch->bscan_ctxt+i);
+		else
+			jtag_add_dr_scan(batch->target->tap, 1, batch->fields + i, TAP_IDLE);
+
 		if (batch->idle_count > 0)
 			jtag_add_runtest(batch->idle_count, TAP_IDLE);
 	}
@@ -61,6 +101,12 @@ int riscv_batch_run(struct riscv_batch *batch)
 		return ERROR_FAIL;
 	}
 
+	if (bscan_tunnel_ir_width != 0) {
+		/* need to right-shift "in" by one bit, because of clock skew between BSCAN TAP and DM TAP */
+		for (size_t i = 0; i < batch->used_scans; ++i)
+			buffer_shr((batch->fields + i)->in_value, DMI_SCAN_BUF_SIZE, 1);
+	}
+
 	for (size_t i = 0; i < batch->used_scans; ++i)
 		dump_field(batch->idle_count, batch->fields + i);
 
@@ -72,8 +118,8 @@ void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned address, uint
 	assert(batch->used_scans < batch->allocated_scans);
 	struct scan_field *field = batch->fields + batch->used_scans;
 	field->num_bits = riscv_dmi_write_u64_bits(batch->target);
-	field->out_value = (void *)(batch->data_out + batch->used_scans * sizeof(uint64_t));
-	field->in_value  = (void *)(batch->data_in  + batch->used_scans * sizeof(uint64_t));
+	field->out_value = (void *)(batch->data_out + batch->used_scans * DMI_SCAN_BUF_SIZE);
+	field->in_value  = (void *)(batch->data_in  + batch->used_scans * DMI_SCAN_BUF_SIZE);
 	riscv_fill_dmi_write_u64(batch->target, (char *)field->out_value, address, data);
 	riscv_fill_dmi_nop_u64(batch->target, (char *)field->in_value);
 	batch->last_scan = RISCV_SCAN_TYPE_WRITE;
@@ -85,35 +131,35 @@ size_t riscv_batch_add_dmi_read(struct riscv_batch *batch, unsigned address)
 	assert(batch->used_scans < batch->allocated_scans);
 	struct scan_field *field = batch->fields + batch->used_scans;
 	field->num_bits = riscv_dmi_write_u64_bits(batch->target);
-	field->out_value = (void *)(batch->data_out + batch->used_scans * sizeof(uint64_t));
-	field->in_value  = (void *)(batch->data_in  + batch->used_scans * sizeof(uint64_t));
+	field->out_value = (void *)(batch->data_out + batch->used_scans * DMI_SCAN_BUF_SIZE);
+	field->in_value  = (void *)(batch->data_in  + batch->used_scans * DMI_SCAN_BUF_SIZE);
 	riscv_fill_dmi_read_u64(batch->target, (char *)field->out_value, address);
 	riscv_fill_dmi_nop_u64(batch->target, (char *)field->in_value);
 	batch->last_scan = RISCV_SCAN_TYPE_READ;
 	batch->used_scans++;
 
-	/* FIXME We get the read response back on the next scan.  For now I'm
-	 * just sticking a NOP in there, but this should be coalesced away. */
-	riscv_batch_add_nop(batch);
-
-	batch->read_keys[batch->read_keys_used] = batch->used_scans - 1;
+	batch->read_keys[batch->read_keys_used] = batch->used_scans;
 	return batch->read_keys_used++;
 }
 
-uint64_t riscv_batch_get_dmi_read(struct riscv_batch *batch, size_t key)
+unsigned riscv_batch_get_dmi_read_op(struct riscv_batch *batch, size_t key)
 {
 	assert(key < batch->read_keys_used);
 	size_t index = batch->read_keys[key];
 	assert(index <= batch->used_scans);
-	uint8_t *base = batch->data_in + 8 * index;
-	return base[0] |
-		((uint64_t) base[1]) << 8 |
-		((uint64_t) base[2]) << 16 |
-		((uint64_t) base[3]) << 24 |
-		((uint64_t) base[4]) << 32 |
-		((uint64_t) base[5]) << 40 |
-		((uint64_t) base[6]) << 48 |
-		((uint64_t) base[7]) << 56;
+	uint8_t *base = batch->data_in + DMI_SCAN_BUF_SIZE * index;
+	/* extract "op" field from the DMI read result */
+	return (unsigned)buf_get_u32(base, DTM_DMI_OP_OFFSET, DTM_DMI_OP_LENGTH);
+}
+
+uint32_t riscv_batch_get_dmi_read_data(struct riscv_batch *batch, size_t key)
+{
+	assert(key < batch->read_keys_used);
+	size_t index = batch->read_keys[key];
+	assert(index <= batch->used_scans);
+	uint8_t *base = batch->data_in + DMI_SCAN_BUF_SIZE * index;
+	/* extract "data" field from the DMI read result */
+	return buf_get_u32(base, DTM_DMI_DATA_OFFSET, DTM_DMI_DATA_LENGTH);
 }
 
 void riscv_batch_add_nop(struct riscv_batch *batch)
@@ -121,8 +167,8 @@ void riscv_batch_add_nop(struct riscv_batch *batch)
 	assert(batch->used_scans < batch->allocated_scans);
 	struct scan_field *field = batch->fields + batch->used_scans;
 	field->num_bits = riscv_dmi_write_u64_bits(batch->target);
-	field->out_value = (void *)(batch->data_out + batch->used_scans * sizeof(uint64_t));
-	field->in_value  = (void *)(batch->data_in  + batch->used_scans * sizeof(uint64_t));
+	field->out_value = (void *)(batch->data_out + batch->used_scans * DMI_SCAN_BUF_SIZE);
+	field->in_value  = (void *)(batch->data_in  + batch->used_scans * DMI_SCAN_BUF_SIZE);
 	riscv_fill_dmi_nop_u64(batch->target, (char *)field->out_value);
 	riscv_fill_dmi_nop_u64(batch->target, (char *)field->in_value);
 	batch->last_scan = RISCV_SCAN_TYPE_NOP;
@@ -151,13 +197,17 @@ void dump_field(int idle, const struct scan_field *field)
 
 		log_printf_lf(LOG_LVL_DEBUG,
 				__FILE__, __LINE__, __PRETTY_FUNCTION__,
-				"%db %di %s %08x @%02x -> %s %08x @%02x",
-				field->num_bits, idle,
-				op_string[out_op], out_data, out_address,
-				status_string[in_op], in_data, in_address);
+				"%db %s %08x @%02x -> %s %08x @%02x; %di",
+				field->num_bits, op_string[out_op], out_data, out_address,
+				status_string[in_op], in_data, in_address, idle);
 	} else {
 		log_printf_lf(LOG_LVL_DEBUG,
-				__FILE__, __LINE__, __PRETTY_FUNCTION__, "%db %di %s %08x @%02x -> ?",
-				field->num_bits, idle, op_string[out_op], out_data, out_address);
+				__FILE__, __LINE__, __PRETTY_FUNCTION__, "%db %s %08x @%02x -> ?; %di",
+				field->num_bits, op_string[out_op], out_data, out_address, idle);
 	}
 }
+
+size_t riscv_batch_available_scans(struct riscv_batch *batch)
+{
+	return batch->allocated_scans - batch->used_scans - 4;
+}
diff --git a/src/target/riscv/batch.h b/src/target/riscv/batch.h
index 70690a601..9c42ba81e 100644
--- a/src/target/riscv/batch.h
+++ b/src/target/riscv/batch.h
@@ -1,8 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 #ifndef TARGET__RISCV__SCANS_H
 #define TARGET__RISCV__SCANS_H
 
 #include "target/target.h"
 #include "jtag/jtag.h"
+#include "riscv.h"
 
 enum riscv_scan_type {
 	RISCV_SCAN_TYPE_INVALID,
@@ -27,6 +30,11 @@ struct riscv_batch {
 	uint8_t *data_in;
 	struct scan_field *fields;
 
+	/* If in BSCAN mode, this field will be allocated (one per scan),
+	   and utilized to tunnel all the scans in the batch.  If not in
+	   BSCAN mode, this field is unallocated and stays NULL */
+	riscv_bscan_tunneled_scan_context_t *bscan_ctxt;
+
 	/* In JTAG we scan out the previous value's output when performing a
 	 * scan.  This is a pain for users, so we just provide them the
 	 * illusion of not having to do this by eliding all but the last NOP.
@@ -54,11 +62,16 @@ int riscv_batch_run(struct riscv_batch *batch);
 void riscv_batch_add_dmi_write(struct riscv_batch *batch, unsigned address, uint64_t data);
 
 /* DMI reads must be handled in two parts: the first one schedules a read and
- * provides a key, the second one actually obtains the value of that read .*/
+ * provides a key, the second one actually obtains the result of the read -
+ * status (op) and the actual data. */
 size_t riscv_batch_add_dmi_read(struct riscv_batch *batch, unsigned address);
-uint64_t riscv_batch_get_dmi_read(struct riscv_batch *batch, size_t key);
+unsigned riscv_batch_get_dmi_read_op(struct riscv_batch *batch, size_t key);
+uint32_t riscv_batch_get_dmi_read_data(struct riscv_batch *batch, size_t key);
 
 /* Scans in a NOP. */
 void riscv_batch_add_nop(struct riscv_batch *batch);
 
+/* Returns the number of available scans. */
+size_t riscv_batch_available_scans(struct riscv_batch *batch);
+
 #endif
diff --git a/src/target/riscv/debug_defines.h b/src/target/riscv/debug_defines.h
index d6ddd4ff1..cb518a891 100644
--- a/src/target/riscv/debug_defines.h
+++ b/src/target/riscv/debug_defines.h
@@ -1,22 +1,27 @@
+/*
+ * This file is auto-generated by running 'make debug_defines.h' in
+ * https://github.com/riscv/riscv-debug-spec/ (30b1a97)
+ */
+
 #define DTM_IDCODE                          0x01
 /*
-* Identifies the release version of this part.
+ * Identifies the release version of this part.
  */
 #define DTM_IDCODE_VERSION_OFFSET           28
 #define DTM_IDCODE_VERSION_LENGTH           4
 #define DTM_IDCODE_VERSION                  (0xfU << DTM_IDCODE_VERSION_OFFSET)
 /*
-* Identifies the designer's part number of this part.
+ * Identifies the designer's part number of this part.
  */
 #define DTM_IDCODE_PARTNUMBER_OFFSET        12
 #define DTM_IDCODE_PARTNUMBER_LENGTH        16
 #define DTM_IDCODE_PARTNUMBER               (0xffffU << DTM_IDCODE_PARTNUMBER_OFFSET)
 /*
-* Identifies the designer/manufacturer of this part. Bits 6:0 must be
-* bits 6:0 of the designer/manufacturer's Identification Code as
-* assigned by JEDEC Standard JEP106. Bits 10:7 contain the modulo-16
-* count of the number of continuation characters (0x7f) in that same
-* Identification Code.
+ * Identifies the designer/manufacturer of this part. Bits 6:0 must be
+ * bits 6:0 of the designer/manufacturer's Identification Code as
+ * assigned by JEDEC Standard JEP106. Bits 10:7 contain the modulo-16
+ * count of the number of continuation characters (0x7f) in that same
+ * Identification Code.
  */
 #define DTM_IDCODE_MANUFID_OFFSET           1
 #define DTM_IDCODE_MANUFID_LENGTH           11
@@ -26,1389 +31,1892 @@
 #define DTM_IDCODE_1                        (0x1U << DTM_IDCODE_1_OFFSET)
 #define DTM_DTMCS                           0x10
 /*
-* Writing 1 to this bit does a hard reset of the DTM,
-* causing the DTM to forget about any outstanding DMI transactions.
-* In general this should only be used when the Debugger has
-* reason to expect that the outstanding DMI transaction will never
-* complete (e.g. a reset condition caused an inflight DMI transaction to
-* be cancelled).
+ * Writing 1 to this bit does a hard reset of the DTM,
+ * causing the DTM to forget about any outstanding DMI transactions, and
+ * returning all registers and internal state to their reset value.
+ * In general this should only be used when the Debugger has
+ * reason to expect that the outstanding DMI transaction will never
+ * complete (e.g. a reset condition caused an inflight DMI transaction to
+ * be cancelled).
  */
 #define DTM_DTMCS_DMIHARDRESET_OFFSET       17
 #define DTM_DTMCS_DMIHARDRESET_LENGTH       1
 #define DTM_DTMCS_DMIHARDRESET              (0x1U << DTM_DTMCS_DMIHARDRESET_OFFSET)
 /*
-* Writing 1 to this bit clears the sticky error state
-* and allows the DTM to retry or complete the previous
-* transaction.
+ * Writing 1 to this bit clears the sticky error state, but does
+ * not affect outstanding DMI transactions.
  */
 #define DTM_DTMCS_DMIRESET_OFFSET           16
 #define DTM_DTMCS_DMIRESET_LENGTH           1
 #define DTM_DTMCS_DMIRESET                  (0x1U << DTM_DTMCS_DMIRESET_OFFSET)
 /*
-* This is a hint to the debugger of the minimum number of
-* cycles a debugger should spend in
-* Run-Test/Idle after every DMI scan to avoid a `busy'
-* return code (\Fdmistat of 3). A debugger must still
-* check \Fdmistat when necessary.
-*
-* 0: It is not necessary to enter Run-Test/Idle at all.
-*
-* 1: Enter Run-Test/Idle and leave it immediately.
-*
-* 2: Enter Run-Test/Idle and stay there for 1 cycle before leaving.
-*
-* And so on.
+ * This is a hint to the debugger of the minimum number of
+ * cycles a debugger should spend in
+ * Run-Test/Idle after every DMI scan to avoid a `busy'
+ * return code (\FdtmDtmcsDmistat of 3). A debugger must still
+ * check \FdtmDtmcsDmistat when necessary.
+ *
+ * 0: It is not necessary to enter Run-Test/Idle at all.
+ *
+ * 1: Enter Run-Test/Idle and leave it immediately.
+ *
+ * 2: Enter Run-Test/Idle and stay there for 1 cycle before leaving.
+ *
+ * And so on.
  */
 #define DTM_DTMCS_IDLE_OFFSET               12
 #define DTM_DTMCS_IDLE_LENGTH               3
 #define DTM_DTMCS_IDLE                      (0x7U << DTM_DTMCS_IDLE_OFFSET)
 /*
-* 0: No error.
-*
-* 1: Reserved. Interpret the same as 2.
-*
-* 2: An operation failed (resulted in \Fop of 2).
-*
-* 3: An operation was attempted while a DMI access was still in
-* progress (resulted in \Fop of 3).
+ * 0: No error.
+ *
+ * 1: Reserved. Interpret the same as 2.
+ *
+ * 2: An operation failed (resulted in \FdtmDmiOp of 2).
+ *
+ * 3: An operation was attempted while a DMI access was still in
+ * progress (resulted in \FdtmDmiOp of 3).
  */
 #define DTM_DTMCS_DMISTAT_OFFSET            10
 #define DTM_DTMCS_DMISTAT_LENGTH            2
 #define DTM_DTMCS_DMISTAT                   (0x3U << DTM_DTMCS_DMISTAT_OFFSET)
 /*
-* The size of \Faddress in \Rdmi.
+ * The size of \FdmSbaddressZeroAddress in \RdtmDmi.
  */
 #define DTM_DTMCS_ABITS_OFFSET              4
 #define DTM_DTMCS_ABITS_LENGTH              6
 #define DTM_DTMCS_ABITS                     (0x3fU << DTM_DTMCS_ABITS_OFFSET)
 /*
-* 0: Version described in spec version 0.11.
-*
-* 1: Version described in spec version 0.13 (and later?), which
-* reduces the DMI data width to 32 bits.
-*
-* 15: Version not described in any available version of this spec.
+ * 0: Version described in spec version 0.11.
+ *
+ * 1: Version described in spec version 0.13.
+ *
+ * 15: Version not described in any available version of this spec.
  */
 #define DTM_DTMCS_VERSION_OFFSET            0
 #define DTM_DTMCS_VERSION_LENGTH            4
 #define DTM_DTMCS_VERSION                   (0xfU << DTM_DTMCS_VERSION_OFFSET)
 #define DTM_DMI                             0x11
 /*
-* Address used for DMI access. In Update-DR this value is used
-* to access the DM over the DMI.
+ * Address used for DMI access. In Update-DR this value is used
+ * to access the DM over the DMI.
  */
 #define DTM_DMI_ADDRESS_OFFSET              34
 #define DTM_DMI_ADDRESS_LENGTH              abits
-#define DTM_DMI_ADDRESS                     (((1L<<abits)-1) << DTM_DMI_ADDRESS_OFFSET)
+#define DTM_DMI_ADDRESS                     (((1L << abits) - 1) << DTM_DMI_ADDRESS_OFFSET)
 /*
-* The data to send to the DM over the DMI during Update-DR, and
-* the data returned from the DM as a result of the previous operation.
+ * The data to send to the DM over the DMI during Update-DR, and
+ * the data returned from the DM as a result of the previous operation.
  */
 #define DTM_DMI_DATA_OFFSET                 2
 #define DTM_DMI_DATA_LENGTH                 32
 #define DTM_DMI_DATA                        (0xffffffffULL << DTM_DMI_DATA_OFFSET)
 /*
-* When the debugger writes this field, it has the following meaning:
-*
-* 0: Ignore \Fdata and \Faddress. (nop)
-*
-* Don't send anything over the DMI during Update-DR.
-* This operation should never result in a busy or error response.
-* The address and data reported in the following Capture-DR
-* are undefined.
-*
-* 1: Read from \Faddress. (read)
-*
-* 2: Write \Fdata to \Faddress. (write)
-*
-* 3: Reserved.
-*
-* When the debugger reads this field, it means the following:
-*
-* 0: The previous operation completed successfully.
-*
-* 1: Reserved.
-*
-* 2: A previous operation failed.  The data scanned into \Rdmi in
-* this access will be ignored.  This status is sticky and can be
-* cleared by writing \Fdmireset in \Rdtmcs.
-*
-* This indicates that the DM itself responded with an error.
-* Note: there are no specified cases in which the DM would
-* respond with an error, and DMI is not required to support
-* returning errors.
-*
-* 3: An operation was attempted while a DMI request is still in
-* progress. The data scanned into \Rdmi in this access will be
-* ignored. This status is sticky and can be cleared by writing
-* \Fdmireset in \Rdtmcs. If a debugger sees this status, it
-* needs to give the target more TCK edges between Update-DR and
-* Capture-DR. The simplest way to do that is to add extra transitions
-* in Run-Test/Idle.
-*
-* (The DTM, DM, and/or component may be in different clock domains,
-* so synchronization may be required. Some relatively fixed number of
-* TCK ticks may be needed for the request to reach the DM, complete,
-* and for the response to be synchronized back into the TCK domain.)
+ * When the debugger writes this field, it has the following meaning:
+ *
+ * 0: Ignore \FdmSbdataZeroData and \FdmSbaddressZeroAddress. (nop)
+ *
+ * Don't send anything over the DMI during Update-DR.
+ * This operation should never result in a busy or error response.
+ * The address and data reported in the following Capture-DR
+ * are undefined.
+ *
+ * 1: Read from \FdmSbaddressZeroAddress. (read)
+ *
+ * 2: Write \FdmSbdataZeroData to \FdmSbaddressZeroAddress. (write)
+ *
+ * 3: Reserved.
+ *
+ * When the debugger reads this field, it means the following:
+ *
+ * 0: The previous operation completed successfully.
+ *
+ * 1: Reserved.
+ *
+ * 2: A previous operation failed.  The data scanned into \RdtmDmi in
+ * this access will be ignored.  This status is sticky and can be
+ * cleared by writing \FdtmDtmcsDmireset in \RdtmDtmcs.
+ *
+ * This indicates that the DM itself responded with an error.
+ * There are no specified cases in which the DM would
+ * respond with an error, and DMI is not required to support
+ * returning errors.
+ *
+ * 3: An operation was attempted while a DMI request is still in
+ * progress. The data scanned into \RdtmDmi in this access will be
+ * ignored. This status is sticky and can be cleared by writing
+ * \FdtmDtmcsDmireset in \RdtmDtmcs. If a debugger sees this status, it
+ * needs to give the target more TCK edges between Update-DR and
+ * Capture-DR. The simplest way to do that is to add extra transitions
+ * in Run-Test/Idle.
  */
 #define DTM_DMI_OP_OFFSET                   0
 #define DTM_DMI_OP_LENGTH                   2
 #define DTM_DMI_OP                          (0x3ULL << DTM_DMI_OP_OFFSET)
 #define CSR_DCSR                            0x7b0
 /*
-* 0: There is no external debug support.
-*
-* 4: External debug support exists as it is described in this document.
-*
-* 15: There is external debug support, but it does not conform to any
-* available version of this spec.
+ * 0: There is no external debug support.
+ *
+ * 4: External debug support exists as it is described in this document.
+ *
+ * 15: There is external debug support, but it does not conform to any
+ * available version of this spec.
  */
 #define CSR_DCSR_XDEBUGVER_OFFSET           28
 #define CSR_DCSR_XDEBUGVER_LENGTH           4
 #define CSR_DCSR_XDEBUGVER                  (0xfU << CSR_DCSR_XDEBUGVER_OFFSET)
 /*
-* When 1, {\tt ebreak} instructions in Machine Mode enter Debug Mode.
+ * 0: {\tt ebreak} instructions in M-mode behave as described in the
+ * Privileged Spec.
+ *
+ * 1: {\tt ebreak} instructions in M-mode enter Debug Mode.
  */
 #define CSR_DCSR_EBREAKM_OFFSET             15
 #define CSR_DCSR_EBREAKM_LENGTH             1
 #define CSR_DCSR_EBREAKM                    (0x1U << CSR_DCSR_EBREAKM_OFFSET)
 /*
-* When 1, {\tt ebreak} instructions in Supervisor Mode enter Debug Mode.
+ * 0: {\tt ebreak} instructions in S-mode behave as described in the
+ * Privileged Spec.
+ *
+ * 1: {\tt ebreak} instructions in S-mode enter Debug Mode.
+ *
+ * This bit is hardwired to 0 if the hart does not support S mode.
  */
 #define CSR_DCSR_EBREAKS_OFFSET             13
 #define CSR_DCSR_EBREAKS_LENGTH             1
 #define CSR_DCSR_EBREAKS                    (0x1U << CSR_DCSR_EBREAKS_OFFSET)
 /*
-* When 1, {\tt ebreak} instructions in User/Application Mode enter
-* Debug Mode.
+ * 0: {\tt ebreak} instructions in U-mode behave as described in the
+ * Privileged Spec.
+ *
+ * 1: {\tt ebreak} instructions in U-mode enter Debug Mode.
+ *
+ * This bit is hardwired to 0 if the hart does not support U mode.
  */
 #define CSR_DCSR_EBREAKU_OFFSET             12
 #define CSR_DCSR_EBREAKU_LENGTH             1
 #define CSR_DCSR_EBREAKU                    (0x1U << CSR_DCSR_EBREAKU_OFFSET)
 /*
-* 0: Interrupts are disabled during single stepping.
-*
-* 1: Interrupts are enabled during single stepping.
-*
-* Implementations may hard wire this bit to 0.
-* The debugger must read back the value it
-* writes to check whether the feature is supported. If not
-* supported, interrupt behavior can be emulated by the debugger.
+ * 0: Interrupts (including NMI) are disabled during single stepping.
+ *
+ * 1: Interrupts (including NMI) are enabled during single stepping.
+ *
+ * Implementations may hard wire this bit to 0.
+ * In that case interrupt behavior can be emulated by the debugger.
+ *
+ * The debugger must not change the value of this bit while the hart
+ * is running.
  */
 #define CSR_DCSR_STEPIE_OFFSET              11
 #define CSR_DCSR_STEPIE_LENGTH              1
 #define CSR_DCSR_STEPIE                     (0x1U << CSR_DCSR_STEPIE_OFFSET)
 /*
-* 0: Increment counters as usual.
-*
-* 1: Don't increment any counters while in Debug Mode or on {\tt
-* ebreak} instructions that cause entry into Debug Mode.  These
-* counters include the {\tt cycle} and {\tt instret} CSRs. This is
-* preferred for most debugging scenarios.
-*
-* An implementation may choose not to support writing to this bit.
-* The debugger must read back the value it writes to check whether
-* the feature is supported.
+ * 0: Increment counters as usual.
+ *
+ * 1: Don't increment any hart-local counters while in Debug Mode or
+ * on {\tt ebreak} instructions that cause entry into Debug Mode.
+ * These counters include the {\tt instret} CSR. On single-hart cores
+ * {\tt cycle} should be stopped, but on multi-hart cores it must keep
+ * incrementing.
+ *
+ * An implementation may hardwire this bit to 0 or 1.
  */
 #define CSR_DCSR_STOPCOUNT_OFFSET           10
 #define CSR_DCSR_STOPCOUNT_LENGTH           1
 #define CSR_DCSR_STOPCOUNT                  (0x1U << CSR_DCSR_STOPCOUNT_OFFSET)
 /*
-* 0: Increment timers as usual.
-*
-* 1: Don't increment any hart-local timers while in Debug Mode.
-*
-* An implementation may choose not to support writing to this bit.
-* The debugger must read back the value it writes to check whether
-* the feature is supported.
+ * 0: Increment timers as usual.
+ *
+ * 1: Don't increment any hart-local timers while in Debug Mode.
+ *
+ * An implementation may hardwire this bit to 0 or 1.
  */
 #define CSR_DCSR_STOPTIME_OFFSET            9
 #define CSR_DCSR_STOPTIME_LENGTH            1
 #define CSR_DCSR_STOPTIME                   (0x1U << CSR_DCSR_STOPTIME_OFFSET)
 /*
-* Explains why Debug Mode was entered.
-*
-* When there are multiple reasons to enter Debug Mode in a single
-* cycle, hardware should set \Fcause to the cause with the highest
-* priority.
-*
-* 1: An {\tt ebreak} instruction was executed. (priority 3)
-*
-* 2: The Trigger Module caused a breakpoint exception. (priority 4)
-*
-* 3: The debugger requested entry to Debug Mode. (priority 2)
-*
-* 4: The hart single stepped because \Fstep was set. (priority 1)
-*
-* Other values are reserved for future use.
+ * Explains why Debug Mode was entered.
+ *
+ * When there are multiple reasons to enter Debug Mode in a single
+ * cycle, hardware should set \FcsrDcsrCause to the cause with the highest
+ * priority.
+ *
+ * 1: An {\tt ebreak} instruction was executed. (priority 3)
+ *
+ * 2: The Trigger Module caused a breakpoint exception. (priority 4)
+ *
+ * 3: The debugger requested entry to Debug Mode using \FdmDmcontrolHaltreq.
+ * (priority 1)
+ *
+ * 4: The hart single stepped because \FcsrDcsrStep was set. (priority 0, lowest)
+ *
+ * 5: The hart halted directly out of reset due to \Fresethaltreq. It
+ * is also acceptable to report 3 when this happens. (priority 2)
+ *
+ * 6: The hart halted because it's part of a halt group. (priority 5,
+ * highest) Harts may report 3 for this cause instead.
+ *
+ * Other values are reserved for future use.
  */
 #define CSR_DCSR_CAUSE_OFFSET               6
 #define CSR_DCSR_CAUSE_LENGTH               3
 #define CSR_DCSR_CAUSE                      (0x7U << CSR_DCSR_CAUSE_OFFSET)
 /*
-* When 1, \Fmprv in \Rmstatus takes effect during debug mode.
-* When 0, it is ignored during debug mode.
-* Implementing this bit is optional.
-* If not implemented it should be tied to 0.
+ * 0: \FcsrMcontrolMprv in \Rmstatus is ignored in Debug Mode.
+ *
+ * 1: \FcsrMcontrolMprv in \Rmstatus takes effect in Debug Mode.
+ *
+ * Implementing this bit is optional. It may be tied to either 0 or 1.
  */
 #define CSR_DCSR_MPRVEN_OFFSET              4
 #define CSR_DCSR_MPRVEN_LENGTH              1
 #define CSR_DCSR_MPRVEN                     (0x1U << CSR_DCSR_MPRVEN_OFFSET)
 /*
-* When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart.
-*
-* Since an NMI can indicate a hardware error condition,
-* reliable debugging may no longer be possible once this bit becomes set.
-* This is implementation-dependent.
+ * When set, there is a Non-Maskable-Interrupt (NMI) pending for the hart.
+ *
+ * Since an NMI can indicate a hardware error condition,
+ * reliable debugging may no longer be possible once this bit becomes set.
+ * This is implementation-dependent.
  */
 #define CSR_DCSR_NMIP_OFFSET                3
 #define CSR_DCSR_NMIP_LENGTH                1
 #define CSR_DCSR_NMIP                       (0x1U << CSR_DCSR_NMIP_OFFSET)
 /*
-* When set and not in Debug Mode, the hart will only execute a single
-* instruction and then enter Debug Mode.
-* If the instruction does not complete due to an exception,
-* the hart will immediately enter Debug Mode before executing
-* the trap handler, with appropriate exception registers set.
+ * When set and not in Debug Mode, the hart will only execute a single
+ * instruction and then enter Debug Mode. See Section~\ref{stepBit}
+ * for details.
+ *
+ * The debugger must not change the value of this bit while the hart
+ * is running.
  */
 #define CSR_DCSR_STEP_OFFSET                2
 #define CSR_DCSR_STEP_LENGTH                1
 #define CSR_DCSR_STEP                       (0x1U << CSR_DCSR_STEP_OFFSET)
 /*
-* Contains the privilege level the hart was operating in when Debug
-* Mode was entered. The encoding is described in Table
-* \ref{tab:privlevel}.  A debugger can change this value to change
-* the hart's privilege level when exiting Debug Mode.
-*
-* Not all privilege levels are supported on all harts. If the
-* encoding written is not supported or the debugger is not allowed to
-* change to it, the hart may change to any supported privilege level.
+ * Contains the privilege level the hart was operating in when Debug
+ * Mode was entered. The encoding is described in Table
+ * \ref{tab:privlevel}.  A debugger can change this value to change
+ * the hart's privilege level when exiting Debug Mode.
+ *
+ * Not all privilege levels are supported on all harts. If the
+ * encoding written is not supported or the debugger is not allowed to
+ * change to it, the hart may change to any supported privilege level.
  */
 #define CSR_DCSR_PRV_OFFSET                 0
 #define CSR_DCSR_PRV_LENGTH                 2
 #define CSR_DCSR_PRV                        (0x3U << CSR_DCSR_PRV_OFFSET)
 #define CSR_DPC                             0x7b1
 #define CSR_DPC_DPC_OFFSET                  0
-#define CSR_DPC_DPC_LENGTH                  MXLEN
-#define CSR_DPC_DPC                         (((1L<<MXLEN)-1) << CSR_DPC_DPC_OFFSET)
+#define CSR_DPC_DPC_LENGTH                  DXLEN
+#define CSR_DPC_DPC                         (((1L << DXLEN) - 1) << CSR_DPC_DPC_OFFSET)
 #define CSR_DSCRATCH0                       0x7b2
 #define CSR_DSCRATCH1                       0x7b3
 #define CSR_TSELECT                         0x7a0
 #define CSR_TSELECT_INDEX_OFFSET            0
-#define CSR_TSELECT_INDEX_LENGTH            MXLEN
-#define CSR_TSELECT_INDEX                   (((1L<<MXLEN)-1) << CSR_TSELECT_INDEX_OFFSET)
+#define CSR_TSELECT_INDEX_LENGTH            XLEN
+#define CSR_TSELECT_INDEX                   (((1L << XLEN) - 1) << CSR_TSELECT_INDEX_OFFSET)
 #define CSR_TDATA1                          0x7a1
 /*
-* 0: There is no trigger at this \Rtselect.
-*
-* 1: The trigger is a legacy SiFive address match trigger. These
-* should not be implemented and aren't further documented here.
-*
-* 2: The trigger is an address/data match trigger. The remaining bits
-* in this register act as described in \Rmcontrol.
-*
-* 3: The trigger is an instruction count trigger. The remaining bits
-* in this register act as described in \Ricount.
-*
-* 4: The trigger is an interrupt trigger. The remaining bits
-* in this register act as described in \Ritrigger.
-*
-* 5: The trigger is an exception trigger. The remaining bits
-* in this register act as described in \Retrigger.
-*
-* 15: This trigger exists (so enumeration shouldn't terminate), but
-* is not currently available.
-*
-* Other values are reserved for future use.
-*
-* When this field is written to an unsupported value, it takes on its
-* reset value instead. The reset value is any one of the types
-* supported by the trigger selected by \Rtselect.
- */
-#define CSR_TDATA1_TYPE_OFFSET              (MXLEN-4)
+ * 0: There is no trigger at this \RcsrTselect.
+ *
+ * 1: The trigger is a legacy SiFive address match trigger. These
+ * should not be implemented and aren't further documented here.
+ *
+ * 2: The trigger is an address/data match trigger. The remaining bits
+ * in this register act as described in \RcsrMcontrol.
+ *
+ * 3: The trigger is an instruction count trigger. The remaining bits
+ * in this register act as described in \RcsrIcount.
+ *
+ * 4: The trigger is an interrupt trigger. The remaining bits
+ * in this register act as described in \RcsrItrigger.
+ *
+ * 5: The trigger is an exception trigger. The remaining bits
+ * in this register act as described in \RcsrEtrigger.
+ *
+ * 12--14: These trigger types are available for non-standard use.
+ *
+ * 15: This trigger exists (so enumeration shouldn't terminate), but
+ * is not currently available.
+ *
+ * Other values are reserved for future use.
+ */
+#define CSR_TDATA1_TYPE_OFFSET              (XLEN-4)
 #define CSR_TDATA1_TYPE_LENGTH              4
 #define CSR_TDATA1_TYPE                     (0xfULL << CSR_TDATA1_TYPE_OFFSET)
 /*
-* 0: Both Debug and M Mode can write the {\tt tdata} registers at the
-* selected \Rtselect.
-*
-* 1: Only Debug Mode can write the {\tt tdata} registers at the
-* selected \Rtselect.  Writes from other modes are ignored.
-*
-* This bit is only writable from Debug Mode.
- */
-#define CSR_TDATA1_DMODE_OFFSET             (MXLEN-5)
+ * If \FcsrTdataOneType is 0, then this bit is hard-wired to 0.
+ *
+ * 0: Both Debug and M-mode can write the {\tt tdata} registers at the
+ * selected \RcsrTselect.
+ *
+ * 1: Only Debug Mode can write the {\tt tdata} registers at the
+ * selected \RcsrTselect.  Writes from other modes are ignored.
+ *
+ * This bit is only writable from Debug Mode.
+ * When clearing this bit, the debugger should also clear the action field
+ * (whose location depends on \FcsrTdataOneType).
+ */
+#define CSR_TDATA1_DMODE_OFFSET             (XLEN-5)
 #define CSR_TDATA1_DMODE_LENGTH             1
 #define CSR_TDATA1_DMODE                    (0x1ULL << CSR_TDATA1_DMODE_OFFSET)
 /*
-* Trigger-specific data.
+ * If \FcsrTdataOneType is 0, then this field is hard-wired to 0.
+ *
+ * Trigger-specific data.
  */
 #define CSR_TDATA1_DATA_OFFSET              0
-#define CSR_TDATA1_DATA_LENGTH              (MXLEN - 5)
-#define CSR_TDATA1_DATA                     (((1L<<MXLEN - 5)-1) << CSR_TDATA1_DATA_OFFSET)
+#define CSR_TDATA1_DATA_LENGTH              (XLEN - 5)
+#define CSR_TDATA1_DATA                     (((1L << XLEN - 5) - 1) << CSR_TDATA1_DATA_OFFSET)
 #define CSR_TDATA2                          0x7a2
 #define CSR_TDATA2_DATA_OFFSET              0
-#define CSR_TDATA2_DATA_LENGTH              MXLEN
-#define CSR_TDATA2_DATA                     (((1L<<MXLEN)-1) << CSR_TDATA2_DATA_OFFSET)
+#define CSR_TDATA2_DATA_LENGTH              XLEN
+#define CSR_TDATA2_DATA                     (((1L << XLEN) - 1) << CSR_TDATA2_DATA_OFFSET)
 #define CSR_TDATA3                          0x7a3
 #define CSR_TDATA3_DATA_OFFSET              0
-#define CSR_TDATA3_DATA_LENGTH              MXLEN
-#define CSR_TDATA3_DATA                     (((1L<<MXLEN)-1) << CSR_TDATA3_DATA_OFFSET)
+#define CSR_TDATA3_DATA_LENGTH              XLEN
+#define CSR_TDATA3_DATA                     (((1L << XLEN) - 1) << CSR_TDATA3_DATA_OFFSET)
 #define CSR_TINFO                           0x7a4
 /*
-* One bit for each possible \Ftype enumerated in \Rtdataone. Bit N
-* corresponds to type N. If the bit is set, then that type is
-* supported by the currently selected trigger.
-*
-* If the currently selected trigger doesn't exist, this field
-* contains 1.
-*
-* If \Ftype is not writable, this register may be unimplemented, in
-* which case reading it causes an illegal instruction exception. In
-* this case the debugger can read the only supported type from
-* \Rtdataone.
+ * One bit for each possible \FcsrTdataOneType enumerated in \RcsrTdataOne. Bit N
+ * corresponds to type N. If the bit is set, then that type is
+ * supported by the currently selected trigger.
+ *
+ * If the currently selected trigger doesn't exist, this field
+ * contains 1.
  */
 #define CSR_TINFO_INFO_OFFSET               0
 #define CSR_TINFO_INFO_LENGTH               16
 #define CSR_TINFO_INFO                      (0xffffULL << CSR_TINFO_INFO_OFFSET)
+#define CSR_TCONTROL                        0x7a5
+/*
+ * M-mode previous trigger enable field.
+ *
+ * When a trap into M-mode is taken, \FcsrTcontrolMpte is set to the value of
+ * \FcsrTcontrolMte.
+ */
+#define CSR_TCONTROL_MPTE_OFFSET            7
+#define CSR_TCONTROL_MPTE_LENGTH            1
+#define CSR_TCONTROL_MPTE                   (0x1ULL << CSR_TCONTROL_MPTE_OFFSET)
+/*
+ * M-mode trigger enable field.
+ *
+ * 0: Triggers with action=0 do not match/fire while the hart is in M-mode.
+ *
+ * 1: Triggers do match/fire while the hart is in M-mode.
+ *
+ * When a trap into M-mode is taken, \FcsrTcontrolMte is set to 0. When {\tt
+ * mret} is executed, \FcsrTcontrolMte is set to the value of \FcsrTcontrolMpte.
+ */
+#define CSR_TCONTROL_MTE_OFFSET             3
+#define CSR_TCONTROL_MTE_LENGTH             1
+#define CSR_TCONTROL_MTE                    (0x1ULL << CSR_TCONTROL_MTE_OFFSET)
+#define CSR_MCONTEXT                        0x7a8
+/*
+ * Machine mode software can write a context number to this register,
+ * which can be used to set triggers that only fire in that specific
+ * context.
+ *
+ * An implementation may tie any number of upper bits in this field to
+ * 0. It's recommended to implement no more than 6 bits on RV32, and
+ * 13 on RV64.
+ */
+#define CSR_MCONTEXT_MCONTEXT_OFFSET        0
+#define CSR_MCONTEXT_MCONTEXT_LENGTH        XLEN
+#define CSR_MCONTEXT_MCONTEXT               (((1L << XLEN) - 1) << CSR_MCONTEXT_MCONTEXT_OFFSET)
+#define CSR_SCONTEXT                        0x7aa
+/*
+ * Supervisor mode software can write a context number to this
+ * register, which can be used to set triggers that only fire in that
+ * specific context.
+ *
+ * An implementation may tie any number of high bits in this field to
+ * 0. It's recommended to implement no more than 16 bits on RV32, and
+ * 34 on RV64.
+ */
+#define CSR_SCONTEXT_DATA_OFFSET            0
+#define CSR_SCONTEXT_DATA_LENGTH            XLEN
+#define CSR_SCONTEXT_DATA                   (((1L << XLEN) - 1) << CSR_SCONTEXT_DATA_OFFSET)
 #define CSR_MCONTROL                        0x7a1
-#define CSR_MCONTROL_TYPE_OFFSET            (MXLEN-4)
+#define CSR_MCONTROL_TYPE_OFFSET            (XLEN-4)
 #define CSR_MCONTROL_TYPE_LENGTH            4
 #define CSR_MCONTROL_TYPE                   (0xfULL << CSR_MCONTROL_TYPE_OFFSET)
-#define CSR_MCONTROL_DMODE_OFFSET           (MXLEN-5)
+#define CSR_MCONTROL_DMODE_OFFSET           (XLEN-5)
 #define CSR_MCONTROL_DMODE_LENGTH           1
 #define CSR_MCONTROL_DMODE                  (0x1ULL << CSR_MCONTROL_DMODE_OFFSET)
 /*
-* Specifies the largest naturally aligned powers-of-two (NAPOT) range
-* supported by the hardware when \Fmatch is 1. The value is the
-* logarithm base 2 of the
-* number of bytes in that range.  A value of 0 indicates that only
-* exact value matches are supported (one byte range). A value of 63
-* corresponds to the maximum NAPOT range, which is $2^{63}$ bytes in
-* size.
+ * Specifies the largest naturally aligned powers-of-two (NAPOT) range
+ * supported by the hardware when \FcsrMcontrolMatch is 1. The value is the
+ * logarithm base 2 of the
+ * number of bytes in that range.  A value of 0 indicates that only
+ * exact value matches are supported (one byte range). A value of 63
+ * corresponds to the maximum NAPOT range, which is $2^{63}$ bytes in
+ * size.
  */
-#define CSR_MCONTROL_MASKMAX_OFFSET         (MXLEN-11)
+#define CSR_MCONTROL_MASKMAX_OFFSET         (XLEN-11)
 #define CSR_MCONTROL_MASKMAX_LENGTH         6
 #define CSR_MCONTROL_MASKMAX                (0x3fULL << CSR_MCONTROL_MASKMAX_OFFSET)
 /*
-* If this optional bit is implemented, the hardware sets it when this
-* trigger matches. The trigger's user can set or clear it at any
-* time. The trigger's user can use this bit to determine which
-* trigger(s) matched.  If the bit is not implemented, it is always 0
-* and writing it has no effect.
+ * This field only exists when XLEN is at least 64.
+ * It contains the 2 high bits of the access size. The low bits
+ * come from \FcsrMcontrolSizelo. See \FcsrMcontrolSizelo for how this
+ * is used.
+ */
+#define CSR_MCONTROL_SIZEHI_OFFSET          21
+#define CSR_MCONTROL_SIZEHI_LENGTH          2
+#define CSR_MCONTROL_SIZEHI                 (0x3ULL << CSR_MCONTROL_SIZEHI_OFFSET)
+/*
+ * If this bit is implemented, the hardware sets it when this
+ * trigger matches. The trigger's user can set or clear it at any
+ * time. It is used to determine which
+ * trigger(s) matched.  If the bit is not implemented, it is always 0
+ * and writing it has no effect.
  */
 #define CSR_MCONTROL_HIT_OFFSET             20
 #define CSR_MCONTROL_HIT_LENGTH             1
 #define CSR_MCONTROL_HIT                    (0x1ULL << CSR_MCONTROL_HIT_OFFSET)
 /*
-* 0: Perform a match on the virtual address.
-*
-* 1: Perform a match on the data value loaded/stored, or the
-* instruction executed.
+ * 0: Perform a match on the lowest virtual address of the access.  In
+ * addition, it is recommended that the trigger also fires if any of
+ * the other accessed virtual addresses match.
+ * (E.g. on a 32-bit read from 0x4000, the lowest address is 0x4000
+ * and the other addresses are 0x4001, 0x4002, and 0x4003.)
+ *
+ * 1: Perform a match on the data value loaded or stored, or the
+ * instruction executed.
  */
 #define CSR_MCONTROL_SELECT_OFFSET          19
 #define CSR_MCONTROL_SELECT_LENGTH          1
 #define CSR_MCONTROL_SELECT                 (0x1ULL << CSR_MCONTROL_SELECT_OFFSET)
 /*
-* 0: The action for this trigger will be taken just before the
-* instruction that triggered it is executed, but after all preceding
-* instructions are are committed.
-*
-* 1: The action for this trigger will be taken after the instruction
-* that triggered it is executed. It should be taken before the next
-* instruction is executed, but it is better to implement triggers and
-* not implement that suggestion than to not implement them at all.
-*
-* Most hardware will only implement one timing or the other, possibly
-* dependent on \Fselect, \Fexecute, \Fload, and \Fstore. This bit
-* primarily exists for the hardware to communicate to the debugger
-* what will happen. Hardware may implement the bit fully writable, in
-* which case the debugger has a little more control.
-*
-* Data load triggers with \Ftiming of 0 will result in the same load
-* happening again when the debugger lets the hart run. For data load
-* triggers, debuggers must first attempt to set the breakpoint with
-* \Ftiming of 1.
-*
-* A chain of triggers that don't all have the same \Ftiming value
-* will never fire (unless consecutive instructions match the
-* appropriate triggers).
+ * 0: The action for this trigger will be taken just before the
+ * instruction that triggered it is executed, but after all preceding
+ * instructions are committed. \Rmepc or \RcsrDpc (depending on
+ * \FcsrMcontrolAction) must be set to the virtual address of the
+ * instruction that matched.
+ *
+ * If this is combined with \FcsrMcontrolLoad then a memory access will be
+ * performed (including any side effects of performing such an access) even
+ * though the load will not update its destination register. Debuggers
+ * should consider this when setting such breakpoints on, for example,
+ * memory-mapped I/O addresses.
+ *
+ * 1: The action for this trigger will be taken after the instruction
+ * that triggered it is executed. It should be taken before the next
+ * instruction is executed, but it is better to implement triggers imprecisely
+ * than to not implement them at all.
+ * \Rmepc or \RcsrDpc (depending on \FcsrMcontrolAction) must be set to
+ * the virtual address of the next instruction that must be executed to
+ * preserve the program flow.
+ *
+ * Most hardware will only implement one timing or the other, possibly
+ * dependent on \FcsrMcontrolSelect, \FcsrMcontrolExecute,
+ * \FcsrMcontrolLoad, and \FcsrMcontrolStore. This bit
+ * primarily exists for the hardware to communicate to the debugger
+ * what will happen. Hardware may implement the bit fully writable, in
+ * which case the debugger has a little more control.
+ *
+ * Data load triggers with \FcsrMcontrolTiming of 0 will result in the same load
+ * happening again when the debugger lets the hart run. For data load
+ * triggers, debuggers must first attempt to set the breakpoint with
+ * \FcsrMcontrolTiming of 1.
+ *
+ * If a trigger with \FcsrMcontrolTiming of 0 matches, it is
+ * implementation-dependent whether that prevents a trigger with
+ * \FcsrMcontrolTiming of 1 matching as well.
  */
 #define CSR_MCONTROL_TIMING_OFFSET          18
 #define CSR_MCONTROL_TIMING_LENGTH          1
 #define CSR_MCONTROL_TIMING                 (0x1ULL << CSR_MCONTROL_TIMING_OFFSET)
 /*
-* The action to take when the trigger fires. The values are explained
-* in Table~\ref{tab:action}.
+ * This field contains the 2 low bits of the access size. The high bits come
+ * from \FcsrMcontrolSizehi. The combined value is interpreted as follows:
+ *
+ * 0: The trigger will attempt to match against an access of any size.
+ * The behavior is only well-defined if $|select|=0$, or if the access
+ * size is XLEN.
+ *
+ * 1: The trigger will only match against 8-bit memory accesses.
+ *
+ * 2: The trigger will only match against 16-bit memory accesses or
+ * execution of 16-bit instructions.
+ *
+ * 3: The trigger will only match against 32-bit memory accesses or
+ * execution of 32-bit instructions.
+ *
+ * 4: The trigger will only match against execution of 48-bit instructions.
+ *
+ * 5: The trigger will only match against 64-bit memory accesses or
+ * execution of 64-bit instructions.
+ *
+ * 6: The trigger will only match against execution of 80-bit instructions.
+ *
+ * 7: The trigger will only match against execution of 96-bit instructions.
+ *
+ * 8: The trigger will only match against execution of 112-bit instructions.
+ *
+ * 9: The trigger will only match against 128-bit memory accesses or
+ * execution of 128-bit instructions.
+ *
+ * An implementation must support the value of 0, but all other values
+ * are optional. It is recommended to support triggers for every
+ * access size the hart supports, as well as for every instruction
+ * size the hart supports.
+ */
+#define CSR_MCONTROL_SIZELO_OFFSET          16
+#define CSR_MCONTROL_SIZELO_LENGTH          2
+#define CSR_MCONTROL_SIZELO                 (0x3ULL << CSR_MCONTROL_SIZELO_OFFSET)
+/*
+ * The action to take when the trigger fires. The values are explained
+ * in Table~\ref{tab:action}.
  */
 #define CSR_MCONTROL_ACTION_OFFSET          12
-#define CSR_MCONTROL_ACTION_LENGTH          6
-#define CSR_MCONTROL_ACTION                 (0x3fULL << CSR_MCONTROL_ACTION_OFFSET)
-/*
-* 0: When this trigger matches, the configured action is taken.
-*
-* 1: While this trigger does not match, it prevents the trigger with
-* the next index from matching.
-*
-* Because \Fchain affects the next trigger, hardware must zero it in
-* writes to \Rmcontrol that set \Fdmode to 0 if the next trigger has
-* \Fdmode of 1.
-* In addition hardware should ignore writes to \Rmcontrol that set
-* \Fdmode to 1 if the previous trigger has both \Fdmode of 0 and
-* \Fchain of 1. Debuggers must avoid the latter case by checking
-* \Fchain on the previous trigger if they're writing \Rmcontrol.
-*
-* Implementations that wish to limit the maximum length of a trigger
-* chain (eg. to meet timing requirements) may do so by zeroing
-* \Fchain in writes to \Rmcontrol that would make the chain too long.
+#define CSR_MCONTROL_ACTION_LENGTH          4
+#define CSR_MCONTROL_ACTION                 (0xfULL << CSR_MCONTROL_ACTION_OFFSET)
+/*
+ * 0: When this trigger matches, the configured action is taken.
+ *
+ * 1: While this trigger does not match, it prevents the trigger with
+ * the next index from matching.
+ *
+ * A trigger chain starts on the first trigger with $|chain|=1$ after
+ * a trigger with $|chain|=0$, or simply on the first trigger if that
+ * has $|chain|=1$. It ends on the first trigger after that which has
+ * $|chain|=0$. This final trigger is part of the chain. The action
+ * on all but the final trigger is ignored.  The action on that final
+ * trigger will be taken if and only if all the triggers in the chain
+ * match at the same time.
+ *
+ * Because \FcsrMcontrolChain affects the next trigger, hardware must zero it in
+ * writes to \RcsrMcontrol that set \FcsrTdataOneDmode to 0 if the next trigger has
+ * \FcsrTdataOneDmode of 1.
+ * In addition hardware should ignore writes to \RcsrMcontrol that set
+ * \FcsrTdataOneDmode to 1 if the previous trigger has both \FcsrTdataOneDmode of 0 and
+ * \FcsrMcontrolChain of 1. Debuggers must avoid the latter case by checking
+ * \FcsrMcontrolChain on the previous trigger if they're writing \RcsrMcontrol.
+ *
+ * Implementations that wish to limit the maximum length of a trigger
+ * chain (eg. to meet timing requirements) may do so by zeroing
+ * \FcsrMcontrolChain in writes to \RcsrMcontrol that would make the chain too long.
  */
 #define CSR_MCONTROL_CHAIN_OFFSET           11
 #define CSR_MCONTROL_CHAIN_LENGTH           1
 #define CSR_MCONTROL_CHAIN                  (0x1ULL << CSR_MCONTROL_CHAIN_OFFSET)
 /*
-* 0: Matches when the value equals \Rtdatatwo.
-*
-* 1: Matches when the top M bits of the value match the top M bits of
-* \Rtdatatwo. M is MXLEN-1 minus the index of the least-significant
-* bit containing 0 in \Rtdatatwo.
-*
-* 2: Matches when the value is greater than (unsigned) or equal to
-* \Rtdatatwo.
-*
-* 3: Matches when the value is less than (unsigned) \Rtdatatwo.
-*
-* 4: Matches when the lower half of the value equals the lower half
-* of \Rtdatatwo after the lower half of the value is ANDed with the
-* upper half of \Rtdatatwo.
-*
-* 5: Matches when the upper half of the value equals the lower half
-* of \Rtdatatwo after the upper half of the value is ANDed with the
-* upper half of \Rtdatatwo.
-*
-* Other values are reserved for future use.
+ * 0: Matches when the value equals \RcsrTdataTwo.
+ *
+ * 1: Matches when the top M bits of the value match the top M bits of
+ * \RcsrTdataTwo. M is XLEN-1 minus the index of the least-significant
+ * bit containing 0 in \RcsrTdataTwo. Debuggers should only write values
+ * to \RcsrTdataTwo such that M + \FcsrMcontrolMaskmax $\geq$ XLEN, otherwise it's
+ * undefined on what conditions the trigger will fire.
+ *
+ * 2: Matches when the value is greater than (unsigned) or equal to
+ * \RcsrTdataTwo.
+ *
+ * 3: Matches when the value is less than (unsigned) \RcsrTdataTwo.
+ *
+ * 4: Matches when the lower half of the value equals the lower half
+ * of \RcsrTdataTwo after the lower half of the value is ANDed with the
+ * upper half of \RcsrTdataTwo.
+ *
+ * 5: Matches when the upper half of the value equals the lower half
+ * of \RcsrTdataTwo after the upper half of the value is ANDed with the
+ * upper half of \RcsrTdataTwo.
+ *
+ * 8: Matches when \FcsrMcontrolMatch$=0$ would not match.
+ *
+ * 9: Matches when \FcsrMcontrolMatch$=1$ would not match.
+ *
+ * 12: Matches when \FcsrMcontrolMatch$=4$ would not match.
+ *
+ * 13: Matches when \FcsrMcontrolMatch$=5$ would not match.
+ *
+ * Other values are reserved for future use.
  */
 #define CSR_MCONTROL_MATCH_OFFSET           7
 #define CSR_MCONTROL_MATCH_LENGTH           4
 #define CSR_MCONTROL_MATCH                  (0xfULL << CSR_MCONTROL_MATCH_OFFSET)
 /*
-* When set, enable this trigger in M mode.
+ * When set, enable this trigger in M-mode.
  */
 #define CSR_MCONTROL_M_OFFSET               6
 #define CSR_MCONTROL_M_LENGTH               1
 #define CSR_MCONTROL_M                      (0x1ULL << CSR_MCONTROL_M_OFFSET)
 /*
-* When set, enable this trigger in S mode.
+ * When set, enable this trigger in S-mode.
  */
 #define CSR_MCONTROL_S_OFFSET               4
 #define CSR_MCONTROL_S_LENGTH               1
 #define CSR_MCONTROL_S                      (0x1ULL << CSR_MCONTROL_S_OFFSET)
 /*
-* When set, enable this trigger in U mode.
+ * When set, enable this trigger in U-mode.
  */
 #define CSR_MCONTROL_U_OFFSET               3
 #define CSR_MCONTROL_U_LENGTH               1
 #define CSR_MCONTROL_U                      (0x1ULL << CSR_MCONTROL_U_OFFSET)
 /*
-* When set, the trigger fires on the virtual address or opcode of an
-* instruction that is executed.
+ * When set, the trigger fires on the virtual address or opcode of an
+ * instruction that is executed.
  */
 #define CSR_MCONTROL_EXECUTE_OFFSET         2
 #define CSR_MCONTROL_EXECUTE_LENGTH         1
 #define CSR_MCONTROL_EXECUTE                (0x1ULL << CSR_MCONTROL_EXECUTE_OFFSET)
 /*
-* When set, the trigger fires on the virtual address or data of a store.
+ * When set, the trigger fires on the virtual address or data of any
+ * store.
  */
 #define CSR_MCONTROL_STORE_OFFSET           1
 #define CSR_MCONTROL_STORE_LENGTH           1
 #define CSR_MCONTROL_STORE                  (0x1ULL << CSR_MCONTROL_STORE_OFFSET)
 /*
-* When set, the trigger fires on the virtual address or data of a load.
+ * When set, the trigger fires on the virtual address or data of any
+ * load.
  */
 #define CSR_MCONTROL_LOAD_OFFSET            0
 #define CSR_MCONTROL_LOAD_LENGTH            1
 #define CSR_MCONTROL_LOAD                   (0x1ULL << CSR_MCONTROL_LOAD_OFFSET)
 #define CSR_ICOUNT                          0x7a1
-#define CSR_ICOUNT_TYPE_OFFSET              (MXLEN-4)
+#define CSR_ICOUNT_TYPE_OFFSET              (XLEN-4)
 #define CSR_ICOUNT_TYPE_LENGTH              4
 #define CSR_ICOUNT_TYPE                     (0xfULL << CSR_ICOUNT_TYPE_OFFSET)
-#define CSR_ICOUNT_DMODE_OFFSET             (MXLEN-5)
+#define CSR_ICOUNT_DMODE_OFFSET             (XLEN-5)
 #define CSR_ICOUNT_DMODE_LENGTH             1
 #define CSR_ICOUNT_DMODE                    (0x1ULL << CSR_ICOUNT_DMODE_OFFSET)
 /*
-* If this optional bit is implemented, the hardware sets it when this
-* trigger matches. The trigger's user can set or clear it at any
-* time. The trigger's user can use this bit to determine which
-* trigger(s) matched.  If the bit is not implemented, it is always 0
-* and writing it has no effect.
+ * If this bit is implemented, the hardware sets it when this
+ * trigger matches. The trigger's user can set or clear it at any
+ * time. It is used to determine which
+ * trigger(s) matched.  If the bit is not implemented, it is always 0
+ * and writing it has no effect.
  */
 #define CSR_ICOUNT_HIT_OFFSET               24
 #define CSR_ICOUNT_HIT_LENGTH               1
 #define CSR_ICOUNT_HIT                      (0x1ULL << CSR_ICOUNT_HIT_OFFSET)
 /*
-* When count is decremented to 0, the trigger fires. Instead of
-* changing \Fcount from 1 to 0, it is also acceptable for hardware to
-* clear \Fm, \Fs, and \Fu. This allows \Fcount to be hard-wired
-* to 1 if this register just exists for single step.
+ * When count is decremented to 0, the trigger fires. Instead of
+ * changing \FcsrIcountCount from 1 to 0, it is also acceptable for hardware to
+ * clear \FcsrMcontrolM, \FcsrMcontrolS, and \FcsrMcontrolU. This allows \FcsrIcountCount to be hard-wired
+ * to 1 if this register just exists for single step.
  */
 #define CSR_ICOUNT_COUNT_OFFSET ...
 
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- Log -----------------------------------------------------------------
commit fc7edd57ac6678d1113bc09265798de3fdc68347
Author: Benedikt-Alexander Mokroß <mo...@ge...>
Date:   Mon Aug 24 10:59:27 2020 +0200

    flash/nor/at91sam4: ATSAMG55x19 Rev.B
    
    Add support for ATSAMG55x19 Rev.B.
    Both chips have nearly the same cidr, however, Rev.B has an incremented version.
    
    Change-Id: I5939c41fa5d54c4d3bfb850964974b878f709d13
    Signed-off-by: Benedikt-Alexander Mokroß <mo...@ge...>
    Reviewed-on: http://openocd.zylin.com/5825
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins

diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c
index 1c6106425..86abf7005 100644
--- a/src/flash/nor/at91sam4.c
+++ b/src/flash/nor/at91sam4.c
@@ -1330,7 +1330,7 @@ static const struct sam4_chip_details all_sam4_details[] = {
 		}
 	},
 
-	/* atsamg55g19 */
+	/* atsamg55g19 Rev.A */
 	{
 		.chipid_cidr    = 0x24470ae0,
 		.name           = "atsamg55g19",
@@ -1364,7 +1364,41 @@ static const struct sam4_chip_details all_sam4_details[] = {
 		}
 	},
 
-	/* atsamg55j19 */
+	/* atsamg55g19 Rev.B */
+	{
+		.chipid_cidr    = 0x24470ae1,
+		.name           = "atsamg55g19b",
+		.total_flash_size     = 512 * 1024,
+		.total_sram_size      = 160 * 1024,
+		.n_gpnvms       = 2,
+		.n_banks        = 1,
+
+		{
+/*			.bank[0] = */
+			{
+				.probed = false,
+				.pChip  = NULL,
+				.pBank  = NULL,
+				.bank_number = 0,
+				.base_address = FLASH_BANK_BASE_S,
+				.controller_address = 0x400e0a00,
+				.flash_wait_states = 5,
+				.present = true,
+				.size_bytes =  512 * 1024,
+				.nsectors   =  64,
+				.sector_size = 8192,
+				.page_size   = 512,
+			},
+/*			.bank[1] = */
+			{
+				.present = false,
+				.probed = false,
+				.bank_number = 1,
+			},
+		}
+	},
+
+	/* atsamg55j19 Rev.A */
 	{
 		.chipid_cidr    = 0x24570ae0,
 		.name           = "atsamg55j19",
@@ -1398,6 +1432,40 @@ static const struct sam4_chip_details all_sam4_details[] = {
 		}
 	},
 
+	/* atsamg55j19 Rev.B */
+	{
+		.chipid_cidr    = 0x24570ae1,
+		.name           = "atsamg55j19b",
+		.total_flash_size     = 512 * 1024,
+		.total_sram_size      = 160 * 1024,
+		.n_gpnvms       = 2,
+		.n_banks        = 1,
+
+		{
+/*			.bank[0] = */
+			{
+				.probed = false,
+				.pChip  = NULL,
+				.pBank  = NULL,
+				.bank_number = 0,
+				.base_address = FLASH_BANK_BASE_S,
+				.controller_address = 0x400e0a00,
+				.flash_wait_states = 5,
+				.present = true,
+				.size_bytes =  512 * 1024,
+				.nsectors   =  64,
+				.sector_size = 8192,
+				.page_size   = 512,
+			},
+/*			.bank[1] = */
+			{
+				.present = false,
+				.probed = false,
+				.bank_number = 1,
+			},
+		}
+	},
+
 	/* terminate */
 	{
 		.chipid_cidr    = 0,

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/at91sam4.c | 72 ++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 70 insertions(+), 2 deletions(-)


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- Log -----------------------------------------------------------------
commit 3ffa14b043225b9766132b1979db7ddb8d91ba5e
Author: Antonio Borneo <bor...@gm...>
Date:   Wed Sep 16 15:26:40 2020 +0200

    target/aarch64: fix use of 'target->private_config'
    
    The function adiv5_jim_configure() casts the void pointer
    'target->private_config' to a struct adiv5_private_config pointer.
    This is tricky in case of aarch64, where the private data are in a
    struct aarch64_private_config that has as first element the struct
    adiv5_private_config.
    
    While the current solution is working fine, it's not clean and
    requires special attention for any further code development.
    
    Override 'target->private_config' to the correct pointer while
    calling adiv5_jim_configure().
    
    Change-Id: Ic2fc047dd1e57013943d96e6d5879a919d1eb7b3
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5847
    Tested-by: jenkins
    Reviewed-by: Tarek BOCHKATI <tar...@gm...>

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 8d23bcabc..d111a0568 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -2504,8 +2504,13 @@ static int aarch64_jim_configure(struct target *target, Jim_GetOptInfo *goi)
 	 * options, JIM_OK if it correctly parsed the topmost option
 	 * and JIM_ERR if an error occurred during parameter evaluation.
 	 * For JIM_CONTINUE, we check our own params.
+	 *
+	 * adiv5_jim_configure() assumes 'private_config' to point to
+	 * 'struct adiv5_private_config'. Override 'private_config'!
 	 */
+	target->private_config = &pc->adiv5_config;
 	e = adiv5_jim_configure(target, goi);
+	target->private_config = pc;
 	if (e != JIM_CONTINUE)
 		return e;
 

commit 63d3640add4c024864b18d021f626fd377b1165c
Author: Kevin Yang <kan...@go...>
Date:   Wed Sep 2 20:15:31 2020 -0700

    target/aarch64: Use apnum setting
    
    Change aarch64 to use ap-num setting if provided. Fall back to original
    behavior of using first AP when ap-num is invalid.
    
    Change-Id: I0d3624f75c86ba5fd5a322ac60856dbbb6e71eaf
    Signed-off-by: Kevin Yang <kan...@go...>
    Reviewed-on: http://openocd.zylin.com/5831
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index dee16d116..8d23bcabc 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -2248,7 +2248,7 @@ static int aarch64_examine_first(struct target *target)
 	struct aarch64_common *aarch64 = target_to_aarch64(target);
 	struct armv8_common *armv8 = &aarch64->armv8_common;
 	struct adiv5_dap *swjdp = armv8->arm.dap;
-	struct aarch64_private_config *pc;
+	struct aarch64_private_config *pc = target->private_config;
 	int i;
 	int retval = ERROR_OK;
 	uint64_t debug, ttypr;
@@ -2256,11 +2256,18 @@ static int aarch64_examine_first(struct target *target)
 	uint32_t tmp0, tmp1, tmp2, tmp3;
 	debug = ttypr = cpuid = 0;
 
-	/* Search for the APB-AB - it is needed for access to debug registers */
-	retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv8->debug_ap);
-	if (retval != ERROR_OK) {
-		LOG_ERROR("Could not find APB-AP for debug access");
-		return retval;
+	if (pc == NULL)
+		return ERROR_FAIL;
+
+	if (pc->adiv5_config.ap_num == DP_APSEL_INVALID) {
+		/* Search for the APB-AB */
+		retval = dap_find_ap(swjdp, AP_TYPE_APB_AP, &armv8->debug_ap);
+		if (retval != ERROR_OK) {
+			LOG_ERROR("Could not find APB-AP for debug access");
+			return retval;
+		}
+	} else {
+		armv8->debug_ap = dap_ap(swjdp, pc->adiv5_config.ap_num);
 	}
 
 	retval = mem_ap_init(armv8->debug_ap);
@@ -2335,10 +2342,6 @@ static int aarch64_examine_first(struct target *target)
 	LOG_DEBUG("ttypr = 0x%08" PRIx64, ttypr);
 	LOG_DEBUG("debug = 0x%08" PRIx64, debug);
 
-	if (target->private_config == NULL)
-		return ERROR_FAIL;
-
-	pc = (struct aarch64_private_config *)target->private_config;
 	if (pc->cti == NULL)
 		return ERROR_FAIL;
 
@@ -2491,6 +2494,7 @@ static int aarch64_jim_configure(struct target *target, Jim_GetOptInfo *goi)
 	pc = (struct aarch64_private_config *)target->private_config;
 	if (pc == NULL) {
 			pc = calloc(1, sizeof(struct aarch64_private_config));
+			pc->adiv5_config.ap_num = DP_APSEL_INVALID;
 			target->private_config = pc;
 	}
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/aarch64.c | 29 +++++++++++++++++++----------
 1 file changed, 19 insertions(+), 10 deletions(-)


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- Log -----------------------------------------------------------------
commit 9a877a83a1c8b1f105cdc0de46c5cbc4d9e8799e
Author: Antonio Borneo <bor...@gm...>
Date:   Thu Oct 1 14:19:16 2020 +0200

    drivers/jlink: fix (again) calculate_swo_prescaler formula
    
    The prescaler computation should round at the nearest integer
    value, not to the next integer value.
    
    Change-Id: I957e0774421211f3c4ba4b312738b1c67b87c4a2
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Fixes: 051e80812b1b ("drivers/jlink: fix calculate_swo_prescaler formula")
    Reviewed-on: http://openocd.zylin.com/5846
    Tested-by: jenkins
    Reviewed-by: Adrian M Negreanu <adr...@nx...>

diff --git a/src/jtag/drivers/jlink.c b/src/jtag/drivers/jlink.c
index 910799ce2..ae8ce49c6 100644
--- a/src/jtag/drivers/jlink.c
+++ b/src/jtag/drivers/jlink.c
@@ -1269,8 +1269,7 @@ static uint32_t calculate_trace_buffer_size(void)
 static bool calculate_swo_prescaler(unsigned int traceclkin_freq,
 		uint32_t trace_freq, uint16_t *prescaler)
 {
-	unsigned int presc;
-	presc = DIV_ROUND_UP(traceclkin_freq, trace_freq);
+	unsigned int presc = (traceclkin_freq + trace_freq / 2) / trace_freq;
 	if (presc > TPIU_ACPR_MAX_SWOSCALER)
 		return false;
 

commit 87d2651edc595bd40a1cf65a7666bbc8247397f9
Author: Andreas Fritiofson <and...@gm...>
Date:   Sat Dec 24 11:38:04 2016 +0100

    Update user dir config file search path
    
    Search in XDG_CONFIG_HOME as per XDG Base Directory Specification
    in addition to $HOME/.openocd.
    
    On Darwin, search in ~/Library/Preferences/org.openocd/ which
    appears to be one of the conventional locations.
    
    Make $OPENOCD_SCRIPTS highest priority on all platforms, previously
    it was only higher on WIN32.
    
    Update the documentation to reflect the search order.
    
    Change-Id: Ibaf4b59b51fdf452712d91b47ea2b5312bb5ada9
    Signed-off-by: Andreas Fritiofson <and...@gm...>
    Reviewed-on: http://openocd.zylin.com/3890
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 3506ccab1..90b49ee35 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -724,8 +724,11 @@ Configuration files and scripts are searched for in
 @item the current directory,
 @item any search dir specified on the command line using the @option{-s} option,
 @item any search dir specified using the @command{add_script_search_dir} command,
-@item @file{$HOME/.openocd} (not on Windows),
 @item a directory in the @env{OPENOCD_SCRIPTS} environment variable (if set),
+@item @file{%APPDATA%/OpenOCD} (only on Windows),
+@item @file{$HOME/Library/Preferences/org.openocd} (only on Darwin),
+@item @file{$XDG_CONFIG_HOME/openocd} (@env{$XDG_CONFIG_HOME} defaults to @file{$HOME/.config}),
+@item @file{$HOME/.openocd},
 @item the site wide script library @file{$pkgdatadir/site} and
 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
 @end enumerate
diff --git a/src/helper/options.c b/src/helper/options.c
index 6622ece6c..0ccbf5642 100644
--- a/src/helper/options.c
+++ b/src/helper/options.c
@@ -178,6 +178,63 @@ static char *find_relative_path(const char *from, const char *to)
 	return relpath;
 }
 
+static void add_user_dirs(void)
+{
+	char *path;
+
+#if IS_WIN32
+	const char *appdata = getenv("APPDATA");
+
+	if (appdata) {
+		path = alloc_printf("%s/OpenOCD", appdata);
+		if (path) {
+			/* Convert path separators to UNIX style, should work on Windows also. */
+			for (char *p = path; *p; p++) {
+				if (*p == '\\')
+					*p = '/';
+			}
+			add_script_search_dir(path);
+			free(path);
+		}
+	}
+	/* WIN32 may also have HOME defined, particularly under Cygwin, so add those paths below too */
+#endif
+
+	const char *home = getenv("HOME");
+#if IS_DARWIN
+	if (home) {
+		path = alloc_printf("%s/Library/Preferences/org.openocd", home);
+		if (path) {
+			add_script_search_dir(path);
+			free(path);
+		}
+	}
+#endif
+	const char *xdg_config = getenv("XDG_CONFIG_HOME");
+
+	if (xdg_config) {
+		path = alloc_printf("%s/openocd", xdg_config);
+		if (path) {
+			add_script_search_dir(path);
+			free(path);
+		}
+	} else if (home) {
+		path = alloc_printf("%s/.config/openocd", home);
+		if (path) {
+			add_script_search_dir(path);
+			free(path);
+		}
+	}
+
+	if (home) {
+		path = alloc_printf("%s/.openocd", home);
+		if (path) {
+			add_script_search_dir(path);
+			free(path);
+		}
+	}
+}
+
 static void add_default_dirs(void)
 {
 	char *path;
@@ -194,32 +251,11 @@ static void add_default_dirs(void)
 	 * listed last in the built-in search order, so the user can
 	 * override these scripts with site-specific customizations.
 	 */
-	const char *home = getenv("HOME");
-
-	if (home) {
-		path = alloc_printf("%s/.openocd", home);
-		if (path) {
-			add_script_search_dir(path);
-			free(path);
-		}
-	}
-
 	path = getenv("OPENOCD_SCRIPTS");
-
 	if (path)
 		add_script_search_dir(path);
 
-#ifdef _WIN32
-	const char *appdata = getenv("APPDATA");
-
-	if (appdata) {
-		path = alloc_printf("%s/OpenOCD", appdata);
-		if (path) {
-			add_script_search_dir(path);
-			free(path);
-		}
-	}
-#endif
+	add_user_dirs();
 
 	path = alloc_printf("%s/%s/%s", exepath, bin2data, "site");
 	if (path) {

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi         |  5 ++-
 src/helper/options.c     | 80 +++++++++++++++++++++++++++++++++++-------------
 src/jtag/drivers/jlink.c |  3 +-
 3 files changed, 63 insertions(+), 25 deletions(-)


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- Log -----------------------------------------------------------------
commit 2ff1824a87e3aa3b17d88cc58b9b173fc65a4356
Author: Karl Palsson <ka...@et...>
Date:   Thu Sep 24 14:29:36 2020 +0000

    FreeRTOS: strip duplicate line returns
    
    Log lines already print a new line, so these superfluous \r\n result in
    blank lines being printed in the log.  Remove per review comment
    request.
    
    Change-Id: I8f5b20776634cf70ce4490fc4f732c916130928a
    Signed-off-by: Karl Palsson <ka...@et...>
    Reviewed-on: http://openocd.zylin.com/5843
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/rtos/FreeRTOS.c b/src/rtos/FreeRTOS.c
index d663b6e8f..ee9b48bb9 100644
--- a/src/rtos/FreeRTOS.c
+++ b/src/rtos/FreeRTOS.c
@@ -185,7 +185,7 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 	retval = target_read_u32(rtos->target,
 			rtos->symbols[FreeRTOS_VAL_uxCurrentNumberOfTasks].address,
 			&thread_list_size);
-	LOG_DEBUG("FreeRTOS: Read uxCurrentNumberOfTasks at 0x%" PRIx64 ", value %" PRIu32 "\r\n",
+	LOG_DEBUG("FreeRTOS: Read uxCurrentNumberOfTasks at 0x%" PRIx64 ", value %" PRIu32,
 										rtos->symbols[FreeRTOS_VAL_uxCurrentNumberOfTasks].address,
 										thread_list_size);
 
@@ -207,7 +207,7 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 		return retval;
 	}
 	rtos->current_thread = pointer_casts_are_bad;
-	LOG_DEBUG("FreeRTOS: Read pxCurrentTCB at 0x%" PRIx64 ", value 0x%" PRIx64 "\r\n",
+	LOG_DEBUG("FreeRTOS: Read pxCurrentTCB at 0x%" PRIx64 ", value 0x%" PRIx64,
 										rtos->symbols[FreeRTOS_VAL_pxCurrentTCB].address,
 										rtos->current_thread);
 
@@ -255,7 +255,7 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 			&top_used_priority);
 	if (retval != ERROR_OK)
 		return retval;
-	LOG_DEBUG("FreeRTOS: Read uxTopUsedPriority at 0x%" PRIx64 ", value %" PRIu32 "\r\n",
+	LOG_DEBUG("FreeRTOS: Read uxTopUsedPriority at 0x%" PRIx64 ", value %" PRIu32,
 										rtos->symbols[FreeRTOS_VAL_uxTopUsedPriority].address,
 										top_used_priority);
 	if (top_used_priority > FREERTOS_MAX_PRIORITIES) {
@@ -303,7 +303,7 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 			free(list_of_lists);
 			return retval;
 		}
-		LOG_DEBUG("FreeRTOS: Read thread count for list %u at 0x%" PRIx64 ", value %" PRIu32 "\r\n",
+		LOG_DEBUG("FreeRTOS: Read thread count for list %u at 0x%" PRIx64 ", value %" PRIu32,
 										i, list_of_lists[i], list_thread_count);
 
 		if (list_thread_count == 0)
@@ -320,7 +320,7 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 			free(list_of_lists);
 			return retval;
 		}
-		LOG_DEBUG("FreeRTOS: Read first item for list %u at 0x%" PRIx64 ", value 0x%" PRIx32 "\r\n",
+		LOG_DEBUG("FreeRTOS: Read first item for list %u at 0x%" PRIx64 ", value 0x%" PRIx32,
 										i, list_of_lists[i] + param->list_next_offset, list_elem_ptr);
 
 		while ((list_thread_count > 0) && (list_elem_ptr != 0) &&
@@ -337,7 +337,7 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 				return retval;
 			}
 			rtos->thread_details[tasks_found].threadid = pointer_casts_are_bad;
-			LOG_DEBUG("FreeRTOS: Read Thread ID at 0x%" PRIx32 ", value 0x%" PRIx64 "\r\n",
+			LOG_DEBUG("FreeRTOS: Read Thread ID at 0x%" PRIx32 ", value 0x%" PRIx64,
 										list_elem_ptr + param->list_elem_content_offset,
 										rtos->thread_details[tasks_found].threadid);
 
@@ -357,7 +357,7 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 				return retval;
 			}
 			tmp_str[FREERTOS_THREAD_NAME_STR_SIZE-1] = '\x00';
-			LOG_DEBUG("FreeRTOS: Read Thread Name at 0x%" PRIx64 ", value \"%s\"\r\n",
+			LOG_DEBUG("FreeRTOS: Read Thread Name at 0x%" PRIx64 ", value '%s'",
 										rtos->thread_details[tasks_found].threadid + param->thread_name_offset,
 										tmp_str);
 
@@ -391,7 +391,7 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 				free(list_of_lists);
 				return retval;
 			}
-			LOG_DEBUG("FreeRTOS: Read next thread location at 0x%" PRIx32 ", value 0x%" PRIx32 "\r\n",
+			LOG_DEBUG("FreeRTOS: Read next thread location at 0x%" PRIx32 ", value 0x%" PRIx32,
 										prev_list_elem_ptr + param->list_elem_next_offset,
 										list_elem_ptr);
 		}
@@ -430,7 +430,7 @@ static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
 		return retval;
 	}
 	stack_ptr = pointer_casts_are_bad;
-	LOG_DEBUG("FreeRTOS: Read stack pointer at 0x%" PRIx64 ", value 0x%" PRIx64 "\r\n",
+	LOG_DEBUG("FreeRTOS: Read stack pointer at 0x%" PRIx64 ", value 0x%" PRIx64,
 										thread_id + param->thread_stack_offset,
 										stack_ptr);
 
@@ -463,7 +463,7 @@ static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
 				stack_ptr + 0x20,
 				&LR_svc);
 		if (retval != ERROR_OK) {
-			LOG_OUTPUT("Error reading stack frame from FreeRTOS thread\r\n");
+			LOG_OUTPUT("Error reading stack frame from FreeRTOS thread");
 			return retval;
 		}
 		if ((LR_svc & 0x10) == 0)

-----------------------------------------------------------------------

Summary of changes:
 src/rtos/FreeRTOS.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)


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- Log -----------------------------------------------------------------
commit 4dade98c44dffa235ee2ddd15fa063105902691f
Author: Karl Palsson <ka...@et...>
Date:   Thu Sep 24 09:09:11 2020 +0000

    FreeRTOS: properly read on big endian systems.
    
    Remember, don't cast your pointers between types of different sizes!
    
    While the FreeRTOS handlers attempt to account for different pointer and
    list widths, the types used are always fixed, so this will _remain_
    broken if/when someone targets FreeRTOS on 8/16/64 bit targets. (Note
    that this patch does not _change_ that, it was fixed to 32bit before as
    well)
    
    In the meantime, this properly handles 32bit reads on a mips BE system
    (ath79) as well as remaining fully functional on x86_64.
    
    Change-Id: I677bb7130e25dccb7c1bee8fabaee27371494d00
    Signed-off-by: Karl Palsson <ka...@et...>
    Reviewed-on: http://openocd.zylin.com/5842
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/rtos/FreeRTOS.c b/src/rtos/FreeRTOS.c
index 9a51974c5..d663b6e8f 100644
--- a/src/rtos/FreeRTOS.c
+++ b/src/rtos/FreeRTOS.c
@@ -37,6 +37,11 @@
 
 #define FreeRTOS_STRUCT(int_type, ptr_type, list_prev_offset)
 
+/* FIXME: none of the _width parameters are actually observed properly!
+ * you WILL need to edit more if you actually attempt to target a 8/16/64
+ * bit target!
+ */
+
 struct FreeRTOS_params {
 	const char *target_name;
 	const unsigned char thread_count_width;
@@ -158,7 +163,7 @@ static const struct symbols FreeRTOS_symbol_list[] = {
 static int FreeRTOS_update_threads(struct rtos *rtos)
 {
 	int retval;
-	int tasks_found = 0;
+	unsigned int tasks_found = 0;
 	const struct FreeRTOS_params *param;
 
 	if (rtos->rtos_specific_params == NULL)
@@ -176,12 +181,11 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 		return -2;
 	}
 
-	int thread_list_size = 0;
-	retval = target_read_buffer(rtos->target,
+	uint32_t thread_list_size = 0;
+	retval = target_read_u32(rtos->target,
 			rtos->symbols[FreeRTOS_VAL_uxCurrentNumberOfTasks].address,
-			param->thread_count_width,
-			(uint8_t *)&thread_list_size);
-	LOG_DEBUG("FreeRTOS: Read uxCurrentNumberOfTasks at 0x%" PRIx64 ", value %d\r\n",
+			&thread_list_size);
+	LOG_DEBUG("FreeRTOS: Read uxCurrentNumberOfTasks at 0x%" PRIx64 ", value %" PRIu32 "\r\n",
 										rtos->symbols[FreeRTOS_VAL_uxCurrentNumberOfTasks].address,
 										thread_list_size);
 
@@ -194,14 +198,15 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 	rtos_free_threadlist(rtos);
 
 	/* read the current thread */
-	retval = target_read_buffer(rtos->target,
+	uint32_t pointer_casts_are_bad;
+	retval = target_read_u32(rtos->target,
 			rtos->symbols[FreeRTOS_VAL_pxCurrentTCB].address,
-			param->pointer_width,
-			(uint8_t *)&rtos->current_thread);
+			&pointer_casts_are_bad);
 	if (retval != ERROR_OK) {
 		LOG_ERROR("Error reading current thread in FreeRTOS thread list");
 		return retval;
 	}
+	rtos->current_thread = pointer_casts_are_bad;
 	LOG_DEBUG("FreeRTOS: Read pxCurrentTCB at 0x%" PRIx64 ", value 0x%" PRIx64 "\r\n",
 										rtos->symbols[FreeRTOS_VAL_pxCurrentTCB].address,
 										rtos->current_thread);
@@ -244,20 +249,17 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 		LOG_ERROR("FreeRTOS: uxTopUsedPriority is not defined, consult the OpenOCD manual for a work-around");
 		return ERROR_FAIL;
 	}
-	uint64_t top_used_priority = 0;
-	/* FIXME: endianness error on almost all target_read_buffer(), see also
-	 * other rtoses */
-	retval = target_read_buffer(rtos->target,
+	uint32_t top_used_priority = 0;
+	retval = target_read_u32(rtos->target,
 			rtos->symbols[FreeRTOS_VAL_uxTopUsedPriority].address,
-			param->pointer_width,
-			(uint8_t *)&top_used_priority);
+			&top_used_priority);
 	if (retval != ERROR_OK)
 		return retval;
-	LOG_DEBUG("FreeRTOS: Read uxTopUsedPriority at 0x%" PRIx64 ", value %" PRIu64 "\r\n",
+	LOG_DEBUG("FreeRTOS: Read uxTopUsedPriority at 0x%" PRIx64 ", value %" PRIu32 "\r\n",
 										rtos->symbols[FreeRTOS_VAL_uxTopUsedPriority].address,
 										top_used_priority);
 	if (top_used_priority > FREERTOS_MAX_PRIORITIES) {
-		LOG_ERROR("FreeRTOS top used priority is unreasonably big, not proceeding: %" PRIu64,
+		LOG_ERROR("FreeRTOS top used priority is unreasonably big, not proceeding: %" PRIu32,
 			top_used_priority);
 		return ERROR_FAIL;
 	}
@@ -292,35 +294,33 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 			continue;
 
 		/* Read the number of threads in this list */
-		int64_t list_thread_count = 0;
-		retval = target_read_buffer(rtos->target,
+		uint32_t list_thread_count = 0;
+		retval = target_read_u32(rtos->target,
 				list_of_lists[i],
-				param->thread_count_width,
-				(uint8_t *)&list_thread_count);
+				&list_thread_count);
 		if (retval != ERROR_OK) {
 			LOG_ERROR("Error reading number of threads in FreeRTOS thread list");
 			free(list_of_lists);
 			return retval;
 		}
-		LOG_DEBUG("FreeRTOS: Read thread count for list %u at 0x%" PRIx64 ", value %" PRId64 "\r\n",
+		LOG_DEBUG("FreeRTOS: Read thread count for list %u at 0x%" PRIx64 ", value %" PRIu32 "\r\n",
 										i, list_of_lists[i], list_thread_count);
 
 		if (list_thread_count == 0)
 			continue;
 
 		/* Read the location of first list item */
-		uint64_t prev_list_elem_ptr = -1;
-		uint64_t list_elem_ptr = 0;
-		retval = target_read_buffer(rtos->target,
+		uint32_t prev_list_elem_ptr = -1;
+		uint32_t list_elem_ptr = 0;
+		retval = target_read_u32(rtos->target,
 				list_of_lists[i] + param->list_next_offset,
-				param->pointer_width,
-				(uint8_t *)&list_elem_ptr);
+				&list_elem_ptr);
 		if (retval != ERROR_OK) {
 			LOG_ERROR("Error reading first thread item location in FreeRTOS thread list");
 			free(list_of_lists);
 			return retval;
 		}
-		LOG_DEBUG("FreeRTOS: Read first item for list %u at 0x%" PRIx64 ", value 0x%" PRIx64 "\r\n",
+		LOG_DEBUG("FreeRTOS: Read first item for list %u at 0x%" PRIx64 ", value 0x%" PRIx32 "\r\n",
 										i, list_of_lists[i] + param->list_next_offset, list_elem_ptr);
 
 		while ((list_thread_count > 0) && (list_elem_ptr != 0) &&
@@ -328,16 +328,16 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 				(tasks_found < thread_list_size)) {
 			/* Get the location of the thread structure. */
 			rtos->thread_details[tasks_found].threadid = 0;
-			retval = target_read_buffer(rtos->target,
+			retval = target_read_u32(rtos->target,
 					list_elem_ptr + param->list_elem_content_offset,
-					param->pointer_width,
-					(uint8_t *)&(rtos->thread_details[tasks_found].threadid));
+					&pointer_casts_are_bad);
 			if (retval != ERROR_OK) {
 				LOG_ERROR("Error reading thread list item object in FreeRTOS thread list");
 				free(list_of_lists);
 				return retval;
 			}
-			LOG_DEBUG("FreeRTOS: Read Thread ID at 0x%" PRIx64 ", value 0x%" PRIx64 "\r\n",
+			rtos->thread_details[tasks_found].threadid = pointer_casts_are_bad;
+			LOG_DEBUG("FreeRTOS: Read Thread ID at 0x%" PRIx32 ", value 0x%" PRIx64 "\r\n",
 										list_elem_ptr + param->list_elem_content_offset,
 										rtos->thread_details[tasks_found].threadid);
 
@@ -383,16 +383,15 @@ static int FreeRTOS_update_threads(struct rtos *rtos)
 
 			prev_list_elem_ptr = list_elem_ptr;
 			list_elem_ptr = 0;
-			retval = target_read_buffer(rtos->target,
+			retval = target_read_u32(rtos->target,
 					prev_list_elem_ptr + param->list_elem_next_offset,
-					param->pointer_width,
-					(uint8_t *)&list_elem_ptr);
+					&list_elem_ptr);
 			if (retval != ERROR_OK) {
 				LOG_ERROR("Error reading next thread item location in FreeRTOS thread list");
 				free(list_of_lists);
 				return retval;
 			}
-			LOG_DEBUG("FreeRTOS: Read next thread location at 0x%" PRIx64 ", value 0x%" PRIx64 "\r\n",
+			LOG_DEBUG("FreeRTOS: Read next thread location at 0x%" PRIx32 ", value 0x%" PRIx32 "\r\n",
 										prev_list_elem_ptr + param->list_elem_next_offset,
 										list_elem_ptr);
 		}
@@ -422,14 +421,15 @@ static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
 	param = (const struct FreeRTOS_params *) rtos->rtos_specific_params;
 
 	/* Read the stack pointer */
-	retval = target_read_buffer(rtos->target,
+	uint32_t pointer_casts_are_bad;
+	retval = target_read_u32(rtos->target,
 			thread_id + param->thread_stack_offset,
-			param->pointer_width,
-			(uint8_t *)&stack_ptr);
+			&pointer_casts_are_bad);
 	if (retval != ERROR_OK) {
 		LOG_ERROR("Error reading stack frame from FreeRTOS thread");
 		return retval;
 	}
+	stack_ptr = pointer_casts_are_bad;
 	LOG_DEBUG("FreeRTOS: Read stack pointer at 0x%" PRIx64 ", value 0x%" PRIx64 "\r\n",
 										thread_id + param->thread_stack_offset,
 										stack_ptr);
@@ -459,10 +459,9 @@ static int FreeRTOS_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
 	if (cm4_fpu_enabled == 1) {
 		/* Read the LR to decide between stacking with or without FPU */
 		uint32_t LR_svc = 0;
-		retval = target_read_buffer(rtos->target,
+		retval = target_read_u32(rtos->target,
 				stack_ptr + 0x20,
-				param->pointer_width,
-				(uint8_t *)&LR_svc);
+				&LR_svc);
 		if (retval != ERROR_OK) {
 			LOG_OUTPUT("Error reading stack frame from FreeRTOS thread\r\n");
 			return retval;

commit cbbec2dce57c6ded1ef495388f93fa1d45977daf
Author: Kevin Burke <ke...@os...>
Date:   Fri Apr 3 20:47:50 2020 -0400

    ARM|Driver: Add DPI Driver for emulation
    
    This driver provides support for Cadence JTAG BFM
    
    The "jtag_dpi" driver implements a JTAG driver acting as a client for the
    SystemVerilog Direct Programming Interface (DPI) for JTAG devices.
    DPI allows OpenOCD to connect to the JTAG interface of a hardware model
    written in SystemVerilog, for example, on an emulation model of
    target hardware.
    
    Tested on Ampere emulation with Altra and Altra Max models
    
    Change-Id: Iaef8ba5cc1398ee2c888f39a606e8cb592484625
    Signed-off-by: Kevin Burke <ke...@os...>
    Signed-off-by: Daniel Goehring <dgo...@os...>
    Reviewed-on: http://openocd.zylin.com/5573
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/configure.ac b/configure.ac
index fc6734cf8..569816637 100644
--- a/configure.ac
+++ b/configure.ac
@@ -267,6 +267,10 @@ AC_ARG_ENABLE([jtag_vpi],
   AS_HELP_STRING([--enable-jtag_vpi], [Enable building support for JTAG VPI]),
   [build_jtag_vpi=$enableval], [build_jtag_vpi=no])
 
+AC_ARG_ENABLE([jtag_dpi],
+  AS_HELP_STRING([--enable-jtag_dpi], [Enable building support for JTAG DPI]),
+  [build_jtag_dpi=$enableval], [build_jtag_dpi=no])
+
 AC_ARG_ENABLE([amtjtagaccel],
   AS_HELP_STRING([--enable-amtjtagaccel], [Enable building the Amontec JTAG-Accelerator driver]),
   [build_amtjtagaccel=$enableval], [build_amtjtagaccel=no])
@@ -569,6 +573,13 @@ AS_IF([test "x$build_jtag_vpi" = "xyes"], [
   AC_DEFINE([BUILD_JTAG_VPI], [0], [0 if you don't want JTAG VPI.])
 ])
 
+AS_IF([test "x$build_jtag_dpi" = "xyes"], [
+  AC_DEFINE([BUILD_JTAG_DPI], [1], [1 if you want JTAG DPI.])
+], [
+  AC_DEFINE([BUILD_JTAG_DPI], [0], [0 if you don't want JTAG DPI.])
+])
+
+
 AS_IF([test "x$build_amtjtagaccel" = "xyes"], [
   AC_DEFINE([BUILD_AMTJTAGACCEL], [1], [1 if you want the Amontec JTAG-Accelerator driver.])
 ], [
@@ -746,6 +757,7 @@ AM_CONDITIONAL([BCM2835GPIO], [test "x$build_bcm2835gpio" = "xyes"])
 AM_CONDITIONAL([IMX_GPIO], [test "x$build_imx_gpio" = "xyes"])
 AM_CONDITIONAL([BITBANG], [test "x$build_bitbang" = "xyes"])
 AM_CONDITIONAL([JTAG_VPI], [test "x$build_jtag_vpi" = "xyes" -o "x$build_jtag_vpi" = "xyes"])
+AM_CONDITIONAL([JTAG_DPI], [test "x$build_jtag_dpi" = "xyes" -o "x$build_jtag_dpi" = "xyes"])
 AM_CONDITIONAL([USB_BLASTER_DRIVER], [test "x$enable_usb_blaster" != "xno" -o "x$enable_usb_blaster_2" != "xno"])
 AM_CONDITIONAL([AMTJTAGACCEL], [test "x$build_amtjtagaccel" = "xyes"])
 AM_CONDITIONAL([GW16012], [test "x$build_gw16012" = "xyes"])
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 317f188d2..3506ccab1 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -615,6 +615,12 @@ produced, PDF schematics are easily found and it is easy to make.
 @* A JTAG driver acting as a client for the JTAG VPI server interface.
 @* Link: @url{http://github.com/fjullien/jtag_vpi}
 
+@item @b{jtag_dpi}
+@* A JTAG driver acting as a client for the SystemVerilog Direct Programming
+Interface (DPI) for JTAG devices. DPI allows OpenOCD to connect to the JTAG
+interface of a hardware model written in SystemVerilog, for example, on an
+emulation model of target hardware.
+
 @item @b{xlnx_pcie_xvc}
 @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
 
@@ -3235,6 +3241,22 @@ This value is only used with the standard variant.
 @end deffn
 @end deffn
 
+
+@deffn {Interface Driver} {jtag_dpi}
+SystemVerilog Direct Programming Interface (DPI) compatible driver for
+JTAG devices in emulation. The driver acts as a client for the SystemVerilog
+DPI server interface.
+
+@deffn {Config Command} {jtag_dpi_set_port} port
+Specifies the TCP/IP port number of the SystemVerilog DPI server interface.
+@end deffn
+
+@deffn {Config Command} {jtag_dpi_set_address} address
+Specifies the TCP/IP address of the SystemVerilog DPI server interface.
+@end deffn
+@end deffn
+
+
 @section Transport Configuration
 @cindex Transport
 As noted earlier, depending on the version of OpenOCD you use,
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index c860833b3..e8d20ccf8 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -82,6 +82,9 @@ endif
 if JTAG_VPI
 DRIVERFILES += %D%/jtag_vpi.c
 endif
+if JTAG_DPI
+DRIVERFILES += %D%/jtag_dpi.c
+endif
 if USB_BLASTER_DRIVER
 %C%_libocdjtagdrivers_la_LIBADD += %D%/usb_blaster/libocdusbblaster.la
 include %D%/usb_blaster/Makefile.am
diff --git a/src/jtag/drivers/jtag_dpi.c b/src/jtag/drivers/jtag_dpi.c
new file mode 100644
index 000000000..575c6bce2
--- /dev/null
+++ b/src/jtag/drivers/jtag_dpi.c
@@ -0,0 +1,407 @@
+/*
+ * JTAG to DPI driver
+ *
+ * Copyright (C) 2013 Franck Jullien, <ele...@gm...>
+ *
+ * Copyright (C) 2019-2020, Ampere Computing LLC
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <jtag/interface.h>
+#ifdef HAVE_ARPA_INET_H
+#include <arpa/inet.h>
+#endif
+
+#ifndef _WIN32
+#include <netinet/tcp.h>
+#endif
+
+#define SERVER_ADDRESS	"127.0.0.1"
+#define SERVER_PORT	5555
+
+static uint16_t server_port = SERVER_PORT;
+static char *server_address;
+
+static int sockfd;
+static struct sockaddr_in serv_addr;
+
+static uint8_t *last_ir_buf;
+static int last_ir_num_bits;
+
+static int write_sock(char *buf, size_t len)
+{
+	if (buf == NULL) {
+		LOG_ERROR("%s: NULL 'buf' argument, file %s, line %d",
+			__func__, __FILE__, __LINE__);
+		return ERROR_FAIL;
+	}
+	if (write(sockfd, buf, len) != (ssize_t)len) {
+		LOG_ERROR("%s: %s, file %s, line %d", __func__,
+			strerror(errno), __FILE__, __LINE__);
+		return ERROR_FAIL;
+	}
+	return ERROR_OK;
+}
+
+static int read_sock(char *buf, size_t len)
+{
+	if (buf == NULL) {
+		LOG_ERROR("%s: NULL 'buf' argument, file %s, line %d",
+			__func__, __FILE__, __LINE__);
+		return ERROR_FAIL;
+	}
+	if (read(sockfd, buf, len) != (ssize_t)len) {
+		LOG_ERROR("%s: %s, file %s, line %d", __func__,
+			strerror(errno), __FILE__, __LINE__);
+		return ERROR_FAIL;
+	}
+	return ERROR_OK;
+}
+
+/**
+ * jtag_dpi_reset - ask to reset the JTAG device
+ * @trst: 1 if TRST is to be asserted
+ * @srst: 1 if SRST is to be asserted
+ */
+static int jtag_dpi_reset(int trst, int srst)
+{
+	char *buf = "reset\n";
+	int ret = ERROR_OK;
+
+	LOG_DEBUG_IO("JTAG DRIVER DEBUG: reset trst: %i srst %i", trst, srst);
+
+	if (trst == 1) {
+		/* reset the JTAG TAP controller */
+		ret = write_sock(buf, strlen(buf));
+		if (ret != ERROR_OK) {
+			LOG_ERROR("write_sock() fail, file %s, line %d",
+				__FILE__, __LINE__);
+		}
+	}
+
+	if (srst == 1) {
+		/* System target reset not supported */
+		LOG_ERROR("DPI SRST not supported");
+		ret = ERROR_FAIL;
+	}
+
+	return ret;
+}
+
+/**
+ * jtag_dpi_scan - launches a DR-scan or IR-scan
+ * @cmd: the command to launch
+ *
+ * Launch a JTAG IR-scan or DR-scan
+ *
+ * Returns ERROR_OK if OK, ERROR_xxx if a read/write error occured.
+ */
+static int jtag_dpi_scan(struct scan_command *cmd)
+{
+	char buf[20];
+	uint8_t *data_buf;
+	int num_bits, bytes;
+	int ret = ERROR_OK;
+
+	num_bits = jtag_build_buffer(cmd, &data_buf);
+	if (data_buf == NULL) {
+		LOG_ERROR("jtag_build_buffer call failed, data_buf == NULL, "
+			"file %s, line %d", __FILE__, __LINE__);
+		return ERROR_FAIL;
+	}
+
+	bytes = DIV_ROUND_UP(num_bits, 8);
+	if (cmd->ir_scan) {
+		free(last_ir_buf);
+		last_ir_buf = (uint8_t *)malloc(bytes * sizeof(uint8_t));
+		if (last_ir_buf == NULL) {
+			LOG_ERROR("%s: malloc fail, file %s, line %d",
+				__func__, __FILE__, __LINE__);
+			ret = ERROR_FAIL;
+			goto out;
+		}
+		memcpy(last_ir_buf, data_buf, bytes);
+		last_ir_num_bits = num_bits;
+	}
+	snprintf(buf, sizeof(buf), "%s %d\n", cmd->ir_scan ? "ib" : "db", num_bits);
+	ret = write_sock(buf, strlen(buf));
+	if (ret != ERROR_OK) {
+		LOG_ERROR("write_sock() fail, file %s, line %d",
+			__FILE__, __LINE__);
+		goto out;
+	}
+	ret = write_sock((char *)data_buf, bytes);
+	if (ret != ERROR_OK) {
+		LOG_ERROR("write_sock() fail, file %s, line %d",
+			__FILE__, __LINE__);
+		goto out;
+	}
+	ret = read_sock((char *)data_buf, bytes);
+	if (ret != ERROR_OK) {
+		LOG_ERROR("read_sock() fail, file %s, line %d",
+			__FILE__, __LINE__);
+		goto out;
+	}
+
+	ret = jtag_read_buffer(data_buf, cmd);
+	if (ret != ERROR_OK) {
+		LOG_ERROR("jtag_read_buffer() fail, file %s, line %d",
+			__FILE__, __LINE__);
+		goto out;
+	}
+
+out:
+	free(data_buf);
+	return ret;
+}
+
+static int jtag_dpi_runtest(int cycles)
+{
+	char buf[20];
+	uint8_t *data_buf = last_ir_buf, *read_scan;
+	int num_bits = last_ir_num_bits, bytes;
+	int ret = ERROR_OK;
+
+	if (data_buf == NULL) {
+		LOG_ERROR("%s: NULL 'data_buf' argument, file %s, line %d",
+			__func__, __FILE__, __LINE__);
+		return ERROR_FAIL;
+	}
+	if (num_bits <= 0) {
+		LOG_ERROR("%s: 'num_bits' invalid value, file %s, line %d",
+			__func__, __FILE__, __LINE__);
+		return ERROR_FAIL;
+	}
+
+	bytes = DIV_ROUND_UP(num_bits, 8);
+	read_scan = (uint8_t *)malloc(bytes * sizeof(uint8_t));
+	if (read_scan == NULL) {
+		LOG_ERROR("%s: malloc fail, file %s, line %d",
+			__func__, __FILE__, __LINE__);
+		return ERROR_FAIL;
+	}
+	snprintf(buf, sizeof(buf), "ib %d\n", num_bits);
+	while (cycles > 0) {
+		ret = write_sock(buf, strlen(buf));
+		if (ret != ERROR_OK) {
+			LOG_ERROR("write_sock() fail, file %s, line %d",
+				__FILE__, __LINE__);
+			goto out;
+		}
+		ret = write_sock((char *)data_buf, bytes);
+		if (ret != ERROR_OK) {
+			LOG_ERROR("write_sock() fail, file %s, line %d",
+				__FILE__, __LINE__);
+			goto out;
+		}
+		ret = read_sock((char *)read_scan, bytes);
+		if (ret != ERROR_OK) {
+			LOG_ERROR("read_sock() fail, file %s, line %d",
+				__FILE__, __LINE__);
+			goto out;
+		}
+
+		cycles -= num_bits + 6;
+	}
+
+out:
+	free(read_scan);
+	return ret;
+}
+
+static int jtag_dpi_stableclocks(int cycles)
+{
+	return jtag_dpi_runtest(cycles);
+}
+
+static int jtag_dpi_execute_queue(void)
+{
+	struct jtag_command *cmd;
+	int ret = ERROR_OK;
+
+	for (cmd = jtag_command_queue; ret == ERROR_OK && cmd != NULL;
+	     cmd = cmd->next) {
+		switch (cmd->type) {
+		case JTAG_RUNTEST:
+			ret = jtag_dpi_runtest(cmd->cmd.runtest->num_cycles);
+			break;
+		case JTAG_STABLECLOCKS:
+			ret = jtag_dpi_stableclocks(cmd->cmd.stableclocks->num_cycles);
+			break;
+		case JTAG_TLR_RESET:
+			/* Enter Test-Logic-Reset state by asserting TRST */
+			if (cmd->cmd.statemove->end_state == TAP_RESET)
+				jtag_dpi_reset(1, 0);
+			break;
+		case JTAG_PATHMOVE:
+			/* unsupported */
+			break;
+		case JTAG_TMS:
+			/* unsupported */
+			break;
+		case JTAG_SLEEP:
+			jtag_sleep(cmd->cmd.sleep->us);
+			break;
+		case JTAG_SCAN:
+			ret = jtag_dpi_scan(cmd->cmd.scan);
+			break;
+		default:
+			LOG_ERROR("BUG: unknown JTAG command type 0x%X",
+				  cmd->type);
+			ret = ERROR_FAIL;
+			break;
+		}
+	}
+
+	return ret;
+}
+
+static int jtag_dpi_init(void)
+{
+	sockfd = socket(AF_INET, SOCK_STREAM, 0);
+	if (sockfd < 0) {
+		LOG_ERROR("socket: %s, function %s, file %s, line %d",
+			strerror(errno), __func__, __FILE__, __LINE__);
+		return ERROR_FAIL;
+	}
+
+	memset(&serv_addr, 0, sizeof(serv_addr));
+
+	serv_addr.sin_family = AF_INET;
+	serv_addr.sin_port = htons(server_port);
+
+	if (server_address == NULL) {
+		server_address = strdup(SERVER_ADDRESS);
+		if (server_address == NULL) {
+			LOG_ERROR("%s: strdup fail, file %s, line %d",
+				__func__, __FILE__, __LINE__);
+			return ERROR_FAIL;
+		}
+	}
+
+	serv_addr.sin_addr.s_addr = inet_addr(server_address);
+
+	if (serv_addr.sin_addr.s_addr == INADDR_NONE) {
+		LOG_ERROR("inet_addr error occured");
+		return ERROR_FAIL;
+	}
+
+	if (connect(sockfd, (struct sockaddr *)&serv_addr, sizeof(serv_addr)) < 0) {
+		close(sockfd);
+		LOG_ERROR("Can't connect to %s : %" PRIu16, server_address, server_port);
+		return ERROR_FAIL;
+	}
+	if (serv_addr.sin_addr.s_addr == htonl(INADDR_LOOPBACK)) {
+		/* This increases performance dramatically for local
+		* connections, which is the most likely arrangement
+		* for a DPI connection. */
+		int flag = 1;
+		setsockopt(sockfd, IPPROTO_TCP, TCP_NODELAY, (char *)&flag, sizeof(int));
+	}
+
+	LOG_INFO("Connection to %s : %" PRIu16 " succeed", server_address, server_port);
+
+	return ERROR_OK;
+}
+
+static int jtag_dpi_quit(void)
+{
+	free(server_address);
+	server_address = NULL;
+
+	return close(sockfd);
+}
+
+COMMAND_HANDLER(jtag_dpi_set_port)
+{
+	if (CMD_ARGC > 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	else if (CMD_ARGC == 0)
+		LOG_INFO("Using server port %" PRIu16, server_port);
+	else {
+		COMMAND_PARSE_NUMBER(u16, CMD_ARGV[0], server_port);
+		LOG_INFO("Set server port to %" PRIu16, server_port);
+	}
+
+	return ERROR_OK;
+}
+
+COMMAND_HANDLER(jtag_dpi_set_address)
+{
+	if (CMD_ARGC > 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+	else if (CMD_ARGC == 0) {
+		if (server_address == NULL) {
+			server_address = strdup(SERVER_ADDRESS);
+			if (server_address == NULL) {
+				LOG_ERROR("%s: strdup fail, file %s, line %d",
+					__func__, __FILE__, __LINE__);
+				return ERROR_FAIL;
+			}
+		}
+		LOG_INFO("Using server address %s", server_address);
+	} else {
+		free(server_address);
+		server_address = strdup(CMD_ARGV[0]);
+		if (server_address == NULL) {
+			LOG_ERROR("%s: strdup fail, file %s, line %d",
+				__func__, __FILE__, __LINE__);
+			return ERROR_FAIL;
+		}
+		LOG_INFO("Set server address to %s", server_address);
+	}
+
+	return ERROR_OK;
+}
+
+static const struct command_registration jtag_dpi_command_handlers[] = {
+	{
+		.name = "jtag_dpi_set_port",
+		.handler = &jtag_dpi_set_port,
+		.mode = COMMAND_CONFIG,
+		.help = "set the port of the DPI server",
+		.usage = "[port]",
+	},
+	{
+		.name = "jtag_dpi_set_address",
+		.handler = &jtag_dpi_set_address,
+		.mode = COMMAND_CONFIG,
+		.help = "set the address of the DPI server",
+		.usage = "[address]",
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
+static struct jtag_interface jtag_dpi_interface = {
+	.supported = DEBUG_CAP_TMS_SEQ,
+	.execute_queue = jtag_dpi_execute_queue,
+};
+
+struct adapter_driver jtag_dpi_adapter_driver = {
+	.name = "jtag_dpi",
+	.transports = jtag_only,
+	.commands = jtag_dpi_command_handlers,
+	.init = jtag_dpi_init,
+	.quit = jtag_dpi_quit,
+	.reset = jtag_dpi_reset,
+	.jtag_ops = &jtag_dpi_interface,
+};
diff --git a/src/jtag/interfaces.c b/src/jtag/interfaces.c
index 45e30c9b0..2fa53be2b 100644
--- a/src/jtag/interfaces.c
+++ b/src/jtag/interfaces.c
@@ -12,6 +12,8 @@
  *   Copyright (C) 2009 Zachary T Welch                                    *
  *   zw...@su...                                                  *
  *                                                                         *
+ *   Copyright (C) 2020, Ampere Computing LLC                              *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -60,6 +62,9 @@ extern struct adapter_driver usb_blaster_adapter_driver;
 #if BUILD_JTAG_VPI == 1
 extern struct adapter_driver jtag_vpi_adapter_driver;
 #endif
+#if BUILD_JTAG_DPI == 1
+extern struct adapter_driver jtag_dpi_adapter_driver;
+#endif
 #if BUILD_FT232R == 1
 extern struct adapter_driver ft232r_adapter_driver;
 #endif
@@ -177,6 +182,9 @@ struct adapter_driver *adapter_drivers[] = {
 #if BUILD_JTAG_VPI == 1
 		&jtag_vpi_adapter_driver,
 #endif
+#if BUILD_JTAG_DPI == 1
+		&jtag_dpi_adapter_driver,
+#endif
 #if BUILD_FT232R == 1
 		&ft232r_adapter_driver,
 #endif
diff --git a/tcl/interface/jtag_dpi.cfg b/tcl/interface/jtag_dpi.cfg
new file mode 100644
index 000000000..e43386d58
--- /dev/null
+++ b/tcl/interface/jtag_dpi.cfg
@@ -0,0 +1,38 @@
+#
+# Provide support for the Cadence JTAG BFM
+#
+# Copyright (c) 2020, Ampere Computing LLC
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program;
+#
+#
+
+adapter driver jtag_dpi
+
+# Set the DPI JTAG server port
+if { [info exists DPI_PORT] } {
+   set _DPI_PORT $DPI_PORT
+} else {
+   set _DPI_PORT 5555
+}
+
+# Set the DPI JTAG server address
+if { [info exists DPI_ADDRESS] } {
+   set _DPI_ADDRESS $DPI_ADDRESS
+} else {
+   set _DPI_ADDRESS "127.0.0.1"
+}
+
+jtag_dpi_set_port $_DPI_PORT
+jtag_dpi_set_address $_DPI_ADDRESS

commit 87b95ab21292166eed23693616c9ee21a2c5a0c0
Author: Daniel Trnka <dan...@gm...>
Date:   Mon Aug 17 17:51:43 2020 +0200

    target/cortex_m.c: vector_catch command checks if a target is examined
    
    If a target is not examined, command vector_catch crashes while accessing
    the debug_ap NULL pointer.
    
    maskisr and reset_config commands don't require this check.
    
    Change-Id: I949b6f6e8b983327dd98fbe403735141f8f0b5d6
    Signed-off-by: Daniel Trnka <dan...@gm...>
    Reviewed-on: http://openocd.zylin.com/5813
    Tested-by: jenkins
    Reviewed-by: Tarek BOCHKATI <tar...@gm...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index e52332dd6..55664a79a 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2502,6 +2502,11 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
 	if (retval != ERROR_OK)
 		return retval;
 
+	if (!target_was_examined(target)) {
+		LOG_ERROR("Target not examined yet");
+		return ERROR_FAIL;
+	}
+
 	retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &demcr);
 	if (retval != ERROR_OK)
 		return retval;

-----------------------------------------------------------------------

Summary of changes:
 configure.ac                 |  12 ++
 doc/openocd.texi             |  22 +++
 src/jtag/drivers/Makefile.am |   3 +
 src/jtag/drivers/jtag_dpi.c  | 407 +++++++++++++++++++++++++++++++++++++++++++
 src/jtag/interfaces.c        |   8 +
 src/rtos/FreeRTOS.c          |  83 +++++----
 src/target/cortex_m.c        |   5 +
 tcl/interface/jtag_dpi.cfg   |  38 ++++
 8 files changed, 536 insertions(+), 42 deletions(-)
 create mode 100644 src/jtag/drivers/jtag_dpi.c
 create mode 100644 tcl/interface/jtag_dpi.cfg


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- Log -----------------------------------------------------------------
commit d7d70c2719e6fe94dc9ca15aeb81cf142d597cdc
Author: Mete Balci <met...@gm...>
Date:   Sat Mar 30 12:27:57 2019 +0100

    target/aarch64: a64 disassembler
    
    Add A64 (AArch64) Disassembler using Capstone framework.
    
    Change-Id: Ia92b57001843b11a818af940a468b131e42a03fd
    Signed-off-by: Mete Balci <met...@gm...>
    [Antonio Borneo: Rebased on current HEAD]
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5004
    Tested-by: jenkins

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 8c99228c3..317f188d2 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -9349,6 +9349,12 @@ target code relies on. In a configuration file, the command would typically be c
 However, normally it is not necessary to use the command at all.
 @end deffn
 
+@deffn Command {aarch64 disassemble} address [count]
+@cindex disassemble
+Disassembles @var{count} instructions starting at @var{address}.
+If @var{count} is not specified, a single instruction is disassembled.
+@end deffn
+
 @deffn Command {aarch64 smp} [on|off]
 Display, enable or disable SMP handling mode. The state of SMP handling influences the way targets in an SMP group
 are handled by the run control. With SMP handling enabled, issuing halt or resume to one core will trigger
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 724f38c24..19ba7714e 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -89,6 +89,7 @@ ARMV8_SRC = \
 	%D%/armv8_dpm.c \
 	%D%/armv8_opcodes.c \
 	%D%/aarch64.c \
+	%D%/a64_disassembler.c \
 	%D%/armv8.c \
 	%D%/armv8_cache.c
 
@@ -176,6 +177,7 @@ ARC_SRC = \
 	%D%/armv7a_cache_l2x.h \
 	%D%/armv7a_mmu.h \
 	%D%/arm_disassembler.h \
+	%D%/a64_disassembler.h \
 	%D%/arm_opcodes.h \
 	%D%/arm_simulator.h \
 	%D%/arm_semihosting.h \
diff --git a/src/target/a64_disassembler.c b/src/target/a64_disassembler.c
new file mode 100644
index 000000000..bd78129dd
--- /dev/null
+++ b/src/target/a64_disassembler.c
@@ -0,0 +1,145 @@
+/***************************************************************************
+ *   Copyright (C) 2019 by Mete Balci                                      *
+ *   met...@gm...                                                   *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <helper/log.h>
+#include "target.h"
+#include "a64_disassembler.h"
+
+#if HAVE_CAPSTONE
+
+#include <capstone/capstone.h>
+
+static void print_opcode(struct command_invocation *cmd, const cs_insn *insn)
+{
+	uint32_t opcode = 0;
+
+	memcpy(&opcode, insn->bytes, insn->size);
+
+	if (insn->size == 4) {
+
+		uint16_t opcode_high = opcode >> 16;
+
+		opcode = opcode & 0xffff;
+
+		command_print(cmd,
+				"0x%08" PRIx64"  %04x %04x\t%s\t%s",
+				insn->address,
+				opcode,
+				opcode_high,
+				insn->mnemonic,
+				insn->op_str);
+
+	} else {
+
+		command_print(
+				cmd,
+				"0x%08" PRIx64"  %04x\t%s\t%s",
+				insn->address,
+				opcode,
+				insn->mnemonic,
+				insn->op_str);
+
+	}
+}
+
+int a64_disassemble(struct command_invocation *cmd, struct target *target, target_addr_t address, size_t count)
+{
+	int ret;
+	int csret;
+	csh handle;
+
+	csret = cs_open(CS_ARCH_ARM64, CS_MODE_LITTLE_ENDIAN, &handle);
+
+	if (csret != CS_ERR_OK) {
+
+		LOG_ERROR("cs_open() failed: %s", cs_strerror(csret));
+		return ERROR_FAIL;
+
+	}
+
+	csret = cs_option(handle, CS_OPT_SKIPDATA, CS_OPT_ON);
+
+	if (csret != CS_ERR_OK) {
+
+		LOG_ERROR("cs_option() failed: %s", cs_strerror(csret));
+		cs_close(&handle);
+		return ERROR_FAIL;
+
+	}
+
+	cs_insn *insn = cs_malloc(handle);
+
+	if (csret != CS_ERR_OK) {
+
+		LOG_ERROR("cs_malloc() failed: %s", cs_strerror(csret));
+		cs_close(&handle);
+		return ERROR_FAIL;
+
+	}
+
+	while (count > 0) {
+
+		uint8_t buffer[4];
+
+		ret = target_read_buffer(target, address, sizeof(buffer), buffer);
+
+		if (ret != ERROR_OK) {
+			cs_free(insn, 1);
+			cs_close(&handle);
+			return ret;
+		}
+
+		size_t size = sizeof(buffer);
+		const uint8_t *tmp = buffer;
+
+		ret = cs_disasm_iter(handle, &tmp, &size, &address, insn);
+
+		if (!ret) {
+
+			LOG_ERROR("cs_disasm_iter() failed: %s", cs_strerror(cs_errno(handle)));
+			cs_free(insn, 1);
+			cs_close(&handle);
+			return ERROR_FAIL;
+
+		}
+
+		print_opcode(cmd, insn);
+		count--;
+
+	}
+
+	cs_free(insn, 1);
+	cs_close(&handle);
+
+	return ERROR_OK;
+}
+
+#else
+
+int a64_disassemble(struct command_invocation *cmd, struct target *target, target_addr_t address, size_t count)
+{
+	command_print(cmd, "capstone disassembly framework required");
+
+	return ERROR_FAIL;
+}
+
+#endif
diff --git a/src/target/a64_disassembler.h b/src/target/a64_disassembler.h
new file mode 100644
index 000000000..5c58bbfe5
--- /dev/null
+++ b/src/target/a64_disassembler.h
@@ -0,0 +1,30 @@
+/***************************************************************************
+ *   Copyright (C) 2019 by Mete Balci                                      *
+ *   met...@gm...                                                   *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
+ ***************************************************************************/
+
+#ifndef OPENOCD_TARGET_AARCH64_DISASSEMBLER_H
+#define OPENOCD_TARGET_AARCH64_DISASSEMBLER_H
+
+#include "target.h"
+
+int a64_disassemble(
+		struct command_invocation *cmd,
+		struct target *target,
+		target_addr_t address,
+		size_t count);
+
+#endif /* OPENOCD_TARGET_AARCH64_DISASSEMBLER_H */
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 4febc8c96..dee16d116 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -23,6 +23,7 @@
 
 #include "breakpoints.h"
 #include "aarch64.h"
+#include "a64_disassembler.h"
 #include "register.h"
 #include "target_request.h"
 #include "target_type.h"
@@ -2566,7 +2567,6 @@ COMMAND_HANDLER(aarch64_handle_cache_info_command)
 			&armv8->armv8_mmu.armv8_cache);
 }
 
-
 COMMAND_HANDLER(aarch64_handle_dbginit_command)
 {
 	struct target *target = get_current_target(CMD_CTX);
@@ -2578,6 +2578,39 @@ COMMAND_HANDLER(aarch64_handle_dbginit_command)
 	return aarch64_init_debug_access(target);
 }
 
+COMMAND_HANDLER(aarch64_handle_disassemble_command)
+{
+	struct target *target = get_current_target(CMD_CTX);
+
+	if (target == NULL) {
+		LOG_ERROR("No target selected");
+		return ERROR_FAIL;
+	}
+
+	struct aarch64_common *aarch64 = target_to_aarch64(target);
+
+	if (aarch64->common_magic != AARCH64_COMMON_MAGIC) {
+		command_print(CMD, "current target isn't an AArch64");
+		return ERROR_FAIL;
+	}
+
+	int count = 1;
+	target_addr_t address;
+
+	switch (CMD_ARGC) {
+		case 2:
+			COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
+		/* FALL THROUGH */
+		case 1:
+			COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
+			break;
+		default:
+			return ERROR_COMMAND_SYNTAX_ERROR;
+	}
+
+	return a64_disassemble(CMD, target, address, count);
+}
+
 COMMAND_HANDLER(aarch64_mask_interrupts_command)
 {
 	struct target *target = get_current_target(CMD_CTX);
@@ -2758,6 +2791,13 @@ static const struct command_registration aarch64_exec_command_handlers[] = {
 		.help = "Initialize core debug",
 		.usage = "",
 	},
+	{
+		.name = "disassemble",
+		.handler = aarch64_handle_disassemble_command,
+		.mode = COMMAND_EXEC,
+		.help = "Disassemble instructions",
+		.usage = "address [count]",
+	},
 	{
 		.name = "maskisr",
 		.handler = aarch64_mask_interrupts_command,

commit a31e579e879cfb3d67583780c4ebb6f1015ed5a5
Author: Ulrich-Lorenz Schlüter <aud...@gm...>
Date:   Tue Mar 31 10:05:47 2020 +0200

    tcl: board/dp_busblaster_v4 Busblaster v4.1a by Seed Studio added
    
    Change-Id: I53141d7f6f022f9dee641858f5fb0e0b70c049f8
    Signed-off-by: Paul Fertser <fer...@gm...>
    Signed-off-by: Ulrich-Lorenz Schlüter <aud...@gm...>
    Reviewed-on: http://openocd.zylin.com/5549
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/board/dp_busblaster_v4.cfg b/tcl/board/dp_busblaster_v4.cfg
new file mode 100644
index 000000000..066b54f3d
--- /dev/null
+++ b/tcl/board/dp_busblaster_v4.cfg
@@ -0,0 +1,19 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Dangerous Prototypes - Bus Blaster
+#
+# http://dangerousprototypes.com/docs/Bus_Blaster
+#
+# The Bus Blaster has a configurable buffer between the FTDI FT2232H
+# and the JTAG header which allows it to emulate various debugger
+# types. This config works with KT-Link compatible implementation from
+# https://raw.githubusercontent.com/dergraaf/busblaster_v4/master/ktlink/ktlink.svf
+#
+# To reprogram the on-board CPLD do:
+# openocd -f board/dp_busblaster_v4.cfg -c "adapter_khz 1000; init; svf <path_to_svf>; shutdown"
+#
+
+source [find interface/ftdi/dp_busblaster.cfg]
+ftdi_channel 1
+
+jtag newtap xc2c64a tap -expected-id 0x06e5c093 -irlen 8

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi                                 |   6 +
 src/target/Makefile.am                           |   2 +
 src/target/a64_disassembler.c                    | 145 +++++++++++++++++++++++
 src/{jtag/driver.h => target/a64_disassembler.h} |  18 +--
 src/target/aarch64.c                             |  42 ++++++-
 tcl/board/dp_busblaster_v4.cfg                   |  19 +++
 6 files changed, 224 insertions(+), 8 deletions(-)
 create mode 100644 src/target/a64_disassembler.c
 copy src/{jtag/driver.h => target/a64_disassembler.h} (74%)
 create mode 100644 tcl/board/dp_busblaster_v4.cfg


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- Log -----------------------------------------------------------------
commit 1593e4a47e7187a84be44c4363b9a2e343db4351
Author: Jan Kowalewski <jko...@an...>
Date:   Thu Jul 9 12:34:22 2020 +0200

    tcl/board: Add QuickLogic QuickFeather configuration
    
    Add configuration for QuickLogic QuickFeather development kit.
    
    Change-Id: I39120714bf0bcafa86e0071c38da84a7d9f12a0d
    Signed-off-by: Jan Kowalewski <jko...@an...>
    Reviewed-on: http://openocd.zylin.com/5803
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/board/quicklogic_quickfeather.cfg b/tcl/board/quicklogic_quickfeather.cfg
new file mode 100644
index 000000000..b522eff7e
--- /dev/null
+++ b/tcl/board/quicklogic_quickfeather.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# QuickLogic EOS S3 QuickFeather
+# https://www.quicklogic.com/products/eos-s3/quickfeather-development-kit/
+
+source [find target/eos_s3.cfg]
+
+reset_config srst_only
+
+transport select swd

commit c3166b43e415305e864c2ee3c4e2ed8c9cd37076
Author: Jan Kowalewski <jko...@an...>
Date:   Fri Jul 3 18:19:01 2020 +0200

    tcl/target: Add QuickLogic EOS S3 MCU configuration
    
    Add configuration for QuickLogic EOS S3 MCU target.
    
    Change-Id: I375057ff387a826e632f194843dbd92148b0c5dd
    Signed-off-by: Jan Kowalewski <jko...@an...>
    Reviewed-on: http://openocd.zylin.com/5802
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/eos_s3.cfg b/tcl/target/eos_s3.cfg
new file mode 100644
index 000000000..f6016fb30
--- /dev/null
+++ b/tcl/target/eos_s3.cfg
@@ -0,0 +1,44 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# QuickLogic EOS S3
+# https://www.quicklogic.com/products/soc/eos-s3-microcontroller/
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME eos_s3
+}
+
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x80000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x2ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -irmask 0xf -expected-id _CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+# For now we use SRAM only for software upload
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+adapter speed 4000
+
+if {![using_hla]} {
+   # if srst is not fitted use SYSRESETREQ to
+   # perform a soft reset
+   cortex_m reset_config sysresetreq
+}

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/quicklogic_quickfeather.cfg |  9 +++++++++
 tcl/target/{efm32.cfg => eos_s3.cfg}  | 25 +++++++++----------------
 2 files changed, 18 insertions(+), 16 deletions(-)
 create mode 100644 tcl/board/quicklogic_quickfeather.cfg
 copy tcl/target/{efm32.cfg => eos_s3.cfg} (55%)


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      from  67008e1bea2dd1a89d77802b892d3390e8a55455 (commit)

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- Log -----------------------------------------------------------------
commit 051e80812b1b3bb4deabef272c12bb95f10748da
Author: Adrian Negreanu <adr...@nx...>
Date:   Mon Sep 7 22:36:10 2020 +0300

    drivers/jlink: fix calculate_swo_prescaler formula
    
    a) TPIU_ACPR is defined as:
            SWO_baudrate = TRACECLKIN/(TPIU_ACPR +1)
    
    b) TPIU_ACPR is set by armv7m_trace_tpiu_config()
            target_write_u32(target, TPIU_ACPR, Prescaler-1), so
            TPIU_ACPR = Prescaler-1
    
    Replacing TPIU_ACPR in a), we get:
            SWO_baudrate = TRACECLKIN/Prescaler, so
    
    c)      Prescaler = TRACECLKIN/SWO_baudrate
    
    The Prescaler calculated by calculate_swo_prescaler() is greater by 1:
            Prescaler = TRACECLKIN/SWO_baudrate + 1
    
    The second problem is that even in situations when
    an exact baudrate match is possible,
    the resulting TRACECLKIN/Prescaler already has a 3% deviation.
    
    For example, TRACECLKIN=88000000, SWO_baudrate=500000,
    calculate_swo_prescaler will return Prescaler=171.
    The correct value should be Prescaler=176 (TPIU_ACPR=175).
    
    Might be related to https://sourceforge.net/p/openocd/tickets/263/
    
    Change-Id: Ib4d6df6e34685a9be4c2995cb500b2411c76e39b
    Signed-off-by: Adrian Negreanu <adr...@nx...>
    Reviewed-on: http://openocd.zylin.com/5807
    Tested-by: jenkins
    Reviewed-by: Marc Schink <de...@za...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/jtag/drivers/jlink.c b/src/jtag/drivers/jlink.c
index 57e357b79..910799ce2 100644
--- a/src/jtag/drivers/jlink.c
+++ b/src/jtag/drivers/jlink.c
@@ -1270,16 +1270,14 @@ static bool calculate_swo_prescaler(unsigned int traceclkin_freq,
 		uint32_t trace_freq, uint16_t *prescaler)
 {
 	unsigned int presc;
-	double deviation;
-
-	presc = ((1.0 - SWO_MAX_FREQ_DEV) * traceclkin_freq) / trace_freq + 1;
-
+	presc = DIV_ROUND_UP(traceclkin_freq, trace_freq);
 	if (presc > TPIU_ACPR_MAX_SWOSCALER)
 		return false;
 
-	deviation = fabs(1.0 - ((double)trace_freq * presc / traceclkin_freq));
-
-	if (deviation > SWO_MAX_FREQ_DEV)
+	/* Probe's UART speed must be within 3% of the TPIU's SWO baud rate. */
+	unsigned int max_deviation = (traceclkin_freq * 3) / 100;
+	if (presc * trace_freq < traceclkin_freq - max_deviation ||
+	    presc * trace_freq > traceclkin_freq + max_deviation)
 		return false;
 
 	*prescaler = presc;

commit 35e580373a77438f2832974b1f0dc36863dc3f03
Author: Tarek BOCHKATI <tar...@gm...>
Date:   Tue Aug 11 12:34:50 2020 +0100

    Add support of STM32H72x/73x 1M (0x483)
    
    STM32H72x/73x flash is similar to STM32H74x/75x,
    except STM32H72x/73x devices have only one single flash bank.
    
    Change-Id: I3d3422dc60234f8273172924f426200210f388cc
    Signed-off-by: Tarek BOCHKATI <tar...@gm...>
    Reviewed-on: http://openocd.zylin.com/5792
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c
index ac7d75948..52e3e0e87 100644
--- a/src/flash/nor/stm32h7x.c
+++ b/src/flash/nor/stm32h7x.c
@@ -147,7 +147,11 @@ static const struct stm32h7x_rev stm32_480_revs[] = {
 	{ 0x1000, "A"},
 };
 
-static uint32_t stm32x_compute_flash_cr_450(uint32_t cmd, int snb)
+static const struct stm32h7x_rev stm32_483_revs[] = {
+	{ 0x1000, "A" }, { 0x1001, "Z" },
+};
+
+static uint32_t stm32x_compute_flash_cr_450_483(uint32_t cmd, int snb)
 {
 	return cmd | (snb << 8);
 }
@@ -177,7 +181,7 @@ static const struct stm32h7x_part_info stm32h7x_parts[] = {
 	.fsize_addr			= 0x1FF1E880,
 	.wps_group_size		= 1,
 	.wps_mask			= 0xFF,
-	.compute_flash_cr	= stm32x_compute_flash_cr_450,
+	.compute_flash_cr	= stm32x_compute_flash_cr_450_483,
 	},
 	{
 	.id					= 0x480,
@@ -194,6 +198,21 @@ static const struct stm32h7x_part_info stm32h7x_parts[] = {
 	.wps_mask			= 0xFFFFFFFF,
 	.compute_flash_cr	= stm32x_compute_flash_cr_480,
 	},
+	{
+	.id					= 0x483,
+	.revs				= stm32_483_revs,
+	.num_revs			= ARRAY_SIZE(stm32_483_revs),
+	.device_str			= "STM32H72x/73x",
+	.page_size_kb		= 128,
+	.block_size			= 32,
+	.max_flash_size_kb	= 1024,
+	.max_bank_size_kb	= 1024,
+	.has_dual_bank		= false,
+	.fsize_addr			= 0x1FF1E880,
+	.wps_group_size		= 1,
+	.wps_mask			= 0xFF,
+	.compute_flash_cr   = stm32x_compute_flash_cr_450_483,
+	},
 };
 
 /* flash bank stm32x <base> <size> 0 0 <target#> */
@@ -804,6 +823,8 @@ static int stm32x_probe(struct flash_bank *bank)
 			/* flash size is 2M or 1M */
 			flash_size_in_kb /= 2;
 		break;
+	case 0x483:
+		break;
 	default:
 		LOG_ERROR("unsupported device");
 		return ERROR_FAIL;

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/stm32h7x.c | 25 +++++++++++++++++++++++--
 src/jtag/drivers/jlink.c | 12 +++++-------
 2 files changed, 28 insertions(+), 9 deletions(-)


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Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1409-g67008e1be

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- Log -----------------------------------------------------------------
commit 67008e1bea2dd1a89d77802b892d3390e8a55455
Author: Marc Schink <de...@za...>
Date:   Wed Aug 12 13:54:10 2020 +0200

    Use capstone for ARM disassembler
    
    Change-Id: I1c9bf3f8178d4a06babe23a918e4411833ebc418
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: http://openocd.zylin.com/4812
    Tested-by: jenkins
    Reviewed-by: Fredrik Hederstierna <fr...@he...>
    Reviewed-by: Tarek BOCHKATI <tar...@gm...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/configure.ac b/configure.ac
index 90ac2a98c..fc6734cf8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -639,6 +639,15 @@ PKG_CHECK_MODULES([LIBUSB1], [libusb-1.0], [
 
 PKG_CHECK_MODULES([LIBUSB0], [libusb], [use_libusb0=yes], [use_libusb0=no])
 
+PKG_CHECK_MODULES([CAPSTONE], [capstone], [have_capstone=yes],
+	[have_capstone=no])
+
+AS_IF([test "x$have_capstone" = "xyes"], [
+  AC_DEFINE([HAVE_CAPSTONE], [1], [1 if you have captone disassembly framework.])
+], [
+  AC_DEFINE([HAVE_CAPSTONE], [0], [0 if you don't have captone disassembly framework.])
+])
+
 for hidapi_lib in hidapi hidapi-hidraw hidapi-libusb; do
 	PKG_CHECK_MODULES([HIDAPI],[$hidapi_lib],[
 		use_hidapi=yes
@@ -757,6 +766,7 @@ AM_CONDITIONAL([USE_LIBGPIOD], [test "x$use_libgpiod" = "xyes"])
 AM_CONDITIONAL([USE_HIDAPI], [test "x$use_hidapi" = "xyes"])
 AM_CONDITIONAL([USE_LIBJAYLINK], [test "x$use_libjaylink" = "xyes"])
 AM_CONDITIONAL([RSHIM], [test "x$build_rshim" = "xyes"])
+AM_CONDITIONAL([HAVE_CAPSTONE], [test "x$have_capstone" = "xyes"])
 
 AM_CONDITIONAL([MINIDRIVER], [test "x$build_minidriver" = "xyes"])
 AM_CONDITIONAL([MINIDRIVER_DUMMY], [test "x$build_minidriver_dummy" = "xyes"])
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 42d809d01..724f38c24 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -7,6 +7,7 @@ endif
 %C%_libtarget_la_LIBADD = %D%/openrisc/libopenrisc.la \
 	%D%/riscv/libriscv.la
 
+%C%_libtarget_la_CPPFLAGS = $(AM_CPPFLAGS)
 
 STARTUP_TCL_SRCS += %D%/startup.tcl
 
@@ -33,6 +34,11 @@ noinst_LTLIBRARIES += %D%/libtarget.la
 	$(ARMV8_SRC) \
 	$(MIPS64_SRC)
 
+if HAVE_CAPSTONE
+%C%_libtarget_la_CPPFLAGS += $(CAPSTONE_CFLAGS)
+%C%_libtarget_la_LIBADD += $(CAPSTONE_LIBS)
+endif
+
 TARGET_CORE_SRC = \
 	%D%/algorithm.c \
 	%D%/register.c \
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 59c0537b7..9b8c09e45 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -26,6 +26,10 @@
 #include "arm_disassembler.h"
 #include <helper/log.h>
 
+#if HAVE_CAPSTONE
+#include <capstone/capstone.h>
+#endif
+
 /*
  * This disassembler supports two main functions for OpenOCD:
  *
@@ -3000,1616 +3004,126 @@ int thumb_evaluate_opcode(uint16_t opcode, uint32_t address, struct arm_instruct
 	return -1;
 }
 
-static int t2ev_b_bl(uint32_t opcode, uint32_t address,
-		     struct arm_instruction *instruction, char *cp)
-{
-	unsigned offset;
-	unsigned b21 = 1 << 21;
-	unsigned b22 = 1 << 22;
-
-	/* instead of combining two smaller 16-bit branch instructions,
-	 * Thumb2 uses only one larger 32-bit instruction.
-	 */
-	offset = opcode & 0x7ff;
-	offset |= (opcode & 0x03ff0000) >> 5;
-	if (opcode & (1 << 26)) {
-		offset |= 0xff << 23;
-		if ((opcode & (1 << 11)) == 0)
-			b21 = 0;
-		if ((opcode & (1 << 13)) == 0)
-			b22 = 0;
-	} else {
-		if (opcode & (1 << 11))
-			b21 = 0;
-		if (opcode & (1 << 13))
-			b22 = 0;
-	}
-	offset |= b21;
-	offset |= b22;
-
-
-	address += 4;
-	address += offset << 1;
-
-	char *inst;
-	switch ((opcode >> 12) & 0x5) {
-	case 0x1:
-		inst = "B.W";
-		instruction->type = ARM_B;
-		break;
-	case 0x4:
-		inst = "BLX";
-		instruction->type = ARM_BLX;
-		address &= 0xfffffffc;
-		break;
-	case 0x5:
-		inst = "BL";
-		instruction->type = ARM_BL;
-		break;
-	default:
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-	instruction->info.b_bl_bx_blx.reg_operand = -1;
-	instruction->info.b_bl_bx_blx.target_address = address;
-	sprintf(cp, "%s\t%#8.8" PRIx32, inst, address);
-
-	return ERROR_OK;
-}
-
-static int t2ev_cond_b(uint32_t opcode, uint32_t address,
-		       struct arm_instruction *instruction, char *cp)
-{
-	unsigned offset;
-	unsigned b17 = 1 << 17;
-	unsigned b18 = 1 << 18;
-	unsigned cond = (opcode >> 22) & 0x0f;
-
-	offset = opcode & 0x7ff;
-	offset |= (opcode & 0x003f0000) >> 5;
-	if (opcode & (1 << 26)) {
-		offset |= 0x1fff << 19;
-		if ((opcode & (1 << 11)) == 0)
-			b17 = 0;
-		if ((opcode & (1 << 13)) == 0)
-			b18 = 0;
-	} else {
-		if (opcode & (1 << 11))
-			b17 = 0;
-		if (opcode & (1 << 13))
-			b18 = 0;
-	}
-	offset |= b17;
-	offset |= b18;
-
-	address += 4;
-	address += offset << 1;
-
-	instruction->type = ARM_B;
-	instruction->info.b_bl_bx_blx.reg_operand = -1;
-	instruction->info.b_bl_bx_blx.target_address = address;
-	sprintf(cp, "B%s.W\t%#8.8" PRIx32,
-			arm_condition_strings[cond],
-			address);
-
-	return ERROR_OK;
-}
-
-static const char *special_name(int number)
+int arm_access_size(struct arm_instruction *instruction)
 {
-	char *special = "(RESERVED)";
-
-	switch (number) {
-		case 0:
-			special = "apsr";
-			break;
-		case 1:
-			special = "iapsr";
-			break;
-		case 2:
-			special = "eapsr";
-			break;
-		case 3:
-			special = "xpsr";
-			break;
-		case 5:
-			special = "ipsr";
-			break;
-		case 6:
-			special = "epsr";
-			break;
-		case 7:
-			special = "iepsr";
-			break;
-		case 8:
-			special = "msp";
-			break;
-		case 9:
-			special = "psp";
-			break;
-		case 16:
-			special = "primask";
-			break;
-		case 17:
-			special = "basepri";
-			break;
-		case 18:
-			special = "basepri_max";
-			break;
-		case 19:
-			special = "faultmask";
-			break;
-		case 20:
-			special = "control";
-			break;
+	if ((instruction->type == ARM_LDRB)
+	    || (instruction->type == ARM_LDRBT)
+	    || (instruction->type == ARM_LDRSB)
+	    || (instruction->type == ARM_STRB)
+	    || (instruction->type == ARM_STRBT))
+		return 1;
+	else if ((instruction->type == ARM_LDRH)
+		 || (instruction->type == ARM_LDRSH)
+		 || (instruction->type == ARM_STRH))
+		return 2;
+	else if ((instruction->type == ARM_LDR)
+		 || (instruction->type == ARM_LDRT)
+		 || (instruction->type == ARM_STR)
+		 || (instruction->type == ARM_STRT))
+		return 4;
+	else if ((instruction->type == ARM_LDRD)
+		 || (instruction->type == ARM_STRD))
+		return 8;
+	else {
+		LOG_ERROR("BUG: instruction type %i isn't a load/store instruction",
+				instruction->type);
+		return 0;
 	}
-	return special;
 }
 
-static int t2ev_hint(uint32_t opcode, uint32_t address,
-		     struct arm_instruction *instruction, char *cp)
+#if HAVE_CAPSTONE
+static void print_opcode(struct command_invocation *cmd, const cs_insn *insn)
 {
-	const char *mnemonic;
+	uint32_t opcode = 0;
 
-	if (opcode & 0x0700) {
-		instruction->type = ARM_UNDEFINED_INSTRUCTION;
-		strcpy(cp, "UNDEFINED");
-		return ERROR_OK;
-	}
+	memcpy(&opcode, insn->bytes, insn->size);
 
-	if (opcode & 0x00f0) {
-		sprintf(cp, "DBG\t#%d", (int) opcode & 0xf);
-		return ERROR_OK;
-	}
+	if (insn->size == 4) {
+		uint16_t opcode_high = opcode >> 16;
+		opcode = opcode & 0xffff;
 
-	switch (opcode & 0x0f) {
-		case 0:
-			mnemonic = "NOP.W";
-			break;
-		case 1:
-			mnemonic = "YIELD.W";
-			break;
-		case 2:
-			mnemonic = "WFE.W";
-			break;
-		case 3:
-			mnemonic = "WFI.W";
-			break;
-		case 4:
-			mnemonic = "SEV.W";
-			break;
-		default:
-			mnemonic = "HINT.W (UNRECOGNIZED)";
-			break;
+		command_print(cmd, "0x%08" PRIx64"  %04x %04x\t%s%s%s",
+			insn->address, opcode, opcode_high, insn->mnemonic,
+			insn->op_str[0] ? "\t" : "", insn->op_str);
+	} else {
+		command_print(cmd, "0x%08" PRIx64"  %04x\t%s%s%s",
+			insn->address, opcode, insn->mnemonic,
+			insn->op_str[0] ? "\t" : "", insn->op_str);
 	}
-	strcpy(cp, mnemonic);
-	return ERROR_OK;
 }
 
-static int t2ev_misc(uint32_t opcode, uint32_t address,
-		     struct arm_instruction *instruction, char *cp)
+int arm_disassemble(struct command_invocation *cmd, struct target *target,
+		target_addr_t address, size_t count, bool thumb_mode)
 {
-	const char *mnemonic;
+	csh handle;
+	int ret;
+	cs_insn *insn;
+	cs_mode mode;
 
-	switch ((opcode >> 4) & 0x0f) {
-		case 0:
-			mnemonic = "LEAVEX";
-			break;
-		case 1:
-			mnemonic = "ENTERX";
-			break;
-		case 2:
-			mnemonic = "CLREX";
-			break;
-		case 4:
-			mnemonic = "DSB";
-			break;
-		case 5:
-			mnemonic = "DMB";
-			break;
-		case 6:
-			mnemonic = "ISB";
-			break;
-		default:
-			return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-	strcpy(cp, mnemonic);
-	return ERROR_OK;
-}
-
-static int t2ev_b_misc(uint32_t opcode, uint32_t address,
-		       struct arm_instruction *instruction, char *cp)
-{
-	/* permanently undefined */
-	if ((opcode & 0x07f07000) == 0x07f02000) {
-		instruction->type = ARM_UNDEFINED_INSTRUCTION;
-		strcpy(cp, "UNDEFINED");
-		return ERROR_OK;
+	if (!cs_support(CS_ARCH_ARM)) {
+		LOG_ERROR("ARM architecture not supported by capstone");
+		return ERROR_FAIL;
 	}
 
-	switch ((opcode >> 12) & 0x5) {
-		case 0x1:
-		case 0x4:
-		case 0x5:
-			return t2ev_b_bl(opcode, address, instruction, cp);
-		case 0:
-			if (((opcode >> 23) & 0x07) != 0x07)
-				return t2ev_cond_b(opcode, address, instruction, cp);
-			if (opcode & (1 << 26))
-				goto undef;
-			break;
-	}
+	mode = CS_MODE_LITTLE_ENDIAN;
 
-	switch ((opcode >> 20) & 0x7f) {
-		case 0x38:
-		case 0x39:
-			sprintf(cp, "MSR\t%s, r%d", special_name(opcode & 0xff),
-				(int) (opcode >> 16) & 0x0f);
-			return ERROR_OK;
-		case 0x3a:
-			return t2ev_hint(opcode, address, instruction, cp);
-		case 0x3b:
-			return t2ev_misc(opcode, address, instruction, cp);
-		case 0x3c:
-			sprintf(cp, "BXJ\tr%d", (int) (opcode >> 16) & 0x0f);
-			return ERROR_OK;
-		case 0x3e:
-		case 0x3f:
-			sprintf(cp, "MRS\tr%d, %s", (int) (opcode >> 8) & 0x0f,
-				special_name(opcode & 0xff));
-			return ERROR_OK;
-	}
+	if (thumb_mode)
+		mode |= CS_MODE_THUMB;
 
-undef:
-	return ERROR_COMMAND_SYNTAX_ERROR;
-}
+	ret = cs_open(CS_ARCH_ARM, mode, &handle);
 
-static int t2ev_data_mod_immed(uint32_t opcode, uint32_t address,
-			       struct arm_instruction *instruction, char *cp)
-{
-	char *mnemonic = NULL;
-	int rn = (opcode >> 16) & 0xf;
-	int rd = (opcode >> 8) & 0xf;
-	unsigned immed = opcode & 0xff;
-	unsigned func;
-	bool one = false;
-	char *suffix = "";
-	char *suffix2 = "";
-
-	/* ARMv7-M: A5.3.2 Modified immediate constants */
-	func = (opcode >> 11) & 0x0e;
-	if (immed & 0x80)
-		func |= 1;
-	if (opcode & (1 << 26))
-		func |= 0x10;
-
-	/* "Modified" immediates */
-	switch (func >> 1) {
-		case 0:
-			break;
-		case 2:
-			immed <<= 8;
-		/* FALLTHROUGH */
-		case 1:
-			immed += immed << 16;
-			break;
-		case 3:
-			immed += immed << 8;
-			immed += immed << 16;
-			break;
-		default:
-			immed |= 0x80;
-			immed = ror(immed, func);
+	if (ret != CS_ERR_OK) {
+		LOG_ERROR("cs_open() failed: %s", cs_strerror(ret));
+		return ERROR_FAIL;
 	}
 
-	if (opcode & (1 << 20))
-		suffix = "S";
+	ret = cs_option(handle, CS_OPT_SKIPDATA, CS_OPT_ON);
 
-	switch ((opcode >> 21) & 0xf) {
-		case 0:
-			if (rd == 0xf) {
-				instruction->type = ARM_TST;
-				mnemonic = "TST";
-				one = true;
-				suffix = "";
-				rd = rn;
-			} else {
-				instruction->type = ARM_AND;
-				mnemonic = "AND";
-			}
-			break;
-		case 1:
-			instruction->type = ARM_BIC;
-			mnemonic = "BIC";
-			break;
-		case 2:
-			if (rn == 0xf) {
-				instruction->type = ARM_MOV;
-				mnemonic = "MOV";
-				one = true;
-				suffix2 = ".W";
-			} else {
-				instruction->type = ARM_ORR;
-				mnemonic = "ORR";
-			}
-			break;
-		case 3:
-			if (rn == 0xf) {
-				instruction->type = ARM_MVN;
-				mnemonic = "MVN";
-				one = true;
-			} else {
-				/* instruction->type = ARM_ORN; */
-				mnemonic = "ORN";
-			}
-			break;
-		case 4:
-			if (rd == 0xf) {
-				instruction->type = ARM_TEQ;
-				mnemonic = "TEQ";
-				one = true;
-				suffix = "";
-				rd = rn;
-			} else {
-				instruction->type = ARM_EOR;
-				mnemonic = "EOR";
-			}
-			break;
-		case 8:
-			if (rd == 0xf) {
-				instruction->type = ARM_CMN;
-				mnemonic = "CMN";
-				one = true;
-				suffix = "";
-				rd = rn;
-			} else {
-				instruction->type = ARM_ADD;
-				mnemonic = "ADD";
-				suffix2 = ".W";
-			}
-			break;
-		case 10:
-			instruction->type = ARM_ADC;
-			mnemonic = "ADC";
-			suffix2 = ".W";
-			break;
-		case 11:
-			instruction->type = ARM_SBC;
-			mnemonic = "SBC";
-			break;
-		case 13:
-			if (rd == 0xf) {
-				instruction->type = ARM_CMP;
-				mnemonic = "CMP";
-				one = true;
-				suffix = "";
-				rd = rn;
-			} else {
-				instruction->type = ARM_SUB;
-				mnemonic = "SUB";
-			}
-			suffix2 = ".W";
-			break;
-		case 14:
-			instruction->type = ARM_RSB;
-			mnemonic = "RSB";
-			suffix2 = ".W";
-			break;
-		default:
-			return ERROR_COMMAND_SYNTAX_ERROR;
+	if (ret != CS_ERR_OK) {
+		LOG_ERROR("cs_option() failed: %s", cs_strerror(ret));
+		cs_close(&handle);
+		return ERROR_FAIL;
 	}
 
-	if (one)
-		sprintf(cp, "%s%s\tr%d, #%d\t; %#8.8x",
-				mnemonic, suffix2, rd, immed, immed);
-	else
-		sprintf(cp, "%s%s%s\tr%d, r%d, #%d\t; %#8.8x",
-				mnemonic, suffix, suffix2,
-				rd, rn, immed, immed);
-
-	return ERROR_OK;
-}
-
-static int t2ev_data_immed(uint32_t opcode, uint32_t address,
-			   struct arm_instruction *instruction, char *cp)
-{
-	char *mnemonic = NULL;
-	int rn = (opcode >> 16) & 0xf;
-	int rd = (opcode >> 8) & 0xf;
-	unsigned immed;
-	bool add = false;
-	bool is_signed = false;
-
-	immed = (opcode & 0x0ff) | ((opcode & 0x7000) >> 4);
-	if (opcode & (1 << 26))
-		immed |= (1 << 11);
+	insn = cs_malloc(handle);
 
-	switch ((opcode >> 20) & 0x1f) {
-		case 0:
-			if (rn == 0xf) {
-				add = true;
-				goto do_adr;
-			}
-			mnemonic = "ADDW";
-			break;
-		case 4:
-			immed |= (opcode >> 4) & 0xf000;
-			sprintf(cp, "MOVW\tr%d, #%d\t; %#3.3x", rd, immed, immed);
-			return ERROR_OK;
-		case 0x0a:
-			if (rn == 0xf)
-				goto do_adr;
-			mnemonic = "SUBW";
-			break;
-		case 0x0c:
-			/* move constant to top 16 bits of register */
-			immed |= (opcode >> 4) & 0xf000;
-			sprintf(cp, "MOVT\tr%d, #%d\t; %#4.4x", rd, immed, immed);
-			return ERROR_OK;
-		case 0x10:
-		case 0x12:
-			is_signed = true;
-			/* fallthrough */
-		case 0x18:
-		case 0x1a:
-			/* signed/unsigned saturated add */
-			immed = (opcode >> 6) & 0x03;
-			immed |= (opcode >> 10) & 0x1c;
-			sprintf(cp, "%sSAT\tr%d, #%d, r%d, %s #%d\t",
-				is_signed ? "S" : "U",
-				rd, (int) (opcode & 0x1f) + is_signed, rn,
-				(opcode & (1 << 21)) ? "ASR" : "LSL",
-				immed ? immed : 32);
-			return ERROR_OK;
-		case 0x14:
-			is_signed = true;
-		/* FALLTHROUGH */
-		case 0x1c:
-			/* signed/unsigned bitfield extract */
-			immed = (opcode >> 6) & 0x03;
-			immed |= (opcode >> 10) & 0x1c;
-			sprintf(cp, "%sBFX\tr%d, r%d, #%d, #%d\t",
-				is_signed ? "S" : "U",
-				rd, rn, immed,
-				(int) (opcode & 0x1f) + 1);
-			return ERROR_OK;
-		case 0x16:
-			immed = (opcode >> 6) & 0x03;
-			immed |= (opcode >> 10) & 0x1c;
-			if (rn == 0xf)	/* bitfield clear */
-				sprintf(cp, "BFC\tr%d, #%d, #%d\t",
-						rd, immed,
-						(int) (opcode & 0x1f) + 1 - immed);
-			else		/* bitfield insert */
-				sprintf(cp, "BFI\tr%d, r%d, #%d, #%d\t",
-						rd, rn, immed,
-						(int) (opcode & 0x1f) + 1 - immed);
-			return ERROR_OK;
-		default:
-			return ERROR_COMMAND_SYNTAX_ERROR;
+	if (!insn) {
+		LOG_ERROR("cs_malloc() failed\n");
+		cs_close(&handle);
+		return ERROR_FAIL;
 	}
 
-	sprintf(cp, "%s\tr%d, r%d, #%d\t; %#3.3x", mnemonic,
-			rd, rn, immed, immed);
-	return ERROR_OK;
+	while (count > 0) {
+	    uint8_t buffer[4];
 
-do_adr:
-	address = thumb_alignpc4(address);
-	if (add)
-		address += immed;
-	else
-		address -= immed;
-	/* REVISIT "ADD/SUB Rd, PC, #const ; 0x..." might be better;
-	 * not hiding the pc-relative stuff will sometimes be useful.
-	 */
-	sprintf(cp, "ADR.W\tr%d, %#8.8" PRIx32, rd, address);
-	return ERROR_OK;
-}
+		ret = target_read_buffer(target, address, sizeof(buffer), buffer);
 
-static int t2ev_store_single(uint32_t opcode, uint32_t address,
-			     struct arm_instruction *instruction, char *cp)
-{
-	unsigned op = (opcode >> 20) & 0xf;
-	char *size = "";
-	char *suffix = "";
-	char *p1 = "";
-	char *p2 = "]";
-	unsigned immed;
-	unsigned rn = (opcode >> 16) & 0x0f;
-	unsigned rt = (opcode >> 12) & 0x0f;
-
-	if (rn == 0xf)
-		return ERROR_COMMAND_SYNTAX_ERROR;
-
-	if (opcode & 0x0800)
-		op |= 1;
-	switch (op) {
-		/* byte */
-		case 0x8:
-		case 0x9:
-			size = "B";
-			goto imm12;
-		case 0x1:
-			size = "B";
-			goto imm8;
-		case 0x0:
-			size = "B";
-			break;
-		/* halfword */
-		case 0xa:
-		case 0xb:
-			size = "H";
-			goto imm12;
-		case 0x3:
-			size = "H";
-			goto imm8;
-		case 0x2:
-			size = "H";
-			break;
-		/* word */
-		case 0xc:
-		case 0xd:
-			goto imm12;
-		case 0x5:
-			goto imm8;
-		case 0x4:
-			break;
-		/* error */
-		default:
-			return ERROR_COMMAND_SYNTAX_ERROR;
-	}
+		if (ret != ERROR_OK) {
+			cs_free(insn, 1);
+			cs_close(&handle);
+			return ret;
+		}
 
-	sprintf(cp, "STR%s.W\tr%d, [r%d, r%d, LSL #%d]",
-			size, rt, rn, (int) opcode & 0x0f,
-			(int) (opcode >> 4) & 0x03);
-	return ERROR_OK;
+		size_t size = sizeof(buffer);
+		const uint8_t *tmp = buffer;
 
-imm12:
-	immed = opcode & 0x0fff;
-	sprintf(cp, "STR%s.W\tr%d, [r%d, #%u]\t; %#3.3x",
-			size, rt, rn, immed, immed);
-	return ERROR_OK;
+		ret = cs_disasm_iter(handle, &tmp, &size, &address, insn);
 
-imm8:
-	immed = opcode & 0x00ff;
+		if (!ret) {
+			LOG_ERROR("cs_disasm_iter() failed: %s",
+				cs_strerror(cs_errno(handle)));
+			cs_free(insn, 1);
+			cs_close(&handle);
+			return ERROR_FAIL;
+		}
 
-	switch (opcode & 0x700) {
-		case 0x600:
-			suffix = "T";
-			break;
-		case 0x000:
-		case 0x200:
-			return ERROR_COMMAND_SYNTAX_ERROR;
+		print_opcode(cmd, insn);
+		count--;
 	}
 
-	/* two indexed modes will write back rn */
-	if (opcode & 0x100) {
-		if (opcode & 0x400)	/* pre-indexed */
-			p2 = "]!";
-		else {			/* post-indexed */
-			p1 = "]";
-			p2 = "";
-		}
-	}
+	cs_free(insn, 1);
+	cs_close(&handle);
 
-	sprintf(cp, "STR%s%s\tr%d, [r%d%s, #%s%u%s\t; %#2.2x",
-			size, suffix, rt, rn, p1,
-			(opcode & 0x200) ? "" : "-",
-			immed, p2, immed);
 	return ERROR_OK;
 }
-
-static int t2ev_mul32(uint32_t opcode, uint32_t address,
-		      struct arm_instruction *instruction, char *cp)
-{
-	int ra = (opcode >> 12) & 0xf;
-
-	switch (opcode & 0x007000f0) {
-		case 0:
-			if (ra == 0xf)
-				sprintf(cp, "MUL\tr%d, r%d, r%d",
-						(int) (opcode >> 8) & 0xf,
-						(int) (opcode >> 16) & 0xf,
-						(int) (opcode >> 0) & 0xf);
-			else
-				sprintf(cp, "MLA\tr%d, r%d, r%d, r%d",
-						(int) (opcode >> 8) & 0xf,
-						(int) (opcode >> 16) & 0xf,
-						(int) (opcode >> 0) & 0xf, ra);
-			break;
-		case 0x10:
-			sprintf(cp, "MLS\tr%d, r%d, r%d, r%d",
-				(int) (opcode >> 8) & 0xf,
-				(int) (opcode >> 16) & 0xf,
-				(int) (opcode >> 0) & 0xf, ra);
-			break;
-		default:
-			return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-	return ERROR_OK;
-}
-
-static int t2ev_mul64_div(uint32_t opcode, uint32_t address,
-			  struct arm_instruction *instruction, char *cp)
-{
-	int op = (opcode >> 4) & 0xf;
-	char *infix = "MUL";
-
-	op += (opcode >> 16) & 0x70;
-	switch (op) {
-		case 0x40:
-		case 0x60:
-			infix = "MLA";
-		/* FALLTHROUGH */
-		case 0:
-		case 0x20:
-			sprintf(cp, "%c%sL\tr%d, r%d, r%d, r%d",
-				(op & 0x20) ? 'U' : 'S',
-				infix,
-				(int) (opcode >> 12) & 0xf,
-				(int) (opcode >> 8) & 0xf,
-				(int) (opcode >> 16) & 0xf,
-				(int) (opcode >> 0) & 0xf);
-			break;
-		case 0x1f:
-		case 0x3f:
-			sprintf(cp, "%cDIV\tr%d, r%d, r%d",
-				(op & 0x20) ? 'U' : 'S',
-				(int) (opcode >> 8) & 0xf,
-				(int) (opcode >> 16) & 0xf,
-				(int) (opcode >> 0) & 0xf);
-			break;
-		default:
-			return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	return ERROR_OK;
-}
-
-static int t2ev_ldm_stm(uint32_t opcode, uint32_t address,
-			struct arm_instruction *instruction, char *cp)
-{
-	int rn = (opcode >> 16) & 0xf;
-	int op = (opcode >> 22) & 0x6;
-	int t = (opcode >> 21) & 1;
-	unsigned registers = opcode & 0xffff;
-	char *mode = "";
-
-	if (opcode & (1 << 20))
-		op |= 1;
-
-	switch (op) {
-		case 0:
-			mode = "DB";
-		/* FALL THROUGH */
-		case 6:
-			sprintf(cp, "SRS%s\tsp%s, #%d", mode,
-				t ? "!" : "",
-				(unsigned) (opcode & 0x1f));
-			return ERROR_OK;
-		case 1:
-			mode = "DB";
-		/* FALL THROUGH */
-		case 7:
-			sprintf(cp, "RFE%s\tr%d%s", mode,
-				(unsigned) ((opcode >> 16) & 0xf),
-				t ? "!" : "");
-			return ERROR_OK;
-		case 2:
-			sprintf(cp, "STM.W\tr%d%s, ", rn, t ? "!" : "");
-			break;
-		case 3:
-			if (rn == 13 && t)
-				sprintf(cp, "POP.W\t");
-			else
-				sprintf(cp, "LDM.W\tr%d%s, ", rn, t ? "!" : "");
-			break;
-		case 4:
-			if (rn == 13 && t)
-				sprintf(cp, "PUSH.W\t");
-			else
-				sprintf(cp, "STMDB\tr%d%s, ", rn, t ? "!" : "");
-			break;
-		case 5:
-			sprintf(cp, "LDMDB.W\tr%d%s, ", rn, t ? "!" : "");
-			break;
-		default:
-			return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	cp = strchr(cp, 0);
-	*cp++ = '{';
-	for (t = 0; registers; t++, registers >>= 1) {
-		if ((registers & 1) == 0)
-			continue;
-		registers &= ~1;
-		sprintf(cp, "r%d%s", t, registers ? ", " : "");
-		cp = strchr(cp, 0);
-	}
-	*cp++ = '}';
-	*cp++ = 0;
-
-	return ERROR_OK;
-}
-
-/* load/store dual or exclusive, table branch */
-static int t2ev_ldrex_strex(uint32_t opcode, uint32_t address,
-			    struct arm_instruction *instruction, char *cp)
-{
-	unsigned op1op2 = (opcode >> 20) & 0x3;
-	unsigned op3 = (opcode >> 4) & 0xf;
-	char *mnemonic;
-	unsigned rn = (opcode >> 16) & 0xf;
-	unsigned rt = (opcode >> 12) & 0xf;
-	unsigned rd = (opcode >> 8) & 0xf;
-	unsigned imm = opcode & 0xff;
-	char *p1 = "";
-	char *p2 = "]";
-
-	op1op2 |= (opcode >> 21) & 0xc;
-	switch (op1op2) {
-		case 0:
-			mnemonic = "STREX";
-			goto strex;
-		case 1:
-			mnemonic = "LDREX";
-			goto ldrex;
-		case 2:
-		case 6:
-		case 8:
-		case 10:
-		case 12:
-		case 14:
-			mnemonic = "STRD";
-			goto immediate;
-		case 3:
-		case 7:
-		case 9:
-		case 11:
-		case 13:
-		case 15:
-			mnemonic = "LDRD";
-			if (rn == 15)
-				goto literal;
-			else
-				goto immediate;
-		case 4:
-			switch (op3) {
-				case 4:
-					mnemonic = "STREXB";
-					break;
-				case 5:
-					mnemonic = "STREXH";
-					break;
-				default:
-					return ERROR_COMMAND_SYNTAX_ERROR;
-			}
-			rd = opcode & 0xf;
-			imm = 0;
-			goto strex;
-		case 5:
-			switch (op3) {
-				case 0:
-					sprintf(cp, "TBB\t[r%u, r%u]", rn, imm & 0xf);
-					return ERROR_OK;
-				case 1:
-					sprintf(cp, "TBH\t[r%u, r%u, LSL #1]", rn, imm & 0xf);
-					return ERROR_OK;
-				case 4:
-					mnemonic = "LDREXB";
-					break;
-				case 5:
-					mnemonic = "LDREXH";
-					break;
-				default:
-					return ERROR_COMMAND_SYNTAX_ERROR;
-			}
-			imm = 0;
-			goto ldrex;
-	}
-	return ERROR_COMMAND_SYNTAX_ERROR;
-
-strex:
-	imm <<= 2;
-	if (imm)
-		sprintf(cp, "%s\tr%u, r%u, [r%u, #%u]\t; %#2.2x",
-				mnemonic, rd, rt, rn, imm, imm);
-	else
-		sprintf(cp, "%s\tr%u, r%u, [r%u]",
-				mnemonic, rd, rt, rn);
-	return ERROR_OK;
-
-ldrex:
-	imm <<= 2;
-	if (imm)
-		sprintf(cp, "%s\tr%u, [r%u, #%u]\t; %#2.2x",
-				mnemonic, rt, rn, imm, imm);
-	else
-		sprintf(cp, "%s\tr%u, [r%u]",
-				mnemonic, rt, rn);
-	return ERROR_OK;
-
-immediate:
-	/* two indexed modes will write back rn */
-	if (opcode & (1 << 21)) {
-		if (opcode & (1 << 24))	/* pre-indexed */
-			p2 = "]!";
-		else {			/* post-indexed */
-			p1 = "]";
-			p2 = "";
-		}
-	}
-
-	imm <<= 2;
-	sprintf(cp, "%s\tr%u, r%u, [r%u%s, #%s%u%s\t; %#2.2x",
-			mnemonic, rt, rd, rn, p1,
-			(opcode & (1 << 23)) ? "" : "-",
-			imm, p2, imm);
-	return ERROR_OK;
-
-literal:
-	address = thumb_alignpc4(address);
-	imm <<= 2;
-	if (opcode & (1 << 23))
-		address += imm;
-	else
-		address -= imm;
-	sprintf(cp, "%s\tr%u, r%u, %#8.8" PRIx32,
-			mnemonic, rt, rd, address);
-	return ERROR_OK;
-}
-
-static int t2ev_data_shift(uint32_t opcode, uint32_t address,
-			   struct arm_instruction *instruction, char *cp)
-{
-	int op = (opcode >> 21) & 0xf;
-	int rd = (opcode >> 8) & 0xf;
-	int rn = (opcode >> 16) & 0xf;
-	int type = (opcode >> 4) & 0x3;
-	int immed = (opcode >> 6) & 0x3;
-	char *mnemonic;
-	char *suffix = "";
-
-	immed |= (opcode >> 10) & 0x1c;
-	if (opcode & (1 << 20))
-		suffix = "S";
-
-	switch (op) {
-		case 0:
-			if (rd == 0xf) {
-				if (!(opcode & (1 << 20)))
-					return ERROR_COMMAND_SYNTAX_ERROR;
-				instruction->type = ARM_TST;
-				mnemonic = "TST";
-				suffix = "";
-				goto two;
-			}
-			instruction->type = ARM_AND;
-			mnemonic = "AND";
-			break;
-		case 1:
-			instruction->type = ARM_BIC;
-			mnemonic = "BIC";
-			break;
-		case 2:
-			if (rn == 0xf) {
-				instruction->type = ARM_MOV;
-				switch (type) {
-					case 0:
-						if (immed == 0) {
-							sprintf(cp, "MOV%s.W\tr%d, r%d",
-									suffix, rd,
-									(int) (opcode & 0xf));
-							return ERROR_OK;
-						}
-						mnemonic = "LSL";
-						break;
-					case 1:
-						mnemonic = "LSR";
-						break;
-					case 2:
-						mnemonic = "ASR";
-						break;
-					default:
-						if (immed == 0) {
-							sprintf(cp, "RRX%s\tr%d, r%d",
-									suffix, rd,
-									(int) (opcode & 0xf));
-							return ERROR_OK;
-						}
-						mnemonic = "ROR";
-						break;
-				}
-				goto immediate;
-			} else {
-				instruction->type = ARM_ORR;
-				mnemonic = "ORR";
-			}
-			break;
-		case 3:
-			if (rn == 0xf) {
-				instruction->type = ARM_MVN;
-				mnemonic = "MVN";
-				rn = rd;
-				goto two;
-			} else {
-				/* instruction->type = ARM_ORN; */
-				mnemonic = "ORN";
-			}
-			break;
-		case 4:
-			if (rd == 0xf) {
-				if (!(opcode & (1 << 20)))
-					return ERROR_COMMAND_SYNTAX_ERROR;
-				instruction->type = ARM_TEQ;
-				mnemonic = "TEQ";
-				suffix = "";
-				goto two;
-			}
-			instruction->type = ARM_EOR;
-			mnemonic = "EOR";
-			break;
-		case 8:
-			if (rd == 0xf) {
-				if (!(opcode & (1 << 20)))
-					return ERROR_COMMAND_SYNTAX_ERROR;
-				instruction->type = ARM_CMN;
-				mnemonic = "CMN";
-				suffix = "";
-				goto two;
-			}
-			instruction->type = ARM_ADD;
-			mnemonic = "ADD";
-			break;
-		case 0xa:
-			instruction->type = ARM_ADC;
-			mnemonic = "ADC";
-			break;
-		case 0xb:
-			instruction->type = ARM_SBC;
-			mnemonic = "SBC";
-			break;
-		case 0xd:
-			if (rd == 0xf) {
-				if (!(opcode & (1 << 21)))
-					return ERROR_COMMAND_SYNTAX_ERROR;
-				instruction->type = ARM_CMP;
-				mnemonic = "CMP";
-				suffix = "";
-				goto two;
-			}
-			instruction->type = ARM_SUB;
-			mnemonic = "SUB";
-			break;
-		case 0xe:
-			instruction->type = ARM_RSB;
-			mnemonic = "RSB";
-			break;
-		default:
-			return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	sprintf(cp, "%s%s.W\tr%d, r%d, r%d",
-			mnemonic, suffix, rd, rn, (int) (opcode & 0xf));
-
-shift:
-	cp = strchr(cp, 0);
-
-	switch (type) {
-		case 0:
-			if (immed == 0)
-				return ERROR_OK;
-			suffix = "LSL";
-			break;
-		case 1:
-			suffix = "LSR";
-			if (immed == 32)
-				immed = 0;
-			break;
-		case 2:
-			suffix = "ASR";
-			if (immed == 32)
-				immed = 0;
-			break;
-		case 3:
-			if (immed == 0) {
-				strcpy(cp, ", RRX");
-				return ERROR_OK;
-			}
-			suffix = "ROR";
-			break;
-	}
-	sprintf(cp, ", %s #%d", suffix, immed ? immed : 32);
-	return ERROR_OK;
-
-two:
-	sprintf(cp, "%s%s.W\tr%d, r%d",
-			mnemonic, suffix, rn, (int) (opcode & 0xf));
-	goto shift;
-
-immediate:
-	sprintf(cp, "%s%s.W\tr%d, r%d, #%d",
-			mnemonic, suffix, rd,
-			(int) (opcode & 0xf), immed ? immed : 32);
-	return ERROR_OK;
-}
-
-static int t2ev_data_reg(uint32_t opcode, uint32_t address,
-			 struct arm_instruction *instruction, char *cp)
-{
-	char *mnemonic;
-	char *suffix = "";
-
-	if (((opcode >> 4) & 0xf) == 0) {
-		switch ((opcode >> 21) & 0x7) {
-			case 0:
-				mnemonic = "LSL";
-				break;
-			case 1:
-				mnemonic = "LSR";
-				break;
-			case 2:
-				mnemonic = "ASR";
-				break;
-			case 3:
-				mnemonic = "ROR";
-				break;
-			default:
-				return ERROR_COMMAND_SYNTAX_ERROR;
-		}
-
-		instruction->type = ARM_MOV;
-		if (opcode & (1 << 20))
-			suffix = "S";
-		sprintf(cp, "%s%s.W\tr%d, r%d, r%d",
-				mnemonic, suffix,
-				(int) (opcode >> 8) & 0xf,
-				(int) (opcode >> 16) & 0xf,
-				(int) (opcode >> 0) & 0xf);
-
-	} else if (opcode & (1 << 7)) {
-		switch ((opcode >> 20) & 0xf) {
-			case 0:
-			case 1:
-			case 4:
-			case 5:
-				switch ((opcode >> 4) & 0x3) {
-					case 1:
-						suffix = ", ROR #8";
-						break;
-					case 2:
-						suffix = ", ROR #16";
-						break;
-					case 3:
-						suffix = ", ROR #24";
-						break;
-				}
-				sprintf(cp, "%cXT%c.W\tr%d, r%d%s",
-					(opcode & (1 << 24)) ? 'U' : 'S',
-					(opcode & (1 << 26)) ? 'B' : 'H',
-					(int) (opcode >> 8) & 0xf,
-					(int) (opcode >> 0) & 0xf,
-					suffix);
-				break;
-			case 8:
-			case 9:
-			case 0xa:
-			case 0xb:
-				if (opcode & (1 << 6))
-					return ERROR_COMMAND_SYNTAX_ERROR;
-				if (((opcode >> 12) & 0xf) != 0xf)
-					return ERROR_COMMAND_SYNTAX_ERROR;
-				if (!(opcode & (1 << 20)))
-					return ERROR_COMMAND_SYNTAX_ERROR;
-
-				switch (((opcode >> 19) & 0x04)
-					| ((opcode >> 4) & 0x3)) {
-					case 0:
-						mnemonic = "REV.W";
-						break;
-					case 1:
-						mnemonic = "REV16.W";
-						break;
-					case 2:
-						mnemonic = "RBIT";
-						break;
-					case 3:
-						mnemonic = "REVSH.W";
-						break;
-					case 4:
-						mnemonic = "CLZ";
-						break;
-					default:
-						return ERROR_COMMAND_SYNTAX_ERROR;
-				}
-				sprintf(cp, "%s\tr%d, r%d",
-					mnemonic,
-					(int) (opcode >> 8) & 0xf,
-					(int) (opcode >> 0) & 0xf);
-				break;
-			default:
-				return ERROR_COMMAND_SYNTAX_ERROR;
-		}
-	}
-
-	return ERROR_OK;
-}
-
-static int t2ev_load_word(uint32_t opcode, uint32_t address,
-			  struct arm_instruction *instruction, char *cp)
-{
-	int rn = (opcode >> 16) & 0xf;
-	int immed;
-
-	instruction->type = ARM_LDR;
-
-	if (rn == 0xf) {
-		immed = opcode & 0x0fff;
-		if ((opcode & (1 << 23)) == 0)
-			immed = -immed;
-		sprintf(cp, "LDR\tr%d, %#8.8" PRIx32,
-				(int) (opcode >> 12) & 0xf,
-				thumb_alignpc4(address) + immed);
-		return ERROR_OK;
-	}
-
-	if (opcode & (1 << 23)) {
-		immed = opcode & 0x0fff;
-		sprintf(cp, "LDR.W\tr%d, [r%d, #%d]\t; %#3.3x",
-				(int) (opcode >> 12) & 0xf,
-				rn, immed, immed);
-		return ERROR_OK;
-	}
-
-	if (!(opcode & (0x3f << 6))) {
-		sprintf(cp, "LDR.W\tr%d, [r%d, r%d, LSL #%d]",
-				(int) (opcode >> 12) & 0xf,
-				rn,
-				(int) (opcode >> 0) & 0xf,
-				(int) (opcode >> 4) & 0x3);
-		return ERROR_OK;
-	}
-
-
-	if (((opcode >> 8) & 0xf) == 0xe) {
-		immed = opcode & 0x00ff;
-
-		sprintf(cp, "LDRT\tr%d, [r%d, #%d]\t; %#2.2x",
-				(int) (opcode >> 12) & 0xf,
-				rn, immed, immed);
-		return ERROR_OK;
-	}
-
-	if (((opcode >> 8) & 0xf) == 0xc || (opcode & 0x0900) == 0x0900) {
-		char *p1 = "]", *p2 = "";
-
-		if (!(opcode & 0x0500))
-			return ERROR_COMMAND_SYNTAX_ERROR;
-
-		immed = opcode & 0x00ff;
-
-		/* two indexed modes will write back rn */
-		if (opcode & 0x100) {
-			if (opcode & 0x400)	/* pre-indexed */
-				p2 = "]!";
-			else {			/* post-indexed */
-				p1 = "]";
-				p2 = "";
-			}
-		}
-
-		sprintf(cp, "LDR\tr%d, [r%d%s, #%s%u%s\t; %#2.2x",
-				(int) (opcode >> 12) & 0xf,
-				rn, p1,
-				(opcode & 0x200) ? "" : "-",
-				immed, p2, immed);
-		return ERROR_OK;
-	}
-
-	return ERROR_COMMAND_SYNTAX_ERROR;
-}
-
-static int t2ev_load_byte_hints(uint32_t opcode, uint32_t address,
-				struct arm_instruction *instruction, char *cp)
-{
-	int rn = (opcode >> 16) & 0xf;
-	int rt = (opcode >> 12) & 0xf;
-	int op2 = (opcode >> 6) & 0x3f;
-	unsigned immed;
-	char *p1 = "", *p2 = "]";
-	char *mnemonic;
-
-	switch ((opcode >> 23) & 0x3) {
-		case 0:
-			if ((rn & rt) == 0xf) {
-pld_literal:
-				immed = opcode & 0xfff;
-				address = thumb_alignpc4(address);
-				if (opcode & (1 << 23))
-					address += immed;
-				else
-					address -= immed;
-				sprintf(cp, "PLD\tr%d, %#8.8" PRIx32,
-						rt, address);
-				return ERROR_OK;
-			}
-			if (rn == 0x0f && rt != 0x0f) {
-ldrb_literal:
-				immed = opcode & 0xfff;
-				address = thumb_alignpc4(address);
-				if (opcode & (1 << 23))
-					address += immed;
-				else
-					address -= immed;
-				sprintf(cp, "LDRB\tr%d, %#8.8" PRIx32,
-						rt, address);
-				return ERROR_OK;
-			}
-			if (rn == 0x0f)
-				break;
-			if ((op2 & 0x3c) == 0x38) {
-				immed = opcode & 0xff;
-				sprintf(cp, "LDRBT\tr%d, [r%d, #%d]\t; %#2.2x",
-						rt, rn, immed, immed);
-				return ERROR_OK;
-			}
-			if ((op2 & 0x3c) == 0x30) {
-				if (rt == 0x0f) {
-					immed = opcode & 0xff;
-					immed = -immed;
-preload_immediate:
-					p1 = (opcode & (1 << 21)) ? "W" : "";
-					sprintf(cp, "PLD%s\t[r%d, #%d]\t; %#6.6x",
-							p1, rn, immed, immed);
-					return ERROR_OK;
-				}
-				mnemonic = "LDRB";
-ldrxb_immediate_t3:
-				immed = opcode & 0xff;
-				if (!(opcode & 0x200))
-					immed = -immed;
-
-				/* two indexed modes will write back rn */
-				if (opcode & 0x100) {
-					if (opcode & 0x400)	/* pre-indexed */
-						p2 = "]!";
-					else {		/* post-indexed */
-						p1 = "]";
-						p2 = "";
-					}
-				}
-ldrxb_immediate_t2:
-				sprintf(cp, "%s\tr%d, [r%d%s, #%d%s\t; %#8.8x",
-						mnemonic, rt, rn, p1,
-						immed, p2, immed);
-				return ERROR_OK;
-			}
-			if ((op2 & 0x24) == 0x24) {
-				mnemonic = "LDRB";
-				goto ldrxb_immediate_t3;
-			}
-			if (op2 == 0) {
-				int rm = opcode & 0xf;
-
-				if (rt == 0x0f)
-					sprintf(cp, "PLD\t");
-				else
-					sprintf(cp, "LDRB.W\tr%d, ", rt);
-				immed = (opcode >> 4) & 0x3;
-				cp = strchr(cp, 0);
-				sprintf(cp, "[r%d, r%d, LSL #%d]", rn, rm, immed);
-				return ERROR_OK;
-			}
-			break;
-		case 1:
-			if ((rn & rt) == 0xf)
-				goto pld_literal;
-			if (rt == 0xf) {
-				immed = opcode & 0xfff;
-				goto preload_immediate;
-			}
-			if (rn == 0x0f)
-				goto ldrb_literal;
-			mnemonic = "LDRB.W";
-			immed = opcode & 0xfff;
-			goto ldrxb_immediate_t2;
-		case 2:
-			if ((rn & rt) == 0xf) {
-				immed = opcode & 0xfff;
-				address = thumb_alignpc4(address);
-				if (opcode & (1 << 23))
-					address += immed;
-				else
-					address -= immed;
-				sprintf(cp, "PLI\t%#8.8" PRIx32, address);
-				return ERROR_OK;
-			}
-			if (rn == 0xf && rt != 0xf) {
-ldrsb_literal:
-				immed = opcode & 0xfff;
-				address = thumb_alignpc4(address);
-				if (opcode & (1 << 23))
-					address += immed;
-				else
-					address -= immed;
-				sprintf(cp, "LDRSB\t%#8.8" PRIx32, address);
-				return ERROR_OK;
-			}
-			if (rn == 0xf)
-				break;
-			if ((op2 & 0x3c) == 0x38) {
-				immed = opcode & 0xff;
-				sprintf(cp, "LDRSBT\tr%d, [r%d, #%d]\t; %#2.2x",
-						rt, rn, immed, immed);
-				return ERROR_OK;
-			}
-			if ((op2 & 0x3c) == 0x30) {
-				if (rt == 0xf) {
-					immed = opcode & 0xff;
-					immed = -immed;	/* pli */
-					sprintf(cp, "PLI\t[r%d, #%d]\t; -%#2.2x",
-							rn, immed, -immed);
-					return ERROR_OK;
-				}
-				mnemonic = "LDRSB";
-				goto ldrxb_immediate_t3;
-			}
-			if ((op2 & 0x24) == 0x24) {
-				mnemonic = "LDRSB";
-				goto ldrxb_immediate_t3;
-			}
-			if (op2 == 0) {
-				int rm = opcode & 0xf;
-
-				if (rt == 0x0f)
-					sprintf(cp, "PLI\t");
-				else
-					sprintf(cp, "LDRSB.W\tr%d, ", rt);
-				immed = (opcode >> 4) & 0x3;
-				cp = strchr(cp, 0);
-				sprintf(cp, "[r%d, r%d, LSL #%d]", rn, rm, immed);
-				return ERROR_OK;
-			}
-			break;
-		case 3:
-			if (rt == 0xf) {
-				immed = opcode & 0xfff;
-				sprintf(cp, "PLI\t[r%d, #%d]\t; %#3.3x",
-						rn, immed, immed);
-				return ERROR_OK;
-			}
-			if (rn == 0xf)
-				goto ldrsb_literal;
-			immed = opcode & 0xfff;
-			mnemonic = "LDRSB";
-			goto ldrxb_immediate_t2;
-	}
-
-	return ERROR_COMMAND_SYNTAX_ERROR;
-}
-
-static int t2ev_load_halfword(uint32_t opcode, uint32_t address,
-			      struct arm_instruction *instruction, char *cp)
-{
-	int rn = (opcode >> 16) & 0xf;
-	int rt = (opcode >> 12) & 0xf;
-	int op2 = (opcode >> 6) & 0x3f;
-	char *sign = "";
-	unsigned immed;
-
-	if (rt == 0xf) {
-		sprintf(cp, "HINT (UNALLOCATED)");
-		return ERROR_OK;
-	}
-
-	if (opcode & (1 << 24))
-		sign = "S";
-
-	if ((opcode & (1 << 23)) == 0) {
-		if (rn == 0xf) {
-ldrh_literal:
-			immed = opcode & 0xfff;
-			address = thumb_alignpc4(address);
-			if (opcode & (1 << 23))
-				address += immed;
-			else
-				address -= immed;
-			sprintf(cp, "LDR%sH\tr%d, %#8.8" PRIx32,
-					sign, rt, address);
-			return ERROR_OK;
-		}
-		if (op2 == 0) {
-			int rm = opcode & 0xf;
-
-			immed = (opcode >> 4) & 0x3;
-			sprintf(cp, "LDR%sH.W\tr%d, [r%d, r%d, LSL #%d]",
-					sign, rt, rn, rm, immed);
-			return ERROR_OK;
-		}
-		if ((op2 & 0x3c) == 0x38) {
-			immed = opcode & 0xff;
-			sprintf(cp, "LDR%sHT\tr%d, [r%d, #%d]\t; %#2.2x",
-					sign, rt, rn, immed, immed);
-			return ERROR_OK;
-		}
-		if ((op2 & 0x3c) == 0x30 || (op2 & 0x24) == 0x24) {
-			char *p1 = "", *p2 = "]";
-
-			immed = opcode & 0xff;
-			if (!(opcode & 0x200))
-				immed = -immed;
-
-			/* two indexed modes will write back rn */
-			if (opcode & 0x100) {
-				if (opcode & 0x400)	/* pre-indexed */
-					p2 = "]!";
-				else {			/* post-indexed */
-					p1 = "]";
-					p2 = "";
-				}
-			}
-			sprintf(cp, "LDR%sH\tr%d, [r%d%s, #%d%s\t; %#8.8x",
-					sign, rt, rn, p1, immed, p2, immed);
-			return ERROR_OK;
-		}
-	} else {
-		if (rn == 0xf)
-			goto ldrh_literal;
-
-		immed = opcode & 0xfff;
-		sprintf(cp, "LDR%sH%s\tr%d, [r%d, #%d]\t; %#6.6x",
-				sign, *sign ? "" : ".W",
-				rt, rn, immed, immed);
-		return ERROR_OK;
-	}
-
-	return ERROR_COMMAND_SYNTAX_ERROR;
-}
-
-/*
- * REVISIT for Thumb2 instructions, instruction->type and friends aren't
- * always set.  That means eventual arm_simulate_step() support for Thumb2
- * will need work in this area.
- */
-int thumb2_opcode(struct target *target, uint32_t address, struct arm_instruction *instruction)
-{
-	int retval;
-	uint16_t op;
-	uint32_t opcode;
-	char *cp;
-
-	/* clear low bit ... it's set on function pointers */
-	address &= ~1;
-
-	/* clear fields, to avoid confusion */
-	memset(instruction, 0, sizeof(struct arm_instruction));
-
-	/* read first halfword, see if this is the only one */
-	retval = target_read_u16(target, address, &op);
-	if (retval != ERROR_OK)
-		return retval;
-
-	switch (op & 0xf800) {
-		case 0xf800:
-		case 0xf000:
-		case 0xe800:
-			/* 32-bit instructions */
-			instruction->instruction_size = 4;
-			opcode = op << 16;
-			retval = target_read_u16(target, address + 2, &op);
-			if (retval != ERROR_OK)
-				return retval;
-			opcode |= op;
-			instruction->opcode = opcode;
-			break;
-		default:
-			/* 16-bit:  Thumb1 + IT + CBZ/CBNZ + ... */
-			return thumb_evaluate_opcode(op, address, instruction);
-	}
-
-	snprintf(instruction->text, 128,
-			"0x%8.8" PRIx32 "  0x%8.8" PRIx32 "\t",
-			address, opcode);
-	cp = strchr(instruction->text, 0);
-	retval = ERROR_FAIL;
-
-	/* ARMv7-M: A5.3.1 Data processing (modified immediate) */
-	if ((opcode & 0x1a008000) == 0x10000000)
-		retval = t2ev_data_mod_immed(opcode, address, instruction, cp);
-
-	/* ARMv7-M: A5.3.3 Data processing (plain binary immediate) */
-	else if ((opcode & 0x1a008000) == 0x12000000)
-		retval = t2ev_data_immed(opcode, address, instruction, cp);
-
-	/* ARMv7-M: A5.3.4 Branches and miscellaneous control */
-	else if ((opcode & 0x18008000) == 0x10008000)
-		retval = t2ev_b_misc(opcode, address, instruction, cp);
-
-	/* ARMv7-M: A5.3.5 Load/store multiple */
-	else if ((opcode & 0x1e400000) == 0x08000000)
-		retval = t2ev_ldm_stm(opcode, address, instruction, cp);
-
-	/* ARMv7-M: A5.3.6 Load/store dual or exclusive, table branch */
-	else if ((opcode & 0x1e400000) == 0x08400000)
-		retval = t2ev_ldrex_strex(opcode, address, instruction, cp);
-
-	/* ARMv7-M: A5.3.7 Load word */
-	else if ((opcode & 0x1f700000) == 0x18500000)
-		retval = t2ev_load_word(opcode, address, instruction, cp);
-
-	/* ARMv7-M: A5.3.8 Load halfword, unallocated memory hints */
-	else if ((opcode & 0x1e700000) == 0x18300000)
-		retval = t2ev_load_halfword(opcode, address, instruction, cp);
-
-	/* ARMv7-M: A5.3.9 Load byte, memory hints */
-	else if ((opcode & 0x1e700000) == 0x18100000)
-		retval = t2ev_load_byte_hints(opcode, address, instruction, cp);
-
-	/* ARMv7-M: A5.3.10 Store single data item */
-	else if ((opcode & 0x1f100000) == 0x18000000)
-		retval = t2ev_store_single(opcode, address, instruction, cp);
-
-	/* ARMv7-M: A5.3.11 Data processing (shifted register) */
-	else if ((opcode & 0x1e000000) == 0x0a000000)
-		retval = t2ev_data_shift(opcode, address, instruction, cp);
-
-	/* ARMv7-M: A5.3.12 Data processing (register)
-	 * and A5.3.13 Miscellaneous operations
-	 */
-	else if ((opcode & 0x1f000000) == 0x1a000000)
-		retval = t2ev_data_reg(opcode, address, instruction, cp);
-
-	/* ARMv7-M: A5.3.14 Multiply, and multiply accumulate */
-	else if ((opcode & 0x1f800000) == 0x1b000000)
-		retval = t2ev_mul32(opcode, address, instruction, cp);
-
-	/* ARMv7-M: A5.3.15 Long multiply, long multiply accumulate, divide */
-	else if ((opcode & 0x1f800000) == 0x1b800000)
-		retval = t2ev_mul64_div(opcode, address, instruction, cp);
-
-	if (retval == ERROR_OK)
-		return retval;
-
-	/*
-	 * Thumb2 also supports coprocessor, ThumbEE, and DSP/Media (SIMD)
-	 * instructions; not yet handled here.
-	 */
-
-	if (retval == ERROR_COMMAND_SYNTAX_ERROR) {
-		instruction->type = ARM_UNDEFINED_INSTRUCTION;
-		strcpy(cp, "UNDEFINED OPCODE");
-		return ERROR_OK;
-	}
-
-	LOG_DEBUG("Can't decode 32-bit Thumb2 yet (opcode=%08" PRIx32 ")",
-			opcode);
-
-	strcpy(cp, "(32-bit Thumb2 ...)");
-	return ERROR_OK;
-}
-
-int arm_access_size(struct arm_instruction *instruction)
-{
-	if ((instruction->type == ARM_LDRB)
-	    || (instruction->type == ARM_LDRBT)
-	    || (instruction->type == ARM_LDRSB)
-	    || (instruction->type == ARM_STRB)
-	    || (instruction->type == ARM_STRBT))
-		return 1;
-	else if ((instruction->type == ARM_LDRH)
-		 || (instruction->type == ARM_LDRSH)
-		 || (instruction->type == ARM_STRH))
-		return 2;
-	else if ((instruction->type == ARM_LDR)
-		 || (instruction->type == ARM_LDRT)
-		 || (instruction->type == ARM_STR)
-		 || (instruction->type == ARM_STRT))
-		return 4;
-	else if ((instruction->type == ARM_LDRD)
-		 || (instruction->type == ARM_STRD))
-		return 8;
-	else {
-		LOG_ERROR("BUG: instruction type %i isn't a load/store instruction",
-				instruction->type);
-		return 0;
-	}
-}
+#endif /* HAVE_CAPSTONE */
diff --git a/src/target/arm_disassembler.h b/src/target/arm_disassembler.h
index 486e903e3..beecb3f30 100644
--- a/src/target/arm_disassembler.h
+++ b/src/target/arm_disassembler.h
@@ -197,9 +197,11 @@ int arm_evaluate_opcode(uint32_t opcode, uint32_t address,
 		struct arm_instruction *instruction);
 int thumb_evaluate_opcode(uint16_t opcode, uint32_t address,
 		struct arm_instruction *instruction);
-int thumb2_opcode(struct target *target, uint32_t address,
-		struct arm_instruction *instruction);
 int arm_access_size(struct arm_instruction *instruction);
+#if HAVE_CAPSTONE
+int arm_disassemble(struct command_invocation *cmd, struct target *target,
+		target_addr_t address, size_t count, bool thumb_mode);
+#endif
 
 #define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000) >> 28])
 
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 58bc3390a..7da28e349 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -942,7 +942,7 @@ COMMAND_HANDLER(handle_armv4_5_core_state_command)
 
 COMMAND_HANDLER(handle_arm_disassemble_command)
 {
-	int retval = ERROR_OK;
+#if HAVE_CAPSTONE
 	struct target *target = get_current_target(CMD_CTX);
 
 	if (target == NULL) {
@@ -952,8 +952,8 @@ COMMAND_HANDLER(handle_arm_disassemble_command)
 
 	struct arm *arm = target_to_arm(target);
 	target_addr_t address;
-	int count = 1;
-	int thumb = 0;
+	unsigned int count = 1;
+	bool thumb = false;
 
 	if (!is_arm(arm)) {
 		command_print(CMD, "current target isn't an ARM");
@@ -962,62 +962,37 @@ COMMAND_HANDLER(handle_arm_disassemble_command)
 
 	if (arm->core_type == ARM_CORE_TYPE_M_PROFILE) {
 		/* armv7m is always thumb mode */
-		thumb = 1;
+		thumb = true;
 	}
 
 	switch (CMD_ARGC) {
 		case 3:
 			if (strcmp(CMD_ARGV[2], "thumb") != 0)
-				goto usage;
-			thumb = 1;
+				return ERROR_COMMAND_SYNTAX_ERROR;
+			thumb = true;
 		/* FALL THROUGH */
 		case 2:
-			COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], count);
+			COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], count);
 		/* FALL THROUGH */
 		case 1:
 			COMMAND_PARSE_ADDRESS(CMD_ARGV[0], address);
 			if (address & 0x01) {
 				if (!thumb) {
 					command_print(CMD, "Disassemble as Thumb");
-					thumb = 1;
+					thumb = true;
 				}
 				address &= ~1;
 			}
 			break;
 		default:
-usage:
-			count = 0;
-			retval = ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	while (count-- > 0) {
-		struct arm_instruction cur_instruction;
-
-		if (thumb) {
-			/* Always use Thumb2 disassembly for best handling
-			 * of 32-bit BL/BLX, and to work with newer cores
-			 * (some ARMv6, all ARMv7) that use Thumb2.
-			 */
-			retval = thumb2_opcode(target, address,
-					&cur_instruction);
-			if (retval != ERROR_OK)
-				break;
-		} else {
-			uint32_t opcode;
-
-			retval = target_read_u32(target, address, &opcode);
-			if (retval != ERROR_OK)
-				break;
-			retval = arm_evaluate_opcode(opcode, address,
-					&cur_instruction) != ERROR_OK;
-			if (retval != ERROR_OK)
-				break;
-		}
-		command_print(CMD, "%s", cur_instruction.text);
-		address += cur_instruction.instruction_size;
+			return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-	return retval;
+	return arm_disassemble(CMD, target, address, count, thumb);
+#else
+	command_print(CMD, "capstone disassembly framework required");
+	return ERROR_FAIL;
+#endif
 }
 
 static int jim_mcrmrc(Jim_Interp *interp, int argc, Jim_Obj * const *argv)

-----------------------------------------------------------------------

Summary of changes:
 configure.ac                  |   10 +
 src/target/Makefile.am        |    6 +
 src/target/arm_disassembler.c | 1666 +++--------------------------------------
 src/target/arm_disassembler.h |    6 +-
 src/target/armv4_5.c          |   53 +-
 5 files changed, 124 insertions(+), 1617 deletions(-)


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       via  762ddcb74948852b0dfb25fcbca0965b09249a2f (commit)
      from  f2c83fade3ea7e51e5c9283aa3ff94632a41cc55 (commit)

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- Log -----------------------------------------------------------------
commit 762ddcb74948852b0dfb25fcbca0965b09249a2f
Author: Tarek BOCHKATI <tar...@gm...>
Date:   Tue Aug 11 15:23:19 2020 +0100

    cortex_m: add detection of Cortex M35P and M55
    
    Change-Id: I52599b2b09c2dc50c95d64059213c832d380ea31
    Signed-off-by: Tarek BOCHKATI <tar...@gm...>
    Reviewed-on: http://openocd.zylin.com/5799
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 4b0ea50cc..e52332dd6 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2176,11 +2176,15 @@ int cortex_m_examine(struct target *target)
 			case CORTEX_M23_PARTNO:
 				i = 23;
 				break;
-
 			case CORTEX_M33_PARTNO:
 				i = 33;
 				break;
-
+			case CORTEX_M35P_PARTNO:
+				i = 35;
+				break;
+			case CORTEX_M55_PARTNO:
+				i = 55;
+				break;
 			default:
 				armv7m->arm.is_armv8m = false;
 				break;
@@ -2213,7 +2217,7 @@ int cortex_m_examine(struct target *target)
 				LOG_DEBUG("Cortex-M%d floating point feature FPv4_SP found", i);
 				armv7m->fp_feature = FPv4_SP;
 			}
-		} else if (i == 7 || i == 33) {
+		} else if (i == 7 || i == 33 || i == 35 || i == 55) {
 			target_read_u32(target, MVFR0, &mvfr0);
 			target_read_u32(target, MVFR1, &mvfr1);
 
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 354532823..415a6c22f 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -44,6 +44,8 @@
 
 #define CORTEX_M23_PARTNO	0xD200
 #define CORTEX_M33_PARTNO	0xD210
+#define CORTEX_M35P_PARTNO	0xD310
+#define CORTEX_M55_PARTNO	0xD220
 
 /* Debug Control Block */
 #define DCB_DHCSR	0xE000EDF0

-----------------------------------------------------------------------

Summary of changes:
 src/target/cortex_m.c | 10 +++++++---
 src/target/cortex_m.h |  2 ++
 2 files changed, 9 insertions(+), 3 deletions(-)


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       via  6e339478999bab6ae029a3b24fa79ddc698e1a4f (commit)
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- Log -----------------------------------------------------------------
commit f2c83fade3ea7e51e5c9283aa3ff94632a41cc55
Author: Tarek BOCHKATI <tar...@gm...>
Date:   Tue Aug 11 14:06:04 2020 +0100

    cortex_m: read and display core security state
    
    Change-Id: I0fce3c66af7e98df2dc2258daf0d6af661e29ae7
    Signed-off-by: Laurent LEMELE <lau...@st...>
    Signed-off-by: Tarek BOCHKATI <tar...@gm...>
    Reviewed-on: http://openocd.zylin.com/5798
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/arm.h b/src/target/arm.h
index 3450260f0..d97a95edf 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -197,6 +197,9 @@ struct arm {
 	/** Flag reporting armv6m based core. */
 	bool is_armv6m;
 
+	/** Flag reporting armv8m based core. */
+	bool is_armv8m;
+
 	/** Floating point or VFP version, 0 if disabled. */
 	int arm_vfp_version;
 
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 62e08468d..4b0ea50cc 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -502,6 +502,18 @@ static int cortex_m_debug_entry(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 
+	/* examine PE security state */
+	bool secure_state = false;
+	if (armv7m->arm.is_armv8m) {
+		uint32_t dscsr;
+
+		retval = mem_ap_read_u32(armv7m->debug_ap, DCB_DSCSR, &dscsr);
+		if (retval != ERROR_OK)
+			return retval;
+
+		secure_state = (dscsr & DSCSR_CDS) == DSCSR_CDS;
+	}
+
 	/* Examine target state and mode
 	 * First load register accessible through core debug port */
 	int num_regs = arm->core_cache->num_regs;
@@ -548,9 +560,10 @@ static int cortex_m_debug_entry(struct target *target)
 	if (armv7m->exception_number)
 		cortex_m_examine_exception_reason(target);
 
-	LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
+	LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s",
 		arm_mode_name(arm->core_mode),
 		buf_get_u32(arm->pc->value, 0, 32),
+		secure_state ? "Secure" : "Non-Secure",
 		target_state_name(target));
 
 	if (armv7m->post_debug_entry) {
@@ -2156,6 +2169,9 @@ int cortex_m_examine(struct target *target)
 		/* Get CPU Type */
 		i = (cpuid >> 4) & 0xf;
 
+		/* Check if it is an ARMv8-M core */
+		armv7m->arm.is_armv8m = true;
+
 		switch (cpuid & ARM_CPUID_PARTNO_MASK) {
 			case CORTEX_M23_PARTNO:
 				i = 23;
@@ -2166,6 +2182,7 @@ int cortex_m_examine(struct target *target)
 				break;
 
 			default:
+				armv7m->arm.is_armv8m = false;
 				break;
 		}
 
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 794eda4c7..354532823 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -50,6 +50,7 @@
 #define DCB_DCRSR	0xE000EDF4
 #define DCB_DCRDR	0xE000EDF8
 #define DCB_DEMCR	0xE000EDFC
+#define DCB_DSCSR	0xE000EE08
 
 #define DCRSR_WnR	BIT(16)
 
@@ -114,6 +115,9 @@
 #define VC_MMERR		BIT(4)
 #define VC_CORERESET	BIT(0)
 
+/* DCB_DSCSR bit and field definitions */
+#define DSCSR_CDS		BIT(16)
+
 /* NVIC registers */
 #define NVIC_ICTR		0xE000E004
 #define NVIC_ISE0		0xE000E100

commit 6e339478999bab6ae029a3b24fa79ddc698e1a4f
Author: Tarek BOCHKATI <tar...@gm...>
Date:   Tue Aug 11 12:56:36 2020 +0100

    armv8-m: add SecureFault exception
    
    Change-Id: I4e1963631e834b6334bc917e956c2db4464b7b08
    Signed-off-by: Laurent LEMELE <lau...@st...>
    Signed-off-by: Tarek BOCHKATI <tar...@gm...>
    Reviewed-on: http://openocd.zylin.com/5797
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 017d693ce..ea6ee6117 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -48,7 +48,7 @@
 
 static const char * const armv7m_exception_strings[] = {
 	"", "Reset", "NMI", "HardFault",
-	"MemManage", "BusFault", "UsageFault", "RESERVED",
+	"MemManage", "BusFault", "UsageFault", "SecureFault",
 	"RESERVED", "RESERVED", "RESERVED", "SVCall",
 	"DebugMonitor", "RESERVED", "PendSV", "SysTick"
 };
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 5ea928a32..62e08468d 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -445,6 +445,14 @@ static int cortex_m_examine_exception_reason(struct target *target)
 			if (retval != ERROR_OK)
 				return retval;
 			break;
+		case 7:	/* Secure Fault */
+			retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFSR, &except_sr);
+			if (retval != ERROR_OK)
+				return retval;
+			retval = mem_ap_read_u32(armv7m->debug_ap, NVIC_SFAR, &except_ar);
+			if (retval != ERROR_OK)
+				return retval;
+			break;
 		case 11:	/* SVCall */
 			break;
 		case 12:	/* Debug Monitor */
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index a767f93c5..794eda4c7 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -114,6 +114,7 @@
 #define VC_MMERR		BIT(4)
 #define VC_CORERESET	BIT(0)
 
+/* NVIC registers */
 #define NVIC_ICTR		0xE000E004
 #define NVIC_ISE0		0xE000E100
 #define NVIC_ICSR		0xE000ED04
@@ -127,6 +128,8 @@
 #define NVIC_DFSR		0xE000ED30
 #define NVIC_MMFAR		0xE000ED34
 #define NVIC_BFAR		0xE000ED38
+#define NVIC_SFSR		0xE000EDE4
+#define NVIC_SFAR		0xE000EDE8
 
 /* NVIC_AIRCR bits */
 #define AIRCR_VECTKEY		(0x5FAul << 16)

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm.h      |  3 +++
 src/target/armv7m.c   |  2 +-
 src/target/cortex_m.c | 27 ++++++++++++++++++++++++++-
 src/target/cortex_m.h |  7 +++++++
 4 files changed, 37 insertions(+), 2 deletions(-)


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- Log -----------------------------------------------------------------
commit c20f65b63202bcf2735dbf1e8085fa978b6104c5
Author: Tarek BOCHKATI <tar...@gm...>
Date:   Tue Jun 2 22:03:18 2020 +0100

    GitHub: add workflow to provide an openocd snapshot binaries for win32
    
    This change could be used within OpenOCD GitHub forks.
    
    Once workflow actions are enabled in the GitHub project, this workflow
    will be run automatically on each push into OpenOCD.
    
    This workflow will provide a neutral build of openocd for win32, then
    the package will be available for download in Actions section.
    Note: the artifact will be deleted after 90 day (actual GitHub rules)
    
    If the push is a tag, the generated package will be uploaded to release
    pane under the corresponding release, and it will resides forever.
    
    The built openocd enables libusb1, hidapi and libftdi adapters,
    and could be extended to cover more adapters and Oses
    
    PS: ./contrib/cross-build.sh updated to build libftdi from source like
    libusb1 and hidapi.
    
    Change-Id: I290c8aa14a12548e2dcb6a0eee456430ea44ab9f
    Signed-off-by: Tarek BOCHKATI <tar...@gm...>
    Reviewed-on: http://openocd.zylin.com/5594
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/.github/workflows/snapshot.yml b/.github/workflows/snapshot.yml
new file mode 100644
index 000000000..2b73f9c8c
--- /dev/null
+++ b/.github/workflows/snapshot.yml
@@ -0,0 +1,92 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Copyright (C) 2020 by Tarek BOUCHKATI <tar...@gm...>
+
+on: push
+
+name: OpenOCD Snapshot
+
+jobs:
+  package:
+    runs-on: [ubuntu-18.04]
+    env:
+      DL_DIR: ../downloads
+      BUILD_DIR: ../build
+    steps:
+      - name: Install needed packages
+        run: sudo apt-get install autotools-dev autoconf automake libtool pkg-config cmake texinfo texlive g++-mingw-w64-i686
+      - uses: actions/checkout@v1
+      - run: ./bootstrap
+      - name: Prepare libusb1
+        env:
+          LIBUSB1_VER: 1.0.23
+        run: |
+          mkdir -p $DL_DIR && cd $DL_DIR
+          wget "https://github.com/libusb/libusb/releases/download/v${LIBUSB1_VER}/libusb-${LIBUSB1_VER}.tar.bz2"
+          tar -xjf libusb-${LIBUSB1_VER}.tar.bz2
+          echo "::set-env name=LIBUSB1_SRC::$PWD/libusb-${LIBUSB1_VER}"
+      - name: Prepare hidapi
+        env:
+          HIDAPI_VER: 0.9.0
+        run: |
+          mkdir -p $DL_DIR && cd $DL_DIR
+          wget "https://github.com/libusb/hidapi/archive/hidapi-${HIDAPI_VER}.tar.gz"
+          tar -xzf hidapi-${HIDAPI_VER}.tar.gz
+          cd hidapi-hidapi-${HIDAPI_VER}
+          ./bootstrap
+          echo "::set-env name=HIDAPI_SRC::$PWD"
+      - name: Prepare libftdi
+        env:
+          LIBFTDI_VER: 1.4
+        run: |
+          mkdir -p $DL_DIR && cd $DL_DIR
+          wget "http://www.intra2net.com/en/developer/libftdi/download/libftdi1-${LIBFTDI_VER}.tar.bz2"
+          tar -xjf libftdi1-${LIBFTDI_VER}.tar.bz2
+          echo "::set-env name=LIBFTDI_SRC::$PWD/libftdi1-${LIBFTDI_VER}"
+      - name: Package OpenOCD for windows
+        env:
+          MAKE_JOBS: 2
+          HOST: i686-w64-mingw32
+          LIBUSB1_CONFIG: --enable-shared --enable-static
+          HIDAPI_CONFIG: --enable-shared --disable-static --disable-testgui
+          LIBFTDI_CONFIG: "-DCMAKE_TOOLCHAIN_FILE='${{ env.LIBFTDI_SRC }}/cmake/Toolchain-i686-w64-mingw32.cmake' -DBUILD_TESTS:BOOL=off -DFTDIPP:BOOL=off -DPYTHON_BINDINGS:BOOL=off -DEXAMPLES:BOOL=off -DDOCUMENTATION:BOOL=off -DFTDI_EEPROM:BOOL=off"
+        run: |
+          # set snapshot tag
+          OPENOCD_TAG="`git tag --points-at HEAD`"
+          [ -z $OPENOCD_TAG ] && OPENOCD_TAG="`git rev-parse --short HEAD`"
+          # set env and call cross-build.sh
+          export OPENOCD_TAG=$OPENOCD_TAG
+          export OPENOCD_SRC=$PWD
+          export OPENOCD_CONFIG=""
+          mkdir -p $BUILD_DIR &&  cd $BUILD_DIR
+          bash $OPENOCD_SRC/contrib/cross-build.sh $HOST
+          # add missing dlls
+          cd $HOST-root/usr
+          cp `$HOST-gcc --print-file-name=libwinpthread-1.dll` ./bin/
+          cp `$HOST-gcc --print-file-name=libgcc_s_sjlj-1.dll` ./bin/
+          # prepare the artifact
+          ARTIFACT="openocd-${OPENOCD_TAG}-${HOST}.tar.gz"
+          tar -czf $ARTIFACT *
+          echo "::set-env name=ARTIFACT_NAME::$ARTIFACT"
+          echo "::set-env name=ARTIFACT_PATH::$PWD/$ARTIFACT"
+      - name: Publish OpenOCD packaged for windows
+        uses: actions/upload-artifact@v1
+        with:
+          name: ${{ env.ARTIFACT_NAME }}
+          path: ${{ env.ARTIFACT_PATH }}
+      - name: Get the upload URL for a release
+        id: get_release
+        if: startsWith(github.ref, 'refs/tags/')
+        uses: bruceadams/get-release@v1.2.0
+        env:
+          GITHUB_TOKEN: ${{ github.token }}
+      - name: Release OpenOCD packaged for windows
+        if: startsWith(github.ref, 'refs/tags/')
+        uses: actions/upload-release-asset@v1
+        env:
+          GITHUB_TOKEN: ${{ secrets.GITHUB_TOKEN }}
+        with:
+          upload_url: ${{ steps.get_release.outputs.upload_url }}
+          asset_path: ${{ env.ARTIFACT_PATH }}
+          asset_name: ${{ env.ARTIFACT_NAME }}
+          asset_content_type: application/gzip
diff --git a/contrib/cross-build.sh b/contrib/cross-build.sh
index d508bed47..821d48ec7 100755
--- a/contrib/cross-build.sh
+++ b/contrib/cross-build.sh
@@ -15,8 +15,8 @@
 #
 # This script is probably more useful as a reference than as a complete build
 # tool but for some configurations it may be usable as-is. It only cross-
-# builds libusb-1.0 from source, but the script can be extended to build other
-# prerequisites in a similar manner.
+# builds libusb-1.0, hidapi and libftdi from source, but the script can be
+# extended to build other prerequisites in a similar manner.
 #
 # Usage:
 # export LIBUSB1_SRC=/path/to/libusb-1.0
@@ -36,17 +36,20 @@ WORK_DIR=$PWD
 
 ## Source code paths, customize as necessary
 : ${OPENOCD_SRC:="`dirname "$0"`/.."}
-: ${LIBUSB1_SRC:=/path/to/libusb}
+: ${LIBUSB1_SRC:=/path/to/libusb1}
 : ${HIDAPI_SRC:=/path/to/hidapi}
+: ${LIBFTDI_SRC:=/path/to/libftdi}
 
 OPENOCD_SRC=`readlink -m $OPENOCD_SRC`
 LIBUSB1_SRC=`readlink -m $LIBUSB1_SRC`
 HIDAPI_SRC=`readlink -m $HIDAPI_SRC`
+LIBFTDI_SRC=`readlink -m $LIBFTDI_SRC`
 
 HOST_TRIPLET=$1
 BUILD_DIR=$WORK_DIR/$HOST_TRIPLET-build
 LIBUSB1_BUILD_DIR=$BUILD_DIR/libusb1
 HIDAPI_BUILD_DIR=$BUILD_DIR/hidapi
+LIBFTDI_BUILD_DIR=$BUILD_DIR/libftdi
 OPENOCD_BUILD_DIR=$BUILD_DIR/openocd
 
 ## Root of host file tree
@@ -55,8 +58,12 @@ SYSROOT=$WORK_DIR/$HOST_TRIPLET-root
 ## Install location within host file tree
 : ${PREFIX=/usr}
 
+## Make parallel jobs
+: ${MAKE_JOBS:=1}
+
 ## OpenOCD-only install dir for packaging
-PACKAGE_DIR=$WORK_DIR/openocd_`git --git-dir=$OPENOCD_SRC/.git describe`_$HOST_TRIPLET
+: ${OPENOCD_TAG:=`git --git-dir=$OPENOCD_SRC/.git describe --tags`}
+PACKAGE_DIR=$WORK_DIR/openocd_${OPENOCD_TAG}_${HOST_TRIPLET}
 
 #######
 
@@ -86,13 +93,15 @@ rm -rf $SYSROOT $BUILD_DIR
 mkdir -p $SYSROOT
 
 # libusb-1.0 build & install into sysroot
-mkdir -p $LIBUSB1_BUILD_DIR
-cd $LIBUSB1_BUILD_DIR
-$LIBUSB1_SRC/configure --build=`$LIBUSB1_SRC/config.guess` --host=$HOST_TRIPLET \
---with-sysroot=$SYSROOT --prefix=$PREFIX \
-$LIBUSB1_CONFIG
-make
-make install DESTDIR=$SYSROOT
+if [ -d $LIBUSB1_SRC ] ; then
+  mkdir -p $LIBUSB1_BUILD_DIR
+  cd $LIBUSB1_BUILD_DIR
+  $LIBUSB1_SRC/configure --build=`$LIBUSB1_SRC/config.guess` --host=$HOST_TRIPLET \
+  --with-sysroot=$SYSROOT --prefix=$PREFIX \
+  $LIBUSB1_CONFIG
+  make -j $MAKE_JOBS
+  make install DESTDIR=$SYSROOT
+fi
 
 # hidapi build & install into sysroot
 if [ -d $HIDAPI_SRC ] ; then
@@ -101,7 +110,22 @@ if [ -d $HIDAPI_SRC ] ; then
   $HIDAPI_SRC/configure --build=`$HIDAPI_SRC/config.guess` --host=$HOST_TRIPLET \
     --with-sysroot=$SYSROOT --prefix=$PREFIX \
     $HIDAPI_CONFIG
-  make
+  make -j $MAKE_JOBS
+  make install DESTDIR=$SYSROOT
+fi
+
+# libftdi build & install into sysroot
+if [ -d $LIBFTDI_SRC ] ; then
+  mkdir -p $LIBFTDI_BUILD_DIR
+  cd $LIBFTDI_BUILD_DIR
+  # libftdi requires libusb1 static libraries, granted by:
+  # export LIBUSB1_CONFIG="--enable-static ..."
+  cmake $LIBFTDI_CONFIG \
+    -DLIBUSB_INCLUDE_DIR=${SYSROOT}${PREFIX}/include/libusb-1.0 \
+    -DLIBUSB_LIBRARIES=${SYSROOT}${PREFIX}/lib/libusb-1.0.a \
+    -DCMAKE_INSTALL_PREFIX=${PREFIX} \
+    -DPKG_CONFIG_EXECUTABLE=`which pkg-config` \
+    $LIBFTDI_SRC
   make install DESTDIR=$SYSROOT
 fi
 
@@ -111,9 +135,10 @@ cd $OPENOCD_BUILD_DIR
 $OPENOCD_SRC/configure --build=`$OPENOCD_SRC/config.guess` --host=$HOST_TRIPLET \
 --with-sysroot=$SYSROOT --prefix=$PREFIX \
 $OPENOCD_CONFIG
-make
-make install DESTDIR=$SYSROOT
+make -j $MAKE_JOBS
+make install-strip DESTDIR=$SYSROOT
 
 # Separate OpenOCD install w/o dependencies. OpenOCD will have to be linked
 # statically or have dependencies packaged/installed separately.
-make install DESTDIR=$PACKAGE_DIR
+make install-strip DESTDIR=$PACKAGE_DIR
+

-----------------------------------------------------------------------

Summary of changes:
 .github/workflows/snapshot.yml | 92 ++++++++++++++++++++++++++++++++++++++++++
 contrib/cross-build.sh         | 55 ++++++++++++++++++-------
 2 files changed, 132 insertions(+), 15 deletions(-)
 create mode 100644 .github/workflows/snapshot.yml


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- Log -----------------------------------------------------------------
commit 3934483429b77525f25922787933fb7ee3e73a0f
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Aug 17 09:58:58 2020 +0200

    target: avoid checking for non NULL pointer to free it
    
    The function free() can be called with a NULL pointer as argument,
    no need to check the argument before. If the pointer is NULL, no
    operation is performed by free().
    
    Remove the occurrences of pattern:
            if (ptr)
                    free(ptr);
    
    In target/openrisc/jsp_server.c, an error is logged if the ptr was
    already NULL. This cannot happen since the pointer was already
    referenced few lines before and openocd would have been already
    SIGSEGV in that case, so remove the log.
    
    Change-Id: I290a32e6d4deab167676af4ddc83523c830ae49e
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5809
    Tested-by: jenkins

diff --git a/src/target/image.c b/src/target/image.c
index 64d4d52c3..8160e5f92 100644
--- a/src/target/image.c
+++ b/src/target/image.c
@@ -984,40 +984,30 @@ void image_close(struct image *image)
 
 		fileio_close(image_ihex->fileio);
 
-		if (image_ihex->buffer) {
-			free(image_ihex->buffer);
-			image_ihex->buffer = NULL;
-		}
+		free(image_ihex->buffer);
+		image_ihex->buffer = NULL;
 	} else if (image->type == IMAGE_ELF) {
 		struct image_elf *image_elf = image->type_private;
 
 		fileio_close(image_elf->fileio);
 
-		if (image_elf->header) {
-			free(image_elf->header);
-			image_elf->header = NULL;
-		}
+		free(image_elf->header);
+		image_elf->header = NULL;
 
-		if (image_elf->segments) {
-			free(image_elf->segments);
-			image_elf->segments = NULL;
-		}
+		free(image_elf->segments);
+		image_elf->segments = NULL;
 	} else if (image->type == IMAGE_MEMORY) {
 		struct image_memory *image_memory = image->type_private;
 
-		if (image_memory->cache) {
-			free(image_memory->cache);
-			image_memory->cache = NULL;
-		}
+		free(image_memory->cache);
+		image_memory->cache = NULL;
 	} else if (image->type == IMAGE_SRECORD) {
 		struct image_mot *image_mot = image->type_private;
 
 		fileio_close(image_mot->fileio);
 
-		if (image_mot->buffer) {
-			free(image_mot->buffer);
-			image_mot->buffer = NULL;
-		}
+		free(image_mot->buffer);
+		image_mot->buffer = NULL;
 	} else if (image->type == IMAGE_BUILDER) {
 		int i;
 
@@ -1027,15 +1017,11 @@ void image_close(struct image *image)
 		}
 	}
 
-	if (image->type_private) {
-		free(image->type_private);
-		image->type_private = NULL;
-	}
+	free(image->type_private);
+	image->type_private = NULL;
 
-	if (image->sections) {
-		free(image->sections);
-		image->sections = NULL;
-	}
+	free(image->sections);
+	image->sections = NULL;
 }
 
 int image_calculate_checksum(uint8_t *buffer, uint32_t nbytes, uint32_t *checksum)
diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c
index 81be70d12..9bac40eb0 100644
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@@ -346,8 +346,7 @@ void pracc_add_li32(struct pracc_queue_info *ctx, uint32_t reg_num, uint32_t dat
 
 inline void pracc_queue_free(struct pracc_queue_info *ctx)
 {
-	if (ctx->pracc_list != NULL)
-		free(ctx->pracc_list);
+	free(ctx->pracc_list);
 }
 
 int mips32_pracc_queue_exec(struct mips_ejtag *ejtag_info, struct pracc_queue_info *ctx,
@@ -550,8 +549,7 @@ int mips32_pracc_read_mem(struct mips_ejtag *ejtag_info, uint32_t addr, int size
 	}
 exit:
 	pracc_queue_free(&ctx);
-	if (data != NULL)
-		free(data);
+	free(data);
 	return ctx.retval;
 }
 
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 85eea932d..52b4b3217 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -1072,7 +1072,7 @@ static int mips_m4k_read_memory(struct target *target, target_addr_t address,
 		}
 	}
 
-	if ((size > 1) && (t != NULL))
+	if (size > 1)
 		free(t);
 
 	return retval;
@@ -1135,8 +1135,7 @@ static int mips_m4k_write_memory(struct target *target, target_addr_t address,
 	else
 		retval = mips32_dmaacc_write_mem(ejtag_info, address, size, count, buffer);
 
-	if (t != NULL)
-		free(t);
+	free(t);
 
 	if (ERROR_OK != retval)
 		return retval;
@@ -1261,8 +1260,7 @@ static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t addre
 	retval = mips32_pracc_fastdata_xfer(ejtag_info, mips32->fast_data_area, write_t, address,
 			count, t);
 
-	if (t != NULL)
-		free(t);
+	free(t);
 
 	if (retval != ERROR_OK)
 		LOG_ERROR("Fastdata access Failed");
diff --git a/src/target/nds32.c b/src/target/nds32.c
index 0d1a23a8d..487e19c6a 100644
--- a/src/target/nds32.c
+++ b/src/target/nds32.c
@@ -1462,8 +1462,7 @@ int nds32_add_software_breakpoint(struct target *target,
 		break_insn = NDS32_BREAK_32;
 	}
 
-	if (breakpoint->orig_instr != NULL)
-		free(breakpoint->orig_instr);
+	free(breakpoint->orig_instr);
 
 	breakpoint->orig_instr = malloc(breakpoint->length);
 	memcpy(breakpoint->orig_instr, &data, breakpoint->length);
@@ -2334,10 +2333,8 @@ int nds32_get_gdb_fileio_info(struct target *target, struct gdb_fileio_info *fil
 	LOG_DEBUG("hit syscall ID: 0x%" PRIx32, syscall_id);
 
 	/* free previous identifier storage */
-	if (NULL != fileio_info->identifier) {
-		free(fileio_info->identifier);
-		fileio_info->identifier = NULL;
-	}
+	free(fileio_info->identifier);
+	fileio_info->identifier = NULL;
 
 	uint32_t reg_r0, reg_r1, reg_r2;
 	nds32_get_mapped_reg(nds32, R0, &reg_r0);
diff --git a/src/target/openrisc/jsp_server.c b/src/target/openrisc/jsp_server.c
index f28815df9..1d05944bc 100644
--- a/src/target/openrisc/jsp_server.c
+++ b/src/target/openrisc/jsp_server.c
@@ -190,12 +190,8 @@ static int jsp_connection_closed(struct connection *connection)
 	if (ERROR_OK != retval)
 		return retval;
 
-	if (connection->priv) {
-		free(connection->priv);
-		connection->priv = NULL;
-	} else
-		LOG_ERROR("BUG: connection->priv == NULL");
-
+	free(connection->priv);
+	connection->priv = NULL;
 	return ERROR_OK;
 }
 
diff --git a/src/target/openrisc/or1k.c b/src/target/openrisc/or1k.c
index 93fb9c6a3..d685359be 100644
--- a/src/target/openrisc/or1k.c
+++ b/src/target/openrisc/or1k.c
@@ -943,8 +943,7 @@ static int or1k_add_breakpoint(struct target *target,
 		return retval;
 	}
 
-	if (breakpoint->orig_instr != NULL)
-		free(breakpoint->orig_instr);
+	free(breakpoint->orig_instr);
 
 	breakpoint->orig_instr = malloc(breakpoint->length);
 	memcpy(breakpoint->orig_instr, &data, breakpoint->length);
diff --git a/src/target/openrisc/or1k_du_adv.c b/src/target/openrisc/or1k_du_adv.c
index afc773f56..31b248776 100644
--- a/src/target/openrisc/or1k_du_adv.c
+++ b/src/target/openrisc/or1k_du_adv.c
@@ -975,8 +975,7 @@ static int or1k_adv_jtag_write_memory(struct or1k_jtag *jtag_info,
 					     size, blocks_this_round,
 					     block_count_address);
 		if (retval != ERROR_OK) {
-			if (t != NULL)
-				free(t);
+			free(t);
 			return retval;
 		}
 
@@ -985,9 +984,7 @@ static int or1k_adv_jtag_write_memory(struct or1k_jtag *jtag_info,
 		block_count_buffer += size * MAX_BURST_SIZE;
 	}
 
-	if (t != NULL)
-		free(t);
-
+	free(t);
 	return ERROR_OK;
 }
 
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index afd0cc815..de2f095be 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -276,8 +276,7 @@ static void riscv_free_registers(struct target *target)
 	/* Free the shared structure use for most registers. */
 	if (target->reg_cache) {
 		if (target->reg_cache->reg_list) {
-			if (target->reg_cache->reg_list[0].arch_info)
-				free(target->reg_cache->reg_list[0].arch_info);
+			free(target->reg_cache->reg_list[0].arch_info);
 			/* Free the ones we allocated separately. */
 			for (unsigned i = GDB_REGNO_COUNT; i < target->reg_cache->num_regs; i++)
 				free(target->reg_cache->reg_list[i].arch_info);
@@ -1558,8 +1557,7 @@ int parse_ranges(range_t **ranges, const char **argv)
 		}
 
 		if (pass == 0) {
-			if (*ranges)
-				free(*ranges);
+			free(*ranges);
 			*ranges = calloc(range + 2, sizeof(range_t));
 		} else {
 			(*ranges)[range].low = 1;
@@ -2487,8 +2485,7 @@ int riscv_init_registers(struct target *target)
 		calloc(target->reg_cache->num_regs, sizeof(struct reg));
 
 	const unsigned int max_reg_name_len = 12;
-	if (info->reg_names)
-		free(info->reg_names);
+	free(info->reg_names);
 	info->reg_names =
 		calloc(target->reg_cache->num_regs, max_reg_name_len);
 	char *reg_name = info->reg_names;
diff --git a/src/target/target.c b/src/target/target.c
index a918b3acf..fa609efdb 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -1788,10 +1788,8 @@ static void target_split_working_area(struct working_area *area, uint32_t size)
 
 		/* If backup memory was allocated to this area, it has the wrong size
 		 * now so free it and it will be reallocated if/when needed */
-		if (area->backup) {
-			free(area->backup);
-			area->backup = NULL;
-		}
+		free(area->backup);
+		area->backup = NULL;
 	}
 }
 
@@ -1811,16 +1809,13 @@ static void target_merge_working_areas(struct target *target)
 			/* Remove the last */
 			struct working_area *to_be_freed = c->next;
 			c->next = c->next->next;
-			if (to_be_freed->backup)
-				free(to_be_freed->backup);
+			free(to_be_freed->backup);
 			free(to_be_freed);
 
 			/* If backup memory was allocated to the remaining area, it's has
 			 * the wrong size now */
-			if (c->backup) {
-				free(c->backup);
-				c->backup = NULL;
-			}
+			free(c->backup);
+			c->backup = NULL;
 		} else {
 			c = c->next;
 		}
@@ -2050,8 +2045,7 @@ static void target_destroy(struct target *target)
 	if (target->type->deinit_target)
 		target->type->deinit_target(target);
 
-	if (target->semihosting)
-		free(target->semihosting);
+	free(target->semihosting);
 
 	jtag_unregister_event_callback(jtag_enable_callback, target);
 
@@ -5833,11 +5827,8 @@ static struct FastLoad *fastload;
 static void free_fastload(void)
 {
 	if (fastload != NULL) {
-		int i;
-		for (i = 0; i < fastload_num; i++) {
-			if (fastload[i].data)
-				free(fastload[i].data);
-		}
+		for (int i = 0; i < fastload_num; i++)
+			free(fastload[i].data);
 		free(fastload);
 		fastload = NULL;
 	}
diff --git a/src/target/trace.c b/src/target/trace.c
index 943bf1f4f..f2ceb03d9 100644
--- a/src/target/trace.c
+++ b/src/target/trace.c
@@ -62,10 +62,9 @@ COMMAND_HANDLER(handle_trace_point_command)
 	}
 
 	if (!strcmp(CMD_ARGV[0], "clear")) {
-		if (trace->trace_points) {
-			free(trace->trace_points);
-			trace->trace_points = NULL;
-		}
+		free(trace->trace_points);
+		trace->trace_points = NULL;
+
 		trace->num_trace_points = 0;
 		trace->trace_points_size = 0;
 
@@ -102,8 +101,7 @@ COMMAND_HANDLER(handle_trace_history_command)
 			return ERROR_OK;
 		}
 
-		if (trace->trace_history)
-			free(trace->trace_history);
+		free(trace->trace_history);
 
 		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], trace->trace_history_size);
 		trace->trace_history = malloc(sizeof(uint32_t) * trace->trace_history_size);
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 770b3259e..6d1d426d5 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -1110,8 +1110,7 @@ static void xscale_free_trace_data(struct xscale_common *xscale)
 	struct xscale_trace_data *td = xscale->trace.data;
 	while (td) {
 		struct xscale_trace_data *next_td = td->next;
-		if (td->entries)
-			free(td->entries);
+		free(td->entries);
 		free(td);
 		td = next_td;
 	}

-----------------------------------------------------------------------

Summary of changes:
 src/target/image.c                | 42 +++++++++++++--------------------------
 src/target/mips32_pracc.c         |  6 ++----
 src/target/mips_m4k.c             |  8 +++-----
 src/target/nds32.c                |  9 +++------
 src/target/openrisc/jsp_server.c  |  8 ++------
 src/target/openrisc/or1k.c        |  3 +--
 src/target/openrisc/or1k_du_adv.c |  7 ++-----
 src/target/riscv/riscv.c          |  9 +++------
 src/target/target.c               | 25 ++++++++---------------
 src/target/trace.c                | 10 ++++------
 src/target/xscale.c               |  3 +--
 11 files changed, 43 insertions(+), 87 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1403-g0dad8cbfe

[OpenOCD-Gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  0dad8cbfe9e1d43cdcabbc8eb4e2809b7b21381d (commit)
      from  24db985f602bbe21ee4d10147937ed897f28a555 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 0dad8cbfe9e1d43cdcabbc8eb4e2809b7b21381d
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Apr 24 22:59:13 2020 +0200

    drivers/buspirate: remove empty lines at end of file
    
    Change split from http://openocd.zylin.com/5172/ to avoid
    conflicts with other pending changes in gerrit.
    
    Change-Id: Id3e21c92b3da7ddce7b00664280da2143c06f172
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5604
    Tested-by: jenkins

diff --git a/src/jtag/drivers/buspirate.c b/src/jtag/drivers/buspirate.c
index dc38c5db0..12bb81e39 100644
--- a/src/jtag/drivers/buspirate.c
+++ b/src/jtag/drivers/buspirate.c
@@ -1536,5 +1536,3 @@ static int buspirate_swd_run_queue(void)
 	LOG_DEBUG("SWD queue return value: %02x", retval);
 	return retval;
 }
-
-

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/buspirate.c | 2 --
 1 file changed, 2 deletions(-)


hooks/post-receive
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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1402-g24db985f6

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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  24db985f602bbe21ee4d10147937ed897f28a555 (commit)
      from  a098a14eb53131871469a9c32b206b0dc55ef237 (commit)

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- Log -----------------------------------------------------------------
commit 24db985f602bbe21ee4d10147937ed897f28a555
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Aug 17 10:05:11 2020 +0200

    jtag: avoid checking for non NULL pointer to free it
    
    The function free() can be called with a NULL pointer as argument,
    no need to check the argument before. If the pointer is NULL, no
    operation is performed by free().
    
    Remove the occurrences of pattern:
            if (ptr)
                    free(ptr);
    
    Change-Id: I2938e333bd1eac5218bd67aefb9d8f373da017a8
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5810
    Tested-by: jenkins

diff --git a/src/jtag/aice/aice_usb.c b/src/jtag/aice/aice_usb.c
index 5a200eb77..7144632df 100644
--- a/src/jtag/aice/aice_usb.c
+++ b/src/jtag/aice/aice_usb.c
@@ -2537,15 +2537,9 @@ static int aice_usb_close(void)
 {
 	jtag_libusb_close(aice_handler.usb_handle);
 
-	if (custom_srst_script)
-		free(custom_srst_script);
-
-	if (custom_trst_script)
-		free(custom_trst_script);
-
-	if (custom_restart_script)
-		free(custom_restart_script);
-
+	free(custom_srst_script);
+	free(custom_trst_script);
+	free(custom_restart_script);
 	return ERROR_OK;
 }
 
diff --git a/src/jtag/drivers/amt_jtagaccel.c b/src/jtag/drivers/amt_jtagaccel.c
index 81721cbb4..e9ff8dfa1 100644
--- a/src/jtag/drivers/amt_jtagaccel.c
+++ b/src/jtag/drivers/amt_jtagaccel.c
@@ -370,8 +370,7 @@ static int amt_jtagaccel_execute_queue(void)
 				amt_jtagaccel_scan(cmd->cmd.scan->ir_scan, type, buffer, scan_size);
 				if (jtag_read_buffer(buffer, cmd->cmd.scan) != ERROR_OK)
 					retval = ERROR_JTAG_QUEUE_FAILED;
-				if (buffer)
-					free(buffer);
+				free(buffer);
 				break;
 			case JTAG_SLEEP:
 				LOG_DEBUG_IO("sleep %" PRIu32, cmd->cmd.sleep->us);
diff --git a/src/jtag/drivers/arm-jtag-ew.c b/src/jtag/drivers/arm-jtag-ew.c
index 60b119548..40d52acb9 100644
--- a/src/jtag/drivers/arm-jtag-ew.c
+++ b/src/jtag/drivers/arm-jtag-ew.c
@@ -664,8 +664,7 @@ static int armjtagew_tap_execute(void)
 					return ERROR_JTAG_QUEUE_FAILED;
 				}
 
-				if (pending_scan_result->buffer != NULL)
-					free(pending_scan_result->buffer);
+				free(pending_scan_result->buffer);
 			}
 		} else {
 			LOG_ERROR("armjtagew_tap_execute, wrong result %d, expected %d",
diff --git a/src/jtag/drivers/bitbang.c b/src/jtag/drivers/bitbang.c
index b33e87f2a..df1d601b8 100644
--- a/src/jtag/drivers/bitbang.c
+++ b/src/jtag/drivers/bitbang.c
@@ -358,8 +358,7 @@ int bitbang_execute_queue(void)
 					return ERROR_FAIL;
 				if (jtag_read_buffer(buffer, cmd->cmd.scan) != ERROR_OK)
 					retval = ERROR_JTAG_QUEUE_FAILED;
-				if (buffer)
-					free(buffer);
+				free(buffer);
 				break;
 			case JTAG_SLEEP:
 				LOG_DEBUG_IO("sleep %" PRIu32, cmd->cmd.sleep->us);
diff --git a/src/jtag/drivers/buspirate.c b/src/jtag/drivers/buspirate.c
index 2483b4346..dc38c5db0 100644
--- a/src/jtag/drivers/buspirate.c
+++ b/src/jtag/drivers/buspirate.c
@@ -352,10 +352,8 @@ static int buspirate_quit(void)
 
 	buspirate_serial_close(buspirate_fd);
 
-	if (buspirate_port) {
-		free(buspirate_port);
-		buspirate_port = NULL;
-	}
+	free(buspirate_port);
+	buspirate_port = NULL;
 	return ERROR_OK;
 }
 
diff --git a/src/jtag/drivers/ft232r.c b/src/jtag/drivers/ft232r.c
index 3c54809c0..d97db56a6 100644
--- a/src/jtag/drivers/ft232r.c
+++ b/src/jtag/drivers/ft232r.c
@@ -886,8 +886,7 @@ static int syncbb_execute_queue(void)
 				syncbb_scan(cmd->cmd.scan->ir_scan, type, buffer, scan_size);
 				if (jtag_read_buffer(buffer, cmd->cmd.scan) != ERROR_OK)
 					retval = ERROR_JTAG_QUEUE_FAILED;
-				if (buffer)
-					free(buffer);
+				free(buffer);
 				break;
 
 			case JTAG_SLEEP:
diff --git a/src/jtag/drivers/ftdi.c b/src/jtag/drivers/ftdi.c
index d2b97b96e..4fa83ae56 100644
--- a/src/jtag/drivers/ftdi.c
+++ b/src/jtag/drivers/ftdi.c
@@ -709,8 +709,7 @@ static int ftdi_quit(void)
 COMMAND_HANDLER(ftdi_handle_device_desc_command)
 {
 	if (CMD_ARGC == 1) {
-		if (ftdi_device_desc)
-			free(ftdi_device_desc);
+		free(ftdi_device_desc);
 		ftdi_device_desc = strdup(CMD_ARGV[0]);
 	} else {
 		LOG_ERROR("expected exactly one argument to ftdi_device_desc <description>");
@@ -722,8 +721,7 @@ COMMAND_HANDLER(ftdi_handle_device_desc_command)
 COMMAND_HANDLER(ftdi_handle_serial_command)
 {
 	if (CMD_ARGC == 1) {
-		if (ftdi_serial)
-			free(ftdi_serial);
+		free(ftdi_serial);
 		ftdi_serial = strdup(CMD_ARGV[0]);
 	} else {
 		return ERROR_COMMAND_SYNTAX_ERROR;
diff --git a/src/jtag/drivers/gw16012.c b/src/jtag/drivers/gw16012.c
index cad2e1b99..ef4b5d929 100644
--- a/src/jtag/drivers/gw16012.c
+++ b/src/jtag/drivers/gw16012.c
@@ -327,8 +327,7 @@ static int gw16012_execute_queue(void)
 				gw16012_scan(cmd->cmd.scan->ir_scan, type, buffer, scan_size);
 				if (jtag_read_buffer(buffer, cmd->cmd.scan) != ERROR_OK)
 					retval = ERROR_JTAG_QUEUE_FAILED;
-				if (buffer)
-					free(buffer);
+				free(buffer);
 				break;
 			case JTAG_SLEEP:
 				LOG_DEBUG_IO("sleep %" PRIu32, cmd->cmd.sleep->us);
diff --git a/src/jtag/drivers/jtag_usb_common.c b/src/jtag/drivers/jtag_usb_common.c
index 6337272fb..969ea8406 100644
--- a/src/jtag/drivers/jtag_usb_common.c
+++ b/src/jtag/drivers/jtag_usb_common.c
@@ -23,8 +23,7 @@ void jtag_usb_set_location(const char *location)
 	    JTAG_USB_MAX_LOCATION_LENGTH)
 		LOG_WARNING("usb location string is too long!!\n");
 
-	if (jtag_usb_location)
-		free(jtag_usb_location);
+	free(jtag_usb_location);
 
 	jtag_usb_location = strndup(location, JTAG_USB_MAX_LOCATION_LENGTH);
 }
diff --git a/src/jtag/drivers/jtag_vpi.c b/src/jtag/drivers/jtag_vpi.c
index 789d3a466..32a43f8bf 100644
--- a/src/jtag/drivers/jtag_vpi.c
+++ b/src/jtag/drivers/jtag_vpi.c
@@ -439,8 +439,7 @@ static int jtag_vpi_scan(struct scan_command *cmd)
 	if (retval != ERROR_OK)
 		return retval;
 
-	if (buf)
-		free(buf);
+	free(buf);
 
 	if (cmd->end_state != TAP_DRSHIFT) {
 		retval = jtag_vpi_state_move(cmd->end_state);
diff --git a/src/jtag/drivers/kitprog.c b/src/jtag/drivers/kitprog.c
index 4f38d195d..5538bcd73 100644
--- a/src/jtag/drivers/kitprog.c
+++ b/src/jtag/drivers/kitprog.c
@@ -227,18 +227,11 @@ static int kitprog_quit(void)
 {
 	kitprog_usb_close();
 
-	if (kitprog_handle->packet_buffer != NULL)
-		free(kitprog_handle->packet_buffer);
-	if (kitprog_handle->serial != NULL)
-		free(kitprog_handle->serial);
-	if (kitprog_handle != NULL)
-		free(kitprog_handle);
-
-	if (kitprog_serial != NULL)
-		free(kitprog_serial);
-
-	if (pending_transfers != NULL)
-		free(pending_transfers);
+	free(kitprog_handle->packet_buffer);
+	free(kitprog_handle->serial);
+	free(kitprog_handle);
+	free(kitprog_serial);
+	free(pending_transfers);
 
 	return ERROR_OK;
 }
diff --git a/src/jtag/drivers/mpsse.c b/src/jtag/drivers/mpsse.c
index 7488d9dd8..fe8b6b82c 100644
--- a/src/jtag/drivers/mpsse.c
+++ b/src/jtag/drivers/mpsse.c
@@ -404,13 +404,10 @@ void mpsse_close(struct mpsse_ctx *ctx)
 	if (ctx->usb_ctx)
 		libusb_exit(ctx->usb_ctx);
 	bit_copy_discard(&ctx->read_queue);
-	if (ctx->write_buffer)
-		free(ctx->write_buffer);
-	if (ctx->read_buffer)
-		free(ctx->read_buffer);
-	if (ctx->read_chunk)
-		free(ctx->read_chunk);
 
+	free(ctx->write_buffer);
+	free(ctx->read_buffer);
+	free(ctx->read_chunk);
 	free(ctx);
 }
 
diff --git a/src/jtag/drivers/opendous.c b/src/jtag/drivers/opendous.c
index bccd3ddb0..f0e4f566d 100644
--- a/src/jtag/drivers/opendous.c
+++ b/src/jtag/drivers/opendous.c
@@ -386,25 +386,17 @@ static int opendous_quit(void)
 {
 	opendous_usb_close(opendous_jtag_handle);
 
-	if (usb_out_buffer) {
-		free(usb_out_buffer);
-		usb_out_buffer = NULL;
-	}
+	free(usb_out_buffer);
+	usb_out_buffer = NULL;
 
-	if (usb_in_buffer) {
-		free(usb_in_buffer);
-		usb_in_buffer = NULL;
-	}
+	free(usb_in_buffer);
+	usb_in_buffer = NULL;
 
-	if (pending_scan_results_buffer) {
-		free(pending_scan_results_buffer);
-		pending_scan_results_buffer = NULL;
-	}
+	free(pending_scan_results_buffer);
+	pending_scan_results_buffer = NULL;
 
-	if (opendous_type) {
-		free(opendous_type);
-		opendous_type = NULL;
-	}
+	free(opendous_type);
+	opendous_type = NULL;
 
 	return ERROR_OK;
 }
@@ -697,8 +689,7 @@ int opendous_tap_execute(void)
 				return ERROR_JTAG_QUEUE_FAILED;
 			}
 
-			if (pending_scan_result->buffer != NULL)
-				free(pending_scan_result->buffer);
+			free(pending_scan_result->buffer);
 		}
 
 		opendous_tap_init();
diff --git a/src/jtag/drivers/openjtag.c b/src/jtag/drivers/openjtag.c
index 7eab5c130..2cf5751d6 100644
--- a/src/jtag/drivers/openjtag.c
+++ b/src/jtag/drivers/openjtag.c
@@ -591,8 +591,7 @@ static int openjtag_execute_tap_queue(void)
 #endif
 			jtag_read_buffer(buffer, openjtag_scan_result_buffer[res_count].command);
 
-			if (openjtag_scan_result_buffer[res_count].buffer)
-				free(openjtag_scan_result_buffer[res_count].buffer);
+			free(openjtag_scan_result_buffer[res_count].buffer);
 
 			res_count++;
 		}
diff --git a/src/jtag/drivers/parport.c b/src/jtag/drivers/parport.c
index b3abd1205..b203c828b 100644
--- a/src/jtag/drivers/parport.c
+++ b/src/jtag/drivers/parport.c
@@ -392,10 +392,8 @@ static int parport_quit(void)
 		parport_write_data();
 	}
 
-	if (parport_cable) {
-		free(parport_cable);
-		parport_cable = NULL;
-	}
+	free(parport_cable);
+	parport_cable = NULL;
 
 	return ERROR_OK;
 }
diff --git a/src/jtag/drivers/presto.c b/src/jtag/drivers/presto.c
index 4046b22dd..6c3a187db 100644
--- a/src/jtag/drivers/presto.c
+++ b/src/jtag/drivers/presto.c
@@ -511,8 +511,7 @@ static char *presto_serial;
 COMMAND_HANDLER(presto_handle_serial_command)
 {
 	if (CMD_ARGC == 1) {
-		if (presto_serial)
-			free(presto_serial);
+		free(presto_serial);
 		presto_serial = strdup(CMD_ARGV[0]);
 	} else
 		return ERROR_COMMAND_SYNTAX_ERROR;
@@ -553,10 +552,8 @@ static int presto_jtag_quit(void)
 	presto_close();
 	LOG_INFO("PRESTO closed");
 
-	if (presto_serial) {
-		free(presto_serial);
-		presto_serial = NULL;
-	}
+	free(presto_serial);
+	presto_serial = NULL;
 
 	return ERROR_OK;
 }
diff --git a/src/jtag/drivers/ti_icdi_usb.c b/src/jtag/drivers/ti_icdi_usb.c
index f316c8256..d276e588f 100644
--- a/src/jtag/drivers/ti_icdi_usb.c
+++ b/src/jtag/drivers/ti_icdi_usb.c
@@ -662,14 +662,9 @@ static int icdi_usb_close(void *handle)
 	if (h->usb_ctx)
 		libusb_exit(h->usb_ctx);
 
-	if (h->read_buffer)
-		free(h->read_buffer);
-
-	if (h->write_buffer)
-		free(h->write_buffer);
-
+	free(h->read_buffer);
+	free(h->write_buffer);
 	free(handle);
-
 	return ERROR_OK;
 }
 
diff --git a/src/jtag/drivers/usb_blaster/usb_blaster.c b/src/jtag/drivers/usb_blaster/usb_blaster.c
index 3c9c3a769..9648ba2e2 100644
--- a/src/jtag/drivers/usb_blaster/usb_blaster.c
+++ b/src/jtag/drivers/usb_blaster/usb_blaster.c
@@ -736,8 +736,7 @@ static int ublast_scan(struct scan_command *cmd)
 	ublast_queue_tdi(buf, scan_bits, type);
 
 	ret = jtag_read_buffer(buf, cmd);
-	if (buf)
-		free(buf);
+	free(buf);
 	/*
 	 * ublast_queue_tdi sends the last bit with TMS=1. We are therefore
 	 * already in Exit1-DR/IR and have to skip the first step on our way
diff --git a/src/jtag/drivers/usbprog.c b/src/jtag/drivers/usbprog.c
index dd7dcdb4b..627e4653d 100644
--- a/src/jtag/drivers/usbprog.c
+++ b/src/jtag/drivers/usbprog.c
@@ -137,8 +137,7 @@ static int usbprog_execute_queue(void)
 			usbprog_scan(cmd->cmd.scan->ir_scan, type, buffer, scan_size);
 			if (jtag_read_buffer(buffer, cmd->cmd.scan) != ERROR_OK)
 				return ERROR_JTAG_QUEUE_FAILED;
-			if (buffer)
-				free(buffer);
+			free(buffer);
 			break;
 		case JTAG_SLEEP:
 			LOG_DEBUG_IO("sleep %" PRIu32, cmd->cmd.sleep->us);
diff --git a/src/jtag/drivers/versaloon/versaloon.c b/src/jtag/drivers/versaloon/versaloon.c
index 35a0deff5..8efe44353 100644
--- a/src/jtag/drivers/versaloon/versaloon.c
+++ b/src/jtag/drivers/versaloon/versaloon.c
@@ -299,14 +299,11 @@ RESULT versaloon_fini(void)
 
 		versaloon_usb_device_handle = NULL;
 
-		if (versaloon_buf != NULL) {
-			free(versaloon_buf);
-			versaloon_buf = NULL;
-		}
-		if (versaloon_cmd_buf != NULL) {
-			free(versaloon_cmd_buf);
-			versaloon_cmd_buf = NULL;
-		}
+		free(versaloon_buf);
+		versaloon_buf = NULL;
+
+		free(versaloon_cmd_buf);
+		versaloon_cmd_buf = NULL;
 	}
 
 	return ERROR_OK;
diff --git a/src/jtag/drivers/vsllink.c b/src/jtag/drivers/vsllink.c
index 6f2296e6d..9aaed36b7 100644
--- a/src/jtag/drivers/vsllink.c
+++ b/src/jtag/drivers/vsllink.c
@@ -245,18 +245,14 @@ static int vsllink_speed_div(int jtag_speed, int *khz)
 
 static void vsllink_free_buffer(void)
 {
-	if (tdi_buffer != NULL) {
-		free(tdi_buffer);
-		tdi_buffer = NULL;
-	}
-	if (tdo_buffer != NULL) {
-		free(tdo_buffer);
-		tdo_buffer = NULL;
-	}
-	if (tms_buffer != NULL) {
-		free(tms_buffer);
-		tms_buffer = NULL;
-	}
+	free(tdi_buffer);
+	tdi_buffer = NULL;
+
+	free(tdo_buffer);
+	tdo_buffer = NULL;
+
+	free(tms_buffer);
+	tms_buffer = NULL;
 }
 
 static int vsllink_quit(void)
@@ -676,8 +672,7 @@ static int vsllink_jtag_execute(void)
 					return ERROR_JTAG_QUEUE_FAILED;
 				}
 
-				if (pending_scan_result->buffer != NULL)
-					free(pending_scan_result->buffer);
+				free(pending_scan_result->buffer);
 			}
 		}
 	} else {
diff --git a/src/jtag/drivers/xlnx-pcie-xvc.c b/src/jtag/drivers/xlnx-pcie-xvc.c
index 1dca5def8..2423a9f05 100644
--- a/src/jtag/drivers/xlnx-pcie-xvc.c
+++ b/src/jtag/drivers/xlnx-pcie-xvc.c
@@ -282,8 +282,7 @@ static int xlnx_pcie_xvc_execute_scan(struct jtag_command *cmd)
 	};
 
 	err = jtag_read_buffer(buf, cmd->cmd.scan);
-	if (buf)
-		free(buf);
+	free(buf);
 
 	if (tap_get_state() != tap_get_end_state())
 		err = xlnx_pcie_xvc_execute_statemove(1);
@@ -291,8 +290,7 @@ static int xlnx_pcie_xvc_execute_scan(struct jtag_command *cmd)
 	return err;
 
 out_err:
-	if (buf)
-		free(buf);
+	free(buf);
 	return err;
 }
 
@@ -456,8 +454,7 @@ COMMAND_HANDLER(xlnx_pcie_xvc_handle_config_command)
 	 * limit the memory we're leaking by freeing the old one first
 	 * before allocating a new one ...
 	 */
-	if (xlnx_pcie_xvc->device)
-		free(xlnx_pcie_xvc->device);
+	free(xlnx_pcie_xvc->device);
 
 	xlnx_pcie_xvc->device = strdup(CMD_ARGV[0]);
 	return ERROR_OK;
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index 1335c2917..153a98e1b 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -1155,10 +1155,8 @@ COMMAND_HANDLER(handle_irscan_command)
 	retval = jtag_execute_queue();
 
 error_return:
-	for (i = 0; i < num_fields; i++) {
-		if (NULL != fields[i].out_value)
-			free((void *)fields[i].out_value);
-	}
+	for (i = 0; i < num_fields; i++)
+		free((void *)fields[i].out_value);
 
 	free(fields);
 

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/aice/aice_usb.c                   | 12 +++---------
 src/jtag/drivers/amt_jtagaccel.c           |  3 +--
 src/jtag/drivers/arm-jtag-ew.c             |  3 +--
 src/jtag/drivers/bitbang.c                 |  3 +--
 src/jtag/drivers/buspirate.c               |  6 ++----
 src/jtag/drivers/ft232r.c                  |  3 +--
 src/jtag/drivers/ftdi.c                    |  6 ++----
 src/jtag/drivers/gw16012.c                 |  3 +--
 src/jtag/drivers/jtag_usb_common.c         |  3 +--
 src/jtag/drivers/jtag_vpi.c                |  3 +--
 src/jtag/drivers/kitprog.c                 | 17 +++++------------
 src/jtag/drivers/mpsse.c                   |  9 +++------
 src/jtag/drivers/opendous.c                | 27 +++++++++------------------
 src/jtag/drivers/openjtag.c                |  3 +--
 src/jtag/drivers/parport.c                 |  6 ++----
 src/jtag/drivers/presto.c                  |  9 +++------
 src/jtag/drivers/ti_icdi_usb.c             |  9 ++-------
 src/jtag/drivers/usb_blaster/usb_blaster.c |  3 +--
 src/jtag/drivers/usbprog.c                 |  3 +--
 src/jtag/drivers/versaloon/versaloon.c     | 13 +++++--------
 src/jtag/drivers/vsllink.c                 | 23 +++++++++--------------
 src/jtag/drivers/xlnx-pcie-xvc.c           |  9 +++------
 src/jtag/tcl.c                             |  6 ++----
 23 files changed, 60 insertions(+), 122 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1401-ga098a14eb

[OpenOCD-Gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  a098a14eb53131871469a9c32b206b0dc55ef237 (commit)
      from  f788949651ef714024a29b08f4b064e78c9b4791 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit a098a14eb53131871469a9c32b206b0dc55ef237
Author: Stafford Horne <sh...@gm...>
Date:   Wed Apr 5 06:11:30 2017 +0900

    openrisc: Fix segv jsp due to free of unallocated data
    
    The prompt pointer in the jtag serial port is never zero'd or allocated.
    Completely remove it since there is not much use for it as the target
    software will provide the actual prompt.
    
    Change-Id: Id95d8ccb9f725e53b9d03386b11d91eba1cd6ef4
    Signed-off-by: Stafford Horne <sh...@gm...>
    Reviewed-on: http://openocd.zylin.com/4093
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/openrisc/jsp_server.c b/src/target/openrisc/jsp_server.c
index 6fb764a6c..f28815df9 100644
--- a/src/target/openrisc/jsp_server.c
+++ b/src/target/openrisc/jsp_server.c
@@ -184,14 +184,8 @@ static int jsp_input(struct connection *connection)
 
 static int jsp_connection_closed(struct connection *connection)
 {
-	struct telnet_connection *t_con = connection->priv;
 	struct jsp_service *jsp_service = connection->service->priv;
 
-	if (t_con->prompt) {
-		free(t_con->prompt);
-		t_con->prompt = NULL;
-	}
-
 	int retval = target_unregister_timer_callback(&jsp_poll_read, jsp_service);
 	if (ERROR_OK != retval)
 		return retval;

-----------------------------------------------------------------------

Summary of changes:
 src/target/openrisc/jsp_server.c | 6 ------
 1 file changed, 6 deletions(-)


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This is an automated email from the git hooks/post-receive script. It was
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- Log -----------------------------------------------------------------
commit f788949651ef714024a29b08f4b064e78c9b4791
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Aug 23 01:43:21 2020 +0200

    openocd: fix command's usage string
    
    The usage string should contain only the command parameters.
    OpenOCD will automatically prepend the command name to the usage
    string while dumping the usage or help message.
    
    Remove the repeated command name from the usage string.
    
    Change-Id: If10a0f1c254aee302b9ca08958390b7f21cdb21b
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5824
    Tested-by: jenkins

diff --git a/src/jtag/hla/hla_interface.c b/src/jtag/hla/hla_interface.c
index 7be9b2dea..490eb9f4d 100644
--- a/src/jtag/hla/hla_interface.c
+++ b/src/jtag/hla/hla_interface.c
@@ -341,7 +341,7 @@ static const struct command_registration hl_interface_command_handlers[] = {
 	 .handler = &interface_handle_hla_command,
 	 .mode = COMMAND_EXEC,
 	 .help = "execute a custom adapter-specific command",
-	 .usage = "hla_command <command>",
+	 .usage = "<command>",
 	 },
 	COMMAND_REGISTRATION_DONE
 };
diff --git a/src/svf/svf.c b/src/svf/svf.c
index b62cdae08..608703434 100644
--- a/src/svf/svf.c
+++ b/src/svf/svf.c
@@ -1556,7 +1556,7 @@ static const struct command_registration svf_command_handlers[] = {
 		.handler = handle_svf_command,
 		.mode = COMMAND_EXEC,
 		.help = "Runs a SVF file.",
-		.usage = "svf [-tap device.tap] <file> [quiet] [nil] [progress] [ignore_error]",
+		.usage = "[-tap device.tap] <file> [quiet] [nil] [progress] [ignore_error]",
 	},
 	COMMAND_REGISTRATION_DONE
 };
diff --git a/src/target/nds32_cmd.c b/src/target/nds32_cmd.c
index d7d040e4b..1684ea882 100644
--- a/src/target/nds32_cmd.c
+++ b/src/target/nds32_cmd.c
@@ -1036,7 +1036,7 @@ static const struct command_registration nds32_exec_command_handlers[] = {
 		.name = "login_edm_operation",
 		.handler = handle_nds32_login_edm_operation_command,
 		.mode = COMMAND_CONFIG,
-		.usage = "login_edm_operation misc_reg_no value",
+		.usage = "misc_reg_no value",
 		.help = "add EDM operations for secure MCU debugging.",
 	},
 	{
diff --git a/src/target/openrisc/or1k.c b/src/target/openrisc/or1k.c
index 71491119b..93fb9c6a3 100644
--- a/src/target/openrisc/or1k.c
+++ b/src/target/openrisc/or1k.c
@@ -1377,21 +1377,21 @@ static const struct command_registration or1k_hw_ip_command_handlers[] = {
 		.name = "tap_select",
 		.handler = or1k_tap_select_command_handler,
 		.mode = COMMAND_ANY,
-		.usage = "tap_select name",
+		.usage = "name",
 		.help = "Select the TAP core to use",
 	},
 	{
 		.name = "tap_list",
 		.handler = or1k_tap_list_command_handler,
 		.mode = COMMAND_ANY,
-		.usage = "tap_list",
+		.usage = "",
 		.help = "Display available TAP core",
 	},
 	{
 		.name = "du_select",
 		.handler = or1k_du_select_command_handler,
 		.mode = COMMAND_ANY,
-		.usage = "du_select name",
+		.usage = "name",
 		.help = "Select the Debug Unit core to use",
 	},
 	{
@@ -1409,7 +1409,7 @@ static const struct command_registration or1k_reg_command_handlers[] = {
 		.name = "addreg",
 		.handler = or1k_addreg_command_handler,
 		.mode = COMMAND_ANY,
-		.usage = "addreg name addr feature group",
+		.usage = "name addr feature group",
 		.help = "Add a register to the register list",
 	},
 	COMMAND_REGISTRATION_DONE

commit 25b8b376387724e4c74d0c5d005b15504d44ff4c
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Aug 23 01:35:09 2020 +0200

    jtag/aice: fix command's usage string
    
    The usage string should contain only the command parameters.
    OpenOCD will automatically prepend the command name to the usage
    string while dumping the usage or help message.
    
    Remove the repeated command name from the usage string.
    
    Change-Id: Idbc301b34fab19e221131d232577c1629568e6ea
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5823
    Tested-by: jenkins

diff --git a/src/jtag/aice/aice_interface.c b/src/jtag/aice/aice_interface.c
index a2bec327f..160eb1105 100644
--- a/src/jtag/aice/aice_interface.c
+++ b/src/jtag/aice/aice_interface.c
@@ -422,83 +422,83 @@ static const struct command_registration aice_subcommand_handlers[] = {
 		.handler = &aice_handle_aice_info_command,
 		.mode = COMMAND_EXEC,
 		.help = "show aice info",
-		.usage = "aice info",
+		.usage = "",
 	},
 	{
 		.name = "port",
 		.handler = &aice_handle_aice_port_command,
 		.mode = COMMAND_CONFIG,
 		.help = "set the port of the AICE",
-		.usage = "aice port ['aice_pipe'|'aice_usb']",
+		.usage = "['aice_pipe'|'aice_usb']",
 	},
 	{
 		.name = "desc",
 		.handler = &aice_handle_aice_desc_command,
 		.mode = COMMAND_CONFIG,
 		.help = "set the aice device description",
-		.usage = "aice desc [desciption string]",
+		.usage = "[desciption string]",
 	},
 	{
 		.name = "serial",
 		.handler = &aice_handle_aice_serial_command,
 		.mode = COMMAND_CONFIG,
 		.help = "set the serial number of the AICE device",
-		.usage = "aice serial [serial string]",
+		.usage = "[serial string]",
 	},
 	{
 		.name = "vid_pid",
 		.handler = &aice_handle_aice_vid_pid_command,
 		.mode = COMMAND_CONFIG,
 		.help = "the vendor and product ID of the AICE device",
-		.usage = "aice vid_pid (vid pid)*",
+		.usage = "(vid pid)*",
 	},
 	{
 		.name = "adapter",
 		.handler = &aice_handle_aice_adapter_command,
 		.mode = COMMAND_CONFIG,
 		.help = "set the file name of adapter",
-		.usage = "aice adapter [adapter name]",
+		.usage = "[adapter name]",
 	},
 	{
 		.name = "retry_times",
 		.handler = &aice_handle_aice_retry_times_command,
 		.mode = COMMAND_CONFIG,
 		.help = "set retry times as AICE timeout",
-		.usage = "aice retry_times num_of_retry",
+		.usage = "num_of_retry",
 	},
 	{
 		.name = "count_to_check_dbger",
 		.handler = &aice_handle_aice_count_to_check_dbger_command,
 		.mode = COMMAND_CONFIG,
 		.help = "set retry times as checking $DBGER status",
-		.usage = "aice count_to_check_dbger count_of_checking",
+		.usage = "count_of_checking",
 	},
 	{
 		.name = "custom_srst_script",
 		.handler = &aice_handle_aice_custom_srst_script_command,
 		.mode = COMMAND_CONFIG,
-		.usage = "custom_srst_script script_file_name",
+		.usage = "script_file_name",
 		.help = "set custom srst script",
 	},
 	{
 		.name = "custom_trst_script",
 		.handler = &aice_handle_aice_custom_trst_script_command,
 		.mode = COMMAND_CONFIG,
-		.usage = "custom_trst_script script_file_name",
+		.usage = "script_file_name",
 		.help = "set custom trst script",
 	},
 	{
 		.name = "custom_restart_script",
 		.handler = &aice_handle_aice_custom_restart_script_command,
 		.mode = COMMAND_CONFIG,
-		.usage = "custom_restart_script script_file_name",
+		.usage = "script_file_name",
 		.help = "set custom restart script",
 	},
 	{
 		.name = "reset",
 		.handler = &aice_handle_aice_reset_command,
 		.mode = COMMAND_EXEC,
-		.usage = "aice reset",
+		.usage = "",
 		.help = "reset AICE",
 	},
 	COMMAND_REGISTRATION_DONE
@@ -509,7 +509,7 @@ static const struct command_registration aice_command_handlers[] = {
 		.name = "aice",
 		.mode = COMMAND_ANY,
 		.help = "perform aice management",
-		.usage = "aice [subcommand]",
+		.usage = "[subcommand]",
 		.chain = aice_subcommand_handlers,
 	},
 	COMMAND_REGISTRATION_DONE

commit 42faa8a4bc3d757890aeb6b5c7dcd99fdda6ceed
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Aug 23 01:28:38 2020 +0200

    target/arc: fix command's usage string
    
    The usage string should contain only the command parameters.
    OpenOCD will automatically prepend the command name to the usage
    string while dumping the usage or help message.
    
    Remove the repeated command name from the usage string.
    
    Change-Id: I691094a6395acb0e4ea3bea2347ff38379002464
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5822
    Tested-by: jenkins

diff --git a/src/target/arc_cmd.c b/src/target/arc_cmd.c
index 36babc768..18f5cb8f4 100644
--- a/src/target/arc_cmd.c
+++ b/src/target/arc_cmd.c
@@ -451,7 +451,7 @@ static const struct command_registration arc_jtag_command_group[] = {
 			"raw JTAG request that bypasses OpenOCD register cache "
 			"and thus is unsafe and can have unexpected consequences. "
 			"Use at your own risk.",
-		.usage = "arc jtag get-aux-reg <regnum>"
+		.usage = "<regnum>"
 	},
 	{
 		.name = "set-aux-reg",
@@ -461,7 +461,7 @@ static const struct command_registration arc_jtag_command_group[] = {
 			"raw JTAG request that bypasses OpenOCD register cache "
 			"and thus is unsafe and can have unexpected consequences. "
 			"Use at your own risk.",
-		.usage = "arc jtag set-aux-reg <regnum> <value>"
+		.usage = "<regnum> <value>"
 	},
 	{
 		.name = "get-core-reg",
@@ -471,7 +471,7 @@ static const struct command_registration arc_jtag_command_group[] = {
 			"raw JTAG request that bypasses OpenOCD register cache "
 			"and thus is unsafe and can have unexpected consequences. "
 			"Use at your own risk.",
-		.usage = "arc jtag get-core-reg <regnum> [<value>]"
+		.usage = "<regnum> [<value>]"
 	},
 	{
 		.name = "set-core-reg",
@@ -481,7 +481,7 @@ static const struct command_registration arc_jtag_command_group[] = {
 			"raw JTAG request that bypasses OpenOCD register cache "
 			"and thus is unsafe and can have unexpected consequences. "
 			"Use at your own risk.",
-		.usage = "arc jtag set-core-reg <regnum> [<value>]"
+		.usage = "<regnum> [<value>]"
 	},
 	COMMAND_REGISTRATION_DONE
 };
@@ -1010,7 +1010,7 @@ static const struct command_registration arc_core_command_handlers[] = {
 		.name = "add-reg-type-flags",
 		.jim_handler = jim_arc_add_reg_type_flags,
 		.mode = COMMAND_CONFIG,
-		.usage = "arc ardd-reg-type-flags -name <string> -flag <name> <position> "
+		.usage = "-name <string> -flag <name> <position> "
 			"[-flag <name> <position>]...",
 		.help = "Add new 'flags' register data type. Only single bit flags "
 			"are supported. Type name is global. Bitsize of register is fixed "
@@ -1020,7 +1020,7 @@ static const struct command_registration arc_core_command_handlers[] = {
 		.name = "add-reg-type-struct",
 		.jim_handler = jim_arc_add_reg_type_struct,
 		.mode = COMMAND_CONFIG,
-		.usage = "arc add-reg-type-struct -name <string> -bitfield <name> <start> <end> "
+		.usage = "-name <string> -bitfield <name> <start> <end> "
 			"[-bitfield <name> <start> <end>]...",
 		.help = "Add new 'struct' register data type. Only bit-fields are "
 			"supported so far, which means that for each bitfield start and end "
@@ -1032,7 +1032,7 @@ static const struct command_registration arc_core_command_handlers[] = {
 		.name = "add-reg",
 		.jim_handler = jim_arc_add_reg,
 		.mode = COMMAND_CONFIG,
-		.usage = "arc add-reg -name <string> -num <int> -feature <string> [-gdbnum <int>] "
+		.usage = "-name <string> -num <int> -feature <string> [-gdbnum <int>] "
 			"[-core|-bcr] [-type <type_name>] [-g]",
 		.help = "Add new register. Name, architectural number and feature name "
 			"are required options. GDB regnum will default to previous register "
@@ -1043,7 +1043,7 @@ static const struct command_registration arc_core_command_handlers[] = {
 		.name = "set-reg-exists",
 		.handler = arc_set_reg_exists,
 		.mode = COMMAND_ANY,
-		.usage = "arc set-reg-exists <register-name> [<register-name>]...",
+		.usage = "<register-name> [<register-name>]...",
 		.help = "Set that register exists. Accepts multiple register names as "
 			"arguments.",
 	},
@@ -1051,7 +1051,7 @@ static const struct command_registration arc_core_command_handlers[] = {
 		.name = "get-reg-field",
 		.jim_handler = jim_arc_get_reg_field,
 		.mode = COMMAND_ANY,
-		.usage = "arc get-reg-field <regname> <field_name>",
+		.usage = "<regname> <field_name>",
 		.help = "Returns value of field in a register with 'struct' type.",
 	},
 	{
@@ -1083,7 +1083,7 @@ const struct command_registration arc_monitor_command_handlers[] = {
 		.name = "arc",
 		.mode = COMMAND_ANY,
 		.help = "ARC monitor command group",
-		.usage = "Help info ...",
+		.usage = "",
 		.chain = arc_core_command_handlers,
 	},
 	COMMAND_REGISTRATION_DONE

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/aice/aice_interface.c | 26 +++++++++++++-------------
 src/jtag/hla/hla_interface.c   |  2 +-
 src/svf/svf.c                  |  2 +-
 src/target/arc_cmd.c           | 20 ++++++++++----------
 src/target/nds32_cmd.c         |  2 +-
 src/target/openrisc/or1k.c     |  8 ++++----
 6 files changed, 30 insertions(+), 30 deletions(-)


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- Log -----------------------------------------------------------------
commit d3249fd45a7832ed922ed4227c867c3c674b4812
Author: Antonio Borneo <bor...@gm...>
Date:   Tue Aug 18 18:56:53 2020 +0200

    openocd: use proper format with uint32_t
    
    Modify the format strings to properly handle uint32_t data types.
    
    Change-Id: I4de49bf02c9e37b72240224c23fc83abe8a4fa83
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5819
    Tested-by: jenkins

diff --git a/src/pld/xilinx_bit.c b/src/pld/xilinx_bit.c
index a975a7a0c..f83d8942d 100644
--- a/src/pld/xilinx_bit.c
+++ b/src/pld/xilinx_bit.c
@@ -119,7 +119,7 @@ int xilinx_read_bit_file(struct xilinx_bit_file *bit_file, const char *filename)
 	if (read_section(input_file, 4, 'e', &bit_file->length, &bit_file->data) != ERROR_OK)
 		return ERROR_PLD_FILE_LOAD_FAILED;
 
-	LOG_DEBUG("bit_file: %s %s %s,%s %" PRIi32 "", bit_file->source_file, bit_file->part_name,
+	LOG_DEBUG("bit_file: %s %s %s,%s %" PRIu32 "", bit_file->source_file, bit_file->part_name,
 		bit_file->date, bit_file->time, bit_file->length);
 
 	fclose(input_file);
diff --git a/src/rtos/ThreadX.c b/src/rtos/ThreadX.c
index 9605533aa..302641bae 100644
--- a/src/rtos/ThreadX.c
+++ b/src/rtos/ThreadX.c
@@ -248,7 +248,7 @@ static const struct rtos_register_stacking *get_stacking_info_arm926ejs(const st
 		LOG_DEBUG("  solicited stack");
 		return param->stacking_info + 0;
 	} else {
-		LOG_DEBUG("  interrupt stack: %u", flag);
+		LOG_DEBUG("  interrupt stack: %" PRIu32, flag);
 		return param->stacking_info + 1;
 	}
 }
diff --git a/src/rtos/hwthread.c b/src/rtos/hwthread.c
index 38e42a041..e0789aa63 100644
--- a/src/rtos/hwthread.c
+++ b/src/rtos/hwthread.c
@@ -281,7 +281,7 @@ static int hwthread_get_thread_reg(struct rtos *rtos, int64_t thread_id,
 
 	struct reg *reg = register_get_by_number(curr->reg_cache, reg_num, true);
 	if (!reg) {
-		LOG_ERROR("Couldn't find register %d in thread %" PRId64 ".", reg_num,
+		LOG_ERROR("Couldn't find register %" PRIu32 " in thread %" PRId64 ".", reg_num,
 				thread_id);
 		return ERROR_FAIL;
 	}
diff --git a/src/rtos/linux.c b/src/rtos/linux.c
index dbbf97b44..44e132d36 100644
--- a/src/rtos/linux.c
+++ b/src/rtos/linux.c
@@ -1483,13 +1483,13 @@ static char *linux_ps_command(struct target *target)
 				if (temp->context)
 					tmp +=
 						sprintf(tmp,
-							"%" PRId32 "\t\t%" PRId32 "\t\t%" PRIx32 "\t\t%s\n",
+							"%" PRIu32 "\t\t%" PRIu32 "\t\t%" PRIx32 "\t\t%s\n",
 							temp->pid, temp->oncpu,
 							temp->asid, temp->name);
 				else
 					tmp +=
 						sprintf(tmp,
-							"%" PRId32 "\t\t%" PRId32 "\t\t%" PRIx32 "\t\t%s\n",
+							"%" PRIu32 "\t\t%" PRIu32 "\t\t%" PRIx32 "\t\t%s\n",
 							temp->pid, temp->oncpu,
 							temp->asid, temp->name);
 			}
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 85d3c14b1..c36966554 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -1388,8 +1388,8 @@ static int gdb_set_register_packet(struct connection *connection,
 	}
 
 	if (chars != (DIV_ROUND_UP(reg_list[reg_num]->size, 8) * 2)) {
-		LOG_ERROR("gdb sent %d bits for a %d-bit register (%s)",
-				(int) chars * 4, reg_list[reg_num]->size, reg_list[reg_num]->name);
+		LOG_ERROR("gdb sent %zu bits for a %" PRIu32 "-bit register (%s)",
+				chars * 4, reg_list[reg_num]->size, reg_list[reg_num]->name);
 		free(bin_buf);
 		free(reg_list);
 		return ERROR_SERVER_REMOTE_CLOSED;
@@ -2050,7 +2050,7 @@ static int gdb_generate_reg_type_description(struct target *target,
 		}
 		/* <vector id="id" type="type" count="count"/> */
 		xml_printf(&retval, tdesc, pos, size,
-				"<vector id=\"%s\" type=\"%s\" count=\"%d\"/>\n",
+				"<vector id=\"%s\" type=\"%s\" count=\"%" PRIu32 "\"/>\n",
 				type->id, type->reg_type_vector->type->id,
 				type->reg_type_vector->count);
 
@@ -2097,11 +2097,11 @@ static int gdb_generate_reg_type_description(struct target *target,
 			 *  <field name="name" start="start" end="end"/> ...
 			 * </struct> */
 			xml_printf(&retval, tdesc, pos, size,
-					"<struct id=\"%s\" size=\"%d\">\n",
+					"<struct id=\"%s\" size=\"%" PRIu32 "\">\n",
 					type->id, type->reg_type_struct->size);
 			while (field != NULL) {
 				xml_printf(&retval, tdesc, pos, size,
-						"<field name=\"%s\" start=\"%d\" end=\"%d\" type=\"%s\" />\n",
+						"<field name=\"%s\" start=\"%" PRIu32 "\" end=\"%" PRIu32 "\" type=\"%s\" />\n",
 						field->name, field->bitfield->start, field->bitfield->end,
 						gdb_get_reg_type_name(field->bitfield->type));
 
@@ -2142,14 +2142,14 @@ static int gdb_generate_reg_type_description(struct target *target,
 		 *  <field name="name" start="start" end="end"/> ...
 		 * </flags> */
 		xml_printf(&retval, tdesc, pos, size,
-				"<flags id=\"%s\" size=\"%d\">\n",
+				"<flags id=\"%s\" size=\"%" PRIu32 "\">\n",
 				type->id, type->reg_type_flags->size);
 
 		struct reg_data_type_flags_field *field;
 		field = type->reg_type_flags->fields;
 		while (field != NULL) {
 			xml_printf(&retval, tdesc, pos, size,
-					"<field name=\"%s\" start=\"%d\" end=\"%d\" type=\"%s\" />\n",
+					"<field name=\"%s\" start=\"%" PRIu32 "\" end=\"%" PRIu32 "\" type=\"%s\" />\n",
 					field->name, field->bitfield->start, field->bitfield->end,
 					gdb_get_reg_type_name(field->bitfield->type));
 
@@ -2302,9 +2302,9 @@ static int gdb_generate_target_description(struct target *target, char **tdesc_o
 				xml_printf(&retval, &tdesc, &pos, &size,
 						"<reg name=\"%s\"", reg_list[i]->name);
 				xml_printf(&retval, &tdesc, &pos, &size,
-						" bitsize=\"%d\"", reg_list[i]->size);
+						" bitsize=\"%" PRIu32 "\"", reg_list[i]->size);
 				xml_printf(&retval, &tdesc, &pos, &size,
-						" regnum=\"%d\"", reg_list[i]->number);
+						" regnum=\"%" PRIu32 "\"", reg_list[i]->number);
 				if (reg_list[i]->caller_save)
 					xml_printf(&retval, &tdesc, &pos, &size,
 							" save-restore=\"yes\"");

commit 99add6227fe0a3be536f9b83ff6aa7dd63a8d2dc
Author: Antonio Borneo <bor...@gm...>
Date:   Tue Aug 18 18:56:27 2020 +0200

    target: use proper format with uint32_t
    
    Modify the format strings to properly handle uint32_t data types.
    
    While there, fix prototype mismatch between header and C file of
    the function armv7a_l1_d_cache_inval_virt().
    
    Change-Id: I434bd241fa5c38e0c15d22cda2295097050067f5
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5818
    Tested-by: jenkins

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index e6b1cc007..4febc8c96 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -105,7 +105,7 @@ static int aarch64_restore_system_control_reg(struct target *target)
 			break;
 
 		default:
-			LOG_ERROR("cannot read system control register in this mode: (%s : 0x%" PRIx32 ")",
+			LOG_ERROR("cannot read system control register in this mode: (%s : 0x%x)",
 					armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode);
 			return ERROR_FAIL;
 		}
@@ -180,7 +180,7 @@ static int aarch64_mmu_modify(struct target *target, int enable)
 		break;
 
 	default:
-		LOG_DEBUG("unknown cpu state 0x%" PRIx32, armv8->arm.core_mode);
+		LOG_DEBUG("unknown cpu state 0x%x", armv8->arm.core_mode);
 		break;
 	}
 
@@ -1042,7 +1042,7 @@ static int aarch64_post_debug_entry(struct target *target)
 		break;
 
 	default:
-		LOG_ERROR("cannot read system control register in this mode: (%s : 0x%" PRIx32 ")",
+		LOG_ERROR("cannot read system control register in this mode: (%s : 0x%x)",
 				armv8_mode_name(armv8->arm.core_mode), armv8->arm.core_mode);
 		return ERROR_FAIL;
 	}
diff --git a/src/target/arc.c b/src/target/arc.c
index ba8903d48..e1b576436 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -197,7 +197,7 @@ int arc_reg_add(struct target *target, struct arc_reg_desc *arc_reg,
 	arc->num_regs += 1;
 
 	LOG_DEBUG(
-			"added register {name=%s, num=0x%x, type=%s%s%s%s}",
+			"added register {name=%s, num=0x%" PRIx32 ", type=%s%s%s%s}",
 			arc_reg->name, arc_reg->arch_num, arc_reg->data_type->id,
 			arc_reg->is_core ? ", core" : "",  arc_reg->is_bcr ? ", bcr" : "",
 			arc_reg->is_general ? ", general" : ""
@@ -889,7 +889,7 @@ static int arc_save_context(struct target *target)
 			core_cnt += 1;
 			reg->valid = true;
 			reg->dirty = false;
-			LOG_DEBUG("Get core register regnum=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
+			LOG_DEBUG("Get core register regnum=%u, name=%s, value=0x%08" PRIx32,
 				i, arc_reg->name, core_values[core_cnt]);
 		}
 	}
@@ -904,7 +904,7 @@ static int arc_save_context(struct target *target)
 			aux_cnt += 1;
 			reg->valid = true;
 			reg->dirty = false;
-			LOG_DEBUG("Get aux register regnum=%" PRIu32 ", name=%s, value=0x%08" PRIx32,
+			LOG_DEBUG("Get aux register regnum=%u, name=%s, value=0x%08" PRIx32,
 				i, arc_reg->name, aux_values[aux_cnt]);
 		}
 	}
@@ -1464,7 +1464,7 @@ static int arc_configure_actionpoint(struct target *target, uint32_t ap_num,
 	if (control_tt != AP_AC_TT_DISABLE) {
 
 		if (arc->actionpoints_num_avail < 1) {
-			LOG_ERROR("No free actionpoints, maximim amount is %" PRIu32,
+			LOG_ERROR("No free actionpoints, maximim amount is %u",
 					arc->actionpoints_num);
 			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 		}
@@ -1551,7 +1551,7 @@ static int arc_set_breakpoint(struct target *target,
 		}
 
 		if (bp_num >= arc->actionpoints_num) {
-			LOG_ERROR("No free actionpoints, maximum amount is %" PRIu32,
+			LOG_ERROR("No free actionpoints, maximum amount is %u",
 					arc->actionpoints_num);
 			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 		}
@@ -1607,7 +1607,7 @@ static int arc_unset_breakpoint(struct target *target,
 			} else {
 				LOG_WARNING("Software breakpoint @0x%" TARGET_PRIxADDR
 					" has been overwritten outside of debugger."
-					"Expected: @0x%" PRIx32 ", got: @0x%" PRIx32,
+					"Expected: @0x%x, got: @0x%" PRIx32,
 					breakpoint->address, ARC_SDBBP_32, current_instr);
 			}
 		} else if (breakpoint->length == 2) {
diff --git a/src/target/arc.h b/src/target/arc.h
index f9ee5b45e..aeb326cb5 100644
--- a/src/target/arc.h
+++ b/src/target/arc.h
@@ -55,7 +55,7 @@
 #define REG_TYPE_MAX_NAME_LENGTH	20
 
 /* ARC 32bits opcodes */
-#define ARC_SDBBP_32 0x256F003F  /* BRK */
+#define ARC_SDBBP_32 0x256F003FU  /* BRK */
 
 /* ARC 16bits opcodes */
 #define ARC_SDBBP_16 0x7FFF      /* BRK_S */
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index b1b9aedd5..d70d27377 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -102,7 +102,7 @@ static void arm7_9_assign_wp(struct arm7_9_common *arm7_9, struct breakpoint *br
 	} else
 		LOG_ERROR("BUG: no hardware comparator available");
 
-	LOG_DEBUG("BPID: %" PRId32 " (0x%08" TARGET_PRIxADDR ") using hw wp: %d",
+	LOG_DEBUG("BPID: %" PRIu32 " (0x%08" TARGET_PRIxADDR ") using hw wp: %d",
 			breakpoint->unique_id,
 			breakpoint->address,
 			breakpoint->set);
@@ -188,7 +188,7 @@ static int arm7_9_set_breakpoint(struct target *target, struct breakpoint *break
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 	int retval = ERROR_OK;
 
-	LOG_DEBUG("BPID: %" PRId32 ", Address: 0x%08" TARGET_PRIxADDR ", Type: %d",
+	LOG_DEBUG("BPID: %" PRIu32 ", Address: 0x%08" TARGET_PRIxADDR ", Type: %d",
 		breakpoint->unique_id,
 		breakpoint->address,
 		breakpoint->type);
@@ -300,7 +300,7 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre
 	int retval = ERROR_OK;
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
-	LOG_DEBUG("BPID: %" PRId32 ", Address: 0x%08" TARGET_PRIxADDR,
+	LOG_DEBUG("BPID: %" PRIu32 ", Address: 0x%08" TARGET_PRIxADDR,
 		breakpoint->unique_id,
 		breakpoint->address);
 
@@ -310,7 +310,7 @@ static int arm7_9_unset_breakpoint(struct target *target, struct breakpoint *bre
 	}
 
 	if (breakpoint->type == BKPT_HARD) {
-		LOG_DEBUG("BPID: %" PRId32 " Releasing hw wp: %d",
+		LOG_DEBUG("BPID: %" PRIu32 " Releasing hw wp: %d",
 			breakpoint->unique_id,
 			breakpoint->set);
 		if (breakpoint->set == 1) {
@@ -1725,7 +1725,7 @@ int arm7_9_resume(struct target *target,
 		breakpoint = breakpoint_find(target,
 				buf_get_u32(arm->pc->value, 0, 32));
 		if (breakpoint != NULL) {
-			LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR " (id: %" PRId32,
+			LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR " (id: %" PRIu32,
 				breakpoint->address,
 				breakpoint->unique_id);
 			retval = arm7_9_unset_breakpoint(target, breakpoint);
diff --git a/src/target/arm946e.c b/src/target/arm946e.c
index 33da4a4f3..8754c861c 100644
--- a/src/target/arm946e.c
+++ b/src/target/arm946e.c
@@ -596,7 +596,7 @@ COMMAND_HANDLER(arm946e_handle_cp15)
 		uint32_t value;
 		retval = arm946e_read_cp15(target, address, &value);
 		if (retval != ERROR_OK) {
-			command_print(CMD, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
+			command_print(CMD, "%s cp15 reg %" PRIu32 " access failed", target_name(target), address);
 			return retval;
 		}
 		retval = jtag_execute_queue();
@@ -611,7 +611,7 @@ COMMAND_HANDLER(arm946e_handle_cp15)
 
 		retval = arm946e_write_cp15(target, address, value);
 		if (retval != ERROR_OK) {
-			command_print(CMD, "%s cp15 reg %" PRIi32 " access failed", target_name(target), address);
+			command_print(CMD, "%s cp15 reg %" PRIu32 " access failed", target_name(target), address);
 			return retval;
 		}
 		if (address == CP15_CTL)
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index 8ddcb3c79..b6d3e50e3 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -199,7 +199,7 @@ COMMAND_HANDLER(arm966e_handle_cp15_command)
 			retval = arm966e_read_cp15(target, address, &value);
 			if (retval != ERROR_OK) {
 				command_print(CMD,
-						"couldn't access reg %" PRIi32,
+						"couldn't access reg %" PRIu32,
 						address);
 				return ERROR_OK;
 			}
@@ -207,7 +207,7 @@ COMMAND_HANDLER(arm966e_handle_cp15_command)
 			if (retval != ERROR_OK)
 				return retval;
 
-			command_print(CMD, "%" PRIi32 ": %8.8" PRIx32,
+			command_print(CMD, "%" PRIu32 ": %8.8" PRIx32,
 					address, value);
 		} else if (CMD_ARGC == 2) {
 			uint32_t value;
@@ -215,11 +215,11 @@ COMMAND_HANDLER(arm966e_handle_cp15_command)
 			retval = arm966e_write_cp15(target, address, value);
 			if (retval != ERROR_OK) {
 				command_print(CMD,
-						"couldn't access reg %" PRIi32,
+						"couldn't access reg %" PRIu32,
 						address);
 				return ERROR_OK;
 			}
-			command_print(CMD, "%" PRIi32 ": %8.8" PRIx32,
+			command_print(CMD, "%" PRIu32 ": %8.8" PRIx32,
 					address, value);
 		}
 	}
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 058484471..a09e2698a 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1682,7 +1682,7 @@ COMMAND_HANDLER(dap_memaccess_command)
 	}
 	dap->ap[dap->apsel].memaccess_tck = memaccess_tck;
 
-	command_print(CMD, "memory bus access delay set to %" PRIi32 " tck",
+	command_print(CMD, "memory bus access delay set to %" PRIu32 " tck",
 			dap->ap[dap->apsel].memaccess_tck);
 
 	return ERROR_OK;
@@ -1695,7 +1695,7 @@ COMMAND_HANDLER(dap_apsel_command)
 
 	switch (CMD_ARGC) {
 	case 0:
-		command_print(CMD, "%" PRIi32, dap->apsel);
+		command_print(CMD, "%" PRIu32, dap->apsel);
 		return ERROR_OK;
 	case 1:
 		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
@@ -1721,7 +1721,7 @@ COMMAND_HANDLER(dap_apcsw_command)
 
 	switch (CMD_ARGC) {
 	case 0:
-		command_print(CMD, "ap %" PRIi32 " selected, csw 0x%8.8" PRIx32,
+		command_print(CMD, "ap %" PRIu32 " selected, csw 0x%8.8" PRIx32,
 			dap->apsel, apcsw);
 		return ERROR_OK;
 	case 1:
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 09dee9151..c36744ddf 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -257,10 +257,10 @@ int armv7a_handle_cache_info_command(struct command_invocation *cmd,
 
 		if (arch->ctype & 1) {
 			command_print(cmd,
-				"L%d I-Cache: linelen %" PRIi32
-				", associativity %" PRIi32
-				", nsets %" PRIi32
-				", cachesize %" PRId32 " KBytes",
+				"L%d I-Cache: linelen %" PRIu32
+				", associativity %" PRIu32
+				", nsets %" PRIu32
+				", cachesize %" PRIu32 " KBytes",
 				cl+1,
 				arch->i_size.linelen,
 				arch->i_size.associativity,
@@ -270,10 +270,10 @@ int armv7a_handle_cache_info_command(struct command_invocation *cmd,
 
 		if (arch->ctype >= 2) {
 			command_print(cmd,
-				"L%d D-Cache: linelen %" PRIi32
-				", associativity %" PRIi32
-				", nsets %" PRIi32
-				", cachesize %" PRId32 " KBytes",
+				"L%d D-Cache: linelen %" PRIu32
+				", associativity %" PRIu32
+				", nsets %" PRIu32
+				", cachesize %" PRIu32 " KBytes",
 				cl+1,
 				arch->d_u_size.linelen,
 				arch->d_u_size.associativity,
@@ -283,7 +283,7 @@ int armv7a_handle_cache_info_command(struct command_invocation *cmd,
 	}
 
 	if (l2x_cache != NULL)
-		command_print(cmd, "Outer unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
+		command_print(cmd, "Outer unified cache Base Address 0x%" PRIx32 ", %" PRIu32 " ways",
 			l2x_cache->base, l2x_cache->way);
 
 	return ERROR_OK;
@@ -399,7 +399,7 @@ int armv7a_identify_cache(struct target *target)
 
 	cache->iminline = 4UL << (ctr & 0xf);
 	cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
-	LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRId32 " ctr.dminline %" PRId32,
+	LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
 		 ctr, cache->iminline, cache->dminline);
 
 	/*  retrieve CLIDR
@@ -439,13 +439,13 @@ int armv7a_identify_cache(struct target *target)
 				goto done;
 			cache->arch[cl].d_u_size = decode_cache_reg(cache_reg);
 
-			LOG_DEBUG("data/unified cache index %d << %d, way %d << %d",
+			LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
 					cache->arch[cl].d_u_size.index,
 					cache->arch[cl].d_u_size.index_shift,
 					cache->arch[cl].d_u_size.way,
 					cache->arch[cl].d_u_size.way_shift);
 
-			LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
+			LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
 					cache->arch[cl].d_u_size.linelen,
 					cache->arch[cl].d_u_size.cachesize,
 					cache->arch[cl].d_u_size.associativity);
@@ -459,13 +459,13 @@ int armv7a_identify_cache(struct target *target)
 				goto done;
 			cache->arch[cl].i_size = decode_cache_reg(cache_reg);
 
-			LOG_DEBUG("instruction cache index %d << %d, way %d << %d",
+			LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
 					cache->arch[cl].i_size.index,
 					cache->arch[cl].i_size.index_shift,
 					cache->arch[cl].i_size.way,
 					cache->arch[cl].i_size.way_shift);
 
-			LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
+			LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
 					cache->arch[cl].i_size.linelen,
 					cache->arch[cl].i_size.cachesize,
 					cache->arch[cl].i_size.associativity);
diff --git a/src/target/armv7a_cache.h b/src/target/armv7a_cache.h
index e0f7eb3a5..8d8ca2d7d 100644
--- a/src/target/armv7a_cache.h
+++ b/src/target/armv7a_cache.h
@@ -25,7 +25,7 @@
 int armv7a_l1_d_cache_clean_virt(struct target *target, uint32_t virt,
 					unsigned int size);
 int armv7a_l1_d_cache_inval_virt(struct target *target, uint32_t virt,
-					unsigned int size);
+					uint32_t size);
 int armv7a_l1_d_cache_flush_virt(struct target *target, uint32_t virt,
 					unsigned int size);
 int armv7a_l1_i_cache_inval_all(struct target *target);
diff --git a/src/target/armv7a_cache_l2x.c b/src/target/armv7a_cache_l2x.c
index 3b20fd870..3607a5122 100644
--- a/src/target/armv7a_cache_l2x.c
+++ b/src/target/armv7a_cache_l2x.c
@@ -185,7 +185,7 @@ static int arm7a_handle_l2x_cache_info_command(struct command_invocation *cmd,
 	}
 
 	command_print(cmd,
-		      "L2 unified cache Base Address 0x%" PRIx32 ", %" PRId32 " ways",
+		      "L2 unified cache Base Address 0x%" PRIx32 ", %" PRIu32 " ways",
 		      l2x_cache->base, l2x_cache->way);
 
 	return ERROR_OK;
diff --git a/src/target/armv7a_mmu.c b/src/target/armv7a_mmu.c
index eec14a36f..b4234b24e 100644
--- a/src/target/armv7a_mmu.c
+++ b/src/target/armv7a_mmu.c
@@ -266,7 +266,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
 		uint32_t first_lvl_descriptor = target_buffer_get_u32(target,
 						(uint8_t *)&first_lvl_ptbl[pt_idx]);
 
-		LOG_DEBUG("L1 desc[%8.8"PRIx32"]: %8.8"PRIx32, pt_idx << 20, first_lvl_descriptor);
+		LOG_DEBUG("L1 desc[%8.8x]: %8.8"PRIx32, pt_idx << 20, first_lvl_descriptor);
 
 		/* skip empty entries in the first level table */
 		if ((first_lvl_descriptor & 3) == 0) {
diff --git a/src/target/armv8.c b/src/target/armv8.c
index e47f6599a..ab60cd371 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -1054,7 +1054,7 @@ COMMAND_HANDLER(armv8_handle_exception_catch_command)
 			nsec = n->name;
 
 		if (sec == NULL || nsec == NULL) {
-			LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02x", edeccr & 0xff);
+			LOG_WARNING("Exception Catch: unknown exception catch configuration: EDECCR = %02" PRIx32, edeccr & 0xff);
 			return ERROR_FAIL;
 		}
 
diff --git a/src/target/armv8_cache.c b/src/target/armv8_cache.c
index 41c85c9ab..86e4a5961 100644
--- a/src/target/armv8_cache.c
+++ b/src/target/armv8_cache.c
@@ -203,10 +203,10 @@ static int armv8_handle_inner_cache_info_command(struct command_invocation *cmd,
 
 		if (arch->ctype & 1) {
 			command_print(cmd,
-				"L%d I-Cache: linelen %" PRIi32
-				", associativity %" PRIi32
-				", nsets %" PRIi32
-				", cachesize %" PRId32 " KBytes",
+				"L%d I-Cache: linelen %" PRIu32
+				", associativity %" PRIu32
+				", nsets %" PRIu32
+				", cachesize %" PRIu32 " KBytes",
 				cl+1,
 				arch->i_size.linelen,
 				arch->i_size.associativity,
@@ -216,10 +216,10 @@ static int armv8_handle_inner_cache_info_command(struct command_invocation *cmd,
 
 		if (arch->ctype >= 2) {
 			command_print(cmd,
-				"L%d D-Cache: linelen %" PRIi32
-				", associativity %" PRIi32
-				", nsets %" PRIi32
-				", cachesize %" PRId32 " KBytes",
+				"L%d D-Cache: linelen %" PRIu32
+				", associativity %" PRIu32
+				", nsets %" PRIu32
+				", cachesize %" PRIu32 " KBytes",
 				cl+1,
 				arch->d_u_size.linelen,
 				arch->d_u_size.associativity,
@@ -336,7 +336,7 @@ int armv8_identify_cache(struct armv8_common *armv8)
 
 	cache->iminline = 4UL << (ctr & 0xf);
 	cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
-	LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRId32 " ctr.dminline %" PRId32,
+	LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
 		 ctr, cache->iminline, cache->dminline);
 
 	/*  retrieve CLIDR */
@@ -373,13 +373,13 @@ int armv8_identify_cache(struct armv8_common *armv8)
 				goto done;
 			cache->arch[cl].d_u_size = decode_cache_reg(cache_reg);
 
-			LOG_DEBUG("data/unified cache index %d << %d, way %d << %d",
+			LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
 					cache->arch[cl].d_u_size.index,
 					cache->arch[cl].d_u_size.index_shift,
 					cache->arch[cl].d_u_size.way,
 					cache->arch[cl].d_u_size.way_shift);
 
-			LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
+			LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
 					cache->arch[cl].d_u_size.linelen,
 					cache->arch[cl].d_u_size.cachesize,
 					cache->arch[cl].d_u_size.associativity);
@@ -393,13 +393,13 @@ int armv8_identify_cache(struct armv8_common *armv8)
 				goto done;
 			cache->arch[cl].i_size = decode_cache_reg(cache_reg);
 
-			LOG_DEBUG("instruction cache index %d << %d, way %d << %d",
+			LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
 					cache->arch[cl].i_size.index,
 					cache->arch[cl].i_size.index_shift,
 					cache->arch[cl].i_size.way,
 					cache->arch[cl].i_size.way_shift);
 
-			LOG_DEBUG("cacheline %d bytes %d KBytes asso %d ways",
+			LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
 					cache->arch[cl].i_size.linelen,
 					cache->arch[cl].i_size.cachesize,
 					cache->arch[cl].i_size.associativity);
diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index 90cf4e059..1e88a445f 100644
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -253,11 +253,11 @@ static int dpmv8_exec_opcode(struct arm_dpm *dpm,
 	/* update dscr and el after each command execution */
 	dpm->dscr = dscr;
 	if (dpm->last_el != ((dscr >> 8) & 3))
-		LOG_DEBUG("EL %i -> %i", dpm->last_el, (dscr >> 8) & 3);
+		LOG_DEBUG("EL %i -> %" PRIu32, dpm->last_el, (dscr >> 8) & 3);
 	dpm->last_el = (dscr >> 8) & 3;
 
 	if (dscr & DSCR_ERR) {
-		LOG_ERROR("Opcode 0x%08"PRIx32", DSCR.ERR=1, DSCR.EL=%i", opcode, dpm->last_el);
+		LOG_ERROR("Opcode 0x%08" PRIx32 ", DSCR.ERR=1, DSCR.EL=%i", opcode, dpm->last_el);
 		armv8_dpm_handle_exception(dpm, true);
 		retval = ERROR_FAIL;
 	}
@@ -560,7 +560,7 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
 		LOG_DEBUG("restoring mode, cpsr = 0x%08"PRIx32, cpsr);
 
 	} else {
-		LOG_DEBUG("setting mode 0x%"PRIx32, mode);
+		LOG_DEBUG("setting mode 0x%x", mode);
 		cpsr = mode;
 	}
 
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index aeeb11626..bd8e49fd9 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -2498,7 +2498,7 @@ static int cortex_a_read_phys_memory(struct target *target,
 	if (!count || !buffer)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	LOG_DEBUG("Reading memory at real address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
+	LOG_DEBUG("Reading memory at real address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
 		address, size, count);
 
 	/* read memory through the CPU */
@@ -2515,7 +2515,7 @@ static int cortex_a_read_memory(struct target *target, target_addr_t address,
 	int retval;
 
 	/* cortex_a handles unaligned memory access */
-	LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
+	LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
 		address, size, count);
 
 	cortex_a_prep_memaccess(target, 0);
@@ -2534,7 +2534,7 @@ static int cortex_a_write_phys_memory(struct target *target,
 	if (!count || !buffer)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	LOG_DEBUG("Writing memory to real address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
+	LOG_DEBUG("Writing memory to real address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
 		address, size, count);
 
 	/* write memory through the CPU */
@@ -2551,7 +2551,7 @@ static int cortex_a_write_memory(struct target *target, target_addr_t address,
 	int retval;
 
 	/* cortex_a handles unaligned memory access */
-	LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRId32 "; count %" PRId32,
+	LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
 		address, size, count);
 
 	/* memory writes bypass the caches, must flush before writing */
diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c
index 3d4c61ae6..b825429e0 100644
--- a/src/target/dsp563xx.c
+++ b/src/target/dsp563xx.c
@@ -937,7 +937,7 @@ static int dsp563xx_examine(struct target *target)
 		if (((chip>>5)&0x1f) == 0)
 			chip += 300;
 
-		LOG_INFO("DSP56%03" PRId32 " device found", chip);
+		LOG_INFO("DSP56%03" PRIu32 " device found", chip);
 
 		/* Clear all breakpoints */
 		dsp563xx_once_reg_write(target->tap, 1, DSP563XX_ONCE_OBCR, 0);
diff --git a/src/target/esirisc_jtag.c b/src/target/esirisc_jtag.c
index 700ae3a60..7fd35e5fd 100644
--- a/src/target/esirisc_jtag.c
+++ b/src/target/esirisc_jtag.c
@@ -181,8 +181,8 @@ static int esirisc_jtag_check_status(struct esirisc_jtag *jtag_info)
 {
 	uint8_t eid = esirisc_jtag_get_eid(jtag_info);
 	if (eid != EID_NONE) {
-		LOG_ERROR("esirisc_jtag: bad status: 0x%02" PRIx32 " (DA: %" PRId32 ", "
-				"S: %" PRId32 ", EID: 0x%02" PRIx32 ")",
+		LOG_ERROR("esirisc_jtag: bad status: 0x%02" PRIx8 " (DA: %" PRId32 ", "
+				"S: %" PRId32 ", EID: 0x%02" PRIx8 ")",
 				jtag_info->status, esirisc_jtag_is_debug_active(jtag_info),
 				esirisc_jtag_is_stopped(jtag_info), eid);
 		return ERROR_FAIL;
@@ -201,13 +201,13 @@ static int esirisc_jtag_send_and_recv(struct esirisc_jtag *jtag_info, uint8_t co
 
 	retval = esirisc_jtag_send(jtag_info, command, num_out_fields, out_fields);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("esirisc_jtag: send failed (command: 0x%02" PRIx32 ")", command);
+		LOG_ERROR("esirisc_jtag: send failed (command: 0x%02" PRIx8 ")", command);
 		return ERROR_FAIL;
 	}
 
 	retval = esirisc_jtag_recv(jtag_info, num_in_fields, in_fields);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("esirisc_jtag: recv failed (command: 0x%02" PRIx32 ")", command);
+		LOG_ERROR("esirisc_jtag: recv failed (command: 0x%02" PRIx8 ")", command);
 		return ERROR_FAIL;
 	}
 
@@ -409,7 +409,7 @@ int esirisc_jtag_read_reg(struct esirisc_jtag *jtag_info, uint8_t reg, uint32_t
 		return retval;
 
 	*data = le_to_h_u32(d);
-	LOG_DEBUG("register: 0x%" PRIx32 ", data: 0x%" PRIx32, reg, *data);
+	LOG_DEBUG("register: 0x%" PRIx8 ", data: 0x%" PRIx32, reg, *data);
 
 	return ERROR_OK;
 }
@@ -419,7 +419,7 @@ int esirisc_jtag_write_reg(struct esirisc_jtag *jtag_info, uint8_t reg, uint32_t
 	struct scan_field out_fields[2];
 	uint8_t d[4];
 
-	LOG_DEBUG("register: 0x%" PRIx32 ", data: 0x%" PRIx32, reg, data);
+	LOG_DEBUG("register: 0x%" PRIx8 ", data: 0x%" PRIx32, reg, data);
 
 	out_fields[0].num_bits = 8;
 	out_fields[0].out_value = &reg;
@@ -457,7 +457,7 @@ int esirisc_jtag_read_csr(struct esirisc_jtag *jtag_info, uint8_t bank, uint8_t
 		return retval;
 
 	*data = le_to_h_u32(d);
-	LOG_DEBUG("bank: 0x%" PRIx32 ", csr: 0x%" PRIx32 ", data: 0x%" PRIx32, bank, csr, *data);
+	LOG_DEBUG("bank: 0x%" PRIx8 ", csr: 0x%" PRIx8 ", data: 0x%" PRIx32, bank, csr, *data);
 
 	return ERROR_OK;
 }
@@ -467,7 +467,7 @@ int esirisc_jtag_write_csr(struct esirisc_jtag *jtag_info, uint8_t bank, uint8_t
 	struct scan_field out_fields[2];
 	uint8_t c[2], d[4];
 
-	LOG_DEBUG("bank: 0x%" PRIx32 ", csr: 0x%" PRIx32 ", data: 0x%" PRIx32, bank, csr, data);
+	LOG_DEBUG("bank: 0x%" PRIx8 ", csr: 0x%" PRIx8 ", data: 0x%" PRIx32, bank, csr, data);
 
 	out_fields[0].num_bits = 16;
 	out_fields[0].out_value = c;
diff --git a/src/target/esirisc_trace.c b/src/target/esirisc_trace.c
index 6a7d5a29d..28d7536af 100644
--- a/src/target/esirisc_trace.c
+++ b/src/target/esirisc_trace.c
@@ -461,7 +461,7 @@ static int esirisc_trace_analyze_full(struct command_invocation *cmd, uint8_t *b
 						if (retval != ERROR_OK)
 							goto fail;
 
-						command_print(cmd, "repeats %" PRId32 " %s", count,
+						command_print(cmd, "repeats %" PRIu32 " %s", count,
 								(count == 1) ? "time" : "times");
 						break;
 					}
@@ -470,13 +470,13 @@ static int esirisc_trace_analyze_full(struct command_invocation *cmd, uint8_t *b
 						return ERROR_OK;
 
 					default:
-						command_print(cmd, "invalid extended trace ID: %" PRId32, ext_id);
+						command_print(cmd, "invalid extended trace ID: %" PRIu32, ext_id);
 						return ERROR_FAIL;
 				}
 				break;
 			}
 			default:
-				command_print(cmd, "invalid trace ID: %" PRId32, id);
+				command_print(cmd, "invalid trace ID: %" PRIu32, id);
 				return ERROR_FAIL;
 		}
 	}
@@ -729,7 +729,7 @@ COMMAND_HANDLER(handle_esirisc_trace_info_command)
 
 	command_print(CMD, "trigger delay: %s",
 			esirisc_trace_delay_strings[trace_info->delay]);
-	command_print(CMD, "trigger delay cycles: %i", trace_info->delay_cycles);
+	command_print(CMD, "trigger delay cycles: %" PRIu32, trace_info->delay_cycles);
 
 	return ERROR_OK;
 }
diff --git a/src/target/ls1_sap.c b/src/target/ls1_sap.c
index 330042f00..5e1218837 100644
--- a/src/target/ls1_sap.c
+++ b/src/target/ls1_sap.c
@@ -182,7 +182,7 @@ static int ls1_sap_read_memory(struct target *target, target_addr_t address,
 			       uint32_t size, uint32_t count, uint8_t *buffer)
 {
 	LOG_DEBUG("Reading memory at physical address 0x%" TARGET_PRIxADDR
-		  "; size %" PRId32 "; count %" PRId32, address, size, count);
+		  "; size %" PRIu32 "; count %" PRIu32, address, size, count);
 
 	if (count == 0 || buffer == NULL)
 		return ERROR_COMMAND_SYNTAX_ERROR;
@@ -204,7 +204,7 @@ static int ls1_sap_write_memory(struct target *target, target_addr_t address,
 				const uint8_t *buffer)
 {
 	LOG_DEBUG("Writing memory at physical address 0x%" TARGET_PRIxADDR
-		  "; size %" PRId32 "; count %" PRId32, address, size, count);
+		  "; size %" PRIu32 "; count %" PRIu32, address, size, count);
 
 
 	if (count == 0 || buffer == NULL)
diff --git a/src/target/mem_ap.c b/src/target/mem_ap.c
index ade48b6d7..7ed41c63c 100644
--- a/src/target/mem_ap.c
+++ b/src/target/mem_ap.c
@@ -150,7 +150,7 @@ static int mem_ap_read_memory(struct target *target, target_addr_t address,
 	struct mem_ap *mem_ap = target->arch_info;
 
 	LOG_DEBUG("Reading memory at physical address " TARGET_ADDR_FMT
-		  "; size %" PRId32 "; count %" PRId32, address, size, count);
+		  "; size %" PRIu32 "; count %" PRIu32, address, size, count);
 
 	if (count == 0 || buffer == NULL)
 		return ERROR_COMMAND_SYNTAX_ERROR;
@@ -165,7 +165,7 @@ static int mem_ap_write_memory(struct target *target, target_addr_t address,
 	struct mem_ap *mem_ap = target->arch_info;
 
 	LOG_DEBUG("Writing memory at physical address " TARGET_ADDR_FMT
-		  "; size %" PRId32 "; count %" PRId32, address, size, count);
+		  "; size %" PRIu32 "; count %" PRIu32, address, size, count);
 
 	if (count == 0 || buffer == NULL)
 		return ERROR_COMMAND_SYNTAX_ERROR;
diff --git a/src/target/mips32.c b/src/target/mips32.c
index ef7f2ad26..e1f2b2832 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -725,7 +725,7 @@ int mips32_read_config_regs(struct target *target)
 	else
 		return ERROR_OK;	/* already successfully read */
 
-	LOG_DEBUG("read  %"PRId32" config registers", ejtag_info->config_regs);
+	LOG_DEBUG("read  %"PRIu32" config registers", ejtag_info->config_regs);
 
 	if (ejtag_info->impcode & EJTAG_IMP_MIPS16) {
 		mips32->isa_imp = MIPS32_MIPS16;
@@ -950,11 +950,11 @@ COMMAND_HANDLER(mips32_handle_cp0_command)
 			retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
 			if (retval != ERROR_OK) {
 				command_print(CMD,
-						"couldn't access reg %" PRIi32,
+						"couldn't access reg %" PRIu32,
 						cp0_reg);
 				return ERROR_OK;
 			}
-			command_print(CMD, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+			command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
 					cp0_reg, cp0_sel, value);
 
 		} else if (CMD_ARGC == 3) {
@@ -963,11 +963,11 @@ COMMAND_HANDLER(mips32_handle_cp0_command)
 			retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
 			if (retval != ERROR_OK) {
 				command_print(CMD,
-						"couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
+						"couldn't access cp0 reg %" PRIu32 ", select %" PRIu32,
 						cp0_reg,  cp0_sel);
 				return ERROR_OK;
 			}
-			command_print(CMD, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+			command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
 					cp0_reg, cp0_sel, value);
 		}
 	}
diff --git a/src/target/mips64_pracc.c b/src/target/mips64_pracc.c
index b19fd044e..3080046f3 100644
--- a/src/target/mips64_pracc.c
+++ b/src/target/mips64_pracc.c
@@ -221,7 +221,7 @@ int mips64_pracc_exec(struct mips_ejtag *ejtag_info,
 	unsigned i;
 
 	for (i = 0; i < code_len; i++)
-		LOG_DEBUG("%08x", code[i]);
+		LOG_DEBUG("%08" PRIx32, code[i]);
 
 	ctx.local_iparam = param_in;
 	ctx.local_oparam = param_out;
@@ -247,7 +247,7 @@ int mips64_pracc_exec(struct mips_ejtag *ejtag_info,
 
 		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 		mips_ejtag_drscan_32(ejtag_info, &address32);
-		LOG_DEBUG("-> %08x", address32);
+		LOG_DEBUG("-> %08" PRIx32, address32);
 		address = 0xffffffffff200000ull | address32;
 
 		int psz = (ejtag_ctrl >> 29) & 3;
@@ -1349,7 +1349,7 @@ int mips64_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info,
 
 	LOG_DEBUG("%s using " TARGET_ADDR_FMT " for write handler", __func__,
 		  source->address);
-	LOG_DEBUG("daddiu: %08x", handler_code[11]);
+	LOG_DEBUG("daddiu: %08" PRIx32, handler_code[11]);
 
 	jmp_code[0] |= UPPER16(source->address);
 	jmp_code[1] |= LOWER16(source->address);
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index d1d094520..85eea932d 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -1309,11 +1309,11 @@ COMMAND_HANDLER(mips_m4k_handle_cp0_command)
 			retval = mips32_cp0_read(ejtag_info, &value, cp0_reg, cp0_sel);
 			if (retval != ERROR_OK) {
 				command_print(CMD,
-						"couldn't access reg %" PRIi32,
+						"couldn't access reg %" PRIu32,
 						cp0_reg);
 				return ERROR_OK;
 			}
-			command_print(CMD, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+			command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
 					cp0_reg, cp0_sel, value);
 
 		} else if (CMD_ARGC == 3) {
@@ -1322,11 +1322,11 @@ COMMAND_HANDLER(mips_m4k_handle_cp0_command)
 			retval = mips32_cp0_write(ejtag_info, value, cp0_reg, cp0_sel);
 			if (retval != ERROR_OK) {
 				command_print(CMD,
-						"couldn't access cp0 reg %" PRIi32 ", select %" PRIi32,
+						"couldn't access cp0 reg %" PRIu32 ", select %" PRIu32,
 						cp0_reg,  cp0_sel);
 				return ERROR_OK;
 			}
-			command_print(CMD, "cp0 reg %" PRIi32 ", select %" PRIi32 ": %8.8" PRIx32,
+			command_print(CMD, "cp0 reg %" PRIu32 ", select %" PRIu32 ": %8.8" PRIx32,
 					cp0_reg, cp0_sel, value);
 		}
 	}
diff --git a/src/target/mips_mips64.c b/src/target/mips_mips64.c
index 3a592f7f3..f941af517 100644
--- a/src/target/mips_mips64.c
+++ b/src/target/mips_mips64.c
@@ -247,7 +247,7 @@ static int mips_mips64_set_hwbp(struct target *target, struct breakpoint *bp)
 		bp_num++;
 
 	if (bp_num >= mips64->num_inst_bpoints) {
-		LOG_DEBUG("ERROR Can not find free FP Comparator(bpid: %d)",
+		LOG_DEBUG("ERROR Can not find free FP Comparator(bpid: %" PRIu32 ")",
 			  bp->unique_id);
 		LOG_WARNING("ERROR Can not find free FP Comparator");
 		exit(-1);
@@ -274,7 +274,7 @@ static int mips_mips64_set_hwbp(struct target *target, struct breakpoint *bp)
 	if (retval != ERROR_OK)
 		return retval;
 
-	LOG_DEBUG("bpid: %d, bp_num %i bp_value 0x%" PRIx64 "", bp->unique_id,
+	LOG_DEBUG("bpid: %" PRIu32 ", bp_num %i bp_value 0x%" PRIx64, bp->unique_id,
 		  bp_num, c->bp_value);
 
 	return ERROR_OK;
@@ -354,7 +354,7 @@ static int mips_mips64_set_breakpoint(struct target *target,
 	if (bp->type == BKPT_HARD) {
 		retval = mips_mips64_set_hwbp(target, bp);
 	} else {
-		LOG_DEBUG("bpid: %d", bp->unique_id);
+		LOG_DEBUG("bpid: %" PRIu32, bp->unique_id);
 
 		switch (bp->length) {
 		case MIPS64_SDBBP_SIZE:
@@ -511,12 +511,12 @@ static int mips_mips64_unset_hwbp(struct target *target, struct breakpoint *bp)
 	bp_num = bp->set - 1;
 
 	if ((bp_num < 0) || (bp_num >= mips64->num_inst_bpoints)) {
-		LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %d)",
+		LOG_DEBUG("Invalid FP Comparator number in breakpoint (bpid: %" PRIu32 ")",
 			  bp->unique_id);
 		return ERROR_OK;
 	}
 
-	LOG_DEBUG("bpid: %d - releasing hw: %d", bp->unique_id, bp_num);
+	LOG_DEBUG("bpid: %" PRIu32 " - releasing hw: %d", bp->unique_id, bp_num);
 	comparator_list[bp_num].used = false;
 	comparator_list[bp_num].bp_value = 0;
 
@@ -576,7 +576,7 @@ static int mips_mips64_unset_breakpoint(struct target *target,
 	if (bp->type == BKPT_HARD) {
 		retval = mips_mips64_unset_hwbp(target, bp);
 	} else {
-		LOG_DEBUG("bpid: %d", bp->unique_id);
+		LOG_DEBUG("bpid: %" PRIu32, bp->unique_id);
 
 		switch (bp->length) {
 		case MIPS64_SDBBP_SIZE:
diff --git a/src/target/nds32_reg.c b/src/target/nds32_reg.c
index 7cefcb1a2..034a07584 100644
--- a/src/target/nds32_reg.c
+++ b/src/target/nds32_reg.c
@@ -367,7 +367,7 @@ bool nds32_reg_exception(uint32_t number, uint32_t value)
 			field_value = (value >> ex_reg_value->ex_value_bit_pos) &
 				ex_reg_value->ex_value_mask;
 			if (field_value == ex_reg_value->ex_value) {
-				LOG_WARNING("It will generate exceptions as setting %" PRId32 " to %s",
+				LOG_WARNING("It will generate exceptions as setting %" PRIu32 " to %s",
 						value, nds32_regs[number].simple_mnemonic);
 				return true;
 			}
diff --git a/src/target/openrisc/or1k.c b/src/target/openrisc/or1k.c
index aa7b0d332..71491119b 100644
--- a/src/target/openrisc/or1k.c
+++ b/src/target/openrisc/or1k.c
@@ -923,7 +923,7 @@ static int or1k_add_breakpoint(struct target *target,
 	struct or1k_du *du_core = or1k_to_du(or1k);
 	uint8_t data;
 
-	LOG_DEBUG("Adding breakpoint: addr 0x%08" TARGET_PRIxADDR ", len %d, type %d, set: %d, id: %" PRId32,
+	LOG_DEBUG("Adding breakpoint: addr 0x%08" TARGET_PRIxADDR ", len %d, type %d, set: %d, id: %" PRIu32,
 		  breakpoint->address, breakpoint->length, breakpoint->type,
 		  breakpoint->set, breakpoint->unique_id);
 
@@ -982,7 +982,7 @@ static int or1k_remove_breakpoint(struct target *target,
 	struct or1k_common *or1k = target_to_or1k(target);
 	struct or1k_du *du_core = or1k_to_du(or1k);
 
-	LOG_DEBUG("Removing breakpoint: addr 0x%08" TARGET_PRIxADDR ", len %d, type %d, set: %d, id: %" PRId32,
+	LOG_DEBUG("Removing breakpoint: addr 0x%08" TARGET_PRIxADDR ", len %d, type %d, set: %d, id: %" PRIu32,
 		  breakpoint->address, breakpoint->length, breakpoint->type,
 		  breakpoint->set, breakpoint->unique_id);
 
diff --git a/src/target/openrisc/or1k_du_adv.c b/src/target/openrisc/or1k_du_adv.c
index d5e740d5d..afc773f56 100644
--- a/src/target/openrisc/or1k_du_adv.c
+++ b/src/target/openrisc/or1k_du_adv.c
@@ -869,7 +869,7 @@ static int or1k_adv_cpu_reset(struct or1k_jtag *jtag_info, int action)
 static int or1k_adv_jtag_read_memory(struct or1k_jtag *jtag_info,
 			    uint32_t addr, uint32_t size, int count, uint8_t *buffer)
 {
-	LOG_DEBUG("Reading WB%" PRId32 " at 0x%08" PRIx32, size * 8, addr);
+	LOG_DEBUG("Reading WB%" PRIu32 " at 0x%08" PRIx32, size * 8, addr);
 
 	int retval;
 	if (!jtag_info->or1k_jtag_inited) {
@@ -924,7 +924,7 @@ static int or1k_adv_jtag_read_memory(struct or1k_jtag *jtag_info,
 static int or1k_adv_jtag_write_memory(struct or1k_jtag *jtag_info,
 			     uint32_t addr, uint32_t size, int count, const uint8_t *buffer)
 {
-	LOG_DEBUG("Writing WB%" PRId32 " at 0x%08" PRIx32, size * 8, addr);
+	LOG_DEBUG("Writing WB%" PRIu32 " at 0x%08" PRIx32, size * 8, addr);
 
 	int retval;
 	if (!jtag_info->or1k_jtag_inited) {
diff --git a/src/target/openrisc/or1k_tap_vjtag.c b/src/target/openrisc/or1k_tap_vjtag.c
index 3372509c9..28366cf53 100644
--- a/src/target/openrisc/or1k_tap_vjtag.c
+++ b/src/target/openrisc/or1k_tap_vjtag.c
@@ -218,7 +218,7 @@ static int or1k_tap_vjtag_init(struct or1k_jtag *jtag_info)
 	LOG_DEBUG("m_width         = %d", m_width);
 	LOG_DEBUG("manufacturer_id = 0x%02" PRIx32, MANUF(hub_info));
 	LOG_DEBUG("nb_of_node      = %d", nb_nodes);
-	LOG_DEBUG("version         = %" PRId32, VER(hub_info));
+	LOG_DEBUG("version         = %" PRIu32, VER(hub_info));
 	LOG_DEBUG("VIR length      = %d", guess_addr_width(nb_nodes) + m_width);
 
 	/* Because the number of SLD nodes is now known, the Nodes on the hub can be
@@ -257,11 +257,11 @@ static int or1k_tap_vjtag_init(struct or1k_jtag *jtag_info)
 
 		LOG_DEBUG("Node info register");
 		LOG_DEBUG("--------------------");
-		LOG_DEBUG("instance_id     = %" PRId32, ID(node_info));
+		LOG_DEBUG("instance_id     = %" PRIu32, ID(node_info));
 		LOG_DEBUG("manufacturer_id = 0x%02" PRIx32, MANUF(node_info));
-		LOG_DEBUG("node_id         = %" PRId32 " (%s)", ID(node_info),
+		LOG_DEBUG("node_id         = %" PRIu32 " (%s)", ID(node_info),
 						       id_to_string(ID(node_info)));
-		LOG_DEBUG("version         = %" PRId32, VER(node_info));
+		LOG_DEBUG("version         = %" PRIu32, VER(node_info));
 
 		if (ID(node_info) == VJTAG_NODE_ID)
 			vjtag_node_address = node_index + 1;
diff --git a/src/target/stm8.c b/src/target/stm8.c
index 4b93dd1fe..78bf6a27a 100644
--- a/src/target/stm8.c
+++ b/src/target/stm8.c
@@ -1308,7 +1308,7 @@ static int stm8_arch_state(struct target *target)
 static int stm8_step(struct target *target, int current,
 		target_addr_t address, int handle_breakpoints)
 {
-	LOG_DEBUG("%" PRIx32 " " TARGET_ADDR_FMT " %" PRIx32,
+	LOG_DEBUG("%x " TARGET_ADDR_FMT " %x",
 		current, address, handle_breakpoints);
 
 	/* get pointers to arch-specific information */
@@ -1969,7 +1969,7 @@ int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi)
 			return e;
 
 		stm8->blocksize = w;
-		LOG_DEBUG("blocksize=%8.8x", stm8->blocksize);
+		LOG_DEBUG("blocksize=%8.8" PRIx32, stm8->blocksize);
 		return JIM_OK;
 	}
 	if (!strcmp(arg, "-flashstart")) {
@@ -1988,7 +1988,7 @@ int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi)
 			return e;
 
 		stm8->flashstart = w;
-		LOG_DEBUG("flashstart=%8.8x", stm8->flashstart);
+		LOG_DEBUG("flashstart=%8.8" PRIx32, stm8->flashstart);
 		return JIM_OK;
 	}
 	if (!strcmp(arg, "-flashend")) {
@@ -2007,7 +2007,7 @@ int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi)
 			return e;
 
 		stm8->flashend = w;
-		LOG_DEBUG("flashend=%8.8x", stm8->flashend);
+		LOG_DEBUG("flashend=%8.8" PRIx32, stm8->flashend);
 		return JIM_OK;
 	}
 	if (!strcmp(arg, "-eepromstart")) {
@@ -2026,7 +2026,7 @@ int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi)
 			return e;
 
 		stm8->eepromstart = w;
-		LOG_DEBUG("eepromstart=%8.8x", stm8->eepromstart);
+		LOG_DEBUG("eepromstart=%8.8" PRIx32, stm8->eepromstart);
 		return JIM_OK;
 	}
 	if (!strcmp(arg, "-eepromend")) {
@@ -2045,7 +2045,7 @@ int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi)
 			return e;
 
 		stm8->eepromend = w;
-		LOG_DEBUG("eepromend=%8.8x", stm8->eepromend);
+		LOG_DEBUG("eepromend=%8.8" PRIx32, stm8->eepromend);
 		return JIM_OK;
 	}
 	if (!strcmp(arg, "-optionstart")) {
@@ -2064,7 +2064,7 @@ int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi)
 			return e;
 
 		stm8->optionstart = w;
-		LOG_DEBUG("optionstart=%8.8x", stm8->optionstart);
+		LOG_DEBUG("optionstart=%8.8" PRIx32, stm8->optionstart);
 		return JIM_OK;
 	}
 	if (!strcmp(arg, "-optionend")) {
@@ -2083,7 +2083,7 @@ int stm8_jim_configure(struct target *target, Jim_GetOptInfo *goi)
 			return e;
 
 		stm8->optionend = w;
-		LOG_DEBUG("optionend=%8.8x", stm8->optionend);
+		LOG_DEBUG("optionend=%8.8" PRIx32, stm8->optionend);
 		return JIM_OK;
 	}
 	if (!strcmp(arg, "-enable_step_irq")) {
diff --git a/src/target/target.c b/src/target/target.c
index affee03b9..a918b3acf 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -2201,7 +2201,7 @@ static int target_profiling_default(struct target *target, uint32_t *samples,
  */
 int target_write_buffer(struct target *target, target_addr_t address, uint32_t size, const uint8_t *buffer)
 {
-	LOG_DEBUG("writing buffer of %" PRIi32 " byte at " TARGET_ADDR_FMT,
+	LOG_DEBUG("writing buffer of %" PRIu32 " byte at " TARGET_ADDR_FMT,
 			  size, address);
 
 	if (!target_was_examined(target)) {
@@ -2263,7 +2263,7 @@ static int target_write_buffer_default(struct target *target,
  */
 int target_read_buffer(struct target *target, target_addr_t address, uint32_t size, uint8_t *buffer)
 {
-	LOG_DEBUG("reading buffer of %" PRIi32 " byte at " TARGET_ADDR_FMT,
+	LOG_DEBUG("reading buffer of %" PRIu32 " byte at " TARGET_ADDR_FMT,
 			  size, address);
 
 	if (!target_was_examined(target)) {
@@ -2333,7 +2333,7 @@ int target_checksum_memory(struct target *target, target_addr_t address, uint32_
 	if (retval != ERROR_OK) {
 		buffer = malloc(size);
 		if (buffer == NULL) {
-			LOG_ERROR("error allocating buffer for section (%" PRId32 " bytes)", size);
+			LOG_ERROR("error allocating buffer for section (%" PRIu32 " bytes)", size);
 			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 		retval = target_read_buffer(target, address, size, buffer);
@@ -4301,7 +4301,7 @@ static int target_mem2array(Jim_Interp *interp, struct target *target, int argc,
 	} else {
 		char buf[100];
 		Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-		sprintf(buf, "mem2array address: 0x%08" PRIx32 " is not aligned for %" PRId32 " byte reads",
+		sprintf(buf, "mem2array address: 0x%08" PRIx32 " is not aligned for %" PRIu32 " byte reads",
 				addr,
 				width);
 		Jim_AppendStrings(interp, Jim_GetResult(interp), buf, NULL);
@@ -4333,7 +4333,7 @@ static int target_mem2array(Jim_Interp *interp, struct target *target, int argc,
 			retval = target_read_memory(target, addr, width, count, buffer);
 		if (retval != ERROR_OK) {
 			/* BOO !*/
-			LOG_ERROR("mem2array: Read @ 0x%08" PRIx32 ", w=%" PRId32 ", cnt=%" PRId32 ", failed",
+			LOG_ERROR("mem2array: Read @ 0x%08" PRIx32 ", w=%" PRIu32 ", cnt=%" PRIu32 ", failed",
 					  addr,
 					  width,
 					  count);
@@ -4507,7 +4507,7 @@ static int target_array2mem(Jim_Interp *interp, struct target *target,
 	} else {
 		char buf[100];
 		Jim_SetResult(interp, Jim_NewEmptyStringObj(interp));
-		sprintf(buf, "array2mem address: 0x%08" PRIx32 " is not aligned for %" PRId32 " byte reads",
+		sprintf(buf, "array2mem address: 0x%08" PRIx32 " is not aligned for %" PRIu32 " byte reads",
 				addr,
 				width);
 		Jim_AppendStrings(interp, Jim_GetResult(interp), buf, NULL);
@@ -4556,7 +4556,7 @@ static int target_array2mem(Jim_Interp *interp, struct target *target,
 			retval = target_write_memory(target, addr, width, count, buffer);
 		if (retval != ERROR_OK) {
 			/* BOO !*/
-			LOG_ERROR("array2mem: Write @ 0x%08" PRIx32 ", w=%" PRId32 ", cnt=%" PRId32 ", failed",
+			LOG_ERROR("array2mem: Write @ 0x%08" PRIx32 ", w=%" PRIu32 ", cnt=%" PRIu32 ", failed",
 					  addr,
 					  width,
 					  count);

commit e66593f8242d49dd05f6b9c4a5121fa466a158aa
Author: Antonio Borneo <bor...@gm...>
Date:   Tue Aug 18 18:56:03 2020 +0200

    flash: use proper format with uint32_t
    
    Modify the format strings to properly handle uint32_t data types.
    
    Change the type of variable retval in 'nor/ambiqmicro.c' to match
    both the value to carry and the returned type of the function.
    
    Fix the prototype mismatch of function lpc2900_address2sector()
    between the header and the C file.
    
    Change-Id: I68ffba9bd83eec8132f83bff3af993861fd09d84
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5816
    Tested-by: jenkins

diff --git a/src/flash/nand/mx3.c b/src/flash/nand/mx3.c
index abeaf159c..b9f5ff1b9 100644
--- a/src/flash/nand/mx3.c
+++ b/src/flash/nand/mx3.c
@@ -40,7 +40,7 @@ get_next_halfword_from_sram_buffer() not tested
 static const char target_not_halted_err_msg[] =
 		"target must be halted to use mx3 NAND flash controller";
 static const char data_block_size_err_msg[] =
-		"minimal granularity is one half-word, %" PRId32 " is incorrect";
+		"minimal granularity is one half-word, %" PRIu32 " is incorrect";
 static const char sram_buffer_bounds_err_msg[] =
 		"trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
 static const char get_status_register_err_msg[] = "can't get NAND status";
diff --git a/src/flash/nand/mxc.c b/src/flash/nand/mxc.c
index bc2ae9324..2c5de0394 100644
--- a/src/flash/nand/mxc.c
+++ b/src/flash/nand/mxc.c
@@ -65,7 +65,7 @@
 static const char target_not_halted_err_msg[] =
 	"target must be halted to use mxc NAND flash controller";
 static const char data_block_size_err_msg[] =
-	"minimal granularity is one half-word, %" PRId32 " is incorrect";
+	"minimal granularity is one half-word, %" PRIu32 " is incorrect";
 static const char sram_buffer_bounds_err_msg[] =
 	"trying to access out of SRAM buffer bound (addr=0x%" PRIx32 ")";
 static const char get_status_register_err_msg[] = "can't get NAND status";
diff --git a/src/flash/nand/tcl.c b/src/flash/nand/tcl.c
index 5480e0d61..ca8b9dad4 100644
--- a/src/flash/nand/tcl.c
+++ b/src/flash/nand/tcl.c
@@ -124,7 +124,7 @@ COMMAND_HANDLER(handle_nand_info_command)
 			bad_state = " (block condition unknown)";
 
 		command_print(CMD,
-			"\t#%i: 0x%8.8" PRIx32 " (%" PRId32 "kB) %s%s",
+			"\t#%i: 0x%8.8" PRIx32 " (%" PRIu32 "kB) %s%s",
 			j,
 			p->blocks[j].offset,
 			p->blocks[j].size / 1024,
diff --git a/src/flash/nor/aducm360.c b/src/flash/nor/aducm360.c
index 5e0a666ea..4e816fd61 100644
--- a/src/flash/nor/aducm360.c
+++ b/src/flash/nor/aducm360.c
@@ -285,7 +285,7 @@ static int aducm360_write_block_sync(
 
 		res = buf_get_u32(reg_params[4].value, 0, 32);
 		if (res) {
-			LOG_ERROR("aducm360 fast sync algorithm reports an error (%02X)", res);
+			LOG_ERROR("aducm360 fast sync algorithm reports an error (%02" PRIX32 ")", res);
 			retval = ERROR_FAIL;
 			break;
 		}
@@ -401,7 +401,7 @@ static int aducm360_write_block_async(
 	} else {
 		res = buf_get_u32(reg_params[4].value, 0, 32);	/*RESULT*/
 		if (res) {
-			LOG_ERROR("aducm360 fast async algorithm reports an error (%02X)", res);
+			LOG_ERROR("aducm360 fast async algorithm reports an error (%02" PRIX32 ")", res);
 			retval = ERROR_FAIL;
 		}
 	}
diff --git a/src/flash/nor/ambiqmicro.c b/src/flash/nor/ambiqmicro.c
index 28dc42d82..1c4dce87d 100644
--- a/src/flash/nor/ambiqmicro.c
+++ b/src/flash/nor/ambiqmicro.c
@@ -212,7 +212,7 @@ static int ambiqmicro_read_part_info(struct flash_bank *bank)
 		/* Set PartNum to default device */
 		PartNum = 0;
 	}
-	LOG_DEBUG("Part number: 0x%x", PartNum);
+	LOG_DEBUG("Part number: 0x%" PRIx32, PartNum);
 
 	/*
 	 * Determine device class.
@@ -260,7 +260,7 @@ static int ambiqmicro_read_part_info(struct flash_bank *bank)
 		ambiqmicro_info->target_name =
 			ambiqmicroParts[0].partname;
 
-	LOG_DEBUG("num_pages: %d, pagesize: %d, flash: %d, sram: %d",
+	LOG_DEBUG("num_pages: %" PRIu32 ", pagesize: %" PRIu32 ", flash: %" PRIu32 ", sram: %" PRIu32,
 		ambiqmicro_info->num_pages,
 		ambiqmicro_info->pagesize,
 		ambiqmicro_info->flshsiz,
@@ -304,7 +304,7 @@ static int check_flash_status(struct target *target, uint32_t address)
 	}
 	/* target flash failed, unknown cause. */
 	if (retflash != 0) {
-		LOG_ERROR("Flash not happy: status(0x%x)", retflash);
+		LOG_ERROR("Flash not happy: status(0x%" PRIx32 ")", retflash);
 		return ERROR_FLASH_OPERATION_FAILED;
 	}
 	return ERROR_OK;
@@ -432,7 +432,7 @@ static int ambiqmicro_erase(struct flash_bank *bank, unsigned int first,
 {
 	struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
 	struct target *target = bank->target;
-	uint32_t retval = ERROR_OK;
+	int retval;
 
 	if (bank->target->state != TARGET_HALTED) {
 		LOG_ERROR("Target not halted");
@@ -615,7 +615,7 @@ static int ambiqmicro_write_block(struct flash_bank *bank,
 			break;
 		}
 
-		LOG_DEBUG("address = 0x%08x", address);
+		LOG_DEBUG("address = 0x%08" PRIx32, address);
 
 		retval = ambiqmicro_exec_command(target, FLASH_PROGRAM_MAIN_FROM_SRAM, 0x1000000c);
 		CHECK_STATUS(retval, "error executing ambiqmicro flash write algorithm");
@@ -641,7 +641,7 @@ static int ambiqmicro_write_block(struct flash_bank *bank,
 static int ambiqmicro_write(struct flash_bank *bank, const uint8_t *buffer,
 	uint32_t offset, uint32_t count)
 {
-	uint32_t retval;
+	int retval;
 
 	/* try using a block write */
 	retval = ambiqmicro_write_block(bank, buffer, offset, count);
@@ -654,7 +654,7 @@ static int ambiqmicro_write(struct flash_bank *bank, const uint8_t *buffer,
 static int ambiqmicro_probe(struct flash_bank *bank)
 {
 	struct ambiqmicro_flash_bank *ambiqmicro_info = bank->driver_priv;
-	uint32_t retval;
+	int retval;
 
 	/* If this is a ambiqmicro chip, it has flash; probe() is just
 	 * to figure out how much is present.  Only do it once.
@@ -698,7 +698,7 @@ static int ambiqmicro_otp_program(struct flash_bank *bank,
 {
 	struct target *target = NULL;
 	struct ambiqmicro_flash_bank *ambiqmicro_info = NULL;
-	uint32_t retval = ERROR_OK;
+	int retval;
 
 	ambiqmicro_info = bank->driver_priv;
 	target = bank->target;
@@ -757,7 +757,7 @@ static int ambiqmicro_otp_program(struct flash_bank *bank,
 	/*
 	 * Program OTP.
 	 */
-	LOG_INFO("Programming OTP offset 0x%08x", offset);
+	LOG_INFO("Programming OTP offset 0x%08" PRIx32, offset);
 
 	/*
 	 * passed pc, addr = ROM function, handle breakpoints, not debugging.
@@ -778,7 +778,7 @@ COMMAND_HANDLER(ambiqmicro_handle_mass_erase_command)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
 	struct flash_bank *bank;
-	uint32_t retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 	if (ERROR_OK != retval)
 		return retval;
 
@@ -798,7 +798,7 @@ COMMAND_HANDLER(ambiqmicro_handle_page_erase_command)
 {
 	struct flash_bank *bank;
 	uint32_t first, last;
-	uint32_t retval;
+	int retval;
 
 	if (CMD_ARGC < 3)
 		return ERROR_COMMAND_SYNTAX_ERROR;
@@ -826,7 +826,7 @@ COMMAND_HANDLER(ambiqmicro_handle_program_otp_command)
 {
 	struct flash_bank *bank;
 	uint32_t offset, count;
-	uint32_t retval;
+	int retval;
 
 	if (CMD_ARGC < 3)
 		return ERROR_COMMAND_SYNTAX_ERROR;
@@ -834,7 +834,7 @@ COMMAND_HANDLER(ambiqmicro_handle_program_otp_command)
 	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], offset);
 	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], count);
 
-	command_print(CMD, "offset=0x%08x count=%d", offset, count);
+	command_print(CMD, "offset=0x%08" PRIx32 " count=%" PRIu32, offset, count);
 
 	CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
 
diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c
index 3f9ea9bfa..1c6106425 100644
--- a/src/flash/nor/at91sam4.c
+++ b/src/flash/nor/at91sam4.c
@@ -1896,7 +1896,7 @@ static uint32_t sam4_reg_fieldname(struct sam4_chip *pChip,
 	}
 
 	/* show the basics */
-	LOG_USER_N("\t%*s: %*" PRId32 " [0x%0*" PRIx32 "] ",
+	LOG_USER_N("\t%*s: %*" PRIu32 " [0x%0*" PRIx32 "] ",
 		REG_NAME_WIDTH, regname,
 		dwidth, v,
 		hwidth, v);
@@ -2549,7 +2549,7 @@ static int sam4_GetDetails(struct sam4_bank_private *pPrivate)
 		sam4_explain_chipid_cidr(pPrivate->pChip);
 		return ERROR_FAIL;
 	} else {
-		LOG_DEBUG("SAM4 Found chip %s, CIDR 0x%08x", pDetails->name, pDetails->chipid_cidr);
+		LOG_DEBUG("SAM4 Found chip %s, CIDR 0x%08" PRIx32, pDetails->name, pDetails->chipid_cidr);
 	}
 
 	/* DANGER: THERE ARE DRAGONS HERE */
diff --git a/src/flash/nor/at91sam4l.c b/src/flash/nor/at91sam4l.c
index 4ee4ff853..d09414cbe 100644
--- a/src/flash/nor/at91sam4l.c
+++ b/src/flash/nor/at91sam4l.c
@@ -346,7 +346,7 @@ static int sam4l_probe(struct flash_bank *bank)
 	/* Done */
 	chip->probed = true;
 
-	LOG_INFO("SAM4L MCU: %s (Rev %c) (%" PRIu32 "KB Flash with %d %" PRId32 "B pages, %" PRIu32 "KB RAM)",
+	LOG_INFO("SAM4L MCU: %s (Rev %c) (%" PRIu32 "KB Flash with %d %" PRIu32 "B pages, %" PRIu32 "KB RAM)",
 			chip->details ? chip->details->name : "unknown", (char)('A' + (id & 0xF)),
 			chip->flash_kb, chip->num_pages, chip->page_size, chip->ram_kb);
 
diff --git a/src/flash/nor/at91sam7.c b/src/flash/nor/at91sam7.c
index 59f5951ae..3d8fee1af 100644
--- a/src/flash/nor/at91sam7.c
+++ b/src/flash/nor/at91sam7.c
@@ -954,7 +954,7 @@ static int at91sam7_write(struct flash_bank *bank, const uint8_t *buffer, uint32
 		/* Send Write Page command to Flash Controller */
 		if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)
 			return ERROR_FLASH_OPERATION_FAILED;
-		LOG_DEBUG("Write flash bank:%u page number:%" PRIi32 "", bank->bank_number, pagen);
+		LOG_DEBUG("Write flash bank:%u page number:%" PRIu32, bank->bank_number, pagen);
 	}
 
 	return ERROR_OK;
diff --git a/src/flash/nor/ath79.c b/src/flash/nor/ath79.c
index c30ddf3c0..9a4595f6d 100644
--- a/src/flash/nor/ath79.c
+++ b/src/flash/nor/ath79.c
@@ -275,7 +275,7 @@ static int ath79_spi_bitbang_chunk(struct flash_bank *bank,
 	*transferred = 0;
 	pracc_queue_init(&ctx);
 
-	LOG_DEBUG("ath79_spi_bitbang_bytes(%p, %08x, %p, %d)",
+	LOG_DEBUG("ath79_spi_bitbang_bytes(%p, %08" PRIx32 ", %p, %d)",
 		  target, ath79_info->io_base, d...
 
[truncated message content]

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1392-g4e98d44fd

[OpenOCD-Gerrit <ope...@us...>]

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       via  4e98d44fd1dc67f763f06eeecc0453d65b1290dc (commit)
       via  62329444abc89ad3b37fbb4ebc2edfd1dee23351 (commit)
       via  47d29ebe11babdddd107ba5edab7e5cd85ce1fee (commit)
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- Log -----------------------------------------------------------------
commit 4e98d44fd1dc67f763f06eeecc0453d65b1290dc
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Aug 16 21:35:10 2020 +0200

    openocd: avoid checking for non NULL pointer to free it
    
    The function free() can be called with a NULL pointer as argument,
    no need to check the argument before. If the pointer is NULL, no
    operation is performed by free().
    
    Remove the occurrences of pattern:
            if (ptr)
                    free(ptr);
    
    While there replace a sequence malloc(size)+memset(,0,size) with a
    calloc(1,size).
    Replace a pointer assignment to '0' with an assignment to NULL.
    In server/*, an error is logged if the ptr was already NULL. This
    cannot happen since the pointer was already referenced few lines
    before and openocd would have been already SIGSEGV in that case,
    so remove the log.
    
    Change-Id: I10822029fe8390b59edff4070575bf7f754e44ac
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5808
    Reviewed-by: Adrian M Negreanu <adr...@nx...>
    Tested-by: jenkins

diff --git a/src/helper/ioutil.c b/src/helper/ioutil.c
index c103ce173..ffdeca898 100644
--- a/src/helper/ioutil.c
+++ b/src/helper/ioutil.c
@@ -230,8 +230,7 @@ COMMAND_HANDLER(handle_cp_command)
 	else
 		command_print(CMD, "copy failed");
 
-	if (data != NULL)
-		free(data);
+	free(data);
 	if (f != NULL)
 		fclose(f);
 
diff --git a/src/rtos/chibios.c b/src/rtos/chibios.c
index 4d2b1b2d7..a56d3ce05 100644
--- a/src/rtos/chibios.c
+++ b/src/rtos/chibios.c
@@ -150,10 +150,8 @@ static int chibios_update_memory_signature(struct rtos *rtos)
 	param = (struct chibios_params *) rtos->rtos_specific_params;
 
 	/* Free existing memory description.*/
-	if (param->signature) {
-		free(param->signature);
-		param->signature = 0;
-	}
+	free(param->signature);
+	param->signature = NULL;
 
 	signature = malloc(sizeof(*signature));
 	if (!signature) {
diff --git a/src/rtos/linux.c b/src/rtos/linux.c
index cd1ed218a..dbbf97b44 100644
--- a/src/rtos/linux.c
+++ b/src/rtos/linux.c
@@ -627,8 +627,7 @@ struct threads *liste_del_task(struct threads *task_list, struct threads **t,
 		task_list = (*t)->next;
 
 	/*  free content of threads */
-	if ((*t)->context)
-		free((*t)->context);
+	free((*t)->context);
 
 	free(*t);
 	*t = prev ? prev : task_list;
@@ -781,8 +780,7 @@ static int clean_threadlist(struct target *target)
 	while (temp != NULL) {
 		old = temp;
 
-		if (temp->context)
-			free(temp->context);
+		free(temp->context);
 
 		temp = temp->next;
 		free(old);
@@ -931,10 +929,8 @@ static int linux_task_update(struct target *target, int context)
 	while (thread_list != NULL) {
 		thread_list->status = 0;	/*setting all tasks to dead state*/
 
-		if (thread_list->context) {
-			free(thread_list->context);
-			thread_list->context = NULL;
-		}
+		free(thread_list->context);
+		thread_list->context = NULL;
 
 		thread_list = thread_list->next;
 	}
diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c
index 97ce255b9..62b65aae1 100644
--- a/src/rtos/rtos.c
+++ b/src/rtos/rtos.c
@@ -100,9 +100,7 @@ static void os_free(struct target *target)
 	if (!target->rtos)
 		return;
 
-	if (target->rtos->symbols)
-		free(target->rtos->symbols);
-
+	free(target->rtos->symbols);
 	free(target->rtos);
 	target->rtos = NULL;
 }
@@ -646,10 +644,9 @@ int rtos_try_next(struct target *target)
 		return 0;
 
 	os->type = *type;
-	if (os->symbols) {
-		free(os->symbols);
-		os->symbols = NULL;
-	}
+
+	free(os->symbols);
+	os->symbols = NULL;
 
 	return 1;
 }
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index f94b72817..85d3c14b1 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -1067,11 +1067,8 @@ static int gdb_connection_closed(struct connection *connection)
 	/* if this connection registered a debug-message receiver delete it */
 	delete_debug_msg_receiver(connection->cmd_ctx, target);
 
-	if (connection->priv) {
-		free(connection->priv);
-		connection->priv = NULL;
-	} else
-		LOG_ERROR("BUG: connection->priv == NULL");
+	free(connection->priv);
+	connection->priv = NULL;
 
 	target_unregister_event_callback(gdb_target_callback_event_handler, connection);
 
@@ -1758,8 +1755,7 @@ static __attribute__ ((format (PRINTF_ATTRIBUTE_FORMAT, 5, 6))) void xml_printf(
 			char *t = *xml;
 			*xml = realloc(*xml, *size);
 			if (*xml == NULL) {
-				if (t)
-					free(t);
+				free(t);
 				*retval = ERROR_SERVER_REMOTE_CLOSED;
 				return;
 			}
diff --git a/src/server/server.c b/src/server/server.c
index d96f0b6cf..3b55d0d7c 100644
--- a/src/server/server.c
+++ b/src/server/server.c
@@ -403,19 +403,14 @@ static int remove_services(void)
 
 		remove_connections(c);
 
-		if (c->name)
-			free(c->name);
+		free(c->name);
 
 		if (c->type == CONNECTION_PIPE) {
 			if (c->fd != -1)
 				close(c->fd);
 		}
-		if (c->port)
-			free(c->port);
-
-		if (c->priv)
-			free(c->priv);
-
+		free(c->port);
+		free(c->priv);
 		/* delete service */
 		free(c);
 
diff --git a/src/server/telnet_server.c b/src/server/telnet_server.c
index d0583a9b3..0243c6328 100644
--- a/src/server/telnet_server.c
+++ b/src/server/telnet_server.c
@@ -451,8 +451,7 @@ static int telnet_input(struct connection *connection)
 							if (*t_con->line && (prev_line == NULL ||
 									strcmp(t_con->line, prev_line))) {
 								/* if the history slot is already taken, free it */
-								if (t_con->history[t_con->next_history])
-									free(t_con->history[t_con->next_history]);
+								free(t_con->history[t_con->next_history]);
 
 								/* add line to history */
 								t_con->history[t_con->next_history] = strdup(t_con->line);
@@ -465,8 +464,7 @@ static int telnet_input(struct connection *connection)
 								t_con->current_history =
 										t_con->next_history;
 
-								if (t_con->history[t_con->current_history])
-									free(t_con->history[t_con->current_history]);
+								free(t_con->history[t_con->current_history]);
 								t_con->history[t_con->current_history] = strdup("");
 							}
 
@@ -647,29 +645,22 @@ static int telnet_connection_closed(struct connection *connection)
 
 	log_remove_callback(telnet_log_callback, connection);
 
-	if (t_con->prompt) {
-		free(t_con->prompt);
-		t_con->prompt = NULL;
-	}
+	free(t_con->prompt);
+	t_con->prompt = NULL;
 
 	/* save telnet history */
 	telnet_save_history(t_con);
 
 	for (i = 0; i < TELNET_LINE_HISTORY_SIZE; i++) {
-		if (t_con->history[i]) {
-			free(t_con->history[i]);
-			t_con->history[i] = NULL;
-		}
+		free(t_con->history[i]);
+		t_con->history[i] = NULL;
 	}
 
 	/* if this connection registered a debug-message receiver delete it */
 	delete_debug_msg_receiver(connection->cmd_ctx, NULL);
 
-	if (connection->priv) {
-		free(connection->priv);
-		connection->priv = NULL;
-	} else
-		LOG_ERROR("BUG: connection->priv == NULL");
+	free(connection->priv);
+	connection->priv = NULL;
 
 	return ERROR_OK;
 }
diff --git a/src/svf/svf.c b/src/svf/svf.c
index 010592076..b62cdae08 100644
--- a/src/svf/svf.c
+++ b/src/svf/svf.c
@@ -302,22 +302,17 @@ static int svf_realloc_buffers(size_t len)
 static void svf_free_xxd_para(struct svf_xxr_para *para)
 {
 	if (NULL != para) {
-		if (para->tdi != NULL) {
-			free(para->tdi);
-			para->tdi = NULL;
-		}
-		if (para->tdo != NULL) {
-			free(para->tdo);
-			para->tdo = NULL;
-		}
-		if (para->mask != NULL) {
-			free(para->mask);
-			para->mask = NULL;
-		}
-		if (para->smask != NULL) {
-			free(para->smask);
-			para->smask = NULL;
-		}
+		free(para->tdi);
+		para->tdi = NULL;
+
+		free(para->tdo);
+		para->tdo = NULL;
+
+		free(para->mask);
+		para->mask = NULL;
+
+		free(para->smask);
+		para->smask = NULL;
 	}
 }
 
@@ -546,28 +541,23 @@ free_all:
 	svf_fd = 0;
 
 	/* free buffers */
-	if (svf_command_buffer) {
-		free(svf_command_buffer);
-		svf_command_buffer = NULL;
-		svf_command_buffer_size = 0;
-	}
-	if (svf_check_tdo_para) {
-		free(svf_check_tdo_para);
-		svf_check_tdo_para = NULL;
-		svf_check_tdo_para_index = 0;
-	}
-	if (svf_tdi_buffer) {
-		free(svf_tdi_buffer);
-		svf_tdi_buffer = NULL;
-	}
-	if (svf_tdo_buffer) {
-		free(svf_tdo_buffer);
-		svf_tdo_buffer = NULL;
-	}
-	if (svf_mask_buffer) {
-		free(svf_mask_buffer);
-		svf_mask_buffer = NULL;
-	}
+	free(svf_command_buffer);
+	svf_command_buffer = NULL;
+	svf_command_buffer_size = 0;
+
+	free(svf_check_tdo_para);
+	svf_check_tdo_para = NULL;
+	svf_check_tdo_para_index = 0;
+
+	free(svf_tdi_buffer);
+	svf_tdi_buffer = NULL;
+
+	free(svf_tdo_buffer);
+	svf_tdo_buffer = NULL;
+
+	free(svf_mask_buffer);
+	svf_mask_buffer = NULL;
+
 	svf_buffer_index = 0;
 	svf_buffer_size = 0;
 
@@ -771,16 +761,12 @@ static int svf_adjust_array_length(uint8_t **arr, int orig_bit_len, int new_bit_
 	int new_byte_len = (new_bit_len + 7) >> 3;
 
 	if ((NULL == *arr) || (((orig_bit_len + 7) >> 3) < ((new_bit_len + 7) >> 3))) {
-		if (*arr != NULL) {
-			free(*arr);
-			*arr = NULL;
-		}
-		*arr = malloc(new_byte_len);
+		free(*arr);
+		*arr = calloc(1, new_byte_len);
 		if (NULL == *arr) {
 			LOG_ERROR("not enough memory");
 			return ERROR_FAIL;
 		}
-		memset(*arr, 0, new_byte_len);
 	}
 	return ERROR_OK;
 }
diff --git a/src/xsvf/xsvf.c b/src/xsvf/xsvf.c
index 53779bb1c..eaa5a3aae 100644
--- a/src/xsvf/xsvf.c
+++ b/src/xsvf/xsvf.c
@@ -411,12 +411,9 @@ COMMAND_HANDLER(handle_xsvf_command)
 				xsdrsize = be_to_h_u32(xsdrsize_buf);
 				LOG_DEBUG("XSDRSIZE %d", xsdrsize);
 
-				if (dr_out_buf)
-					free(dr_out_buf);
-				if (dr_in_buf)
-					free(dr_in_buf);
-				if (dr_in_mask)
-					free(dr_in_mask);
+				free(dr_out_buf);
+				free(dr_in_buf);
+				free(dr_in_mask);
 
 				dr_out_buf = malloc((xsdrsize + 7) / 8);
 				dr_in_buf = malloc((xsdrsize + 7) / 8);
@@ -1027,14 +1024,9 @@ COMMAND_HANDLER(handle_xsvf_command)
 		return ERROR_FAIL;
 	}
 
-	if (dr_out_buf)
-		free(dr_out_buf);
-
-	if (dr_in_buf)
-		free(dr_in_buf);
-
-	if (dr_in_mask)
-		free(dr_in_mask);
+	free(dr_out_buf);
+	free(dr_in_buf);
+	free(dr_in_mask);
 
 	close(xsvf_fd);
 

commit 62329444abc89ad3b37fbb4ebc2edfd1dee23351
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Aug 17 10:08:35 2020 +0200

    flash: avoid checking for non NULL pointer to free it
    
    The function free() can be called with a NULL pointer as argument,
    no need to check the argument before. If the pointer is NULL, no
    operation is performed by free().
    
    Remove the occurrences of pattern:
            if (ptr)
                    free(ptr);
    
    There are cases where the pointer is set to NULL after free(), but
    then re-assigned within few lines. Drop the setting to NULL when
    this is evident. Anyway, the compiler will remove the useless
    assignment so no reason to be too much aggressive in this change.
    
    Change-Id: I55b2ce7cbe201410016398933e34d33a4b66e30b
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5811
    Tested-by: jenkins

diff --git a/src/flash/nand/fileio.c b/src/flash/nand/fileio.c
index 1279e45a4..fee401292 100644
--- a/src/flash/nand/fileio.c
+++ b/src/flash/nand/fileio.c
@@ -99,14 +99,11 @@ int nand_fileio_cleanup(struct nand_fileio_state *state)
 	if (state->file_opened)
 		fileio_close(state->fileio);
 
-	if (state->oob) {
-		free(state->oob);
-		state->oob = NULL;
-	}
-	if (state->page) {
-		free(state->page);
-		state->page = NULL;
-	}
+	free(state->oob);
+	state->oob = NULL;
+
+	free(state->page);
+	state->page = NULL;
 	return ERROR_OK;
 }
 int nand_fileio_finish(struct nand_fileio_state *state)
diff --git a/src/flash/nor/ambiqmicro.c b/src/flash/nor/ambiqmicro.c
index 622943d28..28dc42d82 100644
--- a/src/flash/nor/ambiqmicro.c
+++ b/src/flash/nor/ambiqmicro.c
@@ -672,10 +672,7 @@ static int ambiqmicro_probe(struct flash_bank *bank)
 	if (retval != ERROR_OK)
 		return retval;
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
 
 	/* provide this for the benefit of the NOR flash framework */
 	bank->size = ambiqmicro_info->pagesize * ambiqmicro_info->num_pages;
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index 1e2a074aa..c9baffc70 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -3530,8 +3530,7 @@ static int sam3_write(struct flash_bank *bank,
 	LOG_DEBUG("Done!");
 	r = ERROR_OK;
 done:
-	if (pagebuffer)
-		free(pagebuffer);
+	free(pagebuffer);
 	return r;
 }
 
diff --git a/src/flash/nor/at91sam4.c b/src/flash/nor/at91sam4.c
index 4be3a5962..3f9ea9bfa 100644
--- a/src/flash/nor/at91sam4.c
+++ b/src/flash/nor/at91sam4.c
@@ -3009,8 +3009,7 @@ static int sam4_write(struct flash_bank *bank,
 	LOG_DEBUG("Done!");
 	r = ERROR_OK;
 done:
-	if (pagebuffer)
-		free(pagebuffer);
+	free(pagebuffer);
 	return r;
 }
 
diff --git a/src/flash/nor/at91samd.c b/src/flash/nor/at91samd.c
index 63710d3e0..5fbf8bcaa 100644
--- a/src/flash/nor/at91samd.c
+++ b/src/flash/nor/at91samd.c
@@ -915,9 +915,7 @@ static int samd_write(struct flash_bank *bank, const uint8_t *buffer,
 	}
 
 free_pb:
-	if (pb)
-		free(pb);
-
+	free(pb);
 	return res;
 }
 
diff --git a/src/flash/nor/atsame5.c b/src/flash/nor/atsame5.c
index 82306830a..5d6010a2a 100644
--- a/src/flash/nor/atsame5.c
+++ b/src/flash/nor/atsame5.c
@@ -731,9 +731,7 @@ static int same5_write(struct flash_bank *bank, const uint8_t *buffer,
 	}
 
 free_pb:
-	if (pb)
-		free(pb);
-
+	free(pb);
 	return res;
 }
 
diff --git a/src/flash/nor/avrf.c b/src/flash/nor/avrf.c
index 4ec1161af..70d4d341b 100644
--- a/src/flash/nor/avrf.c
+++ b/src/flash/nor/avrf.c
@@ -333,10 +333,7 @@ static int avrf_probe(struct flash_bank *bank)
 	}
 
 	if (avr_info != NULL) {
-		if (bank->sectors) {
-			free(bank->sectors);
-			bank->sectors = NULL;
-		}
+		free(bank->sectors);
 
 		/* chip found */
 		bank->base = 0x00000000;
diff --git a/src/flash/nor/cc3220sf.c b/src/flash/nor/cc3220sf.c
index 5e88aa61b..5427bd3a9 100644
--- a/src/flash/nor/cc3220sf.c
+++ b/src/flash/nor/cc3220sf.c
@@ -438,10 +438,7 @@ static int cc3220sf_probe(struct flash_bank *bank)
 	size = FLASH_NUM_SECTORS * FLASH_SECTOR_SIZE;
 	num_sectors = FLASH_NUM_SECTORS;
 
-	if (NULL != bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
 
 	bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
 	if (NULL == bank->sectors)
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 887821b79..964e06ac7 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -423,8 +423,7 @@ static int cfi_read_intel_pri_ext(struct flash_bank *bank)
 	struct cfi_flash_bank *cfi_info = bank->driver_priv;
 	struct cfi_intel_pri_ext *pri_ext;
 
-	if (cfi_info->pri_ext)
-		free(cfi_info->pri_ext);
+	free(cfi_info->pri_ext);
 
 	pri_ext = malloc(sizeof(struct cfi_intel_pri_ext));
 	if (pri_ext == NULL) {
@@ -520,8 +519,7 @@ static int cfi_read_spansion_pri_ext(struct flash_bank *bank)
 	struct cfi_flash_bank *cfi_info = bank->driver_priv;
 	struct cfi_spansion_pri_ext *pri_ext;
 
-	if (cfi_info->pri_ext)
-		free(cfi_info->pri_ext);
+	free(cfi_info->pri_ext);
 
 	pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 	if (pri_ext == NULL) {
@@ -623,8 +621,7 @@ static int cfi_read_atmel_pri_ext(struct flash_bank *bank)
 	struct cfi_flash_bank *cfi_info = bank->driver_priv;
 	struct cfi_spansion_pri_ext *pri_ext;
 
-	if (cfi_info->pri_ext)
-		free(cfi_info->pri_ext);
+	free(cfi_info->pri_ext);
 
 	pri_ext = malloc(sizeof(struct cfi_spansion_pri_ext));
 	if (pri_ext == NULL) {
@@ -2593,14 +2590,12 @@ int cfi_probe(struct flash_bank *bank)
 
 	cfi_info->probed = false;
 	cfi_info->num_erase_regions = 0;
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
-	if (cfi_info->erase_region_info) {
-		free(cfi_info->erase_region_info);
-		cfi_info->erase_region_info = NULL;
-	}
+
+	free(bank->sectors);
+	bank->sectors = NULL;
+
+	free(cfi_info->erase_region_info);
+	cfi_info->erase_region_info = NULL;
 
 	/* JEDEC standard JESD21C uses 0x5555 and 0x2aaa as unlock addresses,
 	 * while CFI compatible AMD/Spansion flashes use 0x555 and 0x2aa
diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 2c323b07e..6f2900762 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -951,9 +951,7 @@ reset_pg_and_lock:
 		retval = retval2;
 
 cleanup:
-	if (new_buffer)
-		free(new_buffer);
-
+	free(new_buffer);
 	return retval;
 }
 
@@ -987,10 +985,8 @@ static int efm32x_probe(struct flash_bank *bank)
 
 	assert(num_pages > 0);
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
+	bank->sectors = NULL;
 
 	bank->base = base_address;
 	bank->size = (num_pages * efm32_mcu_info.page_size);
diff --git a/src/flash/nor/em357.c b/src/flash/nor/em357.c
index cb4456209..4e2a169c6 100644
--- a/src/flash/nor/em357.c
+++ b/src/flash/nor/em357.c
@@ -724,10 +724,7 @@ static int em357_probe(struct flash_bank *bank)
 
 	LOG_INFO("flash size = %dkbytes", num_pages*page_size/1024);
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
 
 	bank->base = base_address;
 	bank->size = (num_pages * page_size);
diff --git a/src/flash/nor/kinetis.c b/src/flash/nor/kinetis.c
index 43b90f1f0..6b6121d3b 100644
--- a/src/flash/nor/kinetis.c
+++ b/src/flash/nor/kinetis.c
@@ -2736,14 +2736,11 @@ static int kinetis_probe(struct flash_bank *bank)
 				" please report to OpenOCD mailing list", fcfg2_maxaddr1);
 	}
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
-	if (bank->prot_blocks) {
-		free(bank->prot_blocks);
-		bank->prot_blocks = NULL;
-	}
+	free(bank->sectors);
+	bank->sectors = NULL;
+
+	free(bank->prot_blocks);
+	bank->prot_blocks = NULL;
 
 	if (k_bank->sector_size == 0) {
 		LOG_ERROR("Unknown sector size for bank %u", bank->bank_number);
diff --git a/src/flash/nor/kinetis_ke.c b/src/flash/nor/kinetis_ke.c
index 6afb3b9e6..349b2564d 100644
--- a/src/flash/nor/kinetis_ke.c
+++ b/src/flash/nor/kinetis_ke.c
@@ -1145,10 +1145,7 @@ static int kinetis_ke_probe(struct flash_bank *bank)
 			break;
 	}
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
 
 	assert(bank->num_sectors > 0);
 	bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
diff --git a/src/flash/nor/max32xxx.c b/src/flash/nor/max32xxx.c
index c840bd795..bf54f63ba 100644
--- a/src/flash/nor/max32xxx.c
+++ b/src/flash/nor/max32xxx.c
@@ -651,10 +651,7 @@ static int max32xxx_probe(struct flash_bank *bank)
 	uint32_t arm_id[2];
 	uint16_t arm_pid;
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
 
 	/* provide this for the benefit of the NOR flash framework */
 	bank->size = info->flash_size;
diff --git a/src/flash/nor/mdr.c b/src/flash/nor/mdr.c
index b835f9237..2518c229b 100644
--- a/src/flash/nor/mdr.c
+++ b/src/flash/nor/mdr.c
@@ -458,8 +458,7 @@ reset_pg_and_lock:
 		retval = retval2;
 
 free_buffer:
-	if (new_buffer)
-		free(new_buffer);
+	free(new_buffer);
 
 	/* read some bytes bytes to flush buffer in flash accelerator.
 	 * See errata for 1986VE1T and 1986VE3. Error 0007 */
@@ -573,10 +572,7 @@ static int mdr_probe(struct flash_bank *bank)
 	page_count = mdr_info->page_count;
 	page_size = bank->size / page_count;
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
 
 	bank->num_sectors = page_count;
 	bank->sectors = malloc(sizeof(struct flash_sector) * page_count);
diff --git a/src/flash/nor/msp432.c b/src/flash/nor/msp432.c
index 0c925bdd3..d2417bc89 100644
--- a/src/flash/nor/msp432.c
+++ b/src/flash/nor/msp432.c
@@ -902,10 +902,8 @@ static int msp432_probe(struct flash_bank *bank)
 		}
 	}
 
-	if (NULL != bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
+	bank->sectors = NULL;
 
 	if (num_sectors > 0) {
 		bank->sectors = malloc(sizeof(struct flash_sector) * num_sectors);
@@ -1046,7 +1044,7 @@ static void msp432_flash_free_driver_priv(struct flash_bank *bank)
 
 	/* A single private struct is shared between main and info banks */
 	/* Only free it on the call for main bank */
-	if (is_main && (NULL != bank->driver_priv))
+	if (is_main)
 		free(bank->driver_priv);
 
 	/* Forget about the private struct on both main and info banks */
diff --git a/src/flash/nor/niietcm4.c b/src/flash/nor/niietcm4.c
index 2377e14f7..2a20edcee 100644
--- a/src/flash/nor/niietcm4.c
+++ b/src/flash/nor/niietcm4.c
@@ -1469,9 +1469,7 @@ static int niietcm4_write(struct flash_bank *bank, const uint8_t *buffer,
 	}
 
 free_buffer:
-	if (new_buffer)
-		free(new_buffer);
-
+	free(new_buffer);
 	return retval;
 }
 
@@ -1681,10 +1679,9 @@ static int niietcm4_probe(struct flash_bank *bank)
 	struct niietcm4_flash_bank *niietcm4_info = bank->driver_priv;
 	struct target *target = bank->target;
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
+	bank->sectors = NULL;
+
 	uint32_t retval;
 	uint32_t chipid;
 
diff --git a/src/flash/nor/pic32mx.c b/src/flash/nor/pic32mx.c
index 9b9185344..ae5ebb932 100644
--- a/src/flash/nor/pic32mx.c
+++ b/src/flash/nor/pic32mx.c
@@ -591,8 +591,7 @@ static int pic32mx_write_block(struct flash_bank *bank, const uint8_t *buffer,
 	destroy_reg_param(&reg_params[1]);
 	destroy_reg_param(&reg_params[2]);
 
-	if (new_buffer != NULL)
-		free(new_buffer);
+	free(new_buffer);
 	return retval;
 }
 
@@ -774,10 +773,7 @@ static int pic32mx_probe(struct flash_bank *bank)
 
 	LOG_INFO("flash size = %" PRId32 "kbytes", num_pages / 1024);
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
 
 	/* calculate numbers of pages */
 	num_pages /= page_size;
diff --git a/src/flash/nor/psoc4.c b/src/flash/nor/psoc4.c
index 0c656349f..9c2fdf775 100644
--- a/src/flash/nor/psoc4.c
+++ b/src/flash/nor/psoc4.c
@@ -610,8 +610,7 @@ static int psoc4_protect(struct flash_bank *bank, int set, unsigned int first,
 			break;
 	}
 
-	if (sysrq_buffer)
-		free(sysrq_buffer);
+	free(sysrq_buffer);
 
 	psoc4_protect_check(bank);
 	return retval;
@@ -714,9 +713,7 @@ static int psoc4_write(struct flash_bank *bank, const uint8_t *buffer,
 cleanup:
 	jtag_poll_set_enabled(save_poll);
 
-	if (sysrq_buffer)
-		free(sysrq_buffer);
-
+	free(sysrq_buffer);
 	return retval;
 }
 
@@ -827,9 +824,7 @@ static int psoc4_probe(struct flash_bank *bank)
 		}
 	}
 
-	if (bank->sectors) {
-		free(bank->sectors);
-	}
+	free(bank->sectors);
 
 	psoc4_info->family_id = family_id;
 	psoc4_info->num_macros = num_macros;
diff --git a/src/flash/nor/psoc6.c b/src/flash/nor/psoc6.c
index c7141738d..09a1bed56 100644
--- a/src/flash/nor/psoc6.c
+++ b/src/flash/nor/psoc6.c
@@ -585,10 +585,8 @@ static int psoc6_probe(struct flash_bank *bank)
 	/* Calculate size of Main Flash*/
 	uint32_t flash_sz_bytes = bank_cnt * row_cnt * row_sz;
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
+	bank->sectors = NULL;
 
 	size_t bank_size = 0;
 
diff --git a/src/flash/nor/sim3x.c b/src/flash/nor/sim3x.c
index 21449041c..76280f1ab 100644
--- a/src/flash/nor/sim3x.c
+++ b/src/flash/nor/sim3x.c
@@ -801,10 +801,7 @@ static int sim3x_probe(struct flash_bank *bank)
 	if (ret != ERROR_OK)
 		return ret;
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
 
 	bank->base = FLASH_BASE_ADDRESS;
 	bank->size = sim3x_info->flash_size_kb * SIM3X_FLASH_PAGE_SIZE;
diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c
index 34c9c28fe..55b99de3f 100644
--- a/src/flash/nor/stellaris.c
+++ b/src/flash/nor/stellaris.c
@@ -1250,10 +1250,7 @@ static int stellaris_probe(struct flash_bank *bank)
 	if (retval != ERROR_OK)
 		return retval;
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
 
 	/* provide this for the benefit of the NOR flash framework */
 	bank->size = stellaris_info->num_pages * stellaris_info->pagesize;
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index a07bd847b..78efc8b47 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -617,9 +617,7 @@ reset_pg_and_lock:
 		retval = retval2;
 
 cleanup:
-	if (new_buffer)
-		free(new_buffer);
-
+	free(new_buffer);
 	return retval;
 }
 
@@ -872,15 +870,11 @@ static int stm32x_probe(struct flash_bank *bank)
 	/* check that calculation result makes sense */
 	assert(num_pages > 0);
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
+	bank->sectors = NULL;
 
-	if (bank->prot_blocks) {
-		free(bank->prot_blocks);
-		bank->prot_blocks = NULL;
-	}
+	free(bank->prot_blocks);
+	bank->prot_blocks = NULL;
 
 	bank->base = base_address;
 	bank->size = (num_pages * page_size);
diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c
index 52bad4b0d..e3625f322 100644
--- a/src/flash/nor/stm32f2x.c
+++ b/src/flash/nor/stm32f2x.c
@@ -1013,17 +1013,13 @@ static int stm32x_probe(struct flash_bank *bank)
 	stm32x_info->protection_bits = 12;		/* max. number of nWRPi bits (in FLASH_OPTCR !!!) */
 	num_prot_blocks = 0;
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->num_sectors = 0;
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
+	bank->num_sectors = 0;
+	bank->sectors = NULL;
 
-	if (bank->prot_blocks) {
-		free(bank->prot_blocks);
-		bank->num_prot_blocks = 0;
-		bank->prot_blocks = NULL;
-	}
+	free(bank->prot_blocks);
+	bank->num_prot_blocks = 0;
+	bank->prot_blocks = NULL;
 
 	/* if explicitly called out as OTP bank, short circuit probe */
 	if (stm32x_is_otp(bank)) {
diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c
index 9f456b29d..ac7d75948 100644
--- a/src/flash/nor/stm32h7x.c
+++ b/src/flash/nor/stm32h7x.c
@@ -853,8 +853,7 @@ static int stm32x_probe(struct flash_bank *bank)
 	bank->num_sectors = flash_size_in_kb / stm32x_info->part_info->page_size_kb;
 	assert(bank->num_sectors > 0);
 
-	if (bank->sectors)
-		free(bank->sectors);
+	free(bank->sectors);
 
 	bank->sectors = alloc_block_array(0, stm32x_info->part_info->page_size_kb * 1024,
 			bank->num_sectors);
@@ -871,8 +870,7 @@ static int stm32x_probe(struct flash_bank *bank)
 	bank->num_prot_blocks = bank->num_sectors / wpsn;
 	assert(bank->num_prot_blocks > 0);
 
-	if (bank->prot_blocks)
-		free(bank->prot_blocks);
+	free(bank->prot_blocks);
 
 	bank->prot_blocks = alloc_block_array(0, stm32x_info->part_info->page_size_kb * wpsn * 1024,
 			bank->num_prot_blocks);
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index c56bd6d60..0b5e1b04b 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -1040,10 +1040,7 @@ static int stm32l4_probe(struct flash_bank *bank)
 	assert((stm32l4_info->wrpxxr_mask & 0xFFFF0000) == 0);
 	LOG_DEBUG("WRPxxR mask 0x%04" PRIx16, (uint16_t)stm32l4_info->wrpxxr_mask);
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
 
 	bank->size = (flash_size_kb + gap_size_kb) * 1024;
 	bank->base = STM32_FLASH_BANK_BASE;
diff --git a/src/flash/nor/stm32lx.c b/src/flash/nor/stm32lx.c
index cf5b36040..34c7408b0 100644
--- a/src/flash/nor/stm32lx.c
+++ b/src/flash/nor/stm32lx.c
@@ -836,10 +836,7 @@ static int stm32lx_probe(struct flash_bank *bank)
 	/* calculate numbers of sectors (4kB per sector) */
 	unsigned int num_sectors = (flash_size_in_kb * 1024) / FLASH_SECTOR_SIZE;
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
 
 	bank->size = flash_size_in_kb * 1024;
 	bank->base = base_address;
diff --git a/src/flash/nor/swm050.c b/src/flash/nor/swm050.c
index 020a1dac7..98361eb91 100644
--- a/src/flash/nor/swm050.c
+++ b/src/flash/nor/swm050.c
@@ -156,10 +156,7 @@ COMMAND_HANDLER(swm050_handle_mass_erase_command)
 
 FLASH_BANK_COMMAND_HANDLER(swm050_flash_bank_command)
 {
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
 	bank->write_start_alignment = 4;
 	bank->write_end_alignment = 4;
 	bank->size = SWM050_FLASH_PAGE_SIZE * SWM050_FLASH_PAGES;
diff --git a/src/flash/nor/tms470.c b/src/flash/nor/tms470.c
index 4b8d2208a..611688c6a 100644
--- a/src/flash/nor/tms470.c
+++ b/src/flash/nor/tms470.c
@@ -148,11 +148,9 @@ static int tms470_read_part_info(struct flash_bank *bank)
 	rom_flash = (device_ident_reg >> 10) & 1;
 	part_number = (device_ident_reg >> 3) & 0x7f;
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-		bank->num_sectors = 0;
-	}
+	free(bank->sectors);
+	bank->sectors = NULL;
+	bank->num_sectors = 0;
 
 	/*
 	 * If the part number is known, determine if the flash bank is valid
diff --git a/src/flash/nor/w600.c b/src/flash/nor/w600.c
index 479082177..043959326 100644
--- a/src/flash/nor/w600.c
+++ b/src/flash/nor/w600.c
@@ -331,10 +331,8 @@ static int w600_probe(struct flash_bank *bank)
 	/* check that calculation result makes sense */
 	assert(num_pages > 0);
 
-	if (bank->sectors) {
-		free(bank->sectors);
-		bank->sectors = NULL;
-	}
+	free(bank->sectors);
+	bank->sectors = NULL;
 
 	bank->base = W600_FLASH_BASE;
 	bank->size = num_pages * W600_FLASH_SECSIZE;

commit 47d29ebe11babdddd107ba5edab7e5cd85ce1fee
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Aug 14 10:54:32 2020 +0200

    adi_v5: use macro DP_APSEL_MAX to allocate struct adiv5_ap
    
    Commit 11019a824d02 ("adi_v5: enforce check on AP number value")
    introduces the macro DP_APSEL_MAX and use it in place of hardcoded
    magic numbers for the upper limit of AP selection value.
    
    Use the macro also while defining the array of struct adiv5_ap in
    struct adiv5_dap.
    
    Change-Id: I88f53ceb710f92a48a8026a365709fbf2d9e6912
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5806
    Tested-by: jenkins

diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 17365bddb..ea7155167 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -253,7 +253,7 @@ struct adiv5_dap {
 	/* Control config */
 	uint32_t dp_ctrl_stat;
 
-	struct adiv5_ap ap[256];
+	struct adiv5_ap ap[DP_APSEL_MAX + 1];
 
 	/* The current manually selected AP by the "dap apsel" command */
 	uint32_t apsel;

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nand/fileio.c    | 13 ++++----
 src/flash/nor/ambiqmicro.c |  5 +---
 src/flash/nor/at91sam3.c   |  3 +-
 src/flash/nor/at91sam4.c   |  3 +-
 src/flash/nor/at91samd.c   |  4 +--
 src/flash/nor/atsame5.c    |  4 +--
 src/flash/nor/avrf.c       |  5 +---
 src/flash/nor/cc3220sf.c   |  5 +---
 src/flash/nor/cfi.c        | 23 ++++++--------
 src/flash/nor/efm32.c      | 10 ++-----
 src/flash/nor/em357.c      |  5 +---
 src/flash/nor/kinetis.c    | 13 ++++----
 src/flash/nor/kinetis_ke.c |  5 +---
 src/flash/nor/max32xxx.c   |  5 +---
 src/flash/nor/mdr.c        |  8 ++---
 src/flash/nor/msp432.c     |  8 ++---
 src/flash/nor/niietcm4.c   | 11 +++----
 src/flash/nor/pic32mx.c    |  8 ++---
 src/flash/nor/psoc4.c      | 11 ++-----
 src/flash/nor/psoc6.c      |  6 ++--
 src/flash/nor/sim3x.c      |  5 +---
 src/flash/nor/stellaris.c  |  5 +---
 src/flash/nor/stm32f1x.c   | 16 ++++------
 src/flash/nor/stm32f2x.c   | 16 ++++------
 src/flash/nor/stm32h7x.c   |  6 ++--
 src/flash/nor/stm32l4x.c   |  5 +---
 src/flash/nor/stm32lx.c    |  5 +---
 src/flash/nor/swm050.c     |  5 +---
 src/flash/nor/tms470.c     |  8 ++---
 src/flash/nor/w600.c       |  6 ++--
 src/helper/ioutil.c        |  3 +-
 src/rtos/chibios.c         |  6 ++--
 src/rtos/linux.c           | 12 +++-----
 src/rtos/rtos.c            | 11 +++----
 src/server/gdb_server.c    | 10 ++-----
 src/server/server.c        | 11 ++-----
 src/server/telnet_server.c | 25 +++++-----------
 src/svf/svf.c              | 74 +++++++++++++++++++---------------------------
 src/target/arm_adi_v5.h    |  2 +-
 src/xsvf/xsvf.c            | 20 ++++---------
 40 files changed, 133 insertions(+), 273 deletions(-)


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       via  60f104f45013ce0237df651e19f30181966a7256 (commit)
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- Log -----------------------------------------------------------------
commit aa628304e2a5a629ffee136089c0abee48db355b
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jul 12 00:57:34 2020 +0200

    helper: fix minor typos
    
    Change-Id: I785e388148c0329e51cb0b39ab30e8ee44f5a7cd
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/5801
    Tested-by: jenkins

diff --git a/src/helper/bin2char.sh b/src/helper/bin2char.sh
index 85a0fd6a8..128ea9af6 100755
--- a/src/helper/bin2char.sh
+++ b/src/helper/bin2char.sh
@@ -4,7 +4,7 @@
     echo "Usage: $0"
     echo
     echo "Read binary data from standard input and write it as a comma separated"
-    echo "list of hexadecimal byte values to standard ouput. The output is usable"
+    echo "list of hexadecimal byte values to standard output. The output is usable"
     echo "as a C array initializer. It is terminated with a comma so it can be"
     echo "continued e.g. for zero termination."
     exit 1
diff --git a/src/helper/command.h b/src/helper/command.h
index 886bde86b..b0c84bb43 100644
--- a/src/helper/command.h
+++ b/src/helper/command.h
@@ -168,7 +168,7 @@ struct command_invocation {
  *
  * This is *especially* important for commands such as writing
  * to flash or verifying memory. The reason is that those commands
- * can be used by programs to determine if the operation succeded
+ * can be used by programs to determine if the operation succeeded
  * or not. If the operation failed, then a program can try
  * an alternative approach.
  *
@@ -199,7 +199,7 @@ struct command {
  * Commands should be registered by filling in one or more of these
  * structures and passing them to [un]register_commands().
  *
- * A conventioal format should be used for help strings, to provide both
+ * A conventional format should be used for help strings, to provide both
  * usage and basic information:
  * @code
  * "@<options@> ... - some explanation text"
@@ -252,7 +252,7 @@ int register_commands(struct command_context *cmd_ctx, struct command *parent,
 		const struct command_registration *cmds);
 
 /**
- * Unregisters all commands from the specfied context.
+ * Unregisters all commands from the specified context.
  * @param cmd_ctx The context that will be cleared of registered commands.
  * @param parent If given, only clear commands from under this one command.
  * @returns ERROR_OK on success, or an error code.
@@ -265,7 +265,7 @@ struct command *command_find_in_context(struct command_context *cmd_ctx,
 
 /**
  * Update the private command data field for a command and all descendents.
- * This is used when creating a new heirarchy of commands that depends
+ * This is used when creating a new hierarchy of commands that depends
  * on obtaining a dynamically created context.  The value will be available
  * in command handlers by using the CMD_DATA macro.
  * @param c The command (group) whose data pointer(s) will be updated.
@@ -362,7 +362,7 @@ DECLARE_PARSE_WRAPPER(_target_addr, target_addr_t);
  *
  * This function may cause the calling function to return immediately,
  * so it should be used carefully to avoid leaking resources.  In most
- * situations, parsing should be completed in full before proceding
+ * situations, parsing should be completed in full before proceeding
  * to allocate resources, and this strategy will most prevents leaks.
  */
 #define COMMAND_PARSE_NUMBER(type, in, out) \
diff --git a/src/helper/jim-nvp.h b/src/helper/jim-nvp.h
index 7b4a491d3..4c4dc8ff4 100644
--- a/src/helper/jim-nvp.h
+++ b/src/helper/jim-nvp.h
@@ -127,7 +127,7 @@ void Jim_SetResult_NvpUnknown(Jim_Interp *interp,
 
 /** Debug: convert argc/argv into a printable string for printf() debug
  *
- * \param interp - the interpeter
+ * \param interp - the interpreter
  * \param argc   - arg count
  * \param argv   - the objects
  *
@@ -150,7 +150,7 @@ const char *Jim_Debug_ArgvString(Jim_Interp *interp, int argc, Jim_Obj *const *a
  * Some TCL objects have various "configuration" values.
  * For example - in Tcl/Tk the "buttons" have many options.
  *
- * Usefull when dealing with command options.
+ * Useful when dealing with command options.
  * that may come in any order...
  *
  * Does not support "-foo = 123" type options.
diff --git a/src/helper/log.c b/src/helper/log.c
index b05850df0..7440b70f6 100644
--- a/src/helper/log.c
+++ b/src/helper/log.c
@@ -469,7 +469,7 @@ void kept_alive(void)
 		gdb_timeout_warning(delta_time);
 }
 
-/* if we sleep for extended periods of time, we must invoke keep_alive() intermittantly */
+/* if we sleep for extended periods of time, we must invoke keep_alive() intermittently */
 void alive_sleep(uint64_t ms)
 {
 	uint64_t napTime = 10;
@@ -493,7 +493,7 @@ void busy_sleep(uint64_t ms)
 	}
 }
 
-/* Maximum size of socket error message retreived from operation system */
+/* Maximum size of socket error message retrieved from operation system */
 #define MAX_SOCKET_ERR_MSG_LENGTH 256
 
 /* Provide log message for the last socket error.
diff --git a/src/helper/log.h b/src/helper/log.h
index eac535deb..0c6623f01 100644
--- a/src/helper/log.h
+++ b/src/helper/log.h
@@ -40,7 +40,7 @@
  * LOG_LVL_SILENT - turn off all output. In lieu of try + catch this can be used as a
  *                  feeble ersatz.
  * LOG_LVL_USER - user messages. Could be anything from information
- *                to progress messags. These messages do not represent
+ *                to progress messages. These messages do not represent
  *                incorrect or unexpected behaviour, just normal execution.
  * LOG_LVL_ERROR - fatal errors, that are likely to cause program abort
  * LOG_LVL_WARNING - non-fatal errors, that may be resolved later
diff --git a/src/helper/update_jep106.pl b/src/helper/update_jep106.pl
index caec0664f..561e04b00 100755
--- a/src/helper/update_jep106.pl
+++ b/src/helper/update_jep106.pl
@@ -6,7 +6,7 @@ use File::Basename;
 if (@ARGV != 1) {
 	die "Usage: $0 <JEP106 PDF document>\n\n"
 	. "Convert the JEDEC document containing manufacturer identification codes\n"
-	. "to an array initializer suitable for incusion into jep106.c. The latest\n"
+	. "to an array initializer suitable for inclusion into jep106.c. The latest\n"
 	. "version of the document can be found here:\n"
 	. "http://www.jedec.org/standards-documents/results/jep106\n";
 };
diff --git a/src/helper/util.c b/src/helper/util.c
index 56baf95d1..dcd59e6ea 100644
--- a/src/helper/util.c
+++ b/src/helper/util.c
@@ -47,7 +47,7 @@ static const struct command_registration util_command_handlers[] = {
 		.mode = COMMAND_ANY,
 		.jim_handler = util_Jim_Command_ms,
 		.help =
-			"Returns ever increasing milliseconds. Used to calculuate differences in time.",
+			"Returns ever increasing milliseconds. Used to calculate differences in time.",
 		.usage = "",
 	},
 	COMMAND_REGISTRATION_DONE

commit 60f104f45013ce0237df651e19f30181966a7256
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jan 27 15:49:34 2019 +0100

    hla_transport: split command registration per transport
    
    All the HLA transports (hla_swd and hla_jtag) register the same
    set of commands. Such commands are mainly aimed at handling JTAG
    compatibility that is required for the transport hla_jtag only.
    
    Split per transport the command registration and limit the
    commands to only those required by the transport itself.
    Replace the command "hla newtap" with the transport specific
    "swd newdap" or "jtag newtap".
    Deprecate the command "hla".
    
    Change-Id: I79c78fa97b707482608516d3824151a4d07644c0
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/4877
    Tested-by: jenkins

diff --git a/src/jtag/hla/hla_transport.c b/src/jtag/hla/hla_transport.c
index 338357748..10028260d 100644
--- a/src/jtag/hla/hla_transport.c
+++ b/src/jtag/hla/hla_transport.c
@@ -46,24 +46,37 @@ COMMAND_HANDLER(hl_transport_reset_command)
 }
 
 static const struct command_registration
-hl_transport_stlink_subcommand_handlers[] = {
+hl_swd_transport_subcommand_handlers[] = {
 	{
-	 .name = "newtap",
+	 .name = "newdap",
 	 .mode = COMMAND_CONFIG,
 	 .jim_handler = jim_hl_newtap,
-	 .help = "Create a new TAP instance named basename.tap_type, "
-	 "and appends it to the scan chain.",
-	 .usage = "basename tap_type '-irlen' count "
-	 "['-expected_id' number] ",
+	 .help = "declare a new SWD DAP",
 	 },
+	COMMAND_REGISTRATION_DONE
+};
 
+static const struct command_registration hl_swd_transport_command_handlers[] = {
+	{
+	 .name = "swd",
+	 .mode = COMMAND_ANY,
+	 .help = "SWD command group",
+	 .usage = "",
+	 .chain = hl_swd_transport_subcommand_handlers,
+	 },
 	COMMAND_REGISTRATION_DONE
 };
 
 static const struct command_registration
 hl_transport_jtag_subcommand_handlers[] = {
 	{
-	 .chain = hl_transport_stlink_subcommand_handlers,
+	 .name = "newtap",
+	 .mode = COMMAND_CONFIG,
+	 .jim_handler = jim_hl_newtap,
+	 .help = "Create a new TAP instance named basename.tap_type, "
+	 "and appends it to the scan chain.",
+	 .usage = "basename tap_type '-irlen' count "
+	 "['-expected_id' number] ",
 	 },
 	{
 	 .name = "init",
@@ -120,18 +133,11 @@ hl_transport_jtag_subcommand_handlers[] = {
 	COMMAND_REGISTRATION_DONE
 };
 
-static const struct command_registration stlink_transport_command_handlers[] = {
-
-	{
-	 .name = "hla",
-	 .mode = COMMAND_ANY,
-	 .help = "perform hl adapter actions",
-	 .usage = "",
-	 .chain = hl_transport_stlink_subcommand_handlers,
-	 },
+static const struct command_registration hl_jtag_transport_command_handlers[] = {
 	{
 	 .name = "jtag",
 	 .mode = COMMAND_ANY,
+	 .help = "perform jtag tap actions",
 	 .usage = "",
 	 .chain = hl_transport_jtag_subcommand_handlers,
 	 },
@@ -144,11 +150,6 @@ static const struct command_registration stlink_transport_command_handlers[] = {
 	COMMAND_REGISTRATION_DONE
 };
 
-static int hl_transport_register_commands(struct command_context *cmd_ctx)
-{
-	return register_commands(cmd_ctx, NULL,
-				 stlink_transport_command_handlers);
-}
 
 static int hl_transport_init(struct command_context *cmd_ctx)
 {
@@ -187,34 +188,35 @@ static int hl_transport_init(struct command_context *cmd_ctx)
 	return hl_interface_init_target(t);
 }
 
-static int hl_transport_select(struct command_context *ctx)
+static int hl_jtag_transport_select(struct command_context *cmd_ctx)
 {
-	LOG_DEBUG("hl_transport_select");
-
-	int retval;
+	LOG_DEBUG("hl_jtag_transport_select");
 
 	/* NOTE:  interface init must already have been done.
 	 * That works with only C code ... no Tcl glue required.
 	 */
 
-	retval = hl_transport_register_commands(ctx);
-
-	if (retval != ERROR_OK)
-		return retval;
+	return register_commands(cmd_ctx, NULL,
+				hl_jtag_transport_command_handlers);
+}
 
-	return ERROR_OK;
+static int hl_swd_transport_select(struct command_context *cmd_ctx)
+{
+	LOG_DEBUG("hl_swd_transport_select");
+	return register_commands(cmd_ctx, NULL,
+				hl_swd_transport_command_handlers);
 }
 
 static struct transport hl_swd_transport = {
 	.name = "hla_swd",
-	.select = hl_transport_select,
+	.select = hl_swd_transport_select,
 	.init = hl_transport_init,
 	.override_target = hl_interface_override_target,
 };
 
 static struct transport hl_jtag_transport = {
 	.name = "hla_jtag",
-	.select = hl_transport_select,
+	.select = hl_jtag_transport_select,
 	.init = hl_transport_init,
 	.override_target = hl_interface_override_target,
 };
diff --git a/src/jtag/startup.tcl b/src/jtag/startup.tcl
index 90b675f18..82327a39b 100644
--- a/src/jtag/startup.tcl
+++ b/src/jtag/startup.tcl
@@ -226,4 +226,13 @@ proc xds110_supply_voltage args {
 	eval xds110 supply $args
 }
 
+proc hla {cmd args} {
+        tailcall "hla $cmd" {*}$args
+}
+
+proc "hla newtap" {args} {
+	echo "DEPRECATED! use 'swj_newdap' not 'hla newtap'"
+	eval swj_newdap $args
+}
+
 # END MIGRATION AIDS
diff --git a/tcl/target/swj-dp.tcl b/tcl/target/swj-dp.tcl
index 1d274cb12..3fb0263f1 100644
--- a/tcl/target/swj-dp.tcl
+++ b/tcl/target/swj-dp.tcl
@@ -24,11 +24,12 @@ if [catch {transport select}] {
 }
 
 proc swj_newdap {chip tag args} {
- if [using_hla] {
-     eval hla newtap $chip $tag $args
- } elseif [using_jtag] {
+ if [using_jtag] {
      eval jtag newtap $chip $tag $args
  } elseif [using_swd] {
      eval swd newdap $chip $tag $args
+ } else {
+     echo "Error: transport '[ transport select ]' not supported by swj_newdap"
+     shutdown
  }
 }

-----------------------------------------------------------------------

Summary of changes:
 src/helper/bin2char.sh       |  2 +-
 src/helper/command.h         | 10 +++----
 src/helper/jim-nvp.h         |  4 +--
 src/helper/log.c             |  4 +--
 src/helper/log.h             |  2 +-
 src/helper/update_jep106.pl  |  2 +-
 src/helper/util.c            |  2 +-
 src/jtag/hla/hla_transport.c | 66 +++++++++++++++++++++++---------------------
 src/jtag/startup.tcl         |  9 ++++++
 tcl/target/swj-dp.tcl        |  7 +++--
 10 files changed, 60 insertions(+), 48 deletions(-)


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      from  f1d77a485ce4ca81ea791f3d584f7d5d452a10a9 (commit)

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- Log -----------------------------------------------------------------
commit 1457a1ab425febd3dfceeb8c908b69135ff0b8b6
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jan 26 16:19:55 2019 +0100

    tcl/target: use command 'jtag newtap' to add a boundary scan TAP
    
    A JTAG TAP for boundary scan should be added in the scan chain
    through the command "jtag newtap".
    In some TCL target script the boundary scan TAP is added through
    the command "swj_newdap", command that is inappropriate in this
    context because specific for arm adi-v5 SWJ-DP.
    This situation was probably created to bypass the error with HLA
    framework, caused by missing command "jtag newtap".
    
    Add the command "jtag newtap" in HLA, by reusing the existing
    code for command "hla newtap".
    Fix the TCL target scripts to use the command "jtag newtap" for
    the boundary scan TAPs.
    
    The TCL script target/psoc6.cfg has no evident reference to HLA,
    so the reason for using "swj_newdap" is less clear. Nevertheless
    it uses the wrong command and, once HLA is fixed, there is no
    reason to avoid fixing it too.
    
    Change-Id: Ia92f8221430cf6f3d2c34294e22e5e18963bb88c
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: http://openocd.zylin.com/4873
    Tested-by: jenkins
    Reviewed-by: Andreas Fritiofson <and...@gm...>

diff --git a/src/jtag/hla/hla_transport.c b/src/jtag/hla/hla_transport.c
index fbdddfd65..338357748 100644
--- a/src/jtag/hla/hla_transport.c
+++ b/src/jtag/hla/hla_transport.c
@@ -62,6 +62,9 @@ hl_transport_stlink_subcommand_handlers[] = {
 
 static const struct command_registration
 hl_transport_jtag_subcommand_handlers[] = {
+	{
+	 .chain = hl_transport_stlink_subcommand_handlers,
+	 },
 	{
 	 .name = "init",
 	 .mode = COMMAND_ANY,
diff --git a/tcl/target/em357.cfg b/tcl/target/em357.cfg
index 572007134..f39f3f428 100644
--- a/tcl/target/em357.cfg
+++ b/tcl/target/em357.cfg
@@ -52,7 +52,7 @@ if { [info exists FLASHSIZE] } {
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 if { [using_jtag] } {
-    swj_newdap $_CHIPNAME bs -irlen 4 -expected-id $_BSTAPID -ircapture 0xe -irmask 0xf
+    jtag newtap $_CHIPNAME bs -irlen 4 -expected-id $_BSTAPID -ircapture 0xe -irmask 0xf
 }
 
 set _TARGETNAME $_CHIPNAME.cpu
diff --git a/tcl/target/psoc6.cfg b/tcl/target/psoc6.cfg
index 51d032b17..bf63fd5d4 100644
--- a/tcl/target/psoc6.cfg
+++ b/tcl/target/psoc6.cfg
@@ -146,5 +146,5 @@ if { $_ENABLE_CM0 } {
 }
 
 if {[using_jtag]} {
-	swj_newdap $_CHIPNAME bs -irlen 18 -expected-id 0x2e200069
+	jtag newtap $_CHIPNAME bs -irlen 18 -expected-id 0x2e200069
 }
diff --git a/tcl/target/stm32h7x.cfg b/tcl/target/stm32h7x.cfg
index 2d92eca92..43a8b024e 100644
--- a/tcl/target/stm32h7x.cfg
+++ b/tcl/target/stm32h7x.cfg
@@ -70,7 +70,7 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 if {[using_jtag]} {
- swj_newdap $_CHIPNAME bs -irlen 5
+   jtag newtap $_CHIPNAME bs -irlen 5
 }
 
 if {![using_hla]} {
diff --git a/tcl/target/stm32w108xx.cfg b/tcl/target/stm32w108xx.cfg
index 3a83fd19e..0470bf6ce 100644
--- a/tcl/target/stm32w108xx.cfg
+++ b/tcl/target/stm32w108xx.cfg
@@ -42,11 +42,11 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 if {[using_jtag]} {
  if { [info exists BSTAPID] } {
    set _BSTAPID $BSTAPID
-   swj_newdap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf -expected-id _BSTAPID
+   jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf -expected-id _BSTAPID
  } else {
    set _BSTAPID_1 0x169a862b
    set _BSTAPID_2 0x269a862b
-   swj_newdap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf \
+   jtag newtap $_CHIPNAME bs -irlen 4 -ircapture 0xe -irmask 0xf \
 		-expected-id $_BSTAPID_1 -expected-id $_BSTAPID_2
  }
 }
diff --git a/tcl/target/stm32wlx.cfg b/tcl/target/stm32wlx.cfg
index 98c9a7ee9..ba16fab6b 100644
--- a/tcl/target/stm32wlx.cfg
+++ b/tcl/target/stm32wlx.cfg
@@ -38,7 +38,7 @@ swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPU
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 if {[using_jtag]} {
-	swj_newdap $_CHIPNAME bs -irlen 5
+	jtag newtap $_CHIPNAME bs -irlen 5
 }
 
 set _TARGETNAME $_CHIPNAME.cpu

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/hla/hla_transport.c | 3 +++
 tcl/target/em357.cfg         | 2 +-
 tcl/target/psoc6.cfg         | 2 +-
 tcl/target/stm32h7x.cfg      | 2 +-
 tcl/target/stm32w108xx.cfg   | 4 ++--
 tcl/target/stm32wlx.cfg      | 2 +-
 6 files changed, 9 insertions(+), 6 deletions(-)


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The branch, master has been updated
       via  f1d77a485ce4ca81ea791f3d584f7d5d452a10a9 (commit)
       via  3ac010bb9f1065c0d2cba9ac2c473878d8a6eee6 (commit)
      from  764b25c81481225d425ff711b9ba11fca1d91b31 (commit)

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- Log -----------------------------------------------------------------
commit f1d77a485ce4ca81ea791f3d584f7d5d452a10a9
Author: Alexandre Bourdiol <ale...@st...>
Date:   Tue Sep 1 16:50:08 2020 +0200

    tcl/board/st_nucleo_l1.cfg use dualbank configuration
    
    st_nucleo_l1.cfg is based on STM32L152RET6 which support
    dualbank flash.
    
    Change-Id: I7ecdb7b7557229465e23eed667f20cd84197dfc7
    Signed-off-by: Alexandre Bourdiol <ale...@st...>
    Reviewed-on: http://openocd.zylin.com/5829
    Tested-by: jenkins
    Reviewed-by: Tarek BOCHKATI <tar...@gm...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/board/st_nucleo_l1.cfg b/tcl/board/st_nucleo_l1.cfg
index d97eb7c17..a508bb69c 100644
--- a/tcl/board/st_nucleo_l1.cfg
+++ b/tcl/board/st_nucleo_l1.cfg
@@ -5,6 +5,6 @@ source [find interface/stlink.cfg]
 
 transport select hla_swd
 
-source [find target/stm32l1.cfg]
+source [find target/stm32l1x_dual_bank.cfg]
 
 reset_config srst_only

commit 3ac010bb9f1065c0d2cba9ac2c473878d8a6eee6
Author: Samuel Obuch <so...@co...>
Date:   Tue Aug 11 17:37:01 2020 +0200

    Fix debug prints when loading to flash
    
    While loading to flash with debug level at least 3,
    OpenOCD tries to print the whole loaded bitstream.
    This will be very-very-slow due to implementation of
    conversion from buffer to string.
    
    * fix condition on selected debug level in jtag/core.c
    * replace slow buf_to_str function from helper/binarybuffer.c
      with faster but_to_hex_str function
    
    Change-Id: I3dc01d5846941ca80736f2ed12e3a54114d2b6dd
    Signed-off-by: Samuel Obuch <so...@co...>
    Reviewed-on: http://openocd.zylin.com/5800
    Tested-by: jenkins
    Reviewed-by: Jan Matyas <ma...@co...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/helper/binarybuffer.c b/src/helper/binarybuffer.c
index 76f657f8d..44d139f58 100644
--- a/src/helper/binarybuffer.c
+++ b/src/helper/binarybuffer.c
@@ -199,45 +199,20 @@ static int ceil_f_to_u32(float x)
 	return y;
 }
 
-char *buf_to_str(const void *_buf, unsigned buf_len, unsigned radix)
+char *buf_to_hex_str(const void *_buf, unsigned buf_len)
 {
-	float factor;
-	switch (radix) {
-		case 16:
-			factor = 2.0;	/* log(256) / log(16) = 2.0 */
-			break;
-		case 10:
-			factor = 2.40824;	/* log(256) / log(10) = 2.40824 */
-			break;
-		case 8:
-			factor = 2.66667;	/* log(256) / log(8) = 2.66667 */
-			break;
-		default:
-			return NULL;
-	}
-
-	unsigned str_len = ceil_f_to_u32(DIV_ROUND_UP(buf_len, 8) * factor);
-	char *str = calloc(str_len + 1, 1);
+	unsigned len_bytes = DIV_ROUND_UP(buf_len, 8);
+	char *str = calloc(len_bytes * 2 + 1, 1);
 
 	const uint8_t *buf = _buf;
-	int b256_len = DIV_ROUND_UP(buf_len, 8);
-	for (int i = b256_len - 1; i >= 0; i--) {
-		uint32_t tmp = buf[i];
-		if (((unsigned)i == (buf_len / 8)) && (buf_len % 8))
+	for (unsigned i = 0; i < len_bytes; i++) {
+		uint8_t tmp = buf[len_bytes - i - 1];
+		if ((i == 0) && (buf_len % 8))
 			tmp &= (0xff >> (8 - (buf_len % 8)));
-
-		/* base-256 digits */
-		for (unsigned j = str_len; j > 0; j--) {
-			tmp += (uint32_t)str[j-1] * 256;
-			str[j-1] = (uint8_t)(tmp % radix);
-			tmp /= radix;
-		}
+		str[2 * i] = hex_digits[tmp >> 4];
+		str[2 * i + 1] = hex_digits[tmp & 0xf];
 	}
 
-	const char * const DIGITS = "0123456789ABCDEF";
-	for (unsigned j = 0; j < str_len; j++)
-		str[j] = DIGITS[(int)str[j]];
-
 	return str;
 }
 
diff --git a/src/helper/binarybuffer.h b/src/helper/binarybuffer.h
index 3f2481d9a..36d6adc6f 100644
--- a/src/helper/binarybuffer.h
+++ b/src/helper/binarybuffer.h
@@ -201,7 +201,7 @@ void *buf_set_buf(const void *src, unsigned src_start,
 
 int str_to_buf(const char *str, unsigned len,
 		void *bin_buf, unsigned buf_size, unsigned radix);
-char *buf_to_str(const void *buf, unsigned size, unsigned radix);
+char *buf_to_hex_str(const void *buf, unsigned size);
 
 /* read a uint32_t from a buffer in target memory endianness */
 static inline uint32_t fast_target_buffer_get_u32(const void *p, bool le)
diff --git a/src/jtag/commands.c b/src/jtag/commands.c
index e88a3b74f..cafb05b5b 100644
--- a/src/jtag/commands.c
+++ b/src/jtag/commands.c
@@ -214,10 +214,10 @@ int jtag_build_buffer(const struct scan_command *cmd, uint8_t **buffer)
 	for (i = 0; i < cmd->num_fields; i++) {
 		if (cmd->fields[i].out_value) {
 			if (LOG_LEVEL_IS(LOG_LVL_DEBUG_IO)) {
-				char *char_buf = buf_to_str(cmd->fields[i].out_value,
+				char *char_buf = buf_to_hex_str(cmd->fields[i].out_value,
 						(cmd->fields[i].num_bits > DEBUG_JTAG_IOZ)
 						? DEBUG_JTAG_IOZ
-								: cmd->fields[i].num_bits, 16);
+								: cmd->fields[i].num_bits);
 
 				LOG_DEBUG("fields[%i].out_value[%i]: 0x%s", i,
 						cmd->fields[i].num_bits, char_buf);
@@ -257,10 +257,10 @@ int jtag_read_buffer(uint8_t *buffer, const struct scan_command *cmd)
 					malloc(DIV_ROUND_UP(num_bits, 8)), 0, num_bits);
 
 			if (LOG_LEVEL_IS(LOG_LVL_DEBUG_IO)) {
-				char *char_buf = buf_to_str(captured,
+				char *char_buf = buf_to_hex_str(captured,
 						(num_bits > DEBUG_JTAG_IOZ)
 						? DEBUG_JTAG_IOZ
-								: num_bits, 16);
+								: num_bits);
 
 				LOG_DEBUG("fields[%i].in_value[%i]: 0x%s",
 						i, num_bits, char_buf);
diff --git a/src/jtag/core.c b/src/jtag/core.c
index 1d424b2e4..b8d0b74c0 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -891,8 +891,8 @@ static int jtag_check_value_inner(uint8_t *captured, uint8_t *in_check_value,
 
 		/* NOTE:  we've lost diagnostic context here -- 'which tap' */
 
-		captured_str = buf_to_str(captured, bits, 16);
-		in_check_value_str = buf_to_str(in_check_value, bits, 16);
+		captured_str = buf_to_hex_str(captured, bits);
+		in_check_value_str = buf_to_hex_str(in_check_value, bits);
 
 		LOG_WARNING("Bad value '%s' captured during DR or IR scan:",
 			captured_str);
@@ -904,7 +904,7 @@ static int jtag_check_value_inner(uint8_t *captured, uint8_t *in_check_value,
 		if (in_check_mask) {
 			char *in_check_mask_str;
 
-			in_check_mask_str = buf_to_str(in_check_mask, bits, 16);
+			in_check_mask_str = buf_to_hex_str(in_check_mask, bits);
 			LOG_WARNING(" check_mask: 0x%s", in_check_mask_str);
 			free(in_check_mask_str);
 		}
@@ -960,7 +960,7 @@ int default_interface_jtag_execute_queue(void)
 	 * jtag/Makefile.am if MINIDRIVER_DUMMY || !MINIDRIVER, but those variables
 	 * aren't accessible here. */
 	struct jtag_command *cmd = jtag_command_queue;
-	while (debug_level >= LOG_LVL_DEBUG && cmd) {
+	while (debug_level >= LOG_LVL_DEBUG_IO && cmd) {
 		switch (cmd->type) {
 			case JTAG_SCAN:
 				LOG_DEBUG_IO("JTAG %s SCAN to %s",
@@ -969,12 +969,12 @@ int default_interface_jtag_execute_queue(void)
 				for (int i = 0; i < cmd->cmd.scan->num_fields; i++) {
 					struct scan_field *field = cmd->cmd.scan->fields + i;
 					if (field->out_value) {
-						char *str = buf_to_str(field->out_value, field->num_bits, 16);
+						char *str = buf_to_hex_str(field->out_value, field->num_bits);
 						LOG_DEBUG_IO("  %db out: %s", field->num_bits, str);
 						free(str);
 					}
 					if (field->in_value) {
-						char *str = buf_to_str(field->in_value, field->num_bits, 16);
+						char *str = buf_to_hex_str(field->in_value, field->num_bits);
 						LOG_DEBUG_IO("  %db  in: %s", field->num_bits, str);
 						free(str);
 					}
@@ -1436,7 +1436,7 @@ static int jtag_validate_ircapture(void)
 	/* verify the '11' sentinel we wrote is returned at the end */
 	val = buf_get_u64(ir_test, chain_pos, 2);
 	if (val != 0x3) {
-		char *cbuf = buf_to_str(ir_test, total_ir_length, 16);
+		char *cbuf = buf_to_hex_str(ir_test, total_ir_length);
 
 		LOG_ERROR("IR capture error at bit %d, saw 0x%s not 0x...3",
 			chain_pos, cbuf);
diff --git a/src/jtag/drivers/jtag_vpi.c b/src/jtag/drivers/jtag_vpi.c
index a5f441cc7..789d3a466 100644
--- a/src/jtag/drivers/jtag_vpi.c
+++ b/src/jtag/drivers/jtag_vpi.c
@@ -103,11 +103,10 @@ static int jtag_vpi_send_cmd(struct vpi_cmd *vpi)
 	if (LOG_LEVEL_IS(LOG_LVL_DEBUG_IO)) {
 		if (vpi->nb_bits > 0) {
 			/* command with a non-empty data payload */
-			char *char_buf = buf_to_str(vpi->buffer_out,
+			char *char_buf = buf_to_hex_str(vpi->buffer_out,
 					(vpi->nb_bits > DEBUG_JTAG_IOZ)
 						? DEBUG_JTAG_IOZ
-						: vpi->nb_bits,
-					16);
+						: vpi->nb_bits);
 			LOG_DEBUG_IO("sending JTAG VPI cmd: cmd=%s, "
 					"length=%" PRIu32 ", "
 					"nb_bits=%" PRIu32 ", "
@@ -328,9 +327,8 @@ static int jtag_vpi_queue_tdi_xfer(uint8_t *bits, int nb_bits, int tap_shift)
 
 	/* Optional low-level JTAG debug */
 	if (LOG_LEVEL_IS(LOG_LVL_DEBUG_IO)) {
-		char *char_buf = buf_to_str(vpi.buffer_in,
-				(nb_bits > DEBUG_JTAG_IOZ) ? DEBUG_JTAG_IOZ : nb_bits,
-				16);
+		char *char_buf = buf_to_hex_str(vpi.buffer_in,
+				(nb_bits > DEBUG_JTAG_IOZ) ? DEBUG_JTAG_IOZ : nb_bits);
 		LOG_DEBUG_IO("recvd JTAG VPI data: nb_bits=%d, buf_in=0x%s%s",
 			nb_bits, char_buf, (nb_bits > DEBUG_JTAG_IOZ) ? "(...)" : "");
 		free(char_buf);
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index 8b76bff07..1335c2917 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -204,7 +204,7 @@ static int Jim_Command_drscan(Jim_Interp *interp, int argc, Jim_Obj *const *args
 		char *str;
 
 		Jim_GetLong(interp, args[i], &bits);
-		str = buf_to_str(fields[field_count].in_value, bits, 16);
+		str = buf_to_hex_str(fields[field_count].in_value, bits);
 		free(fields[field_count].in_value);
 
 		Jim_ListAppendElement(interp, list, Jim_NewStringObj(interp, str, strlen(str)));
diff --git a/src/target/target.c b/src/target/target.c
index 4ef5ee19e..affee03b9 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -2897,8 +2897,8 @@ COMMAND_HANDLER(handle_reg_command)
 					continue;
 				/* only print cached values if they are valid */
 				if (reg->valid) {
-					value = buf_to_str(reg->value,
-							reg->size, 16);
+					value = buf_to_hex_str(reg->value,
+							reg->size);
 					command_print(CMD,
 							"(%i) %s (/%" PRIu32 "): 0x%s%s",
 							count, reg->name,
@@ -2965,7 +2965,7 @@ COMMAND_HANDLER(handle_reg_command)
 
 		if (reg->valid == 0)
 			reg->type->get(reg);
-		value = buf_to_str(reg->value, reg->size, 16);
+		value = buf_to_hex_str(reg->value, reg->size);
 		command_print(CMD, "%s (/%i): 0x%s", reg->name, (int)(reg->size), value);
 		free(value);
 		return ERROR_OK;
@@ -2980,7 +2980,7 @@ COMMAND_HANDLER(handle_reg_command)
 
 		reg->type->set(reg, buf);
 
-		value = buf_to_str(reg->value, reg->size, 16);
+		value = buf_to_hex_str(reg->value, reg->size);
 		command_print(CMD, "%s (/%i): 0x%s", reg->name, (int)(reg->size), value);
 		free(value);
 
@@ -3744,8 +3744,8 @@ static int handle_bp_command_list(struct command_invocation *cmd)
 	struct breakpoint *breakpoint = target->breakpoints;
 	while (breakpoint) {
 		if (breakpoint->type == BKPT_SOFT) {
-			char *buf = buf_to_str(breakpoint->orig_instr,
-					breakpoint->length, 16);
+			char *buf = buf_to_hex_str(breakpoint->orig_instr,
+					breakpoint->length);
 			command_print(cmd, "IVA breakpoint: " TARGET_ADDR_FMT ", 0x%x, %i, 0x%s",
 					breakpoint->address,
 					breakpoint->length,

-----------------------------------------------------------------------

Summary of changes:
 src/helper/binarybuffer.c   | 41 ++++++++---------------------------------
 src/helper/binarybuffer.h   |  2 +-
 src/jtag/commands.c         |  8 ++++----
 src/jtag/core.c             | 14 +++++++-------
 src/jtag/drivers/jtag_vpi.c | 10 ++++------
 src/jtag/tcl.c              |  2 +-
 src/target/target.c         | 12 ++++++------
 tcl/board/st_nucleo_l1.cfg  |  2 +-
 8 files changed, 32 insertions(+), 59 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-1384-g764b25c81

[OpenOCD-Gerrit <ope...@us...>]

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      from  d46f28c2ea2611f5fbbc679a5eed253d3dcd2fe3 (commit)

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- Log -----------------------------------------------------------------
commit 764b25c81481225d425ff711b9ba11fca1d91b31
Author: Jan Kowalewski <jko...@an...>
Date:   Fri Aug 14 12:21:54 2020 +0200

    tcl/interface/ftdi: fix comment in minimodule-swd.cfg
    
    Change-Id: I160faca11f231e3e839046ae2045e37e350ca613
    Signed-off-by: Jan Kowalewski <jko...@an...>
    Reviewed-on: http://openocd.zylin.com/5804
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/interface/ftdi/minimodule-swd.cfg b/tcl/interface/ftdi/minimodule-swd.cfg
index 7ab46503e..4bc331edb 100644
--- a/tcl/interface/ftdi/minimodule-swd.cfg
+++ b/tcl/interface/ftdi/minimodule-swd.cfg
@@ -1,5 +1,5 @@
 #
-Supports SWD using the FT2232H or FT4232H minimodule.
+# Supports SWD using the FT2232H or FT4232H minimodule.
 # Each can support 2 SWD interfaces.
 #
 # FT2232H or FT4232H minimodule channel 0 (Channel A)

-----------------------------------------------------------------------

Summary of changes:
 tcl/interface/ftdi/minimodule-swd.cfg | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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- Log -----------------------------------------------------------------
commit d46f28c2ea2611f5fbbc679a5eed253d3dcd2fe3
Author: Andreas Fritiofson <and...@gm...>
Date:   Tue Jun 2 19:37:49 2020 +0200

    Refer to cross-build script in README
    
    Change-Id: Ic983d2505e40891ba0d0eea3468a71a7741f5c3a
    Signed-off-by: Andreas Fritiofson <and...@gm...>
    Reviewed-on: http://openocd.zylin.com/5711
    Tested-by: jenkins
    Reviewed-by: Tarek BOCHKATI <tar...@gm...>

diff --git a/README b/README
index fe70e725f..900324ab1 100644
--- a/README
+++ b/README
@@ -284,6 +284,10 @@ libraries that OpenOCD depends on. Alternatively, you can specify
 *_CFLAGS and *_LIBS environment variables directly, see "./configure
 --help" for the details.
 
+For a more or less complete script that does all this for you, see
+
+  contrib/cross-build.sh
+
 Parallel Port Dongles
 ---------------------
 

-----------------------------------------------------------------------

Summary of changes:
 README | 4 ++++
 1 file changed, 4 insertions(+)


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