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commit b8735bbf7ed7eedb0590edbf2a22929b401887ba
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Oct 16 23:56:23 2022 +0200

    doc: fix riscv commands
    
    - Fix the declaration of riscv command 'set_mem_access'.
    - Remove non existing riscv command 'set_scratch_ram'.
    - Add riscv commands 'info', 'reset_delays'; copy the description
      from the 'help' text.
    - Don't add riscv commands 'set_prefer_sba' and 'test_sba_config_reg'
      as they are marked as deprecated.
    - Ensure that 'test_sba_config_reg' prints a deprecation warning
      when used.
    
    Change-Id: I39dc3aec4e7f13b69ac19685f1b593790acdde83
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Signed-off-by: Jan Matyas <ma...@co...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7268
    Reviewed-by: Tim Newsome <ti...@si...>
    Tested-by: jenkins

diff --git a/doc/openocd.texi b/doc/openocd.texi
index ba495ccd1..6321bf7a6 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -10649,6 +10649,16 @@ $_TARGETNAME expose_custom 32=myregister
 @end example
 @end deffn
 
+@deffn {Command} {riscv info}
+Displays some information OpenOCD detected about the target.
+@end deffn
+
+@deffn {Command} {riscv reset_delays} [wait]
+OpenOCD learns how many Run-Test/Idle cycles are required between scans to avoid
+encountering the target being busy. This command resets those learned values
+after `wait` scans. It's only useful for testing OpenOCD itself.
+@end deffn
+
 @deffn {Command} {riscv set_command_timeout_sec} [seconds]
 Set the wall-clock timeout (in seconds) for individual commands. The default
 should work fine for all but the slowest targets (eg. simulators).
@@ -10659,12 +10669,7 @@ Set the maximum time to wait for a hart to come out of reset after reset is
 deasserted.
 @end deffn
 
-@deffn {Command} {riscv set_scratch_ram} none|[address]
-Set the address of 16 bytes of scratch RAM the debugger can use, or 'none'.
-This is used to access 64-bit floating point registers on 32-bit targets.
-@end deffn
-
-@deffn Command {riscv set_mem_access} method1 [method2] [method3]
+@deffn {Command} {riscv set_mem_access} method1 [method2] [method3]
 Specify which RISC-V memory access method(s) shall be used, and in which order
 of priority. At least one method must be specified.
 
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index ae0a7375d..4f24fb41e 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -2744,6 +2744,9 @@ COMMAND_HANDLER(riscv_dmi_write)
 
 COMMAND_HANDLER(riscv_test_sba_config_reg)
 {
+	LOG_WARNING("Command \"riscv test_sba_config_reg\" is deprecated. "
+		"It will be removed in a future OpenOCD version.");
+
 	if (CMD_ARGC != 4) {
 		LOG_ERROR("Command takes exactly 4 arguments");
 		return ERROR_COMMAND_SYNTAX_ERROR;

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi         | 17 +++++++++++------
 src/target/riscv/riscv.c |  3 +++
 2 files changed, 14 insertions(+), 6 deletions(-)


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commit 1f7d58daeef9d695529af0cc41c52095c8936c80
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Oct 17 12:19:18 2022 +0200

    doc: remove unreferenced anchors
    
    Remove the @anchor{} tags that are not referenced in the
    documentation.
    
    Change-Id: Ia8e9f75afb08e08ef99d0c8fd82115d689e4a267
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7270
    Tested-by: jenkins

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 1768e455d..ba495ccd1 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1785,7 +1785,6 @@ $_TARGETNAME configure -work-area-phys 0x00200000 \
              -work-area-size 0x4000 -work-area-backup 0
 @end example
 
-@anchor{definecputargetsworkinginsmp}
 @subsection Define CPU targets working in SMP
 @cindex SMP
 After setting targets, you can define a list of targets working in SMP.
@@ -1939,7 +1938,6 @@ For an example of this scheme see LPC2000 target config files.
 The @code{init_boards} procedure is a similar concept concerning board config files
 (@xref{theinitboardprocedure,,The init_board procedure}.)
 
-@anchor{theinittargeteventsprocedure}
 @subsection The init_target_events procedure
 @cindex init_target_events procedure
 
@@ -2468,7 +2466,6 @@ the generic mapping may not support all of the listed options.
 Returns the name of the debug adapter driver being used.
 @end deffn
 
-@anchor{adapter_usb_location}
 @deffn {Config Command} {adapter usb location} [<bus>-<port>[.<port>]...]
 Displays or specifies the physical USB port of the adapter to use. The path
 roots at @var{bus} and walks down the physical ports, with each
@@ -6205,7 +6202,6 @@ the flash.
 @end deffn
 @end deffn
 
-@anchor{at91samd}
 @deffn {Flash Driver} {at91samd}
 @cindex at91samd
 All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi | 4 ----
 1 file changed, 4 deletions(-)


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commit 28ad1a14546ef6eb4a77c11a977d785e50e1f51a
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Oct 17 00:08:52 2022 +0200

    doc: fix espusbjtag commands type
    
    Exec commands should be reported as {Command}.
    
    Change-Id: Iacb50d77b354617ecd24b0f1c2ec24e240179698
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7267
    Tested-by: jenkins
    Reviewed-by: Erhan Kurubas <erh...@es...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index b603a4679..1768e455d 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -3504,11 +3504,11 @@ Espressif JTAG driver to communicate with ESP32-C3, ESP32-S3 chips and ESP USB B
 These chips have built-in JTAG circuitry and can be debugged without any additional hardware.
 Only an USB cable connected to the D+/D- pins is necessary.
 
-@deffn {Config Command} {espusbjtag tdo}
+@deffn {Command} {espusbjtag tdo}
 Returns the current state of the TDO line
 @end deffn
 
-@deffn {Config Command} {espusbjtag setio} setio
+@deffn {Command} {espusbjtag setio} setio
 Manually set the status of the output lines with the order of (tdi tms tck trst srst)
 @example
 espusbjtag setio 0 1 0 1 0

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


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commit f0a9b66d13766dec86d1a614a88899b27fd43645
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Oct 16 23:36:15 2022 +0200

    doc: fix xtensa commands type
    
    Config commands should be reported as {Config Command}
    
    Change-Id: Ic778df31bb1dc9aefdbe3d8006b06bb370d25e6f
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7266
    Tested-by: jenkins
    Reviewed-by: Ian Thompson <ia...@ca...>
    Reviewed-by: Erhan Kurubas <erh...@es...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 2a8626b80..b603a4679 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -10976,12 +10976,12 @@ NXP}.
 
 @subsection Xtensa Configuration Commands
 
-@deffn {Command} {xtensa xtdef} (@option{LX}|@option{NX})
+@deffn {Config Command} {xtensa xtdef} (@option{LX}|@option{NX})
 Configure the Xtensa target architecture. Currently, Xtensa support is limited
 to LX6, LX7, and NX cores.
 @end deffn
 
-@deffn {Command} {xtensa xtopt} option value
+@deffn {Config Command} {xtensa xtopt} option value
 Configure Xtensa target options that are relevant to the debug subsystem.
 @var{option} is one of: @option{arnum}, @option{windowed},
 @option{cpenable}, @option{exceptions}, @option{intnum}, @option{hipriints},
@@ -10993,35 +10993,35 @@ NOTE: Some options are specific to Xtensa LX or Xtensa NX architecture, while
 others may be common to both but have different valid ranges.
 @end deffn
 
-@deffn {Command} {xtensa xtmem} (@option{iram}|@option{dram}|@option{sram}|@option{irom}|@option{drom}|@option{srom}) baseaddr bytes
+@deffn {Config Command} {xtensa xtmem} (@option{iram}|@option{dram}|@option{sram}|@option{irom}|@option{drom}|@option{srom}) baseaddr bytes
 Configure Xtensa target memory. Memory type determines access rights,
 where RAMs are read/write while ROMs are read-only. @var{baseaddr} and
 @var{bytes} are both integers, typically hexadecimal and decimal, respectively.
 @end deffn
 
-@deffn {Command} {xtensa xtmem} (@option{icache}|@option{dcache}) linebytes cachebytes ways [writeback]
+@deffn {Config Command} {xtensa xtmem} (@option{icache}|@option{dcache}) linebytes cachebytes ways [writeback]
 Configure Xtensa processor cache. All parameters are required except for
 the optional @option{writeback} parameter; all are integers.
 @end deffn
 
-@deffn {Command} {xtensa xtmpu} numfgseg minsegsz lockable execonly
+@deffn {Config Command} {xtensa xtmpu} numfgseg minsegsz lockable execonly
 Configure an Xtensa Memory Protection Unit (MPU). MPUs can restrict access
 and/or control cacheability of specific address ranges, but are lighter-weight
 than a full traditional MMU. All parameters are required; all are integers.
 @end deffn
 
-@deffn {Command} {xtensa xtmmu} numirefillentries numdrefillentries
+@deffn {Config Command} {xtensa xtmmu} numirefillentries numdrefillentries
 (Xtensa-LX only) Configure an Xtensa Memory Management Unit (MMU). Both
 parameters are required; both are integers.
 @end deffn
 
-@deffn {Command} {xtensa xtregs} numregs
+@deffn {Config Command} {xtensa xtregs} numregs
 Configure the total number of registers for the Xtensa core. Configuration
 logic expects to subsequently process this number of @code{xtensa xtreg}
 definitions. @var{numregs} is an integer.
 @end deffn
 
-@deffn {Command} {xtensa xtregfmt} (@option{sparse}|@option{contiguous}) [general]
+@deffn {Config Command} {xtensa xtregfmt} (@option{sparse}|@option{contiguous}) [general]
 Configure the type of register map used by GDB to access the Xtensa core.
 Generic Xtensa tools (e.g. xt-gdb) require @option{sparse} mapping (default) while
 Espressif tools expect @option{contiguous} mapping. Contiguous mapping takes an
@@ -11029,7 +11029,7 @@ additional, optional integer parameter @option{numgregs}, which specifies the nu
 of general registers used in handling g/G packets.
 @end deffn
 
-@deffn {Command} {xtensa xtreg} name offset
+@deffn {Config Command} {xtensa xtreg} name offset
 Configure an Xtensa core register. All core registers are 32 bits wide,
 while TIE and user registers may have variable widths. @var{name} is a
 character string identifier while @var{offset} is a hexadecimal integer.

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)


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commit ee87f2b4a9cac084903087aed6ff8e3a691c674b
Author: Jonathan Bell <jon...@ra...>
Date:   Thu Oct 13 10:38:53 2022 +0100

    jtag/drivers: bcm2835gpio: implement memory barriers when bitbashing
    
    This GPIO driver is common to SoCs that have in-order ARM cores
    (BCM2835) as well as superscalar (BCM2836-7) and speculative
    out-of-order cores (BCM2711).
    
    For BCM2837 and BCM2711, the processor can dual-issue stores and
    is free to merge writes to peripheral memory for pages mapped
    MT_NORMAL_NC, which is the default provided by /dev/[gpio]mem.
    
    This can cause glitches (or missing edges) on GPIO pins when
    toggled with no delay, as pipelined writes to the same address
    can get arbitrarily squelched.
    
    To prevent this happening, make sure the preceding write ops are
    flushed outside the shareable domain by using a memory barrier.
    
    Signed-off-by: Jonathan Bell <jon...@ra...>
    Change-Id: I8805cc0911667bcb9b7f4ca340d7f4f1cb25d096
    Reviewed-on: https://review.openocd.org/c/openocd/+/7258
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/jtag/drivers/bcm2835gpio.c b/src/jtag/drivers/bcm2835gpio.c
index bd44fca07..5aa1a99e4 100644
--- a/src/jtag/drivers/bcm2835gpio.c
+++ b/src/jtag/drivers/bcm2835gpio.c
@@ -57,6 +57,15 @@ static struct initial_gpio_state {
 } initial_gpio_state[ADAPTER_GPIO_IDX_NUM];
 static uint32_t initial_drive_strength_etc;
 
+static inline void bcm2835_gpio_synchronize(void)
+{
+	/* Ensure that previous writes to GPIO registers are flushed out of
+	 * the inner shareable domain to prevent pipelined writes to the
+	 * same address being merged.
+	 */
+	__sync_synchronize();
+}
+
 static bool is_gpio_config_valid(enum adapter_gpio_config_index idx)
 {
 	/* Only chip 0 is supported, accept unset value (-1) too */
@@ -96,6 +105,7 @@ static void set_gpio_value(const struct adapter_gpio_config *gpio_config, int va
 		}
 		break;
 	}
+	bcm2835_gpio_synchronize();
 }
 
 static void restore_gpio(enum adapter_gpio_config_index idx)
@@ -109,6 +119,7 @@ static void restore_gpio(enum adapter_gpio_config_index idx)
 				GPIO_CLR = 1 << adapter_gpio_config[idx].gpio_num;
 		}
 	}
+	bcm2835_gpio_synchronize();
 }
 
 static void initialize_gpio(enum adapter_gpio_config_index idx)
@@ -143,6 +154,7 @@ static void initialize_gpio(enum adapter_gpio_config_index idx)
 	/* Direction for non push-pull is already set by set_gpio_value() */
 	if (adapter_gpio_config[idx].drive == ADAPTER_GPIO_DRIVE_MODE_PUSH_PULL)
 		OUT_GPIO(adapter_gpio_config[idx].gpio_num);
+	bcm2835_gpio_synchronize();
 }
 
 static bb_value_t bcm2835gpio_read(void)
@@ -164,6 +176,7 @@ static int bcm2835gpio_write(int tck, int tms, int tdi)
 
 	GPIO_SET = set;
 	GPIO_CLR = clear;
+	bcm2835_gpio_synchronize();
 
 	for (unsigned int i = 0; i < jtag_delay; i++)
 		asm volatile ("");
@@ -184,6 +197,7 @@ static int bcm2835gpio_swd_write_fast(int swclk, int swdio)
 
 	GPIO_SET = set;
 	GPIO_CLR = clear;
+	bcm2835_gpio_synchronize();
 
 	for (unsigned int i = 0; i < jtag_delay; i++)
 		asm volatile ("");
@@ -234,6 +248,7 @@ static void bcm2835_swdio_drive(bool is_output)
 		if (is_gpio_config_valid(ADAPTER_GPIO_IDX_SWDIO_DIR))
 			set_gpio_value(&adapter_gpio_config[ADAPTER_GPIO_IDX_SWDIO_DIR], 0);
 	}
+	bcm2835_gpio_synchronize();
 }
 
 static int bcm2835_swdio_read(void)

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/bcm2835gpio.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)


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commit a7ea1ef0aa00920c7c7cb9282080e1d617eb9e81
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Oct 9 17:22:37 2022 +0200

    README: update build dependency list
    
    Add info on what is optional,
    
    Change-Id: Iedfa969243d95736aaf1b236caa2c2b33f563fe7
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7256
    Tested-by: jenkins

diff --git a/README b/README
index d58d377c7..08b8117db 100644
--- a/README
+++ b/README
@@ -221,19 +221,35 @@ You'll also need:
 - libtool
 - pkg-config >= 0.23 or pkgconf
 
+OpenOCD uses jimtcl library; build from git can retrieve jimtcl as git
+submodule.
+
 Additionally, for building from git:
 
 - autoconf >= 2.69
 - automake >= 1.14
 - texinfo >= 5.0
 
-USB-based adapters depend on libusb-1.0.
+Optional USB-based adapter drivers need libusb-1.0.
 
-USB-Blaster, ASIX Presto and OpenJTAG interface adapter
+Optional USB-Blaster, ASIX Presto and OpenJTAG interface adapter
 drivers need:
   - libftdi: http://www.intra2net.com/en/developer/libftdi/index.php
 
-CMSIS-DAP support needs HIDAPI library.
+Optional CMSIS-DAP adapter driver needs HIDAPI library.
+
+Optional linuxgpiod adapter driver needs libgpiod library.
+
+Optional JLink adapter driver needs libjaylink; build from git can
+retrieve libjaylink as git submodule.
+
+Optional ARM disassembly needs capstone library.
+
+Optional development script checkpatch needs:
+
+- perl
+- python
+- python-ply
 
 Permissions delegation
 ----------------------

-----------------------------------------------------------------------

Summary of changes:
 README | 22 +++++++++++++++++++---
 1 file changed, 19 insertions(+), 3 deletions(-)


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commit 1c5c1d1782f73fce377bbaacaab19b19ca43157b
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Oct 9 17:16:16 2022 +0200

    README: cleanup requirements for pkg-config
    
    FreeBSD fully supports pkg-config; the .pc files for the internal
    libusb has been added with
            https://cgit.freebsd.org/src/commit/?id=041d3f3f09b8
    and became part of FreeBSD 10.0 in 2014-01-16.
    
    Remove the obsoleted requirements for adding .pc files.
    
    While there, add pkgconf as an alternative to pkg-config.
    
    Change-Id: I16aea735c44107cb71945f225a979682c8c92d0a
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7255
    Reviewed-by: Paul Fertser <fer...@gm...>
    Tested-by: jenkins

diff --git a/README b/README
index 3c07d7cfe..d58d377c7 100644
--- a/README
+++ b/README
@@ -219,7 +219,7 @@ You'll also need:
 
 - make
 - libtool
-- pkg-config >= 0.23 (or compatible)
+- pkg-config >= 0.23 or pkgconf
 
 Additionally, for building from git:
 
@@ -227,8 +227,7 @@ Additionally, for building from git:
 - automake >= 1.14
 - texinfo >= 5.0
 
-USB-based adapters depend on libusb-1.0. A compatible implementation, such as
-FreeBSD's, additionally needs the corresponding .pc files.
+USB-based adapters depend on libusb-1.0.
 
 USB-Blaster, ASIX Presto and OpenJTAG interface adapter
 drivers need:

commit 3b8333bd3f33ce263245e67706e2bf9e30dd27d0
Author: Erhan Kurubas <erh...@es...>
Date:   Tue Oct 4 22:54:58 2022 +0200

    target/xtensa: fill register number field in the cache
    
    Currently 'number' field is zero in the register cache and
    this causes an issue on `rtos get_thread_reg_list` calls.
    
    Signed-off-by: Erhan Kurubas <erh...@es...>
    Change-Id: Iaef11e01f55d012969bbc1933f82847d5e02fec5
    Reviewed-on: https://review.openocd.org/c/openocd/+/7246
    Tested-by: jenkins
    Reviewed-by: Ian Thompson <ia...@ca...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index faff0afa8..c1b5f43c8 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -2503,6 +2503,12 @@ static int xtensa_build_reg_cache(struct target *target)
 			unsigned int j;
 			for (j = 0; j < reg_cache->num_regs; j++) {
 				if (!strcmp(reg_cache->reg_list[j].name, xtensa->contiguous_regs_desc[i]->name)) {
+					/*	Register number field is not filled above.
+						Here we are assigning the corresponding index from the contiguous reg list.
+						These indexes are in the same order with gdb g-packet request/response.
+						Some more changes may be required for sparse reg lists.
+					*/
+					reg_cache->reg_list[j].number = i;
 					xtensa->contiguous_regs_list[i] = &(reg_cache->reg_list[j]);
 					LOG_TARGET_DEBUG(target,
 						"POPULATE contiguous regs list: %-16s, dbreg_num 0x%04x",

-----------------------------------------------------------------------

Summary of changes:
 README                     | 5 ++---
 src/target/xtensa/xtensa.c | 6 ++++++
 2 files changed, 8 insertions(+), 3 deletions(-)


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- Log -----------------------------------------------------------------
commit 2d5d8a5a621811d0ea58d3bdb90afc17f0cce4ac
Author: Erhan Kurubas <erh...@es...>
Date:   Wed Oct 5 00:49:23 2022 +0200

    target/esp32s2: check xtensa_poll return value
    
    Although scan build couldn't catch, return value overwritten
    without checking.
    
    Signed-off-by: Erhan Kurubas <erh...@es...>
    Change-Id: I02b10002b03640604315047e8a8a639824724c16
    Reviewed-on: https://review.openocd.org/c/openocd/+/7247
    Tested-by: jenkins
    Reviewed-by: Ian Thompson <ia...@ca...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/espressif/esp32s2.c b/src/target/espressif/esp32s2.c
index 62d1ddb1d..64fa69057 100644
--- a/src/target/espressif/esp32s2.c
+++ b/src/target/espressif/esp32s2.c
@@ -402,6 +402,8 @@ static int esp32s2_poll(struct target *target)
 {
 	enum target_state old_state = target->state;
 	int ret = esp_xtensa_poll(target);
+	if (ret != ERROR_OK)
+		return ret;
 
 	if (old_state != TARGET_HALTED && target->state == TARGET_HALTED) {
 		/* Call any event callbacks that are applicable */

-----------------------------------------------------------------------

Summary of changes:
 src/target/espressif/esp32s2.c | 2 ++
 1 file changed, 2 insertions(+)


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commit 45c9e1e8c0809bc4305f269db239641151c6004d
Author: Erhan Kurubas <erh...@es...>
Date:   Tue Oct 4 23:23:55 2022 +0200

    tcl/xtensa: some fixes at xtensa-core-esp32s3.cfg
    
    Some config changes required to run ESP32-S3 with full feature set
    
    Signed-off-by: Erhan Kurubas <erh...@es...>
    Change-Id: I38022bb5ff5830e1cf9d11d6fe795ea99d91e9db
    Reviewed-on: https://review.openocd.org/c/openocd/+/7254
    Tested-by: jenkins
    Reviewed-by: Ian Thompson <ia...@ca...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/xtensa-core-esp32s3.cfg b/tcl/target/xtensa-core-esp32s3.cfg
index f5c1cb3ee..b3f20e39d 100644
--- a/tcl/target/xtensa-core-esp32s3.cfg
+++ b/tcl/target/xtensa-core-esp32s3.cfg
@@ -20,6 +20,7 @@ xtensa xtmem	irom				0x40000000	0x60000
 xtensa xtmem	iram				0x40370000	0x70000
 xtensa xtmem	iram				0x600FE000	0x2000
 xtensa xtmem	drom				0x3C000000	0x1000000
+xtensa xtmem	drom				0x3FF00000	0x20000
 xtensa xtmem	dram				0x3FC88000	0x78000
 xtensa xtmem	dram				0x600FE000	0x2000
 xtensa xtmem	dram				0x50000000	0x2000
@@ -31,8 +32,8 @@ xtensa xtmem	dram				0x60000000	0x10000000
 xtensa xtopt	debuglevel			6
 xtensa xtopt	ibreaknum			2
 xtensa xtopt	dbreaknum			2
-xtensa xtopt	tracemem			16384
-xtensa xtopt	tracememrev			1
+xtensa xtopt	tracemem			0x4000
+xtensa xtopt	tracememrev			0
 xtensa xtopt	perfcount			2
 
 
@@ -43,7 +44,7 @@ xtensa xtopt	perfcount			2
 #				in "Read General Registers" (g-packet) requests.
 #				NOTE: For contiguous format, registers listed in GDB order.
 #  xtregs:		Total number of Xtensa registers in the system
-xtensa xtregs	244
+xtensa xtregs	228
 xtensa xtregfmt	contiguous			128
 xtensa xtreg	pc					0x0020
 xtensa xtreg	ar0					0x0100
@@ -128,10 +129,7 @@ xtensa xtreg	m0					0x0220
 xtensa xtreg	m1					0x0221
 xtensa xtreg	m2					0x0222
 xtensa xtreg	m3					0x0223
-
-# TODO: update gpioout address while testing on S3 HW
-xtensa xtreg	gpioout				0x02f4
-
+xtensa xtreg	gpio_out			0x030c
 xtensa xtreg	f0					0x0030
 xtensa xtreg	f1					0x0031
 xtensa xtreg	f2					0x0032
@@ -150,35 +148,32 @@ xtensa xtreg	f14					0x003e
 xtensa xtreg	f15					0x003f
 xtensa xtreg	fcr					0x03e8
 xtensa xtreg	fsr					0x03e9
-
-# TODO: update TIE state
-xtensa xtreg	accx_0				0x02f4
-xtensa xtreg	accx_1				0x02f4
-xtensa xtreg	qacc_h_0			0x02f4
-xtensa xtreg	qacc_h_1			0x02f4
-xtensa xtreg	qacc_h_2			0x02f4
-xtensa xtreg	qacc_h_3			0x02f4
-xtensa xtreg	qacc_h_4			0x02f4
-xtensa xtreg	qacc_l_0			0x02f4
-xtensa xtreg	qacc_l_1			0x02f4
-xtensa xtreg	qacc_l_2			0x02f4
-xtensa xtreg	qacc_l_3			0x02f4
-xtensa xtreg	qacc_l_4			0x02f4
-xtensa xtreg	sar_byte			0x02f4
-xtensa xtreg	fft_bit_width		0x02f4
-xtensa xtreg	ua_state_0			0x02f4
-xtensa xtreg	ua_state_1			0x02f4
-xtensa xtreg	ua_state_2			0x02f4
-xtensa xtreg	ua_state_3			0x02f4
-xtensa xtreg	q0					0x02f4
-xtensa xtreg	q1					0x02f4
-xtensa xtreg	q2					0x02f4
-xtensa xtreg	q3					0x02f4
-xtensa xtreg	q4					0x02f4
-xtensa xtreg	q5					0x02f4
-xtensa xtreg	q6					0x02f4
-xtensa xtreg	q7					0x02f4
-
+xtensa xtreg	accx_0				0x0300
+xtensa xtreg	accx_1				0x0301
+xtensa xtreg	qacc_h_0			0x0302
+xtensa xtreg	qacc_h_1			0x0303
+xtensa xtreg	qacc_h_2			0x0304
+xtensa xtreg	qacc_h_3			0x0305
+xtensa xtreg	qacc_h_4			0x0306
+xtensa xtreg	qacc_l_0			0x0307
+xtensa xtreg	qacc_l_1			0x0308
+xtensa xtreg	qacc_l_2			0x0309
+xtensa xtreg	qacc_l_3			0x030a
+xtensa xtreg	qacc_l_4			0x030b
+xtensa xtreg	sar_byte			0x030d
+xtensa xtreg	fft_bit_width		0x030e
+xtensa xtreg	ua_state_0			0x030f
+xtensa xtreg	ua_state_1			0x0310
+xtensa xtreg	ua_state_2			0x0311
+xtensa xtreg	ua_state_3			0x0312
+xtensa xtreg	q0					0x1008
+xtensa xtreg	q1					0x1009
+xtensa xtreg	q2					0x100a
+xtensa xtreg	q3					0x100b
+xtensa xtreg	q4					0x100c
+xtensa xtreg	q5					0x100d
+xtensa xtreg	q6					0x100e
+xtensa xtreg	q7					0x100f
 xtensa xtreg	mmid				0x0259
 xtensa xtreg	ibreakenable		0x0260
 xtensa xtreg	memctl				0x0261
@@ -231,38 +226,38 @@ xtensa xtreg	misc0				0x02f4
 xtensa xtreg	misc1				0x02f5
 xtensa xtreg	misc2				0x02f6
 xtensa xtreg	misc3				0x02f7
-xtensa xtreg	pwrctl				0x2025
-xtensa xtreg	pwrstat				0x2026
-xtensa xtreg	eristat				0x2027
-xtensa xtreg	cs_itctrl			0x2028
-xtensa xtreg	cs_claimset			0x2029
-xtensa xtreg	cs_claimclr			0x202a
-xtensa xtreg	cs_lockaccess		0x202b
-xtensa xtreg	cs_lockstatus		0x202c
-xtensa xtreg	cs_authstatus		0x202d
-xtensa xtreg	fault_info			0x203c
-xtensa xtreg	trax_id				0x203d
-xtensa xtreg	trax_control		0x203e
-xtensa xtreg	trax_status			0x203f
-xtensa xtreg	trax_data			0x2040
-xtensa xtreg	trax_address		0x2041
-xtensa xtreg	trax_pctrigger		0x2042
-xtensa xtreg	trax_pcmatch		0x2043
-xtensa xtreg	trax_delay			0x2044
-xtensa xtreg	trax_memstart		0x2045
-xtensa xtreg	trax_memend			0x2046
-xtensa xtreg	pmg					0x2054
-xtensa xtreg	pmpc				0x2055
-xtensa xtreg	pm0					0x2056
-xtensa xtreg	pm1					0x2057
-xtensa xtreg	pmctrl0				0x2058
-xtensa xtreg	pmctrl1				0x2059
-xtensa xtreg	pmstat0				0x205a
-xtensa xtreg	pmstat1				0x205b
-xtensa xtreg	ocdid				0x205c
-xtensa xtreg	ocd_dcrclr			0x205d
-xtensa xtreg	ocd_dcrset			0x205e
-xtensa xtreg	ocd_dsr				0x205f
+xtensa xtreg	pwrctl				0x2028
+xtensa xtreg	pwrstat				0x2029
+xtensa xtreg	eristat				0x202a
+xtensa xtreg	cs_itctrl			0x202b
+xtensa xtreg	cs_claimset			0x202c
+xtensa xtreg	cs_claimclr			0x202d
+xtensa xtreg	cs_lockaccess		0x202e
+xtensa xtreg	cs_lockstatus		0x202f
+xtensa xtreg	cs_authstatus		0x2030
+xtensa xtreg	fault_info			0x203f
+xtensa xtreg	trax_id				0x2040
+xtensa xtreg	trax_control		0x2041
+xtensa xtreg	trax_status			0x2042
+xtensa xtreg	trax_data			0x2043
+xtensa xtreg	trax_address		0x2044
+xtensa xtreg	trax_pctrigger		0x2045
+xtensa xtreg	trax_pcmatch		0x2046
+xtensa xtreg	trax_delay			0x2047
+xtensa xtreg	trax_memstart		0x2048
+xtensa xtreg	trax_memend			0x2049
+xtensa xtreg	pmg					0x2057
+xtensa xtreg	pmpc				0x2058
+xtensa xtreg	pm0					0x2059
+xtensa xtreg	pm1					0x205a
+xtensa xtreg	pmctrl0				0x205b
+xtensa xtreg	pmctrl1				0x205c
+xtensa xtreg	pmstat0				0x205d
+xtensa xtreg	pmstat1				0x205e
+xtensa xtreg	ocdid				0x205f
+xtensa xtreg	ocd_dcrclr			0x2060
+xtensa xtreg	ocd_dcrset			0x2061
+xtensa xtreg	ocd_dsr				0x2062
 xtensa xtreg	a0					0x0000
 xtensa xtreg	a1					0x0001
 xtensa xtreg	a2					0x0002
@@ -279,19 +274,3 @@ xtensa xtreg	a12					0x000c
 xtensa xtreg	a13					0x000d
 xtensa xtreg	a14					0x000e
 xtensa xtreg	a15					0x000f
-xtensa xtreg	b0					0x0010
-xtensa xtreg	b1					0x0011
-xtensa xtreg	b2					0x0012
-xtensa xtreg	b3					0x0013
-xtensa xtreg	b4					0x0014
-xtensa xtreg	b5					0x0015
-xtensa xtreg	b6					0x0016
-xtensa xtreg	b7					0x0017
-xtensa xtreg	b8					0x0018
-xtensa xtreg	b9					0x0019
-xtensa xtreg	b10					0x001a
-xtensa xtreg	b11					0x001b
-xtensa xtreg	b12					0x001c
-xtensa xtreg	b13					0x001d
-xtensa xtreg	b14					0x001e
-xtensa xtreg	b15					0x001f

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/xtensa-core-esp32s3.cfg | 147 ++++++++++++++++---------------------
 1 file changed, 63 insertions(+), 84 deletions(-)


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- Log -----------------------------------------------------------------
commit 48317d86d3c45a855edfd4e7a86c8c6a8a5ac798
Author: Erhan Kurubas <erh...@es...>
Date:   Tue Oct 4 23:22:34 2022 +0200

    tcl/xtensa: some fixes at xtensa-core-esp32s2.cfg
    
    Some config changes required to run ESP32-S2 with full feature set
    
    Signed-off-by: Erhan Kurubas <erh...@es...>
    Change-Id: Ie0a742442254ec6e95d4e05be40213b079a94dab
    Reviewed-on: https://review.openocd.org/c/openocd/+/7253
    Tested-by: jenkins
    Reviewed-by: Ian Thompson <ia...@ca...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/xtensa-core-esp32s2.cfg b/tcl/target/xtensa-core-esp32s2.cfg
index e590e510d..b38cb1dbb 100644
--- a/tcl/target/xtensa-core-esp32s2.cfg
+++ b/tcl/target/xtensa-core-esp32s2.cfg
@@ -23,6 +23,7 @@ xtensa xtmem	iram				0x40020000	0x50000
 xtensa xtmem	iram				0x40070000	0x2000
 xtensa xtmem	drom				0x3F000000	0x400000
 xtensa xtmem	drom				0x3F4D3FFC	0xAAC004
+xtensa xtmem	drom				0x3FFA0000	0x10000
 xtensa xtmem	dram				0x3FFB0000	0x50000
 xtensa xtmem	dram				0x3FF9E000	0x2000
 xtensa xtmem	dram				0x50000000	0x2000
@@ -36,8 +37,8 @@ xtensa xtmem	dram				0x60000000	0x20000000
 xtensa xtopt	debuglevel			6
 xtensa xtopt	ibreaknum			2
 xtensa xtopt	dbreaknum			2
-xtensa xtopt	tracemem			8192
-xtensa xtopt	tracememrev			1
+xtensa xtopt	tracemem			0x4000
+xtensa xtopt	tracememrev			0
 xtensa xtopt	perfcount			2
 
 #  Core Registers
@@ -48,7 +49,7 @@ xtensa xtopt	perfcount			2
 #				NOTE: For contiguous format, registers listed in GDB order.
 #  xtregs:		Total number of Xtensa registers in the system
 xtensa xtregs	171
-xtensa xtregfmt	contiguous			72
+xtensa xtregfmt	contiguous			73
 xtensa xtreg	pc					0x0020
 xtensa xtreg	ar0					0x0100
 xtensa xtreg	ar1					0x0101
@@ -121,8 +122,7 @@ xtensa xtreg	configid0			0x02b0
 xtensa xtreg	configid1			0x02d0
 xtensa xtreg	ps					0x02e6
 xtensa xtreg	threadptr			0x03e7
-# gpio_out should be 0x0300? Hits an exception on wrover
-xtensa xtreg	gpio_out			0x0268
+xtensa xtreg	gpio_out			0x0300
 xtensa xtreg	mmid				0x0259
 xtensa xtreg	ibreakenable		0x0260
 xtensa xtreg	ddr					0x0268
@@ -173,6 +173,38 @@ xtensa xtreg	misc0				0x02f4
 xtensa xtreg	misc1				0x02f5
 xtensa xtreg	misc2				0x02f6
 xtensa xtreg	misc3				0x02f7
+xtensa xtreg	pwrctl				0x2014
+xtensa xtreg	pwrstat				0x2015
+xtensa xtreg	eristat				0x2016
+xtensa xtreg	cs_itctrl			0x2017
+xtensa xtreg	cs_claimset			0x2018
+xtensa xtreg	cs_claimclr			0x2019
+xtensa xtreg	cs_lockaccess		0x201a
+xtensa xtreg	cs_lockstatus		0x201b
+xtensa xtreg	cs_authstatus		0x201c
+xtensa xtreg	fault_info			0x202b
+xtensa xtreg	trax_id				0x202c
+xtensa xtreg	trax_control		0x202d
+xtensa xtreg	trax_status			0x202e
+xtensa xtreg	trax_data			0x202f
+xtensa xtreg	trax_address		0x2030
+xtensa xtreg	trax_pctrigger		0x2031
+xtensa xtreg	trax_pcmatch		0x2032
+xtensa xtreg	trax_delay			0x2033
+xtensa xtreg	trax_memstart		0x2034
+xtensa xtreg	trax_memend			0x2035
+xtensa xtreg	pmg					0x2043
+xtensa xtreg	pmpc				0x2044
+xtensa xtreg	pm0					0x2045
+xtensa xtreg	pm1					0x2046
+xtensa xtreg	pmctrl0				0x2047
+xtensa xtreg	pmctrl1				0x2048
+xtensa xtreg	pmstat0				0x2049
+xtensa xtreg	pmstat1				0x204a
+xtensa xtreg	ocdid				0x204b
+xtensa xtreg	ocd_dcrclr			0x204c
+xtensa xtreg	ocd_dcrset			0x204d
+xtensa xtreg	ocd_dsr				0x204e
 xtensa xtreg	a0					0x0000
 xtensa xtreg	a1					0x0001
 xtensa xtreg	a2					0x0002
@@ -189,35 +221,3 @@ xtensa xtreg	a12					0x000c
 xtensa xtreg	a13					0x000d
 xtensa xtreg	a14					0x000e
 xtensa xtreg	a15					0x000f
-xtensa xtreg	pwrctl				0x2028
-xtensa xtreg	pwrstat				0x2029
-xtensa xtreg	eristat				0x202a
-xtensa xtreg	cs_itctrl			0x202b
-xtensa xtreg	cs_claimset			0x202c
-xtensa xtreg	cs_claimclr			0x202d
-xtensa xtreg	cs_lockaccess		0x202e
-xtensa xtreg	cs_lockstatus		0x202f
-xtensa xtreg	cs_authstatus		0x2030
-xtensa xtreg	fault_info			0x203f
-xtensa xtreg	trax_id				0x2040
-xtensa xtreg	trax_control		0x2041
-xtensa xtreg	trax_status			0x2042
-xtensa xtreg	trax_data			0x2043
-xtensa xtreg	trax_address		0x2044
-xtensa xtreg	trax_pctrigger		0x2045
-xtensa xtreg	trax_pcmatch		0x2046
-xtensa xtreg	trax_delay			0x2047
-xtensa xtreg	trax_memstart		0x2048
-xtensa xtreg	trax_memend			0x2049
-xtensa xtreg	pmg					0x2057
-xtensa xtreg	pmpc				0x2058
-xtensa xtreg	pm0					0x2059
-xtensa xtreg	pm1					0x205a
-xtensa xtreg	pmctrl0				0x2061
-xtensa xtreg	pmctrl1				0x2062
-xtensa xtreg	pmstat0				0x2069
-xtensa xtreg	pmstat1				0x206a
-xtensa xtreg	ocdid				0x2071
-xtensa xtreg	ocd_dcrclr			0x2072
-xtensa xtreg	ocd_dcrset			0x2073
-xtensa xtreg	ocd_dsr				0x2074

commit 46a61ea7abd87ac4105419676ef486c8470f4186
Author: Erhan Kurubas <erh...@es...>
Date:   Tue Oct 4 23:20:32 2022 +0200

    tcl/xtensa: some fixes at xtensa-core-esp32.cfg
    
    Some config changes required to run ESP32 with full feature set
    
    Signed-off-by: Erhan Kurubas <erh...@es...>
    Change-Id: I484324f8497ec7934bb73164c638fc5f6460fcc4
    Reviewed-on: https://review.openocd.org/c/openocd/+/7252
    Tested-by: jenkins
    Reviewed-by: Ian Thompson <ia...@ca...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/xtensa-core-esp32.cfg b/tcl/target/xtensa-core-esp32.cfg
index e7b5a20be..9a70072e4 100644
--- a/tcl/target/xtensa-core-esp32.cfg
+++ b/tcl/target/xtensa-core-esp32.cfg
@@ -22,6 +22,7 @@ xtensa xtmem	irom				0x40000000	0x64F00
 xtensa xtmem	iram				0x40070000	0x30000
 xtensa xtmem	iram				0x400C0000	0x2000
 xtensa xtmem	drom				0x3F400000	0x800000
+xtensa xtmem	drom				0x3FF90000	0x10000
 xtensa xtmem	dram				0x3FFAE000	0x52000
 xtensa xtmem	dram				0x3FF80000	0x2000
 xtensa xtmem	dram				0x3F800000	0x400000
@@ -35,7 +36,7 @@ xtensa xtmem	dram				0x60000000	0x20000000
 xtensa xtopt	debuglevel			6
 xtensa xtopt	ibreaknum			2
 xtensa xtopt	dbreaknum			2
-xtensa xtopt	tracemem			8192
+xtensa xtopt	tracemem			0x4000
 xtensa xtopt	tracememrev			1
 xtensa xtopt	perfcount			2
 
@@ -46,7 +47,7 @@ xtensa xtopt	perfcount			2
 #				in "Read General Registers" (g-packet) requests.
 #				NOTE: For contiguous format, registers listed in GDB order.
 #  xtregs:		Total number of Xtensa registers in the system
-xtensa xtregs	205
+xtensa xtregs	173
 xtensa xtregfmt	contiguous			105
 xtensa xtreg	pc					0x0020
 xtensa xtreg	ar0					0x0100
@@ -123,8 +124,6 @@ xtensa xtreg	configid0			0x02b0
 xtensa xtreg	configid1			0x02d0
 xtensa xtreg	ps					0x02e6
 xtensa xtreg	threadptr			0x03e7
-
-# added by hand for esp32
 xtensa xtreg	br					0x0204
 xtensa xtreg	scompare1			0x020c
 xtensa xtreg	acclo				0x0210
@@ -155,13 +154,10 @@ xtensa xtreg	f14					0x003e
 xtensa xtreg	f15					0x003f
 xtensa xtreg	fcr					0x03e8
 xtensa xtreg	fsr					0x03e9
-
 xtensa xtreg	mmid				0x0259
 xtensa xtreg	ibreakenable		0x0260
-
 xtensa xtreg	memctl				0x0261
 xtensa xtreg	atomctl				0x0263
-
 xtensa xtreg	ddr					0x0268
 xtensa xtreg	ibreaka0			0x0280
 xtensa xtreg	ibreaka1			0x0281
@@ -226,35 +222,3 @@ xtensa xtreg	a12					0x000c
 xtensa xtreg	a13					0x000d
 xtensa xtreg	a14					0x000e
 xtensa xtreg	a15					0x000f
-xtensa xtreg	pwrctl				0x2028
-xtensa xtreg	pwrstat				0x2029
-xtensa xtreg	eristat				0x202a
-xtensa xtreg	cs_itctrl			0x202b
-xtensa xtreg	cs_claimset			0x202c
-xtensa xtreg	cs_claimclr			0x202d
-xtensa xtreg	cs_lockaccess		0x202e
-xtensa xtreg	cs_lockstatus		0x202f
-xtensa xtreg	cs_authstatus		0x2030
-xtensa xtreg	fault_info			0x203f
-xtensa xtreg	trax_id				0x2040
-xtensa xtreg	trax_control		0x2041
-xtensa xtreg	trax_status			0x2042
-xtensa xtreg	trax_data			0x2043
-xtensa xtreg	trax_address		0x2044
-xtensa xtreg	trax_pctrigger		0x2045
-xtensa xtreg	trax_pcmatch		0x2046
-xtensa xtreg	trax_delay			0x2047
-xtensa xtreg	trax_memstart		0x2048
-xtensa xtreg	trax_memend			0x2049
-xtensa xtreg	pmg					0x2057
-xtensa xtreg	pmpc				0x2058
-xtensa xtreg	pm0					0x2059
-xtensa xtreg	pm1					0x205a
-xtensa xtreg	pmctrl0				0x2061
-xtensa xtreg	pmctrl1				0x2062
-xtensa xtreg	pmstat0				0x2069
-xtensa xtreg	pmstat1				0x206a
-xtensa xtreg	ocdid				0x2071
-xtensa xtreg	ocd_dcrclr			0x2072
-xtensa xtreg	ocd_dcrset			0x2073
-xtensa xtreg	ocd_dsr				0x2074

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/xtensa-core-esp32.cfg   | 42 ++--------------------
 tcl/target/xtensa-core-esp32s2.cfg | 74 +++++++++++++++++++-------------------
 2 files changed, 40 insertions(+), 76 deletions(-)


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commit 9d5f833fbd47a5a0631fa1f6f1734f277fdde342
Author: Tomas Vanek <va...@fb...>
Date:   Tue Oct 11 19:04:15 2022 +0200

    tcl/target: fix rp2040-core0.cfg work area backup.
    
    The work area should be backed up.
    The flash probe runs an algorithm on the target CPU.
    The flash is probed during gdb connect if gdb_memory_map is enabled
    (is enabled by default).
    Without backup the target memory gets corrupted on gdb connect.
    
    Change-Id: I3344b9dc6cbf904d49f3b05ab104b541d1d63422
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7257
    Tested-by: jenkins
    Reviewed-by: Jonathan Bell <jon...@ra...>

diff --git a/tcl/target/rp2040-core0.cfg b/tcl/target/rp2040-core0.cfg
index 8c3533bfb..6a0f0ed61 100644
--- a/tcl/target/rp2040-core0.cfg
+++ b/tcl/target/rp2040-core0.cfg
@@ -26,7 +26,10 @@ swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
-$_TARGETNAME configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE
+
+# Backup the work area. The flash probe runs an algorithm on the target CPU.
+# The flash is probed during gdb connect if gdb_memory_map is enabled (by default).
+$_TARGETNAME configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup 1
 
 set _FLASHNAME $_CHIPNAME.flash
 set _FLASHSIZE 0x200000

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/rp2040-core0.cfg | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)


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commit dc6cad855d1557e01437ba777b55ad023ddd04ef
Author: Tomas Vanek <va...@fb...>
Date:   Wed Sep 28 23:19:00 2022 +0200

    target: re-examine before arp_waitstate in ocd_process_reset_inner
    
    arp_waitstate will not work on not-examined state
    
    Change-Id: I56c3e1c7e63af108e4ed1dbacebb567f9bf46264
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7230
    Tested-by: jenkins
    Reviewed-by: Erwan Gouriou
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/startup.tcl b/src/target/startup.tcl
index 290e79d1e..35492a6d9 100644
--- a/src/target/startup.tcl
+++ b/src/target/startup.tcl
@@ -114,10 +114,21 @@ proc ocd_process_reset_inner { MODE } {
 				continue
 			}
 
-			# don't wait for targets where examination is deferred
-			# they can not be halted anyway at this point
-			if { ![$t was_examined] && [$t examine_deferred] } {
-				continue
+			if { ![$t was_examined] } {
+				# don't wait for targets where examination is deferred
+				# they can not be halted anyway at this point
+				if { [$t examine_deferred] } {
+					continue
+				}
+				# try to re-examine or target state will be unknown
+				$t invoke-event examine-start
+				set err [catch "$t arp_examine allow-defer"]
+				if { $err } {
+					$t invoke-event examine-fail
+					return -code error [format "TARGET: %s - Not examined" $t]
+				} else {
+					$t invoke-event examine-end
+				}
 			}
 
 			# Wait up to 1 second for target to halt. Why 1sec? Cause

-----------------------------------------------------------------------

Summary of changes:
 src/target/startup.tcl | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)


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commit 1f84f34850de6dde354bfeb41bb1e7bf5d3fa6a0
Author: Tomas Vanek <va...@fb...>
Date:   Wed Sep 28 23:32:00 2022 +0200

    target/hla_target: try to re-examine under reset in hl_assert_reset()
    
    An application often idling in real sleep mode may make a Cortex-M target
    hard to access as CPU clock are gated and debug requests are responded
    by WAIT ack.
    
    Try to examine the target under reset as the last resort.
    
    Change-Id: I7c3de39fb1e6c23b76e2a0a85ab75f23aac94c4d
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7229
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/hla_target.c b/src/target/hla_target.c
index 33126d65a..8c35a90cb 100644
--- a/src/target/hla_target.c
+++ b/src/target/hla_target.c
@@ -347,6 +347,13 @@ static int hl_assert_reset(struct target *target)
 
 	adapter->layout->api->write_debug_reg(adapter->handle, DCB_DHCSR, DBGKEY|C_DEBUGEN);
 
+	if (!target_was_examined(target) && !target->defer_examine
+		&& srst_asserted && res == ERROR_OK) {
+		/* If the target is not examined, now under reset it is good time to retry examination */
+		LOG_TARGET_DEBUG(target, "Trying to re-examine under reset");
+		target_examine_one(target);
+	}
+
 	/* only set vector catch if halt is requested */
 	if (target->reset_halt)
 		adapter->layout->api->write_debug_reg(adapter->handle, DCB_DEMCR, TRCENA|VC_CORERESET);

-----------------------------------------------------------------------

Summary of changes:
 src/target/hla_target.c | 7 +++++++
 1 file changed, 7 insertions(+)


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- Log -----------------------------------------------------------------
commit f65d1da01356e21e07e6c638d58f7c6d09738aa6
Author: Tomas Vanek <va...@fb...>
Date:   Wed Sep 28 23:01:39 2022 +0200

    target/cortex_m: try to re-examine under reset in cortex_m_assert_reset()
    
    An application often idling in real sleep mode may make a Cortex-M target
    hard to access as CPU clock are gated and debug requests are responded
    by WAIT ack.
    
    Try to examine the target under reset as the last resort.
    
    Change-Id: Ife875a966a838c37dde987bc584ad0a1f4d020d6
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7228
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 94c75a1d4..186344167 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -1437,6 +1437,14 @@ static int cortex_m_assert_reset(struct target *target)
 		srst_asserted = true;
 	}
 
+	/* TODO: replace the hack calling target_examine_one()
+	 * as soon as a better reset framework is available */
+	if (!target_was_examined(target) && !target->defer_examine
+		&& srst_asserted && (jtag_reset_config & RESET_SRST_NO_GATING)) {
+		LOG_TARGET_DEBUG(target, "Trying to re-examine under reset");
+		target_examine_one(target);
+	}
+
 	/* We need at least debug_ap to go further.
 	 * Inform user and bail out if we don't have one. */
 	if (!armv7m->debug_ap) {
@@ -1578,7 +1586,7 @@ static int cortex_m_deassert_reset(struct target *target)
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
 
 	if ((jtag_reset_config & RESET_HAS_SRST) &&
-	    !(jtag_reset_config & RESET_SRST_NO_GATING) &&
+		!(jtag_reset_config & RESET_SRST_NO_GATING) &&
 		armv7m->debug_ap) {
 
 		int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);

-----------------------------------------------------------------------

Summary of changes:
 src/target/cortex_m.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)


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- Log -----------------------------------------------------------------
commit b991c416b7e1a070604be919d8762ffe0a930a3f
Author: Tomas Vanek <va...@fb...>
Date:   Tue Nov 23 10:06:51 2021 +0100

    target/cortex_m: make reset robust again
    
    After merging [1] 'reset halt' does not work on not responding Cortex-M.
    
    Relax the examined tests and try to set vector catch VC_CORERESET
    if debug_ap is available.
    
    While on it add an info about examination state to debug logs.
    
    Fixes: [1] commit 98d9f1168cbd ("target: reset target examined flag if target::examine() fails")
    Change-Id: Ie2e018610026180af5997d70231061a275f05c76
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/6745
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 23d9065e2..94c75a1d4 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -1408,8 +1408,9 @@ static int cortex_m_assert_reset(struct target *target)
 	struct armv7m_common *armv7m = &cortex_m->armv7m;
 	enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
 
-	LOG_TARGET_DEBUG(target, "target->state: %s",
-		target_state_name(target));
+	LOG_TARGET_DEBUG(target, "target->state: %s,%s examined",
+		target_state_name(target),
+		target_was_examined(target) ? "" : " not");
 
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
 
@@ -1428,24 +1429,32 @@ static int cortex_m_assert_reset(struct target *target)
 
 	bool srst_asserted = false;
 
-	if (!target_was_examined(target)) {
-		if (jtag_reset_config & RESET_HAS_SRST) {
-			adapter_assert_reset();
+	if ((jtag_reset_config & RESET_HAS_SRST) &&
+		((jtag_reset_config & RESET_SRST_NO_GATING) || !armv7m->debug_ap)) {
+		/* If we have no debug_ap, asserting SRST is the only thing
+		 * we can do now */
+		adapter_assert_reset();
+		srst_asserted = true;
+	}
+
+	/* We need at least debug_ap to go further.
+	 * Inform user and bail out if we don't have one. */
+	if (!armv7m->debug_ap) {
+		if (srst_asserted) {
 			if (target->reset_halt)
-				LOG_TARGET_ERROR(target, "Target not examined, will not halt after reset!");
+				LOG_TARGET_ERROR(target, "Debug AP not available, will not halt after reset!");
+
+			/* Do not propagate error: reset was asserted, proceed to deassert! */
+			target->state = TARGET_RESET;
+			register_cache_invalidate(cortex_m->armv7m.arm.core_cache);
 			return ERROR_OK;
+
 		} else {
-			LOG_TARGET_ERROR(target, "Target not examined, reset NOT asserted!");
+			LOG_TARGET_ERROR(target, "Debug AP not available, reset NOT asserted!");
 			return ERROR_FAIL;
 		}
 	}
 
-	if ((jtag_reset_config & RESET_HAS_SRST) &&
-	    (jtag_reset_config & RESET_SRST_NO_GATING)) {
-		adapter_assert_reset();
-		srst_asserted = true;
-	}
-
 	/* Enable debug requests */
 	int retval = cortex_m_read_dhcsr_atomic_sticky(target);
 
@@ -1546,7 +1555,7 @@ static int cortex_m_assert_reset(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 
-	if (target->reset_halt) {
+	if (target->reset_halt && target_was_examined(target)) {
 		retval = target_halt(target);
 		if (retval != ERROR_OK)
 			return retval;
@@ -1559,8 +1568,9 @@ static int cortex_m_deassert_reset(struct target *target)
 {
 	struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
 
-	LOG_TARGET_DEBUG(target, "target->state: %s",
-		target_state_name(target));
+	LOG_TARGET_DEBUG(target, "target->state: %s,%s examined",
+		target_state_name(target),
+		target_was_examined(target) ? "" : " not");
 
 	/* deassert reset lines */
 	adapter_deassert_reset();
@@ -1569,7 +1579,7 @@ static int cortex_m_deassert_reset(struct target *target)
 
 	if ((jtag_reset_config & RESET_HAS_SRST) &&
 	    !(jtag_reset_config & RESET_SRST_NO_GATING) &&
-		target_was_examined(target)) {
+		armv7m->debug_ap) {
 
 		int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
 		if (retval != ERROR_OK) {

-----------------------------------------------------------------------

Summary of changes:
 src/target/cortex_m.c | 44 +++++++++++++++++++++++++++-----------------
 1 file changed, 27 insertions(+), 17 deletions(-)


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commit 978c115dac5a2f420b9ef70207f384f09e380e35
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Sep 26 15:32:24 2022 +0200

    openocd: fix build with 'configure --without-capstone'
    
    When configure option --without-capstone is used, the macro
    HAVE_CAPSTONE is not defined in config.h, and the following lines
    are instead present:
            /* 1 if you have Capstone disassembly framework. */
            /* #undef HAVE_CAPSTONE */
    
    This cause compile error with message:
            arm_disassembler.h:190:5: error: "HAVE_CAPSTONE" is not
                    defined, evaluates to 0 [-Werror=undef]
              190 | #if HAVE_CAPSTONE
                  |     ^~~~~~~~~~~~~
    
    This is caused by configure.ac that does not call AC_DEFINE when
    --without-capstone option is present.
    
    Fix configure.ac to always provide the autoconf macro
    HAVE_CAPSTONE, with either value 0 or 1.
    
    Change-Id: Ie5ac98b2c25746dd721812c91baaac61ec877ecd
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7224
    Tested-by: jenkins

diff --git a/configure.ac b/configure.ac
index cfd23846b..13c990465 100644
--- a/configure.ac
+++ b/configure.ac
@@ -631,7 +631,6 @@ AS_IF([test "x$enable_capstone" != xno], [
 	PKG_CHECK_MODULES([CAPSTONE], [capstone], [
 		AC_DEFINE([HAVE_CAPSTONE], [1], [1 if you have Capstone disassembly framework.])
 	], [
-		AC_DEFINE([HAVE_CAPSTONE], [0], [0 if you don't have Capstone disassembly framework.])
 		if test "x$enable_capstone" != xauto; then
 			AC_MSG_ERROR([--with-capstone was given, but test for Capstone failed])
 		fi
@@ -639,6 +638,10 @@ AS_IF([test "x$enable_capstone" != xno], [
 	])
 ])
 
+AS_IF([test "x$enable_capstone" == xno], [
+	AC_DEFINE([HAVE_CAPSTONE], [0], [0 if you don't have Capstone disassembly framework.])
+])
+
 for hidapi_lib in hidapi hidapi-hidraw hidapi-libusb; do
 	PKG_CHECK_MODULES([HIDAPI],[$hidapi_lib],[
 		use_hidapi=yes

-----------------------------------------------------------------------

Summary of changes:
 configure.ac | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)


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commit a69b382efd35f13e0f7e63194086a2f5ac24215b
Author: Daniel Goehring <dgo...@os...>
Date:   Tue Oct 4 00:03:42 2022 -0700

    target/adiv5: 64-bit TAR setup bugfix
    
    For 64-bit TAR setup, if 'tar_valid == false' perform the upper 32-bit
    write even if the cached copy matches the upper TAR value to be written.
    
    Signed-off-by: Daniel Goehring <dgo...@os...>
    Change-Id: I320377dc90a9d1d7b64cbb281b2527e56c7621ee
    Reviewed-on: https://review.openocd.org/c/openocd/+/7245
    Reviewed-by: Tomas Vanek <va...@fb...>
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index c44642825..da5da3197 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -113,7 +113,7 @@ static int mem_ap_setup_tar(struct adiv5_ap *ap, target_addr_t tar)
 		int retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR(ap->dap), (uint32_t)(tar & 0xffffffffUL));
 		if (retval == ERROR_OK && is_64bit_ap(ap)) {
 			/* See if bits 63:32 of tar is different from last setting */
-			if ((ap->tar_value >> 32) != (tar >> 32))
+			if (!ap->tar_valid || (ap->tar_value >> 32) != (tar >> 32))
 				retval = dap_queue_ap_write(ap, MEM_AP_REG_TAR64(ap->dap), (uint32_t)(tar >> 32));
 		}
 		if (retval != ERROR_OK) {

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_adi_v5.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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commit 8bf5482754715f2e1b05be03de8780f26c305955
Author: Nishanth Menon <nm...@ti...>
Date:   Thu Jul 14 16:37:54 2022 -0500

    tcl/target/ti_k3: Handle swd vs jtag
    
    Since all the device definition when accessing device from jtag is also
    valid when accessing from swd, lets make sure the configuration can
    handle the same.
    
    Signed-off-by: Nishanth Menon <nm...@ti...>
    Change-Id: I5af071137fd8c3b52cc4ef72401f8eba952f9cad
    Reviewed-on: https://review.openocd.org/c/openocd/+/7090
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 254bb6971..2454357fc 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -12,6 +12,8 @@
 #  Has 2 ARMV8 Cores and 4 R5 Cores, M4F and an M3
 #
 
+source [find target/swj-dp.tcl]
+
 if { [info exists SOC] } {
 	set _soc $SOC
 } else {
@@ -164,7 +166,8 @@ switch $_soc {
 	}
 }
 
-jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
+
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
 
 set _TARGETNAME $_CHIPNAME.cpu

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/ti_k3.cfg | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)


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commit d6ae732f6e1646742bb179c5247ea6a96acfc47e
Author: Daniel Anselmi <dan...@gm...>
Date:   Sun Oct 2 17:15:41 2022 +0200

    fix leaky file-handle in virtex2 driver
    
    Change-Id: I2784a66c42be71f2982dff7746f9fb2eb1dc8ca6
    Signed-off-by: Daniel Anselmi <dan...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7243
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/pld/xilinx_bit.c b/src/pld/xilinx_bit.c
index 7911b8dc1..792b3375b 100644
--- a/src/pld/xilinx_bit.c
+++ b/src/pld/xilinx_bit.c
@@ -96,31 +96,37 @@ int xilinx_read_bit_file(struct xilinx_bit_file *bit_file, const char *filename)
 	read_count = fread(bit_file->unknown_header, 1, 13, input_file);
 	if (read_count != 13) {
 		LOG_ERROR("couldn't read unknown_header from file '%s'", filename);
+		fclose(input_file);
 		return ERROR_PLD_FILE_LOAD_FAILED;
 	}
 
 	if (read_section(input_file, 2, 'a', NULL, &bit_file->source_file) != ERROR_OK) {
 		xilinx_free_bit_file(bit_file);
+		fclose(input_file);
 		return ERROR_PLD_FILE_LOAD_FAILED;
 	}
 
 	if (read_section(input_file, 2, 'b', NULL, &bit_file->part_name) != ERROR_OK) {
 		xilinx_free_bit_file(bit_file);
+		fclose(input_file);
 		return ERROR_PLD_FILE_LOAD_FAILED;
 	}
 
 	if (read_section(input_file, 2, 'c', NULL, &bit_file->date) != ERROR_OK) {
 		xilinx_free_bit_file(bit_file);
+		fclose(input_file);
 		return ERROR_PLD_FILE_LOAD_FAILED;
 	}
 
 	if (read_section(input_file, 2, 'd', NULL, &bit_file->time) != ERROR_OK) {
 		xilinx_free_bit_file(bit_file);
+		fclose(input_file);
 		return ERROR_PLD_FILE_LOAD_FAILED;
 	}
 
 	if (read_section(input_file, 4, 'e', &bit_file->length, &bit_file->data) != ERROR_OK) {
 		xilinx_free_bit_file(bit_file);
+		fclose(input_file);
 		return ERROR_PLD_FILE_LOAD_FAILED;
 	}
 

commit d983114855eaf7ab6c63f0e5e6a553096e862a31
Author: Daniel Anselmi <dan...@gm...>
Date:   Sun Oct 2 02:16:28 2022 +0200

    don't return ERROR_OK in error cases
    
    Change-Id: I7e046df85838692c9044fe9c9d67e8b2c821eb0f
    Signed-off-by: Daniel Anselmi <dan...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7236
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/pld/virtex2.c b/src/pld/virtex2.c
index b4861e9cb..98fd58adb 100644
--- a/src/pld/virtex2.c
+++ b/src/pld/virtex2.c
@@ -175,7 +175,7 @@ COMMAND_HANDLER(virtex2_handle_read_stat_command)
 	device = get_pld_device_by_num(dev_id);
 	if (!device) {
 		command_print(CMD, "pld device '#%s' is out of bounds", CMD_ARGV[0]);
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	virtex2_read_stat(device, &status);
@@ -197,7 +197,7 @@ PLD_DEVICE_COMMAND_HANDLER(virtex2_pld_device_command)
 	tap = jtag_tap_by_string(CMD_ARGV[1]);
 	if (!tap) {
 		command_print(CMD, "Tap: %s does not exist", CMD_ARGV[1]);
-		return ERROR_OK;
+		return ERROR_FAIL;
 	}
 
 	virtex2_info = malloc(sizeof(struct virtex2_pld_device));

-----------------------------------------------------------------------

Summary of changes:
 src/pld/virtex2.c    | 4 ++--
 src/pld/xilinx_bit.c | 6 ++++++
 2 files changed, 8 insertions(+), 2 deletions(-)


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- Log -----------------------------------------------------------------
commit 0a7e17242037431671d52c7e92f72f216c6a4c57
Author: Daniel Anselmi <dan...@gm...>
Date:   Sun Oct 2 01:17:15 2022 +0200

    fix memory leak in virtex2 driver
    
    Change-Id: Ia08f7aaad25631132885acd5898477c1106f0ec4
    Signed-off-by: Daniel Anselmi <dan...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7235
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/pld/virtex2.c b/src/pld/virtex2.c
index 771af9939..b4861e9cb 100644
--- a/src/pld/virtex2.c
+++ b/src/pld/virtex2.c
@@ -157,6 +157,8 @@ static int virtex2_load(struct pld_device *pld_device, const char *filename)
 	virtex2_set_instr(virtex2_info->tap, 0x3f);		/* BYPASS */
 	jtag_execute_queue();
 
+	xilinx_free_bit_file(&bit_file);
+
 	return ERROR_OK;
 }
 
diff --git a/src/pld/xilinx_bit.c b/src/pld/xilinx_bit.c
index 25deb8082..7911b8dc1 100644
--- a/src/pld/xilinx_bit.c
+++ b/src/pld/xilinx_bit.c
@@ -87,26 +87,42 @@ int xilinx_read_bit_file(struct xilinx_bit_file *bit_file, const char *filename)
 		return ERROR_PLD_FILE_LOAD_FAILED;
 	}
 
+	bit_file->source_file = NULL;
+	bit_file->part_name = NULL;
+	bit_file->date = NULL;
+	bit_file->time = NULL;
+	bit_file->data = NULL;
+
 	read_count = fread(bit_file->unknown_header, 1, 13, input_file);
 	if (read_count != 13) {
 		LOG_ERROR("couldn't read unknown_header from file '%s'", filename);
 		return ERROR_PLD_FILE_LOAD_FAILED;
 	}
 
-	if (read_section(input_file, 2, 'a', NULL, &bit_file->source_file) != ERROR_OK)
+	if (read_section(input_file, 2, 'a', NULL, &bit_file->source_file) != ERROR_OK) {
+		xilinx_free_bit_file(bit_file);
 		return ERROR_PLD_FILE_LOAD_FAILED;
+	}
 
-	if (read_section(input_file, 2, 'b', NULL, &bit_file->part_name) != ERROR_OK)
+	if (read_section(input_file, 2, 'b', NULL, &bit_file->part_name) != ERROR_OK) {
+		xilinx_free_bit_file(bit_file);
 		return ERROR_PLD_FILE_LOAD_FAILED;
+	}
 
-	if (read_section(input_file, 2, 'c', NULL, &bit_file->date) != ERROR_OK)
+	if (read_section(input_file, 2, 'c', NULL, &bit_file->date) != ERROR_OK) {
+		xilinx_free_bit_file(bit_file);
 		return ERROR_PLD_FILE_LOAD_FAILED;
+	}
 
-	if (read_section(input_file, 2, 'd', NULL, &bit_file->time) != ERROR_OK)
+	if (read_section(input_file, 2, 'd', NULL, &bit_file->time) != ERROR_OK) {
+		xilinx_free_bit_file(bit_file);
 		return ERROR_PLD_FILE_LOAD_FAILED;
+	}
 
-	if (read_section(input_file, 4, 'e', &bit_file->length, &bit_file->data) != ERROR_OK)
+	if (read_section(input_file, 4, 'e', &bit_file->length, &bit_file->data) != ERROR_OK) {
+		xilinx_free_bit_file(bit_file);
 		return ERROR_PLD_FILE_LOAD_FAILED;
+	}
 
 	LOG_DEBUG("bit_file: %s %s %s,%s %" PRIu32 "", bit_file->source_file, bit_file->part_name,
 		bit_file->date, bit_file->time, bit_file->length);
@@ -115,3 +131,12 @@ int xilinx_read_bit_file(struct xilinx_bit_file *bit_file, const char *filename)
 
 	return ERROR_OK;
 }
+
+void xilinx_free_bit_file(struct xilinx_bit_file *bit_file)
+{
+	free(bit_file->source_file);
+	free(bit_file->part_name);
+	free(bit_file->date);
+	free(bit_file->time);
+	free(bit_file->data);
+}
diff --git a/src/pld/xilinx_bit.h b/src/pld/xilinx_bit.h
index e30ed2337..f443bf70e 100644
--- a/src/pld/xilinx_bit.h
+++ b/src/pld/xilinx_bit.h
@@ -22,4 +22,6 @@ struct xilinx_bit_file {
 
 int xilinx_read_bit_file(struct xilinx_bit_file *bit_file, const char *filename);
 
+void xilinx_free_bit_file(struct xilinx_bit_file *bit_file);
+
 #endif /* OPENOCD_PLD_XILINX_BIT_H */

-----------------------------------------------------------------------

Summary of changes:
 src/pld/virtex2.c    |  2 ++
 src/pld/xilinx_bit.c | 35 ++++++++++++++++++++++++++++++-----
 src/pld/xilinx_bit.h |  2 ++
 3 files changed, 34 insertions(+), 5 deletions(-)


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- Log -----------------------------------------------------------------
commit cff2cf373f1b86233eb2abab8e590fb0f88c7449
Author: Erhan Kurubas <erh...@es...>
Date:   Wed Sep 28 21:18:49 2022 +0200

    target/xtensa: pass correct buffer on read memory retry
    
    Read values must be at albuff so that can be copied to buffer
    on function exit.
    
    Signed-off-by: Erhan Kurubas <erh...@es...>
    Change-Id: I74a533e8f12f1002ca06a98a7c7cd928552b4cc5
    Reviewed-on: https://review.openocd.org/c/openocd/+/7226
    Tested-by: jenkins
    Reviewed-by: Ian Thompson <ia...@ca...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index c73b80820..faff0afa8 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -1781,9 +1781,9 @@ int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t si
 	if (res != ERROR_OK) {
 		if (xtensa->probe_lsddr32p != 0) {
 			/* Disable fast memory access instructions and retry before reporting an error */
-			LOG_TARGET_INFO(target, "Disabling LDDR32.P/SDDR32.P");
+			LOG_TARGET_DEBUG(target, "Disabling LDDR32.P/SDDR32.P");
 			xtensa->probe_lsddr32p = 0;
-			res = xtensa_read_memory(target, address, size, count, buffer);
+			res = xtensa_read_memory(target, address, size, count, albuff);
 			bswap = false;
 		} else {
 			LOG_TARGET_WARNING(target, "Failed reading %d bytes at address "TARGET_ADDR_FMT,

-----------------------------------------------------------------------

Summary of changes:
 src/target/xtensa/xtensa.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


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commit 10b08d5ac5086aed3259f4f48a67d8d807c8ef11
Author: Erhan Kurubas <erh...@es...>
Date:   Wed Sep 28 21:38:05 2022 +0200

    target/xtensa: rename pc and ps macro names
    
    Actually they are the base of epc and eps
    
    Signed-off-by: Erhan Kurubas <erh...@es...>
    Change-Id: I4f43b9609a9929399fb5d3fa0203efc8a98e94c9
    Reviewed-on: https://review.openocd.org/c/openocd/+/7227
    Tested-by: jenkins
    Reviewed-by: Ian Thompson <ia...@ca...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index 4dfff6ab4..c73b80820 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -168,8 +168,9 @@
 #define XT_REG_A3         (xtensa_regs[XT_REG_IDX_AR3].reg_num)
 #define XT_REG_A4         (xtensa_regs[XT_REG_IDX_AR4].reg_num)
 
-#define XT_PS_REG_NUM_BASE          (0xc0U)	/* (EPS2 - 2), for adding DBGLEVEL */
-#define XT_PC_REG_NUM_BASE          (0xb0U)	/* (EPC1 - 1), for adding DBGLEVEL */
+#define XT_PS_REG_NUM               (0xe6U)
+#define XT_EPS_REG_NUM_BASE         (0xc0U)	/* (EPS2 - 2), for adding DBGLEVEL */
+#define XT_EPC_REG_NUM_BASE         (0xb0U)	/* (EPC1 - 1), for adding DBGLEVEL */
 #define XT_PC_REG_NUM_VIRTUAL       (0xffU)	/* Marker for computing PC (EPC[DBGLEVEL) */
 #define XT_PC_DBREG_NUM_BASE        (0x20U)	/* External (i.e., GDB) access */
 
@@ -245,7 +246,7 @@ struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS] = {
 	XT_MK_REG_DESC("ar63", 0x3F, XT_REG_GENERAL, 0),
 	XT_MK_REG_DESC("windowbase", 0x48, XT_REG_SPECIAL, 0),
 	XT_MK_REG_DESC("windowstart", 0x49, XT_REG_SPECIAL, 0),
-	XT_MK_REG_DESC("ps", 0xE6, XT_REG_SPECIAL, 0),	/* PS (not mapped through EPS[]) */
+	XT_MK_REG_DESC("ps", XT_PS_REG_NUM, XT_REG_SPECIAL, 0),	/* PS (not mapped through EPS[]) */
 	XT_MK_REG_DESC("ibreakenable", 0x60, XT_REG_SPECIAL, 0),
 	XT_MK_REG_DESC("ddr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD),
 	XT_MK_REG_DESC("ibreaka0", 0x80, XT_REG_SPECIAL, 0),
@@ -630,7 +631,7 @@ static int xtensa_write_dirty_registers(struct target *target)
 							/* reg number of PC for debug interrupt depends on NDEBUGLEVEL
 							 **/
 							reg_num =
-								(XT_PC_REG_NUM_BASE +
+								(XT_EPC_REG_NUM_BASE +
 								xtensa->core_config->debug.irq_level);
 						xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, reg_num, XT_REG_A3));
 					}
@@ -1105,10 +1106,10 @@ int xtensa_fetch_all_regs(struct target *target)
 			case XT_REG_SPECIAL:
 				if (reg_num == XT_PC_REG_NUM_VIRTUAL) {
 					/* reg number of PC for debug interrupt depends on NDEBUGLEVEL */
-					reg_num = (XT_PC_REG_NUM_BASE + xtensa->core_config->debug.irq_level);
+					reg_num = XT_EPC_REG_NUM_BASE + xtensa->core_config->debug.irq_level;
 				} else if (reg_num == xtensa_regs[XT_REG_IDX_PS].reg_num) {
 					/* reg number of PS for debug interrupt depends on NDEBUGLEVEL */
-					reg_num = (XT_PS_REG_NUM_BASE + xtensa->core_config->debug.irq_level);
+					reg_num = XT_EPS_REG_NUM_BASE + xtensa->core_config->debug.irq_level;
 				} else if (reg_num == xtensa_regs[XT_REG_IDX_CPENABLE].reg_num) {
 					/* CPENABLE already read/updated; don't re-read */
 					reg_fetched = false;
@@ -3441,8 +3442,8 @@ COMMAND_HELPER(xtensa_cmd_xtreg_do, struct xtensa *xtensa)
 		else
 			rptr->flags = 0;
 
-		if ((rptr->reg_num == (XT_PS_REG_NUM_BASE + xtensa->core_config->debug.irq_level)) &&
-			(xtensa->core_config->core_type == XT_LX) && (rptr->type == XT_REG_SPECIAL)) {
+		if (rptr->reg_num == (XT_EPS_REG_NUM_BASE + xtensa->core_config->debug.irq_level) &&
+			xtensa->core_config->core_type == XT_LX && rptr->type == XT_REG_SPECIAL) {
 			xtensa->eps_dbglevel_idx = XT_NUM_REGS + xtensa->num_optregs - 1;
 			LOG_DEBUG("Setting PS (%s) index to %d", rptr->name, xtensa->eps_dbglevel_idx);
 		}

-----------------------------------------------------------------------

Summary of changes:
 src/target/xtensa/xtensa.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)


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commit af75d70dc5e6d83c57c6e8ee1a23ef9b472d2d52
Author: Keith Packard <ke...@ke...>
Date:   Wed Sep 28 14:02:52 2022 -0700

    flash/nor/at91samd: Use 32-bit register writes for ST-Link compat
    
    ST-Link v2 dongles can be used with many cortex-m parts, but they have
    one limitation -- they can only perform 8-bit and 32-bit writes to the
    target. 16-bit writes are done using a pair of 8-bit writes. While not
    usually an issue, in the case of the at91samd flash driver, the 16-bit
    'command' register must have both halves written in the same
    operation.
    
    Fortunately, this register has two pad bytes above it in the address
    space, making it safe to always access with 32-bit operations.
    
    Change-Id: I44b0db9406982a8db5818c0533d3101618741db2
    Signed-off-by: Keith Packard <ke...@ke...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7234
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/flash/nor/at91samd.c b/src/flash/nor/at91samd.c
index a0252a276..f213444d1 100644
--- a/src/flash/nor/at91samd.c
+++ b/src/flash/nor/at91samd.c
@@ -543,7 +543,8 @@ static int samd_issue_nvmctrl_command(struct target *target, uint16_t cmd)
 	}
 
 	/* Issue the NVM command */
-	res = target_write_u16(target,
+	/* 32-bit write is used to ensure atomic operation on ST-Link */
+	res = target_write_u32(target,
 			SAMD_NVMCTRL + SAMD_NVMCTRL_CTRLA, SAMD_NVM_CMD(cmd));
 	if (res != ERROR_OK)
 		return res;

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/at91samd.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)


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commit 0cedf10f8fd618b78190ce32a40f26dec0fb8253
Author: Evgeniy Naydanov <evg...@sy...>
Date:   Wed Sep 14 17:56:20 2022 +0300

    Remove duplicate of a counter in hwthread_update_threads
    
    There is no need to count number of examined threads twice.
    
    Signed-off-by: Evgeniy Naydanov <evg...@sy...>
    Change-Id: Id32ead853d1ddcd4e67062d6f795700feb20cb4b
    Reviewed-on: https://review.openocd.org/c/openocd/+/7223
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/rtos/hwthread.c b/src/rtos/hwthread.c
index e5eaf425f..bdd5835c2 100644
--- a/src/rtos/hwthread.c
+++ b/src/rtos/hwthread.c
@@ -78,7 +78,6 @@ static int hwthread_fill_thread(struct rtos *rtos, struct target *curr, int thre
 static int hwthread_update_threads(struct rtos *rtos)
 {
 	int threads_found = 0;
-	int thread_list_size = 0;
 	struct target_list *head;
 	struct target *target;
 	int64_t current_thread = 0;
@@ -100,13 +99,13 @@ static int hwthread_update_threads(struct rtos *rtos)
 			if (!target_was_examined(curr))
 				continue;
 
-			++thread_list_size;
+			++threads_found;
 		}
 	} else
-		thread_list_size = 1;
+		threads_found = 1;
 
 	/* create space for new thread details */
-	rtos->thread_details = malloc(sizeof(struct thread_detail) * thread_list_size);
+	rtos->thread_details = malloc(sizeof(struct thread_detail) * threads_found);
 
 	if (target->smp) {
 		/* loop over all threads */
@@ -171,13 +170,10 @@ static int hwthread_update_threads(struct rtos *rtos)
 			default:
 				break;
 			}
-
-			threads_found++;
 		}
 	} else {
 		hwthread_fill_thread(rtos, target, threads_found);
 		current_thread = threadid_from_target(target);
-		threads_found++;
 	}
 
 	rtos->thread_count = threads_found;

-----------------------------------------------------------------------

Summary of changes:
 src/rtos/hwthread.c | 10 +++-------
 1 file changed, 3 insertions(+), 7 deletions(-)


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- Log -----------------------------------------------------------------
commit 759d581fdeec3063475349b2c4ac75140032c0e1
Author: Tomas Vanek <va...@fb...>
Date:   Wed Sep 21 14:46:27 2022 +0200

    jtag/drivers/bitbang: reduce debug verbosity
    
    The bitbang driver floods the log by many messages with very
    little informational value.
    
    Remove some LOG_DEBUGs, convert some others to LOG_DEBUG_IO.
    
    Change-Id: I0c7539467b45543e12932c67dc71e86d58c8c6cd
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7220
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Jonathan Bell <jon...@ra...>
    Tested-by: jenkins

diff --git a/src/jtag/drivers/bitbang.c b/src/jtag/drivers/bitbang.c
index d49e16fa0..2ab0a2a76 100644
--- a/src/jtag/drivers/bitbang.c
+++ b/src/jtag/drivers/bitbang.c
@@ -380,8 +380,6 @@ static int bitbang_swd_init(void)
 
 static void bitbang_swd_exchange(bool rnw, uint8_t buf[], unsigned int offset, unsigned int bit_cnt)
 {
-	LOG_DEBUG("bitbang_swd_exchange");
-
 	if (bitbang_interface->blink) {
 		/* FIXME: we should manage errors */
 		bitbang_interface->blink(1);
@@ -412,11 +410,9 @@ static void bitbang_swd_exchange(bool rnw, uint8_t buf[], unsigned int offset, u
 
 static int bitbang_swd_switch_seq(enum swd_special_seq seq)
 {
-	LOG_DEBUG("bitbang_swd_switch_seq");
-
 	switch (seq) {
 	case LINE_RESET:
-		LOG_DEBUG("SWD line reset");
+		LOG_DEBUG_IO("SWD line reset");
 		bitbang_swd_exchange(false, (uint8_t *)swd_seq_line_reset, 0, swd_seq_line_reset_len);
 		break;
 	case JTAG_TO_SWD:
@@ -459,7 +455,6 @@ static void swd_clear_sticky_errors(void)
 
 static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay_clk)
 {
-	LOG_DEBUG("bitbang_swd_read_reg");
 	assert(cmd & SWD_CMD_RNW);
 
 	if (queued_retval != ERROR_OK) {
@@ -481,7 +476,7 @@ static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay
 		uint32_t data = buf_get_u32(trn_ack_data_parity_trn, 1 + 3, 32);
 		int parity = buf_get_u32(trn_ack_data_parity_trn, 1 + 3 + 32, 1);
 
-		LOG_DEBUG("%s %s read reg %X = %08"PRIx32,
+		LOG_DEBUG_IO("%s %s read reg %X = %08" PRIx32,
 			  ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
 			  cmd & SWD_CMD_APNDP ? "AP" : "DP",
 			  (cmd & SWD_CMD_A32) >> 1,
@@ -510,7 +505,6 @@ static void bitbang_swd_read_reg(uint8_t cmd, uint32_t *value, uint32_t ap_delay
 
 static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay_clk)
 {
-	LOG_DEBUG("bitbang_swd_write_reg");
 	assert(!(cmd & SWD_CMD_RNW));
 
 	if (queued_retval != ERROR_OK) {
@@ -537,7 +531,7 @@ static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay
 
 		int ack = buf_get_u32(trn_ack_data_parity_trn, 1, 3);
 
-		LOG_DEBUG("%s%s %s write reg %X = %08"PRIx32,
+		LOG_DEBUG_IO("%s%s %s write reg %X = %08" PRIx32,
 			  check_ack ? "" : "ack ignored ",
 			  ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ? "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
 			  cmd & SWD_CMD_APNDP ? "AP" : "DP",
@@ -562,14 +556,13 @@ static void bitbang_swd_write_reg(uint8_t cmd, uint32_t value, uint32_t ap_delay
 
 static int bitbang_swd_run_queue(void)
 {
-	LOG_DEBUG("bitbang_swd_run_queue");
 	/* A transaction must be followed by another transaction or at least 8 idle cycles to
 	 * ensure that data is clocked through the AP. */
 	bitbang_swd_exchange(true, NULL, 0, 8);
 
 	int retval = queued_retval;
 	queued_retval = ERROR_OK;
-	LOG_DEBUG("SWD queue return value: %02x", retval);
+	LOG_DEBUG_IO("SWD queue return value: %02x", retval);
 	return retval;
 }
 

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/bitbang.c | 15 ++++-----------
 1 file changed, 4 insertions(+), 11 deletions(-)


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