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From: OpenOCD-Gerrit <ope...@us...> - 2022-11-28 22:23:47
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via e345cefabdda4e14c64b2206105e99b2fa0b9b6b (commit)
from 9d925776b4504f71306b16467c1b731e57b6e7d0 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit e345cefabdda4e14c64b2206105e99b2fa0b9b6b
Author: Nick Kraus <ni...@nc...>
Date: Mon Nov 21 09:55:11 2022 -0500
jtag/drivers/cmsis_dap.c: Fix Length of SWO Baudrate Command
The command should now send the full 5 byte command length, which
includes the command tag (0x19) and the 4-byte baudrate word, instead
of only the last 3 bytes of the baudrate.
Signed-off-by: Nick Kraus <ni...@nc...>
Change-Id: Idd6e084efd7492489aa900cdbf08f540944041cb
Reviewed-on: https://review.openocd.org/c/openocd/+/7370
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/cmsis_dap.c b/src/jtag/drivers/cmsis_dap.c
index 2f5f9c907..44a7dd8cb 100644
--- a/src/jtag/drivers/cmsis_dap.c
+++ b/src/jtag/drivers/cmsis_dap.c
@@ -660,7 +660,7 @@ static int cmsis_dap_cmd_dap_swo_baudrate(
command[0] = CMD_DAP_SWO_BAUDRATE;
h_u32_to_le(&command[1], in_baudrate);
- int retval = cmsis_dap_xfer(cmsis_dap_handle, 4);
+ int retval = cmsis_dap_xfer(cmsis_dap_handle, 5);
uint32_t rvbr = le_to_h_u32(&cmsis_dap_handle->response[1]);
if (retval != ERROR_OK || rvbr == 0) {
LOG_ERROR("CMSIS-DAP: command CMD_SWO_Baudrate(%u) -> %u failed.", in_baudrate, rvbr);
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/cmsis_dap.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
hooks/post-receive
--
Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2022-11-15 21:39:44
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 9d925776b4504f71306b16467c1b731e57b6e7d0 (commit)
from 2e9f04c11a5aeb9c7aa9d387f9f4d0e7c65a1f5b (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 9d925776b4504f71306b16467c1b731e57b6e7d0
Author: Tomas Vanek <va...@fb...>
Date: Sun Oct 16 11:34:57 2022 +0200
target/armv7m: fix feature name of ARMv8M security extension regs
gdb requires this feature to enable stack unwinding of secure/nonsecure
interstate calls and exceptions on an ARMv8M target with
the security extension.
Tested on STM32L5 (Cortex-M33).
Change-Id: Ib09780c011afbc095b352074068597559ad14fcd
Link: https://sourceware.org/git/?p=binutils-gdb.git;a=commit;h=ae7e2f45aa4798be449f282bbf75ad41e73f055e
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7265
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index d28702dd7..93df5877e 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -116,27 +116,27 @@ static const struct {
{ ARMV7M_FAULTMASK, "faultmask", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
{ ARMV7M_CONTROL, "control", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
- /* ARMv8-M specific registers */
- { ARMV8M_MSP_NS, "msp_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
- { ARMV8M_PSP_NS, "psp_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
- { ARMV8M_MSP_S, "msp_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
- { ARMV8M_PSP_S, "psp_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
- { ARMV8M_MSPLIM_S, "msplim_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
- { ARMV8M_PSPLIM_S, "psplim_s", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
- { ARMV8M_MSPLIM_NS, "msplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
- { ARMV8M_PSPLIM_NS, "psplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "v8-m.sp" },
+ /* ARMv8-M security extension (TrustZone) specific registers */
+ { ARMV8M_MSP_NS, "msp_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+ { ARMV8M_PSP_NS, "psp_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+ { ARMV8M_MSP_S, "msp_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+ { ARMV8M_PSP_S, "psp_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+ { ARMV8M_MSPLIM_S, "msplim_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+ { ARMV8M_PSPLIM_S, "psplim_s", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+ { ARMV8M_MSPLIM_NS, "msplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
+ { ARMV8M_PSPLIM_NS, "psplim_ns", 32, REG_TYPE_DATA_PTR, "stack", "org.gnu.gdb.arm.secext" },
{ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_S, "pmsk_bpri_fltmsk_ctrl_s", 32, REG_TYPE_INT, NULL, NULL },
- { ARMV8M_PRIMASK_S, "primask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
- { ARMV8M_BASEPRI_S, "basepri_s", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
- { ARMV8M_FAULTMASK_S, "faultmask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
- { ARMV8M_CONTROL_S, "control_s", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
+ { ARMV8M_PRIMASK_S, "primask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+ { ARMV8M_BASEPRI_S, "basepri_s", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+ { ARMV8M_FAULTMASK_S, "faultmask_s", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+ { ARMV8M_CONTROL_S, "control_s", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
{ ARMV8M_PMSK_BPRI_FLTMSK_CTRL_NS, "pmsk_bpri_fltmsk_ctrl_ns", 32, REG_TYPE_INT, NULL, NULL },
- { ARMV8M_PRIMASK_NS, "primask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
- { ARMV8M_BASEPRI_NS, "basepri_ns", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
- { ARMV8M_FAULTMASK_NS, "faultmask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
- { ARMV8M_CONTROL_NS, "control_ns", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.m-system" },
+ { ARMV8M_PRIMASK_NS, "primask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+ { ARMV8M_BASEPRI_NS, "basepri_ns", 8, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+ { ARMV8M_FAULTMASK_NS, "faultmask_ns", 1, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
+ { ARMV8M_CONTROL_NS, "control_ns", 3, REG_TYPE_INT8, "system", "org.gnu.gdb.arm.secext" },
/* FPU registers */
{ ARMV7M_D0, "d0", 64, REG_TYPE_IEEE_DOUBLE, "float", "org.gnu.gdb.arm.vfp" },
-----------------------------------------------------------------------
Summary of changes:
src/target/armv7m.c | 34 +++++++++++++++++-----------------
1 file changed, 17 insertions(+), 17 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-11-15 21:35:38
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 2e9f04c11a5aeb9c7aa9d387f9f4d0e7c65a1f5b (commit)
from 2bad55bf83bcd4a24711a88b06971f3f828947bd (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 2e9f04c11a5aeb9c7aa9d387f9f4d0e7c65a1f5b
Author: Giulio Fieramosca <gi...@gl...>
Date: Thu Nov 3 20:38:20 2022 +0100
rtos/ThreadX: added check for NULL-named tasks
Thread name loading was not correctly handled if a ThreadX task has a NULL
name.
Signed-off-by: Giulio Fieramosca <gi...@gl...>
Change-Id: I03071930182bc2585b61ce5d8c67491710883dd6
Reviewed-on: https://review.openocd.org/c/openocd/+/7328
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/rtos/ThreadX.c b/src/rtos/ThreadX.c
index 5f90eb644..5bdd007d4 100644
--- a/src/rtos/ThreadX.c
+++ b/src/rtos/ThreadX.c
@@ -370,16 +370,21 @@ static int threadx_update_threads(struct rtos *rtos)
}
/* Read the thread name */
- retval =
- target_read_buffer(rtos->target,
- name_ptr,
- THREADX_THREAD_NAME_STR_SIZE,
- (uint8_t *)&tmp_str);
- if (retval != ERROR_OK) {
- LOG_ERROR("Error reading thread name from ThreadX target");
- return retval;
+ tmp_str[0] = '\x00';
+
+ /* Check if thread has a valid name */
+ if (name_ptr != 0) {
+ retval =
+ target_read_buffer(rtos->target,
+ name_ptr,
+ THREADX_THREAD_NAME_STR_SIZE,
+ (uint8_t *)&tmp_str);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Error reading thread name from ThreadX target");
+ return retval;
+ }
+ tmp_str[THREADX_THREAD_NAME_STR_SIZE - 1] = '\x00';
}
- tmp_str[THREADX_THREAD_NAME_STR_SIZE-1] = '\x00';
if (tmp_str[0] == '\x00')
strcpy(tmp_str, "No Name");
-----------------------------------------------------------------------
Summary of changes:
src/rtos/ThreadX.c | 23 ++++++++++++++---------
1 file changed, 14 insertions(+), 9 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2022-11-15 21:35:05
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 2bad55bf83bcd4a24711a88b06971f3f828947bd (commit)
from 1762aa04ce9a7883e85631c371d6e1f94d16e31a (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 2bad55bf83bcd4a24711a88b06971f3f828947bd
Author: Andreas Bolsch <hyp...@gm...>
Date: Sat Nov 12 16:29:18 2022 +0100
Fix for segfault and some clang reported problems in stmqspi
Change-Id: Id003adb574085cdd603cc13aeb6f2efec73593f1
Signed-off-by: Andreas Bolsch <hyp...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7345
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/stmqspi.c b/src/flash/nor/stmqspi.c
index e5df3b9e0..77ea4c40d 100644
--- a/src/flash/nor/stmqspi.c
+++ b/src/flash/nor/stmqspi.c
@@ -616,8 +616,6 @@ COMMAND_HANDLER(stmqspi_handle_set)
LOG_DEBUG("%s", __func__);
- dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
-
/* chip_erase_cmd, sectorsize and erase_cmd are optional */
if ((CMD_ARGC < 7) || (CMD_ARGC > 10))
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -628,8 +626,9 @@ COMMAND_HANDLER(stmqspi_handle_set)
target = bank->target;
stmqspi_info = bank->driver_priv;
+ dual = (stmqspi_info->saved_cr & BIT(SPI_DUAL_FLASH)) ? 1 : 0;
- /* invalidate all old info */
+ /* invalidate all flash device info */
if (stmqspi_info->probed)
free(bank->sectors);
bank->size = 0;
@@ -721,10 +720,8 @@ COMMAND_HANDLER(stmqspi_handle_set)
uint32_t dcr;
retval = target_read_u32(target, io_base + SPI_DCR, &dcr);
-
if (retval != ERROR_OK)
return retval;
-
fsize = (dcr >> SPI_FSIZE_POS) & (BIT(SPI_FSIZE_LEN) - 1);
LOG_DEBUG("FSIZE = 0x%04x", fsize);
@@ -2080,16 +2077,17 @@ static int stmqspi_probe(struct flash_bank *bank)
bool octal_dtr;
int retval;
- if (stmqspi_info->probed) {
- bank->size = 0;
- bank->num_sectors = 0;
+ /* invalidate all flash device info */
+ if (stmqspi_info->probed)
free(bank->sectors);
- bank->sectors = NULL;
- memset(&stmqspi_info->dev, 0, sizeof(stmqspi_info->dev));
- stmqspi_info->sfdp_dummy1 = 0;
- stmqspi_info->sfdp_dummy2 = 0;
- stmqspi_info->probed = false;
- }
+ bank->size = 0;
+ bank->num_sectors = 0;
+ bank->sectors = NULL;
+ stmqspi_info->sfdp_dummy1 = 0;
+ stmqspi_info->sfdp_dummy2 = 0;
+ stmqspi_info->probed = false;
+ memset(&stmqspi_info->dev, 0, sizeof(stmqspi_info->dev));
+ stmqspi_info->dev.name = "unknown";
/* Abort any previous operation */
retval = stmqspi_abort(bank);
@@ -2104,8 +2102,8 @@ static int stmqspi_probe(struct flash_bank *bank)
/* check whether QSPI_ABR is writeable and readback returns the value written */
retval = target_write_u32(target, io_base + QSPI_ABR, magic);
if (retval == ERROR_OK) {
- retval = target_read_u32(target, io_base + QSPI_ABR, &data);
- retval = target_write_u32(target, io_base + QSPI_ABR, 0);
+ (void)target_read_u32(target, io_base + QSPI_ABR, &data);
+ (void)target_write_u32(target, io_base + QSPI_ABR, 0);
}
if (data == magic) {
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stmqspi.c | 30 ++++++++++++++----------------
1 file changed, 14 insertions(+), 16 deletions(-)
hooks/post-receive
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Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2022-11-15 21:34:50
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 1762aa04ce9a7883e85631c371d6e1f94d16e31a (commit)
from 0d055602c3fcf81e42a3928328e763f80a73097b (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 1762aa04ce9a7883e85631c371d6e1f94d16e31a
Author: Antonio Borneo <bor...@gm...>
Date: Tue Nov 8 11:25:27 2022 +0100
jep106: update to revision JEP106BF.01 Oct 2022
Change-Id: Ia1f19dcce48da997c036ccffa65e76e179de2eb9
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7341
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/helper/jep106.inc b/src/helper/jep106.inc
index 01c3aac07..cb67b926a 100644
--- a/src/helper/jep106.inc
+++ b/src/helper/jep106.inc
@@ -8,7 +8,7 @@
* identification code list, please visit the JEDEC website at www.jedec.org .
*/
-/* This file is aligned to revision JEP106BE January 2022. */
+/* This file is aligned to revision JEP106BF.01 October 2022. */
[0][0x01 - 1] = "AMD",
[0][0x02 - 1] = "AMI",
@@ -149,7 +149,7 @@
[1][0x0b - 1] = "Bestlink Systems",
[1][0x0c - 1] = "Graychip",
[1][0x0d - 1] = "GENNUM",
-[1][0x0e - 1] = "VideoLogic",
+[1][0x0e - 1] = "Imagination Technologies Limited",
[1][0x0f - 1] = "Robert Bosch",
[1][0x10 - 1] = "Chip Express",
[1][0x11 - 1] = "DATARAM",
@@ -1501,7 +1501,7 @@
[11][0x67 - 1] = "Guangzhou Shuvrwine Technology Co",
[11][0x68 - 1] = "Shenzhen Hangshun Chip Technology",
[11][0x69 - 1] = "Chengboliwei Electronic Business",
-[11][0x6a - 1] = "Kowin Memory Technology Co Ltd",
+[11][0x6a - 1] = "Kowin Technology HK Limited",
[11][0x6b - 1] = "Euronet Technology Inc",
[11][0x6c - 1] = "SCY",
[11][0x6d - 1] = "Shenzhen Xinhongyusheng Electrical",
@@ -1705,4 +1705,85 @@
[13][0x37 - 1] = "ORICO Technologies Co. Ltd.",
[13][0x38 - 1] = "Space Exploration Technologies Corp",
[13][0x39 - 1] = "AONDEVICES Inc",
+[13][0x3a - 1] = "Shenzhen Netforward Micro Electronic",
+[13][0x3b - 1] = "Syntacore Ltd",
+[13][0x3c - 1] = "Shenzhen Secmem Microelectronics Co",
+[13][0x3d - 1] = "ONiO As",
+[13][0x3e - 1] = "Shenzhen Peladn Technology Co Ltd",
+[13][0x3f - 1] = "O-Cubes Shanghai Microelectronics",
+[13][0x40 - 1] = "ASTC",
+[13][0x41 - 1] = "UMIS",
+[13][0x42 - 1] = "Paradromics",
+[13][0x43 - 1] = "Sinh Micro Co Ltd",
+[13][0x44 - 1] = "Metorage Semiconductor Technology Co",
+[13][0x45 - 1] = "Aeva Inc",
+[13][0x46 - 1] = "HongKong Hyunion Electronics Co Ltd",
+[13][0x47 - 1] = "China Flash Co Ltd",
+[13][0x48 - 1] = "Sunplus Technology Co Ltd",
+[13][0x49 - 1] = "Idaho Scientific",
+[13][0x4a - 1] = "Suzhou SF Micro Electronics Co Ltd",
+[13][0x4b - 1] = "IMEX Cap AG",
+[13][0x4c - 1] = "Fitipower Integrated Technology Co Ltd",
+[13][0x4d - 1] = "ShenzhenWooacme Technology Co Ltd",
+[13][0x4e - 1] = "KeepData Original Chips",
+[13][0x4f - 1] = "Rivos Inc",
+[13][0x50 - 1] = "Big Innovation Company Limited",
+[13][0x51 - 1] = "Wuhan YuXin Semiconductor Co Ltd",
+[13][0x52 - 1] = "United Memory Technology (Jiangsu)",
+[13][0x53 - 1] = "PQShield Ltd",
+[13][0x54 - 1] = "ArchiTek Corporation",
+[13][0x55 - 1] = "ShenZhen AZW Technology Co Ltd",
+[13][0x56 - 1] = "Hengchi Zhixin (Dongguan) Technology",
+[13][0x57 - 1] = "Eggtronic Engineering Spa",
+[13][0x58 - 1] = "Fusontai Technology",
+[13][0x59 - 1] = "PULP Platform",
+[13][0x5a - 1] = "Koitek Electronic Technology (Shenzhen) Co",
+[13][0x5b - 1] = "Shenzhen Jiteng Network Technology Co",
+[13][0x5c - 1] = "Aviva Links Inc",
+[13][0x5d - 1] = "Trilinear Technologies Inc",
+[13][0x5e - 1] = "Shenzhen Developer Microelectronics Co",
+[13][0x5f - 1] = "Guangdong OPPO Mobile Telecommunication",
+[13][0x60 - 1] = "Akeana",
+[13][0x61 - 1] = "Lyczar",
+[13][0x62 - 1] = "Shenzhen Qiji Technology Co Ltd",
+[13][0x63 - 1] = "Shenzhen Shangzhaoyuan Technology",
+[13][0x64 - 1] = "Han Stor",
+[13][0x65 - 1] = "China Micro Semicon Co., Ltd.",
+[13][0x66 - 1] = "Shenzhen Zhuqin Technology Co Ltd",
+[13][0x67 - 1] = "Shanghai Ningyuan Electronic Technology",
+[13][0x68 - 1] = "Auradine",
+[13][0x69 - 1] = "Suzhou Yishuo Electronics Co Ltd",
+[13][0x6a - 1] = "Faurecia Clarion Electronics",
+[13][0x6b - 1] = "SiMa Technologies",
+[13][0x6c - 1] = "CFD Sales Inc",
+[13][0x6d - 1] = "Suzhou Comay Information Co Ltd",
+[13][0x6e - 1] = "Yentek",
+[13][0x6f - 1] = "Qorvo Inc",
+[13][0x70 - 1] = "Shenzhen Youzhi Computer Technology",
+[13][0x71 - 1] = "Sychw Technology (Shenzhen) Co Ltd",
+[13][0x72 - 1] = "MK Founder Technology Co Ltd",
+[13][0x73 - 1] = "Siliconwaves Technologies Co Ltd",
+[13][0x74 - 1] = "Hongkong Hyunion Electronics Co Ltd",
+[13][0x75 - 1] = "Shenzhen Xinxinzhitao Electronics Business",
+[13][0x76 - 1] = "Shenzhen HenQi Electronic Commerce Co",
+[13][0x77 - 1] = "Shenzhen Jingyi Technology Co Ltd",
+[13][0x78 - 1] = "Xiaohua Semiconductor Co. Ltd.",
+[13][0x79 - 1] = "Shenzhen Dalu Semiconductor Technology",
+[13][0x7a - 1] = "Shenzhen Ninespeed Electronics Co Ltd",
+[13][0x7b - 1] = "ICYC Semiconductor Co Ltd",
+[13][0x7c - 1] = "Shenzhen Jaguar Microsystems Co Ltd",
+[13][0x7d - 1] = "Beijing EC-Founder Co Ltd",
+[13][0x7e - 1] = "Shenzhen Taike Industrial Automation Co",
+[14][0x01 - 1] = "Kalray SA",
+[14][0x02 - 1] = "Shanghai Iluvatar CoreX Semiconductor Co",
+[14][0x03 - 1] = "Fungible Inc",
+[14][0x04 - 1] = "Song Industria E Comercio de Eletronicos",
+[14][0x05 - 1] = "DreamBig Semiconductor Inc",
+[14][0x06 - 1] = "ChampTek Electronics Corp",
+[14][0x07 - 1] = "Fusontai Technology",
+[14][0x08 - 1] = "Endress Hauser AG",
+[14][0x09 - 1] = "altec ComputerSysteme GmbH",
+[14][0x0a - 1] = "UltraRISC Technology (Shanghai) Co Ltd",
+[14][0x0b - 1] = "Shenzhen Jing Da Kang Technology Co Ltd",
+[14][0x0c - 1] = "Hangzhou Hongjun Microelectronics Co Ltd",
/* EOF */
-----------------------------------------------------------------------
Summary of changes:
src/helper/jep106.inc | 87 +++++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 84 insertions(+), 3 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-11-15 21:34:19
|
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commit 0d055602c3fcf81e42a3928328e763f80a73097b
Author: Simon Smiganovski <sim...@fr...>
Date: Wed Nov 9 16:32:26 2022 +0100
flash/nor/stm32f1x: adjust size of the flash loader buffer
target_run_flash_async_algorithm expects the source_buffer to have
at least 2 words reserved for read and write pointers in addition to the
FIFO buffer. If the size of the data to be flashed is <= 8 bytes then
the flash function will fail with "corrupted fifo read pointer" error.
Ensure the allocated buffer is big enough to hold both FIFO buffer and
read/write pointers.
Change-Id: I09c22eaac517b8cfea8e0b463f5deb6b98afd267
Signed-off-by: Simon Smiganovski <sim...@fr...>
Signed-off-by: Paul Fertser <fer...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7342
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index e882d7f79..ab1ef2aef 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -473,7 +473,7 @@ static int stm32x_write_block_async(struct flash_bank *bank, const uint8_t *buff
/* memory buffer */
buffer_size = target_get_working_area_avail(target);
- buffer_size = MIN(hwords_count * 2, MAX(buffer_size, 256));
+ buffer_size = MIN(hwords_count * 2 + 8, MAX(buffer_size, 256));
/* Normally we allocate all available working area.
* MIN shrinks buffer_size if the size of the written block is smaller.
* MAX prevents using async algo if the available working area is smaller
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32f1x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-11-15 21:33:39
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commit 69391878535ec584a472475ee9767b6beaaa138c
Author: Tomas Vanek <va...@fb...>
Date: Tue Oct 18 22:00:18 2022 +0200
target/armv7m: prevent saving and restoring non existent regs
armv7m_start_algorithm() saves register values to arch_info->context.
armv7m_wait_algorithm() restores register values from arch_info->context.
Exclude registers with flag exist = false from both loops.
While on it refactor the register restore: introduce 'struct reg' pointer
and dereference it instead of numerous accesses by a full path
from armv7m pointer.
Change-Id: I1600084db84809ee13bcf8e7828b79f8c9ff9077
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7276
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index d9d01923a..d28702dd7 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -529,6 +529,9 @@ int armv7m_start_algorithm(struct target *target,
/* Store all non-debug execution registers to armv7m_algorithm_info context */
for (unsigned i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
+ if (!reg->exist)
+ continue;
+
if (!reg->valid)
armv7m_get_core_reg(reg);
@@ -688,16 +691,19 @@ int armv7m_wait_algorithm(struct target *target,
}
for (int i = armv7m->arm.core_cache->num_regs - 1; i >= 0; i--) {
+ struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
+ if (!reg->exist)
+ continue;
+
uint32_t regvalue;
- regvalue = buf_get_u32(armv7m->arm.core_cache->reg_list[i].value, 0, 32);
+ regvalue = buf_get_u32(reg->value, 0, 32);
if (regvalue != armv7m_algorithm_info->context[i]) {
LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
- armv7m->arm.core_cache->reg_list[i].name,
- armv7m_algorithm_info->context[i]);
- buf_set_u32(armv7m->arm.core_cache->reg_list[i].value,
+ reg->name, armv7m_algorithm_info->context[i]);
+ buf_set_u32(reg->value,
0, 32, armv7m_algorithm_info->context[i]);
- armv7m->arm.core_cache->reg_list[i].valid = true;
- armv7m->arm.core_cache->reg_list[i].dirty = true;
+ reg->valid = true;
+ reg->dirty = true;
}
}
-----------------------------------------------------------------------
Summary of changes:
src/target/armv7m.c | 18 ++++++++++++------
1 file changed, 12 insertions(+), 6 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-11-15 09:55:02
|
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commit 1d04ef3e55843f9880b7bbab32f564d2018a4b93
Author: Tomas Vanek <va...@fb...>
Date: Thu Nov 3 08:48:53 2022 +0100
tcl/interface: fix raspberrypi2-native.cfg speed coefficient
The speed coefficient for Raspberry Pi 2 was probably calibrated
for a scaled down clock frequency.
To prevent JTAG/SWD overclocking, use the value corresponding
to the 'official' maximum CPU clock.
Change-Id: Iaff58b092198dce6d6552c9d31d6a3ba4aaaa2d5
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7305
Tested-by: jenkins
Reviewed-by: Jonathan Bell <jon...@ra...>
diff --git a/tcl/interface/raspberrypi2-native.cfg b/tcl/interface/raspberrypi2-native.cfg
index 5faabed9d..d5edded0f 100644
--- a/tcl/interface/raspberrypi2-native.cfg
+++ b/tcl/interface/raspberrypi2-native.cfg
@@ -15,9 +15,9 @@ adapter driver bcm2835gpio
bcm2835gpio peripheral_base 0x3F000000
# Transition delay calculation: SPEED_COEFF/khz - SPEED_OFFSET
-# These depend on system clock, calibrated for stock 700MHz
+# These depend on system clock, calibrated for scaling_max_freq 900MHz
# bcm2835gpio speed SPEED_COEFF SPEED_OFFSET
-bcm2835gpio speed_coeffs 146203 36
+bcm2835gpio speed_coeffs 225000 36
# Each of the JTAG lines need a gpio number set: tck tms tdi tdo
# Header pin numbers: 23 22 19 21
-----------------------------------------------------------------------
Summary of changes:
tcl/interface/raspberrypi2-native.cfg | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-11-11 20:24:41
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
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commit 4e077fddadd7d8fedacc61f59ce18a700f6759cf
Author: George Voicu <raz...@ho...>
Date: Sat Nov 5 10:59:43 2022 +0100
tcl/cpld/xilinx-xcu: fix typo
Fix typo in comments
Signed-off-by: George Voicu <raz...@ho...>
Change-Id: Icc2d770e73f896e20dd347de324328030544bdb9
Reviewed-on: https://review.openocd.org/c/openocd/+/7333
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/cpld/xilinx-xcu.cfg b/tcl/cpld/xilinx-xcu.cfg
index 57a59f59a..9df696d4c 100644
--- a/tcl/cpld/xilinx-xcu.cfg
+++ b/tcl/cpld/xilinx-xcu.cfg
@@ -9,7 +9,7 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME xcu
}
-# The cvarious chips in the Ultrascale family have different IR length.
+# The various chips in the Ultrascale family have different IR length.
# Set $CHIP before including this file to determine the device.
array set _XCU_DATA {
XCKU025 {0x03824093 6}
-----------------------------------------------------------------------
Summary of changes:
tcl/cpld/xilinx-xcu.cfg | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-11-11 20:24:18
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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commit d3e79c1eafedf24ee8f6ff872826be07d9e9b654
Author: Daniel Anselmi <dan...@gm...>
Date: Wed Nov 2 17:21:18 2022 +0100
pld/virtex2: small doc extension
Change-Id: I174cd702388be04268b38178fbfacb90db452f72
Signed-off-by: Daniel Anselmi <dan...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7303
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 0fd2322f2..e9f93614c 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -8478,12 +8478,20 @@ that particular type of PLD.
@deffn {FPGA Driver} {virtex2} [no_jstart]
Virtex-II is a family of FPGAs sold by Xilinx.
+This driver can also be used to load Series3, Series6, Series7 and Zynq 7000 devices.
It supports the IEEE 1532 standard for In-System Configuration (ISC).
If @var{no_jstart} is non-zero, the JSTART instruction is not used after
loading the bitstream. While required for Series2, Series3, and Series6, it
breaks bitstream loading on Series7.
+@example
+openocd -f board/digilent_zedboard.cfg -c "init" \
+ -c "pld load 0 zedboard_bitstream.bit"
+@end example
+
+
+
@deffn {Command} {virtex2 read_stat} num
Reads and displays the Virtex-II status register (STAT)
for FPGA @var{num}.
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 8 ++++++++
1 file changed, 8 insertions(+)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-11-11 20:23:39
|
This is an automated email from the git hooks/post-receive script. It was
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commit fb23c9c10bd161ac05b85e73ad91676063592b96
Author: Antonio Borneo <bor...@gm...>
Date: Fri Nov 4 00:32:20 2022 +0100
rtos: hwthread: fix clang error core.NullDereference
Clang spots a potential NULL pointer dereferencing that is instead
an incorrect use of an array of pointers:
src/rtos/hwthread.c:254:32: warning: Dereference of null pointer
[core.NullDereference]
(*rtos_reg_list)[j].number = (*reg_list)[i].number;
^~~~~~~~~~~~~~~~~~~~~
The error has not been spotted before because:
- this function is not called for the first core of the SMP node,
- for the other cores on Cortex-A it still returns valid register
value for the first 12 ARM registers, then it diverges.
Also Valgrind does not spot any issue at runtime.
Address the array correctly.
While there, use DIV_ROUND_UP() macro for the computation.
Change-Id: Ib87e60e0edfd9671091f5dcfa9aedaf1aed800d1
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7337
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/rtos/hwthread.c b/src/rtos/hwthread.c
index e5eaf425f..50e7bae51 100644
--- a/src/rtos/hwthread.c
+++ b/src/rtos/hwthread.c
@@ -255,10 +255,10 @@ static int hwthread_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
for (int i = 0; i < reg_list_size; i++) {
if (!reg_list[i] || reg_list[i]->exist == false || reg_list[i]->hidden)
continue;
- (*rtos_reg_list)[j].number = (*reg_list)[i].number;
- (*rtos_reg_list)[j].size = (*reg_list)[i].size;
- memcpy((*rtos_reg_list)[j].value, (*reg_list)[i].value,
- ((*reg_list)[i].size + 7) / 8);
+ (*rtos_reg_list)[j].number = reg_list[i]->number;
+ (*rtos_reg_list)[j].size = reg_list[i]->size;
+ memcpy((*rtos_reg_list)[j].value, reg_list[i]->value,
+ DIV_ROUND_UP(reg_list[i]->size, 8));
j++;
}
free(reg_list);
-----------------------------------------------------------------------
Summary of changes:
src/rtos/hwthread.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-11-11 20:23:23
|
This is an automated email from the git hooks/post-receive script. It was
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commit 09731b69a6f50c7e0e2f6fa0ba245374034217cb
Author: Tomas Vanek <va...@fb...>
Date: Sun Oct 30 08:22:37 2022 +0000
Revert "Remove duplicate of a counter in hwthread_update_threads"
Commit 0cedf10f8fd6 ("Remove duplicate of a counter in
hwthread_update_threads") introduced a code bug.
In the second foreach_smp_target() loop, variable "threads_found"
gets passed to routine hwthread_fill_thread(). By removing the
counting of threads_found from the second loop, the
incorrect thread counter value gets passed to hwthread_fill_thread().
Change-Id: Ie89e53ccd28bb72b6838ef2f12106a1fe8d00994
Suggested-by: Daniel Goehring <dgo...@os...>
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7307
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/rtos/hwthread.c b/src/rtos/hwthread.c
index bdd5835c2..e5eaf425f 100644
--- a/src/rtos/hwthread.c
+++ b/src/rtos/hwthread.c
@@ -78,6 +78,7 @@ static int hwthread_fill_thread(struct rtos *rtos, struct target *curr, int thre
static int hwthread_update_threads(struct rtos *rtos)
{
int threads_found = 0;
+ int thread_list_size = 0;
struct target_list *head;
struct target *target;
int64_t current_thread = 0;
@@ -99,13 +100,13 @@ static int hwthread_update_threads(struct rtos *rtos)
if (!target_was_examined(curr))
continue;
- ++threads_found;
+ ++thread_list_size;
}
} else
- threads_found = 1;
+ thread_list_size = 1;
/* create space for new thread details */
- rtos->thread_details = malloc(sizeof(struct thread_detail) * threads_found);
+ rtos->thread_details = malloc(sizeof(struct thread_detail) * thread_list_size);
if (target->smp) {
/* loop over all threads */
@@ -170,10 +171,13 @@ static int hwthread_update_threads(struct rtos *rtos)
default:
break;
}
+
+ threads_found++;
}
} else {
hwthread_fill_thread(rtos, target, threads_found);
current_thread = threadid_from_target(target);
+ threads_found++;
}
rtos->thread_count = threads_found;
-----------------------------------------------------------------------
Summary of changes:
src/rtos/hwthread.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-11-11 20:23:00
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 3da0c2504c14ea0736b973fa0b5085c42a9c6ce8
Author: Tomas Vanek <va...@fb...>
Date: Thu Oct 20 11:43:10 2022 +0200
jtag/drivers/cmsis_dap: prevent CDC missdetect as CMSIS-DAP bulk
The autodetection of CMSIS-DAP v2 bulk interface is tricky
as not all adapters conform CMSIS-DAP specs.
If an interface has a string descriptor containing CMSIS-DAP,
then OpenOCD did not insisted on the correct interface class
LIBUSB_CLASS_VENDOR_SPEC.
However the relaxed test caused false autodetection of v2 bulk
interface on some CMSIS-DAP v1 adapters with an additional serial
interface with the string descriptor stupidly containing
CMSIS-DAP text.
Make the test less relaxed, refuse autodetection of the interfaces
with the class number of well known functions including CDC and MSC.
Link: https://sourceforge.net/p/openocd/tickets/368/
Change-Id: I917cb257eb42aab93560cc39c61ec35a60ce52e3
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7279
Tested-by: jenkins
Reviewed-by: SilverFox <yyj...@12...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/cmsis_dap_usb_bulk.c b/src/jtag/drivers/cmsis_dap_usb_bulk.c
index a738200ea..55b9a558a 100644
--- a/src/jtag/drivers/cmsis_dap_usb_bulk.c
+++ b/src/jtag/drivers/cmsis_dap_usb_bulk.c
@@ -262,8 +262,10 @@ static int cmsis_dap_usb_open(struct cmsis_dap *dap, uint16_t vids[], uint16_t p
/* If the interface is reliably identified
* then we need not insist on setting USB class, subclass and protocol
* exactly as the specification requires.
+ * Just filter out the well known classes, mainly CDC and MSC.
* At least KitProg3 uses class 0 contrary to the specification */
- if (intf_identified_reliably) {
+ if (intf_identified_reliably &&
+ (intf_desc->bInterfaceClass == 0 || intf_desc->bInterfaceClass > 0x12)) {
LOG_WARNING("Using CMSIS-DAPv2 interface %d with wrong class %" PRId8
" subclass %" PRId8 " or protocol %" PRId8,
interface_num,
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/cmsis_dap_usb_bulk.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-11-11 20:13:16
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 1dea9ab41f988c5173325521b1e9b75274a785da (commit)
from 5fc4882b8039dbd35f2efcd1419e83fbda9eba28 (commit)
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- Log -----------------------------------------------------------------
commit 1dea9ab41f988c5173325521b1e9b75274a785da
Author: Antonio Borneo <bor...@gm...>
Date: Wed Nov 2 23:11:19 2022 +0100
flash: stmqspi: fix clang error 'dead assignment'
The variable retval is assigned a value that is never used, as it
is reassigned few lines below.
Drop the dead assignment.
Change-Id: Id4e9134408fab3e04936d36e95724bf8d3ab55aa
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7304
Tested-by: jenkins
diff --git a/src/flash/nor/stmqspi.c b/src/flash/nor/stmqspi.c
index 9c266e91a..e5df3b9e0 100644
--- a/src/flash/nor/stmqspi.c
+++ b/src/flash/nor/stmqspi.c
@@ -1799,7 +1799,6 @@ static int find_sfdp_dummy(struct flash_bank *bank, int len)
}
}
- retval = ERROR_FAIL;
LOG_DEBUG("no start of SFDP header even after %u dummy bytes", count);
err:
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stmqspi.c | 1 -
1 file changed, 1 deletion(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-11-11 20:12:59
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 5fc4882b8039dbd35f2efcd1419e83fbda9eba28 (commit)
from 0946e80407150b68acd02bc59f0f3a3170142c4c (commit)
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- Log -----------------------------------------------------------------
commit 5fc4882b8039dbd35f2efcd1419e83fbda9eba28
Author: Antonio Borneo <bor...@gm...>
Date: Wed Nov 2 01:13:49 2022 +0100
dsp5680xx: fix clang error core.UndefinedBinaryOperatorResult
Clang get confused by initializing the array uint16_t lock_word[],
casting it to (uint8_t *), then accessing the second element of
the uint8_t pointer.
src/target/dsp5680xx.c:2046:41: warning: The left operand of '<<'
is a garbage value [core.UndefinedBinaryOperatorResult]
uint16_t tmp = (buffer[0] | (buffer[1] << 8));
~~~~~~~~~ ^
Fix it by replacing the array with a single uint16_t.
The code is still depending on host endianness; no fix for this is
proposed.
Change-Id: I16dfd60cab117dd145aeecf10d9593574ff233a2
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7302
Tested-by: jenkins
diff --git a/src/target/dsp5680xx.c b/src/target/dsp5680xx.c
index 37cf0590d..c90bca3c1 100644
--- a/src/target/dsp5680xx.c
+++ b/src/target/dsp5680xx.c
@@ -2200,8 +2200,8 @@ int dsp5680xx_f_lock(struct target *target)
struct jtag_tap *tap_chp;
struct jtag_tap *tap_cpu;
- uint16_t lock_word[] = { HFM_LOCK_FLASH };
- retval = dsp5680xx_f_wr(target, (uint8_t *) (lock_word), HFM_LOCK_ADDR_L, 2, 1);
+ uint16_t lock_word = HFM_LOCK_FLASH;
+ retval = dsp5680xx_f_wr(target, (uint8_t *)&lock_word, HFM_LOCK_ADDR_L, 2, 1);
err_check_propagate(retval);
jtag_add_reset(0, 1);
-----------------------------------------------------------------------
Summary of changes:
src/target/dsp5680xx.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
hooks/post-receive
--
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From: OpenOCD-Gerrit <ope...@us...> - 2022-11-11 20:11:33
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 0946e80407150b68acd02bc59f0f3a3170142c4c (commit)
from 7a09635735486dd2d74576b003c85c7ff16705d5 (commit)
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- Log -----------------------------------------------------------------
commit 0946e80407150b68acd02bc59f0f3a3170142c4c
Author: Antonio Borneo <bor...@gm...>
Date: Wed Nov 2 00:57:17 2022 +0100
esirisc_jtag: fix clang error core.VLASize
The function esirisc_jtag_recv() can be called with argument
num_in_fields = 0, for example as consequence of calling
esirisc_jtag_continue().
In this case, num_in_bytes is zero and the allocation of the
variable-length array 'r' requires size zero.
src/target/esirisc_jtag.c:133:2: warning: Declared variable-length
array (VLA) has zero size [core.VLASize]
uint8_t r[num_in_bytes * 2];
^~~~~~~~~ ~~~~~~~~~~~~~~~~
Fix it by forcing size one when num_in_bytes is zero.
Change-Id: Id764c7b5ec4f5b3c18c7da650bbff39fc98ed049
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7301
Tested-by: jenkins
diff --git a/src/target/esirisc_jtag.c b/src/target/esirisc_jtag.c
index 54abc4003..1ec1726e5 100644
--- a/src/target/esirisc_jtag.c
+++ b/src/target/esirisc_jtag.c
@@ -130,7 +130,9 @@ static int esirisc_jtag_recv(struct esirisc_jtag *jtag_info,
int num_in_bytes = DIV_ROUND_UP(num_in_bits, 8);
struct scan_field fields[3];
- uint8_t r[num_in_bytes * 2];
+ /* prevent zero-size variable length array */
+ int r_size = num_in_bytes ? num_in_bytes * 2 : 1;
+ uint8_t r[r_size];
esirisc_jtag_set_instr(jtag_info, INSTR_DEBUG);
-----------------------------------------------------------------------
Summary of changes:
src/target/esirisc_jtag.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
hooks/post-receive
--
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|
From: OpenOCD-Gerrit <ope...@us...> - 2022-11-11 20:11:17
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 7a09635735486dd2d74576b003c85c7ff16705d5 (commit)
from aca3707bd8848a568dff190e155a7da31b8b5aa4 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 7a09635735486dd2d74576b003c85c7ff16705d5
Author: Antonio Borneo <bor...@gm...>
Date: Wed Nov 2 00:33:16 2022 +0100
openrisc: fix clang error core.CallAndMessage
Clang assumes that size could assume a value that is not 1 nor 2
nor 4. In such condition the buffer in t is allocated (size != 1)
and not initialized. This triggers an error:
src/target/openrisc/or1k_du_adv.c:655:14: warning: 2nd function
call argument is an uninitialized value [core.CallAndMessage]
crc_calc = adbg_compute_crc(crc_calc, data[i], 8);
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Add the default case to cover other values of size.
After this fix, clang still complains on the same line, this time
misunderstanding the limits of the loop and considering that
buf_bswap16() only swaps the first 16 bits, thus passing not
initialized value data[2] to adbg_compute_crc()
Replace malloc() with calloc() to silent it.
Change-Id: I358d7fb2ebefd69255670641bd435b770762a301
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7300
Tested-by: jenkins
diff --git a/src/target/openrisc/or1k_du_adv.c b/src/target/openrisc/or1k_du_adv.c
index cfb7d0ef0..e4c89e5b5 100644
--- a/src/target/openrisc/or1k_du_adv.c
+++ b/src/target/openrisc/or1k_du_adv.c
@@ -934,7 +934,7 @@ static int or1k_adv_jtag_write_memory(struct or1k_jtag *jtag_info,
void *t = NULL;
struct target *target = jtag_info->target;
if ((target->endianness == TARGET_BIG_ENDIAN) && (size != 1)) {
- t = malloc(count * size * sizeof(uint8_t));
+ t = calloc(count * size, sizeof(uint8_t));
if (!t) {
LOG_ERROR("Out of memory");
return ERROR_FAIL;
@@ -947,6 +947,9 @@ static int or1k_adv_jtag_write_memory(struct or1k_jtag *jtag_info,
case 2:
buf_bswap16(t, buffer, size * count);
break;
+ default:
+ free(t);
+ return ERROR_TARGET_FAILURE;
}
buffer = t;
}
-----------------------------------------------------------------------
Summary of changes:
src/target/openrisc/or1k_du_adv.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-11-11 20:10:58
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via aca3707bd8848a568dff190e155a7da31b8b5aa4 (commit)
from 3ca7bc7354ea3f8db8384142c2bd8675789e7888 (commit)
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- Log -----------------------------------------------------------------
commit aca3707bd8848a568dff190e155a7da31b8b5aa4
Author: Antonio Borneo <bor...@gm...>
Date: Tue Nov 1 19:21:35 2022 +0100
helper/types: use unsigned type for all h_u64_to_le() and similar
All the converters functions:
h_u64_to_le()
h_u64_to_be()
h_u32_to_le()
h_u32_to_be()
h_u24_to_le()
h_u24_to_be()
h_u16_to_le()
h_u16_to_be()
have signed type in their prototype, while the function name and
all the current use cases pass an unsigned value.
Change the prototypes to use unsigned types.
Change-Id: I76dcfdd7912b81f60902184712b2907eae9843f7
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7299
Tested-by: jenkins
diff --git a/src/helper/types.h b/src/helper/types.h
index b99ece109..587ed22c8 100644
--- a/src/helper/types.h
+++ b/src/helper/types.h
@@ -151,7 +151,7 @@ static inline uint16_t be_to_h_u16(const uint8_t *buf)
return (uint16_t)((uint16_t)buf[1] | (uint16_t)buf[0] << 8);
}
-static inline void h_u64_to_le(uint8_t *buf, int64_t val)
+static inline void h_u64_to_le(uint8_t *buf, uint64_t val)
{
buf[7] = (uint8_t) (val >> 56);
buf[6] = (uint8_t) (val >> 48);
@@ -163,7 +163,7 @@ static inline void h_u64_to_le(uint8_t *buf, int64_t val)
buf[0] = (uint8_t) (val >> 0);
}
-static inline void h_u64_to_be(uint8_t *buf, int64_t val)
+static inline void h_u64_to_be(uint8_t *buf, uint64_t val)
{
buf[0] = (uint8_t) (val >> 56);
buf[1] = (uint8_t) (val >> 48);
@@ -175,7 +175,7 @@ static inline void h_u64_to_be(uint8_t *buf, int64_t val)
buf[7] = (uint8_t) (val >> 0);
}
-static inline void h_u32_to_le(uint8_t *buf, int val)
+static inline void h_u32_to_le(uint8_t *buf, uint32_t val)
{
buf[3] = (uint8_t) (val >> 24);
buf[2] = (uint8_t) (val >> 16);
@@ -183,7 +183,7 @@ static inline void h_u32_to_le(uint8_t *buf, int val)
buf[0] = (uint8_t) (val >> 0);
}
-static inline void h_u32_to_be(uint8_t *buf, int val)
+static inline void h_u32_to_be(uint8_t *buf, uint32_t val)
{
buf[0] = (uint8_t) (val >> 24);
buf[1] = (uint8_t) (val >> 16);
@@ -191,27 +191,27 @@ static inline void h_u32_to_be(uint8_t *buf, int val)
buf[3] = (uint8_t) (val >> 0);
}
-static inline void h_u24_to_le(uint8_t *buf, int val)
+static inline void h_u24_to_le(uint8_t *buf, unsigned int val)
{
buf[2] = (uint8_t) (val >> 16);
buf[1] = (uint8_t) (val >> 8);
buf[0] = (uint8_t) (val >> 0);
}
-static inline void h_u24_to_be(uint8_t *buf, int val)
+static inline void h_u24_to_be(uint8_t *buf, unsigned int val)
{
buf[0] = (uint8_t) (val >> 16);
buf[1] = (uint8_t) (val >> 8);
buf[2] = (uint8_t) (val >> 0);
}
-static inline void h_u16_to_le(uint8_t *buf, int val)
+static inline void h_u16_to_le(uint8_t *buf, uint16_t val)
{
buf[1] = (uint8_t) (val >> 8);
buf[0] = (uint8_t) (val >> 0);
}
-static inline void h_u16_to_be(uint8_t *buf, int val)
+static inline void h_u16_to_be(uint8_t *buf, uint16_t val)
{
buf[0] = (uint8_t) (val >> 8);
buf[1] = (uint8_t) (val >> 0);
-----------------------------------------------------------------------
Summary of changes:
src/helper/types.h | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
hooks/post-receive
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From: OpenOCD-Gerrit <ope...@us...> - 2022-11-04 21:49:31
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 3ca7bc7354ea3f8db8384142c2bd8675789e7888 (commit)
from 12ce170945917198b166a35160214d909dfb0dc0 (commit)
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- Log -----------------------------------------------------------------
commit 3ca7bc7354ea3f8db8384142c2bd8675789e7888
Author: Ben McMorran <bem...@mi...>
Date: Thu Oct 20 15:39:24 2022 -0700
ThreadX: set current_thread for kernel execution
If we just invented thread 1 to represent the current execution, we
need to make sure the RTOS object also claims it's the current thread
so that threadx_get_thread_reg_list() doesn't attempt to read a
thread control block at 0x00000001.
Signed-off-by: Ben McMorran <bem...@mi...>
Change-Id: I7f71e730d047858898297e4cb31db8e47e0c371c
Reviewed-on: https://review.openocd.org/c/openocd/+/7280
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/rtos/ThreadX.c b/src/rtos/ThreadX.c
index 7b76fb625..5f90eb644 100644
--- a/src/rtos/ThreadX.c
+++ b/src/rtos/ThreadX.c
@@ -320,6 +320,12 @@ static int threadx_update_threads(struct rtos *rtos)
rtos->thread_details->thread_name_str = malloc(sizeof(tmp_str));
strcpy(rtos->thread_details->thread_name_str, tmp_str);
+ /* If we just invented thread 1 to represent the current execution, we
+ * need to make sure the RTOS object also claims it's the current thread
+ * so that threadx_get_thread_reg_list() doesn't attempt to read a
+ * thread control block at 0x00000001. */
+ rtos->current_thread = 1;
+
if (thread_list_size == 0) {
rtos->thread_count = 1;
return ERROR_OK;
-----------------------------------------------------------------------
Summary of changes:
src/rtos/ThreadX.c | 6 ++++++
1 file changed, 6 insertions(+)
hooks/post-receive
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From: OpenOCD-Gerrit <ope...@us...> - 2022-10-26 13:59:03
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The annotated tag, v0.12.0-rc2 has been created
at bc403d2f7adf0b56afa0b1ca82a8c7a45b3265f2 (tag)
tagging 62cdf7a1df6b43230f1d6ea20755e0b61bb826f9 (commit)
replaces v0.12.0-rc1
tagged by Paul Fertser
on Wed Oct 26 16:57:50 2022 +0300
- Log -----------------------------------------------------------------
The openocd-0.12.0-rc2 release.
Antonio Borneo (17):
checkpatch: fix for flag --no-tree
doc: fix copyright dates
jtag/adapter: fix doxygen warning
target/dsp563xx: fix scan-build warning
target/riscv-013: fix unchecked return code
target/riscv-013: fix unused initialization
target/riscv: fix unused initialization
target/riscv: fix dead assignment
target/riscv: fix undefined operation
target/riscv: fix use of uninitialized value
openocd: fix build with 'configure --without-capstone'
README: cleanup requirements for pkg-config
README: update build dependency list
doc: fix xtensa commands type
doc: fix espusbjtag commands type
doc: remove unreferenced anchors
doc: fix riscv commands
Daniel Anselmi (3):
fix memory leak in virtex2 driver
don't return ERROR_OK in error cases
fix leaky file-handle in virtex2 driver
Daniel Goehring (2):
target/target: read_memory 64-bit bugfix
target/adiv5: 64-bit TAR setup bugfix
Erhan Kurubas (8):
target/xtensa: rename pc and ps macro names
target/xtensa: pass correct buffer on read memory retry
tcl/xtensa: some fixes at xtensa-core-esp32.cfg
tcl/xtensa: some fixes at xtensa-core-esp32s2.cfg
tcl/xtensa: some fixes at xtensa-core-esp32s3.cfg
target/esp32s2: check xtensa_poll return value
target/xtensa: fill register number field in the cache
target/xtensa: remove redundant call for `TARGET_EVENT_HALTED`
Evgeniy Naydanov (1):
Remove duplicate of a counter in hwthread_update_threads
Ian Thompson (1):
target/xtensa: fix final clang analyzer warning
Jonathan Bell (1):
jtag/drivers: bcm2835gpio: implement memory barriers when bitbashing
Keith Packard (1):
flash/nor/at91samd: Use 32-bit register writes for ST-Link compat
Nishanth Menon (1):
tcl/target/ti_k3: Handle swd vs jtag
Paul Fertser (2):
Restore +dev suffix
The openocd-0.12.0-rc2 release candidate
Tarek BOCHKATI (2):
tcl/stm32l5x|u5x: support HLA adapters in non-secure mode only
doc: fix semihosting_redirect command documentation
Tomas Vanek (21):
target/stm32l5x,stm32u5x: fix trace settings
target/adi_v5_swd: fix SWD multidrop
target/adi_v5_swd: suppress reconnect in swd_multidrop_select()
flash/nor/rp2040: preparatory refactoring
flash/nor/rp2040: fix memory leak of target stack workarea
flash/nor/rp2040: fix size of flash write buffer
flash/nor/rp2040: fix flash erase timeout
flash/nor/rp2040: check target halted before flash operation
flash/nor/rp2040: use LOG_TARGET_xxx to show core name
flash/nor/rp2040: remove new line from error message
flash/nor/rp2040: fix setting sp
target/armv7m: prevent storing invalid register
target/armv7m: show target name in 'halted' message
jtag/drivers/cmsis_dap: add LOG_DEBUG_IO to cmsis_dap_metacmd_targetsel
jtag/drivers/bitbang: reduce debug verbosity
target/cortex_m: make reset robust again
target/cortex_m: try to re-examine under reset in cortex_m_assert_reset()
target/hla_target: try to re-examine under reset in hl_assert_reset()
target: re-examine before arp_waitstate in ocd_process_reset_inner
tcl/target: fix rp2040-core0.cfg work area backup.
tcl/target: add basic RP2040 target config
-----------------------------------------------------------------------
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From: OpenOCD-Gerrit <ope...@us...> - 2022-10-26 13:45:45
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 12ce170945917198b166a35160214d909dfb0dc0 (commit)
via 62cdf7a1df6b43230f1d6ea20755e0b61bb826f9 (commit)
from 92169e9f5529959aa63f13c47c3975dfe90a686b (commit)
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- Log -----------------------------------------------------------------
commit 12ce170945917198b166a35160214d909dfb0dc0
Author: Paul Fertser <fer...@gm...>
Date: Wed Oct 26 16:43:49 2022 +0300
Restore +dev suffix
Signed-off-by: Paul Fertser <fer...@gm...>
diff --git a/configure.ac b/configure.ac
index b1d1ee21c..503e79169 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
AC_PREREQ([2.69])
-AC_INIT([openocd], [0.12.0-rc2],
+AC_INIT([openocd], [0.12.0-rc2+dev],
[OpenOCD Mailing List <ope...@li...>])
AC_CONFIG_SRCDIR([src/openocd.c])
AC_CONFIG_AUX_DIR([build-aux])
commit 62cdf7a1df6b43230f1d6ea20755e0b61bb826f9
Author: Paul Fertser <fer...@gm...>
Date: Wed Oct 26 13:45:09 2022 +0300
The openocd-0.12.0-rc2 release candidate
Signed-off-by: Paul Fertser <fer...@gm...>
diff --git a/NEWS b/NEWS
index 50cb98439..5bb6e5e7b 100644
--- a/NEWS
+++ b/NEWS
@@ -121,7 +121,7 @@ This release also contains a number of other important functional and
cosmetic bugfixes. For more details about what has changed since the
last release, see the git repository history:
-http://sourceforge.net/p/openocd/code/ci/v0.12.0-rc1/log/?path=
+http://sourceforge.net/p/openocd/code/ci/v0.12.0-rc2/log/?path=
For older NEWS, see the NEWS files associated with each release
diff --git a/configure.ac b/configure.ac
index 13c990465..b1d1ee21c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-or-later
AC_PREREQ([2.69])
-AC_INIT([openocd], [0.12.0-rc1+dev],
+AC_INIT([openocd], [0.12.0-rc2],
[OpenOCD Mailing List <ope...@li...>])
AC_CONFIG_SRCDIR([src/openocd.c])
AC_CONFIG_AUX_DIR([build-aux])
-----------------------------------------------------------------------
Summary of changes:
NEWS | 2 +-
configure.ac | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-10-21 18:26:04
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from fada2c001fcdd6b0629b64769752445b41116b83 (commit)
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- Log -----------------------------------------------------------------
commit 92169e9f5529959aa63f13c47c3975dfe90a686b
Author: Tomas Vanek <va...@fb...>
Date: Tue Oct 18 21:19:20 2022 +0200
tcl/target: add basic RP2040 target config
The existing rp2040-core0.cfg configuration file was intended
for a special adapter which selects a SWD multidrop target on its own.
This means that rp2040-core0.cfg is totally unusable with a standard SWD
adapter.
To fix the problem, mark rp2040-core0.cfg as deprecated and
add rp2040.cfg, a basic config file with multidrop target selection.
Change-Id: I5194e42f529a2d9645481424b7c66ab61efa44ee
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7275
Tested-by: jenkins
Reviewed-by: Jonathan Bell <jon...@ra...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/rp2040-core0.cfg b/tcl/target/rp2040-core0.cfg
index 6a0f0ed61..8a111bcbc 100644
--- a/tcl/target/rp2040-core0.cfg
+++ b/tcl/target/rp2040-core0.cfg
@@ -1,5 +1,17 @@
# SPDX-License-Identifier: GPL-2.0-or-later
+# RP2040 is a microcontroller with dual Cortex-M0+ core.
+# https://www.raspberrypi.com/documentation/microcontrollers/rp2040.html
+
+# The device requires multidrop SWD for debug.
+# This configuration file is intended for a special adapter
+# which selects a multidrop target on its own.
+# Cannot be used with a standard SWD adapter!
+
+echo "Warn : rp2040-core0.cfg configuration file is deprecated and will be"
+echo " removed in the next release. Use following parameters instead:"
+echo " -c 'set USE_CORE 0' -f target/rp2040.cfg"
+
transport select swd
source [find target/swj-dp.tcl]
diff --git a/tcl/target/rp2040.cfg b/tcl/target/rp2040.cfg
new file mode 100644
index 000000000..ee455420b
--- /dev/null
+++ b/tcl/target/rp2040.cfg
@@ -0,0 +1,74 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# RP2040 is a microcontroller with dual Cortex-M0+ core.
+# https://www.raspberrypi.com/documentation/microcontrollers/rp2040.html
+
+# The device requires multidrop SWD for debug.
+transport select swd
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME rp2040
+}
+
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ set _WORKAREASIZE 0x10000
+}
+
+if { [info exists CPUTAPID] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x01002927
+}
+
+# Set to '0' or '1' for single core configuration,
+# anything else for isolated debugging of both cores
+if { [info exists USE_CORE] } {
+ set _USE_CORE $USE_CORE
+} else {
+ set _USE_CORE { 0 1 }
+}
+set _BOTH_CORES [expr { $_USE_CORE != 0 && $_USE_CORE != 1 }]
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+
+# core 0
+if { $_USE_CORE != 1 } {
+ dap create $_CHIPNAME.dap0 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 0
+ set _TARGETNAME_0 $_CHIPNAME.core0
+ target create $_TARGETNAME_0 cortex_m -dap $_CHIPNAME.dap0 -coreid 0
+ # srst does not exist; use SYSRESETREQ to perform a soft reset
+ $_TARGETNAME_0 cortex_m reset_config sysresetreq
+}
+
+# core 1
+if { $_USE_CORE != 0 } {
+ dap create $_CHIPNAME.dap1 -chain-position $_CHIPNAME.cpu -dp-id $_CPUTAPID -instance-id 1
+ set _TARGETNAME_1 $_CHIPNAME.core1
+ target create $_TARGETNAME_1 cortex_m -dap $_CHIPNAME.dap1 -coreid 1
+ $_TARGETNAME_1 cortex_m reset_config sysresetreq
+}
+
+if { $_USE_CORE == 1 } {
+ set _FLASH_TARGET $_TARGETNAME_1
+} else {
+ set _FLASH_TARGET $_TARGETNAME_0
+}
+# Backup the work area. The flash probe runs an algorithm on the target CPU.
+# The flash is probed during gdb connect if gdb_memory_map is enabled (by default).
+$_FLASH_TARGET configure -work-area-phys 0x20010000 -work-area-size $_WORKAREASIZE -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME rp2040_flash 0x10000000 0 0 0 $_FLASH_TARGET
+
+if { $_BOTH_CORES } {
+ # Alias to ensure gdb connecting to core 1 gets the correct memory map
+ flash bank $_CHIPNAME.alias virtual 0x10000000 0 0 0 $_TARGETNAME_1 $_FLASHNAME
+
+ # Select core 0
+ targets $_TARGETNAME_0
+}
-----------------------------------------------------------------------
Summary of changes:
tcl/target/rp2040-core0.cfg | 12 ++++++++
tcl/target/rp2040.cfg | 74 +++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 86 insertions(+)
create mode 100644 tcl/target/rp2040.cfg
hooks/post-receive
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From: OpenOCD-Gerrit <ope...@us...> - 2022-10-21 18:23:42
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via fada2c001fcdd6b0629b64769752445b41116b83 (commit)
from c4f88aeb4d1f88f908f96ba252995c5ba247b737 (commit)
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- Log -----------------------------------------------------------------
commit fada2c001fcdd6b0629b64769752445b41116b83
Author: Tarek BOCHKATI <tar...@st...>
Date: Wed Oct 19 14:26:28 2022 +0100
doc: fix semihosting_redirect command documentation
Change-Id: I78c82a21e4160851a5c0b58394ac7897479808ff
Signed-off-by: Tarek BOCHKATI <tar...@st...>
Reviewed-on: https://review.openocd.org/c/openocd/+/7278
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 6321bf7a6..0fd2322f2 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -9498,14 +9498,14 @@ requests by using a special SVC instruction that is trapped at the
Supervisor Call vector by OpenOCD.
@end deffn
-@deffn {Command} {arm semihosting_redirect} (@option{disable} | @option{tcp} <port>
-[@option{debug}|@option{stdio}|@option{all})
+@deffn {Command} {arm semihosting_redirect} (@option{disable} | @option{tcp} <port> [@option{debug}|@option{stdio}|@option{all}])
@cindex ARM semihosting
Redirect semihosting messages to a specified TCP port.
This command redirects debug (READC, WRITEC and WRITE0) and stdio (READ, WRITE)
semihosting operations to the specified TCP port.
The command allows to select which type of operations to redirect (debug, stdio, all (default)).
+
Note: for stdio operations, only I/O from/to ':tt' file descriptors are redirected.
@end deffn
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-10-21 18:20:13
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via c4f88aeb4d1f88f908f96ba252995c5ba247b737 (commit)
from 535de48ca69ba34860067dfe5ea6f7fa6638f7f9 (commit)
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- Log -----------------------------------------------------------------
commit c4f88aeb4d1f88f908f96ba252995c5ba247b737
Author: Tarek BOCHKATI <tar...@gm...>
Date: Fri Sep 24 13:47:14 2021 +0100
tcl/stm32l5x|u5x: support HLA adapters in non-secure mode only
instrument "target/stm32x5x_common.cfg" used by both STM32L5x/U5x
to support HLA adapters like "interface/stlink.cfg" in non-secure mode
if the device switches to secure mode, the debug session will be
stopped immediately (with an explanatory message).
Change-Id: I645fdd55e3448ef82d0ddcc396f42fd7b2f39ac3
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reported-by: Patrik Bachan <di...@us...>
Fixes: https://sourceforge.net/p/openocd/tickets/317/
Reviewed-on: https://review.openocd.org/c/openocd/+/6546
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/tcl/target/stm32x5x_common.cfg b/tcl/target/stm32x5x_common.cfg
index 321abff80..fb3aeb18c 100644
--- a/tcl/target/stm32x5x_common.cfg
+++ b/tcl/target/stm32x5x_common.cfg
@@ -58,7 +58,9 @@ if {[using_jtag]} {
reset_config srst_nogate
-if {![using_hla]} {
+if {[using_hla]} {
+ echo "Warn : The selected adapter does not support debugging this device in secure mode"
+} else {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
@@ -71,13 +73,18 @@ proc stm32x5x_is_secure {} {
}
proc stm32x5x_ahb_ap_non_secure_access {} {
- # SPROT=1=Non Secure access, Priv=1
- [[target current] cget -dap] apcsw 0x4B000000 0x4F000000
+ # in HLA mode, non-secure debugging is possible without changing the AP CSW
+ if {![using_hla]} {
+ # SPROT=1=Non Secure access, Priv=1
+ [[target current] cget -dap] apcsw 0x4B000000 0x4F000000
+ }
}
proc stm32x5x_ahb_ap_secure_access {} {
- # SPROT=0=Secure access, Priv=1
- [[target current] cget -dap] apcsw 0x0B000000 0x4F000000
+ if {![using_hla]} {
+ # SPROT=0=Secure access, Priv=1
+ [[target current] cget -dap] apcsw 0x0B000000 0x4F000000
+ }
}
$_TARGETNAME configure -event reset-start {
-----------------------------------------------------------------------
Summary of changes:
tcl/target/stm32x5x_common.cfg | 17 ++++++++++++-----
1 file changed, 12 insertions(+), 5 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-10-21 18:16:57
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from b8735bbf7ed7eedb0590edbf2a22929b401887ba (commit)
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- Log -----------------------------------------------------------------
commit 535de48ca69ba34860067dfe5ea6f7fa6638f7f9
Author: Erhan Kurubas <erh...@es...>
Date: Tue Oct 18 17:23:15 2022 +0200
target/xtensa: remove redundant call for `TARGET_EVENT_HALTED`
`xtensa_do_step` is invoked from `xtensa_prepare_resume` to silently
step over BP/WP before resuming.
For example; in the case of WPs (DEBUGCAUSE_DB), in the current
implementation `xtensa_do_step` will generate one more
`TARGET_EVENT_HALTED` after the original one caused by WP itself.
This patch moves the halted event cb call after
the step is done successfully.
Signed-off-by: Erhan Kurubas <erh...@es...>
Change-Id: I9048e14fb316dc124847a42cfaefb1f76b5ce53e
Reviewed-on: https://review.openocd.org/c/openocd/+/7274
Tested-by: jenkins
Reviewed-by: Ian Thompson <ia...@ca...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index c1b5f43c8..c2c047edb 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -1630,7 +1630,6 @@ int xtensa_do_step(struct target *target, int current, target_addr_t address, in
target->debug_reason = DBG_REASON_SINGLESTEP;
target->state = TARGET_HALTED;
- target_call_event_callbacks(target, TARGET_EVENT_HALTED);
LOG_DEBUG("Done stepping, PC=%" PRIX32, cur_pc);
if (cause & DEBUGCAUSE_DB) {
@@ -1658,7 +1657,12 @@ int xtensa_do_step(struct target *target, int current, target_addr_t address, in
int xtensa_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
{
- return xtensa_do_step(target, current, address, handle_breakpoints);
+ int retval = xtensa_do_step(target, current, address, handle_breakpoints);
+ if (retval != ERROR_OK)
+ return retval;
+ target_call_event_callbacks(target, TARGET_EVENT_HALTED);
+
+ return ERROR_OK;
}
/**
-----------------------------------------------------------------------
Summary of changes:
src/target/xtensa/xtensa.c | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
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