Menu
▾
▴
openocd-commit — OpenOCD commit maling list - read only
You can subscribe to this list here.
| 2008 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
(75) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2009 |
Jan
(70) |
Feb
(20) |
Mar
(52) |
Apr
(149) |
May
(387) |
Jun
(466) |
Jul
(133) |
Aug
(87) |
Sep
(122) |
Oct
(140) |
Nov
(185) |
Dec
(105) |
| 2010 |
Jan
(85) |
Feb
(45) |
Mar
(75) |
Apr
(17) |
May
(41) |
Jun
(52) |
Jul
(33) |
Aug
(29) |
Sep
(36) |
Oct
(15) |
Nov
(26) |
Dec
(34) |
| 2011 |
Jan
(26) |
Feb
(25) |
Mar
(26) |
Apr
(29) |
May
(20) |
Jun
(27) |
Jul
(15) |
Aug
(32) |
Sep
(13) |
Oct
(64) |
Nov
(60) |
Dec
(10) |
| 2012 |
Jan
(64) |
Feb
(63) |
Mar
(39) |
Apr
(43) |
May
(54) |
Jun
(11) |
Jul
(30) |
Aug
(45) |
Sep
(11) |
Oct
(70) |
Nov
(24) |
Dec
(23) |
| 2013 |
Jan
(17) |
Feb
(8) |
Mar
(35) |
Apr
(40) |
May
(20) |
Jun
(24) |
Jul
(36) |
Aug
(25) |
Sep
(42) |
Oct
(40) |
Nov
(9) |
Dec
(21) |
| 2014 |
Jan
(29) |
Feb
(24) |
Mar
(60) |
Apr
(22) |
May
(22) |
Jun
(46) |
Jul
(11) |
Aug
(23) |
Sep
(26) |
Oct
(10) |
Nov
(14) |
Dec
(2) |
| 2015 |
Jan
(28) |
Feb
(47) |
Mar
(33) |
Apr
(58) |
May
(5) |
Jun
(1) |
Jul
|
Aug
(8) |
Sep
(12) |
Oct
(25) |
Nov
(58) |
Dec
(21) |
| 2016 |
Jan
(12) |
Feb
(40) |
Mar
(2) |
Apr
(1) |
May
(67) |
Jun
(2) |
Jul
(5) |
Aug
(36) |
Sep
|
Oct
(24) |
Nov
(17) |
Dec
(50) |
| 2017 |
Jan
(14) |
Feb
(16) |
Mar
(2) |
Apr
(35) |
May
(14) |
Jun
(16) |
Jul
(3) |
Aug
(3) |
Sep
|
Oct
(19) |
Nov
|
Dec
(16) |
| 2018 |
Jan
(55) |
Feb
(11) |
Mar
(34) |
Apr
(14) |
May
(4) |
Jun
(20) |
Jul
(39) |
Aug
(16) |
Sep
(17) |
Oct
(16) |
Nov
(20) |
Dec
(30) |
| 2019 |
Jan
(29) |
Feb
(24) |
Mar
(37) |
Apr
(26) |
May
(19) |
Jun
(21) |
Jul
(2) |
Aug
(3) |
Sep
(9) |
Oct
(12) |
Nov
(12) |
Dec
(12) |
| 2020 |
Jan
(47) |
Feb
(36) |
Mar
(54) |
Apr
(44) |
May
(37) |
Jun
(19) |
Jul
(32) |
Aug
(13) |
Sep
(16) |
Oct
(24) |
Nov
(32) |
Dec
(11) |
| 2021 |
Jan
(14) |
Feb
(5) |
Mar
(40) |
Apr
(32) |
May
(42) |
Jun
(31) |
Jul
(29) |
Aug
(47) |
Sep
(38) |
Oct
(17) |
Nov
(74) |
Dec
(33) |
| 2022 |
Jan
(11) |
Feb
(15) |
Mar
(40) |
Apr
(21) |
May
(39) |
Jun
(44) |
Jul
(19) |
Aug
(46) |
Sep
(79) |
Oct
(35) |
Nov
(21) |
Dec
(15) |
| 2023 |
Jan
(56) |
Feb
(13) |
Mar
(43) |
Apr
(28) |
May
(60) |
Jun
(15) |
Jul
(29) |
Aug
(28) |
Sep
(32) |
Oct
(21) |
Nov
(42) |
Dec
(39) |
| 2024 |
Jan
(35) |
Feb
(17) |
Mar
(28) |
Apr
(7) |
May
(14) |
Jun
(35) |
Jul
(30) |
Aug
(35) |
Sep
(30) |
Oct
(28) |
Nov
(38) |
Dec
(18) |
| 2025 |
Jan
(21) |
Feb
(28) |
Mar
(36) |
Apr
(35) |
May
(34) |
Jun
(58) |
Jul
(9) |
Aug
(37) |
Sep
|
Oct
|
Nov
|
Dec
|
|
From: Øyvind H. <go...@us...> - 2009-12-30 19:09:00
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via c116d8f6bcb745ccc8fb8e6b562c8f22d54cd003 (commit)
from 20354a66b963b17fb842b0e49b7d0acd3d554c54 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit c116d8f6bcb745ccc8fb8e6b562c8f22d54cd003
Author: Antonio Borneo <bor...@gm...>
Date: Wed Dec 30 22:34:48 2009 +0800
Fix parport_dcl5 config file.
Signed-off-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/interface/parport_dlc5.cfg b/tcl/interface/parport_dlc5.cfg
index 0f94c65..85caefc 100644
--- a/tcl/interface/parport_dlc5.cfg
+++ b/tcl/interface/parport_dlc5.cfg
@@ -5,6 +5,6 @@
#
interface parport
-parport_port /dev/parport0
+parport_port 0
parport_cable dlc5
-----------------------------------------------------------------------
Summary of changes:
tcl/interface/parport_dlc5.cfg | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2009-12-30 13:47:45
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 20354a66b963b17fb842b0e49b7d0acd3d554c54 (commit)
via 2cf6d473752982b2ea46bf083ac9f5e7fe9c9d1b (commit)
from 272c33c190a72999697dd1d7b74a7603d30a84b8 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 20354a66b963b17fb842b0e49b7d0acd3d554c54
Author: Ãyvind Harboe <oyv...@zy...>
Date: Wed Dec 30 13:13:31 2009 +0100
zy1000: add zy1000_ prefix to uart command
less polution of the general namespace(preventive action,
no problems reported).
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/ecosboard.c b/src/ecosboard.c
index c31c596..de2a42c 100644
--- a/src/ecosboard.c
+++ b/src/ecosboard.c
@@ -1097,7 +1097,7 @@ int main(int argc, char *argv[])
NULL, NULL);
#endif
- Jim_CreateCommand(httpstate.jim_interp, "uart", zylinjtag_Jim_Command_uart, NULL, NULL);
+ Jim_CreateCommand(httpstate.jim_interp, "zy1000_uart", zylinjtag_Jim_Command_uart, NULL, NULL);
log_init();
commit 2cf6d473752982b2ea46bf083ac9f5e7fe9c9d1b
Author: Ãyvind Harboe <oyv...@zy...>
Date: Wed Dec 30 12:36:22 2009 +0100
zy1000: unlock flash upon startup for revc
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/ecosboard.c b/src/ecosboard.c
index d7fdabd..c31c596 100644
--- a/src/ecosboard.c
+++ b/src/ecosboard.c
@@ -995,6 +995,20 @@ int main(int argc, char *argv[])
copydir("/rom", "/ram/cgi");
+#ifdef CYGPKG_HAL_NIOS2
+ cyg_flashaddr_t err_address;
+#define UNCACHED_EXT_FLASH_BASE (0x80000000 + EXT_FLASH_BASE)
+ /* The revc flash is locked upon reset, unlock it */
+#ifdef CYGHWR_IO_FLASH_BLOCK_LOCKING
+ if ((err = flash_unlock((void *) UNCACHED_EXT_FLASH_BASE, EXT_FLASH_SPAN,
+ (void **) &err_address)) != 0)
+ {
+ diag_printf("Error: could not unlock flash\n");
+ }
+#endif
+#endif
+
+
err = mount("/dev/flash1", "/config", "jffs2");
if (err < 0)
{
-----------------------------------------------------------------------
Summary of changes:
src/ecosboard.c | 16 +++++++++++++++-
1 files changed, 15 insertions(+), 1 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2009-12-30 12:16:50
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 272c33c190a72999697dd1d7b74a7603d30a84b8 (commit)
via bd3700e89d80b2548890102da3e25012acbd3e41 (commit)
via 12618e4c6d07f6291e2e0c6d7f99a0945b1b67b3 (commit)
from d4bef466c3781b3ee9930681509a9954aaa425a1 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 272c33c190a72999697dd1d7b74a7603d30a84b8
Author: Ãyvind Harboe <oyv...@zy...>
Date: Tue Dec 29 12:30:02 2009 +0100
zy1000: reconfigure FPGA upon reset instead of just the CPU
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/ecosboard.c b/src/ecosboard.c
index 32eb085..d7fdabd 100644
--- a/src/ecosboard.c
+++ b/src/ecosboard.c
@@ -62,6 +62,7 @@
#include "rom.h"
#ifdef CYGPKG_HAL_NIOS2
+#include <cyg/hal/io.h>
#define ZY1000_SER_DEV "/dev/uart_0"
#else
#define ZY1000_SER_DEV "/dev/ser0"
@@ -145,7 +146,14 @@ static void zylinjtag_reboot(cyg_addrword_t data)
diag_printf("Unmounting /config..\n");
umount("/config");
diag_printf("Rebooting..\n");
+#ifdef CYGPKG_HAL_NIOS2
+ /* This will reboot & reconfigure the FPGA from the bootloader
+ * and on.
+ */
+ IOWR(REMOTE_UPDATE_BASE, 0x20, 0x1);
+#else
HAL_PLATFORM_RESET();
+#endif
}
static cyg_thread zylinjtag_thread_object;
static cyg_handle_t zylinjtag_thread_handle;
commit bd3700e89d80b2548890102da3e25012acbd3e41
Author: Ãyvind Harboe <oyv...@zy...>
Date: Fri Dec 25 21:50:41 2009 +0100
zy1000: firmware upgrade fixes for revc
Use ecos firmwareutil upgrade utilities
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c
index 30b9a4b..7c5f440 100644
--- a/src/jtag/zy1000/zy1000.c
+++ b/src/jtag/zy1000/zy1000.c
@@ -55,6 +55,11 @@
#include <time.h>
+#ifdef CYGPKG_HAL_NIOS2
+#include <cyg/hal/io.h>
+#include <cyg/firmwareutil/firmwareutil.h>
+#endif
+
#define ZYLIN_VERSION GIT_ZY1000_VERSION
#define ZYLIN_DATE __DATE__
#define ZYLIN_TIME __TIME__
@@ -322,33 +327,57 @@ static int jim_zy1000_version(Jim_Interp *interp, int argc, Jim_Obj *const *argv
#ifdef CYGPKG_HAL_NIOS2
+
+
+struct info_forward
+{
+ void *data;
+ struct cyg_upgrade_info *upgraded_file;
+};
+
+static void report_info(void *data, const char * format, va_list args)
+{
+ char *s = alloc_vprintf(format, args);
+ LOG_USER_N("%s", s);
+ free(s);
+}
+
+struct cyg_upgrade_info firmware_info =
+{
+ (cyg_uint8 *)0x84000000,
+ "/ram/firmware.phi",
+ "Firmware",
+ 0x0300000,
+ 0x1f00000 -
+ 0x0300000,
+ "ZylinNiosFirmware\n",
+ report_info,
+};
+
static int jim_zy1000_writefirmware(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
{
if (argc != 2)
return JIM_ERR;
int length;
- int stat;
const char *str = Jim_GetString(argv[1], &length);
- /* BUG!!!! skip header! */
- void *firmware_address=0x4000000;
- int firmware_length=0x100000;
-
- if (length>firmware_length)
+ /* */
+ int tmpFile;
+ if ((tmpFile = open(firmware_info.file, O_RDWR | O_CREAT | O_TRUNC)) <= 0)
+ {
+ return JIM_ERR;
+ }
+ bool success;
+ success = write(tmpFile, str, length) == length;
+ close(tmpFile);
+ if (!success)
return JIM_ERR;
- void *err_addr;
-
- if ((stat = flash_erase((void *)firmware_address, firmware_length, (void **)&err_addr)) != 0)
- {
- return JIM_ERR;
- }
-
- if ((stat = flash_program(firmware_address, str, length, (void **)&err_addr)) != 0)
- return JIM_ERR;
+ if (!cyg_firmware_upgrade(NULL, firmware_info))
+ return JIM_ERR;
- return JIM_OK;
+ return JIM_OK;
}
#endif
commit 12618e4c6d07f6291e2e0c6d7f99a0945b1b67b3
Author: Ãyvind Harboe <oyv...@zy...>
Date: Fri Dec 25 23:05:50 2009 +0100
zy1000: less warnings
use inline for static functions in header files to
avoid warnings about fn not being used.
Signed-off-by: Ãyvind Harboe <oyv...@zy...>
diff --git a/src/jtag/zy1000/jtag_minidriver.h b/src/jtag/zy1000/jtag_minidriver.h
index a78a063..1dcf23a 100644
--- a/src/jtag/zy1000/jtag_minidriver.h
+++ b/src/jtag/zy1000/jtag_minidriver.h
@@ -50,7 +50,7 @@ static __inline__ void waitQueue(void)
// waitIdle();
}
-static void sampleShiftRegister(void)
+static __inline__ void sampleShiftRegister(void)
{
#if 0
cyg_uint32 dummy;
@@ -59,8 +59,7 @@ static void sampleShiftRegister(void)
#endif
}
-/* -O3 will inline this for us */
-static void setCurrentState(enum tap_state state)
+static __inline__ void setCurrentState(enum tap_state state)
{
cyg_uint32 a;
a = state;
-----------------------------------------------------------------------
Summary of changes:
src/ecosboard.c | 8 +++++
src/jtag/zy1000/jtag_minidriver.h | 5 +--
src/jtag/zy1000/zy1000.c | 61 +++++++++++++++++++++++++++----------
3 files changed, 55 insertions(+), 19 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2009-12-29 12:42:24
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via d4bef466c3781b3ee9930681509a9954aaa425a1 (commit)
via aa81462618a3dd8b116d4ebdaf8b8b0c6b9351b6 (commit)
from 6b1eeb92fe603c2a3d8d04f299aa1318d2ad4b36 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit d4bef466c3781b3ee9930681509a9954aaa425a1
Author: Piotr Esden-Tempski <pi...@es...>
Date: Mon Dec 28 17:30:32 2009 +0100
Added Open-BLDC board config file.
diff --git a/tcl/board/open-bldc.cfg b/tcl/board/open-bldc.cfg
new file mode 100644
index 0000000..da8654c
--- /dev/null
+++ b/tcl/board/open-bldc.cfg
@@ -0,0 +1,7 @@
+# Open Source Brush Less DC Motor Controller
+# http://open-bldc.org
+
+# Work-area size (RAM size) = 20kB for STM32F103RB device
+set WORKAREASIZE 0x5000
+
+source [find target/stm32.cfg]
commit aa81462618a3dd8b116d4ebdaf8b8b0c6b9351b6
Author: Piotr Esden-Tempski <pi...@es...>
Date: Mon Dec 28 17:15:21 2009 +0100
Added floss-jtag interface config file.
diff --git a/tcl/interface/flossjtag.cfg b/tcl/interface/flossjtag.cfg
new file mode 100644
index 0000000..396e964
--- /dev/null
+++ b/tcl/interface/flossjtag.cfg
@@ -0,0 +1,11 @@
+#
+# FlossJTAG
+#
+# http://github.com/esden/floss-jtag
+#
+
+interface ft2232
+ft2232_vid_pid 0x0403 0x6010
+ft2232_device_desc "Dual RS232-HS"
+ft2232_layout "usbjtag"
+ft2232_latency 2
-----------------------------------------------------------------------
Summary of changes:
tcl/board/{olimex_stm32_h103.cfg => open-bldc.cfg} | 4 ++--
tcl/interface/flossjtag.cfg | 11 +++++++++++
2 files changed, 13 insertions(+), 2 deletions(-)
copy tcl/board/{olimex_stm32_h103.cfg => open-bldc.cfg} (61%)
create mode 100644 tcl/interface/flossjtag.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-12-28 22:24:52
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 6b1eeb92fe603c2a3d8d04f299aa1318d2ad4b36 (commit)
via 37cc6c495f0b5fd2257aecdbde111ddfb6d8b083 (commit)
via ec297e4bf10f7d903d8b5fc3237a7c6bbfa6273d (commit)
via cba1813d5c017e2d20969bb419a856fe15c5ceef (commit)
from 3ace333663628d00795fd0b5ab80c91e6025b4dc (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 6b1eeb92fe603c2a3d8d04f299aa1318d2ad4b36
Author: Freddie Chopin <fre...@op...>
Date: Mon Dec 28 21:08:48 2009 +0100
MinGW build fixes
Print "ssize_t" as "%ld" (+ cast to long) not as "%zu".
Official MinGW (gcc 3.4.5) doesn't understand "z" flag.
Signed-off-by: Freddie Chopin <fre...@op...>
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/flash/mflash.c b/src/flash/mflash.c
index 5c8ca8c..04f5c77 100644
--- a/src/flash/mflash.c
+++ b/src/flash/mflash.c
@@ -751,8 +751,8 @@ COMMAND_HANDLER(mg_write_cmd)
if (duration_measure(&bench) == ERROR_OK)
{
- command_print(CMD_CTX, "wrote %zu byte from file %s "
- "in %fs (%0.3f kB/s)", fileio.size, CMD_ARGV[1],
+ command_print(CMD_CTX, "wrote %ld bytes from file %s "
+ "in %fs (%0.3f kB/s)", (long)fileio.size, CMD_ARGV[1],
duration_elapsed(&bench), duration_kbps(&bench, fileio.size));
}
diff --git a/src/flash/nand/tcl.c b/src/flash/nand/tcl.c
index ad77d7c..4f90c7b 100644
--- a/src/flash/nand/tcl.c
+++ b/src/flash/nand/tcl.c
@@ -409,8 +409,8 @@ COMMAND_HANDLER(handle_nand_dump_command)
if (nand_fileio_finish(&s) == ERROR_OK)
{
- command_print(CMD_CTX, "dumped %zu bytes in %fs (%0.3f kb/s)",
- s.fileio.size, duration_elapsed(&s.bench),
+ command_print(CMD_CTX, "dumped %ld bytes in %fs (%0.3f kb/s)",
+ (long)s.fileio.size, duration_elapsed(&s.bench),
duration_kbps(&s.bench, s.fileio.size));
}
return ERROR_OK;
diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
index 1097bdf..ad2b8f1 100644
--- a/src/flash/nor/tcl.c
+++ b/src/flash/nor/tcl.c
@@ -625,9 +625,9 @@ COMMAND_HANDLER(handle_flash_write_bank_command)
if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK))
{
- command_print(CMD_CTX, "wrote %zu bytes from file %s to flash bank %u"
+ command_print(CMD_CTX, "wrote %ld bytes from file %s to flash bank %u"
" at offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
- fileio.size, CMD_ARGV[1], p->bank_number, offset,
+ (long)fileio.size, CMD_ARGV[1], p->bank_number, offset,
duration_elapsed(&bench), duration_kbps(&bench, fileio.size));
}
diff --git a/src/target/target.c b/src/target/target.c
index ebddbba..8cb53b3 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -2488,7 +2488,7 @@ COMMAND_HANDLER(handle_dump_image_command)
if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK))
{
command_print(CMD_CTX,
- "dumped %zu bytes in %fs (%0.3f kb/s)", fileio.size,
+ "dumped %ld bytes in %fs (%0.3f kb/s)", (long)fileio.size,
duration_elapsed(&bench), duration_kbps(&bench, fileio.size));
}
commit 37cc6c495f0b5fd2257aecdbde111ddfb6d8b083
Author: Freddie Chopin <fre...@op...>
Date: Mon Dec 28 21:40:39 2009 +0100
stm32x commands get "usage"
Add .usage fields to stm32x command_registration,
so that "help stm32x" shows required parameters.
Signed-off-by: Freddie Chopin <fre...@op...>
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/flash/nor/stm32x.c b/src/flash/nor/stm32x.c
index 9e761f9..9e08576 100644
--- a/src/flash/nor/stm32x.c
+++ b/src/flash/nor/stm32x.c
@@ -1188,30 +1188,35 @@ static const struct command_registration stm32x_exec_command_handlers[] = {
.name = "lock",
.handler = &stm32x_handle_lock_command,
.mode = COMMAND_EXEC,
+ .usage = "<bank>",
.help = "lock device",
},
{
.name = "unlock",
.handler = &stm32x_handle_unlock_command,
.mode = COMMAND_EXEC,
+ .usage = "<bank>",
.help = "unlock protected device",
},
{
.name = "mass_erase",
.handler = &stm32x_handle_mass_erase_command,
.mode = COMMAND_EXEC,
+ .usage = "<bank>",
.help = "mass erase device",
},
{
.name = "options_read",
.handler = &stm32x_handle_options_read_command,
.mode = COMMAND_EXEC,
+ .usage = "<bank>",
.help = "read device option bytes",
},
{
.name = "options_write",
.handler = &stm32x_handle_options_write_command,
.mode = COMMAND_EXEC,
+ .usage = "<bank> <SWWDG | HWWDG> <RSTSTNDBY | NORSTSTNDBY> <RSTSTOP | NORSTSTOP>",
.help = "write device option bytes",
},
COMMAND_REGISTRATION_DONE
commit ec297e4bf10f7d903d8b5fc3237a7c6bbfa6273d
Author: David Brownell <dbr...@us...>
Date: Mon Dec 28 12:59:47 2009 -0800
Fix Luminary FT2232 layout docs/configs
Most of this patch updates documentation and comments for various
Luminary boards, supporting two bug fixes by helping to make sense
of the current mess:
- Recent rev C lm3s811 eval boards didn't work. They must use
the ICDI layout, which sets up some signals that the older
boards didn't need. This is actually safe and appropriate
for *all* recent boards ... so just make "luminary.cfg" use
the ICDI layout.
- "luminary-lm3s811.cfg", was previously unusable! No VID/PID;
and the wrong vendor string. Make it work, but reserve it
for older boards where the ICDI layout is wrong.
- Default the LM3748 eval board to "luminary.cfg", like the
other boards. If someone uses an external JTAG adapter, all
boards will use the same workaround (override that default).
The difference between the two FT2232 layouts is that eventually
the EVB layout will fail cleanly when asked to enable SWO trace,
but the ICDI layout will as cleanly be able to enable it. Folk
using "luminary.cfg" with Rev B boards won't see anything going
wrong until SWO support is (someday) added.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/NEWS b/NEWS
index e3e813c..ba7e0e6 100644
--- a/NEWS
+++ b/NEWS
@@ -52,6 +52,9 @@ Board, Target, and Interface Configuration Scripts:
ARM9
- ETM and ETB hookup for iMX2* targets
Add $HOME/.openocd to the search path.
+ Handle Rev C of LM3S811 eval boards.
+ - use "luminary-lm3s811.cfg" for older boards
+ - use "luminary.cfg" for RevC and newer
Core Jim/TCL Scripting:
New 'usage' command to provide terse command help.
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 154ecbc..02caf5b 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -288,10 +288,17 @@ chips are starting to become available in JTAG adapters.
@* See: @url{http://www.oocdlink.com} By Joern Kaipf
@item @b{signalyzer}
@* See: @url{http://www.signalyzer.com}
-@item @b{evb_lm3s811}
-@* See: @url{http://www.luminarymicro.com} - The Stellaris LM3S811 eval board has an FTD2232C chip built in.
-@item @b{luminary_icdi}
-@* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug Interface (ICDI) Board, included in the Stellaris LM3S9B90 and LM3S9B92 Evaluation Kits.
+@item @b{Stellaris Eval Boards}
+@* See: @url{http://www.luminarymicro.com} - The Stellaris eval boards
+bundle FT2232-based JTAG and SWD support, which can be used to debug
+the Stellaris chips. Using separate JTAG adapters is optional.
+These boards can also be used as JTAG adapters to other target boards,
+disabling the Stellaris chip.
+@item @b{Luminary ICDI}
+@* See: @url{http://www.luminarymicro.com} - Luminary In-Circuit Debug
+Interface (ICDI) Boards are included in Stellaris LM3S9B90 and LM3S9B92
+Evaluation Kits. Like the non-detachable FT2232 support on the other
+Stellaris eval boards, they can be used to debug other target boards.
@item @b{olimex-jtag}
@* See: @url{http://www.olimex.com}
@item @b{flyswatter}
@@ -1962,7 +1969,12 @@ Currently valid layout @var{name} values include:
@item @b{evb_lm3s811} Luminary Micro EVB_LM3S811 as a JTAG interface,
either for the local Cortex-M3 (SRST only)
or in a passthrough mode (neither SRST nor TRST)
-@item @b{luminary_icdi} Luminary In-Circuit Debug Interface (ICDI) Board
+This layout can not support the SWO trace mechanism, and should be
+used only for older boards (before rev C).
+@item @b{luminary_icdi} This layout should be used with most Luminary
+eval boards, including Rev C LM3S811 eval boards and the eponymous
+ICDI boards, to debug either the local Cortex-M3 or in passthrough mode
+to debug some other target. It can support the SWO trace mechanism.
@item @b{flyswatter} Tin Can Tools Flyswatter
@item @b{icebear} ICEbear JTAG adapter from Section 5
@item @b{jtagkey} Amontec JTAGkey and JTAGkey-Tiny (and compatibles)
diff --git a/src/jtag/drivers/ft2232.c b/src/jtag/drivers/ft2232.c
index 831a5dc..06fc252 100644
--- a/src/jtag/drivers/ft2232.c
+++ b/src/jtag/drivers/ft2232.c
@@ -2182,6 +2182,11 @@ static int usbjtag_init(void)
}
else if (strcmp(ft2232_layout, "evb_lm3s811") == 0)
{
+ /* There are multiple revisions of LM3S811 eval boards:
+ * - Rev B (and older?) boards have no SWO trace support.
+ * - Rev C boards add ADBUS_6 DBG_ENn and BDBUS_4 SWO_EN;
+ * they should use the "luminary_icdi" layout instead.
+ */
nTRST = 0x0;
nTRSTnOE = 0x00;
nSRST = 0x20;
@@ -2191,6 +2196,9 @@ static int usbjtag_init(void)
}
else if (strcmp(ft2232_layout, "luminary_icdi") == 0)
{
+ /* Most Luminary eval boards support SWO trace output,
+ * and should use this "luminary_icdi" layout.
+ */
nTRST = 0x0;
nTRSTnOE = 0x00;
nSRST = 0x20;
diff --git a/tcl/board/ek-lm3s3748.cfg b/tcl/board/ek-lm3s3748.cfg
index 950e511..7613a0a 100644
--- a/tcl/board/ek-lm3s3748.cfg
+++ b/tcl/board/ek-lm3s3748.cfg
@@ -1,8 +1,8 @@
# Stellaris lm3s3748 Evaluation Kit
# http://www.luminarymicro.com/products/lm3s3748_usb_h_d_evaluation_kits.html
-# NOTE: to use the on-board FT2232 JTAG interface:
-# source [find interface/luminary.cfg]
+# NOTE: using the on-board FT2232 JTAG/SWD/SWO interface is optional!
+source [find interface/luminary.cfg]
source [find target/stellaris.cfg]
diff --git a/tcl/interface/luminary-icdi.cfg b/tcl/interface/luminary-icdi.cfg
index 04330a1..ec77256 100644
--- a/tcl/interface/luminary-icdi.cfg
+++ b/tcl/interface/luminary-icdi.cfg
@@ -2,6 +2,11 @@
# Luminary Micro Stellaris LM3S9B9x Evaluation Kits
# In-Circuit Debug Interface (ICDI) Board
#
+# This is a discrete FT2232 based debug board which supports ARM's
+# JTAG/SWD connectors in both backwards-compatible 20-pin format and
+# in the new-style compact 10-pin. There's also an 8-pin connector
+# with serial port support. It's included with LM3S9B9x eval boards.
+#
# http://www.luminarymicro.com/products/ek-lm3s9b90.html
# http://www.luminarymicro.com/products/ek-lm3s9b92.html
#
diff --git a/tcl/interface/luminary-lm3s811.cfg b/tcl/interface/luminary-lm3s811.cfg
index 3d4b976..4c1accd 100644
--- a/tcl/interface/luminary-lm3s811.cfg
+++ b/tcl/interface/luminary-lm3s811.cfg
@@ -3,8 +3,16 @@
#
# http://www.luminarymicro.com/products/stellaris_811_evaluation_kits.html
#
+# NOTE: this is only for boards *before* Rev C, which adds support
+# for SWO tracing with ADBUS_6 DBG_ENn and BDBUS_4 SWO_EN signals.
+# The "evb_lm3s811" layout doesn't set up those signals.
+#
+# Rev C boards work more like the other Stellaris eval boards. They
+# need to use the "luminary_icdi" layout to work correctly.
+#
interface ft2232
-ft2232_device_desc "LM3S811 Evaluation Board"
+ft2232_device_desc "Stellaris Evaluation Board"
ft2232_layout evb_lm3s811
+ft2232_vid_pid 0x0403 0xbcd9
diff --git a/tcl/interface/luminary.cfg b/tcl/interface/luminary.cfg
index c86dbb6..e94e514 100644
--- a/tcl/interface/luminary.cfg
+++ b/tcl/interface/luminary.cfg
@@ -1,11 +1,31 @@
#
-# Luminary Micro Stellaris LM3S811 Evaluation Kit
+# Luminary Micro Stellaris Evaluation Kits
#
-# http://www.luminarymicro.com/products/stellaris_811_evaluation_kits.html
+# http://www.luminarymicro.com/products/evaluation_kits.html
+#
+# There are a number of evaluation kits for Stellaris Cortex-M3 chips.
+# Currently they all bundle FT2232 based debug support. When that is
+# used (instead of an external adapter), use this config file in one
+# of these two modes:
+#
+# - Eval board debug ... debug of the Stellaris chip via port A.
+#
+# - Other board debug ... same thing, but the board acts as a debug
+# adapter for another board (using a standard ARM JTAG connector).
+# The Stellaris chip stays in reset.
+#
+# Those support both JTAG and SWD. SWD is an ARM-only two-wire debug
+# protocol; in 2009, OpenOCD does not support SWD.
+#
+# Port B of the FT2232 chip is normally used as a serial link to the
+# Stellaris chip. On most boards (but not older LM3S811 eval boards),
+# when SWD is used Port B may instead be used to read low-bandwidth
+# "SWO trace" data, including so-called "printf style" output from
+# firmware via the ITM module as well as profile data.
#
interface ft2232
ft2232_device_desc "Stellaris Evaluation Board"
-ft2232_layout evb_lm3s811
+ft2232_layout luminary_icdi
ft2232_vid_pid 0x0403 0xbcd9
commit cba1813d5c017e2d20969bb419a856fe15c5ceef
Author: Piotr Esden-Tempski <pi...@es...>
Date: Mon Dec 28 16:43:51 2009 +0100
NOR: last_addr also needs correction when checking alignment
Otherwise the new alignment checking algorithm thinks that the
address is not aligned, because it is way beyond the last sector.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/flash/nor/core.c b/src/flash/nor/core.c
index 5eb51cd..01088f3 100644
--- a/src/flash/nor/core.c
+++ b/src/flash/nor/core.c
@@ -316,6 +316,7 @@ static int flash_iterate_address_range(struct target *target,
/** @todo: handle erasures that cross into adjacent banks */
addr -= c->base;
+ last_addr -= c->base;
for (i = 0; i < c->num_sectors; i++)
{
-----------------------------------------------------------------------
Summary of changes:
NEWS | 3 +++
doc/openocd.texi | 22 +++++++++++++++++-----
src/flash/mflash.c | 4 ++--
src/flash/nand/tcl.c | 4 ++--
src/flash/nor/core.c | 1 +
src/flash/nor/stm32x.c | 5 +++++
src/flash/nor/tcl.c | 4 ++--
src/jtag/drivers/ft2232.c | 8 ++++++++
src/target/target.c | 2 +-
tcl/board/ek-lm3s3748.cfg | 4 ++--
tcl/interface/luminary-icdi.cfg | 5 +++++
tcl/interface/luminary-lm3s811.cfg | 10 +++++++++-
tcl/interface/luminary.cfg | 26 +++++++++++++++++++++++---
13 files changed, 80 insertions(+), 18 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-12-27 21:24:35
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 3ace333663628d00795fd0b5ab80c91e6025b4dc (commit)
via 155a6a2c0bacdd4752e944ffd579d441361883db (commit)
from 84dbf8ab5a2e85c9d9c9d276fba152a45a441433 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 3ace333663628d00795fd0b5ab80c91e6025b4dc
Author: David Brownell <dbr...@us...>
Date: Sun Dec 27 12:16:55 2009 -0800
create tcl/board/dm365evm.cfg
This config is only lightly tested, and doesn't work well yet;
but it's a start.
* Notably missing is PLL configuration, since each DaVinci
does that just a bit differently; and thus DDR2 setup.
* The SRST workaround needed for the goof in the CPLD's VHDL
depends on at least the not-yet-merged patch letting ARM9
(and ARM7) chips perform resets that don't use SRST.
So this isn't yet suitable for debugging U-Boot.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/tcl/board/dm365evm.cfg b/tcl/board/dm365evm.cfg
new file mode 100644
index 0000000..f8ec4e0
--- /dev/null
+++ b/tcl/board/dm365evm.cfg
@@ -0,0 +1,147 @@
+# DM365 EVM board -- Beta
+# http://focus.ti.com/docs/toolsw/folders/print/tmdxevm365.html
+# http://support.spectrumdigital.com/boards/evmdm365
+
+source [find target/ti_dm365.cfg]
+
+# NOTE: in Rev C boards, the CPLD ignores SRST from the ARM-20 JTAG
+# connector, so it doesn't affect generation of the reset signal.
+# Accordingly, resets require something else. ICEpick could do it;
+# but its docs aren't generally available.
+#
+# At this writing, newer boards aren't available ... so assume no SRST.
+# Also ICEpick docs aren't available ... so we must use watchdog reset,
+# and hope the CPU isn't wedged or in a WFI loop (either of which can
+# block access to CPU and thus watchdog registers).
+
+reset_config trst_only
+$_TARGETNAME configure -event reset-assert "davinci_wdog_reset"
+
+# SW5.1 routes CS0: NAND vs OneNAND.
+# SW4.6:4 controls AEMIF width (8 for NAND, 16 for OneNand)
+# for boot-from-flash, those must agree with SW4.3:1 settings.
+
+if { [info exists CS0MODE] } {
+ # NAND or OneNAND
+ set CS0 $CS0MODE
+} else {
+ set CS0 ""
+ echo "WARNING: CS0 configuration not known"
+ proc cs0_setup {a_emif} {}
+ proc flashprobe {} {}
+}
+
+set a_emif [dict get $dm365 a_emif]
+
+# As shipped: boot from NAND.
+if { $CS0 == "NAND" } {
+ echo "CS0 NAND"
+
+ # NAND socket has two chipselects. Default MT29F16G08FAA chip
+ # has 1GByte on each one.
+ # NOTE: "hwecc4" here presumes that you're not updating anything
+ # that needs infix layout (e.g. UBL, old U-Boot, etc)
+ nand device low davinci $_TARGETNAME 0x02000000 hwecc4 $a_emif
+ nand device high davinci $_TARGETNAME 0x02004000 hwecc4 $a_emif
+
+ proc cs0_setup {a_emif} {
+ global dm365
+
+ # 8 bit EMIF
+ davinci_pinmux $dm365 2 0x00000016
+
+ # slow/pessimistic timings
+ set nand_timings 0x40400204
+ # fast (25% faster page reads)
+ #set nand_timings 0x0400008c
+
+ # CS0 == socketed NAND (default MT29F16G08FAA, 2 GBytes)
+ mww [expr $a_emif + 0x10] $nand_timings
+
+ # NANDFCR -- CS0 has NAND
+ mww [expr $a_emif + 0x60] 0x01
+ }
+ proc flashprobe {} {
+ nand probe 0
+ nand probe 1
+ }
+
+} elseif { $CS0 == "OneNAND" } {
+ echo "CS0 OneNAND"
+
+ # No support for this OneNAND in OpenOCD (yet) or Linux ...
+ # REVISIT OneNAND timings not verified to work!
+ echo "WARNING -- OneNAND not yet tested!"
+
+ proc cs0_setup {a_emif} {
+ global dm365
+
+ # 16 bit EMIF
+ davinci_pinmux $dm365 2 0x00000055
+
+ # CS0 == OneNAND (KFG1G16U2B-DIB6, 128 KBytes)
+ mww [expr $a_emif + 0x10] 0x00000001
+
+ # ONENANDCTRL -- CS0 has OneNAND, enable sync reads
+ mww [expr $a_emif + 0x5c] 0x0441
+ }
+ proc flashprobe {} { }
+}
+
+# NOTE: disable or replace this call to dm365evm_init if you're
+# debugging new UBL/NANDboot code from SRAM.
+$_TARGETNAME configure -event reset-init { dm365evm_init }
+
+#
+# This post-reset init is called when the MMU isn't active, all IRQs
+# are disabled, etc. It should do most of what a UBL does, except for
+# loading code (like U-Boot) into DRAM and running it.
+#
+proc dm365evm_init {} {
+ global dm365
+
+ echo "Initialize DM365 EVM board"
+
+ # CLKIN = 24 MHz ... can't talk quickly to ARM yet
+ jtag_khz 1500
+
+ # FIXME -- PLL init
+
+ ########################
+ # PINMUX setup
+
+ davinci_pinmux $dm365 0 0x00fd0000
+ davinci_pinmux $dm365 1 0x00145555
+ # mux2 controls AEMIF ... 8 bit for NAND, 16 for OneNand
+ davinci_pinmux $dm365 3 0x375affff
+ davinci_pinmux $dm365 4 0x55556555
+
+ ########################
+ # PSC setup (minimal)
+
+ # DDR EMIF/13, AEMIF/14, UART0/19
+ psc_enable 13
+ psc_enable 14
+ psc_enable 19
+ psc_go
+
+ # FIXME setup DDR2 (needs PLL)
+
+ ########################
+ # ASYNC EMIF
+
+ set a_emif [dict get $dm365 a_emif]
+
+ # AWCCR
+ mww [expr $a_emif + 0x04] 0xff
+ # CS0 == NAND or OneNAND
+ cs0_setup $a_emif
+ # CS1 == CPLD
+ mww [expr $a_emif + 0x14] 0x00a00505
+
+ # FIXME setup UART0
+
+ flashprobe
+}
+
+
commit 155a6a2c0bacdd4752e944ffd579d441361883db
Author: David Brownell <dbr...@us...>
Date: Sun Dec 27 11:34:31 2009 -0800
NOR: make flash_write_unlock() pad to sector end
Resolve a regression when using newish automagic "write_image"
modes, by always padding to the end of affected sectors.
Also document some issues associated with those automagic options,
in the User's Guide and also some related code comments.
We might need similar padding at the *beginning* of some sectors,
but this is a minimalist fix for the problems which have currently
been reported (plus doc updates).
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 1c20716..154ecbc 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -3857,8 +3857,29 @@ explicitly as @option{bin} (binary), @option{ihex} (Intel hex),
The relevant flash sectors will be erased prior to programming
if the @option{erase} parameter is given. If @option{unlock} is
provided, then the flash banks are unlocked before erase and
-program. The flash bank to use is inferred from the @var{address} of
-each image segment.
+program. The flash bank to use is inferred from the address of
+each image section.
+
+@quotation Warning
+Be careful using the @option{erase} flag when the flash is holding
+data you want to preserve.
+Portions of the flash outside those described in the image's
+sections might be erased with no notice.
+@itemize
+@item
+When a section of the image being written does not fill out all the
+sectors it uses, the unwritten parts of those sectors are necessarily
+also erased, because sectors can't be partially erased.
+@item
+Data stored in sector "holes" between image sections are also affected.
+For example, "@command{flash write_image erase ...}" of an image with
+one byte at the beginning of a flash bank and one byte at the end
+erases the entire bank -- not just the two sectors being written.
+@end itemize
+Also, when flash protection is important, you must re-apply it after
+it has been removed by the @option{unlock} flag.
+@end quotation
+
@end deffn
@section Other Flash commands
diff --git a/src/flash/nor/core.c b/src/flash/nor/core.c
index fe5372b..5eb51cd 100644
--- a/src/flash/nor/core.c
+++ b/src/flash/nor/core.c
@@ -439,9 +439,26 @@ int flash_write_unlock(struct target *target, struct image *image,
{
if (image->sections[section_last + 1].base_address < (run_address + run_size))
{
- LOG_DEBUG("section %d out of order(very slightly surprising, but supported)", section_last + 1);
+ LOG_DEBUG("section %d out of order "
+ "(surprising, but supported)",
+ section_last + 1);
+ /* REVISIT this can break with autoerase ...
+ * clobbering data after it's written.
+ */
break;
}
+
+ /* REVISIT This needlessly touches sectors BETWEEN the
+ * sections it's writing. Without auto erase, it just
+ * writes ones; unlikely to destroy data.
+ *
+ * With auto erase enabled, data in those sectors will
+ * be needlessly destroyed; and some of the limited
+ * number of flash erase cycles will be wasted...
+ *
+ * In both cases, the extra writes slow things down.
+ */
+
/* if we have multiple sections within our image, flash programming could fail due to alignment issues
* attempt to rebuild a consecutive buffer for the flash loader */
pad_bytes = (image->sections[section_last + 1].base_address) - (run_address + run_size);
@@ -450,7 +467,6 @@ int flash_write_unlock(struct target *target, struct image *image,
padding[section_last] = pad_bytes;
run_size += image->sections[++section_last].size;
run_size += pad_bytes;
- padding[section_last] = 0;
LOG_INFO("Padding image section %d with %d bytes", section_last-1, pad_bytes);
}
@@ -458,11 +474,35 @@ int flash_write_unlock(struct target *target, struct image *image,
/* fit the run into bank constraints */
if (run_address + run_size - 1 > c->base + c->size - 1)
{
+ /* REVISIT isn't this superfluous, given the while()
+ * loop conditions above??
+ */
LOG_WARNING("writing %d bytes only - as image section is %d bytes and bank is only %d bytes", \
(int)(c->base + c->size - run_address), (int)(run_size), (int)(c->size));
run_size = c->base + c->size - run_address;
}
+ /* If we're applying any sector automagic, then pad this
+ * (maybe-combined) segment to the end of its last sector.
+ */
+ if (unlock || erase) {
+ int sector;
+ uint32_t offset_start = run_address - c->base;
+ uint32_t offset_end = offset_start + run_size;
+ uint32_t end = offset_end, delta;
+
+ for (sector = 0; sector < c->num_sectors; sector++) {
+ end = c->sectors[sector].offset
+ + c->sectors[sector].size;
+ if (offset_end <= end)
+ break;
+ }
+
+ delta = end - offset_end;
+ padding[section_last] += delta;
+ run_size += delta;
+ }
+
/* allocate buffer */
buffer = malloc(run_size);
buffer_size = 0;
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 25 ++++++++-
src/flash/nor/core.c | 44 ++++++++++++++-
tcl/board/dm365evm.cfg | 147 ++++++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 212 insertions(+), 4 deletions(-)
create mode 100644 tcl/board/dm365evm.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-12-27 00:05:38
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 84dbf8ab5a2e85c9d9c9d276fba152a45a441433 (commit)
from 900d745567809d9f0163cfde5832b10ec0581a0e (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 84dbf8ab5a2e85c9d9c9d276fba152a45a441433
Author: Catalin Patulea <ca...@vv...>
Date: Sat Dec 26 15:05:06 2009 -0800
Driver for USB-JTAG, Altera USB-Blaster and compatibles
The 10-pin JTAG layout used with these adapters is used by
a variety of platforms including AVR.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/NEWS b/NEWS
index 173d06a..e3e813c 100644
--- a/NEWS
+++ b/NEWS
@@ -5,6 +5,7 @@ and other issues not mentioned here.
JTAG Layer:
Support KT-Link JTAG adapter.
+ Support USB-JTAG, Altera USB-Blaster and compatibles.
Boundary Scan:
Target Layer:
diff --git a/configure.in b/configure.in
index 7ce7955..21edba9 100644
--- a/configure.in
+++ b/configure.in
@@ -392,6 +392,14 @@ AC_ARG_ENABLE(ft2232_ftd2xx,
AS_HELP_STRING([--enable-ft2232_ftd2xx], [Enable building support for FT2232 based devices using the FTD2XX driver from ftdichip.com]),
[build_ft2232_ftd2xx=$enableval], [build_ft2232_ftd2xx=no])
+AC_ARG_ENABLE(usb_blaster_libftdi,
+ AS_HELP_STRING([--enable-usb_blaster_libftdi], [Enable building support for the Altera USB-Blaster using the libftdi driver, opensource alternate of FTD2XX]),
+ [build_usb_blaster_libftdi=$enableval], [build_usb_blaster_libftdi=no])
+
+AC_ARG_ENABLE(usb_blaster_ftd2xx,
+ AS_HELP_STRING([--enable-usb_blaster_ftd2xx], [Enable building support for the Altera USB-Blaster using the FTD2XX driver from ftdichip.com]),
+ [build_usb_blaster_ftd2xx=$enableval], [build_usb_blaster_ftd2xx=no])
+
AC_ARG_ENABLE(amtjtagaccel,
AS_HELP_STRING([--enable-amtjtagaccel], [Enable building the Amontec JTAG-Accelerator driver]),
[build_amtjtagaccel=$enableval], [build_amtjtagaccel=no])
@@ -651,6 +659,20 @@ else
AC_DEFINE(BUILD_FT2232_FTD2XX, 0, [0 if you don't want ftd2xx ft2232.])
fi
+if test $build_usb_blaster_libftdi = yes; then
+ build_bitbang=yes
+ AC_DEFINE(BUILD_USB_BLASTER_LIBFTDI, 1, [1 if you want libftdi usb_blaster.])
+else
+ AC_DEFINE(BUILD_USB_BLASTER_LIBFTDI, 0, [0 if you don't want libftdi usb_blaster.])
+fi
+
+if test $build_usb_blaster_ftd2xx = yes; then
+ build_bitbang=yes
+ AC_DEFINE(BUILD_USB_BLASTER_FTD2XX, 1, [1 if you want ftd2xx usb_blaster.])
+else
+ AC_DEFINE(BUILD_USB_BLASTER_FTD2XX, 0, [0 if you don't want ftd2xx usb_blaster.])
+fi
+
if test $build_amtjtagaccel = yes; then
AC_DEFINE(BUILD_AMTJTAGACCEL, 1, [1 if you want the Amontec JTAG-Accelerator driver.])
else
@@ -727,7 +749,7 @@ then
AC_MSG_ERROR([The option: with_ftd2xx_linux_tardir is for LINUX only.])
fi
-if test $build_ft2232_ftd2xx = yes -o $build_presto_ftd2xx = yes ; then
+if test $build_ft2232_ftd2xx = yes -o $build_presto_ftd2xx = yes -o $build_usb_blaster_ftd2xx = yes ; then
AC_MSG_CHECKING([for ftd2xx.lib exists (win32)])
# if we are given a zipdir...
@@ -1001,6 +1023,8 @@ AM_CONDITIONAL(AT91RM9200, test $build_at91rm9200 = yes)
AM_CONDITIONAL(BITBANG, test $build_bitbang = yes)
AM_CONDITIONAL(FT2232_LIBFTDI, test $build_ft2232_libftdi = yes)
AM_CONDITIONAL(FT2232_DRIVER, test $build_ft2232_ftd2xx = yes -o $build_ft2232_libftdi = yes)
+AM_CONDITIONAL(USB_BLASTER_LIBFTDI, test $build_usb_blaster_libftdi = yes)
+AM_CONDITIONAL(USB_BLASTER_DRIVER, test $build_usb_blaster_ftd2xx = yes -o $build_usb_blaster_libftdi = yes)
AM_CONDITIONAL(AMTJTAGACCEL, test $build_amtjtagaccel = yes)
AM_CONDITIONAL(GW16012, test $build_gw16012 = yes)
AM_CONDITIONAL(PRESTO_LIBFTDI, test $build_presto_libftdi = yes)
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 013a31a..1c20716 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -310,6 +310,25 @@ chips are starting to become available in JTAG adapters.
@* Link @url{http://www.hitex.com/index.php?id=cortino}
@end itemize
+@section USB-JTAG / Altera USB-Blaster compatibles
+
+These devices also show up as FTDI devices, but are not
+protocol-compatible with the FT2232 devices. They are, however,
+protocol-compatible among themselves. USB-JTAG devices typically consist
+of a FT245 followed by a CPLD that understands a particular protocol,
+or emulate this protocol using some other hardware.
+
+They may appear under different USB VID/PID depending on the particular
+product. The driver can be configured to search for any VID/PID pair
+(see the section on driver commands).
+
+@itemize
+@item @b{USB-JTAG} Kolja Waschk's USB Blaster-compatible adapter
+@* Link: @url{http://www.ixo.de/info/usb_jtag/}
+@item @b{Altera USB-Blaster}
+@* Link: @url{http://www.altera.com/literature/ug/ug_usb_blstr.pdf}
+@end itemize
+
@section USB JLINK based
There are several OEM versions of the Segger @b{JLINK} adapter. It is
an example of a micro controller based JTAG adapter, it uses an
@@ -1989,6 +2008,46 @@ ft2232_vid_pid 0x0403 0xbdc8
@end example
@end deffn
+@deffn {Interface Driver} {usb_blaster}
+USB JTAG/USB-Blaster compatibles over one of the userspace libraries
+for FTDI chips. These interfaces have several commands, used to
+configure the driver before initializing the JTAG scan chain:
+
+@deffn {Config Command} {usb_blaster_device_desc} description
+Provides the USB device description (the @emph{iProduct string})
+of the FTDI FT245 device. If not
+specified, the FTDI default value is used. This setting is only valid
+if compiled with FTD2XX support.
+@end deffn
+
+@deffn {Config Command} {usb_blaster_vid_pid} vid pid
+The vendor ID and product ID of the FTDI FT245 device. If not specified,
+default values are used.
+Currently, only one @var{vid}, @var{pid} pair may be given, e.g. for
+Altera USB-Blaster (default):
+@example
+ft2232_vid_pid 0x09FB 0x6001
+@end example
+The following VID/PID is for Kolja Waschk's USB JTAG:
+@example
+ft2232_vid_pid 0x16C0 0x06AD
+@end example
+@end deffn
+
+@deffn {Command} {usb_blaster} (@option{pin6}|@option{pin8}) (@option{0}|@option{1})
+Sets the state of the unused GPIO pins on USB-Blasters (pins 6 and 8 on the
+female JTAG header). These pins can be used as SRST and/or TRST provided the
+appropriate connections are made on the target board.
+
+For example, to use pin 6 as SRST (as with an AVR board):
+@example
+$_TARGETNAME configure -event reset-assert \
+ "usb_blaster pin6 1; wait 1; usb_blaster pin6 0"
+@end example
+@end deffn
+
+@end deffn
+
@deffn {Interface Driver} {gw16012}
Gateworks GW16012 JTAG programmer.
This has one driver-specific command:
diff --git a/src/Makefile.am b/src/Makefile.am
index f60feac..a566b4d 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -60,12 +60,16 @@ endif
if FT2232_LIBFTDI
FTDI2232LIB = -lftdi -lusb
else
+if USB_BLASTER_LIBFTDI
+FTDI2232LIB = -lftdi -lusb
+else
if PRESTO_LIBFTDI
FTDI2232LIB = -lftdi -lusb
else
FTDI2232LIB =
endif
endif
+endif
if USBPROG
LIBUSB = -lusb
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index 8ee5ac5..d6113c6 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -28,6 +28,9 @@ endif
if FT2232_DRIVER
DRIVERFILES += ft2232.c
endif
+if USB_BLASTER_DRIVER
+DRIVERFILES += usb_blaster.c
+endif
if AMTJTAGACCEL
DRIVERFILES += amt_jtagaccel.c
endif
diff --git a/src/jtag/drivers/usb_blaster.c b/src/jtag/drivers/usb_blaster.c
new file mode 100644
index 0000000..3703323
--- /dev/null
+++ b/src/jtag/drivers/usb_blaster.c
@@ -0,0 +1,589 @@
+/***************************************************************************
+ * Driver for USB-JTAG, Altera USB-Blaster and compatibles *
+ * Original code from Kolja Waschk's USB-JTAG project *
+ * (http://www.ixo.de/info/usb_jtag/). *
+ * Some updates by Anthony Liu (2006). *
+ * Minor updates and cleanup by Catalin Patulea (2009). *
+ * *
+ * Copyright (C) 2009 Catalin Patulea *
+ * ca...@vv... *
+ * *
+ * Copyright (C) 2006 Kolja Waschk *
+ * us...@ix... *
+ * *
+ * Based on ft2232.c and bitbang.c, *
+ * Copyright (C) 2004,2006 by Dominic Rath *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+
+/*
+ * The following information is originally from Kolja Waschk's USB-JTAG,
+ * where it was obtained by reverse engineering an Altera USB-Blaster.
+ * See http://www.ixo.de/info/usb_jtag/ for USB-Blaster block diagram and
+ * usb_jtag-20080705-1200.zip#usb_jtag/host/openocd for protocol.
+ *
+ * The same information is also on the UrJTAG mediawiki, with some additional
+ * notes on bits marked as "unknown" by usb_jtag.
+ * (http://sourceforge.net/apps/mediawiki/urjtag/index.php?
+ * title=Cable_Altera_USB-Blaster)
+ *
+ * USB-JTAG, Altera USB-Blaster and compatibles are typically implemented as
+ * an FTDIChip FT245 followed by a CPLD which handles a two-mode protocol:
+ *
+ * _________
+ * | |
+ * | AT93C46 |
+ * |_________|
+ * __|__________ _________
+ * | | | |
+ * USB__| FTDI 245BM |__| EPM7064 |__JTAG (B_TDO,B_TDI,B_TMS,B_TCK)
+ * |_____________| |_________|
+ * __|__________ _|___________
+ * | | | |
+ * | 6 MHz XTAL | | 24 MHz Osc. |
+ * |_____________| |_____________|
+ *
+ * Protocol details are given in the code below.
+ *
+ * It is also possible to emulate this configuration using a single-chip USB
+ * controller like the Cypress FX2 (again, see usb_jtag for details).
+ */
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#if IS_CYGWIN == 1
+#include "windows.h"
+#undef LOG_ERROR
+#endif
+
+/* project specific includes */
+#include <jtag/interface.h>
+#include <jtag/commands.h>
+#include <helper/time_support.h>
+
+/* system includes */
+#include <string.h>
+#include <stdlib.h>
+#include <unistd.h>
+
+#include "bitbang.h"
+
+#if (BUILD_USB_BLASTER_FTD2XX == 1 && BUILD_USB_BLASTER_LIBFTDI == 1)
+#error "BUILD_USB_BLASTER_FTD2XX && BUILD_USB_BLASTER_LIBFTDI "
+ "are mutually exclusive"
+#elif (BUILD_USB_BLASTER_FTD2XX != 1 && BUILD_USB_BLASTER_LIBFTDI != 1)
+#error "BUILD_USB_BLASTER_FTD2XX || BUILD_USB_BLASTER_LIBFTDI must be chosen"
+#endif
+
+/* USB_BLASTER access library includes */
+#if BUILD_USB_BLASTER_FTD2XX == 1
+#include <ftd2xx.h>
+#elif BUILD_USB_BLASTER_LIBFTDI == 1
+#include <ftdi.h>
+#endif
+
+#include <sys/time.h>
+#include <time.h>
+
+static char *usb_blaster_device_desc;
+static uint16_t usb_blaster_vid = 0x09fb; /* Altera */
+static uint16_t usb_blaster_pid = 0x6001; /* USB-Blaster */
+
+/* last output byte in simple bit banging mode */
+static uint8_t out_value;
+
+#if BUILD_USB_BLASTER_FTD2XX == 1
+static FT_HANDLE ftdih;
+#elif BUILD_USB_BLASTER_LIBFTDI == 1
+static struct ftdi_context ftdic;
+#endif
+
+static int usb_blaster_buf_write(
+ uint8_t *buf, int size, uint32_t *bytes_written)
+{
+#if BUILD_USB_BLASTER_FTD2XX == 1
+ FT_STATUS status;
+ DWORD dw_bytes_written;
+
+#ifdef _DEBUG_JTAG_IO_
+ LOG_DEBUG("usb_blaster_buf_write %02X (%d)\n", buf[0], size);
+#endif
+ status = FT_Write(ftdih, buf, size, &dw_bytes_written);
+ if (status != FT_OK)
+ {
+ *bytes_written = dw_bytes_written;
+ LOG_ERROR("FT_Write returned: %lu", status);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ *bytes_written = dw_bytes_written;
+ return ERROR_OK;
+#elif BUILD_USB_BLASTER_LIBFTDI == 1
+ int retval;
+#ifdef _DEBUG_JTAG_IO_
+ LOG_DEBUG("usb_blaster_buf_write %02X (%d)\n", buf[0], size);
+#endif
+ retval = ftdi_write_data(&ftdic, buf, size);
+ if (retval < 0)
+ {
+ *bytes_written = 0;
+ LOG_ERROR("ftdi_write_data: %s", ftdi_get_error_string(&ftdic));
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ *bytes_written = retval;
+ return ERROR_OK;
+#endif
+}
+
+static int
+usb_blaster_buf_read(uint8_t *buf, unsigned size, uint32_t *bytes_read)
+{
+#if BUILD_USB_BLASTER_FTD2XX == 1
+ DWORD dw_bytes_read;
+ FT_STATUS status;
+
+ status = FT_Read(ftdih, buf, size, &dw_bytes_read);
+ if (status != FT_OK)
+ {
+ *bytes_read = dw_bytes_read;
+ LOG_ERROR("FT_Read returned: %lu", status);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+#ifdef _DEBUG_JTAG_IO_
+ LOG_DEBUG("usb_blaster_buf_read %02X (%lu)\n", buf[0], dw_bytes_read);
+#endif
+ *bytes_read = dw_bytes_read;
+ return ERROR_OK;
+
+#elif BUILD_USB_BLASTER_LIBFTDI == 1
+ int retval;
+ int timeout = 100;
+
+ *bytes_read = 0;
+ while ((*bytes_read < size) && timeout--)
+ {
+ retval = ftdi_read_data(&ftdic, buf + *bytes_read,
+ size - *bytes_read);
+ if (retval < 0)
+ {
+ *bytes_read = 0;
+ LOG_ERROR("ftdi_read_data: %s",
+ ftdi_get_error_string(&ftdic));
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ *bytes_read += retval;
+ }
+#ifdef _DEBUG_JTAG_IO_
+ LOG_DEBUG("usb_blaster_buf_read %02X (%d)\n", buf[0], *bytes_read);
+#endif
+ return ERROR_OK;
+#endif
+}
+
+/* The following code doesn't fully utilize the possibilities of the
+ * USB-Blaster. It writes one byte per JTAG pin state change at a time; it
+ * doesn't even try to buffer data up to the maximum packet size of 64 bytes.
+ *
+ * Actually, the USB-Blaster offers a byte-shift mode to transmit up to 504 data
+ * bits (bidirectional) in a single USB packet. A header byte has to be sent as
+ * the first byte in a packet with the following meaning:
+ *
+ * Bit 7 (0x80): Must be set to indicate byte-shift mode.
+ * Bit 6 (0x40): If set, the USB-Blaster will also read data, not just write.
+ * Bit 5..0: Define the number N of following bytes
+ *
+ * All N following bytes will then be clocked out serially on TDI. If Bit 6 was
+ * set, it will afterwards return N bytes with TDO data read while clocking out
+ * the TDI data. LSB of the first byte after the header byte will appear first
+ * on TDI.
+ */
+
+/* Simple bit banging mode:
+ *
+ * Bit 7 (0x80): Must be zero (see byte-shift mode above)
+ * Bit 6 (0x40): If set, you will receive a byte indicating the state of TDO
+ * in return.
+ * Bit 5 (0x20): Output Enable/LED.
+ * Bit 4 (0x10): TDI Output.
+ * Bit 3 (0x08): nCS Output (not used in JTAG mode).
+ * Bit 2 (0x04): nCE Output (not used in JTAG mode).
+ * Bit 1 (0x02): TMS Output.
+ * Bit 0 (0x01): TCK Output.
+ *
+ * For transmitting a single data bit, you need to write two bytes. Up to 64
+ * bytes can be combined in a single USB packet (but this is not done in the
+ * code below). It isn't possible to read a data without transmitting data.
+ */
+
+#define TCK (1 << 0)
+#define TMS (1 << 1)
+#define NCE (1 << 2)
+#define NCS (1 << 3)
+#define TDI (1 << 4)
+#define LED (1 << 5)
+#define READ (1 << 6)
+#define SHMODE (1 << 7)
+#define OTHERS ((1 << 2) | (1 << 3) | (1 << 5))
+
+#define READ_TDO (1 << 0)
+
+static void usb_blaster_write_data(void)
+{
+ uint32_t bytes_written;
+ usb_blaster_buf_write(&out_value, 1, &bytes_written);
+}
+
+static int usb_blaster_read_data(void)
+{
+ int status;
+ uint8_t buf[1];
+ uint32_t bytes_read;
+
+ out_value |= READ;
+ usb_blaster_write_data();
+ out_value &= ~READ;
+
+ status = usb_blaster_buf_read(buf, 1, &bytes_read);
+ if (status < 0)
+ return 0;
+
+ return !!(buf[0] & READ_TDO);
+}
+
+static void usb_blaster_write(int tck, int tms, int tdi)
+{
+#ifdef _DEBUG_JTAG_IO_
+ LOG_DEBUG("---- usb_blaster_write(%d,%d,%d)\n", tck, tms, tdi);
+#endif
+ out_value &= ~(TCK | TMS | TDI);
+ if (tck)
+ out_value |= TCK;
+ if (tms)
+ out_value |= TMS;
+ if (tdi)
+ out_value |= TDI;
+
+ usb_blaster_write_data();
+}
+
+static int usb_blaster_speed(int speed)
+{
+#if BUILD_USB_BLASTER_FTD2XX == 1
+ LOG_DEBUG("TODO: usb_blaster_speed() isn't implemented for libftd2xx!");
+#elif BUILD_USB_BLASTER_LIBFTDI == 1
+ LOG_DEBUG("TODO: usb_blaster_speed() isn't optimally implemented!");
+
+ /* TODO: libftdi's ftdi_set_baudrate chokes on high rates, use lowlevel
+ * usb function instead! And additionally allow user to throttle.
+ */
+ if (ftdi_set_baudrate(&ftdic, 3000000 / 4) < 0)
+ {
+ LOG_ERROR("Can't set baud rate to max: %s",
+ ftdi_get_error_string(&ftdic));
+ return ERROR_JTAG_DEVICE_ERROR;
+ };
+#endif
+
+ return ERROR_OK;
+}
+
+static void usb_blaster_reset(int trst, int srst)
+{
+ LOG_DEBUG("TODO: usb_blaster_reset(%d,%d) isn't implemented!",
+ trst, srst);
+}
+
+static struct bitbang_interface usb_blaster_bitbang = {
+ .read = usb_blaster_read_data,
+ .write = usb_blaster_write,
+ .reset = usb_blaster_reset,
+};
+
+static int usb_blaster_init(void)
+{
+ uint8_t latency_timer;
+
+#if BUILD_USB_BLASTER_FTD2XX == 1
+ FT_STATUS status;
+#endif
+
+#if BUILD_USB_BLASTER_FTD2XX == 1
+ LOG_DEBUG("'usb_blaster' interface using FTD2XX");
+#elif BUILD_USB_BLASTER_LIBFTDI == 1
+ LOG_DEBUG("'usb_blaster' interface using libftdi");
+#endif
+
+#if BUILD_USB_BLASTER_FTD2XX == 1
+ /* Open by device description */
+ if (usb_blaster_device_desc == NULL)
+ {
+ LOG_WARNING("no usb_blaster device description specified, "
+ "using default 'USB-Blaster'");
+ usb_blaster_device_desc = "USB-Blaster";
+ }
+
+#if IS_WIN32 == 0
+ /* Add non-standard Vid/Pid to the linux driver */
+ status = FT_SetVIDPID(usb_blaster_vid, usb_blaster_pid);
+ if (status != FT_OK)
+ {
+ LOG_WARNING("couldn't add %4.4x:%4.4x",
+ usb_blaster_vid, usb_blaster_pid);
+ }
+#endif
+
+ status = FT_OpenEx(usb_blaster_device_desc, FT_OPEN_BY_DESCRIPTION,
+ &ftdih);
+ if (status != FT_OK)
+ {
+ DWORD num_devices;
+
+ LOG_ERROR("unable to open ftdi device: %lu", status);
+ status = FT_ListDevices(&num_devices, NULL,
+ FT_LIST_NUMBER_ONLY);
+ if (status == FT_OK)
+ {
+ char **desc_array = malloc(sizeof(char *)
+ * (num_devices + 1));
+ unsigned int i;
+
+ for (i = 0; i < num_devices; i++)
+ desc_array[i] = malloc(64);
+ desc_array[num_devices] = NULL;
+
+ status = FT_ListDevices(desc_array, &num_devices,
+ FT_LIST_ALL | FT_OPEN_BY_DESCRIPTION);
+
+ if (status == FT_OK)
+ {
+ LOG_ERROR("ListDevices: %lu\n", num_devices);
+ for (i = 0; i < num_devices; i++)
+ LOG_ERROR("%i: %s", i, desc_array[i]);
+ }
+
+ for (i = 0; i < num_devices; i++)
+ free(desc_array[i]);
+ free(desc_array);
+ }
+ else
+ {
+ printf("ListDevices: NONE\n");
+ }
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ status = FT_SetLatencyTimer(ftdih, 2);
+ if (status != FT_OK)
+ {
+ LOG_ERROR("unable to set latency timer: %lu", status);
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ status = FT_GetLatencyTimer(ftdih, &latency_timer);
+ if (status != FT_OK)
+ {
+ LOG_ERROR("unable to get latency timer: %lu", status);
+ return ERROR_JTAG_INIT_FAILED;
+ }
+ LOG_DEBUG("current latency timer: %i", latency_timer);
+
+ status = FT_SetBitMode(ftdih, 0x00, 0);
+ if (status != FT_OK)
+ {
+ LOG_ERROR("unable to disable bit i/o mode: %lu", status);
+ return ERROR_JTAG_INIT_FAILED;
+ }
+#elif BUILD_USB_BLASTER_LIBFTDI == 1
+ if (ftdi_init(&ftdic) < 0)
+ return ERROR_JTAG_INIT_FAILED;
+
+ /* context, vendor id, product id */
+ if (ftdi_usb_open(&ftdic, usb_blaster_vid, usb_blaster_pid) < 0)
+ {
+ LOG_ERROR("unable to open ftdi device: %s", ftdic.error_str);
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ if (ftdi_usb_reset(&ftdic) < 0)
+ {
+ LOG_ERROR("unable to reset ftdi device");
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ if (ftdi_set_latency_timer(&ftdic, 2) < 0)
+ {
+ LOG_ERROR("unable to set latency timer");
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ if (ftdi_get_latency_timer(&ftdic, &latency_timer) < 0)
+ {
+ LOG_ERROR("unable to get latency timer");
+ return ERROR_JTAG_INIT_FAILED;
+ }
+ LOG_DEBUG("current latency timer: %u", latency_timer);
+
+ ftdi_disable_bitbang(&ftdic);
+#endif
+
+ bitbang_interface = &usb_blaster_bitbang;
+
+ usb_blaster_speed(jtag_get_speed());
+
+#if 0
+#if BUILD_USB_BLASTER_FTD2XX == 1
+ if ((status = FT_Purge(ftdih, FT_PURGE_RX | FT_PURGE_TX)) != FT_OK)
+ {
+ LOG_ERROR("error purging ftd2xx device: %i", status);
+ return ERROR_JTAG_INIT_FAILED;
+ }
+#elif BUILD_USB_BLASTER_LIBFTDI == 1
+ if (ftdi_usb_purge_buffers(&ftdic) < 0)
+ {
+ LOG_ERROR("ftdi_purge_buffers: %s", ftdic.error_str);
+ return ERROR_JTAG_INIT_FAILED;
+ }
+#endif
+#endif
+
+ return ERROR_OK;
+}
+
+static int usb_blaster_quit(void)
+{
+#if BUILD_USB_BLASTER_FTD2XX == 1
+ FT_STATUS status;
+
+ status = FT_Close(ftdih);
+#elif BUILD_USB_BLASTER_LIBFTDI == 1
+ ftdi_usb_close(&ftdic);
+ ftdi_deinit(&ftdic);
+#endif
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(usb_blaster_handle_device_desc_command)
+{
+ if (CMD_ARGC == 1)
+ usb_blaster_device_desc = strdup(CMD_ARGV[0]);
+ else
+ LOG_ERROR("require exactly one argument to "
+ "usb_blaster_device_desc <description>");
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(usb_blaster_handle_vid_pid_command)
+{
+ if (CMD_ARGC > 2)
+ {
+ LOG_WARNING("ignoring extra IDs in ft2232_vid_pid "
+ "(maximum is 1 pair)");
+ CMD_ARGC = 2;
+ }
+ if (CMD_ARGC == 2)
+ {
+ COMMAND_PARSE_NUMBER(u16, CMD_ARGV[0], usb_blaster_vid);
+ COMMAND_PARSE_NUMBER(u16, CMD_ARGV[1], usb_blaster_pid);
+ }
+ else
+ LOG_WARNING("incomplete usb_blaster_vid_pid configuration");
+
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(usb_blaster_handle_pin_command)
+{
+ if (CMD_ARGC == 2)
+ {
+ const char * const pin_name = CMD_ARGV[0];
+ uint8_t mask;
+ unsigned int state;
+
+ if (!strcmp(pin_name, "pin6"))
+ mask = NCE;
+ else if (!strcmp(pin_name, "pin8"))
+ mask = NCS;
+ else
+ {
+ LOG_ERROR("%s: pin name must be \"pin6\" or \"pin8\"",
+ CMD_NAME);
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], state);
+ if (state == 0)
+ {
+ out_value &= ~mask;
+ usb_blaster_write_data();
+ }
+ else if (state == 1)
+ {
+ out_value |= mask;
+ usb_blaster_write_data();
+ }
+ else
+ {
+ LOG_ERROR("%s: pin state must be 0 or 1", CMD_NAME);
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ return ERROR_OK;
+ }
+ else
+ {
+ LOG_ERROR("%s takes exactly two arguments", CMD_NAME);
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+}
+
+static const struct command_registration usb_blaster_command_handlers[] = {
+ {
+ .name = "usb_blaster_device_desc",
+ .handler = usb_blaster_handle_device_desc_command,
+ .mode = COMMAND_CONFIG,
+ .help = "set the USB device description of the USB-Blaster",
+ .usage = "description-string",
+ },
+ {
+ .name = "usb_blaster_vid_pid",
+ .handler = usb_blaster_handle_vid_pid_command,
+ .mode = COMMAND_CONFIG,
+ .help = "the vendor ID and product ID of the USB-Blaster",
+ .usage = "vid pid",
+ },
+ {
+ .name = "usb_blaster",
+ .handler = usb_blaster_handle_pin_command,
+ .mode = COMMAND_ANY,
+ .help = "set pin state for the unused GPIO pins",
+ .usage = "(pin6|pin8) (0|1)",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+struct jtag_interface usb_blaster_interface = {
+ .name = "usb_blaster",
+ .commands = usb_blaster_command_handlers,
+
+ .execute_queue = bitbang_execute_queue,
+
+ .speed = usb_blaster_speed,
+ .init = usb_blaster_init,
+ .quit = usb_blaster_quit,
+};
diff --git a/src/jtag/interfaces.c b/src/jtag/interfaces.c
index 643e111..f6d8219 100644
--- a/src/jtag/interfaces.c
+++ b/src/jtag/interfaces.c
@@ -58,6 +58,9 @@ extern struct jtag_interface ft2232_interface;
#if BUILD_FT2232_LIBFTDI == 1
extern struct jtag_interface ft2232_interface;
#endif
+#if BUILD_USB_BLASTER_LIBFTDI == 1 || BUILD_USB_BLASTER_FTD2XX == 1
+extern struct jtag_interface usb_blaster_interface;
+#endif
#if BUILD_AMTJTAGACCEL == 1
extern struct jtag_interface amt_jtagaccel_interface;
#endif
@@ -115,6 +118,9 @@ struct jtag_interface *jtag_interfaces[] = {
#if BUILD_FT2232_LIBFTDI == 1
&ft2232_interface,
#endif
+#if BUILD_USB_BLASTER_LIBFTDI == 1 || BUILD_USB_BLASTER_FTD2XX == 1
+ &usb_blaster_interface,
+#endif
#if BUILD_AMTJTAGACCEL == 1
&amt_jtagaccel_interface,
#endif
diff --git a/tcl/interface/altera-usb-blaster.cfg b/tcl/interface/altera-usb-blaster.cfg
new file mode 100644
index 0000000..ae21465
--- /dev/null
+++ b/tcl/interface/altera-usb-blaster.cfg
@@ -0,0 +1,11 @@
+#
+# Altera USB-Blaster
+#
+# http://www.altera.com/literature/ug/ug_usb_blstr.pdf
+#
+
+interface usb_blaster
+# These are already the defaults.
+# usb_blaster_vid_pid 0x09FB 0x6001
+# usb_blaster_device_desc "USB-Blaster"
+jtag_khz 3000
diff --git a/tcl/interface/usb-jtag.cfg b/tcl/interface/usb-jtag.cfg
new file mode 100644
index 0000000..b81028d
--- /dev/null
+++ b/tcl/interface/usb-jtag.cfg
@@ -0,0 +1,11 @@
+#
+# Kolja Waschk's USB-JTAG
+#
+# http://www.ixo.de/info/usb_jtag/
+#
+
+interface usb_blaster
+usb_blaster_vid_pid 0x16C0 0x06AD
+usb_blaster_device_desc "USB-JTAG-IF"
+jtag_khz 3000
+
-----------------------------------------------------------------------
Summary of changes:
NEWS | 1 +
configure.in | 26 ++-
doc/openocd.texi | 59 ++++
src/Makefile.am | 4 +
src/jtag/drivers/Makefile.am | 3 +
src/jtag/drivers/usb_blaster.c | 589 ++++++++++++++++++++++++++++++++++
src/jtag/interfaces.c | 6 +
tcl/interface/altera-usb-blaster.cfg | 11 +
tcl/interface/usb-jtag.cfg | 11 +
9 files changed, 709 insertions(+), 1 deletions(-)
create mode 100644 src/jtag/drivers/usb_blaster.c
create mode 100644 tcl/interface/altera-usb-blaster.cfg
create mode 100644 tcl/interface/usb-jtag.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-12-26 22:09:36
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 900d745567809d9f0163cfde5832b10ec0581a0e (commit)
from 3a84436afb8e1deddffac079573325c6ec3463df (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 900d745567809d9f0163cfde5832b10ec0581a0e
Author: Dean Glazeski <dn...@gm...>
Date: Wed Dec 9 12:51:52 2009 -0600
Olimex SAM9-L9260 board configuration update.
This updates the board configuration for the SAM9-L9260 board with the
configuration for the on-board NAND and dataflash. Included are commands
for configuring the AT91SAM9 NAND flash driver.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/tcl/board/olimex_sam9_l9260.cfg b/tcl/board/olimex_sam9_l9260.cfg
index 5c4714e..7c4b2cc 100644
--- a/tcl/board/olimex_sam9_l9260.cfg
+++ b/tcl/board/olimex_sam9_l9260.cfg
@@ -35,6 +35,7 @@ $_TARGETNAME configure -event reset-init {
##
# Clock configuration for 99.328 MHz main clock.
##
+ puts "Setting up clock"
mww 0xfffffc20 0x00004001 # CKGR_MOR : enable main oscillator, 512 slow clock startup
sleep 20 # wait 20 ms (need 15.6 ms for startup)
mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator (18.432 MHz)
@@ -53,6 +54,7 @@ $_TARGETNAME configure -event reset-init {
##
# SDRAM configuration for 2 x Samsung K4S561632J-UC75, 4M x 16Bit x 4 Banks.
##
+ puts "Configuring SDRAM"
mww 0xfffff870 0xffff0000 # PIOC_ASR : select peripheral function for D15..D31
mww 0xfffff804 0xffff0000 # PIOC_PDR : disable PIO function for D15..D31
@@ -86,4 +88,54 @@ $_TARGETNAME configure -event reset-init {
mww 0x20000000 0
mww 0xffffea04 0x2b6 # SDRAMC_TR : set refresh timer count to 7 us
+
+ ##
+ # NAND Flash Configuration for 1 x Samsung K9F4G08U0M, 512M x 8Bit.
+ ##
+ puts "Configuring NAND flash"
+ mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock
+ mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
+ mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14
+ mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
+ mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
+ mww 0xfffff864 0x00002000 ;# PIOC_PUER : enable pull-up on 13
+
+ mww 0xffffef1c 0x0001000A ;# EBI_CSA : assign EBI CS3 to NAND, same settings as before
+
+ mww 0xffffec30 0x00010001 ;# SMC_SETUP3 : 1 clock cycle setup for NRD and NWE
+ mww 0xffffec34 0x03030303 ;# SMC_PULSE3 : 3 clock cycle pulse for all signals
+ mww 0xffffec38 0x00050005 ;# SMC_CYCLE3 : 5 clock cycle NRD and NWE cycle
+ mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
+ # 3 TDF cycles, no optimization
+
+ mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
+ mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
+
+ nand probe at91sam9260.flash
+
+ ##
+ # Dataflash configuration for 1 x Atmel AT45DB161D, 16Mbit
+ ##
+ puts "Setting up dataflash"
+ mww 0xfffff404 0x00000807 ;# PIOA_PDR : disable PIO function for 0(SPI0_MISO), 1(SPI0_MOSI),
+ # 2(SPI0_SPCK), and 11(SPI0_NPCS1)
+ mww 0xfffff470 0x00000007 ;# PIOA_ASR : select peripheral A function for 0, 1, and 2
+ mww 0xfffff474 0x00000800 ;# PIOA_BSR : select peripheral B function for 11
+ mww 0xfffffc10 0x00001000 ;# PMC_PCER : enable SPI0 clock
+
+ mww 0xfffc8000 0x00000080 ;# SPI0_CR : software reset SPI0
+ mww 0xfffc8000 0x00000080 ;# SPI0_CR : again to be sure
+ mww 0xfffc8004 0x000F0011 ;# SPI0_MR : master mode with nothing selected
+
+ mww 0xfffc8034 0x011a0302 ;# SPI0_CSR1 : capture on leading edge, 8-bits/tx. 33MHz baud,
+ # 250ns delay before SPCK, 250ns b/n tx
+
+ mww 0xfffc8004 0x000D0011 ;# SPI0_MR : same config, select NPCS1
+ mww 0xfffc8000 0x00000001 ;# SPI0_CR : enable SPI0
}
+
+nand device at91sam9260.flash at91sam9 at91sam9260.cpu 0x40000000 0xffffe800
+at91sam9 cle 0 22
+at91sam9 ale 0 21
+at91sam9 rdy_busy 0 0xfffff800 13
+at91sam9 ce 0 0xfffff800 14
-----------------------------------------------------------------------
Summary of changes:
tcl/board/olimex_sam9_l9260.cfg | 52 +++++++++++++++++++++++++++++++++++++++
1 files changed, 52 insertions(+), 0 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-12-26 20:27:36
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 3a84436afb8e1deddffac079573325c6ec3463df (commit)
via e7f81c11c9da8bbe46ca953f41809811b0f47639 (commit)
via df58812b528c9b7857d8bde8f3eea4ad46ed034f (commit)
via 396b0f3012955f21d7932d958fc7547532cdc90a (commit)
via 08a890e4aae307d874bd617f4dc742a56f2064a2 (commit)
from f9d203d1e6656041affc09528ac373a2b32497ee (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 3a84436afb8e1deddffac079573325c6ec3463df
Author: David Brownell <dbr...@us...>
Date: Sat Dec 26 11:25:44 2009 -0800
ARM: add comment re register exports
Modern versions of GDB can understand VFP3 and iwMMXt hardware.
diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 593e895..424263d 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -1686,6 +1686,7 @@ struct target_type cortexa8_target = {
.deassert_reset = cortex_a8_deassert_reset,
.soft_reset_halt = NULL,
+ /* REVISIT allow exporting VFP3 registers ... */
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = cortex_a8_read_memory,
diff --git a/src/target/xscale.c b/src/target/xscale.c
index f1afc71..6efe59c 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -3731,6 +3731,7 @@ struct target_type xscale_target =
.deassert_reset = xscale_deassert_reset,
.soft_reset_halt = NULL,
+ /* REVISIT on some cores, allow exporting iwmmxt registers ... */
.get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = xscale_read_memory,
commit e7f81c11c9da8bbe46ca953f41809811b0f47639
Author: David Brownell <dbr...@us...>
Date: Sat Dec 26 10:35:24 2009 -0800
User's Guide: update GDB info
Advise leaving background polling enabled; fix broken URL;
add simple program startup example.
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 4244a1e..013a31a 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1805,6 +1805,7 @@ allows background polling to be enabled and disabled.
You could use this from the TCL command shell, or
from GDB using @command{monitor poll} command.
+Leave background polling enabled while you're using GDB.
@example
> poll
background polling: on
@@ -6572,8 +6573,8 @@ if that's the tool chain used to compile your code.
@cindex Connecting to GDB
Use GDB 6.7 or newer with OpenOCD if you run into trouble. For
instance GDB 6.3 has a known bug that produces bogus memory access
-errors, which has since been fixed: look up 1836 in
-@url{http://sourceware.org/cgi-bin/gnatsweb.pl?database=gdb}
+errors, which has since been fixed; see
+@url{http://osdir.com/ml/gdb.bugs.discuss/2004-12/msg00018.html}
OpenOCD can communicate with GDB in two ways:
@@ -6597,6 +6598,38 @@ session.
To list the available OpenOCD commands type @command{monitor help} on the
GDB command line.
+@section Sample GDB session startup
+
+With the remote protocol, GDB sessions start a little differently
+than they do when you're debugging locally.
+Here's an examples showing how to start a debug session with a
+small ARM program.
+In this case the program was linked to be loaded into SRAM on a Cortex-M3.
+Most programs would be written into flash (address 0) and run from there.
+
+@example
+$ arm-none-eabi-gdb example.elf
+(gdb) target remote localhost:3333
+Remote debugging using localhost:3333
+...
+(gdb) monitor reset halt
+...
+(gdb) load
+Loading section .vectors, size 0x100 lma 0x20000000
+Loading section .text, size 0x5a0 lma 0x20000100
+Loading section .data, size 0x18 lma 0x200006a0
+Start address 0x2000061c, load size 1720
+Transfer rate: 22 KB/sec, 573 bytes/write.
+(gdb) continue
+Continuing.
+...
+@end example
+
+You could then interrupt the GDB session to make the program break,
+type @command{where} to show the stack, @command{list} to show the
+code around the program counter, @command{step} through code,
+set breakpoints or watchpoints, and so on.
+
@section Configuring GDB for OpenOCD
OpenOCD supports the gdb @option{qSupported} packet, this enables information
commit df58812b528c9b7857d8bde8f3eea4ad46ed034f
Author: David Brownell <dbr...@us...>
Date: Sat Dec 26 10:24:39 2009 -0800
NOR: messaging fix
Fix syntax error: default to "wrote N bytes"; writing a
single byte is an unusual case, not the normal one.
diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
index b5e1b2c..1097bdf 100644
--- a/src/flash/nor/tcl.c
+++ b/src/flash/nor/tcl.c
@@ -439,7 +439,7 @@ COMMAND_HANDLER(handle_flash_write_image_command)
if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK))
{
- command_print(CMD_CTX, "wrote %" PRIu32 " byte from file %s "
+ command_print(CMD_CTX, "wrote %" PRIu32 " bytes from file %s "
"in %fs (%0.3f kb/s)", written, CMD_ARGV[0],
duration_elapsed(&bench), duration_kbps(&bench, written));
}
@@ -625,7 +625,7 @@ COMMAND_HANDLER(handle_flash_write_bank_command)
if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK))
{
- command_print(CMD_CTX, "wrote %zu byte from file %s to flash bank %u"
+ command_print(CMD_CTX, "wrote %zu bytes from file %s to flash bank %u"
" at offset 0x%8.8" PRIx32 " in %fs (%0.3f kb/s)",
fileio.size, CMD_ARGV[1], p->bank_number, offset,
duration_elapsed(&bench), duration_kbps(&bench, fileio.size));
commit 396b0f3012955f21d7932d958fc7547532cdc90a
Author: David Brownell <dbr...@us...>
Date: Sat Dec 26 10:22:28 2009 -0800
NOR: Allocate the right amount of memory
Switch to calloc() to simplify review and initialization.
diff --git a/src/flash/nor/core.c b/src/flash/nor/core.c
index 67fd78b..fe5372b 100644
--- a/src/flash/nor/core.c
+++ b/src/flash/nor/core.c
@@ -401,7 +401,7 @@ int flash_write_unlock(struct target *target, struct image *image,
}
/* allocate padding array */
- padding = malloc(image->num_sections * sizeof(padding));
+ padding = calloc(image->num_sections, sizeof(*padding));
/* loop until we reach end of the image */
while (section < image->num_sections)
commit 08a890e4aae307d874bd617f4dc742a56f2064a2
Author: David Brownell <dbr...@us...>
Date: Sat Dec 26 10:19:19 2009 -0800
cygwin 1.7 build fixes
It's less accepting of signed char ... insisting that e.g. tolower()
not receive one as a parameter.
It's probably good to phase out such usage, given the number of bugs
that lurk in the vicinity (assumptions that char is unsigned), so fix
these even though such usage is actually legal.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/flash/mflash.c b/src/flash/mflash.c
index 123d61c..5c8ca8c 100644
--- a/src/flash/mflash.c
+++ b/src/flash/mflash.c
@@ -1345,7 +1345,8 @@ COMMAND_HANDLER(mg_bank_cmd)
char *str;
mflash_bank->rst_pin.num = strtoul(CMD_ARGV[2], &str, 0);
if (*str)
- mflash_bank->rst_pin.port[0] = (uint16_t)tolower(str[0]);
+ mflash_bank->rst_pin.port[0] = (uint16_t)
+ tolower((unsigned)str[0]);
mflash_bank->target = target;
diff --git a/src/helper/jim.c b/src/helper/jim.c
index c04acf0..53d1a75 100644
--- a/src/helper/jim.c
+++ b/src/helper/jim.c
@@ -2217,7 +2217,7 @@ static Jim_Obj *JimStringToLower(Jim_Interp *interp, Jim_Obj *strObjPtr)
memcpy(buf, strObjPtr->bytes, strObjPtr->length + 1);
for (i = 0; i < strObjPtr->length; i++)
- buf[i] = tolower(buf[i]);
+ buf[i] = tolower((unsigned)buf[i]);
return Jim_NewStringObjNoAlloc(interp, buf, strObjPtr->length);
}
@@ -2233,7 +2233,7 @@ static Jim_Obj *JimStringToUpper(Jim_Interp *interp, Jim_Obj *strObjPtr)
memcpy(buf, strObjPtr->bytes, strObjPtr->length + 1);
for (i = 0; i < strObjPtr->length; i++)
- buf[i] = toupper(buf[i]);
+ buf[i] = toupper((unsigned)buf[i]);
return Jim_NewStringObjNoAlloc(interp, buf, strObjPtr->length);
}
@@ -2347,7 +2347,7 @@ static Jim_Obj *Jim_FormatString_Inner(Jim_Interp *interp, Jim_Obj *fmtObjPtr,
case '8':
case '9':
accum = 0;
- while (isdigit(*fmt) && (fmtLen > 0)) {
+ while (isdigit((unsigned)*fmt) && (fmtLen > 0)) {
accum = (accum * 10) + (*fmt - '0');
fmt++; fmtLen--;
}
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 8798ae0..cf62864 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -943,7 +943,7 @@ void gdb_str_to_target(struct target *target, char *tstr, struct reg *reg)
}
}
-static int hextoint(char c)
+static int hextoint(int c)
{
if (c>='0'&&c<='9')
{
diff --git a/src/server/tcl_server.c b/src/server/tcl_server.c
index 0824768..a772c0a 100644
--- a/src/server/tcl_server.c
+++ b/src/server/tcl_server.c
@@ -88,7 +88,7 @@ static int tcl_input(struct connection *connection)
const char *result;
int reslen;
struct tcl_connection *tclc;
- char in[256];
+ unsigned char in[256];
rlen = read_socket(connection->fd, &in, sizeof(in));
if (rlen <= 0) {
diff --git a/src/server/telnet_server.c b/src/server/telnet_server.c
index 929c1c1..92e7480 100644
--- a/src/server/telnet_server.c
+++ b/src/server/telnet_server.c
@@ -195,8 +195,8 @@ void telnet_clear_line(struct connection *connection, struct telnet_connection *
int telnet_input(struct connection *connection)
{
int bytes_read;
- char buffer[TELNET_BUFFER_SIZE];
- char *buf_p;
+ unsigned char buffer[TELNET_BUFFER_SIZE];
+ unsigned char *buf_p;
struct telnet_connection *t_con = connection->priv;
struct command_context *command_context = connection->cmd_ctx;
@@ -216,7 +216,7 @@ int telnet_input(struct connection *connection)
switch (t_con->state)
{
case TELNET_STATE_DATA:
- if (*buf_p == '\xff')
+ if (*buf_p == 0xff)
{
t_con->state = TELNET_STATE_IAC;
}
@@ -395,16 +395,16 @@ int telnet_input(struct connection *connection)
case TELNET_STATE_IAC:
switch (*buf_p)
{
- case '\xfe':
+ case 0xfe:
t_con->state = TELNET_STATE_DONT;
break;
- case '\xfd':
+ case 0xfd:
t_con->state = TELNET_STATE_DO;
break;
- case '\xfc':
+ case 0xfc:
t_con->state = TELNET_STATE_WONT;
break;
- case '\xfb':
+ case 0xfb:
t_con->state = TELNET_STATE_WILL;
break;
}
diff --git a/src/svf/svf.c b/src/svf/svf.c
index 1c746f3..dfdecbc 100644
--- a/src/svf/svf.c
+++ b/src/svf/svf.c
@@ -470,7 +470,8 @@ free_all:
#define SVFP_CMD_INC_CNT 1024
static int svf_read_command_from_file(int fd)
{
- char ch, *tmp_buffer = NULL;
+ unsigned char ch;
+ char *tmp_buffer = NULL;
int cmd_pos = 0, cmd_ok = 0, slash = 0, comment = 0;
while (!cmd_ok && (read(fd, &ch, 1) > 0))
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 37 +++++++++++++++++++++++++++++++++++--
src/flash/mflash.c | 3 ++-
src/flash/nor/core.c | 2 +-
src/flash/nor/tcl.c | 4 ++--
src/helper/jim.c | 6 +++---
src/server/gdb_server.c | 2 +-
src/server/tcl_server.c | 2 +-
src/server/telnet_server.c | 14 +++++++-------
src/svf/svf.c | 3 ++-
src/target/cortex_a8.c | 1 +
src/target/xscale.c | 1 +
11 files changed, 56 insertions(+), 19 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2009-12-26 10:32:38
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via f9d203d1e6656041affc09528ac373a2b32497ee (commit)
from 4e2b15fc93e9bd46a125449f3c1d85b774a50966 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit f9d203d1e6656041affc09528ac373a2b32497ee
Author: Antonio Borneo <bor...@gm...>
Date: Sat Dec 26 08:06:10 2009 +0800
PARPORT code cleanup:
Align elements in array.
Signed-off-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/parport.c b/src/jtag/drivers/parport.c
index 7ff675b..04ac272 100644
--- a/src/jtag/drivers/parport.c
+++ b/src/jtag/drivers/parport.c
@@ -76,16 +76,15 @@ struct cable {
static struct cable cables[] =
{
- /* name tdo trst tms tck tdi srst o_inv i_inv init exit led */
+ /* name tdo trst tms tck tdi srst o_inv i_inv init exit led */
{ "wiggler", 0x80, 0x10, 0x02, 0x04, 0x08, 0x01, 0x01, 0x80, 0x80, 0x80, 0x00 },
{ "wiggler2", 0x80, 0x10, 0x02, 0x04, 0x08, 0x01, 0x01, 0x80, 0x80, 0x00, 0x20 },
- { "wiggler_ntrst_inverted",
- 0x80, 0x10, 0x02, 0x04, 0x08, 0x01, 0x11, 0x80, 0x80, 0x80, 0x00 },
- { "old_amt_wiggler", 0x80, 0x01, 0x02, 0x04, 0x08, 0x10, 0x11, 0x80, 0x80, 0x80, 0x00 },
+ { "wiggler_ntrst_inverted", 0x80, 0x10, 0x02, 0x04, 0x08, 0x01, 0x11, 0x80, 0x80, 0x80, 0x00 },
+ { "old_amt_wiggler", 0x80, 0x01, 0x02, 0x04, 0x08, 0x10, 0x11, 0x80, 0x80, 0x80, 0x00 },
{ "arm-jtag", 0x80, 0x01, 0x02, 0x04, 0x08, 0x10, 0x01, 0x80, 0x80, 0x80, 0x00 },
{ "chameleon", 0x80, 0x00, 0x04, 0x01, 0x02, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00 },
- { "dlc5", 0x10, 0x00, 0x04, 0x02, 0x01, 0x00, 0x00, 0x00, 0x10, 0x10, 0x00 },
- { "triton", 0x80, 0x08, 0x04, 0x01, 0x02, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00 },
+ { "dlc5", 0x10, 0x00, 0x04, 0x02, 0x01, 0x00, 0x00, 0x00, 0x10, 0x10, 0x00 },
+ { "triton", 0x80, 0x08, 0x04, 0x01, 0x02, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00 },
{ "lattice", 0x40, 0x10, 0x04, 0x02, 0x01, 0x08, 0x00, 0x00, 0x18, 0x18, 0x00 },
{ "flashlink", 0x20, 0x10, 0x02, 0x01, 0x04, 0x20, 0x30, 0x20, 0x00, 0x00, 0x00 },
/* Altium Universal JTAG cable. Set the cable to Xilinx Mode and wire to target as follows:
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/parport.c | 11 +++++------
1 files changed, 5 insertions(+), 6 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-12-21 23:50:04
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 4e2b15fc93e9bd46a125449f3c1d85b774a50966 (commit)
from 0c55017a2241891e23eaace45126195bc0401cad (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 4e2b15fc93e9bd46a125449f3c1d85b774a50966
Author: David Brownell <dbr...@us...>
Date: Mon Dec 21 14:49:36 2009 -0800
Restore "-dev" version suffix
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/configure.in b/configure.in
index 6b57a33..7ce7955 100644
--- a/configure.in
+++ b/configure.in
@@ -1,5 +1,5 @@
AC_PREREQ(2.60)
-AC_INIT([openocd], [0.4.0-rc1],
+AC_INIT([openocd], [0.4.0-rc1-dev],
[OpenOCD Mailing List <ope...@li...>])
AC_CONFIG_SRCDIR([src/openocd.c])
-----------------------------------------------------------------------
Summary of changes:
configure.in | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-12-21 23:49:14
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 0c55017a2241891e23eaace45126195bc0401cad (commit)
from 07c06ec5e23ae90a3a1f8faba60828b453ff6be7 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 0c55017a2241891e23eaace45126195bc0401cad
Author: David Brownell <dbr...@us...>
Date: Mon Dec 21 14:45:52 2009 -0800
v0.4.0-rc1 milestone
Winter Solstice, 2009.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/configure.in b/configure.in
index 12270eb..6b57a33 100644
--- a/configure.in
+++ b/configure.in
@@ -1,5 +1,5 @@
AC_PREREQ(2.60)
-AC_INIT([openocd], [0.4.0-dev],
+AC_INIT([openocd], [0.4.0-rc1],
[OpenOCD Mailing List <ope...@li...>])
AC_CONFIG_SRCDIR([src/openocd.c])
-----------------------------------------------------------------------
Summary of changes:
configure.in | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-12-21 23:48:35
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The annotated tag, v0.4.0-rc1 has been created
at cd8ad2e961d3476ddfad3353390ce99a4872bdf1 (tag)
tagging 0c55017a2241891e23eaace45126195bc0401cad (commit)
replaces v0.3.0
tagged by David Brownell
on Mon Dec 21 14:46:36 2009 -0800
- Log -----------------------------------------------------------------
The OpenOCD v0.4.0-rc1 milestone.
Andreas Fritiofson (3):
show script search dirs in debug log
support for scripts in $HOME/.openocd
improve alloc_vprintf
Antonio Borneo (1):
arm7_9: Support VINITHI signal
David Brownell (270):
Version 0.4.0-dev
PXA255: support Intel "Lubbock" platform
ft2232: cleanup
ARMv7M: add docs, remove exports
Cortex-M3: DWT cleanup/fixes
Cortex-M3: minor cleanup
Cortex-M3: expose most DWT registers
watchpoint_add() cleanup
User's Guide: TAP setup tweakage
ARM920: remove exports and forward decls
ARM926: more cleanup
ARM966: remove exports and forward decls
ARM9TDMI: remove forward decls
FA526: remove exports and forward decls
ARM720: remove exports and forward decls
ARM7TDMI: remove forward decls
target: provide container_of()
Cortex-M3: use the new inheritance/nesting scheme
ARM920 uses the new inheritance/nesting scheme
FA526 uses the new inheritance/nesting scheme
ARM926 uses the new inheritance/nesting scheme
ARM966 uses the new inheritance/nesting scheme
ARM9TDMI uses the new inheritance/nesting scheme
XScale uses the new inheritance/nesting scheme
ARM720 uses the new inheritance/nesting scheme
ARM7TDMI uses the new inheritance/nesting scheme
Cortex-A8: use the new inheritance/nesting scheme
ARM: other code uses the new inheritance/nesting scheme
ARM: shrink offsets
target: don't swap MMU/no-MMU work areas
Merge branch 'master' of ssh://dbr...@op.../gitroot/openocd/openocd
target.cfg: remove "-work-area-virt 0"
Cortex-M3: fix (debug) message priority
ARM: minor simulator cleanup
EmbeddedICE: minor cleanups
User's Guide: bugfix global state info
User's Guide: Flash/NAND doc tweaks
finish removing deprecated/obsolete commands
Revert "target: add target->type->has_mmu fn"
Target: fix bad error messages
ARM720: implement basic MMU ops
ARM920: implement basic MMU ops
Target: minor cleanup
target.cfg: (re)move some bogus reset_config lines
target: MMU-aware init for memory read/write
ARM720: bugfix
ETM cleanup
ARM: start generalized base type
ETM: update arm[79]tdmi_examine()
ETM: update port drivers
ETM: use new toplevel ETM handle
ETM: remove old mid-level ETM handle
ETM: start support for ETMv2+
Cortex-A8: fix indent
ARM7/9: rm arm7_9_get_arch_pointers()
target.cfg: label ETBs correctly
target: remove unused "bitfield" infrastructure
ARM11: switch to new "arm" base type
ETM: simplify ETM initialization code paths
ARM7/ARM9: use shared examine() method
iMX2* + ETB targets: hook up ETM and ETB
ARM11: revert etmr/etmw commands
ARM11: ETM + ETB support
remove annoying $URL$ startup message
flash: remove needless lpc2900.h header
lpc2900.h -- remove from Makefile.am too
target: make "examined" flag be per-target
ARM: memory utils aren't ARM7/ARM9 dependent
ARM11: fixup method table
ARM11: use now-generic memory utils
target: don't implicitly include "breakpoint.h"
target: don't implicitly include "algorithm.h"
target: less implicit inclusion of "command.h"
target: no implicit #includes of "register.h"
#include "target.h" less wildly
target: less implicit inclusion of "etm.h"
"types.h" doxygen fix
binarybuffer: regression fix
JTAG: no LOG_WARNING() for taps without IDCODE
ARM: move mode functions out of header
target: don't include "log.h" from "armv4_5.h"
ARM: standard disassembler uses Thumb2 entry
JTAG: fix autoprobe failure.
ARM: "armv4_5" command prefix becomes "arm"
ARM11: register (most) standard ARM commands
ARMv7A: use standard disassembler
Cortex-M3: don't exit()
ARM11: fewer exit() calls
ARMv4/ARMv5: no exit() calls
ARMv7-M: no exit() calls
MIPS: no exit() calls
XScale: fewere exit() calls
Cortex-A8: no exit() calls, add missing v7-A init
ARMv7-A: no exit() calls
target: remove some more duplicate includes
ARM7TDMI: remove now-needless "struct arm7tdmi"
ARM9TDMI: remove now-needless "struct arm9tdmi"
target: simplify register get/set ops
ARM: only use one set of dummy FPA registers
ARM: add arm_mode_name()
ARM: add is_arm_mode()
ARM: add "core_type" field to "struct arm"
ARM: setup "secure monitor mode" shadow regs
ARM: simplify ARMv7-A register handling
ARM: add a default full_context() method
Cortex-A8: xPSR handling updates
ARM: rework "arm reg" output for new mode
ARMv7-A: use standard ARM core_mode symbols
ARMv7-A: use standard ARM core states
Cortex-A8: parts of examine() run just once
ARM: streamline register init
ARM: remove per-register malloc
target: create/use register_cache_invalidate()
Cortex-A8: mode support
Cortex-A8: better context restore
target.cfg: TAP id for Hilscher netX 500
ARM7/ARM9: remove old "debug commands"
ARM: pass 'struct reg *' to register r/w routines
ARM11: remove disabled register hooks
ARM: simplify CPSR handling
ARM: define two register utilities
ARM: arm_set_cpsr() handles T and J bits
ARM: remove 'armv4_5_common_s' migration #define
target: make register flags "bool"
ARM11: remove needless string format #ifdeffery
ARM: use arm_reg_current()
TODO: ref 'checkstack.pl' not 'checkpatch.pl'
ARM11: macro cleanup
ARM11: remove unused state and exports
target: cope with *any* error setting a breakpoint
ARM: new DPM interface
ARM11: implement provider for new DPM interface
ARM11: remove register "history" debug stuff
ARM11: partial support for standard ARM register interfaces.
ARM11: use standard single step simulation
ARM11: use standard run_algorithm()
ARM11: remove old R0..R15/CPSR code
Cortex-A8: minor cleanup
Cortex-A8: implement DPM
Cortex-A8: hook up DPM
Cortex-A8: avoid DSCR reads
NEWS updates
ARM7/9: shrink run_algorithm_inner() lines
ARM: comment tweaks in ADIv5
ARM: minor armv4/armv5 cleanup
omap3530.cfg: yes we have SRAM!
target: target_get_name() --> target_type_name()
target: create and use target_name()
XScale: add stub {read,write}_phys routines
ARM11: write_memory() avoids increment check
target: groundwork for "reset-assert" event
Cortex-A8: support "reset-assert" event
omap3530.cfg: use new "reset-assert" event
NEWS: mention new reset-assert event
target: remove unused TARGET_EVENT_OLD_* symbols
target: uplevel add_{break,watch}point() error checks
ARM11: fix dbgtap JTAG_DEBUG
ARM11: fix warning on amd64
Cortex-M3: don't chain "struct arm" commands
bugfix: 'init' changes state, not main()
ARM11: fix warning on cygwin
XScale: debug entry uses new register mapping
XScale: clean up full_context() (#1)
XScale: clean up full_context() (#2)
XScale: context restore, cleanup/bugfix
XScale: restore_context() cleanup
Cortex-A8: stop using CP15 ops
ARMv7-A: stop using CP15 ops
target: "mcr" and "mrc" are ARM-specific
ARM: implement mrc()/mcr() as DPM ops
Cortex-A8: remove previous mcr()/mrc() methods
ARM11: remove previous mcr()/mrc() methods
Tcl and doc: update to match new 'arm mcr ...' etc
ARMv7a: move constants out of Cortex-A8 header
ARM: core DPM support for watchpoints
Cortex-A8: basic watchpoint support
ARM: label SP and LR correctly
ARMv7a/Cortex-A8: report watchpoint trigger insn
stubs: buildfix
ARM DPM: tweak initialization
ARM11: remove arm11->target
ARM11: streamline debug entry
ARM11: don't expose RDTR
ARM11: don't expose WDTR
ARM11: store a clean copy of DSCR
ARM11: don't expose DSCR
fix another init regression
ARM DPM: make DSCR bit defs sharable
ARM11: use shared DSCR bit names
ARM DPM: share debug reason logic
ARMv7-A: tweak arch_state()
doxygen: remove some warnings
target: cygwin build fixes
User's Guide: more semihosting info
ARM: remove semihosting globals
ARM: semihosting entry cleanup
ARM11: tweak TAP ops and debugging
ARM11: basic watchpoint support
ARM11: report watchpoint trigger insn
ARM: rename ARMV4_5_STATE_* as ARM_STATE_*
ARM: rename ARMV4_5_MODE_* as ARM_MODE_*
ARM: rename armv4_5_mode_* AS arm_mode_*
ARM: rename armv4_5_state_* as arm_state_*
ARM: switch target_to_armv4_5() to target_to_arm()
ARM: ARMV4_5_COMMON_MAGIC --> ARM_COMMON_MAGIC
ARM: misc generic cleanup
ARM: rename armv4_5_algorithm as arm_algorithm
ARM: rename armv4_5_build_reg_cache() as arm_*()
ARM: doc updates for main header
misc code review updates
User's Guide: mention ETM on ARM11 comes up too
OMAP2420: define reset-assert event
ARM DPM: don't write low bits of watchpoint value
ARM: disassemble two more v6+ instructions
ARM: remove mrc_opcode(), use MRC() or MCR()
ARM: move opcode macros to <target/arm_opcodes.h>
ARM: rename some generic routines
ARM: use <target/arm.h> not armv4_5.h
User's Guide: add quickie setup notes
ARM: don't clone arm_arch_state() code
target: add debug_reason_name()
ARM: list number of HW breakpoints/watchpoints
ARM: cope with stupidheaded compiler
ARM: cygwin complile fixes
target: move 'extern' decls to *.h files
target: remove needless "extern"s
target: remove more exit() calls
Comment and doxygen fixes
stellaris: flash protection updates, minor fixes
ARM: update arm_opcodes.h copyright
anotyer cygwin compile fix
ARM11: minor cleanup, mostly ITR comments
ARM: disassembly fixes for LDC/STC/MRRC/MCRR
ARM DPM: support updating HW breakpoints
ARM11: avoid pointless status returns
LPC2000: rename "r13_svc" as "sp_svc"
target: further shrink Jim-awareness
target files shouldn't #include <target/...h>
jtag: add '-ignore-version' option
lm3748: use new Stellaris config file
ARM: disassemble STM correctly
ARM11: improved reset support
XScale: use all-ones for BYPASS, not five-ones
testing/examples/.../*cfg: rm jtag_device calls
more tcl/{board,target} cleanup
NOR: bugfix "flash fill[bwh] ..." helptext
stellaris: avoid chip writes
stellaris: remove needless code
stellaris: probe() cleanups
stellaris: comments
JTAG: shrink "scan_chain" output
Remove duplicate Olimex-"tiny" interface
stellaris: update bulk flash writes
dsp563xx: cygwin build fixes
XScale: better {read,write}_phys()
stellaris: fix min buffer length checks
Subject: flash fill[bwh] should use bulk i/o
NOR FLASH: only erase/unlock whole sectors
NEWS: mention libftdi 0.17
ETM trigger_percent becomes an ETB command
ETM: start cleaning up ETM_CTRL bit handling
ETM: more ETM_CTRL bit cleanup
ETM: add "etm trigger_debug" command
oocd_trace buildfixes
cygwin build fixes
ARM11: recognize ARM11 MPCore
Cortex-M3: cleanup
Packaging fix
Packaging fix, NEWS update
v0.4.0-rc1 milestone
Dean Glazeski (14):
Invalid command syntax errors with MWW.
nand_fileio_parse_args parses wrong param for size
NAND verify doesn't advance.
NAND Flash documentation update.
ARM NAND I/O read function.
ARM NAND I/O refactor code copying.
ARM NAND I/O documentation update.
ARM NAND I/O header documentation update.
NAND page command refactoring.
ARM NAND I/O interface update
Make ARM NAND I/O operations aware of last op
NAND read data page refactor.
NAND write data page refactoring.
AT91SAM9 NAND flash driver.
Eric Wetzel (2):
fix 'flash protect' and 'flash erase_sector'
stellaris: device IDs
Ferdinand Postema (1):
compile with cygwin (32-bit)
Jerry Ling (1):
mips: fix gaffe when removing dynamic array allocation
Jonas Horberg (1):
parport: add support for the jtag_khz command.
Krzysztof Dziuba (1):
Fix for md* commands, similar to mw*.
Krzysztof Kajstura (1):
JTAG: support KT-LINK adapter
Liam Redmond (1):
WinXP-x64: find right D2XX libraries
Marek Vasut (2):
XScale: initial PXA3xx support
create target/pxa3xx.cfg
Mathias Kuester (1):
NOR: add 29LV400BC flash device
Michael Bruck (1):
arm11: add etmr/etmw registers to access ETM via DBGTAP scan chain
Nicolas Pitre (4):
feroceon.c should be part of ARM7_9_SRC
basic ARM semihosting support
ARM semihosting: work with both low and high vectors
ARM semihosting: use breakpoint on ARM7
Oyvind Harboe (1):
help: list all commands that match string
Rafael Campos Las Heras (1):
Fix compilation error with gcc 4.4.1
Spencer Oliver (4):
ETM: only include oocd_trace.h when tracing enabled.
build: fix cygwin build warnings
server: add server_preinit which is called before config file is parsed.
target.cfg: update to use new flash configuration syntax
Thomas Kindler (1):
stm32.cfg: remove reset_config
Uwe Hermann (3):
fix typos in source files
fix typos in documentation
update bug reporting information
Yegor Yefremov (1):
Common target file for Stellaris chips
Zachary T Welch (595):
Add stringify macros in src/helper/types.h.
Add macro for parsing numeric command arguments.
Improve debug_level command argument parsing.
Improve jtag command argument parsing.
Improve target.c command argument parsing.
Add server port command helper function.
Update all server port command to use new helper.
Improve pld command argument parsing.
Improve xscale command argument parsing.
Improve armv4_5 command argument parsing.
Improve armv7a command argument parsing.
Improve armv7m command argument parsing.
Improve arm7_9_common command argument parsing.
Improve arm720t command argument parsing.
Improve arm920t command argument parsing.
Improve arm926ejs command argument parsing.
Improve arm966e command argument parsing.
Improve arm11 command argument parsing.
Improve xscale command argument parsing.
Improve cortex_m3 command argument parsing.
Improve arm_adi_v5 command argument parsing.
Improve trace command argument parsing.
Improve etm command argument parsing.
Improve ETM tracemode update command.
Add Flash/NAND bank command argument helpers.
Improve flash.c command argument parsing.
Improve nand.c command argument parsing.
Improve at91sam3.c command argument parsing.
Improve at91sam7.c command argument parsing.
Improve davinci_nand.c command argument parsing.
Improve orion_nand.c command argument parsing.
Improve avrf.c command argument parsing.
Improve cfi.c command argument parsing.
Improve lpc2000.c command argument parsing.
Improve lpc288x.c command argument parsing.
Improve lpc2900.c command argument parsing.
Improve lpc3180_nand_controller.c parsing.
Improve mflash.c command argument parsing.
Improve pic32mx.c command argument parsing.
Improve stellaris.c erase argument parsing.
Improve stm32x.c command argument parsing.
Improve str7x config command argument parsing.
Improve str9x config command argument parsing.
Improve str9xpec command argument parsing.
Fix arm11 vcr command parsing.
Improve flash indentation.
Simplify nand indentation.
Fix vsllink bulk out endpoint parsing.
ARM11: remove exports and forward decls
Add private header for ARM11 internals.
Overhaul time support API
src/helper: wrap and clean headers.
src/jtag: remove 'extern' and wrap headers.
src/flash: remove 'extern' and wrap headers
src/{server,pld,svf,xsvf}: remove 'extern' keyword
target.h: remove extern keyword and wrap
src/target: remove 'extern' and wrap headers
flash/flash.c: remove forward declarations
flash/*nand*.c: remove useless declarations
flash/lpc2???.c: remove useless declarations
flash/at91sam[37].c: remove useless declarations
flash/<assorted>.c: remove useless declarations
flash/<various>.c: remove useless declarations
str{7,9}x*.c: remove useless forward declarations
{pic32m,stm32}x.c: remove useless declarations
target.c: remove useless declarations
jtag: remove useless declarations
server: remove useless declarations
command.c: make commands static
svf,xsvf,arm7_9_common: trim forard declarations
fix bug in ARM720: bugfix
makefiles: improve build order
time_support: improve use of types
log: improve log_callback_fn signature
command.c: make private routines static
script_debug(): improve types
change argv to args in command handlers
add const keyword to some APIs
cortex_a8: remove declarations, use static keyword
remove more useless declarations
remove obsolete doxygen comments
wrap help command
add command_name helper
eliminate duplicate helptext management
add help regardless of callback
improve command registration
fix 'jtag interface' behavior
nand: rename device to nand
add command_output_handler_t
add COMMAND_HANDLER and COMMAND_HELPER macros
add command_handler_t type
use COMMAND_HANDLER macro to define all commands
use COMMAND_HELPER for command helper functions
arm_adi,armv7[am]: use COMMAND_HELPER for helpers
s3c24xx: use COMMAND_HANDLER with command helper
add FLASH_BANK_COMMAND_HANDLER macro
use FLASH_BANK_COMMAND_HANDLER macro
nand: add NAND_DEVICE_COMMAND_HANDLER macro
add PLD_DEVICE_COMMAND_HANDLER macro
use CALL_COMMAND_HANDLER instead of direct calls
add CMD_NAME macro for command handlers
command_handler_t: make argc unsigned
command_handler_t: make cmd parameter const
command_handler_t: make args parameter const
command_handler_t: make cmd an indirect parameter
add src/hello.c to augment new command tutorial
add documention for writing built-in commands
remove accidental artifact
log_callback_t -> struct log_callback
fileio_t -> struct fileio
jtag_tap_t -> struct jtag_tap
scan_field_t -> struct scan_field
encapsulate bitq_state structure
bitq_interface_t -> struct biq_interface
bitbang_interface_t -> struct bitbang_interface
jtag_interface_t -> struct jtag_interface
jtag_event_callback_t -> struct jtag_event_callback
use struct jtag_tap_event_action
armjtagew_jtag_t -> struct armjtagew
pending_scan_result_t -> struct pending_scan_result
cable_t -> struct cable
jlink_jtag_t -> struct jlink
ft2232_device_t -> struct ft2232_device
presto_t -> struct presto
vsllink_jtag_t -> struct vsllink
more vsllink typedef cleanup
scan_command_t -> struct scan_command
cmd_queue_page_t -> struct cmd_queue_page
statemove_command_t -> struct statemove_command
pathmove_command_t -> struct pathmove_command
runtest_command_t -> struct runtest_command
stableclocks_command_t -> struct stableclocks_command
reset_command_t -> struct reset_command
end_state_command_t -> struct end_state_command
sleep_command_t -> struct sleep_command
jtag_command_container_t -> union jtag_command_container
jtag_command_t -> struct jtag_command
at91sam7_flash_bank_t -> struct at91sam7_flash_bank
avrf_type_t -> struct avrf_type
avrf_flash_bank_t -> struct avrf_flash_bank
cfi_flash_bank_t -> struct cfi_flash_bank
cfi_intel_pri_ext_t -> struct cfi_intel_pri_ext
cfi_atmel_pri_ext_t -> struct cfi_atmel_pri_ext
cfi_spansion_pri_ext_t -> struct cfi_spansion_pri_ext
cfi_unlock_addresses_t -> struct cfi_unlock_addresses
cfi_fixup_t -> struct cfi_fixup
ecosflash_flash_bank_t -> struct ecosflash_flash_bank
faux_flash_bank_t -> struct faux_flash_bank
flash_sector_t -> struct flash_sector
flash_driver_t -> struct flash_driver
lpc2000_flash_bank_t -> struct lpc2000_flash_bank
lpc288x_flash_bank_t -> struct lpc288x_flash_bank
lpc2900_flash_bank_t -> struct lpc2900_flash_bank
lpc3180_nand_controller_t -> struct lpc3180_nand_controller
mflash_gpio_num_t -> struct mflash_gpio_num
mflash_gpio_drv_t -> struct mflash_gpio_drv
mg_drv_info_t -> struct mg_drv_info
mflash_bank_t -> struct mflash_bank
mx3_nf_controller_t -> struct mx3_nf_controller
nand_flash_controller_t -> struct nand_flash_controller
nand_ecclayout_t -> struct nand_ecclayout
nand_manufacturer_t -> struct nand_manufacturer
nand_info_t -> struct nand_info
ocl_priv_t -> struct ocl_priv
orion_nand_controller_t -> struct orion_nand_controller
pic32mx_flash_bank_t -> struct pic32mx_flash_bank
s3c24xx_nand_controller_t -> struct s3c24xx_nand_controller
stellaris_flash_bank_t -> struct stellaris_flash_bank
stm32x_options_t -> struct stm32x_options
stm32x_flash_bank_t -> struct stm32x_flash_bank
stm32x_mem_layout_t -> struct stm32x_mem_layout
str7x_flash_bank_t -> struct str7x_flash_bank
str7x_mem_layout_t -> struct str7x_mem_layout
str9x_flash_bank_t -> struct str9x_flash_bank
str9xpec_flash_controller_t -> struct str9xpec_flash_controller
nand_block_t -> struct nand_block
non_cfi_t -> struct non_cfi
pic32mx_mem_layout_t -> struct pic32mx_mem_layout
tms470_flash_bank_t -> struct tms470_flash_bank
aduc702x_flash_bank_t -> struct aduc702x_flash_bank
remove unused aduc702x structure.
gdb_connection_t -> struct gdb_connection
gdb_service_t -> struct gdb_service
telnet_service_t -> struct telnet_service
service_t -> struct service
tcl_connection_t -> struct tcl_connection
telnet_connection_t -> struct telnet_connection
connection_t -> struct connection
pld_driver_t -> struct pld_driver
xilinx_bit_file_t -> struct xilinx_bit_file
virtex2_pld_device_t -> struct virtex2_pld_device
pld_device_t -> struct pld_device
remove typedef keyword from svf structures
arm11_register_history_t -> struct arm11_register_history
arm920t_common_t -> struct arm920t_common
mem_param_t -> struct mem_param
reg_param_t -> struct reg_param
arm11_reg_defs_t -> struct arm11_reg_defs
arm11_common_t -> struct arm11_common
arm11_reg_state_t -> struct arm11_reg_state
arm11_sc7_action_t -> struct arm11_sc7_action
arm720t_common_t -> struct arm720t_common
arm7_9_common_t -> struct arm7_9_common
arm7tdmi_common_t -> struct arm7tdmi_common
arm920t_cache_line_t -> struct arm920t_cache_line
arm920t_tlb_entry_t -> struct arm920t_tlb_entry
arm926ejs_common_t -> struct arm926ejs_common
arm966e_common_t -> struct arm966e_common
arm9tdmi_common_t -> struct arm9tdmi_common
swjdp_reg_t -> struct swjdp_reg
swjdp_common_t -> struct swjdp_common
arm_b_bl_bx_blx_instr_t -> struct arm_b_bl_bx_blx_instr
arm_data_proc_instr_t -> struct arm_data_proc_instr
arm_load_store_instr_t -> struct arm_load_store_instr
arm_load_store_multiple_instr_t -> struct arm_load_store_multiple_instr
arm_jtag_t -> struct arm_jtag
armv4_5_algorithm_t -> struct armv4_5_algorithm
armv4_5_core_reg_t -> struct armv4_5_core_reg
armv4_5_cachesize_t -> struct armv4_5_cachesize
armv4_5_cache_common_t -> struct armv4_5_cache_common
armv4_5_mmu_common_t -> struct armv4_5_mmu_common
armv7a_common_t -> struct armv7a_common
armv7a_algorithm_t -> struct armv7a_algorithm
armv7a_core_reg_t -> struct armv7a_core_reg
armv7m_common_t -> struct armv7m_common
armv7m_algorithm_t -> struct armv7m_algorithm
armv7m_core_reg_t -> struct armv7m_core_reg
mcu_jtag_t -> struct mcu_jtag
avr_common_t -> struct avr_common
watchpoint_t -> struct watchpoint
cortex_a8_common_t -> struct cortex_a8_common
cortex_m3_common_t -> struct cortex_m3_common
embeddedice_reg_t -> struct embeddedice_reg
etb_reg_t -> struct etb_reg
etm_reg_t -> struct etm_reg
etm_capture_driver_t -> struct etm_capture_driver
etmv1_trace_data_t -> struct etmv1_trace_data
image_section_t -> struct image_section
image_binary_t -> struct image_binary
image_ihex_t -> struct image_ihex
image_memory_t -> struct image_memory
image_mot_t -> struct image_mot
mips32_comparator_t -> struct mips32_comparator
mips32_common_t -> struct mips32_common
mips32_core_reg_t -> struct mips32_core_reg
mips_ejtag_t -> struct mips_ejtag
mips_m4k_common_t -> struct mips_m4k_common
oocd_trace_t -> struct oocd_trace
bitfield_desc_t -> struct bitfield_desc
reg_cache_t -> struct reg_cache
reg_arch_type_t -> struct reg_arch_type
working_area_t -> struct working_area
target_event_callback_t -> struct target_event_callback
target_timer_callback_t -> struct target_timer_callback
debug_msg_receiver_t -> struct debug_msg_receiver
trace_point_t -> struct trace_point
xscale_trace_data_t -> struct xscale_trace_data
xscale_common_t -> struct xscale_common
xscale_reg_t -> struct xscale_reg
arm9tdmi_vector_t -> struct arm9tdmi_vector
arm_instruction_t -> struct arm_instruction
target_event_action_t -> struct target_event_action
xscale_trace_entry_t -> struct xscale_trace_entry
xscale_trace_t -> struct xscale_trace
breakpoint_t -> struct breakpoint
cortex_a8_brp_t -> struct cortex_a8_brp
cortex_a8_wrp_t -> struct cortex_a8_wrp
cortex_m3_fp_comparator_t -> struct cortex_m3_fp_comparator
cortex_m3_dwt_comparator_t -> struct cortex_m3_dwt_comparator
image_elf_t -> struct image_elf
trace_t -> struct trace
etb_t -> struct etb
etm_context_t -> struct etm_context
armv4_5_common_t -> struct arm
image_t -> struct image
improve mips32_pracc_context
target_type_t -> struct target_type
reg_t -> struct reg
target_t -> struct target
nand_device_t -> struct nand_device
flash_bank_t -> struct flash_bank
remove rlink structure typedefs
command_context_t -> struct command_context
command_t -> struct command
update developer manual for new types
add openocd.h for top-level declarations
struct scan_field_s -> struct scan_field
remove unused buf_to_u32_handler
remove unused arm_jtag_buf_to_* helpers
rlink: fix overzealous sed
arm-jtag-ew,jlink: switch to COMMAND_HANDLER
binarybuffer: fix whitespace related issues
binarybuffer: move variables to point of first use
improve str_to_buf and buf_to_str helpers
improve buf_cmp and buf_cmp_mask helpers
improve buf_cpy helper
improve buf_set_ones
improve buf_set_buf helper
improve inline binarybuffer helpers
binarybuffer: add API documentation
Add nand_fileio_* helper APIs.
Use nand_fileio_* in write/dump commands.
Add FILEIO_NONE access mode.
Add 'nand verify' command
cleanup jtag minidrivers
flash_command_get_bank_by_num: make COMMAND_HELPER
nand_command_get_device_by_num: make COMMAND_HELPER
move container_of to types.h
rename CEIL as DIV_ROUND_UP
remove TAP_SCAN_BYTES macro
armv7m: make core reg read/write use unsigned
move ARRAY_SIZE macro to types.h
make command line options const
improve constness of open_file_from_path
use Jim_CmdProc in jim_register
helper/log: improve API parameter types
struct fileio: improve member types
fileio: improve API types
add more command_handler conversion macros
command_handler: change to 'argc' to CMD_ARGC
command_handler: change 'args' to CMD_ARGV
command_handler: change 'cmd_ctx' to CMD_CTX
add struct command_invocation for COMMAND_HANDLER
add CMD_NAME variable in command_invocation
remove unused variable from run_command
update command_handler documentation
update doxygen configuration to produce a PDF
allow documentation to be configured
fix regression in md/mw commands
move startup.c to libopenocd
split startup.tcl file across modules
pass startup_tcl to command_init
fix segfault at startup
add COMMAND_PARSE_BOOL macro and friends
use COMMAND_PARSE_ON_OFF where appropriate
use COMMAND_PARSE_ENABLE macro where appropriate
add handle_command_parse_bool command helper
change all bool parsers to accept any value
update src/hello.c with parsing examples
remove fast command and jim_global_long
fix zy1000 command handler
allow flash/nand banks commands to accept names
rename flash and nand command helpers
refactor handle_flash_bank_command
add support for naming flash banks
update 'flash bank' usage in scripts
refactor handle_nand_device_command
add support for naming NAND banks
update 'nand device' usage in scripts
document new flash syntax
fix flash/nand name parsing
factor script_command argv allocation
change command_find helper interface
refactor command registration
factor help script command into parts
improve 'help' command
provide command context during cmd_init
add add_help_text command handler
maintain command lists in sorted order
allow jtag interfaces to lack commands
jtag: remove useless forward declarations
add jtag/usb_common.[ch] files
arm-jtag-ew: use jtag_usb_open
usbprog: use jtag_usb_open
vsllink: rewrite to use jtag_usb_open
rlink: eliminate spurious indentation
rlink: use jtag_usb_open helper
jlink: remove superfluous indentation
jlink: rewrite to use jtag_usb_open
fix doxygen build
improve startup tcl scripts
add COMMAND_REGISTER macro
use COMMAND_REGISTER macro
add struct command_registration
add register_commands for batch registration
add command usage, separate from help
command: use register_commands for handlers
more command registration refactoring
add command registration chaining
refactor script_command context grabbing
add public API for locating commands
rewrite 'unknown' command dispatching in C
hello: use register_commands()
demonstrate chaining with foo commands
openocd: use register_commands()
ioutil: use register_commands()
log: use register_commands()
server: use register_commands
{,x}svf: use register_commands()
pld: use register_commands()
pld: use static registration instead of callback
amt_jtagaccel: use register_commands()
arm-jtag-ew: use register_commands()
at91rm9200: use register_commands()
ft2232: use register_commands()
gw16012: use register_commands()
jlink: use register_commands()
parport: use register_commands()
presto: use register_commands()
jtag: use register_commands()
vsllink: use register_commands()
remove register_callbacks from jtag interface
at91sam3: use register_commands()
at91sam7: use register_commands()
avrf: use register_commands()
cfi: use register_commands()
ecos: use register_commands()
flash: use register_commands()
lpc2000: use register_commands()
lpc2900: use register_commands()
lpc3180_nand_controller: use register_commands()
mflash: use register_commands()
nand: use register_commands()
pic32mx: use register_commands()
stellaris: use register_commands()
stm32x: use register_commands()
str7x: use register_commands()
str9x: use register_commands()
str9xpec: use register_commands()
tms470: use register_commands()
remove flash_driver->register_callbacks
remove nand_controller->register_callbacks
arm11: use register_commands()
arm720t: use register_commands()
arm7_9_common: use register_commands()
arm920t: use register_commands()
arm926ejs: use register_commands()
arm966e: use register_commands()
arm9tdmi: use register_commands()
armv4_5: use register_commands()
armv7a: use register_commands()
armv7m: use register_commands()
cortex_a8: use register_commands()
cortex_m3: use register_commands()
etb: use register_commands()
etm: use register_commands()
etm_dummy: use register_commands()
oocd_trace: use register_commands()
target: use register_commands()
target_request: use register_commands()
trace: use register_commands()
xscale: use register_commands()
remove target_type register_command callback
remove register_commands from etm_capture_driver
refactor command_new to use command_registration
add jim_handler to command_registration
httpd: use register_commands()
allow scripts to update usage information
improve usage and help command output
combine help and usage command handlers
encapsulate and re-use log capture, retval setup
add script_command_run helper
improve command handling examples
add 'testee' target type
update command handler documentation
log: improve initialization
support OPENOCD_DEBUG_LEVEL environment setting
use ARRAY_SIZE macro
update NEWS with recent developments
fix 'nand info' command
update minidummy interface driver command handling
fix regression causing duplicated output
add 'command type' introspective handler
improve command handler wrapper script
remove unknown handler
add 'command mode' introspective handler
add command private data setter/accessor
refactor command mode detection
include mode information in help text.
add error checking in command_new
remove redundant 'rm' command handler
split jim_jtag_command into multiple handlers
begin moving JTAG jim handlers/helpers
improve jtag_tap_handle_event indentation
improve jtag_tap_configure
split jim_newtap_cmd into pieces
split jim_target into multiple handlers
explode tcl_target_func into many handlers
add more stub handlers to testee target
add 'nonce' nand driver
improve gdb_init() sequence
move server_init() to openocd_main()
allow deferal of init
only display usable commands in help
improve command_done() API and docs
move improperly located documentation
make syntax errors respond with 'usage'
fix foo command group help messages
jtag: avoid using interp global variable
target: avoid using interp global variable
do not extern 'interp' from command.c
command output capture: do not use interp global
remove interp global variable!
improve command prohibition error report
pld: factor init to 'pld init'
nand: factor init to 'nand init'
mflash: factor init to 'mflash init'
flash: factor init to 'flash init'
jtag: factor init into 'jtag init'
target: factor target_init() into pieces
target: factor init to 'target init'
remove #if logic for openocd_sleep_*lude
remove BUILD_IOUTIL symbol
remove #if BUILD_HTTPD
fix 'target init' command registration
adding files required for distribution
fix configure problem when building w/o USB
move nand drivers to src/flash/nand/
move nor drivers to src/flash/nor
move jtag drivers to src/jtag/drivers
remove #if HAVE_JTAG_INTERFACE_H from minidriver.h
allow #include directives to use module name
change autoconf #include in configure.in
normalize headers to make changing easier
change #include "binarybuffer.h" to <helper/binarybuffer.h>
change #include "command.h" to <helper/command.h>
change #include "configuration.h" to <helper/configuration.h>
change #include "fileio.h" to <helper/fileio.h>
change #include "ioutil.h" to <helper/ioutil.h>
change #include "jim.h" to <helper/jim.h>
change #include "log.h" to <helper/log.h>
change #include "membuf.h" to <helper/membuf.h>
change #include "replacements.h" to <helper/replacements.h>
change #include "time_support.h" to <helper/time_support.h>
change #include "types.h" to <helper/types.h>
change #include "commands.h" to <jtag/commands.h>
change #include "interface.h" to <jtag/interface.h>
change #include "jtag.h" to <jtag/jtag.h>
change #include "minidriver.h" to <jtag/minidriver.h>
change #include "algorithm.h" to <target/algorithm.h>
change #include "arm11.h" to <target/arm11.h>
change #include "arm7_9_common.h" to <target/arm7_9_common.h>
change #include "arm7tdmi.h" to <target/arm7tdmi.h>
change #include "arm966e.h" to <target/arm966e.h>
change #include "arm9tdmi.h" to <target/arm9tdmi.h>
change #include "arm_adi_v5.h" to <target/arm_adi_v5.h>
change #include "arm_dpm.h" to <target/arm_dpm.h>
change #include "arm_jtag.h" to <target/arm_jtag.h>
change #include "armv4_5.h" to <target/armv4_5.h>
change #include "armv4_5_cache.h" to <target/armv4_5_cache.h>
change #include "armv4_5_mmu.h" to <target/armv4_5_mmu.h>
change #include "armv7a.h" to <target/armv7a.h>
change #include "armv7m.h" to <target/armv7m.h>
change #include "avrt.h" to <target/avrt.h>
change #include "breakpoints.h" to <target/breakpoints.h>
change #include "embeddedice.h" to <target/embeddedice.h>
change #include "etm.h" to <target/etm.h>
change #include "image.h" to <target/image.h>
change #include "mips32.h" to <target/mips32.h>
change #include "mips32_pracc.h" to <target/mips32_pracc.h>
change #include "mips_ejtag.h" to <target/mips_ejtag.h>
change #include "register.h" to <target/register.h>
change #include "target.h" to <target/target.h>
change #include "target_request.h" to <target/target_request.h>
change #include "trace.h" to <target/trace.h>
change #include "arm_nandio.h" to <flash/arm_nandio.h>
change #include "flash.h" to <flash/flash.h>
change #include "mflash.h" to <flash/mflash.h>
change #include "nand.h" to <flash/nand.h>
change #include "ocl.h" to <flash/nor/ocl.h>
change #include "s3c24xx_regs.h" to <flash/nand/s3c24xx_regs.h>
change #include "gdb_server.h" to <server/gdb_server.h>
change #include "httpd.h" to <server/httpd.h>
change #include "server.h" to <server/server.h>
change #include "telnet_server.h" to <server/telnet_server.h>
change #include "pld.h" to <pld/pld.h>
change #include "svf.h" to <svf/svf.h>
change #include "xsvf.h" to <xsvf/xsvf.h>
change #include "../hello.h" to "hello.h"
remove tertiary include paths
fix regressions with GDB port numbers
fix double 'init' regression
allow 'jtag init' to be run in any mode
check top-level command registrations
switch 'rm' command away from using Jim
separate Jim from jtag/core.c
add flash/nor/{tcl.c,imp.h} from flash/flash.c
add flash/nor/core.[ch]
move more nor flash implementation details
add flash/nor/drivers.c
eliminate src/flash/flash.c
split NOR and NAND flash headers
remove target.h from flash.h
split flash.h into into flash/nor/*.h
remove flash.h from tree
reorder build order of src directory
split NAND driver handling into nand/driver.[ch]
split nand.c into nand/{core,fileio,tcl}.c
move remaining nand helper files
rename nand.h to flash//nand/core.h
fix NOR flash regression
allow 'flash_banks' command to give GDB output
add 'flash list', rewrite 'flash banks'
fix 'write_image' usage information
add missing call to add new NAND devices
lementec fabien (1):
fix s3c24xx device command helper
mk...@us... (1):
target: add basic dsp563xx support
Ãyvind Harboe (66):
warnings: remove
debug interface: get rid of unused pre_debug fn
target: remove unused interface fn that clutters code
Make default implementation of mdw/mmw phys return error 'not implemented'
target: add target->type->has_mmu fn.
cortex_a8: add mrc mcr interface.
target: Only register mrc mcr commands when one of the targets support them.
TODO: Wrote up list of remaining tasks for target->type->mrc/mcr
ARM11: added mrc/mcr support to arm11 code.
target: check args to mrc/mcr.
target: fix ordering of arguments to mcr and mrc commands
arm11: check if target is halted before executing mrc/mcr commands.
arm920t: add mrcmcr interface fn's.
tcl: HostOs now picks up eCos as well during compile time
httpd: fix warnings, more robust error handling, improved MIME handling
telo.cfg: fix search paths
ARM11: remove old mrc/mcr commands
zy1000: fix trivial syntax error introduced by latest refactorings
zy1000: fix bug when running on non-arm CPU
zy1000: add version command to print FPGA version and timestamps
zy1000: revC UART forwarding
jtag_registers: Avalon bridge flushing tweaks
jtag-api: get rid of unecessary buf_set_u23() that make code obtuse.
build: fix breakage in building bin2char
zy1000: fix breakage in command parsing code for power command
embedded: save stack
embedded: do not allocate large temporary structures on stack
embedded: reduce stack usage
zy1000: un-break uart command after command handler refactoring
todo: add tip on how to identify excessive stack usage
target: reduce stack usage
flash: dynamically allocate working storage
arm926ejs: fix warnings
arm11: do not use dynamic arrays
mips: use const for code sequences
mips: remove dynamic arrays - reduces stack usage
arm926ejs: retire cp15 commands, handled by mrc/mcr.
arm926ejs: fix gaffe when converting from arm926ejs cp15 to mcr
styleguide: add some embedded style rules.
minidummy: fix compilation error
zy1000: keep up with changes to log_init()
zy1000: keep up with new command registration stuff
zy1000: keep up with changes to command structure
main: invoke jtag_interface_quit() explicitly
command: the Jim interpreter can now be provided rather than created
zy1000: keep up with latest changes to command handling
target: at91eb40a.cfg is a board, not a target.
zy1000: keep up with startup refactoring work.
zy1000: include files have moved about
zy1000: FPGA revC wip
bootstrap: stop execution upon error
build: add build/src to include path
zy1000: remove unecessary include
minidriver: fix inline capability of minidriver
zy1000: some background info on the zy1000 file.
zy1000: revc FPGA now works
embedded hosts: optimize common code path for core arm operations
optimisation: tiny optimisation for embedded ice
gdb_server: make struct gdb_connection private
gdb_server: use more local variables in inner loop of fetching packetstiny refactoring to allow optimisation of inner loops
imx31: move srst delay into config script
command: retire obsolete macro
zy1000: keep up with command.h cleanup
server: server loop will exhaust data inputs before sleeping
ecos: crisper implementation of timeval_ms()
zy1000: removed some redundant include
-----------------------------------------------------------------------
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-12-21 23:12:28
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 07c06ec5e23ae90a3a1f8faba60828b453ff6be7 (commit)
via b963e17be718fe5f01cb4f1238e22fd9c39e7c06 (commit)
from b5962b23d83fa692e023512a5b63e736a06d6422 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 07c06ec5e23ae90a3a1f8faba60828b453ff6be7
Author: David Brownell <dbr...@us...>
Date: Mon Dec 21 12:50:17 2009 -0800
Packaging fix, NEWS update
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/NEWS b/NEWS
index e122912..173d06a 100644
--- a/NEWS
+++ b/NEWS
@@ -35,6 +35,7 @@ Target Layer:
ETM, ETB
- "trigger_percent" command moved ETM --> ETB
- "etm trigger_debug" command added
+ Freescale DSP563xx cores (partial support)
Flash Layer:
'flash bank' and 'nand device' take <bank_name> as first argument.
@@ -44,6 +45,7 @@ Flash Layer:
New 'nand verify' command to check bank against an image file.
The "flash erase_address" command now rejects partial sectors;
previously it would silently erase extra data.
+ New at91sam9 NAND controller driver.
Board, Target, and Interface Configuration Scripts:
ARM9
diff --git a/src/flash/nand/Makefile.am b/src/flash/nand/Makefile.am
index bb9998e..2ffa4c4 100644
--- a/src/flash/nand/Makefile.am
+++ b/src/flash/nand/Makefile.am
@@ -30,8 +30,10 @@ NAND_DRIVERS = \
noinst_HEADERS = \
arm_io.h \
core.h \
- lpc3180.h \
driver.h \
+ fileio.h \
+ imp.h \
+ lpc3180.h \
mx3.h \
s3c24xx.h \
s3c24xx_regs.h
commit b963e17be718fe5f01cb4f1238e22fd9c39e7c06
Author: David Brownell <dbr...@us...>
Date: Mon Dec 21 12:31:12 2009 -0800
Packaging fix
Don't forget to list target/arm_opcodes.h
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index df54a03..ad0ff7c 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -105,6 +105,7 @@ noinst_HEADERS = \
arm_jtag.h \
arm_adi_v5.h \
arm_disassembler.h \
+ arm_opcodes.h \
arm_simulator.h \
arm_semihosting.h \
arm7_9_common.h \
-----------------------------------------------------------------------
Summary of changes:
NEWS | 2 ++
src/flash/nand/Makefile.am | 4 +++-
src/target/Makefile.am | 1 +
3 files changed, 6 insertions(+), 1 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2009-12-21 11:20:39
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via b5962b23d83fa692e023512a5b63e736a06d6422 (commit)
from 34bbbe796178a85305dcd2ffb3dae02b6a372e55 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit b5962b23d83fa692e023512a5b63e736a06d6422
Author: Oyvind Harboe <oyv...@zy...>
Date: Sun Dec 20 22:14:10 2009 +0100
help: list all commands that match string
Restore behavior where help lists all commands that
match string passed to help.
Signed-off-by: Oyvind Harboe <oyv...@zy...>
diff --git a/src/helper/command.c b/src/helper/command.c
index 76050ef..b991544 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -860,13 +860,13 @@ static COMMAND_HELPER(command_help_find, struct command *head,
}
static COMMAND_HELPER(command_help_show, struct command *c, unsigned n,
- bool show_help);
+ bool show_help, const char *match);
static COMMAND_HELPER(command_help_show_list, struct command *head, unsigned n,
- bool show_help)
+ bool show_help, const char *match)
{
for (struct command *c = head; NULL != c; c = c->next)
- CALL_COMMAND_HANDLER(command_help_show, c, n, show_help);
+ CALL_COMMAND_HANDLER(command_help_show, c, n, show_help, match);
return ERROR_OK;
}
@@ -899,7 +899,7 @@ static void command_help_show_wrap(const char *str, unsigned n, unsigned n2)
}
}
static COMMAND_HELPER(command_help_show, struct command *c, unsigned n,
- bool show_help)
+ bool show_help, const char *match)
{
if (!command_can_run(CMD_CTX, c))
return ERROR_OK;
@@ -908,18 +908,30 @@ static COMMAND_HELPER(command_help_show, struct command *c, unsigned n,
if (NULL == cmd_name)
return -ENOMEM;
- command_help_show_indent(n);
- LOG_USER_N("%s", cmd_name);
+ /* If the match string occurs anywhere, we print out
+ * stuff for this command. */
+ bool is_match = (strstr(cmd_name, match) != NULL) ||
+ ((c->usage != NULL) && (strstr(c->usage, match) != NULL)) ||
+ ((c->help != NULL) && (strstr(c->help, match) != NULL));
+
+ if (is_match)
+ {
+ command_help_show_indent(n);
+ LOG_USER_N("%s", cmd_name);
+ }
free(cmd_name);
- if (c->usage) {
- LOG_USER_N(" ");
- command_help_show_wrap(c->usage, 0, n + 5);
+ if (is_match)
+ {
+ if (c->usage) {
+ LOG_USER_N(" ");
+ command_help_show_wrap(c->usage, 0, n + 5);
+ }
+ else
+ LOG_USER_N("\n");
}
- else
- LOG_USER_N("\n");
- if (show_help)
+ if (is_match && show_help)
{
const char *stage_msg;
switch (c->mode) {
@@ -942,7 +954,7 @@ static COMMAND_HELPER(command_help_show, struct command *c, unsigned n,
return ERROR_OK;
return CALL_COMMAND_HANDLER(command_help_show_list,
- c->children, n, show_help);
+ c->children, n, show_help, match);
}
COMMAND_HANDLER(handle_help_command)
{
@@ -950,14 +962,15 @@ COMMAND_HANDLER(handle_help_command)
struct command *c = CMD_CTX->commands;
- if (0 == CMD_ARGC)
- return CALL_COMMAND_HANDLER(command_help_show_list, c, 0, full);
-
- int retval = CALL_COMMAND_HANDLER(command_help_find, c, &c);
- if (ERROR_OK != retval)
- return retval;
-
- return CALL_COMMAND_HANDLER(command_help_show, c, 0, full);
+ const char *match = "";
+ if (CMD_ARGC == 0)
+ match = "";
+ else if (CMD_ARGC == 1)
+ match = CMD_ARGV[0];
+ else
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ return CALL_COMMAND_HANDLER(command_help_show_list, c, 0, full, match);
}
static int command_unknown_find(unsigned argc, Jim_Obj *const *argv,
@@ -975,6 +988,7 @@ static int command_unknown_find(unsigned argc, Jim_Obj *const *argv,
return command_unknown_find(--argc, ++argv, (*out)->children, out, false);
}
+
static int command_unknown(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
{
const char *cmd_name = Jim_GetString(argv[0], NULL);
-----------------------------------------------------------------------
Summary of changes:
src/helper/command.c | 56 +++++++++++++++++++++++++++++++------------------
1 files changed, 35 insertions(+), 21 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-12-21 02:13:53
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 34bbbe796178a85305dcd2ffb3dae02b6a372e55 (commit)
via abf01895aea06b0e5c79687b68c424e62b205546 (commit)
from 0df5d1eb3c3a640c34de52787c4a70c07b53535f (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 34bbbe796178a85305dcd2ffb3dae02b6a372e55
Author: David Brownell <dbr...@us...>
Date: Sun Dec 20 16:33:00 2009 -0800
Cortex-M3: cleanup
Misc:
- Introduce some "struct reg" temporaries, for clarity
- Shorten lines
- Add some missing whitespace
- Clean up comments
- Add notes about some fault handling issues
- Most of these errata workarounds are for *OLD* chip revisions
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 6bc427a..edf9b6f 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -42,6 +42,10 @@
/* NOTE: most of this should work fine for the Cortex-M1 and
* Cortex-M0 cores too, although they're ARMv6-M not ARMv7-M.
+ *
+ * Although there are some workarounds for errata seen only in r0p0
+ * silicon, such old parts are hard to find and thus not much tested
+ * any longer.
*/
@@ -138,6 +142,7 @@ static int cortex_m3_clear_halt(struct target *target)
/* Read Debug Fault Status Register */
mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
+
/* Clear Debug Fault Status */
mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
@@ -154,10 +159,15 @@ static int cortex_m3_single_step_core(struct target *target)
/* backup dhcsr reg */
dhcsr_save = cortex_m3->dcb_dhcsr;
- /* mask interrupts if not done already */
+ /* Mask interrupts before clearing halt, if done already. This avoids
+ * Erratum 377497 (fixed in r1p0) where setting MASKINTS while clearing
+ * HALT can put the core into an unknown state.
+ */
if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
- mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
- mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
+ mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
+ DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
+ mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
+ DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
LOG_DEBUG(" ");
/* restore dhcsr reg */
@@ -176,10 +186,11 @@ static int cortex_m3_endreset_event(struct target *target)
struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
+ /* FIXME handling of DEMCR clobbers vector_catch config ... */
mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
- /* this regsiter is used for emulated dcc channel */
+ /* this register is used for emulated dcc channel */
mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
/* Enable debug requests */
@@ -190,11 +201,26 @@ static int cortex_m3_endreset_event(struct target *target)
/* clear any interrupt masking */
cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
- /* Enable trace and dwt */
+ /* Enable trace and DWT; trap hard and bus faults.
+ *
+ * REVISIT why trap those two? And why trash the vector_catch
+ * config, instead of preserving it? Catching HARDERR and BUSERR
+ * will interfere with code that handles those itself...
+ */
mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
- /* Monitor bus faults */
+
+ /* Monitor bus faults as such (instead of as generic HARDERR), but
+ * leave memory management and usage faults disabled.
+ *
+ * REVISIT setting BUSFAULTENA interferes with code which relies
+ * on the default setting. Why do it?
+ */
mem_ap_write_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
+ /* Paranoia: evidently some (early?) chips don't preserve all the
+ * debug state (including FBP, DWT, etc) across reset...
+ */
+
/* Enable FPB */
target_write_u32(target, FP_CTRL, 3);
cortex_m3->fpb_enabled = 1;
@@ -308,6 +334,7 @@ static int cortex_m3_debug_entry(struct target *target)
struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
struct armv7m_common *armv7m = &cortex_m3->armv7m;
struct swjdp_common *swjdp = &armv7m->swjdp_info;
+ struct reg *r;
LOG_DEBUG(" ");
@@ -327,7 +354,8 @@ static int cortex_m3_debug_entry(struct target *target)
armv7m->read_core_reg(target, i);
}
- xPSR = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32);
+ r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
+ xPSR = buf_get_u32(r->value, 0, 32);
#ifdef ARMV7_GDB_HACKS
/* FIXME this breaks on scan chains with more than one Cortex-M3.
@@ -336,14 +364,14 @@ static int cortex_m3_debug_entry(struct target *target)
/* copy real xpsr reg for gdb, setting thumb bit */
buf_set_u32(armv7m_gdb_dummy_cpsr_value, 0, 32, xPSR);
buf_set_u32(armv7m_gdb_dummy_cpsr_value, 5, 1, 1);
- armv7m_gdb_dummy_cpsr_reg.valid = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
- armv7m_gdb_dummy_cpsr_reg.dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty;
+ armv7m_gdb_dummy_cpsr_reg.valid = r->valid;
+ armv7m_gdb_dummy_cpsr_reg.dirty = r->dirty;
#endif
/* For IT instructions xPSR must be reloaded on resume and clear on debug exec */
if (xPSR & 0xf00)
{
- armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = armv7m->core_cache->reg_list[ARMV7M_xPSR].valid;
+ r->dirty = r->valid;
cortex_m3_store_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 16, xPSR &~ 0xff);
}
@@ -355,7 +383,8 @@ static int cortex_m3_debug_entry(struct target *target)
}
else
{
- armv7m->core_mode = buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_CONTROL].value, 0, 1);
+ armv7m->core_mode = buf_get_u32(armv7m->core_cache
+ ->reg_list[ARMV7M_CONTROL].value, 0, 1);
armv7m->exception_number = 0;
}
@@ -404,8 +433,11 @@ static int cortex_m3_poll(struct target *target)
if (target->state == TARGET_RESET)
{
- /* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */
- LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32 "", cortex_m3->dcb_dhcsr);
+ /* Cannot switch context while running so endreset is
+ * called with target->state == TARGET_RESET
+ */
+ LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
+ cortex_m3->dcb_dhcsr);
cortex_m3_endreset_event(target);
target->state = TARGET_RUNNING;
prev_target_state = TARGET_RUNNING;
@@ -498,11 +530,13 @@ static int cortex_m3_soft_reset_halt(struct target *target)
uint32_t dcb_dhcsr = 0;
int retval, timeout = 0;
- /* Enter debug state on reset, cf. end_reset_event() */
- mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
+ /* Enter debug state on reset; see end_reset_event() */
+ mem_ap_write_u32(swjdp, DCB_DEMCR,
+ TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
- /* Request a reset */
- mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET);
+ /* Request a core-only reset */
+ mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR,
+ AIRCR_VECTKEY | AIRCR_VECTRESET);
target->state = TARGET_RESET;
/* registers are now invalid */
@@ -513,15 +547,23 @@ static int cortex_m3_soft_reset_halt(struct target *target)
retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
if (retval == ERROR_OK)
{
- mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
- if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
+ mem_ap_read_atomic_u32(swjdp, NVIC_DFSR,
+ &cortex_m3->nvic_dfsr);
+ if ((dcb_dhcsr & S_HALT)
+ && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
{
- LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%" PRIx32 ", nvic_dfsr 0x%" PRIx32 "", dcb_dhcsr, cortex_m3->nvic_dfsr);
+ LOG_DEBUG("system reset-halted, DHCSR 0x%08x, "
+ "DFSR 0x%08x",
+ (unsigned) dcb_dhcsr,
+ (unsigned) cortex_m3->nvic_dfsr);
cortex_m3_poll(target);
+ /* FIXME restore user's vector catch config */
return ERROR_OK;
}
else
- LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%" PRIx32 ", %i ms", dcb_dhcsr, timeout);
+ LOG_DEBUG("waiting for system reset-halt, "
+ "DHCSR 0x%08x, %d ms",
+ (unsigned) dcb_dhcsr, timeout);
}
timeout++;
alive_sleep(1);
@@ -549,6 +591,7 @@ static int cortex_m3_resume(struct target *target, int current,
struct armv7m_common *armv7m = target_to_armv7m(target);
struct breakpoint *breakpoint = NULL;
uint32_t resume_pc;
+ struct reg *r;
if (target->state != TARGET_HALTED)
{
@@ -565,30 +608,40 @@ static int cortex_m3_resume(struct target *target, int current,
if (debug_execution)
{
+ r = armv7m->core_cache->reg_list + ARMV7M_PRIMASK;
+
/* Disable interrupts */
- /* We disable interrupts in the PRIMASK register instead of masking with C_MASKINTS,
- * This is probably the same issue as Cortex-M3 Errata 377493:
- * C_MASKINTS in parallel with disabled interrupts can cause local faults to not be taken. */
- buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_PRIMASK].value, 0, 32, 1);
- armv7m->core_cache->reg_list[ARMV7M_PRIMASK].dirty = 1;
- armv7m->core_cache->reg_list[ARMV7M_PRIMASK].valid = 1;
+ /* We disable interrupts in the PRIMASK register instead of
+ * masking with C_MASKINTS. This is probably the same issue
+ * as Cortex-M3 Erratum 377493 (fixed in r1p0): C_MASKINTS
+ * in parallel with disabled interrupts can cause local faults
+ * to not be taken.
+ *
+ * REVISIT this clearly breaks non-debug execution, since the
+ * PRIMASK register state isn't saved/restored... workaround
+ * by never resuming app code after debug execution.
+ */
+ buf_set_u32(r->value, 0, 1, 1);
+ r->dirty = true;
+ r->valid = true;
/* Make sure we are in Thumb mode */
- buf_set_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32,
- buf_get_u32(armv7m->core_cache->reg_list[ARMV7M_xPSR].value, 0, 32) | (1 << 24));
- armv7m->core_cache->reg_list[ARMV7M_xPSR].dirty = 1;
- armv7m->core_cache->reg_list[ARMV7M_xPSR].valid = 1;
+ r = armv7m->core_cache->reg_list + ARMV7M_xPSR;
+ buf_set_u32(r->value, 24, 1, 1);
+ r->dirty = true;
+ r->valid = true;
}
/* current = 1: continue on current pc, otherwise continue at <address> */
+ r = armv7m->core_cache->reg_list + 15;
if (!current)
{
- buf_set_u32(armv7m->core_cache->reg_list[15].value, 0, 32, address);
- armv7m->core_cache->reg_list[15].dirty = 1;
- armv7m->core_cache->reg_list[15].valid = 1;
+ buf_set_u32(r->value, 0, 32, address);
+ r->dirty = true;
+ r->valid = true;
}
- resume_pc = buf_get_u32(armv7m->core_cache->reg_list[15].value, 0, 32);
+ resume_pc = buf_get_u32(r->value, 0, 32);
armv7m_restore_context(target);
@@ -639,6 +692,7 @@ static int cortex_m3_step(struct target *target, int current,
struct armv7m_common *armv7m = &cortex_m3->armv7m;
struct swjdp_common *swjdp = &armv7m->swjdp_info;
struct breakpoint *breakpoint = NULL;
+ struct reg *pc = armv7m->core_cache->reg_list + 15;
if (target->state != TARGET_HALTED)
{
@@ -648,13 +702,12 @@ static int cortex_m3_step(struct target *target, int current,
/* current = 1: continue on current pc, otherwise continue at <address> */
if (!current)
- buf_set_u32(cortex_m3->armv7m.core_cache->reg_list[15].value,
- 0, 32, address);
+ buf_set_u32(pc->value, 0, 32, address);
/* the front-end may request us not to handle breakpoints */
if (handle_breakpoints) {
- breakpoint = breakpoint_find(target, buf_get_u32(armv7m
- ->core_cache->reg_list[15].value, 0, 32));
+ breakpoint = breakpoint_find(target,
+ buf_get_u32(pc->value, 0, 32));
if (breakpoint)
cortex_m3_unset_breakpoint(target, breakpoint);
}
@@ -675,12 +728,16 @@ static int cortex_m3_step(struct target *target, int current,
if (breakpoint)
cortex_m3_set_breakpoint(target, breakpoint);
- LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
+ LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
+ " nvic_icsr = 0x%" PRIx32,
+ cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
cortex_m3_debug_entry(target);
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
- LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
+ LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
+ " nvic_icsr = 0x%" PRIx32,
+ cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
return ERROR_OK;
}
@@ -714,7 +771,8 @@ static int cortex_m3_assert_reset(struct target *target)
{
/* Set/Clear C_MASKINTS in a separate operation */
if (cortex_m3->dcb_dhcsr & C_MASKINTS)
- mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT);
+ mem_ap_write_atomic_u32(swjdp, DCB_DHCSR,
+ DBGKEY | C_DEBUGEN | C_HALT);
/* clear any debug flags before resuming */
cortex_m3_clear_halt(target);
@@ -723,12 +781,14 @@ static int cortex_m3_assert_reset(struct target *target)
cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
/* Enter debug state on reset, cf. end_reset_event() */
- mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
+ mem_ap_write_u32(swjdp, DCB_DEMCR,
+ TRCENA | VC_HARDERR | VC_BUSERR);
}
else
{
/* Enter debug state on reset, cf. end_reset_event() */
- mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
+ mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
+ TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
}
/*
@@ -1311,8 +1371,11 @@ static int cortex_m3_store_core_reg_u32(struct target *target,
retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
if (retval != ERROR_OK)
{
+ struct reg *r;
+
LOG_ERROR("JTAG failure %i", retval);
- armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
+ r = armv7m->core_cache->reg_list + num;
+ r->dirty = r->valid;
return ERROR_JTAG_DEVICE_ERROR;
}
LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
@@ -1455,6 +1518,9 @@ struct dwt_reg {
static struct dwt_reg dwt_base_regs[] = {
{ DWT_CTRL, "dwt_ctrl", 32, },
+ /* NOTE that Erratum 532314 (fixed r2p0) affects CYCCNT: it wrongly
+ * increments while the core is asleep.
+ */
{ DWT_CYCCNT, "dwt_cyccnt", 32, },
/* plus some 8 bit counters, useful for profiling with TPIU */
};
commit abf01895aea06b0e5c79687b68c424e62b205546
Author: David Brownell <dbr...@us...>
Date: Sat Dec 19 22:54:07 2009 -0800
ARM11: recognize ARM11 MPCore
And add my copyright. MPCore is untested, but it's the
only other ARM11 core to care about.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 970738c..67a8409 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -6,6 +6,8 @@
* *
* Copyright (C) 2008 Georg Acher <ac...@in...> *
* *
+ * Copyright (C) 2009 David Brownell *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
@@ -1209,20 +1211,24 @@ static int arm11_examine(struct target *target)
CHECK_RETVAL(jtag_execute_queue());
- switch (device_id & 0x0FFFF000)
+ /* assume the manufacturer id is ok; check the part # */
+ switch ((device_id >> 12) & 0xFFFF)
{
- case 0x07B36000:
+ case 0x7B36:
type = "ARM1136";
break;
- case 0x07B56000:
+ case 0x7B37:
+ type = "ARM11 MPCore";
+ break;
+ case 0x7B56:
type = "ARM1156";
break;
- case 0x07B76000:
+ case 0x7B76:
arm11->arm.core_type = ARM_MODE_MON;
type = "ARM1176";
break;
default:
- LOG_ERROR("'target arm11' expects IDCODE 0x*7B*7****");
+ LOG_ERROR("unexpected ARM11 ID code");
return ERROR_FAIL;
}
LOG_INFO("found %s", type);
-----------------------------------------------------------------------
Summary of changes:
src/target/arm11.c | 16 ++++--
src/target/cortex_m3.c | 156 ++++++++++++++++++++++++++++++++++--------------
2 files changed, 122 insertions(+), 50 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Øyvind H. <go...@us...> - 2009-12-20 19:24:33
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 0df5d1eb3c3a640c34de52787c4a70c07b53535f (commit)
from b72bfabf0dc697e6445c4ed3dba632b164a006e1 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 0df5d1eb3c3a640c34de52787c4a70c07b53535f
Author: Antonio Borneo <bor...@gm...>
Date: Mon Dec 21 01:30:18 2009 +0800
arm7_9: Support VINITHI signal
Command "reset halt" checks if PC properly resets, issueing warning:
"PC was not 0. Does this target need srst_pulls_trst?".
Checking PC against 0 is not always correct.
Removed PC value check, as suggested by Ãyvind Harboe.
Signed-off-by: Antonio Borneo <bor...@gm...>
Signed-off-by: U-PROPRIET-28D9DF\PROPRIETAIRE <PROPRIETAIRE@propriet-28d9df.(none)>
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 280704e..e596980 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -889,34 +889,11 @@ int arm7_9_poll(struct target *target)
}
if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
{
- int check_pc = 0;
- if (target->state == TARGET_RESET)
- {
- if (target->reset_halt)
- {
- enum reset_types jtag_reset_config = jtag_get_reset_config();
- if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
- {
- check_pc = 1;
- }
- }
- }
-
target->state = TARGET_HALTED;
if ((retval = arm7_9_debug_entry(target)) != ERROR_OK)
return retval;
- if (check_pc)
- {
- struct reg *reg = register_get_by_name(target->reg_cache, "pc", 1);
- uint32_t t=*((uint32_t *)reg->value);
- if (t != 0)
- {
- LOG_ERROR("PC was not 0. Does this target need srst_pulls_trst?");
- }
- }
-
if (arm_semihosting(target, &retval) != 0)
return retval;
-----------------------------------------------------------------------
Summary of changes:
src/target/arm7_9_common.c | 23 -----------------------
1 files changed, 0 insertions(+), 23 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-12-20 00:44:38
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via b72bfabf0dc697e6445c4ed3dba632b164a006e1 (commit)
from 3ac2a440419a52752a5e11eba8ab2722a1fe73bf (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit b72bfabf0dc697e6445c4ed3dba632b164a006e1
Author: David Brownell <dbr...@us...>
Date: Sat Dec 19 15:43:55 2009 -0800
cygwin build fixes
and shrink some too-long lines
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/flash/nand/at91sam9.c b/src/flash/nand/at91sam9.c
index 7cfd763..5cfbb0a 100644
--- a/src/flash/nand/at91sam9.c
+++ b/src/flash/nand/at91sam9.c
@@ -414,12 +414,16 @@ static int at91sam9_read_page(struct nand_device *nand, uint32_t page,
// attempt recovery
uint32_t parity;
- target_read_u32(target, info->ecc + AT91C_ECCx_PR, &parity);
+ target_read_u32(target,
+ info->ecc + AT91C_ECCx_PR,
+ &parity);
uint32_t word = (parity & 0x0000FFF0) >> 4;
uint32_t bit = parity & 0x0F;
data[word] ^= (0x1) << bit;
- LOG_INFO("Data word %d, bit %d corrected.", word, bit);
+ LOG_INFO("Data word %d, bit %d corrected.",
+ (unsigned) word,
+ (unsigned) bit);
}
}
diff --git a/src/flash/nor/core.c b/src/flash/nor/core.c
index 1873dee..67fd78b 100644
--- a/src/flash/nor/core.c
+++ b/src/flash/nor/core.c
@@ -281,7 +281,8 @@ int default_flash_blank_check(struct flash_bank *bank)
}
/* erase given flash region, selects proper bank according to target and address */
-static int flash_iterate_address_range(struct target *target, uint32_t addr, uint32_t length,
+static int flash_iterate_address_range(struct target *target,
+ uint32_t addr, uint32_t length,
int (*callback)(struct flash_bank *bank, int first, int last))
{
struct flash_bank *c;
@@ -344,8 +345,8 @@ static int flash_iterate_address_range(struct target *target, uint32_t addr, uin
if (first == -1 || last == -1) {
LOG_ERROR("address range 0x%8.8x .. 0x%8.8x "
"is not sector-aligned",
- (unsigned) c->base + addr,
- (unsigned) last_addr - 1);
+ (unsigned) (c->base + addr),
+ (unsigned) (last_addr - 1));
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
}
@@ -357,7 +358,8 @@ static int flash_iterate_address_range(struct target *target, uint32_t addr, uin
return callback(c, first, last);
}
-int flash_erase_address_range(struct target *target, uint32_t addr, uint32_t length)
+int flash_erase_address_range(struct target *target,
+ uint32_t addr, uint32_t length)
{
return flash_iterate_address_range(target,
addr, length, &flash_driver_erase);
-----------------------------------------------------------------------
Summary of changes:
src/flash/nand/at91sam9.c | 8 ++++++--
src/flash/nor/core.c | 10 ++++++----
2 files changed, 12 insertions(+), 6 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-12-19 22:34:42
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 3ac2a440419a52752a5e11eba8ab2722a1fe73bf (commit)
via 28f8e9dfb7bfaf87957c95790c3ffe5d9fbd8834 (commit)
via abe8b43755fdbc4fe92b966c48b367159deff226 (commit)
via 64934d9204dc854d40893634a66e29ece09ad578 (commit)
via e25819645ee2beb0818a79006eed9c9cedaaf5bb (commit)
via 9abad965ab358c1d598f1354842967cad637b284 (commit)
via bfadd79965cc448a75b4f51abaf9523c4ec0ae26 (commit)
from 3f18900b19f49a84ba9df56f2e089c255e610011 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 3ac2a440419a52752a5e11eba8ab2722a1fe73bf
Author: Dean Glazeski <dn...@gm...>
Date: Wed Dec 9 12:40:54 2009 -0600
AT91SAM9 NAND flash driver.
This creates the TCL interface for configuring an AT91SAM9 NAND flash
controller and implements the necessary functions to correctly work with
a NAND flash device connected to the chip. This includes updates to the
driver list and the Makefile.am to support building the driver and also
houses the documentation update in openocd.texi.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index d9cb4ea..4244a1e 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4812,6 +4812,41 @@ As noted above, the @command{nand device} command allows
driver-specific options and behaviors.
Some controllers also activate controller-specific commands.
+@deffn {NAND Driver} at91sam9
+This driver handles the NAND controllers found on AT91SAM9 family chips from
+Atmel. It takes two extra parameters: address of the NAND chip;
+address of the ECC controller.
+@example
+nand device $NANDFLASH at91sam9 $CHIPNAME 0x40000000 0xfffffe800
+@end example
+AT91SAM9 chips support single-bit ECC hardware. The @code{write_page} and
+@code{read_page} methods are used to utilize the ECC hardware unless they are
+disabled by using the @command{nand raw_access} command. There are four
+additional commands that are needed to fully configure the AT91SAM9 NAND
+controller. Two are optional; most boards use the same wiring for ALE/CLE:
+@deffn Command {at91sam9 cle} num addr_line
+Configure the address line used for latching commands. The @var{num}
+parameter is the value shown by @command{nand list}.
+@end deffn
+@deffn Command {at91sam9 ale} num addr_line
+Configure the address line used for latching addresses. The @var{num}
+parameter is the value shown by @command{nand list}.
+@end deffn
+
+For the next two commands, it is assumed that the pins have already been
+properly configured for input or output.
+@deffn Command {at91sam9 rdy_busy} num pio_base_addr pin
+Configure the RDY/nBUSY input from the NAND device. The @var{num}
+parameter is the value shown by @command{nand list}. @var{pio_base_addr}
+is the base address of the PIO controller and @var{pin} is the pin number.
+@end deffn
+@deffn Command {at91sam9 ce} num pio_base_addr pin
+Configure the chip enable input to the NAND device. The @var{num}
+parameter is the value shown by @command{nand list}. @var{pio_base_addr}
+is the base address of the PIO controller and @var{pin} is the pin number.
+@end deffn
+@end deffn
+
@deffn {NAND Driver} davinci
This driver handles the NAND controllers found on DaVinci family
chips from Texas Instruments.
diff --git a/src/flash/nand/Makefile.am b/src/flash/nand/Makefile.am
index f3033b8..bb9998e 100644
--- a/src/flash/nand/Makefile.am
+++ b/src/flash/nand/Makefile.am
@@ -24,7 +24,8 @@ NAND_DRIVERS = \
s3c2410.c \
s3c2412.c \
s3c2440.c \
- s3c2443.c
+ s3c2443.c \
+ at91sam9.c
noinst_HEADERS = \
arm_io.h \
diff --git a/src/flash/nand/at91sam9.c b/src/flash/nand/at91sam9.c
new file mode 100644
index 0000000..7cfd763
--- /dev/null
+++ b/src/flash/nand/at91sam9.c
@@ -0,0 +1,750 @@
+/*
+ * Copyright (C) 2009 by Dean Glazeski
+ * dn...@gm...
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the
+ * Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include <target/arm.h>
+#include <helper/log.h>
+#include "imp.h"
+#include "arm_io.h"
+
+#define AT91C_PIOx_SODR (0x30) /**< Offset to PIO SODR. */
+#define AT91C_PIOx_CODR (0x34) /**< Offset to PIO CODR. */
+#define AT91C_PIOx_PDSR (0x3C) /**< Offset to PIO PDSR. */
+#define AT91C_ECCx_CR (0x00) /**< Offset to ECC CR. */
+#define AT91C_ECCx_SR (0x08) /**< Offset to ECC SR. */
+#define AT91C_ECCx_PR (0x0C) /**< Offset to ECC PR. */
+#define AT91C_ECCx_NPR (0x10) /**< Offset to ECC NPR. */
+
+/**
+ * Representation of a pin on an AT91SAM9 chip.
+ */
+struct at91sam9_pin {
+ /** Target this pin is on. */
+ struct target *target;
+
+ /** Address of the PIO controller. */
+ uint32_t pioc;
+
+ /** Pin number. */
+ uint32_t num;
+};
+
+/**
+ * Private data for the controller that is stored in the NAND device structure.
+ */
+struct at91sam9_nand {
+ /** Target the NAND is attached to. */
+ struct target *target;
+
+ /** Address of the ECC controller for NAND. */
+ uint32_t ecc;
+
+ /** Address data is written to. */
+ uint32_t data;
+
+ /** Address commands are written to. */
+ uint32_t cmd;
+
+ /** Address addresses are written to. */
+ uint32_t addr;
+
+ /** I/O structure for hosted reads/writes. */
+ struct arm_nand_data io;
+
+ /** Pin representing the ready/~busy line. */
+ struct at91sam9_pin busy;
+
+ /** Pin representing the chip enable. */
+ struct at91sam9_pin ce;
+};
+
+/**
+ * Checks if the target is halted and prints an error message if it isn't.
+ *
+ * @param target Target to be checked.
+ * @param label String label for where function is called from.
+ * @return True if the target is halted.
+ */
+static int at91sam9_halted(struct target *target, const char *label)
+{
+ if (target->state == TARGET_HALTED)
+ return true;
+
+ LOG_ERROR("Target must be halted to use NAND controller (%s)", label);
+ return false;
+}
+
+/**
+ * Initialize the AT91SAM9 NAND controller.
+ *
+ * @param nand NAND device the controller is attached to.
+ * @return Success or failure of initialization.
+ */
+static int at91sam9_init(struct nand_device *nand)
+{
+ struct at91sam9_nand *info = nand->controller_priv;
+ struct target *target = info->target;
+
+ if (!at91sam9_halted(target, "init")) {
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ return ERROR_OK;
+}
+
+/**
+ * Enable NAND device attached to a controller.
+ *
+ * @param info NAND controller information for controlling NAND device.
+ * @return Success or failure of the enabling.
+ */
+static int at91sam9_enable(struct at91sam9_nand *info)
+{
+ struct target *target = info->target;
+
+ return target_write_u32(target, info->ce.pioc + AT91C_PIOx_CODR, 1 << info->ce.num);
+}
+
+/**
+ * Disable NAND device attached to a controller.
+ *
+ * @param info NAND controller information for controlling NAND device.
+ * @return Success or failure of the disabling.
+ */
+static int at91sam9_disable(struct at91sam9_nand *info)
+{
+ struct target *target = info->target;
+
+ return target_write_u32(target, info->ce.pioc + AT91C_PIOx_SODR, 1 << info->ce.num);
+}
+
+/**
+ * Send a command to the NAND device.
+ *
+ * @param nand NAND device to write the command to.
+ * @param command Command to be written.
+ * @return Success or failure of writing the command.
+ */
+static int at91sam9_command(struct nand_device *nand, uint8_t command)
+{
+ struct at91sam9_nand *info = nand->controller_priv;
+ struct target *target = info->target;
+
+ if (!at91sam9_halted(target, "command")) {
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ at91sam9_enable(info);
+
+ return target_write_u8(target, info->cmd, command);
+}
+
+/**
+ * Reset the AT91SAM9 NAND controller.
+ *
+ * @param nand NAND device to be reset.
+ * @return Success or failure of reset.
+ */
+static int at91sam9_reset(struct nand_device *nand)
+{
+ struct at91sam9_nand *info = nand->controller_priv;
+
+ if (!at91sam9_halted(info->target, "reset")) {
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ return at91sam9_disable(info);
+}
+
+/**
+ * Send an address to the NAND device attached to an AT91SAM9 NAND controller.
+ *
+ * @param nand NAND device to send the address to.
+ * @param address Address to be sent.
+ * @return Success or failure of sending the address.
+ */
+static int at91sam9_address(struct nand_device *nand, uint8_t address)
+{
+ struct at91sam9_nand *info = nand->controller_priv;
+ struct target *target = info->target;
+
+ if (!at91sam9_halted(info->target, "address")) {
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ return target_write_u8(target, info->addr, address);
+}
+
+/**
+ * Read data directly from the NAND device attached to an AT91SAM9 NAND
+ * controller.
+ *
+ * @param nand NAND device to read from.
+ * @param data Pointer to where the data should be put.
+ * @return Success or failure of reading the data.
+ */
+static int at91sam9_read_data(struct nand_device *nand, void *data)
+{
+ struct at91sam9_nand *info = nand->controller_priv;
+ struct target *target = info->target;
+
+ if (!at91sam9_halted(info->target, "read data")) {
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ return target_read_u8(target, info->data, data);
+}
+
+/**
+ * Write data directly to the NAND device attached to an AT91SAM9 NAND
+ * controller.
+ *
+ * @param nand NAND device to be written to.
+ * @param data Data to be written.
+ * @return Success or failure of the data write.
+ */
+static int at91sam9_write_data(struct nand_device *nand, uint16_t data)
+{
+ struct at91sam9_nand *info = nand->controller_priv;
+ struct target *target = info->target;
+
+ if (!at91sam9_halted(target, "write data")) {
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ return target_write_u8(target, info->data, data);
+}
+
+/**
+ * Determine if the NAND device is ready by looking at the ready/~busy pin.
+ *
+ * @param nand NAND device to check.
+ * @param timeout Time in milliseconds to wait for NAND to be ready.
+ * @return True if the NAND is ready in the timeout period.
+ */
+static int at91sam9_nand_ready(struct nand_device *nand, int timeout)
+{
+ struct at91sam9_nand *info = nand->controller_priv;
+ struct target *target = info->target;
+ uint32_t status;
+
+ if (!at91sam9_halted(target, "nand ready")) {
+ return 0;
+ }
+
+ do {
+ target_read_u32(target, info->busy.pioc + AT91C_PIOx_PDSR, &status);
+
+ if (status & (1 << info->busy.num)) {
+ return 1;
+ }
+
+ alive_sleep(1);
+ } while (timeout-- > 0);
+
+ return 0;
+}
+
+/**
+ * Read a block of data from the NAND device attached to an AT91SAM9. This
+ * utilizes the ARM hosted NAND read function.
+ *
+ * @param nand NAND device to read from.
+ * @param data Pointer to where the read data should be placed.
+ * @param size Size of the data being read.
+ * @return Success or failure of the hosted read.
+ */
+static int at91sam9_read_block_data(struct nand_device *nand, uint8_t *data, int size)
+{
+ struct at91sam9_nand *info = nand->controller_priv;
+ struct arm_nand_data *io = &info->io;
+ int status;
+
+ if (!at91sam9_halted(info->target, "read block")) {
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ io->chunk_size = nand->page_size;
+ status = arm_nandread(io, data, size);
+
+ return status;
+}
+
+/**
+ * Write a block of data to a NAND device attached to an AT91SAM9. This uses
+ * the ARM hosted write function to write the data.
+ *
+ * @param nand NAND device to write to.
+ * @param data Data to be written to device.
+ * @param size Size of the data being written.
+ * @return Success or failure of the hosted write.
+ */
+static int at91sam9_write_block_data(struct nand_device *nand, uint8_t *data, int size)
+{
+ struct at91sam9_nand *info = nand->controller_priv;
+ struct arm_nand_data *io = &info->io;
+ int status;
+
+ if (!at91sam9_halted(info->target, "write block")) {
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ io->chunk_size = nand->page_size;
+ status = arm_nandwrite(io, data, size);
+
+ return status;
+}
+
+/**
+ * Initialize the ECC controller on the AT91SAM9.
+ *
+ * @param target Target to configure ECC on.
+ * @param info NAND controller information for where the ECC is.
+ * @return Success or failure of initialization.
+ */
+static int at91sam9_ecc_init(struct target *target, struct at91sam9_nand *info)
+{
+ if (!info->ecc) {
+ LOG_ERROR("ECC controller address must be set when not reading raw NAND data");
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ // reset ECC parity registers
+ return target_write_u32(target, info->ecc + AT91C_ECCx_CR, 1);
+}
+
+/**
+ * Initialize an area for the OOB based on whether a user is requesting the OOB
+ * data. This determines the size of the OOB and allocates the space in case
+ * the user has not requested the OOB data.
+ *
+ * @param nand NAND device we are creating an OOB for.
+ * @param oob Pointer to the user supplied OOB area.
+ * @param size Size of the OOB.
+ * @return Pointer to an area to store OOB data.
+ */
+static uint8_t * at91sam9_oob_init(struct nand_device *nand, uint8_t *oob, uint32_t *size)
+{
+ if (!oob) {
+ // user doesn't want OOB, allocate it
+ if (nand->page_size == 512) {
+ *size = 16;
+ } else if (nand->page_size == 2048) {
+ *size = 64;
+ }
+
+ oob = malloc(*size);
+ if (!oob) {
+ LOG_ERROR("Unable to allocate space for OOB");
+ }
+
+ memset(oob, 0xFF, *size);
+ }
+
+ return oob;
+}
+
+/**
+ * Reads a page from an AT91SAM9 NAND controller and verifies using 1-bit ECC
+ * controller on chip. This makes an attempt to correct any errors that are
+ * encountered while reading the page of data.
+ *
+ * @param nand NAND device to read from
+ * @param page Page to be read.
+ * @param data Pointer to where data should be read to.
+ * @param data_size Size of the data to be read.
+ * @param oob Pointer to where OOB data should be read to.
+ * @param oob_size Size of the OOB data to be read.
+ * @return Success or failure of reading the NAND page.
+ */
+static int at91sam9_read_page(struct nand_device *nand, uint32_t page,
+ uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
+{
+ int retval;
+ struct at91sam9_nand *info = nand->controller_priv;
+ struct target *target = info->target;
+ uint8_t *oob_data;
+ uint32_t status;
+
+ retval = at91sam9_ecc_init(target, info);
+ if (ERROR_OK != retval) {
+ return retval;
+ }
+
+ retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
+ if (ERROR_OK != retval) {
+ return retval;
+ }
+
+ if (data) {
+ retval = nand_read_data_page(nand, data, data_size);
+ if (ERROR_OK != retval) {
+ return retval;
+ }
+ }
+
+ oob_data = at91sam9_oob_init(nand, oob, &oob_size);
+ retval = nand_read_data_page(nand, oob_data, oob_size);
+ if (ERROR_OK == retval && data) {
+ target_read_u32(target, info->ecc + AT91C_ECCx_SR, &status);
+ if (status & 1) {
+ LOG_ERROR("Error detected!");
+ if (status & 4) {
+ LOG_ERROR("Multiple errors encountered; unrecoverable!");
+ } else {
+ // attempt recovery
+ uint32_t parity;
+
+ target_read_u32(target, info->ecc + AT91C_ECCx_PR, &parity);
+ uint32_t word = (parity & 0x0000FFF0) >> 4;
+ uint32_t bit = parity & 0x0F;
+
+ data[word] ^= (0x1) << bit;
+ LOG_INFO("Data word %d, bit %d corrected.", word, bit);
+ }
+ }
+
+ if (status & 2) {
+ // we could write back correct ECC data
+ LOG_ERROR("Error in ECC bytes detected");
+ }
+ }
+
+ if (!oob) {
+ // if it wasn't asked for, free it
+ free(oob_data);
+ }
+
+ return retval;
+}
+
+/**
+ * Write a page of data including 1-bit ECC information to a NAND device
+ * attached to an AT91SAM9 controller. If there is OOB data to be written,
+ * this will ignore the computed ECC from the ECC controller.
+ *
+ * @param nand NAND device to write to.
+ * @param page Page to write.
+ * @param data Pointer to data being written.
+ * @param data_size Size of the data being written.
+ * @param oob Pointer to OOB data being written.
+ * @param oob_size Size of the OOB data.
+ * @return Success or failure of the page write.
+ */
+static int at91sam9_write_page(struct nand_device *nand, uint32_t page,
+ uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
+{
+ struct at91sam9_nand *info = nand->controller_priv;
+ struct target *target = info->target;
+ int retval;
+ uint8_t *oob_data = oob;
+ uint32_t parity, nparity;
+
+ retval = at91sam9_ecc_init(target, info);
+ if (ERROR_OK != retval) {
+ return retval;
+ }
+
+ retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
+ if (ERROR_OK != retval) {
+ return retval;
+ }
+
+ if (data) {
+ retval = nand_write_data_page(nand, data, data_size);
+ if (ERROR_OK != retval) {
+ LOG_ERROR("Unable to write data to NAND device");
+ return retval;
+ }
+ }
+
+ oob_data = at91sam9_oob_init(nand, oob, &oob_size);
+
+ if (!oob) {
+ // no OOB given, so read in the ECC parity from the ECC controller
+ target_read_u32(target, info->ecc + AT91C_ECCx_PR, &parity);
+ target_read_u32(target, info->ecc + AT91C_ECCx_NPR, &nparity);
+
+ oob_data[0] = (uint8_t) parity;
+ oob_data[1] = (uint8_t) (parity >> 8);
+ oob_data[2] = (uint8_t) nparity;
+ oob_data[3] = (uint8_t) (nparity >> 8);
+ }
+
+ retval = nand_write_data_page(nand, oob_data, oob_size);
+
+ if (!oob) {
+ free(oob_data);
+ }
+
+ if (ERROR_OK != retval) {
+ LOG_ERROR("Unable to write OOB data to NAND");
+ return retval;
+ }
+
+ retval = nand_write_finish(nand);
+
+ return retval;
+}
+
+/**
+ * Handle the initial NAND device command for AT91SAM9 controllers. This
+ * initializes much of the controller information struct to be ready for future
+ * reads and writes.
+ */
+NAND_DEVICE_COMMAND_HANDLER(at91sam9_nand_device_command)
+{
+ struct target *target = NULL;
+ unsigned long chip = 0, ecc = 0;
+ struct at91sam9_nand *info = NULL;
+
+ LOG_DEBUG("AT91SAM9 NAND Device Command\n");
+
+ if (CMD_ARGC < 3 || CMD_ARGC > 4) {
+ LOG_ERROR("parameters: %s target chip_addr", CMD_ARGV[0]);
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ target = get_target(CMD_ARGV[1]);
+ if (!target) {
+ LOG_ERROR("invalid target: %s", CMD_ARGV[1]);
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[2], chip);
+ if (chip == 0) {
+ LOG_ERROR("invalid NAND chip address: %s", CMD_ARGV[2]);
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ if (CMD_ARGC == 4) {
+ COMMAND_PARSE_NUMBER(ulong, CMD_ARGV[3], ecc);
+ if (ecc == 0) {
+ LOG_ERROR("invalid ECC controller address: %s", CMD_ARGV[3]);
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+ }
+
+ info = calloc(1, sizeof(*info));
+ if (!info) {
+ LOG_ERROR("unable to allocate space for controller private data");
+ return ERROR_NAND_OPERATION_FAILED;
+ }
+
+ info->target = target;
+ info->data = chip;
+ info->cmd = chip | (1 << 22);
+ info->addr = chip | (1 << 21);
+ info->ecc = ecc;
+
+ nand->controller_priv = info;
+ info->io.target = target;
+ info->io.data = info->data;
+ info->io.op = ARM_NAND_NONE;
+
+ return ERROR_OK;
+}
+
+/**
+ * Handle the AT91SAM9 CLE command for specifying the address line to use for
+ * writing commands to a NAND device.
+ */
+COMMAND_HANDLER(handle_at91sam9_cle_command)
+{
+ struct nand_device *nand = NULL;
+ struct at91sam9_nand *info = NULL;
+ unsigned num, address_line;
+
+ if (CMD_ARGC != 2) {
+ command_print(CMD_CTX, "incorrect number of arguments for 'at91sam9 cle' command");
+ return ERROR_OK;
+ }
+
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
+ nand = get_nand_device_by_num(num);
+ if (!nand) {
+ command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
+ return ERROR_OK;
+ }
+
+ info = nand->controller_priv;
+
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], address_line);
+ info->cmd = info->data | (1 << address_line);
+
+ return ERROR_OK;
+}
+
+/**
+ * Handle the AT91SAM9 ALE command for specifying the address line to use for
+ * writing addresses to the NAND device.
+ */
+COMMAND_HANDLER(handle_at91sam9_ale_command)
+{
+ struct nand_device *nand = NULL;
+ struct at91sam9_nand *info = NULL;
+ unsigned num, address_line;
+
+ if (CMD_ARGC != 2) {
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
+ nand = get_nand_device_by_num(num);
+ if (!nand) {
+ command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
+
+ info = nand->controller_priv;
+
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], address_line);
+ info->addr = info->data | (1 << address_line);
+
+ return ERROR_OK;
+}
+
+/**
+ * Handle the AT91SAM9 RDY/~BUSY command for specifying the pin that watches the
+ * RDY/~BUSY line from the NAND device.
+ */
+COMMAND_HANDLER(handle_at91sam9_rdy_busy_command)
+{
+ struct nand_device *nand = NULL;
+ struct at91sam9_nand *info = NULL;
+ unsigned num, base_pioc, pin_num;
+
+ if (CMD_ARGC != 3) {
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
+ nand = get_nand_device_by_num(num);
+ if (!nand) {
+ command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
+
+ info = nand->controller_priv;
+
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], base_pioc);
+ info->busy.pioc = base_pioc;
+
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], pin_num);
+ info->busy.num = pin_num;
+
+ return ERROR_OK;
+}
+
+/**
+ * Handle the AT91SAM9 CE command for specifying the pin that is used to enable
+ * or disable the NAND device.
+ */
+COMMAND_HANDLER(handle_at91sam9_ce_command)
+{
+ struct nand_device *nand = NULL;
+ struct at91sam9_nand *info = NULL;
+ unsigned num, base_pioc, pin_num;
+
+ if (CMD_ARGC != 3) {
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[0], num);
+ nand = get_nand_device_by_num(num);
+ if (!nand) {
+ command_print(CMD_CTX, "invalid nand device number: %s", CMD_ARGV[0]);
+ return ERROR_COMMAND_ARGUMENT_INVALID;
+ }
+
+ info = nand->controller_priv;
+
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[1], base_pioc);
+ info->ce.pioc = base_pioc;
+
+ COMMAND_PARSE_NUMBER(uint, CMD_ARGV[2], pin_num);
+ info->ce.num = pin_num;
+
+ return ERROR_OK;
+}
+
+static const struct command_registration at91sam9_sub_command_handlers[] = {
+ {
+ .name = "cle",
+ .handler = handle_at91sam9_cle_command,
+ .mode = COMMAND_CONFIG,
+ .help = "set command latch enable address line (default is 22)",
+ .usage = "<device_id> <address_line>",
+ },
+ {
+ .name = "ale",
+ .handler = handle_at91sam9_ale_command,
+ .mode = COMMAND_CONFIG,
+ .help = "set address latch enable address line (default is 21)",
+ .usage = "<device_id> <address_line>",
+ },
+ {
+ .name = "rdy_busy",
+ .handler = handle_at91sam9_rdy_busy_command,
+ .mode = COMMAND_CONFIG,
+ .help = "set the input pin connected to RDY/~BUSY signal (no default)",
+ .usage = "<device_id> <base_pioc> <pin_num>",
+ },
+ {
+ .name = "ce",
+ .handler = handle_at91sam9_ce_command,
+ .mode = COMMAND_CONFIG,
+ .help = "set the output pin connected to chip enable signal (no default)",
+ .usage = "<device_id> <base_pioc> <pin_num>",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration at91sam9_command_handler[] = {
+ {
+ .name = "at91sam9",
+ .mode = COMMAND_ANY,
+ .help = "AT91SAM9 NAND flash controller commands",
+ .chain = at91sam9_sub_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+/**
+ * Structure representing the AT91SAM9 NAND controller.
+ */
+struct nand_flash_controller at91sam9_nand_controller = {
+ .name = "at91sam9",
+ .nand_device_command = at91sam9_nand_device_command,
+ .commands = at91sam9_command_handler,
+ .init = at91sam9_init,
+ .command = at91sam9_command,
+ .reset = at91sam9_reset,
+ .address = at91sam9_address,
+ .read_data = at91sam9_read_data,
+ .write_data = at91sam9_write_data,
+ .nand_ready = at91sam9_nand_ready,
+ .read_block_data = at91sam9_read_block_data,
+ .write_block_data = at91sam9_write_block_data,
+ .read_page = at91sam9_read_page,
+ .write_page = at91sam9_write_page,
+};
diff --git a/src/flash/nand/driver.c b/src/flash/nand/driver.c
index 1ccc4f4..0e174b2 100644
--- a/src/flash/nand/driver.c
+++ b/src/flash/nand/driver.c
@@ -37,6 +37,7 @@ extern struct nand_flash_controller s3c2412_nand_controller;
extern struct nand_flash_controller s3c2440_nand_controller;
extern struct nand_flash_controller s3c2443_nand_controller;
extern struct nand_flash_controller imx31_nand_flash_controller;
+extern struct nand_flash_controller at91sam9_nand_controller;
/* extern struct nand_flash_controller boundary_scan_nand_controller; */
@@ -51,6 +52,7 @@ static struct nand_flash_controller *nand_flash_controllers[] =
&s3c2440_nand_controller,
&s3c2443_nand_controller,
&imx31_nand_flash_controller,
+ &at91sam9_nand_controller,
/* &boundary_scan_nand_controller, */
NULL
};
commit 28f8e9dfb7bfaf87957c95790c3ffe5d9fbd8834
Author: David Brownell <dbr...@us...>
Date: Sat Dec 19 13:24:59 2009 -0800
oocd_trace buildfixes
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/oocd_trace.c b/src/target/oocd_trace.c
index b9615bc..2533c40 100644
--- a/src/target/oocd_trace.c
+++ b/src/target/oocd_trace.c
@@ -238,21 +238,21 @@ static int oocd_trace_start_capture(struct etm_context *etm_ctx)
uint32_t control = 0x1; /* 0x1: enabled */
uint32_t trigger_count;
- if (((etm_ctx->portmode & ETM_PORT_MODE_MASK) != ETM_PORT_NORMAL)
- || ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_4BIT))
+ if (((etm_ctx->control & ETM_PORT_MODE_MASK) != ETM_PORT_NORMAL)
+ || ((etm_ctx->control & ETM_PORT_WIDTH_MASK) != ETM_PORT_4BIT))
{
LOG_DEBUG("OpenOCD + trace only supports normal 4-bit ETM mode");
return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
}
- if ((etm_ctx->portmode & ETM_PORT_CLOCK_MASK) == ETM_PORT_HALF_CLOCK)
+ if ((etm_ctx->control & ETM_PORT_CLOCK_MASK) == ETM_PORT_HALF_CLOCK)
{
control |= 0x2; /* half rate clock, capture at twice the clock rate */
}
/* OpenOCD + trace holds up to 16 million samples,
* but trigger counts is set in multiples of 16 */
- trigger_count = (1048576 * etm_ctx->trigger_percent) / 100;
+ trigger_count = (1048576 * /* trigger_percent */ 50) / 100;
/* capturing always starts at address zero */
oocd_trace_write_reg(oocd_trace, OOCD_TRACE_ADDRESS, 0x0);
commit abe8b43755fdbc4fe92b966c48b367159deff226
Author: David Brownell <dbr...@us...>
Date: Sat Dec 19 13:09:19 2009 -0800
ETM: add "etm trigger_debug" command
In conjunction with manual register setup, this lets the ETM trigger
cause entry to debug state. It should make it easier to test and
bugfix the ETM code, by enabling non-trace usage and isolating bugs
specific to thef ETM support. (One current issue being that trace
data collection using the ETB doesn't yet behave.)
For example, many ARM9 cores with an ETM should be able to implement
four more (simple) breakpoints and two more (simple) watchpoints than
the EmbeddedICE supports. Or, they should be able to support complex
breakpoints, incorporating ETM sequencer, counters, and/or subroutine
entry/exit criteria int criteria used to trigger debug entry.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/NEWS b/NEWS
index efcf8f6..e122912 100644
--- a/NEWS
+++ b/NEWS
@@ -34,6 +34,7 @@ Target Layer:
- Exposed DWT registers like cycle counter
ETM, ETB
- "trigger_percent" command moved ETM --> ETB
+ - "etm trigger_debug" command added
Flash Layer:
'flash bank' and 'nand device' take <bank_name> as first argument.
diff --git a/doc/openocd.texi b/doc/openocd.texi
index bb3e51a..d9cb4ea 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5512,6 +5512,17 @@ trace stream without an image of the code.
@end itemize
@end deffn
+@deffn Command {etm trigger_debug} (@option{enable}|@option{disable})
+Displays whether ETM triggering debug entry (like a breakpoint) is
+enabled or disabled, after optionally modifying that configuration.
+The default behaviour is @option{disable}.
+Any change takes effect after the next @command{etm start}.
+
+By using script commands to configure ETM registers, you can make the
+processor enter debug state automatically when certain conditions,
+more complex than supported by the breakpoint hardware, happen.
+@end deffn
+
@subsection ETM Trace Operation
After setting up the ETM, you can use it to collect data.
diff --git a/src/target/etm.c b/src/target/etm.c
index a506d1c..d22bc40 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -446,12 +446,15 @@ int etm_setup(struct target *target)
etm_ctrl_value = (etm_ctrl_value
& ~ETM_PORT_WIDTH_MASK
& ~ETM_PORT_MODE_MASK
+ & ~ETM_CTRL_DBGRQ
& ~ETM_PORT_CLOCK_MASK)
| etm_ctx->control;
buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
etm_store_reg(etm_ctrl_reg);
+ etm_ctx->control = etm_ctrl_value;
+
if ((retval = jtag_execute_queue()) != ERROR_OK)
return retval;
@@ -1338,8 +1341,6 @@ COMMAND_HANDLER(handle_etm_tracemode_command)
if (!etm_ctrl_reg)
return ERROR_FAIL;
- etm_get_reg(etm_ctrl_reg);
-
etm->control &= ~TRACEMODE_MASK;
etm->control |= tracemode & TRACEMODE_MASK;
@@ -2016,6 +2017,56 @@ COMMAND_HANDLER(handle_etm_stop_command)
return ERROR_OK;
}
+COMMAND_HANDLER(handle_etm_trigger_debug_command)
+{
+ struct target *target;
+ struct arm *arm;
+ struct etm_context *etm;
+
+ target = get_current_target(CMD_CTX);
+ arm = target_to_arm(target);
+ if (!is_arm(arm))
+ {
+ command_print(CMD_CTX, "ETM: %s isn't an ARM",
+ target_name(target));
+ return ERROR_FAIL;
+ }
+
+ etm = arm->etm;
+ if (!etm)
+ {
+ command_print(CMD_CTX, "ETM: no ETM configured for %s",
+ target_name(target));
+ return ERROR_FAIL;
+ }
+
+ if (CMD_ARGC == 1) {
+ struct reg *etm_ctrl_reg;
+ bool dbgrq;
+
+ etm_ctrl_reg = etm_reg_lookup(etm, ETM_CTRL);
+ if (!etm_ctrl_reg)
+ return ERROR_FAIL;
+
+ COMMAND_PARSE_ENABLE(CMD_ARGV[0], dbgrq);
+ if (dbgrq)
+ etm->control |= ETM_CTRL_DBGRQ;
+ else
+ etm->control &= ~ETM_CTRL_DBGRQ;
+
+ /* etm->control will be written to hardware
+ * the next time an "etm start" is issued.
+ */
+ buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
+ }
+
+ command_print(CMD_CTX, "ETM: %s debug halt",
+ (etm->control & ETM_CTRL_DBGRQ)
+ ? "triggers"
+ : "does not trigger");
+ return ERROR_OK;
+}
+
COMMAND_HANDLER(handle_etm_analyze_command)
{
struct target *target;
@@ -2112,10 +2163,17 @@ static const struct command_registration etm_exec_command_handlers[] = {
.help = "stop ETM trace collection",
},
{
+ .name = "trigger_debug",
+ .handler = handle_etm_trigger_debug_command,
+ .mode = COMMAND_EXEC,
+ .help = "enable/disable debug entry on trigger",
+ .usage = "(enable | disable)",
+ },
+ {
.name = "analyze",
- .handler = &handle_etm_analyze_command,
+ .handler = handle_etm_analyze_command,
.mode = COMMAND_EXEC,
- .help = "anaylze collected ETM trace",
+ .help = "analyze collected ETM trace",
},
{
.name = "image",
commit 64934d9204dc854d40893634a66e29ece09ad578
Author: David Brownell <dbr...@us...>
Date: Sat Dec 19 13:07:26 2009 -0800
ETM: more ETM_CTRL bit cleanup
Change handling of the CYCLE_ACCURATE, BRANCH_OUTPUT, and
TRACE_* flags; also the CONTEXTID size values.
- Convert to symbols matching the actual register bits, instead of
some random *other* bits (and then correcting that abuse).
- Get rid of a now-needless enum.
- Keep those values in etm->control, and remove etm->tracemode.
These values all affect the trace data that's recorded by a trace
pod or in the ETB. I modified the file format used to dump ETB
data; since it's fairly clear nobody can use this mechanism now,
this can't cause anyone trouble.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/etm.c b/src/target/etm.c
index aaa0219..a506d1c 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -1059,7 +1059,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *
ctx->data_half = old_data_half;
}
- if (ctx->tracemode & ETMV1_TRACE_ADDR)
+ if (ctx->control & ETM_CTRL_TRACE_ADDR)
{
uint8_t packet;
int shift = 0;
@@ -1081,7 +1081,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *
}
}
- if (ctx->tracemode & ETMV1_TRACE_DATA)
+ if (ctx->control & ETM_CTRL_TRACE_DATA)
{
if ((instruction.type == ARM_LDM) || (instruction.type == ARM_STM))
{
@@ -1141,7 +1141,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *
/* if the trace was captured with cycle accurate tracing enabled,
* output the number of cycles since the last executed instruction
*/
- if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
+ if (ctx->control & ETM_CTRL_CYCLE_ACCURATE)
{
snprintf(cycles_text, 32, " (%i %s)",
(int)cycles,
@@ -1178,13 +1178,13 @@ static COMMAND_HELPER(handle_etm_tracemode_command_update,
/* what parts of data access are traced? */
if (strcmp(CMD_ARGV[0], "none") == 0)
- tracemode = ETMV1_TRACE_NONE;
+ tracemode = 0;
else if (strcmp(CMD_ARGV[0], "data") == 0)
- tracemode = ETMV1_TRACE_DATA;
+ tracemode = ETM_CTRL_TRACE_DATA;
else if (strcmp(CMD_ARGV[0], "address") == 0)
- tracemode = ETMV1_TRACE_ADDR;
+ tracemode = ETM_CTRL_TRACE_ADDR;
else if (strcmp(CMD_ARGV[0], "all") == 0)
- tracemode = ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR;
+ tracemode = ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR;
else
{
command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[0]);
@@ -1196,16 +1196,16 @@ static COMMAND_HELPER(handle_etm_tracemode_command_update,
switch (context_id)
{
case 0:
- tracemode |= ETMV1_CONTEXTID_NONE;
+ tracemode |= ETM_CTRL_CONTEXTID_NONE;
break;
case 8:
- tracemode |= ETMV1_CONTEXTID_8;
+ tracemode |= ETM_CTRL_CONTEXTID_8;
break;
case 16:
- tracemode |= ETMV1_CONTEXTID_16;
+ tracemode |= ETM_CTRL_CONTEXTID_16;
break;
case 32:
- tracemode |= ETMV1_CONTEXTID_32;
+ tracemode |= ETM_CTRL_CONTEXTID_32;
break;
default:
command_print(CMD_CTX, "invalid option '%s'", CMD_ARGV[1]);
@@ -1215,12 +1215,12 @@ static COMMAND_HELPER(handle_etm_tracemode_command_update,
bool etmv1_cycle_accurate;
COMMAND_PARSE_ENABLE(CMD_ARGV[2], etmv1_cycle_accurate);
if (etmv1_cycle_accurate)
- tracemode |= ETMV1_CYCLE_ACCURATE;
+ tracemode |= ETM_CTRL_CYCLE_ACCURATE;
bool etmv1_branch_output;
COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
if (etmv1_branch_output)
- tracemode |= ETMV1_BRANCH_OUTPUT;
+ tracemode |= ETM_CTRL_BRANCH_OUTPUT;
/* IGNORED:
* - CPRT tracing (coprocessor register transfers)
@@ -1249,7 +1249,7 @@ COMMAND_HANDLER(handle_etm_tracemode_command)
return ERROR_FAIL;
}
- uint32_t tracemode = etm->tracemode;
+ uint32_t tracemode = etm->control;
switch (CMD_ARGC)
{
@@ -1272,39 +1272,39 @@ COMMAND_HANDLER(handle_etm_tracemode_command)
command_print(CMD_CTX, "current tracemode configuration:");
- switch (tracemode & ETMV1_TRACE_MASK)
+ switch (tracemode & ETM_CTRL_TRACE_MASK)
{
- case ETMV1_TRACE_NONE:
+ default:
command_print(CMD_CTX, "data tracing: none");
break;
- case ETMV1_TRACE_DATA:
+ case ETM_CTRL_TRACE_DATA:
command_print(CMD_CTX, "data tracing: data only");
break;
- case ETMV1_TRACE_ADDR:
+ case ETM_CTRL_TRACE_ADDR:
command_print(CMD_CTX, "data tracing: address only");
break;
- case ETMV1_TRACE_DATA | ETMV1_TRACE_ADDR:
+ case ETM_CTRL_TRACE_DATA | ETM_CTRL_TRACE_ADDR:
command_print(CMD_CTX, "data tracing: address and data");
break;
}
- switch (tracemode & ETMV1_CONTEXTID_MASK)
+ switch (tracemode & ETM_CTRL_CONTEXTID_MASK)
{
- case ETMV1_CONTEXTID_NONE:
+ case ETM_CTRL_CONTEXTID_NONE:
command_print(CMD_CTX, "contextid tracing: none");
break;
- case ETMV1_CONTEXTID_8:
+ case ETM_CTRL_CONTEXTID_8:
command_print(CMD_CTX, "contextid tracing: 8 bit");
break;
- case ETMV1_CONTEXTID_16:
+ case ETM_CTRL_CONTEXTID_16:
command_print(CMD_CTX, "contextid tracing: 16 bit");
break;
- case ETMV1_CONTEXTID_32:
+ case ETM_CTRL_CONTEXTID_32:
command_print(CMD_CTX, "contextid tracing: 32 bit");
break;
}
- if (tracemode & ETMV1_CYCLE_ACCURATE)
+ if (tracemode & ETM_CTRL_CYCLE_ACCURATE)
{
command_print(CMD_CTX, "cycle-accurate tracing enabled");
}
@@ -1313,7 +1313,7 @@ COMMAND_HANDLER(handle_etm_tracemode_command)
command_print(CMD_CTX, "cycle-accurate tracing disabled");
}
- if (tracemode & ETMV1_BRANCH_OUTPUT)
+ if (tracemode & ETM_CTRL_BRANCH_OUTPUT)
{
command_print(CMD_CTX, "full branch address output enabled");
}
@@ -1322,8 +1322,15 @@ COMMAND_HANDLER(handle_etm_tracemode_command)
command_print(CMD_CTX, "full branch address output disabled");
}
+#define TRACEMODE_MASK ( \
+ ETM_CTRL_CONTEXTID_MASK \
+ | ETM_CTRL_BRANCH_OUTPUT \
+ | ETM_CTRL_CYCLE_ACCURATE \
+ | ETM_CTRL_TRACE_MASK \
+ )
+
/* only update ETM_CTRL register if tracemode changed */
- if (etm->tracemode != tracemode)
+ if ((etm->control & TRACEMODE_MASK) != tracemode)
{
struct reg *etm_ctrl_reg;
@@ -1333,13 +1340,11 @@ COMMAND_HANDLER(handle_etm_tracemode_command)
etm_get_reg(etm_ctrl_reg);
- buf_set_u32(etm_ctrl_reg->value, 2, 2, tracemode & ETMV1_TRACE_MASK);
- buf_set_u32(etm_ctrl_reg->value, 14, 2, (tracemode & ETMV1_CONTEXTID_MASK) >> 4);
- buf_set_u32(etm_ctrl_reg->value, 12, 1, (tracemode & ETMV1_CYCLE_ACCURATE) >> 8);
- buf_set_u32(etm_ctrl_reg->value, 8, 1, (tracemode & ETMV1_BRANCH_OUTPUT) >> 9);
- etm_store_reg(etm_ctrl_reg);
+ etm->control &= ~TRACEMODE_MASK;
+ etm->control |= tracemode & TRACEMODE_MASK;
- etm->tracemode = tracemode;
+ buf_set_u32(etm_ctrl_reg->value, 0, 32, etm->control);
+ etm_store_reg(etm_ctrl_reg);
/* invalidate old trace data */
etm->capture_status = TRACE_IDLE;
@@ -1351,6 +1356,8 @@ COMMAND_HANDLER(handle_etm_tracemode_command)
etm->trace_depth = 0;
}
+#undef TRACEMODE_MASK
+
return ERROR_OK;
}
@@ -1825,7 +1832,6 @@ COMMAND_HANDLER(handle_etm_dump_command)
fileio_write_u32(&file, etm_ctx->capture_status);
fileio_write_u32(&file, etm_ctx->control);
- fileio_write_u32(&file, etm_ctx->tracemode);
fileio_write_u32(&file, etm_ctx->trace_depth);
for (i = 0; i < etm_ctx->trace_depth; i++)
@@ -1897,7 +1903,6 @@ COMMAND_HANDLER(handle_etm_load_command)
uint32_t tmp;
fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
fileio_read_u32(&file, &tmp); etm_ctx->control = tmp;
- fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
fileio_read_u32(&file, &etm_ctx->trace_depth);
}
etm_ctx->trace_data = malloc(sizeof(struct etmv1_trace_data) * etm_ctx->trace_depth);
diff --git a/src/target/etm.h b/src/target/etm.h
index e4d4685..8a482c1 100644
--- a/src/target/etm.h
+++ b/src/target/etm.h
@@ -89,7 +89,10 @@ enum
ETM_CTRL_POWERDOWN = (1 << 0),
ETM_CTRL_MONITOR_CPRT = (1 << 1),
- // bits 3:2 == trace type (ETMV1_TRACE_* << 2)
+ /* bits 3:2 == trace type */
+ ETM_CTRL_TRACE_DATA = (1 << 2),
+ ETM_CTRL_TRACE_ADDR = (2 << 2),
+ ETM_CTRL_TRACE_MASK = (3 << 2),
/* Port width (bits 21 and 6:4) */
ETM_PORT_4BIT = 0x00,
@@ -116,7 +119,11 @@ enum
ETM_PORT_CLOCK_MASK = (1 << 13),
// bits 15:14 == context ID size used in tracing
- // ETMV1_CONTEXTID_* << 8
+ ETM_CTRL_CONTEXTID_NONE = (0 << 14),
+ ETM_CTRL_CONTEXTID_8 = (1 << 14),
+ ETM_CTRL_CONTEXTID_16 = (2 << 14),
+ ETM_CTRL_CONTEXTID_32 = (3 << 14),
+ ETM_CTRL_CONTEXTID_MASK = (3 << 14),
/* Port modes -- bits 17:16, tied to clocking mode */
ETM_PORT_NORMAL = (0 << 16),
@@ -127,24 +134,6 @@ enum
// bits 31:18 defined in v3.0 and later (e.g. ARM11+)
};
-enum
-{
- /* Data trace */
- ETMV1_TRACE_NONE = 0x00,
- ETMV1_TRACE_DATA = 0x01,
- ETMV1_TRACE_ADDR = 0x02,
- ETMV1_TRACE_MASK = 0x03,
- /* ContextID */
- ETMV1_CONTEXTID_NONE = 0x00,
- ETMV1_CONTEXTID_8 = 0x10,
- ETMV1_CONTEXTID_16 = 0x20,
- ETMV1_CONTEXTID_32 = 0x30,
- ETMV1_CONTEXTID_MASK = 0x30,
- /* Misc */
- ETMV1_CYCLE_ACCURATE = 0x100,
- ETMV1_BRANCH_OUTPUT = 0x200
-};
-
/* forward-declare ETM context */
struct etm_context;
@@ -187,7 +176,6 @@ struct etm_context
struct etmv1_trace_data *trace_data; /* trace data */
uint32_t trace_depth; /* number of cycles to be analyzed, 0 if no data available */
uint32_t control; /* shadow of ETM_CTRL */
- uint32_t tracemode; /* type of info trace contains */
int /*arm_state*/ core_state; /* current core state */
struct image *image; /* source for target opcodes */
uint32_t pipe_index; /* current trace cycle */
commit e25819645ee2beb0818a79006eed9c9cedaaf5bb
Author: David Brownell <dbr...@us...>
Date: Sat Dec 19 13:07:25 2009 -0800
ETM: start cleaning up ETM_CTRL bit handling
Provide better comments for the ETM_CTRL bits; use the correct bit
for half/full clock mode; and define a few more of the bits available
from the earliest ETM versions.
The new bit defintions use ETM_CTRL_* names to match their register
(instead of ETM_PORT_* or ETMV1_*). For clarity, and better matching
to docs, they are defined with bitshifting not pre-computed masks.
Stop abusing typdefs for ETM_CTRL values; such values are not limited
to the enumerated set of individual bit values.
Rename etm->portmode to etm->control ... and start morphing it into a
single generic shadow of ETM_CTRL. Eventually etm->tracemode should
vanish, so we can just write etm->control to ETM_CTRL.
Restore an "if" that somehow got dropped.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/etb.c b/src/target/etb.c
index a789777..fb2dd60 100644
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -579,9 +579,9 @@ static int etb_read_trace(struct etm_context *etm_ctx)
free(etm_ctx->trace_data);
}
- if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
+ if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
etm_ctx->trace_depth = num_frames * 3;
- else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
+ else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
etm_ctx->trace_depth = num_frames * 2;
else
etm_ctx->trace_depth = num_frames;
@@ -590,7 +590,7 @@ static int etb_read_trace(struct etm_context *etm_ctx)
for (i = 0, j = 0; i < num_frames; i++)
{
- if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
+ if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_4BIT)
{
/* trace word j */
etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
@@ -636,7 +636,7 @@ static int etb_read_trace(struct etm_context *etm_ctx)
j += 3;
}
- else if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
+ else if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
{
/* trace word j */
etm_ctx->trace_data[j].pipestat = trace_data[i] & 0x7;
@@ -699,9 +699,9 @@ static int etb_start_capture(struct etm_context *etm_ctx)
uint32_t etb_ctrl_value = 0x1;
uint32_t trigger_count;
- if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
+ if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_DEMUXED)
{
- if ((etm_ctx->portmode & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
+ if ((etm_ctx->control & ETM_PORT_WIDTH_MASK) != ETM_PORT_8BIT)
{
LOG_ERROR("ETB can't run in demultiplexed mode with a 4 or 16 bit port");
return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
@@ -709,7 +709,7 @@ static int etb_start_capture(struct etm_context *etm_ctx)
etb_ctrl_value |= 0x2;
}
- if ((etm_ctx->portmode & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) {
+ if ((etm_ctx->control & ETM_PORT_MODE_MASK) == ETM_PORT_MUXED) {
LOG_ERROR("ETB: can't run in multiplexed mode");
return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
}
diff --git a/src/target/etm.c b/src/target/etm.c
index fff9494..aaa0219 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -435,10 +435,10 @@ int etm_setup(struct target *target)
/* initialize some ETM control register settings */
etm_get_reg(etm_ctrl_reg);
- etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size);
+ etm_ctrl_value = buf_get_u32(etm_ctrl_reg->value, 0, 32);
/* clear the ETM powerdown bit (0) */
- etm_ctrl_value &= ~0x1;
+ etm_ctrl_value &= ~ETM_CTRL_POWERDOWN;
/* configure port width (21,6:4), mode (13,17:16) and
* for older modules clocking (13)
@@ -447,9 +447,9 @@ int etm_setup(struct target *target)
& ~ETM_PORT_WIDTH_MASK
& ~ETM_PORT_MODE_MASK
& ~ETM_PORT_CLOCK_MASK)
- | etm_ctx->portmode;
+ | etm_ctx->control;
- buf_set_u32(etm_ctrl_reg->value, 0, etm_ctrl_reg->size, etm_ctrl_value);
+ buf_set_u32(etm_ctrl_reg->value, 0, 32, etm_ctrl_value);
etm_store_reg(etm_ctrl_reg);
if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -727,7 +727,8 @@ static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
continue;
}
- if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
+ /* FIXME there are more port widths than these... */
+ if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_16BIT)
{
if (ctx->data_half == 0)
{
@@ -741,7 +742,7 @@ static int etmv1_next_packet(struct etm_context *ctx, uint8_t *packet, int apo)
ctx->data_index++;
}
}
- else if ((ctx->portmode & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
+ else if ((ctx->control & ETM_PORT_WIDTH_MASK) == ETM_PORT_8BIT)
{
*packet = ctx->trace_data[ctx->data_index].packet & 0xff;
ctx->data_index++;
@@ -1171,9 +1172,9 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_context *
}
static COMMAND_HELPER(handle_etm_tracemode_command_update,
- etmv1_tracemode_t *mode)
+ uint32_t *mode)
{
- etmv1_tracemode_t tracemode;
+ uint32_t tracemode;
/* what parts of data access are traced? */
if (strcmp(CMD_ARGV[0], "none") == 0)
@@ -1218,6 +1219,7 @@ static COMMAND_HELPER(handle_etm_tracemode_command_update,
bool etmv1_branch_output;
COMMAND_PARSE_ENABLE(CMD_ARGV[3], etmv1_branch_output);
+ if (etmv1_branch_output)
tracemode |= ETMV1_BRANCH_OUTPUT;
/* IGNORED:
@@ -1247,7 +1249,7 @@ COMMAND_HANDLER(handle_etm_tracemode_command)
return ERROR_FAIL;
}
- etmv1_tracemode_t tracemode = etm->tracemode;
+ uint32_t tracemode = etm->tracemode;
switch (CMD_ARGC)
{
@@ -1356,7 +1358,7 @@ COMMAND_HANDLER(handle_etm_config_command)
{
struct target *target;
struct arm *arm;
- etm_portmode_t portmode = 0x0;
+ uint32_t portmode = 0x0;
struct etm_context *etm_ctx;
int i;
@@ -1495,7 +1497,7 @@ COMMAND_HANDLER(handle_etm_config_command)
etm_ctx->target = target;
etm_ctx->trace_data = NULL;
- etm_ctx->portmode = portmode;
+ etm_ctx->control = portmode;
etm_ctx->core_state = ARM_STATE_ARM;
arm->etm = etm_ctx;
@@ -1822,7 +1824,7 @@ COMMAND_HANDLER(handle_etm_dump_command)
}
fileio_write_u32(&file, etm_ctx->capture_status);
- fileio_write_u32(&file, etm_ctx->portmode);
+ fileio_write_u32(&file, etm_ctx->control);
fileio_write_u32(&file, etm_ctx->tracemode);
fileio_write_u32(&file, etm_ctx->trace_depth);
@@ -1894,7 +1896,7 @@ COMMAND_HANDLER(handle_etm_load_command)
{
uint32_t tmp;
fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
- fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
+ fileio_read_u32(&file, &tmp); etm_ctx->control = tmp;
fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
fileio_read_u32(&file, &etm_ctx->trace_depth);
}
diff --git a/src/target/etm.h b/src/target/etm.h
index 78a5996..e4d4685 100644
--- a/src/target/etm.h
+++ b/src/target/etm.h
@@ -78,9 +78,20 @@ struct etm_reg
struct arm_jtag *jtag_info;
};
-typedef enum
+/* Subset of ETM_CTRL bit assignments. Many of these
+ * control the configuration of trace output, which
+ * hooks up either to ETB or to an external device.
+ *
+ * NOTE that these have evolved since the ~v1.3 defns ...
+ */
+enum
{
- /* Port width */
+ ETM_CTRL_POWERDOWN = (1 << 0),
+ ETM_CTRL_MONITOR_CPRT = (1 << 1),
+
+ // bits 3:2 == trace type (ETMV1_TRACE_* << 2)
+
+ /* Port width (bits 21 and 6:4) */
ETM_PORT_4BIT = 0x00,
ETM_PORT_8BIT = 0x10,
ETM_PORT_16BIT = 0x20,
@@ -91,18 +102,32 @@ typedef enum
ETM_PORT_1BIT = 0x00 | (1 << 21),
ETM_PORT_2BIT = 0x10 | (1 << 21),
ETM_PORT_WIDTH_MASK = 0x70 | (1 << 21),
- /* Port modes */
- ETM_PORT_NORMAL = 0x00000,
- ETM_PORT_MUXED = 0x10000,
- ETM_PORT_DEMUXED = 0x20000,
- ETM_PORT_MODE_MASK = 0x30000,
- /* Clocking modes */
- ETM_PORT_FULL_CLOCK = 0x0000,
- ETM_PORT_HALF_CLOCK = 0x1000,
- ETM_PORT_CLOCK_MASK = 0x1000,
-} etm_portmode_t;
-typedef enum
+ ETM_CTRL_FIFOFULL_STALL = (1 << 7),
+ ETM_CTRL_BRANCH_OUTPUT = (1 << 8),
+ ETM_CTRL_DBGRQ = (1 << 9),
+ ETM_CTRL_ETM_PROG = (1 << 10),
+ ETM_CTRL_ETMEN = (1 << 11),
+ ETM_CTRL_CYCLE_ACCURATE = (1 << 12),
+
+ /* Clocking modes -- up to v2.1, bit 13 */
+ ETM_PORT_FULL_CLOCK = (0 << 13),
+ ETM_PORT_HALF_CLOCK = (1 << 13),
+ ETM_PORT_CLOCK_MASK = (1 << 13),
+
+ // bits 15:14 == context ID size used in tracing
+ // ETMV1_CONTEXTID_* << 8
+
+ /* Port modes -- bits 17:16, tied to clocking mode */
+ ETM_PORT_NORMAL = (0 << 16),
+ ETM_PORT_MUXED = (1 << 16),
+ ETM_PORT_DEMUXED = (2 << 16),
+ ETM_PORT_MODE_MASK = (3 << 16),
+
+ // bits 31:18 defined in v3.0 and later (e.g. ARM11+)
+};
+
+enum
{
/* Data trace */
ETMV1_TRACE_NONE = 0x00,
@@ -118,7 +143,7 @@ typedef enum
/* Misc */
ETMV1_CYCLE_ACCURATE = 0x100,
ETMV1_BRANCH_OUTPUT = 0x200
-} etmv1_tracemode_t;
+};
/* forward-declare ETM context */
struct etm_context;
@@ -161,8 +186,8 @@ struct etm_context
trace_status_t capture_status; /* current state of capture run */
struct etmv1_trace_data *trace_data; /* trace data */
uint32_t trace_depth; /* number of cycles to be analyzed, 0 if no data available */
- etm_portmode_t portmode; /* normal, multiplexed or demultiplexed */
- etmv1_tracemode_t tracemode; /* type of info trace contains */
+ uint32_t control; /* shadow of ETM_CTRL */
+ uint32_t tracemode; /* type of info trace contains */
int /*arm_state*/ core_state; /* current core state */
struct image *image; /* source for target opcodes */
uint32_t pipe_index; /* current trace cycle */
commit 9abad965ab358c1d598f1354842967cad637b284
Author: David Brownell <dbr...@us...>
Date: Sat Dec 19 13:06:46 2009 -0800
ETM trigger_percent becomes an ETB command
This command was misplaced; it's not generic to all traceport drivers,
only the ETB supports this kind of configuration. So move it, and
update the relevant documentation.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/NEWS b/NEWS
index 67778ef..efcf8f6 100644
--- a/NEWS
+++ b/NEWS
@@ -32,6 +32,8 @@ Target Layer:
- watchpoint support
Cortex-M3
- Exposed DWT registers like cycle counter
+ ETM, ETB
+ - "trigger_percent" command moved ETM --> ETB
Flash Layer:
'flash bank' and 'nand device' take <bank_name> as first argument.
diff --git a/doc/openocd.texi b/doc/openocd.texi
index cda5be3..bb3e51a 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5512,28 +5512,6 @@ trace stream without an image of the code.
@end itemize
@end deffn
-@deffn Command {etm trigger_percent} [percent]
-This displays, or optionally changes, the trace port driver's
-behavior after the ETM's configured @emph{trigger} event fires.
-It controls how much more trace data is saved after the (single)
-trace trigger becomes active.
-
-@itemize
-@item The default corresponds to @emph{trace around} usage,
-recording 50 percent data before the event and the rest
-afterwards.
-@item The minimum value of @var{percent} is 2 percent,
-recording almost exclusively data before the trigger.
-Such extreme @emph{trace before} usage can help figure out
-what caused that event to happen.
-@item The maximum value of @var{percent} is 100 percent,
-recording data almost exclusively after the event.
-This extreme @emph{trace after} usage might help sort out
-how the event caused trouble.
-@end itemize
-@c REVISIT allow "break" too -- enter debug mode.
-@end deffn
-
@subsection ETM Trace Operation
After setting up the ETM, you can use it to collect data.
@@ -5617,6 +5595,28 @@ to use on-chip ETB memory.
Associates the ETM for @var{target} with the ETB at @var{etb_tap}.
You can see the ETB registers using the @command{reg} command.
@end deffn
+@deffn Command {etb trigger_percent} [percent]
+This displays, or optionally changes, ETB behavior after the
+ETM's configured @emph{trigger} event fires.
+It controls how much more trace data is saved after the (single)
+trace trigger becomes active.
+
+@itemize
+@item The default corresponds to @emph{trace around} usage,
+recording 50 percent data before the event and the rest
+afterwards.
+@item The minimum value of @var{percent} is 2 percent,
+recording almost exclusively data before the trigger.
+Such extreme @emph{trace before} usage can help figure out
+what caused that event to happen.
+@item The maximum value of @var{percent} is 100 percent,
+recording data almost exclusively after the event.
+This extreme @emph{trace after} usage might help sort out
+how the event caused trouble.
+@end itemize
+@c REVISIT allow "break" too -- enter debug mode.
+@end deffn
+
@end deffn
@deffn {Trace Port Driver} oocd_trace
diff --git a/src/target/etb.c b/src/target/etb.c
index 3113eca..a789777 100644
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -402,12 +402,63 @@ COMMAND_HANDLER(handle_etb_config_command)
return ERROR_OK;
}
+COMMAND_HANDLER(handle_etb_trigger_percent_command)
+{
+ struct target *target;
+ struct arm *arm;
+ struct etm_context *etm;
+ struct etb *etb;
+
+ target = get_current_target(CMD_CTX);
+ arm = target_to_arm(target);
+ if (!is_arm(arm))
+ {
+ command_print(CMD_CTX, "ETB: current target isn't an ARM");
+ return ERROR_FAIL;
+ }
+
+ etm = arm->etm;
+ if (!etm) {
+ command_print(CMD_CTX, "ETB: target has no ETM configured");
+ return ERROR_FAIL;
+ }
+ if (etm->capture_driver != &etb_capture_driver) {
+ command_print(CMD_CTX, "ETB: target not using ETB");
+ return ERROR_FAIL;
+ }
+ etb = arm->etm->capture_driver_priv;
+
+ if (CMD_ARGC > 0) {
+ uint32_t new_value;
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_value);
+ if ((new_value < 2) || (new_value > 100))
+ command_print(CMD_CTX,
+ "valid percentages are 2%% to 100%%");
+ else
+ etb->trigger_percent = (unsigned) new_value;
+ }
+
+ command_print(CMD_CTX, "%d percent of tracebuffer fills after trigger",
+ etb->trigger_percent);
+
+ return ERROR_OK;
+}
+
static const struct command_registration etb_config_command_handlers[] = {
{
.name = "config",
.handler = &handle_etb_config_command,
.mode = COMMAND_CONFIG,
- .usage = "<target> <tap>",
+ .usage = "target tap",
+ },
+ {
+ .name = "trigger_percent",
+ .handler = &handle_etb_trigger_percent_command,
+ .mode = COMMAND_EXEC,
+ .help = "percent of trace buffer to be filled "
+ "after the trigger occurs",
+ .usage = "[percent]",
},
COMMAND_REGISTRATION_DONE
};
@@ -435,6 +486,8 @@ static int etb_init(struct etm_context *etm_ctx)
etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
+ etb->trigger_percent = 50;
+
return ERROR_OK;
}
@@ -661,7 +714,7 @@ static int etb_start_capture(struct etm_context *etm_ctx)
return ERROR_ETM_PORTMODE_NOT_SUPPORTED;
}
- trigger_count = (etb->ram_depth * etm_ctx->trigger_percent) / 100;
+ trigger_count = (etb->ram_depth * etb->trigger_percent) / 100;
etb_write_reg(&etb->reg_cache->reg_list[ETB_TRIGGER_COUNTER], trigger_count);
etb_write_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER], 0x0);
diff --git a/src/target/etb.h b/src/target/etb.h
index 49385ee..dfffb68 100644
--- a/src/target/etb.h
+++ b/src/target/etb.h
@@ -44,6 +44,9 @@ struct etb
/* ETB parameters */
uint32_t ram_depth;
uint32_t ram_width;
+
+ /** how much trace buffer to fill after trigger */
+ unsigned trigger_percent;
};
struct etb_reg
diff --git a/src/target/etm.c b/src/target/etm.c
index 9cb647c..fff9494 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -1494,7 +1494,6 @@ COMMAND_HANDLER(handle_etm_config_command)
}
etm_ctx->target = target;
- etm_ctx->trigger_percent = 50;
etm_ctx->trace_data = NULL;
etm_ctx->portmode = portmode;
etm_ctx->core_state = ARM_STATE_ARM;
@@ -1923,47 +1922,6 @@ COMMAND_HANDLER(handle_etm_load_command)
return ERROR_OK;
}
-COMMAND_HANDLER(handle_etm_trigger_percent_command)
-{
- struct target *target;
- struct arm *arm;
- struct etm_context *etm_ctx;
-
- target = get_current_target(CMD_CTX);
- arm = target_to_arm(target);
- if (!is_arm(arm))
- {
- command_print(CMD_CTX, "ETM: current target isn't an ARM");
- return ERROR_FAIL;
- }
-
- etm_ctx = arm->etm;
- if (!etm_ctx)
- {
- command_print(CMD_CTX, "current target doesn't have an ETM configured");
- return ERROR_FAIL;
- }
-
- if (CMD_ARGC > 0)
- {
- uint32_t new_value;
- COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], new_value);
-
- if ((new_value < 2) || (new_value > 100))
- {
- command_print(CMD_CTX, "valid settings are 2%% to 100%%");
- }
- else
- {
- etm_ctx->trigger_percent = new_value;
- }
- }
-
- command_print(CMD_CTX, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
-
- return ERROR_OK;
-}
-
COMMAND_HANDLER(handle_etm_start_command)
{
struct target *target;
@@ -2129,13 +2087,6 @@ static const struct command_registration etm_exec_command_handlers[] = {
.help = "display info about the current target's ETM",
},
{
- .name = "trigger_percent",
- .handler = &handle_etm_trigger_percent_command,
- .mode = COMMAND_EXEC,
- .help = "amount (<percent>) of trace buffer "
- "to be filled after the trigger occured",
- },
- {
.name = "status",
.handler = &handle_etm_status_command,
.mode = COMMAND_EXEC,
diff --git a/src/target/etm.h b/src/target/etm.h
index 5b4d5e1..78a5996 100644
--- a/src/target/etm.h
+++ b/src/target/etm.h
@@ -158,7 +158,6 @@ struct etm_context
struct reg_cache *reg_cache; /* ETM register cache */
struct etm_capture_driver *capture_driver; /* driver used to access ETM data */
void *capture_driver_priv; /* capture driver private data */
- uint32_t trigger_percent; /* how much trace buffer to fill after trigger */
trace_status_t capture_status; /* current state of capture run */
struct etmv1_trace_data *trace_data; /* trace data */
uint32_t trace_depth; /* number of cycles to be analyzed, 0 if no data available */
commit bfadd79965cc448a75b4f51abaf9523c4ec0ae26
Author: David Brownell <dbr...@us...>
Date: Sat Dec 19 13:01:30 2009 -0800
NEWS: mention libftdi 0.17
diff --git a/NEWS b/NEWS
index 2d01f00..67778ef 100644
--- a/NEWS
+++ b/NEWS
@@ -60,6 +60,8 @@ Documentation:
Build and Release:
Use --enable-doxygen-pdf to build PDF developer documentation.
+ Consider upgrading to libftdi 0.17 if you use that library; it
+ includes bugfixes which improve FT2232H support.
For more details about what has changed since the last release,
see the git repository history. With gitweb, you can browse that
-----------------------------------------------------------------------
Summary of changes:
NEWS | 5 +
doc/openocd.texi | 84 ++++--
s...
[truncated message content] |
|
From: David B. <dbr...@us...> - 2009-12-18 20:58:26
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 3f18900b19f49a84ba9df56f2e089c255e610011 (commit)
via 013b05f7f813f0d0c15a6bb20068e9423a28bd0d (commit)
via 7641934197abbd851127afcb0b7cebc30242f717 (commit)
via 12b8c7b89b021c882e68bb0e28863c802fe36ac4 (commit)
from 85a4136d0baccf5c3b8f717710584f7faed0ca30 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 3f18900b19f49a84ba9df56f2e089c255e610011
Author: David Brownell <dbr...@us...>
Date: Fri Dec 18 10:16:52 2009 -0800
NOR FLASH: only erase/unlock whole sectors
Much to my surprise, I observed a "flash erase_address ..."
command erasing data which I said should not be erased.
The issue turns out to be generic NOR flash code which was
silently, and rather dangerously, morphing partial-sector
references into unrequested whole-sector ones.
This patch removes that low-level morphing. If desired, it
can and should be done in higher level code. (We might need
to fix some stuff in the GDB server code.)
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/NEWS b/NEWS
index 498797b..2d01f00 100644
--- a/NEWS
+++ b/NEWS
@@ -39,6 +39,8 @@ Flash Layer:
- <bank_name>: reference the bank with its defined name
- <driver_name>[.N]: reference the driver's Nth bank
New 'nand verify' command to check bank against an image file.
+ The "flash erase_address" command now rejects partial sectors;
+ previously it would silently erase extra data.
Board, Target, and Interface Configuration Scripts:
ARM9
diff --git a/src/flash/nor/core.c b/src/flash/nor/core.c
index c2ea134..1873dee 100644
--- a/src/flash/nor/core.c
+++ b/src/flash/nor/core.c
@@ -279,11 +279,13 @@ int default_flash_blank_check(struct flash_bank *bank)
return ERROR_OK;
}
+
/* erase given flash region, selects proper bank according to target and address */
static int flash_iterate_address_range(struct target *target, uint32_t addr, uint32_t length,
int (*callback)(struct flash_bank *bank, int first, int last))
{
struct flash_bank *c;
+ uint32_t last_addr = addr + length; /* first address AFTER end */
int first = -1;
int last = -1;
int i;
@@ -306,26 +308,52 @@ static int flash_iterate_address_range(struct target *target, uint32_t addr, uin
return callback(c, 0, c->num_sectors - 1);
}
- /* check whether it fits */
+ /* check whether it all fits in this bank */
if (addr + length - 1 > c->base + c->size - 1)
return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ /** @todo: handle erasures that cross into adjacent banks */
+
addr -= c->base;
for (i = 0; i < c->num_sectors; i++)
{
- /* check whether sector overlaps with the given range and is not yet erased */
- if (addr < c->sectors[i].offset + c->sectors[i].size && addr + length > c->sectors[i].offset && c->sectors[i].is_erased != 1) {
- /* if first is not set yet then this is the first sector */
- if (first == -1)
+ struct flash_sector *f = c->sectors + i;
+
+ /* start only on a sector boundary */
+ if (first < 0) {
+ /* is this the first sector? */
+ if (addr == f->offset)
first = i;
- last = i; /* and it is the last one so far in any case */
+ else if (addr < f->offset)
+ break;
}
+
+ /* is this (also?) the last sector? */
+ if (last_addr == f->offset + f->size) {
+ last = i;
+ break;
+ }
+
+ /* MUST finish on a sector boundary */
+ if (last_addr <= f->offset)
+ break;
}
- if (first == -1 || last == -1)
- return ERROR_OK;
+ /* invalid start or end address? */
+ if (first == -1 || last == -1) {
+ LOG_ERROR("address range 0x%8.8x .. 0x%8.8x "
+ "is not sector-aligned",
+ (unsigned) c->base + addr,
+ (unsigned) last_addr - 1);
+ return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ }
+ /* The NOR driver may trim this range down, based on
+ * whether or not a given sector is already erased.
+ *
+ * REVISIT should *we* trim it... ?
+ */
return callback(c, first, last);
}
commit 013b05f7f813f0d0c15a6bb20068e9423a28bd0d
Author: David Brownell <dbr...@us...>
Date: Fri Dec 18 10:09:35 2009 -0800
Subject: flash fill[bwh] should use bulk i/o
It's currently allocating a big buffer but writing it out in
units of sizeof(host's pointer) ... sub-optimal.
Plus fix a couple minor coding style goofs.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
index 1e933b2..b5e1b2c 100644
--- a/src/flash/nor/tcl.c
+++ b/src/flash/nor/tcl.c
@@ -534,14 +534,16 @@ COMMAND_HANDLER(handle_flash_fill_command)
for (wrote = 0; wrote < (count*wordsize); wrote += cur_size)
{
- cur_size = MIN((count*wordsize - wrote), sizeof(chunk));
struct flash_bank *bank;
+
bank = get_flash_bank_by_addr(target, address);
if (bank == NULL)
{
retval = ERROR_FAIL;
goto done;
}
+
+ cur_size = MIN((count * wordsize - wrote), chunksize);
err = flash_driver_write(bank, chunk, address - bank->base + wrote, cur_size);
if (err != ERROR_OK)
{
@@ -576,7 +578,7 @@ COMMAND_HANDLER(handle_flash_fill_command)
duration_elapsed(&bench), duration_kbps(&bench, wrote));
}
- done:
+done:
free(readback);
free(chunk);
commit 7641934197abbd851127afcb0b7cebc30242f717
Author: David Brownell <dbr...@us...>
Date: Fri Dec 18 09:59:40 2009 -0800
stellaris: fix min buffer length checks
Word count == size/4; cope. And increase buf_min so it's large
enough to cover the overhead in my tests.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c
index 51fe677..f414ca6 100644
--- a/src/flash/nor/stellaris.c
+++ b/src/flash/nor/stellaris.c
@@ -826,10 +826,10 @@ static int stellaris_write_block(struct flash_bank *bank,
int retval = ERROR_OK;
/* power of two, and multiple of word size */
- static const unsigned buf_min = 32;
+ static const unsigned buf_min = 128;
/* for small buffers it's faster not to download an algorithm */
- if (wcount < buf_min)
+ if (wcount * 4 < buf_min)
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32 "",
@@ -843,11 +843,8 @@ static int stellaris_write_block(struct flash_bank *bank,
};
/* plus a buffer big enough for this data */
- if (wcount < buffer_size) {
- buffer_size = wcount;
- buffer_size += buf_min - 1;
- buffer_size &= ~(buf_min - 1);
- }
+ if (wcount * 4 < buffer_size)
+ buffer_size = wcount * 4;
/* memory buffer */
while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
commit 12b8c7b89b021c882e68bb0e28863c802fe36ac4
Author: David Brownell <dbr...@us...>
Date: Fri Dec 18 09:53:59 2009 -0800
XScale: better {read,write}_phys()
We can actually do the right thing if the MMU is off; save
the error message for the phys-but-MMU-enabled path, which
is what isn't yet supported.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 4cf5aeb..f1afc71 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -1905,7 +1905,13 @@ static int xscale_read_memory(struct target *target, uint32_t address,
static int xscale_read_phys_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
- /** \todo: provide a non-stub implementtion of this routine. */
+ struct xscale_common *xscale = target_to_xscale(target);
+
+ /* with MMU inactive, there are only physical addresses */
+ if (!xscale->armv4_5_mmu.mmu_enabled)
+ return xscale_read_memory(target, address, size, count, buffer);
+
+ /** \todo: provide a non-stub implementation of this routine. */
LOG_ERROR("%s: %s is not implemented. Disable MMU?",
target_name(target), __func__);
return ERROR_FAIL;
@@ -1992,7 +1998,13 @@ static int xscale_write_memory(struct target *target, uint32_t address,
static int xscale_write_phys_memory(struct target *target, uint32_t address,
uint32_t size, uint32_t count, uint8_t *buffer)
{
- /** \todo: provide a non-stub implementtion of this routine. */
+ struct xscale_common *xscale = target_to_xscale(target);
+
+ /* with MMU inactive, there are only physical addresses */
+ if (!xscale->armv4_5_mmu.mmu_enabled)
+ return xscale_read_memory(target, address, size, count, buffer);
+
+ /** \todo: provide a non-stub implementation of this routine. */
LOG_ERROR("%s: %s is not implemented. Disable MMU?",
target_name(target), __func__);
return ERROR_FAIL;
-----------------------------------------------------------------------
Summary of changes:
NEWS | 2 ++
src/flash/nor/core.c | 44 ++++++++++++++++++++++++++++++++++++--------
src/flash/nor/stellaris.c | 11 ++++-------
src/flash/nor/tcl.c | 6 ++++--
src/target/xscale.c | 16 ++++++++++++++--
5 files changed, 60 insertions(+), 19 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-12-18 12:09:33
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 85a4136d0baccf5c3b8f717710584f7faed0ca30 (commit)
from e40f6380638ed3f7780b78ceb1411f8b7059a073 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 85a4136d0baccf5c3b8f717710584f7faed0ca30
Author: David Brownell <dbr...@us...>
Date: Fri Dec 18 03:08:49 2009 -0800
dsp563xx: cygwin build fixes
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c
index d3fa4c3..9e2f609 100644
--- a/src/target/dsp563xx.c
+++ b/src/target/dsp563xx.c
@@ -547,7 +547,7 @@ int dsp563xx_halt(struct target *target)
LOG_DEBUG("%02X", jtag_status);
dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OSCR,
&once_status);
- LOG_DEBUG("%02X", once_status);
+ LOG_DEBUG("%02X", (unsigned) once_status);
}
LOG_DEBUG("target->state: %s", target_state_name(target));
@@ -606,7 +606,7 @@ int dsp563xx_step(struct target *target, int current, uint32_t address,
return ERROR_OK;
}
- LOG_DEBUG("%s %08X %08X", __FUNCTION__, current, address);
+ LOG_DEBUG("%s %08X %08X", __FUNCTION__, current, (unsigned) address);
dsp563xx_jtag_debug_request(target);
@@ -666,13 +666,13 @@ int dsp563xx_step(struct target *target, int current, uint32_t address,
dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABFR,
&dr_in);
- LOG_DEBUG("%08X", dr_in);
+ LOG_DEBUG("%08X", (unsigned) dr_in);
dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABDR,
&dr_in);
- LOG_DEBUG("%08X", dr_in);
+ LOG_DEBUG("%08X", (unsigned) dr_in);
dsp563xx_once_reg_read(target->tap, DSP563XX_ONCE_OPABEX,
&dr_in);
- LOG_DEBUG("%08X", dr_in);
+ LOG_DEBUG("%08X", (unsigned) dr_in);
/* reset trace mode */
dsp563xx_once_reg_write(target->tap, DSP563XX_ONCE_OSCR,
-----------------------------------------------------------------------
Summary of changes:
src/target/dsp563xx.c | 10 +++++-----
1 files changed, 5 insertions(+), 5 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-12-18 10:33:47
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via e40f6380638ed3f7780b78ceb1411f8b7059a073 (commit)
via ef4fbd36d491b1c89cb13d43f6c03e26fd0d8a7d (commit)
via b8b4bb0745b63e03eec745ce0eb97bfa6e0792a1 (commit)
from 3616b93eee128b0c12fa0d453fbe6ced998e482f (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit e40f6380638ed3f7780b78ceb1411f8b7059a073
Author: David Brownell <dbr...@us...>
Date: Fri Dec 18 01:33:19 2009 -0800
stellaris: update bulk flash writes
Try to right-size the SRAM buffers, by not:
- using them for very small writes
- giving up when a large buffer isn't available
- allocating buffers much larger than their data
Also don't:
- bother loading the code unless we allocate the writebuffer too
- be so verbose with messaging:
* be more concise
* reduce importance (e.g. DEBUG not WARNING)
* remove duplication
The minimum buffer size is something of a guess. It's eight
times smaller than before, almost the same size as the code
being downloaded. It probably deserves some tuning.
Also, note an erratum affecting flash protection on some chips;
and narrow many over-wide lines affected by the above changes.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c
index 4183cba..51fe677 100644
--- a/src/flash/nor/stellaris.c
+++ b/src/flash/nor/stellaris.c
@@ -748,6 +748,8 @@ static int stellaris_protect(struct flash_bank *bank, int set, int first, int la
/* Write commit command */
/* REVISIT safety check, since this cannot be undone
* except by the "Recover a locked device" procedure.
+ * REVISIT DustDevil-A0 parts have an erratum making FMPPE commits
+ * inadvisable ... it makes future mass erase operations fail.
*/
LOG_WARNING("Flash protection cannot be removed once commited, commit is NOT executed !");
/* target_write_u32(target, FLASH_FMC, FMC_WRKEY | FMC_COMT); */
@@ -823,37 +825,47 @@ static int stellaris_write_block(struct flash_bank *bank,
struct armv7m_algorithm armv7m_info;
int retval = ERROR_OK;
+ /* power of two, and multiple of word size */
+ static const unsigned buf_min = 32;
+
+ /* for small buffers it's faster not to download an algorithm */
+ if (wcount < buf_min)
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+
LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32 "",
bank, buffer, offset, wcount);
/* flash write code */
if (target_alloc_working_area(target, sizeof(stellaris_write_code), &write_algorithm) != ERROR_OK)
{
- LOG_WARNING("no working area available, can't do block memory writes");
+ LOG_DEBUG("no working area for block memory writes");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
};
- target_write_buffer(target, write_algorithm->address,
- sizeof(stellaris_write_code),
- (uint8_t *) stellaris_write_code);
+ /* plus a buffer big enough for this data */
+ if (wcount < buffer_size) {
+ buffer_size = wcount;
+ buffer_size += buf_min - 1;
+ buffer_size &= ~(buf_min - 1);
+ }
/* memory buffer */
while (target_alloc_working_area(target, buffer_size, &source) != ERROR_OK)
{
- LOG_DEBUG("called target_alloc_working_area(target=%p buffer_size=%08" PRIx32 " source=%p)",
- target, buffer_size, source);
buffer_size /= 2;
- if (buffer_size <= 256)
+ if (buffer_size <= buf_min)
{
- /* if we already allocated the writing code, but failed to get a buffer, free the algorithm */
- if (write_algorithm)
- target_free_working_area(target, write_algorithm);
-
- LOG_WARNING("no large enough working area available, can't do block memory writes");
+ target_free_working_area(target, write_algorithm);
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
+ LOG_DEBUG("retry target_alloc_working_area(%s, size=%u)",
+ target_name(target), (unsigned) buffer_size);
};
+ retval = target_write_buffer(target, write_algorithm->address,
+ sizeof(stellaris_write_code),
+ (uint8_t *) stellaris_write_code);
+
armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
armv7m_info.core_mode = ARMV7M_MODE_ANY;
@@ -870,11 +882,20 @@ static int stellaris_write_block(struct flash_bank *bank,
buf_set_u32(reg_params[0].value, 0, 32, source->address);
buf_set_u32(reg_params[1].value, 0, 32, address);
buf_set_u32(reg_params[2].value, 0, 32, 4*thisrun_count);
- LOG_INFO("Algorithm flash write %" PRIi32 " words to 0x%" PRIx32 ", %" PRIi32 " remaining", thisrun_count, address, (wcount - thisrun_count));
- LOG_DEBUG("Algorithm flash write %" PRIi32 " words to 0x%" PRIx32 ", %" PRIi32 " remaining", thisrun_count, address, (wcount - thisrun_count));
- if ((retval = target_run_algorithm(target, 0, NULL, 3, reg_params, write_algorithm->address, write_algorithm->address + sizeof(stellaris_write_code)-10, 10000, &armv7m_info)) != ERROR_OK)
+ LOG_DEBUG("Algorithm flash write %u words to 0x%" PRIx32
+ ", %u remaining",
+ (unsigned) thisrun_count, address,
+ (unsigned) (wcount - thisrun_count));
+ retval = target_run_algorithm(target, 0, NULL, 3, reg_params,
+ write_algorithm->address,
+ write_algorithm->address +
+ sizeof(stellaris_write_code) - 10,
+ 10000, &armv7m_info);
+ if (retval != ERROR_OK)
{
- LOG_ERROR("error executing stellaris flash write algorithm");
+ LOG_ERROR("error %d executing stellaris "
+ "flash write algorithm",
+ retval);
retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
@@ -884,6 +905,10 @@ static int stellaris_write_block(struct flash_bank *bank,
wcount -= thisrun_count;
}
+ /* REVISIT we could speed up writing multi-section images by
+ * not freeing the initialized write_algorithm this way.
+ */
+
target_free_working_area(target, write_algorithm);
target_free_working_area(target, source);
@@ -942,13 +967,13 @@ static int stellaris_write(struct flash_bank *bank, uint8_t *buffer, uint32_t of
if (words_remaining > 0)
{
/* try using a block write */
- if ((retval = stellaris_write_block(bank, buffer, offset, words_remaining)) != ERROR_OK)
+ retval = stellaris_write_block(bank, buffer, offset,
+ words_remaining);
+ if (retval != ERROR_OK)
{
if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE)
{
- /* if block write failed (no sufficient working area),
- * we use normal (slow) single dword accesses */
- LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
+ LOG_DEBUG("writing flash word-at-a-time");
}
else if (retval == ERROR_FLASH_OPERATION_FAILED)
{
commit ef4fbd36d491b1c89cb13d43f6c03e26fd0d8a7d
Author: Dean Glazeski <dn...@gm...>
Date: Thu Dec 17 21:02:40 2009 -0600
NAND write data page refactoring.
Refactored the write page raw function into two new functions
for writing data to a NAND device and then another function to
finish up a write to a NAND device. This includes some new
updates to introduce more error checking to existing code.
[dbr...@us...: fix fault handling, whitespace]
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/flash/nand/core.c b/src/flash/nand/core.c
index 1056696..50d8249 100644
--- a/src/flash/nand/core.c
+++ b/src/flash/nand/core.c
@@ -675,7 +675,9 @@ static int nand_write_plain(struct nand_device *nand, uint32_t address, uint8_t
}
#endif
-int nand_write_page(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
+int nand_write_page(struct nand_device *nand, uint32_t page,
+ uint8_t *data, uint32_t data_size,
+ uint8_t *oob, uint32_t oob_size)
{
uint32_t block;
@@ -808,66 +810,41 @@ int nand_read_page_raw(struct nand_device *nand, uint32_t page,
return ERROR_OK;
}
-int nand_write_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size)
+int nand_write_data_page(struct nand_device *nand, uint8_t *data, uint32_t size)
{
- uint32_t i;
- int retval;
- uint8_t status;
+ int retval = ERROR_NAND_NO_BUFFER;
- retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
- if (ERROR_OK != retval)
- return retval;
+ if (nand->controller->write_block_data != NULL)
+ retval = (nand->controller->write_block_data)(nand, data, size);
- if (data)
- {
- if (nand->controller->write_block_data != NULL)
- (nand->controller->write_block_data)(nand, data, data_size);
- else
- {
- for (i = 0; i < data_size;)
- {
- if (nand->device->options & NAND_BUSWIDTH_16)
- {
- uint16_t data_buf = le_to_h_u16(data);
- nand->controller->write_data(nand, data_buf);
- data += 2;
- i += 2;
- }
- else
- {
- nand->controller->write_data(nand, *data);
- data += 1;
- i += 1;
- }
- }
- }
- }
+ if (ERROR_NAND_NO_BUFFER == retval) {
+ bool is16bit = nand->device->options & NAND_BUSWIDTH_16;
+ uint32_t incr = is16bit ? 2 : 1;
+ uint16_t write_data;
+ uint32_t i;
- if (oob)
- {
- if (nand->controller->write_block_data != NULL)
- (nand->controller->write_block_data)(nand, oob, oob_size);
- else
- {
- for (i = 0; i < oob_size;)
- {
- if (nand->device->options & NAND_BUSWIDTH_16)
- {
- uint16_t oob_buf = le_to_h_u16(data);
- nand->controller->write_data(nand, oob_buf);
- oob += 2;
- i += 2;
- }
- else
- {
- nand->controller->write_data(nand, *oob);
- oob += 1;
- i += 1;
- }
- }
+ for (i = 0; i < size; i += incr) {
+ if (is16bit)
+ write_data = le_to_h_u16(data);
+ else
+ write_data = *data;
+
+ retval = nand->controller->write_data(nand, write_data);
+ if (ERROR_OK != retval)
+ break;
+
+ data += incr;
}
}
+ return retval;
+}
+
+int nand_write_finish(struct nand_device *nand)
+{
+ int retval;
+ uint8_t status;
+
nand->controller->command(nand, NAND_CMD_PAGEPROG);
retval = nand->controller->nand_ready ?
@@ -876,18 +853,47 @@ int nand_write_page_raw(struct nand_device *nand, uint32_t page, uint8_t *data,
if (!retval)
return ERROR_NAND_OPERATION_TIMEOUT;
- if ((retval = nand_read_status(nand, &status)) != ERROR_OK)
- {
+ retval = nand_read_status(nand, &status);
+ if (ERROR_OK != retval) {
LOG_ERROR("couldn't read status");
return ERROR_NAND_OPERATION_FAILED;
}
- if (status & NAND_STATUS_FAIL)
- {
- LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
+ if (status & NAND_STATUS_FAIL) {
+ LOG_ERROR("write operation didn't pass, status: 0x%2.2x",
+ status);
return ERROR_NAND_OPERATION_FAILED;
}
return ERROR_OK;
}
+int nand_write_page_raw(struct nand_device *nand, uint32_t page,
+ uint8_t *data, uint32_t data_size,
+ uint8_t *oob, uint32_t oob_size)
+{
+ int retval;
+
+ retval = nand_page_command(nand, page, NAND_CMD_SEQIN, !data);
+ if (ERROR_OK != retval)
+ return retval;
+
+ if (data) {
+ retval = nand_write_data_page(nand, data, data_size);
+ if (ERROR_OK != retval) {
+ LOG_ERROR("Unable to write data to NAND device");
+ return retval;
+ }
+ }
+
+ if (oob) {
+ retval = nand_write_data_page(nand, oob, oob_size);
+ if (ERROR_OK != retval) {
+ LOG_ERROR("Unable to write OOB data to NAND device");
+ return retval;
+ }
+ }
+
+ return nand_write_finish(nand);
+}
+
diff --git a/src/flash/nand/core.h b/src/flash/nand/core.h
index 990114a..d2d1571 100644
--- a/src/flash/nand/core.h
+++ b/src/flash/nand/core.h
@@ -212,6 +212,10 @@ int nand_page_command(struct nand_device *nand, uint32_t page,
uint8_t cmd, bool oob_only);
int nand_read_data_page(struct nand_device *nand, uint8_t *data, uint32_t size);
+int nand_write_data_page(struct nand_device *nand,
+ uint8_t *data, uint32_t size);
+
+int nand_write_finish(struct nand_device *nand);
int nand_read_page_raw(struct nand_device *nand, uint32_t page,
uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
commit b8b4bb0745b63e03eec745ce0eb97bfa6e0792a1
Author: Dean Glazeski <dn...@gm...>
Date: Thu Dec 17 21:02:39 2009 -0600
NAND read data page refactor.
Added a new function to encapsulate reading a page of data from
a NAND device using either the read_block_data function of a NAND
controller or to use direct reading of data from the NAND device.
This also adds some performance enhancements and uses the read_data
function if the read_block_data function fails safely (because it
can't allocate a buffer in the working area).
[dbr...@us...: fix fault handling, whitespace]
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/src/flash/nand/core.c b/src/flash/nand/core.c
index d52cf5d..1056696 100644
--- a/src/flash/nand/core.c
+++ b/src/flash/nand/core.c
@@ -768,11 +768,31 @@ int nand_page_command(struct nand_device *nand, uint32_t page,
return ERROR_OK;
}
+int nand_read_data_page(struct nand_device *nand, uint8_t *data, uint32_t size)
+{
+ int retval = ERROR_NAND_NO_BUFFER;
+
+ if (nand->controller->read_block_data != NULL)
+ retval = (nand->controller->read_block_data)(nand, data, size);
+
+ if (ERROR_NAND_NO_BUFFER == retval) {
+ uint32_t i;
+ int incr = (nand->device->options & NAND_BUSWIDTH_16) ? 2 : 1;
+
+ retval = ERROR_OK;
+ for (i = 0; retval == ERROR_OK && i < size; i += incr) {
+ retval = nand->controller->read_data(nand, data);
+ data += incr;
+ }
+ }
+
+ return retval;
+}
+
int nand_read_page_raw(struct nand_device *nand, uint32_t page,
uint8_t *data, uint32_t data_size,
uint8_t *oob, uint32_t oob_size)
{
- uint32_t i;
int retval;
retval = nand_page_command(nand, page, NAND_CMD_READ0, !data);
@@ -780,52 +800,10 @@ int nand_read_page_raw(struct nand_device *nand, uint32_t page,
return retval;
if (data)
- {
- if (nand->controller->read_block_data != NULL)
- (nand->controller->read_block_data)(nand, data, data_size);
- else
- {
- for (i = 0; i < data_size;)
- {
- if (nand->device->options & NAND_BUSWIDTH_16)
- {
- nand->controller->read_data(nand, data);
- data += 2;
- i += 2;
- }
- else
- {
- nand->controller->read_data(nand, data);
- data += 1;
- i += 1;
- }
- }
- }
- }
+ nand_read_data_page(nand, data, data_size);
if (oob)
- {
- if (nand->controller->read_block_data != NULL)
- (nand->controller->read_block_data)(nand, oob, oob_size);
- else
- {
- for (i = 0; i < oob_size;)
- {
- if (nand->device->options & NAND_BUSWIDTH_16)
- {
- nand->controller->read_data(nand, oob);
- oob += 2;
- i += 2;
- }
- else
- {
- nand->controller->read_data(nand, oob);
- oob += 1;
- i += 1;
- }
- }
- }
- }
+ nand_read_data_page(nand, oob, oob_size);
return ERROR_OK;
}
diff --git a/src/flash/nand/core.h b/src/flash/nand/core.h
index b8dc01c..990114a 100644
--- a/src/flash/nand/core.h
+++ b/src/flash/nand/core.h
@@ -211,6 +211,8 @@ struct nand_device *get_nand_device_by_num(int num);
int nand_page_command(struct nand_device *nand, uint32_t page,
uint8_t cmd, bool oob_only);
+int nand_read_data_page(struct nand_device *nand, uint8_t *data, uint32_t size);
+
int nand_read_page_raw(struct nand_device *nand, uint32_t page,
uint8_t *data, uint32_t data_size, uint8_t *oob, uint32_t oob_size);
int nand_write_page_raw(struct nand_device *nand, uint32_t page,
-----------------------------------------------------------------------
Summary of changes:
src/flash/nand/core.c | 192 +++++++++++++++++++++------------------------
src/flash/nand/core.h | 6 ++
src/flash/nor/stellaris.c | 65 +++++++++++-----
3 files changed, 139 insertions(+), 124 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: Spencer O. <nt...@us...> - 2009-12-17 12:42:42
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 3616b93eee128b0c12fa0d453fbe6ced998e482f (commit)
from 960ad2f77631988bc8aef86255ea6f4007b34153 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 3616b93eee128b0c12fa0d453fbe6ced998e482f
Author: Spencer Oliver <nt...@us...>
Date: Thu Dec 17 10:53:09 2009 +0000
target.cfg: update to use new flash configuration syntax
Signed-off-by: Spencer Oliver <nt...@us...>
diff --git a/tcl/target/aduc702x.cfg b/tcl/target/aduc702x.cfg
index 58cc9b9..50b2a0d 100644
--- a/tcl/target/aduc702x.cfg
+++ b/tcl/target/aduc702x.cfg
@@ -36,7 +36,7 @@ $_TARGETNAME configure -work-area-phys 0x10000 -work-area-size 0x2000
## flash configuration
# only target number is needed
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME aduc702x 0 0 0 0 0
+flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
## If you use the watchdog, the following code makes sure that the board
## doesn't reboot when halted via JTAG. Yes, on the older generation
diff --git a/tcl/target/faux.cfg b/tcl/target/faux.cfg
index 6fe0cd7..b2bdb2b 100644
--- a/tcl/target/faux.cfg
+++ b/tcl/target/faux.cfg
@@ -27,4 +27,4 @@ target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAM
#dummy flash driver
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME faux 0x01000000 0x200000 2 2 0
+flash bank $_FLASHNAME faux 0x01000000 0x200000 2 2 $_TARGETNAME
diff --git a/tcl/target/lpc2900.cfg b/tcl/target/lpc2900.cfg
index 769d39d..b258086 100644
--- a/tcl/target/lpc2900.cfg
+++ b/tcl/target/lpc2900.cfg
@@ -63,4 +63,4 @@ arm7_9 dcc_downloads enable
# Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz>
# Flash base address, total flash size, and number of sectors are all configured automatically.
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK
+flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK
diff --git a/tcl/target/mega128.cfg b/tcl/target/mega128.cfg
index 2bc2294..2cf31d6 100644
--- a/tcl/target/mega128.cfg
+++ b/tcl/target/mega128.cfg
@@ -23,7 +23,7 @@ target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
#$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME avr 0 0 0 0 0
+flash bank $_FLASHNAME avr 0 0 0 0 $_TARGETNAME
#to use it, script will be like:
#init
diff --git a/tcl/target/pic32mx.cfg b/tcl/target/pic32mx.cfg
index a346c47..e0ebdc2 100644
--- a/tcl/target/pic32mx.cfg
+++ b/tcl/target/pic32mx.cfg
@@ -34,9 +34,9 @@ target create $_TARGETNAME mips_m4k -endian $_ENDIAN -chain-position $_TARGETNAM
$_TARGETNAME configure -work-area-phys 0xa0000000 -work-area-size 16384 -work-area-backup 0
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME pic32mx 0xbd000000 0 0 0 0
+flash bank $_FLASHNAME pic32mx 0xbd000000 0 0 0 $_TARGETNAME
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME pic32mx 0xbfc00000 0 0 0 0
+flash bank $_FLASHNAME pic32mx 0xbfc00000 0 0 0 $_TARGETNAME
# For more information about the configuration files, take a look at:
# openocd.texi
diff --git a/tcl/target/sam7se512.cfg b/tcl/target/sam7se512.cfg
index d255067..c48afef 100644
--- a/tcl/target/sam7se512.cfg
+++ b/tcl/target/sam7se512.cfg
@@ -36,5 +36,5 @@ $_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-a
#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
+flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
diff --git a/tcl/target/sam7x256.cfg b/tcl/target/sam7x256.cfg
index 5bab642..19145e5 100644
--- a/tcl/target/sam7x256.cfg
+++ b/tcl/target/sam7x256.cfg
@@ -47,7 +47,7 @@ $_TARGETNAME configure -work-area-phys 0x00200000 -work-area-size 0x4000 -work-a
#flash bank <driver> <base_addr> <size> <chip_width> <bus_width> <target_number> [<target_name> <banks> <sectors_per_bank> <pages_per_sector> <page_size> <num_nvmbits> <ext_freq_khz>]
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME at91sam7 0 0 0 0 0 0 0 0 0 0 0 0 18432
+flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME 0 0 0 0 0 0 0 18432
# For more information about the configuration files, take a look at:
# openocd.texi
diff --git a/tcl/target/str710.cfg b/tcl/target/str710.cfg
index 395a26c..9da69ac 100644
--- a/tcl/target/str710.cfg
+++ b/tcl/target/str710.cfg
@@ -40,9 +40,9 @@ $_TARGETNAME configure -work-area-phys 0x2000C000 -work-area-size 0x4000 -work-a
#flash bank str7x <base> <size> 0 0 <target#> <variant>
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 0 STR71x
+flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME str7x 0x400C0000 0x00004000 0 0 0 STR71x
+flash bank $_FLASHNAME str7x 0x400C0000 0x00004000 0 0 $_TARGETNAME STR71x
# For more information about the configuration files, take a look at:
# openocd.texi
diff --git a/tcl/target/str730.cfg b/tcl/target/str730.cfg
index 6432d15..381fa5f 100644
--- a/tcl/target/str730.cfg
+++ b/tcl/target/str730.cfg
@@ -43,5 +43,5 @@ $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-a
#flash bank <driver> <base> <size> <chip_width> <bus_width>
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 0 STR3x
+flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 $_TARGETNAME STR3x
diff --git a/tcl/target/str750.cfg b/tcl/target/str750.cfg
index 496c4e3..5df968b 100644
--- a/tcl/target/str750.cfg
+++ b/tcl/target/str750.cfg
@@ -46,7 +46,7 @@ $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x4000 -work-a
#flash bank <driver> <base> <size> <chip_width> <bus_width>
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 0 STR75x
+flash bank $_FLASHNAME str7x 0x20000000 0x00040000 0 0 $_TARGETNAME STR75x
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME str7x 0x200C0000 0x00004000 0 0 0 STR75x
+flash bank $_FLASHNAME str7x 0x200C0000 0x00004000 0 0 $_TARGETNAME STR75x
diff --git a/tcl/target/str912.cfg b/tcl/target/str912.cfg
index d844584..2defe9f 100644
--- a/tcl/target/str912.cfg
+++ b/tcl/target/str912.cfg
@@ -64,9 +64,9 @@ $_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-ar
#flash bank str9x <base> <size> 0 0 <target#> <variant>
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0
+flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 $_TARGETNAME
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0
+flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 $_TARGETNAME
# For more information about the configuration files, take a look at:
# openocd.texi
-----------------------------------------------------------------------
Summary of changes:
tcl/target/aduc702x.cfg | 2 +-
tcl/target/faux.cfg | 2 +-
tcl/target/lpc2900.cfg | 2 +-
tcl/target/mega128.cfg | 2 +-
tcl/target/pic32mx.cfg | 4 ++--
tcl/target/sam7se512.cfg | 2 +-
tcl/target/sam7x256.cfg | 2 +-
tcl/target/str710.cfg | 4 ++--
tcl/target/str730.cfg | 2 +-
tcl/target/str750.cfg | 4 ++--
tcl/target/str912.cfg | 4 ++--
11 files changed, 15 insertions(+), 15 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-12-16 23:22:16
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 960ad2f77631988bc8aef86255ea6f4007b34153 (commit)
from 2c3e413d49d8f446ec5347c4356888fbbfa4ec1d (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 960ad2f77631988bc8aef86255ea6f4007b34153
Author: David Brownell <dbr...@us...>
Date: Wed Dec 16 14:21:06 2009 -0800
Remove duplicate Olimex-"tiny" interface
We already have tcl/interface/olimex-jtag-tiny.cfg and
don't need a clone of it.
diff --git a/tcl/interface/arm-usb-ocd-tiny.cfg b/tcl/interface/arm-usb-ocd-tiny.cfg
deleted file mode 100644
index 34793f3..0000000
--- a/tcl/interface/arm-usb-ocd-tiny.cfg
+++ /dev/null
@@ -1,10 +0,0 @@
-#
-# Olimex ARM-USB-OCD-TINY
-#
-# http://www.olimex.com/dev/arm-usb-tiny.html
-#
-
-interface ft2232
-ft2232_device_desc "Olimex OpenOCD JTAG TINY"
-ft2232_layout "olimex-jtag"
-ft2232_vid_pid 0x15ba 0x0004
-----------------------------------------------------------------------
Summary of changes:
tcl/interface/arm-usb-ocd-tiny.cfg | 10 ----------
1 files changed, 0 insertions(+), 10 deletions(-)
delete mode 100644 tcl/interface/arm-usb-ocd-tiny.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: David B. <dbr...@us...> - 2009-12-16 23:20:12
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 2c3e413d49d8f446ec5347c4356888fbbfa4ec1d (commit)
from d265c219b90bfe9454991bed6b41f790f085d230 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 2c3e413d49d8f446ec5347c4356888fbbfa4ec1d
Author: David Brownell <dbr...@us...>
Date: Wed Dec 16 14:19:44 2009 -0800
JTAG: shrink "scan_chain" output
Tweak the "scan_chain" output by removing column separators. Also
remove the "current instruction" state ... which changes constantly.
Now its style resembles the "targets" output, and can even fit on
one line in standard terminals and in the PDF docs.
Signed-off-by: David Brownell <dbr...@us...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 9d56523..cda5be3 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2592,13 +2592,15 @@ debugging targets.)
Here's what the scan chain might look like for a chip more than one TAP:
@verbatim
- TapName Enabled IdCode Expected IrLen IrCap IrMask Instr
--- ------------------ ------- ---------- ---------- ----- ----- ------ -----
- 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0 0 0x...
- 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x1 0 0xc
- 2 omap5912.unknown Y 0x00000000 0x00000000 8 0 0 0xff
+ TapName Enabled IdCode Expected IrLen IrCap IrMask
+-- ------------------ ------- ---------- ---------- ----- ----- ------
+ 0 omap5912.dsp Y 0x03df1d81 0x03df1d81 38 0x01 0x03
+ 1 omap5912.arm Y 0x0692602f 0x0692602f 4 0x01 0x0f
+ 2 omap5912.unknown Y 0x00000000 0x00000000 8 0x01 0x03
@end verbatim
+OpenOCD can detect some of that information, but not all
+of it. @xref{Autoprobing}.
Unfortunately those TAPs can't always be autoconfigured,
because not all devices provide good support for that.
JTAG doesn't require supporting IDCODE instructions, and
@@ -2659,8 +2661,6 @@ The set of TAPs listed by this command is fixed by
exiting the OpenOCD configuration stage,
but systems with a JTAG router can
enable or disable TAPs dynamically.
-In addition to the enable/disable status, the contents of
-each TAP's instruction register can also change.
@end deffn
@c FIXME! "jtag cget" should be able to return all TAP
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index f4815c8..00b1038 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -1021,11 +1021,13 @@ COMMAND_HANDLER(handle_scan_chain_command)
char expected_id[12];
tap = jtag_all_taps();
- command_print(CMD_CTX, " TapName | Enabled | IdCode Expected IrLen IrCap IrMask Instr ");
- command_print(CMD_CTX, "---|--------------------|---------|------------|------------|------|------|------|---------");
+ command_print(CMD_CTX,
+" TapName Enabled IdCode Expected IrLen IrCap IrMask");
+ command_print(CMD_CTX,
+"-- ------------------- -------- ---------- ---------- ----- ----- ------");
while (tap) {
- uint32_t expected, expected_mask, cur_instr, ii;
+ uint32_t expected, expected_mask, ii;
snprintf(expected_id, sizeof expected_id, "0x%08x",
(unsigned)((tap->expected_ids_cnt > 0)
@@ -1036,10 +1038,9 @@ COMMAND_HANDLER(handle_scan_chain_command)
expected = buf_get_u32(tap->expected, 0, tap->ir_length);
expected_mask = buf_get_u32(tap->expected_mask, 0, tap->ir_length);
- cur_instr = buf_get_u32(tap->cur_instr, 0, tap->ir_length);
command_print(CMD_CTX,
- "%2d | %-18s | %c | 0x%08x | %s | 0x%02x | 0x%02x | 0x%02x | 0x%02x",
+ "%2d %-18s %c 0x%08x %s %5d 0x%02x 0x%02x",
tap->abs_chain_position,
tap->dotted_name,
tap->enabled ? 'Y' : 'n',
@@ -1047,8 +1048,7 @@ COMMAND_HANDLER(handle_scan_chain_command)
expected_id,
(unsigned int)(tap->ir_length),
(unsigned int)(expected),
- (unsigned int)(expected_mask),
- (unsigned int)(cur_instr));
+ (unsigned int)(expected_mask));
for (ii = 1; ii < tap->expected_ids_cnt; ii++) {
snprintf(expected_id, sizeof expected_id, "0x%08x",
@@ -1057,7 +1057,7 @@ COMMAND_HANDLER(handle_scan_chain_command)
expected_id[2] = '*';
command_print(CMD_CTX,
- " | | | | %s | | | | ",
+ " %s",
expected_id);
}
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 14 +++++++-------
src/jtag/tcl.c | 16 ++++++++--------
2 files changed, 15 insertions(+), 15 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
