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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-114-g6c4a643

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- Log -----------------------------------------------------------------
commit 6c4a643d632c6cff647c5099bd450d1e417903ea
Author: David Brownell <dbr...@us...>
Date:   Fri Jan 15 12:53:26 2010 -0800

    ARM DPM: disable some nyet-ready breakpoint code
    
    Until we manage breakpoints at runtime (patches not ready for 0.4)
    the only way this code should touch them is to disable them at server
    startup (a previous debug session may have left them active).
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 0908ca9..4bd22ff 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -341,13 +341,21 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
 	if (retval != ERROR_OK)
 		goto done;
 
-	/* enable/disable hardware breakpoints */
-	for (unsigned i = 0; i < dpm->nbp; i++) {
-		struct dpm_bp *dbp = dpm->dbp + i;
-		struct breakpoint *bp = dbp->bp;
+	/* If we're managing hardware breakpoints for this core, enable
+	 * or disable them as requested.
+	 *
+	 * REVISIT We don't yet manage them for ANY cores.  Eventually
+	 * we should be able to assume we handle them; but until then,
+	 * cope with the hand-crafted breakpoint code.
+	 */
+	if (0) {
+		for (unsigned i = 0; i < dpm->nbp; i++) {
+			struct dpm_bp *dbp = dpm->dbp + i;
+			struct breakpoint *bp = dbp->bp;
 
-		retval = dpm_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
-				bp ? &bp->set : NULL);
+			retval = dpm_maybe_update_bpwp(dpm, bpwp, &dbp->bpwp,
+					bp ? &bp->set : NULL);
+		}
 	}
 
 	/* enable/disable watchpoints */

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_dpm.c |   20 ++++++++++++++------
 1 files changed, 14 insertions(+), 6 deletions(-)


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- Log -----------------------------------------------------------------
commit 187ccb60eece14a1fb6cdeb38ab0ce4ccac443af
Author: David Brownell <dbr...@us...>
Date:   Fri Jan 15 09:36:01 2010 -0800

    NEWS: include s3c64xx NAND driver
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/NEWS b/NEWS
index ce4896f..c4abd13 100644
--- a/NEWS
+++ b/NEWS
@@ -54,6 +54,7 @@ Flash Layer:
 		want to erase the rest of the first and/or last sectors
 		instead of failing, you must pass an explicit "pad" flag.
 	New at91sam9 NAND controller driver.
+	New s3c64xx NAND controller driver.
 
 Board, Target, and Interface Configuration Scripts:
 	ARM9

-----------------------------------------------------------------------

Summary of changes:
 NEWS |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-112-g0f7cea2

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- Log -----------------------------------------------------------------
commit 0f7cea2847d718f671b807c9d37cc6a4b648bc28
Author: David Brownell <dbr...@us...>
Date:   Thu Jan 14 14:38:24 2010 -0800

    jtag.h whitespace/comment cleanup
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h
index f79ef93..0555754 100644
--- a/src/jtag/jtag.h
+++ b/src/jtag/jtag.h
@@ -525,8 +525,8 @@ int jtag_add_statemove(tap_state_t goal_state);
  * to @a endstate (unless it is also TAP_IDLE).
  *
  * @param num_cycles Number of cycles in TAP_IDLE state.  This argument
- * 	may be 0, in which case this routine will navigate to @a endstate
- * 	via TAP_IDLE.
+ *	may be 0, in which case this routine will navigate to @a endstate
+ *	via TAP_IDLE.
  * @param endstate The final state.
  */
 void jtag_add_runtest(int num_cycles, tap_state_t endstate);
@@ -563,23 +563,22 @@ void jtag_add_reset(int req_tlr_or_trst, int srst);
  * Set a global variable to \a state if \a state != TAP_INVALID.
  *
  * Return the value of the global variable.
- *
- **/
+ */
 tap_state_t jtag_set_end_state(tap_state_t state);
+
 /**
  * Function jtag_get_end_state
  *
  * Return the value of the global variable for end state
- *
- **/
+ */
 tap_state_t jtag_get_end_state(void);
-void jtag_add_sleep(uint32_t us);
 
+void jtag_add_sleep(uint32_t us);
 
 /**
- * Function jtag_add_stable_clocks
+ * Function jtag_add_clocks
  * first checks that the state in which the clocks are to be issued is
- * stable, then queues up clock_count clocks for transmission.
+ * stable, then queues up num_cycles clocks for transmission.
  */
 void jtag_add_clocks(int num_cycles);
 

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/jtag.h |   17 ++++++++---------
 1 files changed, 8 insertions(+), 9 deletions(-)


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- Log -----------------------------------------------------------------
commit 8e1b5c313840544ec4aafbb9a6f464824b6414a9
Author: David Brownell <dbr...@us...>
Date:   Thu Jan 14 12:58:39 2010 -0800

    ARM ADIv5: add comments
    
    Add doxygen and other comments for what's more or less the lowest
    level JDAG-DP primitive, to access JTAG_DP_{A,D}PACC registers.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index e490f2e..1a86458 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -88,7 +88,24 @@ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address
  *                                                                         *
 ***************************************************************************/
 
-/* Scan out and in from target ordered uint8_t buffers */
+/**
+ * Scan DPACC or APACC using target ordered uint8_t buffers.  No endianness
+ * conversions are performed.  See section 4.4.3 of the ADIv5 spec, which
+ * discusses operations which access these registers.
+ *
+ * Note that only one scan is performed.  If RnW is set, a separate scan
+ * will be needed to collect the data which was read; the "invalue" collects
+ * the posted result of a preceding operation, not the current one.
+ *
+ * @param swjdp the DAP
+ * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
+ * @param reg_addr two significant bits; A[3:2]; for APACC access, the
+ *	SELECT register has more addressing bits.
+ * @param RnW false iff outvalue will be written to the DP or AP
+ * @param outvalue points to a 32-bit (little-endian) integer
+ * @param invalue NULL, or points to a 32-bit (little-endian) integer
+ * @param ack points to where the three bit JTAG_ACK_* code will be stored
+ */
 static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
 		uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 		uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
@@ -104,6 +121,7 @@ static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
 
 	/* REVISIT these TCK cycles should be *AFTER*  updating APACC, since
 	 * they provide more time for the (MEM) AP to complete the read ...
+	 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
 	 */
 	if ((instr == JTAG_DP_APACC)
 			&& ((reg_addr == AP_REG_DRW)
@@ -111,12 +129,20 @@ static int adi_jtag_dp_scan(struct swjdp_common *swjdp,
 			&& (swjdp->memaccess_tck != 0))
 		jtag_add_runtest(swjdp->memaccess_tck, jtag_set_end_state(TAP_IDLE));
 
+	/* Scan out a read or write operation using some DP or AP register.
+	 * For APACC access with any sticky error flag set, this is discarded.
+	 */
 	fields[0].tap = jtag_info->tap;
 	fields[0].num_bits = 3;
 	buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
 	fields[0].out_value = &out_addr_buf;
 	fields[0].in_value = ack;
 
+	/* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
+	 * complete; data we write is discarded, data we read is unpredictable.
+	 * When overrun detect is active, STICKYORUN is set.
+	 */
+
 	fields[1].tap = jtag_info->tap;
 	fields[1].num_bits = 32;
 	fields[1].out_value = outvalue;

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_adi_v5.c |   28 +++++++++++++++++++++++++++-
 1 files changed, 27 insertions(+), 1 deletions(-)


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- Log -----------------------------------------------------------------
commit 1d140c4dcd79cf5e6257d53986db23dc71c2521b
Author: David Brownell <dbr...@us...>
Date:   Thu Jan 14 12:45:58 2010 -0800

    ARM7/ARM9: improved reset support
    
    Teach most remaining ARM cores how to use the "reset-assert" event.
    
    Same model as elsewhere:  iff a handler is provided for that event,
    use that instead of trying to assert SRST (which may be unavailable,
    or inappropriate since it resets too much).  Else no change.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index baf3e45..ca1d84f 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -944,13 +944,15 @@ int arm7_9_assert_reset(struct target *target)
 {
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
+	bool use_event = false;
 
 	LOG_DEBUG("target->state: %s",
 		  target_state_name(target));
 
-	if (!(jtag_reset_config & RESET_HAS_SRST))
-	{
-		LOG_ERROR("Can't assert SRST");
+	if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT))
+		use_event = true;
+	else if (!(jtag_reset_config & RESET_HAS_SRST)) {
+		LOG_ERROR("%s: how to reset?", target_name(target));
 		return ERROR_FAIL;
 	}
 
@@ -965,7 +967,8 @@ int arm7_9_assert_reset(struct target *target)
 	 */
 	bool srst_asserted = false;
 
-	if (((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
+	if (!use_event
+			&& !(jtag_reset_config & RESET_SRST_PULLS_TRST)
 			&& (jtag_reset_config & RESET_SRST_NO_GATING))
 	{
 		jtag_add_reset(0, 1);
@@ -1015,22 +1018,28 @@ int arm7_9_assert_reset(struct target *target)
 		}
 	}
 
-	/* here we should issue an SRST only, but we may have to assert TRST as well */
-	if (jtag_reset_config & RESET_SRST_PULLS_TRST)
-	{
-		jtag_add_reset(1, 1);
-	} else if (!srst_asserted)
-	{
-		jtag_add_reset(0, 1);
+	if (use_event) {
+		target_handle_event(target, TARGET_EVENT_RESET_ASSERT);
+	} else {
+		/* If we use SRST ... we'd like to issue just SRST, but the
+		 * board or chip may be set up so we have to assert TRST as
+		 * well.  On some chips that combination is equivalent to a
+		 * power-up reset, and generally clobbers EICE state.
+		 */
+		if (jtag_reset_config & RESET_SRST_PULLS_TRST)
+			jtag_add_reset(1, 1);
+		else if (!srst_asserted)
+			jtag_add_reset(0, 1);
+		jtag_add_sleep(50000);
 	}
 
 	target->state = TARGET_RESET;
-	jtag_add_sleep(50000);
-
 	register_cache_invalidate(arm7_9->armv4_5_common.core_cache);
 
+	/* REVISIT why isn't standard debug entry logic sufficient?? */
 	if (target->reset_halt
-			&& !(jtag_reset_config & RESET_SRST_PULLS_TRST))
+			&& (!(jtag_reset_config & RESET_SRST_PULLS_TRST)
+				|| use_event))
 	{
 		/* debug entry was prepared above */
 		target->debug_reason = DBG_REASON_DBGRQ;

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm7_9_common.c |   37 +++++++++++++++++++++++--------------
 1 files changed, 23 insertions(+), 14 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-109-g000a1cf

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- Log -----------------------------------------------------------------
commit 000a1cfd011d0b1e9ae30446df4eabe269202550
Author: Peter Korsgaard <ja...@su...>
Date:   Mon Jan 11 22:59:29 2010 +0100

    nand flash support for s3c64xx
    
    Identical to the existing 2412/2443 support except for the base address
    and NFCONF value (bit 2 is reserved and should be written as 1 ref UM).
    
    Tested on a s3c6410 board, but controller is identical in 6400/6410
    except for 8bit MLC ECC support in 6410 which isn't supported by the
    driver.
    
    Signed-off-by: Peter Korsgaard <ja...@su...>
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 4446046..a0fc0fb 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5041,7 +5041,8 @@ change any behavior.
 @deffnx {NAND Driver} s3c2412
 @deffnx {NAND Driver} s3c2440
 @deffnx {NAND Driver} s3c2443
-These S3C24xx family controllers don't have any special
+@deffnx {NAND Driver} s3c6400
+These S3C family controllers don't have any special
 @command{nand device} options, and don't define any
 specialized commands.
 At this writing, their drivers don't include @code{write_page}
diff --git a/src/flash/nand/Makefile.am b/src/flash/nand/Makefile.am
index 2ffa4c4..a495dfd 100644
--- a/src/flash/nand/Makefile.am
+++ b/src/flash/nand/Makefile.am
@@ -25,6 +25,7 @@ NAND_DRIVERS = \
 	s3c2412.c \
 	s3c2440.c \
 	s3c2443.c \
+	s3c6400.c \
 	at91sam9.c
 
 noinst_HEADERS = \
diff --git a/src/flash/nand/driver.c b/src/flash/nand/driver.c
index 0e174b2..1c28dbc 100644
--- a/src/flash/nand/driver.c
+++ b/src/flash/nand/driver.c
@@ -36,6 +36,7 @@ extern struct nand_flash_controller s3c2410_nand_controller;
 extern struct nand_flash_controller s3c2412_nand_controller;
 extern struct nand_flash_controller s3c2440_nand_controller;
 extern struct nand_flash_controller s3c2443_nand_controller;
+extern struct nand_flash_controller s3c6400_nand_controller;
 extern struct nand_flash_controller imx31_nand_flash_controller;
 extern struct nand_flash_controller at91sam9_nand_controller;
 
@@ -51,6 +52,7 @@ static struct nand_flash_controller *nand_flash_controllers[] =
 	&s3c2412_nand_controller,
 	&s3c2440_nand_controller,
 	&s3c2443_nand_controller,
+	&s3c6400_nand_controller,
 	&imx31_nand_flash_controller,
 	&at91sam9_nand_controller,
 /*	&boundary_scan_nand_controller, */
diff --git a/src/flash/nand/s3c6400.c b/src/flash/nand/s3c6400.c
new file mode 100644
index 0000000..20b6cc1
--- /dev/null
+++ b/src/flash/nand/s3c6400.c
@@ -0,0 +1,76 @@
+/***************************************************************************
+ *   Copyright (C) 2010 by Peter Korsgaard <ja...@su...>             *
+ *   Heavily based on s3c2412.c by Ben Dooks <be...@fl...>               *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "s3c24xx.h"
+/* s3c64xx uses another base address for the nand controller than 24xx */
+#undef S3C2410_NFREG
+#define S3C2410_NFREG(x) ((x) + 0x70200000)
+
+NAND_DEVICE_COMMAND_HANDLER(s3c6400_nand_device_command)
+{
+	struct s3c24xx_nand_controller *info;
+	CALL_S3C24XX_DEVICE_COMMAND(nand, &info);
+
+	/* fill in the address fields for the core device */
+	info->cmd = S3C2440_NFCMD;
+	info->addr = S3C2440_NFADDR;
+	info->data = S3C2440_NFDATA;
+	info->nfstat = S3C2412_NFSTAT;
+
+	return ERROR_OK;
+}
+
+static int s3c6400_init(struct nand_device *nand)
+{
+	struct s3c24xx_nand_controller *s3c24xx_info = nand->controller_priv;
+	struct target *target = s3c24xx_info->target;
+
+	target_write_u32(target, S3C2410_NFCONF,
+			 S3C2440_NFCONF_TACLS(3) |
+			 S3C2440_NFCONF_TWRPH0(7) |
+			 S3C2440_NFCONF_TWRPH1(7) | 4);
+
+	target_write_u32(target, S3C2440_NFCONT,
+			 S3C2412_NFCONT_INIT_MAIN_ECC |
+			 S3C2440_NFCONT_ENABLE);
+
+	return ERROR_OK;
+}
+
+struct nand_flash_controller s3c6400_nand_controller = {
+		.name = "s3c6400",
+		.nand_device_command = &s3c6400_nand_device_command,
+		.init = &s3c6400_init,
+		.reset = &s3c24xx_reset,
+		.command = &s3c24xx_command,
+		.address = &s3c24xx_address,
+		.write_data = &s3c24xx_write_data,
+		.read_data = &s3c24xx_read_data,
+		.write_page = s3c24xx_write_page,
+		.read_page = s3c24xx_read_page,
+		.write_block_data = &s3c2440_write_block_data,
+		.read_block_data = &s3c2440_read_block_data,
+		.controller_ready = &s3c24xx_controller_ready,
+		.nand_ready = &s3c2440_nand_ready,
+	};

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi                        |    3 ++-
 src/flash/nand/Makefile.am              |    1 +
 src/flash/nand/driver.c                 |    2 ++
 src/flash/nand/{s3c2443.c => s3c6400.c} |   28 ++++++++++++----------------
 4 files changed, 17 insertions(+), 17 deletions(-)
 copy src/flash/nand/{s3c2443.c => s3c6400.c} (81%)


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- Log -----------------------------------------------------------------
commit 24653c950a18c49d267efb17a36423d9c455a886
Author: Laurentiu Cocanu <lau...@zy...>
Date:   Thu Jan 14 13:59:36 2010 +0100

    str9x.c: remove optimization when erasing the whole bank
    
    Using the erase bank command will cause a time out error. Replacing
    this with the erase sector bank will provide a slower but safer and
    stable method to erase the flash.
    
    Signed-off-by: Laurentiu Cocanu <lau...@zy...>
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/flash/nor/str9x.c b/src/flash/nor/str9x.c
index bf3f750..d0c1278 100644
--- a/src/flash/nor/str9x.c
+++ b/src/flash/nor/str9x.c
@@ -230,17 +230,9 @@ static int str9x_erase(struct flash_bank *bank, int first, int last)
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	/* Check if we erase whole bank */
-	if ((first == 0) && (last == (bank->num_sectors - 1)))
-	{
-		/* Optimize to run erase bank command instead of sector */
-		erase_cmd = 0x80;
-	}
-	else
-	{
-		/* Erase sector command */
-		erase_cmd = 0x20;
-	}
+	/*A slower but stable way of erasing*/
+	/* Erase sector command */
+	erase_cmd = 0x20;
 
 	for (i = first; i <= last; i++)
 	{
@@ -296,10 +288,6 @@ static int str9x_erase(struct flash_bank *bank, int first, int last)
 			LOG_ERROR("error erasing flash bank, status: 0x%x", status);
 			return ERROR_FLASH_OPERATION_FAILED;
 		}
-
-		/* If we ran erase bank command, we are finished */
-		if (erase_cmd == 0x80)
-			break;
 	}
 
 	for (i = first; i <= last; i++)

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/str9x.c |   18 +++---------------
 1 files changed, 3 insertions(+), 15 deletions(-)


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- Log -----------------------------------------------------------------
commit e1679a29f084e3172077d513d14a0fde9ea2ea77
Author: David Brownell <dbr...@us...>
Date:   Thu Jan 14 03:16:07 2010 -0800

    ARM7/9 minor cleanups
    
    Shrink some overlong lines.  Add my 2009 copyright.
    Move a declaration to the beginning of its block.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 0f8f263..baf3e45 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -11,6 +11,8 @@
  *   Copyright (C) 2008 by Hongtao Zheng                                   *
  *   ho...@12...                                                        *
  *                                                                         *
+ *   Copyright (C) 2009 by David Brownell                                  *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -941,11 +943,11 @@ int arm7_9_poll(struct target *target)
 int arm7_9_assert_reset(struct target *target)
 {
 	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+	enum reset_types jtag_reset_config = jtag_get_reset_config();
 
 	LOG_DEBUG("target->state: %s",
 		  target_state_name(target));
 
-	enum reset_types jtag_reset_config = jtag_get_reset_config();
 	if (!(jtag_reset_config & RESET_HAS_SRST))
 	{
 		LOG_ERROR("Can't assert SRST");
@@ -973,28 +975,43 @@ int arm7_9_assert_reset(struct target *target)
 	if (target->reset_halt)
 	{
 		/*
-		 * Some targets do not support communication while SRST is asserted. We need to
-		 * set up the reset vector catch here.
+		 * For targets that don't support communication while SRST is
+		 * asserted, we need to set up the reset vector catch first.
 		 *
-		 * If TRST is asserted, then these settings will be reset anyway, so setting them
-		 * here is harmless.
+		 * When we use TRST+SRST and that's equivalent to a power-up
+		 * reset, these settings may well be reset anyway; so setting
+		 * them here won't matter.
 		 */
 		if (arm7_9->has_vector_catch)
 		{
-			/* program vector catch register to catch reset vector */
-			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_VEC_CATCH], 0x1);
+			/* program vector catch register to catch reset */
+			embeddedice_write_reg(&arm7_9->eice_cache
+					->reg_list[EICE_VEC_CATCH], 0x1);
 
-			/* extra runtest added as issues were found with certain ARM9 cores (maybe more) - AT91SAM9260 and STR9 */
+			/* extra runtest added as issues were found with
+			 * certain ARM9 cores (maybe more) - AT91SAM9260
+			 * and STR9
+			 */
 			jtag_add_runtest(1, jtag_get_end_state());
 		}
 		else
 		{
-			/* program watchpoint unit to match on reset vector address */
-			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], 0x0);
-			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_MASK], 0x3);
-			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_DATA_MASK], 0xffffffff);
-			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], EICE_W_CTRL_ENABLE);
-			embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_MASK], ~EICE_W_CTRL_nOPC & 0xff);
+			/* program watchpoint unit to match on reset vector
+			 * address
+			 */
+			embeddedice_write_reg(&arm7_9->eice_cache
+					->reg_list[EICE_W0_ADDR_VALUE], 0x0);
+			embeddedice_write_reg(&arm7_9->eice_cache
+					->reg_list[EICE_W0_ADDR_MASK], 0x3);
+			embeddedice_write_reg(&arm7_9->eice_cache
+					->reg_list[EICE_W0_DATA_MASK],
+						0xffffffff);
+			embeddedice_write_reg(&arm7_9->eice_cache
+					->reg_list[EICE_W0_CONTROL_VALUE],
+						EICE_W_CTRL_ENABLE);
+			embeddedice_write_reg(&arm7_9->eice_cache
+					->reg_list[EICE_W0_CONTROL_MASK],
+						~EICE_W_CTRL_nOPC & 0xff);
 		}
 	}
 
@@ -1012,9 +1029,10 @@ int arm7_9_assert_reset(struct target *target)
 
 	register_cache_invalidate(arm7_9->armv4_5_common.core_cache);
 
-	if ((target->reset_halt) && ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0))
+	if (target->reset_halt
+			&& !(jtag_reset_config & RESET_SRST_PULLS_TRST))
 	{
-		/* debug entry was already prepared in arm7_9_assert_reset() */
+		/* debug entry was prepared above */
 		target->debug_reason = DBG_REASON_DBGRQ;
 	}
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm7_9_common.c |   52 +++++++++++++++++++++++++++++--------------
 1 files changed, 35 insertions(+), 17 deletions(-)


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- Log -----------------------------------------------------------------
commit e2d3266ff1e10068d03e9a8ba3fc6c2238ff2251
Author: Spencer Oliver <nt...@us...>
Date:   Thu Jan 14 00:58:07 2010 +0000

    GDB: change gdb_breakpoint_override to COMMAND_ANY
    
     - enable gdb_breakpoint_override to be used within config script.
    
    Signed-off-by: Spencer Oliver <nt...@us...>

diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 4191cc2..d656745 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -2476,7 +2476,7 @@ static const struct command_registration gdb_command_handlers[] = {
 	{
 		.name = "gdb_breakpoint_override",
 		.handler = handle_gdb_breakpoint_override_command,
-		.mode = COMMAND_EXEC,
+		.mode = COMMAND_ANY,
 		.help = "Display or specify type of breakpoint "
 			"to be used by gdb 'break' commands.",
 		.usage = "('hard'|'soft'|'disable')"

-----------------------------------------------------------------------

Summary of changes:
 src/server/gdb_server.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


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- Log -----------------------------------------------------------------
commit b60dd35e33b622216c12d5804f949df087eb59fa
Author: David Brownell <dbr...@us...>
Date:   Wed Jan 13 23:33:53 2010 -0800

    User's Guide updates
    
    Capture various bits of useful information that have come up on the
    list but haven't yet gotten into the documentation:
    
     - Watchdog timers firing during JTAG debug need attention;
    
     - Some chips have special registers to help JTAG debug;
    
     - Cortex-M3 stepping example with IRQs and maskisr;
    
     - Clarifications re adaptive clocking:  not all ARMs do it, and
       explain it a bit better.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 3e0b5db..4446046 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -942,6 +942,33 @@ handling issues like:
 
 @itemize @bullet
 
+@item @b{Watchdog Timers}...
+Watchog timers are typically used to automatically reset systems if
+some application task doesn't periodically reset the timer.  (The
+assumption is that the system has locked up if the task can't run.)
+When a JTAG debugger halts the system, that task won't be able to run
+and reset the timer ... potentially causing resets in the middle of
+your debug sessions.
+
+It's rarely a good idea to disable such watchdogs, since their usage
+needs to be debugged just like all other parts of your firmware.
+That might however be your only option.
+
+Look instead for chip-specific ways to stop the watchdog from counting
+while the system is in a debug halt state.  It may be simplest to set
+that non-counting mode in your debugger startup scripts.  You may however
+need a different approach when, for example, a motor could be physically
+damaged by firmware remaining inactive in a debug halt state.  That might
+involve a type of firmware mode where that "non-counting" mode is disabled
+at the beginning then re-enabled at the end; a watchdog reset might fire
+and complicate the debug session, but hardware (or people) would be
+protected.@footnote{Note that many systems support a "monitor mode" debug
+that is a somewhat cleaner way to address such issues.  You can think of
+it as only halting part of the system, maybe just one task,
+instead of the whole thing.
+At this writing, January 2010, OpenOCD based debugging does not support
+monitor mode debug, only "halt mode" debug.}
+
 @item @b{ARM Semihosting}...
 @cindex ARM semihosting
 When linked with a special runtime library provided with many
@@ -964,7 +991,12 @@ via the @code{WFI} instruction (or its coprocessor equivalent, before ARMv7).
 
 You may want to @emph{disable that instruction} in source code,
 or otherwise prevent using that state,
-to ensure you can get JTAG access at any time.
+to ensure you can get JTAG access at any time.@footnote{As a more
+polite alternative, some processors have special debug-oriented
+registers which can be used to change various features including
+how the low power states are clocked while debugging.
+The STM32 DBGMCU_CR register is an example; at the cost of extra
+power consumption, JTAG can be used during low power states.}
 For example, the OpenOCD @command{halt} command may not
 work for an idle processor otherwise.
 
@@ -6699,8 +6731,10 @@ to debug remote targets.
 Setting up GDB to work with OpenOCD can involve several components:
 
 @itemize
-@item OpenOCD itself may need to be configured.  @xref{GDB Configuration}.
-@item GDB itself may need configuration, as shown in this chapter.
+@item The OpenOCD server support for GDB may need to be configured.
+@xref{GDB Configuration}.
+@item GDB's support for OpenOCD may need configuration,
+as shown in this chapter.
 @item If you have a GUI environment like Eclipse,
 that also will probably need to be configured.
 @end itemize
@@ -6803,6 +6837,24 @@ With that particular hardware (Cortex-M3) the hardware breakpoints
 only work for code running from flash memory.  Most other ARM systems
 do not have such restrictions.
 
+Another example of useful GDB configuration came from a user who
+found that single stepping his Cortex-M3 didn't work well with IRQs
+and an RTOS until he told GDB to disable the IRQs while stepping:
+
+@example
+define hook-step
+mon cortex_m3 maskisr on
+end
+define hookpost-step
+mon cortex_m3 maskisr off
+end
+@end example
+
+Rather than typing such commands interactively, you may prefer to
+save them in a file and have GDB execute them as it starts, perhaps
+using a @file{.gdbinit} in your project directory or starting GDB
+using @command{gdb -x filename}.
+
 @section Programming using GDB
 @cindex Programming using GDB
 
@@ -6947,36 +6999,48 @@ is jim, not real tcl).
 
 In digital circuit design it is often refered to as ``clock
 synchronisation'' the JTAG interface uses one clock (TCK or TCLK)
-operating at some speed, your target is operating at another.  The two
-clocks are not synchronised, they are ``asynchronous''
+operating at some speed, your CPU target is operating at another.
+The two clocks are not synchronised, they are ``asynchronous''
 
-In order for the two to work together they must be synchronised. Otherwise
-the two systems will get out of sync with each other and nothing will
-work. There are 2 basic options:
+In order for the two to work together they must be synchronised
+well enough to work; JTAG can't go ten times faster than the CPU,
+for example.  There are 2 basic options:
 @enumerate
 @item
-Use a special circuit.
+Use a special "adaptive clocking" circuit to change the JTAG
+clock rate to match what the CPU currently supports.
 @item
-One clock must be some multiple slower than the other.
+The JTAG clock must be fixed at some speed that's enough slower than
+the CPU clock that all TMS and TDI transitions can be detected.
 @end enumerate
 
 @b{Does this really matter?} For some chips and some situations, this
-is a non-issue (i.e.: A 500MHz ARM926) but for others - for example some
-Atmel SAM7 and SAM9 chips start operation from reset at 32kHz -
-program/enable the oscillators and eventually the main clock. It is in
-those critical times you must slow the JTAG clock to sometimes 1 to
-4kHz.
-
-Imagine debugging a 500MHz ARM926 hand held battery powered device
-that ``deep sleeps'' at 32kHz between every keystroke. It can be
-painful.
+is a non-issue, like a 500MHz ARM926 with a 5 MHz JTAG link;
+the CPU has no difficulty keeping up with JTAG.
+Startup sequences are often problematic though, as are other
+situations where the CPU clock rate changes (perhaps to save
+power).
+
+For example, Atmel AT91SAM chips start operation from reset with
+a 32kHz system clock.  Boot firmware may activate the main oscillator
+and PLL before switching to a faster clock (perhaps that 500 MHz
+ARM926 scenario).
+If you're using JTAG to debug that startup sequence, you must slow
+the JTAG clock to sometimes 1 to 4kHz.  After startup completes,
+JTAG can use a faster clock.
+
+Consider also debugging a 500MHz ARM926 hand held battery powered
+device that enters a low power ``deep sleep'' mode, at 32kHz CPU
+clock, between keystrokes unless it has work to do.   When would
+that 5 MHz JTAG clock be usable?
 
 @b{Solution #1 - A special circuit}
 
-In order to make use of this, your JTAG dongle must support the RTCK
+In order to make use of this,
+both your CPU and your JTAG dongle must support the RTCK
 feature. Not all dongles support this - keep reading!
 
-The RTCK signal often found in some ARM chips is used to help with
+The RTCK ("Return TCK") signal in some ARM chips is used to help with
 this problem. ARM has a good description of the problem described at
 this link: @url{http://www.arm.com/support/faqdev/4170.html} [checked
 28/nov/2008]. Link title: ``How does the JTAG synchronisation logic
@@ -7013,8 +7077,9 @@ ARM11 cores use an 8:1 division.
 Note: Many FTDI2232C based JTAG dongles are limited to 6MHz.
 
 You can still debug the 'low power' situations - you just need to
-manually adjust the clock speed at every step. While painful and
-tedious, it is not always practical.
+either use a fixed and very slow JTAG clock rate ... or else
+manually adjust the clock speed at every step. (Adjusting is painful
+and tedious, and is not always practical.)
 
 It is however easy to ``code your way around it'' - i.e.: Cheat a little,
 have a special debug mode in your application that does a ``high power

commit 73566405b6e105b0a8b7f21db48331926bec97ad
Author: David Brownell <dbr...@us...>
Date:   Wed Jan 13 23:33:25 2010 -0800

    NOR: add optional "flash erase_address" sector padding
    
    Add a NOR flash mechanism where erase_address ranges can be padded
    out to sector boundaries, triggering a diagnostic:
    
      > flash erase_address 0x0001f980 16
      address range 0x0001f980 .. 0x0001f98f is not sector-aligned
      Command handler execution failed
      in procedure 'flash' called at file "command.c", line 647
      called at file "command.c", line 361
      >
    
      > flash erase_address pad 0x0001f980 16
      Adding extra erase range, 0x0001f800 to 0x0001f97f
      Adding extra erase range, 0x0001f990 to 0x0001fbff
      erased address 0x0001f980 (length 16) in 0.095975s (0.163 kb/s)
      >
    
    This addresses what would otherwise be something of a functional
    regression.  An earlier version of the interface had a dangerous
    problem:  it would silently erase data outside the range it was
    told to erase.  Fixing that bug turned up some folk who relied on
    that unsafe behavior.  (The classic problem with interface bugs!)
    Now they can get that behavior again.  If they really need it,
    just specify "pad".
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/NEWS b/NEWS
index a8b2b44..ce4896f 100644
--- a/NEWS
+++ b/NEWS
@@ -50,7 +50,9 @@ Flash Layer:
 		- <driver_name>[.N]: reference the driver's Nth bank
 	New 'nand verify' command to check bank against an image file.
 	The "flash erase_address" command now rejects partial sectors;
-		previously it would silently erase extra data.
+		previously it would silently erase extra data.  If you
+		want to erase the rest of the first and/or last sectors
+		instead of failing, you must pass an explicit "pad" flag.
 	New at91sam9 NAND controller driver.
 
 Board, Target, and Interface Configuration Scripts:
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 0eb40b1..3e0b5db 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -3841,8 +3841,12 @@ specifies "to the end of the flash bank".
 The @var{num} parameter is a value shown by @command{flash banks}.
 @end deffn
 
-@deffn Command {flash erase_address} address length
+@deffn Command {flash erase_address} [@option{pad}] address length
 Erase sectors starting at @var{address} for @var{length} bytes.
+Unless @option{pad} is specified, @math{address} must begin a
+flash sector, and @math{address + length - 1} must end a sector.
+Specifying @option{pad} erases extra data at the beginning and/or
+end of the specified region, as needed to erase only full sectors.
 The flash bank to use is inferred from the @var{address}, and
 the specified length must stay within that bank.
 As a special case, when @var{length} is zero and @var{address} is
diff --git a/src/flash/nor/core.c b/src/flash/nor/core.c
index 9083ed1..aedaa86 100644
--- a/src/flash/nor/core.c
+++ b/src/flash/nor/core.c
@@ -287,9 +287,22 @@ int default_flash_blank_check(struct flash_bank *bank)
 	return ERROR_OK;
 }
 
-/* erase given flash region, selects proper bank according to target and address */
+/* Manipulate given flash region, selecting the bank according to target
+ * and address.  Maps an address range to a set of sectors, and issues
+ * the callback() on that set ... e.g. to erase or unprotect its members.
+ *
+ * (Note a current bad assumption:  that protection operates on the same
+ * size sectors as erase operations use.)
+ *
+ * The "pad_reason" parameter is a kind of boolean:  when it's NULL, the
+ * range must fit those sectors exactly.  This is clearly safe; it can't
+ * erase data which the caller said to leave alone, for example.  If it's
+ * non-NULL, rather than failing, extra data in the first and/or last
+ * sectors will be added to the range, and that reason string is used when
+ * warning about those additions.
+ */
 static int flash_iterate_address_range(struct target *target,
-		uint32_t addr, uint32_t length,
+		char *pad_reason, uint32_t addr, uint32_t length,
 		int (*callback)(struct flash_bank *bank, int first, int last))
 {
 	struct flash_bank *c;
@@ -328,18 +341,53 @@ static int flash_iterate_address_range(struct target *target,
 	for (i = 0; i < c->num_sectors; i++)
 	{
 		struct flash_sector *f = c->sectors + i;
+		uint32_t end = f->offset + f->size;
 
 		/* start only on a sector boundary */
 		if (first < 0) {
+			/* scanned past the first sector? */
+			if (addr < f->offset)
+				break;
+
 			/* is this the first sector? */
 			if (addr == f->offset)
 				first = i;
-			else if (addr < f->offset)
-				break;
+
+			/* Does this need head-padding?  If so, pad and warn;
+			 * or else force an error.
+			 *
+			 * Such padding can make trouble, since *WE* can't
+			 * ever know if that data was in use.  The warning
+			 * should help users sort out messes later.
+			 */
+			else if (addr < end && pad_reason) {
+				/* FIXME say how many bytes (e.g. 80 KB) */
+				LOG_WARNING("Adding extra %s range, "
+						"%#8.8x to %#8.8x",
+					pad_reason,
+					(unsigned) f->offset,
+					(unsigned) addr - 1);
+				first = i;
+			} else
+				continue;
 		}
 
 		/* is this (also?) the last sector? */
-		if (last_addr == f->offset + f->size) {
+		if (last_addr == end) {
+			last = i;
+			break;
+		}
+
+		/* Does this need tail-padding?  If so, pad and warn;
+		 * or else force an error.
+		 */
+		if (last_addr < end && pad_reason) {
+			/* FIXME say how many bytes (e.g. 80 KB) */
+			LOG_WARNING("Adding extra %s range, "
+					"%#8.8x to %#8.8x",
+				pad_reason,
+				(unsigned) last_addr,
+				(unsigned) end - 1);
 			last = i;
 			break;
 		}
@@ -358,18 +406,17 @@ static int flash_iterate_address_range(struct target *target,
 		return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 	}
 
-	/* The NOR driver may trim this range down, based on
-	 * whether or not a given sector is already erased.
-	 *
-	 * REVISIT should *we* trim it... ?
+	/* The NOR driver may trim this range down, based on what
+	 * sectors are already erased/unprotected.  GDB currently
+	 * blocks such optimizations.
 	 */
 	return callback(c, first, last);
 }
 
 int flash_erase_address_range(struct target *target,
-		uint32_t addr, uint32_t length)
+		bool pad, uint32_t addr, uint32_t length)
 {
-	return flash_iterate_address_range(target,
+	return flash_iterate_address_range(target, pad ? "erase" : NULL,
 			addr, length, &flash_driver_erase);
 }
 
@@ -380,7 +427,11 @@ static int flash_driver_unprotect(struct flash_bank *bank, int first, int last)
 
 static int flash_unlock_address_range(struct target *target, uint32_t addr, uint32_t length)
 {
-	return flash_iterate_address_range(target,
+	/* By default, pad to sector boundaries ... the real issue here
+	 * is that our (only) caller *permanently* removes protection,
+	 * and doesn't restore it.
+	 */
+	return flash_iterate_address_range(target, "unprotect",
 			addr, length, &flash_driver_unprotect);
 }
 
@@ -394,6 +445,12 @@ int flash_write_unlock(struct target *target, struct image *image,
 	struct flash_bank *c;
 	int *padding;
 
+	/* REVISIT do_pad should perhaps just be another parameter.
+	 * GDB wouldn't ever need it, since it erases separately.
+	 * But "flash write_image" commands might want that option.
+	 */
+	bool do_pad = false;
+
 	section = 0;
 	section_offset = 0;
 
@@ -470,7 +527,8 @@ int flash_write_unlock(struct target *target, struct image *image,
 			 * In both cases, the extra writes slow things down.
 			 */
 
-			/* if we have multiple sections within our image, flash programming could fail due to alignment issues
+			/* if we have multiple sections within our image,
+			 * flash programming could fail due to alignment issues
 			 * attempt to rebuild a consecutive buffer for the flash loader */
 			pad_bytes = (image->sections[section_last + 1].base_address) - (run_address + run_size);
 			if ((run_address + run_size + pad_bytes) > (c->base + c->size))
@@ -560,7 +618,8 @@ int flash_write_unlock(struct target *target, struct image *image,
 			if (erase)
 			{
 				/* calculate and erase sectors */
-				retval = flash_erase_address_range(target, run_address, run_size);
+				retval = flash_erase_address_range(target,
+						do_pad, run_address, run_size);
 			}
 		}
 
diff --git a/src/flash/nor/core.h b/src/flash/nor/core.h
index 36e163d..b164b8d 100644
--- a/src/flash/nor/core.h
+++ b/src/flash/nor/core.h
@@ -102,10 +102,14 @@ int flash_init_drivers(struct command_context *cmd_ctx);
 
 /**
  * Erases @a length bytes in the @a target flash, starting at @a addr.
+ * The range @a addr to @a addr + @a length - 1 must be strictly
+ * sector aligned, unless @a pad is true.  Setting @a pad true extends
+ * the range, at beginning and/or end, if needed for sector alignment.
  * @returns ERROR_OK if successful; otherwise, an error code.
  */
 int flash_erase_address_range(struct target *target,
-		uint32_t addr, uint32_t length);
+		bool pad, uint32_t addr, uint32_t length);
+
 /**
  * Writes @a image into the @a target flash.  The @a written parameter
  * will contain the
diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
index b7e80df..cf40a81 100644
--- a/src/flash/nor/tcl.c
+++ b/src/flash/nor/tcl.c
@@ -203,14 +203,29 @@ COMMAND_HANDLER(handle_flash_erase_address_command)
 	int retval;
 	int address;
 	int length;
-
+	bool do_pad = false;
 	struct target *target = get_current_target(CMD_CTX);
 
-	if (CMD_ARGC != 2)
+	switch (CMD_ARGC) {
+	case 3:
+		/* Optionally pad out the address range to block/sector
+		 * boundaries.  We can't know if there's data in that part
+		 * of the flash; only do padding if we're told to.
+		 */
+		if (strcmp("pad", CMD_ARGV[0]) != 0)
+			return ERROR_COMMAND_SYNTAX_ERROR;
+		do_pad = true;
+		CMD_ARGC--;
+		CMD_ARGV++;
+		/* FALL THROUGH */
+	case 2:
+		COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], address);
+		COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], length);
+		break;
+	default:
 		return ERROR_COMMAND_SYNTAX_ERROR;
+	}
 
-	COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], address);
-	COMMAND_PARSE_NUMBER(int, CMD_ARGV[1], length);
 	if (length <= 0)
 	{
 		command_print(CMD_CTX, "Length must be >0");
@@ -229,7 +244,7 @@ COMMAND_HANDLER(handle_flash_erase_address_command)
 	struct duration bench;
 	duration_start(&bench);
 
-	retval = flash_erase_address_range(target, address, length);
+	retval = flash_erase_address_range(target, do_pad, address, length);
 
 	if ((ERROR_OK == retval) && (duration_measure(&bench) == ERROR_OK))
 	{
@@ -698,9 +713,12 @@ static const struct command_registration flash_exec_command_handlers[] = {
 		.name = "erase_address",
 		.handler = handle_flash_erase_address_command,
 		.mode = COMMAND_EXEC,
-		.usage = "address length",
-		.help = "Erase flash blocks starting at address "
-			"and continuing for length bytes.",
+		.usage = "['pad'] address length",
+		.help = "Erase flash sectors starting at address and "
+			"continuing for length bytes.  If 'pad' is specified, "
+			"data outside that range may also be erased: the start "
+			"address may be decreased, and length increased, so "
+			"that all of the first and last sectors are erased.",
 	},
 	{
 		.name = "fillw",
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 8018e6f..4191cc2 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -1928,9 +1928,19 @@ int gdb_v_packet(struct connection *connection, struct target *target, char *pac
 		flash_set_dirty();
 
 		/* perform any target specific operations before the erase */
-		target_call_event_callbacks(gdb_service->target, TARGET_EVENT_GDB_FLASH_ERASE_START);
-		result = flash_erase_address_range(gdb_service->target, addr, length);
-		target_call_event_callbacks(gdb_service->target, TARGET_EVENT_GDB_FLASH_ERASE_END);
+		target_call_event_callbacks(gdb_service->target,
+				TARGET_EVENT_GDB_FLASH_ERASE_START);
+
+		/* vFlashErase:addr,length messages require region start and
+		 * end to be "block" aligned ... if padding is ever needed,
+		 * GDB will have become dangerously confused.
+		 */
+		result = flash_erase_address_range(gdb_service->target,
+				false, addr, length);
+
+		/* perform any target specific operations after the erase */
+		target_call_event_callbacks(gdb_service->target,
+				TARGET_EVENT_GDB_FLASH_ERASE_END);
 
 		/* perform erase */
 		if (result != ERROR_OK)

-----------------------------------------------------------------------

Summary of changes:
 NEWS                    |    4 +-
 doc/openocd.texi        |  117 +++++++++++++++++++++++++++++++++++++----------
 src/flash/nor/core.c    |   87 +++++++++++++++++++++++++++++------
 src/flash/nor/core.h    |    6 ++-
 src/flash/nor/tcl.c     |   34 ++++++++++---
 src/server/gdb_server.c |   16 +++++-
 6 files changed, 213 insertions(+), 51 deletions(-)


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- Log -----------------------------------------------------------------
commit d91941d5a01ca0b9d43571edc03ba18741076cca
Author: David Brownell <dbr...@us...>
Date:   Wed Jan 13 03:16:37 2010 -0800

    Cortex-M3: improved core exception handling
    
    This updates three aspects of debugger/exception interactions:
    
     - Save the user's "vector_catch" setting, and restore it after reset.
       Previously, it was obliterated (rather annoyingly) each time.
    
     - Don't catch BusFault and HardFault exceptions unless the user says
       to do so.  Target firmware may need to handle them.
    
     - Don't modify SHCSR to prevent escalating BusFault to HardFault.
       Target firmware may expect to handle it as a HardFault.
    
    Those simplifications fix several bugs.  In one annoying case, OpenOCD
    would cause the target to lock up on ome faults which triggered after
    the debugger disconnected.
    
    NOTE:  a known remaining issue is that OpenOCD can still leave DEMCR
    set after an otherwise-clean OpenOCD shutdown.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/NEWS b/NEWS
index b169606..a8b2b44 100644
--- a/NEWS
+++ b/NEWS
@@ -34,6 +34,8 @@ Target Layer:
 		- watchpoint support
 	Cortex-M3
 		- Exposed DWT registers like cycle counter
+		- vector_catch settings not clobbered by resets
+		- no longer interferes with firmware's fault handling
 	ETM, ETB
 		- "trigger_percent" command moved ETM --> ETB
 		- "etm trigger_debug" command added
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index ac559b9..86caae2 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -106,9 +106,14 @@ struct armv7m_common
 	int exception_number;
 	struct swjdp_common swjdp_info;
 
+	uint32_t demcr;
+
 	/* Direct processor core register read and writes */
-	int (*load_core_reg_u32)(struct target *target, enum armv7m_regtype type, uint32_t num, uint32_t *value);
-	int (*store_core_reg_u32)(struct target *target, enum armv7m_regtype type, uint32_t num, uint32_t value);
+	int (*load_core_reg_u32)(struct target *target,
+		enum armv7m_regtype type, uint32_t num, uint32_t *value);
+	int (*store_core_reg_u32)(struct target *target,
+		enum armv7m_regtype type, uint32_t num, uint32_t value);
+
 	/* register cache to processor synchronization */
 	int (*read_core_reg)(struct target *target, unsigned num);
 	int (*write_core_reg)(struct target *target, unsigned num);
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index c6b1bb2..48f8114 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -185,11 +185,12 @@ static int cortex_m3_endreset_event(struct target *target)
 	int i;
 	uint32_t dcb_demcr;
 	struct cortex_m3_common *cortex_m3 = target_to_cm3(target);
+	struct armv7m_common *armv7m = &cortex_m3->armv7m;
 	struct swjdp_common *swjdp = &cortex_m3->armv7m.swjdp_info;
 	struct cortex_m3_fp_comparator *fp_list = cortex_m3->fp_comparator_list;
 	struct cortex_m3_dwt_comparator *dwt_list = cortex_m3->dwt_comparator_list;
 
-	/* FIXME handling of DEMCR clobbers vector_catch config ... */
+	/* REVISIT The four debug monitor bits are currently ignored... */
 	mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
 	LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
 
@@ -204,21 +205,14 @@ static int cortex_m3_endreset_event(struct target *target)
 	/* clear any interrupt masking */
 	cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
 
-	/* Enable trace and DWT; trap hard and bus faults.
+	/* Enable features controlled by ITM and DWT blocks, and catch only
+	 * the vectors we were told to pay attention to.
 	 *
-	 * REVISIT why trap those two?  And why trash the vector_catch
-	 * config, instead of preserving it?  Catching HARDERR and BUSERR
-	 * will interfere with code that handles those itself...
+	 * Target firmware is responsible for all fault handling policy
+	 * choices *EXCEPT* explicitly scripted overrides like "vector_catch"
+	 * or manual updates to the NVIC SHCSR and CCR registers.
 	 */
-	mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
-
-	/* Monitor bus faults as such (instead of as generic HARDERR), but
-	 * leave memory management and usage faults disabled.
-	 *
-	 * REVISIT setting BUSFAULTENA interferes with code which relies
-	 * on the default setting.  Why do it?
-	 */
-	mem_ap_write_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
+	mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | armv7m->demcr);
 
 	/* Paranoia: evidently some (early?) chips don't preserve all the
 	 * debug state (including FBP, DWT, etc) across reset...
@@ -533,7 +527,7 @@ static int cortex_m3_soft_reset_halt(struct target *target)
 	uint32_t dcb_dhcsr = 0;
 	int retval, timeout = 0;
 
-	/* Enter debug state on reset; see end_reset_event() */
+	/* Enter debug state on reset; restore DEMCR in endreset_event() */
 	mem_ap_write_u32(swjdp, DCB_DEMCR,
 			TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 
@@ -782,14 +776,15 @@ static int cortex_m3_assert_reset(struct target *target)
 
 		/* clear C_HALT in dhcsr reg */
 		cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
-
-		/* Enter debug state on reset, cf. end_reset_event() */
-		mem_ap_write_u32(swjdp, DCB_DEMCR,
-				TRCENA | VC_HARDERR | VC_BUSERR);
 	}
 	else
 	{
-		/* Enter debug state on reset, cf. end_reset_event() */
+		/* Halt in debug on reset; endreset_event() restores DEMCR.
+		 *
+		 * REVISIT catching BUSERR presumably helps to defend against
+		 * bad vector table entries.  Should this include MMERR or
+		 * other flags too?
+		 */
 		mem_ap_write_atomic_u32(swjdp, DCB_DEMCR,
 				TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
 	}
@@ -1938,12 +1933,20 @@ COMMAND_HANDLER(handle_cortex_m3_vector_catch_command)
 			}
 		}
 write:
+		/* For now, armv7m->demcr only stores vector catch flags. */
+		armv7m->demcr = catch;
+
 		demcr &= ~0xffff;
 		demcr |= catch;
 
-		/* write, but don't assume it stuck */
+		/* write, but don't assume it stuck (why not??) */
 		mem_ap_write_u32(swjdp, DCB_DEMCR, demcr);
 		mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &demcr);
+
+		/* FIXME be sure to clear DEMCR on clean server shutdown.
+		 * Otherwise the vector catch hardware could fire when there's
+		 * no debugger hooked up, causing much confusion...
+		 */
 	}
 
 	for (unsigned i = 0; i < ARRAY_SIZE(vec_ids); i++)

-----------------------------------------------------------------------

Summary of changes:
 NEWS                   |    2 ++
 src/target/armv7m.h    |    9 +++++++--
 src/target/cortex_m3.c |   45 ++++++++++++++++++++++++---------------------
 3 files changed, 33 insertions(+), 23 deletions(-)


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- Log -----------------------------------------------------------------
commit b8e930e3bfc78f4a0582edb8b7cec44b5c9f4cad
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Jan 11 15:30:22 2010 +0100

    arm7/9: enable check that DCC downloads have been enabled
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 2f51699..a5dde2c 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -578,4 +578,5 @@ struct target_type arm720t_target =
 	.target_create = arm720t_target_create,
 	.init_target = arm720t_init_target,
 	.examine = arm7_9_examine,
+	.check_reset = arm7_9_check_reset,
 };
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index a5a0f80..0f8f263 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2732,6 +2732,8 @@ int arm7_9_check_reset(struct target *target)
 	{
 		LOG_WARNING("NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.");
 	}
+
+	return ERROR_OK;
 }
 
 COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index d576d07..16f16b0 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -752,4 +752,5 @@ struct target_type arm7tdmi_target =
 	.target_create  = arm7tdmi_target_create,
 	.init_target = arm7tdmi_init_target,
 	.examine = arm7_9_examine,
+	.check_reset = arm7_9_check_reset,
 };
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 29eb62d..e0b1c70 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -1476,4 +1476,5 @@ struct target_type arm920t_target =
 	.target_create = arm920t_target_create,
 	.init_target = arm9tdmi_init_target,
 	.examine = arm7_9_examine,
+	.check_reset = arm7_9_check_reset,
 };
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index e099919..32ecf72 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -815,6 +815,7 @@ struct target_type arm926ejs_target =
 	.target_create = arm926ejs_target_create,
 	.init_target = arm9tdmi_init_target,
 	.examine = arm7_9_examine,
+	.check_reset = arm7_9_check_reset,
 	.virt2phys = arm926ejs_virt2phys,
 	.mmu = arm926ejs_mmu,
 
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index 86af0f6..2f5e390 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -294,4 +294,5 @@ struct target_type arm966e_target =
 	.target_create = arm966e_target_create,
 	.init_target = arm9tdmi_init_target,
 	.examine = arm7_9_examine,
+	.check_reset = arm7_9_check_reset,
 };
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 823e962..761e7cf 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -975,4 +975,5 @@ struct target_type arm9tdmi_target =
 	.target_create = arm9tdmi_target_create,
 	.init_target = arm9tdmi_init_target,
 	.examine = arm7_9_examine,
+	.check_reset = arm7_9_check_reset,
 };
diff --git a/src/target/fa526.c b/src/target/fa526.c
index 7c6cae6..b6149e3 100644
--- a/src/target/fa526.c
+++ b/src/target/fa526.c
@@ -390,4 +390,5 @@ struct target_type fa526_target =
 	.target_create = fa526_target_create,
 	.init_target = arm9tdmi_init_target,
 	.examine = arm7_9_examine,
+	.check_reset = arm7_9_check_reset,
 };

commit ee519ab3562870aa5bb1bc79f3c24cb3b3074d65
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Jan 11 15:29:09 2010 +0100

    arm7/9: add fn to check if dcc downloads have been enabled
    
    DCC downloads should be enabled for any self repecting
    openocd config file for arm7/9. Print out note about
    it otherwise.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 2f4c408..a5a0f80 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dom...@gm...                                                   *
  *                                                                         *
- *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
+ *   Copyright (C) 2007-2009 Øyvind Harboe                                 *
  *   oyv...@zy...                                               *
  *                                                                         *
  *   Copyright (C) 2008 by Spencer Oliver                                  *
@@ -2723,6 +2723,17 @@ int arm7_9_examine(struct target *target)
 	return retval;
 }
 
+
+int arm7_9_check_reset(struct target *target)
+{
+	struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+
+	if (get_target_reset_nag() && !arm7_9->dcc_downloads)
+	{
+		LOG_WARNING("NOTE! DCC downloads have not been enabled, defaulting to slow memory writes. Type 'help dcc'.");
+	}
+}
+
 COMMAND_HANDLER(handle_arm7_9_dbgrq_command)
 {
 	struct target *target = get_current_target(CMD_CTX);
diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h
index 021238e..93bee07 100644
--- a/src/target/arm7_9_common.h
+++ b/src/target/arm7_9_common.h
@@ -157,5 +157,6 @@ int arm7_9_execute_sys_speed(struct target *target);
 
 int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9);
 int arm7_9_examine(struct target *target);
+int arm7_9_check_reset(struct target *target);
 
 #endif /* ARM7_9_COMMON_H */

commit dc793455e9a04be556b0b25eb1513ecbb7be3f51
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Jan 11 15:28:18 2010 +0100

    target: add check_reset hook
    
    Allow targets to run checks post reset. Used to check
    that e.g. DCC downloads have been enabled.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/target.c b/src/target/target.c
index 7994aff..c56265c 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -477,6 +477,11 @@ int target_process_reset(struct command_context *cmd_ctx, enum target_reset_mode
 	/* We want any events to be processed before the prompt */
 	retval = target_call_timer_callbacks_now();
 
+	struct target *target;
+	for (target = all_targets; target; target = target->next) {
+		target->type->check_reset(target);
+	}
+
 	return retval;
 }
 
@@ -499,6 +504,12 @@ static int default_examine(struct target *target)
 	return ERROR_OK;
 }
 
+/* no check by default */
+static int default_check_reset(struct target *target)
+{
+	return ERROR_OK;
+}
+
 int target_examine_one(struct target *target)
 {
 	return target->type->examine(target);
@@ -708,6 +719,9 @@ static int target_init_one(struct command_context *cmd_ctx,
 	if (type->examine == NULL)
 		type->examine = default_examine;
 
+	if (type->check_reset== NULL)
+		type->check_reset = default_check_reset;
+
 	int retval = type->init_target(cmd_ctx, target);
 	if (ERROR_OK != retval)
 	{
@@ -4887,6 +4901,20 @@ int target_register_commands(struct command_context *cmd_ctx)
 	return register_commands(cmd_ctx, NULL, target_command_handlers);
 }
 
+static bool target_reset_nag = true;
+
+bool get_target_reset_nag(void)
+{
+	return target_reset_nag;
+}
+
+COMMAND_HANDLER(handle_target_reset_nag)
+{
+	return CALL_COMMAND_HANDLER(handle_command_parse_bool,
+			&target_reset_nag, "Nag after each reset about options to improve "
+			"performance");
+}
+
 static const struct command_registration target_exec_command_handlers[] = {
 	{
 		.name = "fast_load_image",
@@ -5088,6 +5116,14 @@ static const struct command_registration target_exec_command_handlers[] = {
 			"and write the 8/16/32 bit values",
 		.usage = "arrayname bitwidth address count",
 	},
+	{
+		.name = "reset_nag",
+		.handler = handle_target_reset_nag,
+		.mode = COMMAND_ANY,
+		.help = "Nag after each reset about options that could have been "
+				"enabled to improve performance. ",
+		.usage = "['enable'|'disable']",
+	},
 	COMMAND_REGISTRATION_DONE
 };
 int target_register_user_commands(struct command_context *cmd_ctx)
diff --git a/src/target/target.h b/src/target/target.h
index 4151c22..da91d46 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dom...@gm...                                                   *
  *                                                                         *
- *   Copyright (C) 2007,2008,2009 Øyvind Harboe                            *
+ *   Copyright (C) 2007-9 Øyvind Harboe                                    *
  *   oyv...@zy...                                               *
  *                                                                         *
  *   Copyright (C) 2008 by Spencer Oliver                                  *
@@ -483,4 +483,6 @@ void target_all_handle_event(enum target_event e);
 
 const char *target_strerror_safe(int err);
 
+extern bool get_target_reset_nag(void);
+
 #endif /* TARGET_H */
diff --git a/src/target/target_type.h b/src/target/target_type.h
index 67041b3..70eb962 100644
--- a/src/target/target_type.h
+++ b/src/target/target_type.h
@@ -213,6 +213,13 @@ struct target_type
 
 	int (*mmu)(struct target *target, int *enabled);
 
+	/* after reset is complete, the target can check if things are properly set up.
+	 *
+	 * This can be used to check if e.g. DCC memory writes have been enabled for
+	 * arm7/9 targets, which they really should except in the most contrived
+	 * circumstances.
+	 */
+	int (*check_reset)(struct target *target);
 };
 
 #endif // TARGET_TYPE_H

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm720t.c       |    1 +
 src/target/arm7_9_common.c |   15 ++++++++++++++-
 src/target/arm7_9_common.h |    1 +
 src/target/arm7tdmi.c      |    1 +
 src/target/arm920t.c       |    1 +
 src/target/arm926ejs.c     |    1 +
 src/target/arm966e.c       |    1 +
 src/target/arm9tdmi.c      |    1 +
 src/target/fa526.c         |    1 +
 src/target/target.c        |   36 ++++++++++++++++++++++++++++++++++++
 src/target/target.h        |    4 +++-
 src/target/target_type.h   |    7 +++++++
 12 files changed, 68 insertions(+), 2 deletions(-)


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commit 3e33393078105f25ebd591b5b76c7c1501ff41d5
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Jan 11 09:22:08 2010 +0100

    gdbserver: fix typo that broke read/write watchpoint
    
    It looks like a bugfix from normal breakpoints was not
    copied over.
    
    Do not use clever mathematics and assumptions to convert from
    GDB enum for break/watchpoints to OpenOCD enum.
    
    Drop connection upon unknown breakpoint type, this code path
    was not really considered by the previous code I think.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index f4a99ca..8018e6f 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -1423,7 +1423,7 @@ int gdb_breakpoint_watchpoint_packet(struct connection *connection, struct targe
 {
 	int type;
 	enum breakpoint_type bp_type = BKPT_SOFT /* dummy init to avoid warning */;
-	enum watchpoint_rw wp_type;
+	enum watchpoint_rw wp_type = WPT_READ /* dummy init to avoid warning */;
 	uint32_t address;
 	uint32_t size;
 	char *separator;
@@ -1443,6 +1443,12 @@ int gdb_breakpoint_watchpoint_packet(struct connection *connection, struct targe
 		wp_type = WPT_READ;
 	else if (type == 4) /* access watchpoint */
 		wp_type = WPT_ACCESS;
+	else
+	{
+		LOG_ERROR("invalid gdb watch/breakpoint type(%d), dropping connection", type);
+		return ERROR_SERVER_REMOTE_CLOSED;
+	}
+
 
 	if (gdb_breakpoint_override && ((bp_type == BKPT_SOFT)||(bp_type == BKPT_HARD)))
 	{
@@ -1493,7 +1499,7 @@ int gdb_breakpoint_watchpoint_packet(struct connection *connection, struct targe
 		{
 			if (packet[0] == 'Z')
 			{
-				if ((retval = watchpoint_add(target, address, size, type-2, 0, 0xffffffffu)) != ERROR_OK)
+				if ((retval = watchpoint_add(target, address, size, wp_type, 0, 0xffffffffu)) != ERROR_OK)
 				{
 					if ((retval = gdb_error(connection, retval)) != ERROR_OK)
 						return retval;

-----------------------------------------------------------------------

Summary of changes:
 src/server/gdb_server.c |   10 ++++++++--
 1 files changed, 8 insertions(+), 2 deletions(-)


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commit 6c75f5249cf721aa8b8c2d774cdeeac6f9770e32
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Jan 11 15:54:52 2010 +0100

    debug: make logging of commands terser
    
    one line / command instead of one line per argument.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/helper/command.c b/src/helper/command.c
index cf66f8a..ebd9aa6 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -108,10 +108,15 @@ static int command_retval_set(Jim_Interp *interp, int retval)
 
 extern struct command_context *global_cmd_ctx;
 
+/* dump a single line to the log for the command.
+ * Do nothing in case we are not at debug level 3 */
 void script_debug(Jim_Interp *interp, const char *name,
 		unsigned argc, Jim_Obj *const *argv)
 {
-	LOG_DEBUG("command - %s", name);
+	if (debug_level < LOG_LVL_DEBUG)
+		return;
+
+	char * dbg = alloc_printf("command - %s", name);
 	for (unsigned i = 0; i < argc; i++)
 	{
 		int len;
@@ -121,8 +126,12 @@ void script_debug(Jim_Interp *interp, const char *name,
 		if (*w == '#')
 			break;
 
-		LOG_DEBUG("%s - argv[%d]=%s", name, i, w);
+		char * t = alloc_printf("%s %s", dbg, w);
+		free (dbg);
+		dbg = t;
 	}
+	LOG_DEBUG("%s", dbg);
+	free(dbg);
 }
 
 static void script_command_args_free(const char **words, unsigned nwords)

-----------------------------------------------------------------------

Summary of changes:
 src/helper/command.c |   13 +++++++++++--
 1 files changed, 11 insertions(+), 2 deletions(-)


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commit b4a4d5c7310c88ef263bfaaa060b5c249d98c446
Author: David Brownell <dbr...@us...>
Date:   Tue Jan 12 12:40:39 2010 -0800

    ARM: bugfix for "movt" disassembly
    
    Use the correct bitfield to specify the register whose
    top halfword gets replaced.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 912e37c..587131b 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -3247,7 +3247,7 @@ static int t2ev_data_immed(uint32_t opcode, uint32_t address,
 	case 0x0c:
 		/* move constant to top 16 bits of register */
 		immed |= (opcode >> 4) & 0xf000;
-		sprintf(cp, "MOVT\tr%d, #%d\t; %#4.4x", rn, immed, immed);
+		sprintf(cp, "MOVT\tr%d, #%d\t; %#4.4x", rd, immed, immed);
 		return ERROR_OK;
 	case 0x10:
 	case 0x12:

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_disassembler.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


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commit 1de107a5a269fa71c9a69eba182fecea68e38a06
Author: Vladimir Zapolskiy <vza...@gm...>
Date:   Mon Jan 11 17:49:37 2010 +0300

    Added Openmoko USB JTAG interface config file.
    
    Added interface config file for JTAG/RS232 debug board originally
    integrated to Neo 1973 and Neo FreeRunner phones.
    Adapter was tested with i.MX31, S3C2410 and AT91SAM9260 processors.
    
    Signed-off-by: Vladimir Zapolskiy <vza...@gm...>

diff --git a/tcl/interface/neodb.cfg b/tcl/interface/neodb.cfg
new file mode 100644
index 0000000..8e2f526
--- /dev/null
+++ b/tcl/interface/neodb.cfg
@@ -0,0 +1,10 @@
+#
+# Openmoko USB JTAG/RS232 adapter
+#
+# http://wiki.openmoko.org/wiki/Debug_Board_v3
+#
+
+interface ft2232
+ft2232_device_desc "Debug Board for Neo1973"
+ft2232_layout jtagkey
+ft2232_vid_pid 0x1457 0x5118

-----------------------------------------------------------------------

Summary of changes:
 tcl/interface/neodb.cfg |   10 ++++++++++
 1 files changed, 10 insertions(+), 0 deletions(-)
 create mode 100644 tcl/interface/neodb.cfg


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commit e5349bfb4954366579b521dc8181c01c5bd4679e
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Jan 11 14:59:14 2010 +0100

    target: return JIM_OK instead of ERROR_OK
    
    No change in actual binary as JIM_OK == ERROR_OK,
    but JIM_OK is correct here.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index 7329cee..f48993f 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -623,7 +623,7 @@ static int jim_newtap_cmd(Jim_GetOptInfo *goi)
 	if (pTap->ir_length != 0)
 	{
 		jtag_tap_init(pTap);
-		return ERROR_OK;
+		return JIM_OK;
 	}
 
 	Jim_SetResult_sprintf(goi->interp,

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/tcl.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


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commit fb71a0a0dddf68fa3f266aab5e35409773acc567
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Jan 11 12:54:49 2010 +0100

    reset: better error messages
    
    Use correct tcl syntax to throw exception.
    
    the syntax is "return -code error" not "return -error"
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/startup.tcl b/src/target/startup.tcl
index b597b84..d68417e 100644
--- a/src/target/startup.tcl
+++ b/src/target/startup.tcl
@@ -41,7 +41,7 @@ proc ocd_process_reset_inner { MODE } {
 		set halt 0;
 	}
 	if { $halt < 0 } {
-		return -error "Invalid mode: $MODE, must be one of: halt, init, or run";
+		return -code error "Invalid mode: $MODE, must be one of: halt, init, or run";
 	}
 
 	# Target event handlers *might* change which TAPs are enabled
@@ -119,7 +119,7 @@ proc ocd_process_reset_inner { MODE } {
 			set s [$t curstate]
 
 			if { 0 != [string compare $s "halted" ] } {
-				return -error [format "TARGET: %s - Not halted" $t]
+				return -code error [format "TARGET: %s - Not halted" $t]
 			}
 		}
 	}

commit 6d8604de37855da6e9acf79adbb488788bdc9917
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Jan 11 12:53:55 2010 +0100

    commands: make error messages a bit more terse
    
    we don't need to know the build path of command.c when
    reading normal user level error messages.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/helper/command.c b/src/helper/command.c
index 568596d..cf66f8a 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -349,7 +349,7 @@ static int register_command_handler(struct command_context *cmd_ctx,
 	if (NULL == override_name)
 		return JIM_ERR;
 
-	retval = Jim_Eval_Named(interp, override_name, __FILE__, __LINE__);
+	retval = Jim_Eval_Named(interp, override_name, __THIS__FILE__ , __LINE__);
 	free((void *)override_name);
 
 	return retval;

-----------------------------------------------------------------------

Summary of changes:
 src/helper/command.c   |    2 +-
 src/target/startup.tcl |    4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)


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- Log -----------------------------------------------------------------
commit c74ca40e09baebe8b86b1a77ad343f7b8ebde5d6
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Jan 11 10:21:56 2010 +0100

    zy1000: reset bugfix
    
    flush JTAG FIFO before reset. Fixes RCLK problems observed
    w/lpc2148, but really fixes a wider range of problems.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c
index e66a8b5..9070f2e 100644
--- a/src/jtag/zy1000/zy1000.c
+++ b/src/jtag/zy1000/zy1000.c
@@ -132,6 +132,13 @@ static int zy1000_power_dropout(int *dropout)
 void zy1000_reset(int trst, int srst)
 {
 	LOG_DEBUG("zy1000 trst=%d, srst=%d", trst, srst);
+
+	/* flush the JTAG FIFO. Not flushing the queue before messing with
+	 * reset has such interesting bugs as causing hard to reproduce
+	 * RCLK bugs as RCLK will stop responding when TRST is asserted
+	 */
+	waitIdle();
+
 	if (!srst)
 	{
 		ZY1000_POKE(ZY1000_JTAG_BASE + 0x14, 0x00000001);
@@ -156,7 +163,6 @@ void zy1000_reset(int trst, int srst)
 
 	if (trst||(srst && (jtag_get_reset_config() & RESET_SRST_PULLS_TRST)))
 	{
-		waitIdle();
 		/* we're now in the RESET state until trst is deasserted */
 		ZY1000_POKE(ZY1000_JTAG_BASE + 0x20, TAP_RESET);
 	} else

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/zy1000/zy1000.c |    8 +++++++-
 1 files changed, 7 insertions(+), 1 deletions(-)


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commit 8c730aaee22a505cf66666be3ff28734ac885418
Author: David Brownell <dbr...@us...>
Date:   Mon Jan 11 00:14:01 2010 -0800

    Doxygen file comments
    
    Add file comments to a few files.  Make the GDB server use
    more conventional (pointer-free) hex digit conversion.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/flash/nor/core.c b/src/flash/nor/core.c
index 7e783d4..9083ed1 100644
--- a/src/flash/nor/core.c
+++ b/src/flash/nor/core.c
@@ -29,6 +29,13 @@
 #include <target/image.h>
 
 
+/**
+ * @file
+ * Upper level of NOR flash framework.
+ * The lower level interfaces are to drivers.  These upper level ones
+ * primarily support access from Tcl scripts or from GDB.
+ */
+
 struct flash_bank *flash_banks;
 
 int flash_driver_erase(struct flash_bank *bank, int first, int last)
diff --git a/src/flash/nor/core.h b/src/flash/nor/core.h
index c1e26cd..36e163d 100644
--- a/src/flash/nor/core.h
+++ b/src/flash/nor/core.h
@@ -24,6 +24,11 @@
 
 #include <flash/common.h>
 
+/**
+ * @file
+ * Upper level NOR flash interfaces.
+ */
+
 struct image;
 
 #define FLASH_MAX_ERROR_STR	(128)
diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
index 65523fb..b7e80df 100644
--- a/src/flash/nor/tcl.c
+++ b/src/flash/nor/tcl.c
@@ -26,6 +26,11 @@
 #include <helper/time_support.h>
 #include <target/image.h>
 
+/**
+ * @file
+ * Implements Tcl commands used to access NOR flash facilities.
+ */
+
 COMMAND_HELPER(flash_command_get_bank, unsigned name_index,
 		struct flash_bank **bank)
 {
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 08daa68..f4a99ca 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -37,6 +37,15 @@
 #include <jtag/jtag.h>
 
 
+/**
+ * @file
+ * GDB server implementation.
+ *
+ * This implements the GDB Remote Serial Protocol, over TCP connections,
+ * giving GDB access to the JTAG or other hardware debugging facilities
+ * found in most modern embedded processors.
+ */
+
 /* private connection data for GDB */
 struct gdb_connection
 {
@@ -68,7 +77,7 @@ static enum breakpoint_type gdb_breakpoint_override_type;
 extern int gdb_error(struct connection *connection, int retval);
 static unsigned short gdb_port = 3333;
 static unsigned short gdb_port_next = 0;
-static const char *DIGITS = "0123456789abcdef";
+static const char DIGITS[16] = "0123456789abcdef";
 
 static void gdb_log_callback(void *priv, const char *file, unsigned line,
 		const char *function, const char *string);

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/core.c    |    7 +++++++
 src/flash/nor/core.h    |    5 +++++
 src/flash/nor/tcl.c     |    5 +++++
 src/server/gdb_server.c |   11 ++++++++++-
 4 files changed, 27 insertions(+), 1 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-90-g88907cc

[Øyvind H. <go...@us...>]

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- Log -----------------------------------------------------------------
commit 88907cc7f941ce85f0dc35ed3dbc4d2dbc87cef7
Author: Øyvind Harboe <oyv...@zy...>
Date:   Fri Jan 8 15:30:10 2010 +0100

    shutdown: more graceful shutdown
    
    Shutdown is not an error condition, do not return error
    from main.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/server/server.c b/src/server/server.c
index f762704..173beb8 100644
--- a/src/server/server.c
+++ b/src/server/server.c
@@ -563,9 +563,11 @@ int server_quit(void)
 /* tell the server we want to shut down */
 COMMAND_HANDLER(handle_shutdown_command)
 {
+	LOG_USER("shutdown command invoked");
+
 	shutdown_openocd = 1;
 
-	return ERROR_COMMAND_CLOSE_CONNECTION;
+	return ERROR_OK;
 }
 
 static const struct command_registration server_command_handlers[] = {

-----------------------------------------------------------------------

Summary of changes:
 src/server/server.c |    4 +++-
 1 files changed, 3 insertions(+), 1 deletions(-)


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- Log -----------------------------------------------------------------
commit d746dee833ef4774adcee6a33c97f8039a5bd744
Author: Spencer Oliver <nt...@us...>
Date:   Sun Jan 10 14:30:06 2010 +0000

    build: doxygen build
    
     - Fix for building doxygen out of tree
    
    Signed-off-by: Spencer Oliver <nt...@us...>

diff --git a/Doxyfile.in b/Doxyfile.in
index 519bb2f..f6e3ced 100644
--- a/Doxyfile.in
+++ b/Doxyfile.in
@@ -569,7 +569,7 @@ INPUT                  = @srcdir@/doc/manual \
                          @srcdir@/BUGS \
                          @srcdir@/PATCHES.txt \
                          @srcdir@/src \
-                         @srcdir@/config.h
+                         @builddir@/config.h
 
 # This tag can be used to specify the character encoding of the source files
 # that doxygen parses. Internally doxygen uses the UTF-8 encoding, which is
diff --git a/Makefile.am b/Makefile.am
index fab4704..7d42fd3 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -26,6 +26,7 @@ Doxyfile: $(srcdir)/Doxyfile.in
 	  echo "### @@@ -= DO NOT EDIT THIS FILE =- @@@ ###" && \
 	  echo "### @@@ Make changes to Doxyfile.in @@@ ###" && \
 	  sed -e 's,@srcdir\@,$(srcdir),' \
+	    -e 's,@builddir\@,$(builddir),' \
 	    -e 's,@doxygen_as_html\@,$(doxygen_as_html),' \
 	    -e 's,@doxygen_as_pdf\@,$(doxygen_as_pdf),' $< \
 	) > $@

-----------------------------------------------------------------------

Summary of changes:
 Doxyfile.in |    2 +-
 Makefile.am |    1 +
 2 files changed, 2 insertions(+), 1 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-88-gc826793

[David B. <dbr...@us...>]

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- Log -----------------------------------------------------------------
commit c8267930c7cff5685b33cd0174deb75a46dbb09b
Author: David Brownell <dbr...@us...>
Date:   Sun Jan 10 10:06:58 2010 -0800

    FreeBSD build fixes
    
    Based on notes from Tomek Cedro <tom...@gm...> and
    Steve Franks <bah...@gm...>.
    
    In the User's Guide, sort the list of operating systems reported
    through Tcl with $ocd_HOSTOS ... and include FreeBSD.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 6466d6d..0eb40b1 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6913,11 +6913,12 @@ variables. JimTCL, as implemented in OpenOCD creates $ocd_HOSTOS which
 holds one of the following values:
 
 @itemize @bullet
-@item @b{winxx}    Built using Microsoft Visual Studio
-@item @b{linux}    Linux is the underlying operating sytem
-@item @b{darwin}   Darwin (mac-os) is the underlying operating sytem.
 @item @b{cygwin}   Running under Cygwin
+@item @b{darwin}   Darwin (Mac-OS) is the underlying operating sytem.
+@item @b{freebsd}  Running under FreeBSD
+@item @b{linux}    Linux is the underlying operating sytem
 @item @b{mingw32}  Running under MingW32
+@item @b{winxx}    Built using Microsoft Visual Studio
 @item @b{other}    Unknown, none of the above.
 @end itemize
 
diff --git a/src/helper/command.c b/src/helper/command.c
index 288ed72..568596d 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -1358,6 +1358,7 @@ struct command_context* command_init(const char *startup_tcl, Jim_Interp *interp
 #endif
 	context->interp = interp;
 
+	/* Stick to lowercase for HostOS strings. */
 #if defined(_MSC_VER)
 	/* WinXX - is generic, the forward
 	 * looking problem is this:
@@ -1377,6 +1378,8 @@ struct command_context* command_init(const char *startup_tcl, Jim_Interp *interp
 	HostOs = "mingw32";
 #elif defined(__ECOS)
 	HostOs = "ecos";
+#elif defined(__FreeBSD__)
+	HostOs = "freebsd";
 #else
 #warning "Unrecognized host OS..."
 	HostOs = "other";

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi     |    7 ++++---
 src/helper/command.c |    3 +++
 2 files changed, 7 insertions(+), 3 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-87-g5e221fa

[David B. <dbr...@us...>]

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- Log -----------------------------------------------------------------
commit 5e221fa3a72dcdde92cf749495131748d32f7d8a
Author: David Brownell <dbr...@us...>
Date:   Sat Jan 9 22:24:43 2010 -0800

    Presto: doxygen fix
    
    Newline needed.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/jtag/drivers/presto.c b/src/jtag/drivers/presto.c
index ababf09..72126a1 100644
--- a/src/jtag/drivers/presto.c
+++ b/src/jtag/drivers/presto.c
@@ -19,7 +19,8 @@
  ***************************************************************************/
 
 /**
- * @file Holds driver for PRESTO programmer from ASIX.
+ * @file
+ * Holds driver for PRESTO programmer from ASIX.
  * http://tools.asix.net/prg_presto.htm
  */
 #ifdef HAVE_CONFIG_H

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/presto.c |    3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)


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- Log -----------------------------------------------------------------
commit ab4307e693dad8181f1570b5cdd7f132661a608b
Author: David Brownell <dbr...@us...>
Date:   Sat Jan 9 22:15:57 2010 -0800

    jtag/tcl help/usage fixups
    
    The usual: expand several helptexts to be more correct and to use
    full sentences; make the usage messages use the same EBNF as the
    User's Guide; use function names for their addresses.
    
    Also add a comment about that odd jtag_command_handlers_to_move[] thing.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index 00b1038..7329cee 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -269,26 +269,39 @@ static int Jim_Command_flush_count(Jim_Interp *interp, int argc, Jim_Obj *const
 	return JIM_OK;
 }
 
+/* REVISIT Just what about these should "move" ... ?
+ * These registrations, into the main JTAG table?
+ *
+ * There's a minor compatibility issue, these all show up twice;
+ * that's not desirable:
+ *  - jtag drscan ... NOT DOCUMENTED!
+ *  - drscan ...
+ *
+ * The "irscan" command (for example) doesn't show twice.
+ */
 static const struct command_registration jtag_command_handlers_to_move[] = {
 	{
 		.name = "drscan",
 		.mode = COMMAND_EXEC,
-		.jim_handler = &Jim_Command_drscan,
-		.help = "execute DR scan <device> "
-			"<num_bits> <value> <num_bits1> <value2> ...",
+		.jim_handler = Jim_Command_drscan,
+		.help = "Execute Data Register (DR) scan for one TAP.  "
+			"Other TAPs must be in BYPASS mode.",
+		.usage = "tap_name [num_bits value]* ['-endstate' state_name]",
 	},
 	{
 		.name = "flush_count",
 		.mode = COMMAND_EXEC,
-		.jim_handler = &Jim_Command_flush_count,
-		.help = "returns number of times the JTAG queue has been flushed",
+		.jim_handler = Jim_Command_flush_count,
+		.help = "Returns the number of times the JTAG queue "
+			"has been flushed.",
 	},
 	{
 		.name = "pathmove",
 		.mode = COMMAND_EXEC,
-		.jim_handler = &Jim_Command_pathmove,
-		.usage = "<state1>,<state2>,<state3>... ",
-		.help = "move JTAG to state1 then to state2, state3, etc.",
+		.jim_handler = Jim_Command_pathmove,
+		.usage = "start_state state1 [state2 [state3 ...]]",
+		.help = "Move JTAG state machine from current state "
+			"(start_state) to state1, then state2, state3, etc.",
 	},
 	COMMAND_REGISTRATION_DONE
 };
@@ -658,7 +671,8 @@ static void jtag_tap_handle_event(struct jtag_tap *tap, enum jtag_event e)
 	}
 }
 
-static int jim_jtag_interface(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
+static int
+jim_jtag_interface(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 {
 	Jim_GetOptInfo goi;
 	Jim_GetOpt_Setup(&goi, interp, argc-1, argv + 1);
@@ -845,73 +859,88 @@ static const struct command_registration jtag_subcommand_handlers[] = {
 	{
 		.name = "init",
 		.mode = COMMAND_ANY,
-		.handler = &handle_jtag_init_command,
+		.handler = handle_jtag_init_command,
 		.help = "initialize jtag scan chain",
 	},
 	{
 		.name = "interface",
 		.mode = COMMAND_ANY,
-		.jim_handler = &jim_jtag_interface,
-		.help = "Returns the selected interface",
+		.jim_handler = jim_jtag_interface,
+		.help = "Returns the name of the currently selected interface.",
 	},
 	{
 		.name = "arp_init",
 		.mode = COMMAND_ANY,
-		.jim_handler = &jim_jtag_arp_init,
+		.jim_handler = jim_jtag_arp_init,
+		.help = "Validates JTAG scan chain against the list of "
+			"declared TAPs using just the four standard JTAG "
+			"signals.",
 	},
 	{
 		.name = "arp_init-reset",
 		.mode = COMMAND_ANY,
-		.jim_handler = &jim_jtag_arp_init_reset,
+		.jim_handler = jim_jtag_arp_init_reset,
+		.help = "Uses TRST and SRST to try resetting everything on "
+			"the JTAG scan chain, then performs 'jtag arp_init'."
 	},
 	{
 		.name = "newtap",
 		.mode = COMMAND_CONFIG,
-		.jim_handler = &jim_jtag_newtap,
-		.help = "Create a new TAP instance",
-		.usage = "<name> <type> -irlen <count> [-ircapture <count>] "
-			"[-irmask <count>] [-enable|-disable]",
+		.jim_handler = jim_jtag_newtap,
+		.help = "Create a new TAP instance named basename.tap_type, "
+			"and appends it to the scan chain.",
+		.usage = "basename tap_type '-irlen' count "
+			"['-enable'|'-disable'] "
+			"['-expected_id' number] "
+			"['-ignore-version'] "
+			"['-ircapture' number] "
+			"['-mask' number] ",
 	},
 	{
 		.name = "tapisenabled",
 		.mode = COMMAND_EXEC,
-		.jim_handler = &jim_jtag_tap_enabler,
-		.help = "Returns a integer indicating TAP state (0/1)",
-		.usage = "<name>",
+		.jim_handler = jim_jtag_tap_enabler,
+		.help = "Returns a Tcl boolean (0/1) indicating whether "
+			"the TAP is enabled (1) or not (0).",
+		.usage = "tap_name",
 	},
 	{
 		.name = "tapenable",
 		.mode = COMMAND_EXEC,
-		.jim_handler = &jim_jtag_tap_enabler,
-		.help = "Enable the specified TAP",
-		.usage = "<name>",
+		.jim_handler = jim_jtag_tap_enabler,
+		.help = "Try to enable the specified TAP using the "
+			"'tap-enable' TAP event.",
+		.usage = "tap_name",
 	},
 	{
 		.name = "tapdisable",
 		.mode = COMMAND_EXEC,
-		.jim_handler = &jim_jtag_tap_enabler,
-		.help = "Enable the specified TAP",
-		.usage = "<name>",
+		.jim_handler = jim_jtag_tap_enabler,
+		.help = "Try to disable the specified TAP using the "
+			"'tap-disable' TAP event.",
+		.usage = "tap_name",
 	},
 	{
 		.name = "configure",
 		.mode = COMMAND_EXEC,
-		.jim_handler = &jim_jtag_configure,
-		.help = "Enable the specified TAP",
-		.usage = "<name> [<key> <value> ...]",
+		.jim_handler = jim_jtag_configure,
+		.help = "Provide a Tcl handler for the specified "
+			"TAP event.",
+		.usage = "tap_name '-event' event_name handler",
 	},
 	{
 		.name = "cget",
 		.mode = COMMAND_EXEC,
-		.jim_handler = &jim_jtag_configure,
-		.help = "Enable the specified TAP",
-		.usage = "<name> [<key> <value> ...]",
+		.jim_handler = jim_jtag_configure,
+		.help = "Return any Tcl handler for the specified "
+			"TAP event.",
+		.usage = "tap_name '-event' event_name",
 	},
 	{
 		.name = "names",
 		.mode = COMMAND_ANY,
-		.jim_handler = &jim_jtag_names,
-		.help = "Returns list of all JTAG tap names",
+		.jim_handler = jim_jtag_names,
+		.help = "Returns list of all JTAG tap names.",
 	},
 	{
 		.chain = jtag_command_handlers_to_move,
@@ -1574,34 +1603,38 @@ COMMAND_HANDLER(handle_tms_sequence_command)
 static const struct command_registration jtag_command_handlers[] = {
 	{
 		.name = "interface",
-		.handler = &handle_interface_command,
+		.handler = handle_interface_command,
 		.mode = COMMAND_CONFIG,
-		.help = "select a JTAG interface",
-		.usage = "<driver_name>",
+		.help = "Select a JTAG interface",
+		.usage = "driver_name",
 	},
 	{
 		.name = "interface_list",
-		.handler = &handle_interface_list_command,
+		.handler = handle_interface_list_command,
 		.mode = COMMAND_ANY,
-		.help = "list all built-in interfaces",
+		.help = "List all built-in interfaces",
 	},
 	{
 		.name = "jtag_khz",
-		.handler = &handle_jtag_khz_command,
+		.handler = handle_jtag_khz_command,
 		.mode = COMMAND_ANY,
-		.help = "set maximum jtag speed (if supported)",
-		.usage = "<khz:0=rtck>",
+		.help = "With an argument, change to the specified maximum "
+			"jtag speed.  Pass 0 to require adaptive clocking. "
+			"With or without argument, display current setting.",
+		.usage = "[khz]",
 	},
 	{
 		.name = "jtag_rclk",
-		.handler = &handle_jtag_rclk_command,
+		.handler = handle_jtag_rclk_command,
 		.mode = COMMAND_ANY,
-		.help = "set JTAG speed to RCLK or use fallback speed",
-		.usage = "<fallback_speed_khz>",
+		.help = "With an argument, change to to use adaptive clocking "
+			"if possible; else to use the fallback speed.  "
+			"With or without argument, display current setting.",
+		.usage = "[fallback_speed_khz]",
 	},
 	{
 		.name = "reset_config",
-		.handler = &handle_reset_config_command,
+		.handler = handle_reset_config_command,
 		.mode = COMMAND_ANY,
 		.help = "configure JTAG reset behavior",
 		.usage = "[none|trst_only|srst_only|trst_and_srst] "
@@ -1612,79 +1645,87 @@ static const struct command_registration jtag_command_handlers[] = {
 	},
 	{
 		.name = "jtag_nsrst_delay",
-		.handler = &handle_jtag_nsrst_delay_command,
+		.handler = handle_jtag_nsrst_delay_command,
 		.mode = COMMAND_ANY,
 		.help = "delay after deasserting srst in ms",
-		.usage = "<ms>",
+		.usage = "[milliseconds]",
 	},
 	{
 		.name = "jtag_ntrst_delay",
-		.handler = &handle_jtag_ntrst_delay_command,
+		.handler = handle_jtag_ntrst_delay_command,
 		.mode = COMMAND_ANY,
 		.help = "delay after deasserting trst in ms",
-		.usage = "<ms>"
+		.usage = "[milliseconds]",
 	},
 	{
 		.name = "jtag_nsrst_assert_width",
-		.handler = &handle_jtag_nsrst_assert_width_command,
+		.handler = handle_jtag_nsrst_assert_width_command,
 		.mode = COMMAND_ANY,
 		.help = "delay after asserting srst in ms",
-		.usage = "<ms>"
+		.usage = "[milliseconds]",
 	},
 	{
 		.name = "jtag_ntrst_assert_width",
-		.handler = &handle_jtag_ntrst_assert_width_command,
+		.handler = handle_jtag_ntrst_assert_width_command,
 		.mode = COMMAND_ANY,
 		.help = "delay after asserting trst in ms",
-		.usage = "<ms>"
+		.usage = "[milliseconds]",
 	},
 	{
 		.name = "scan_chain",
-		.handler = &handle_scan_chain_command,
+		.handler = handle_scan_chain_command,
 		.mode = COMMAND_EXEC,
 		.help = "print current scan chain configuration",
 	},
 	{
 		.name = "jtag_reset",
-		.handler = &handle_jtag_reset_command,
+		.handler = handle_jtag_reset_command,
 		.mode = COMMAND_EXEC,
-		.help = "toggle reset lines",
-		.usage = "<trst> <srst>",
+		.help = "Set reset line values.  Value '1' is active, "
+			"value '0' is inactive.",
+		.usage = "trst_active srst_active",
 	},
 	{
 		.name = "runtest",
-		.handler = &handle_runtest_command,
+		.handler = handle_runtest_command,
 		.mode = COMMAND_EXEC,
-		.help = "move to Run-Test/Idle, and execute <num_cycles>",
-		.usage = "<num_cycles>"
+		.help = "Move to Run-Test/Idle, and issue TCK for num_cycles.",
+		.usage = "num_cycles"
 	},
 	{
 		.name = "irscan",
-		.handler = &handle_irscan_command,
+		.handler = handle_irscan_command,
 		.mode = COMMAND_EXEC,
-		.help = "execute IR scan",
-		.usage = "<device> <instr> [dev2] [instr2] ...",
+		.help = "Execute Instruction Register (DR) scan.  The "
+			"specified opcodes are put into each TAP's IR, "
+			"and other TAPs are put in BYPASS.",
+		.usage = "[tap_name instruction]* ['-endstate' state_name]",
 	},
 	{
 		.name = "verify_ircapture",
-		.handler = &handle_verify_ircapture_command,
+		.handler = handle_verify_ircapture_command,
 		.mode = COMMAND_ANY,
-		.help = "verify value captured during Capture-IR",
-		.usage = "<enable | disable>",
+		.help = "Display or assign flag controlling whether to "
+			"verify values captured during Capture-IR.",
+		.usage = "['enable'|'disable']",
 	},
 	{
 		.name = "verify_jtag",
-		.handler = &handle_verify_jtag_command,
+		.handler = handle_verify_jtag_command,
 		.mode = COMMAND_ANY,
-		.help = "verify value capture",
-		.usage = "<enable | disable>",
+		.help = "Display or assign flag controlling whether to "
+			"verify values captured during IR and DR scans.",
+		.usage = "['enable'|'disable']",
 	},
 	{
 		.name = "tms_sequence",
-		.handler = &handle_tms_sequence_command,
+		.handler = handle_tms_sequence_command,
 		.mode = COMMAND_ANY,
-		.help = "choose short(default) or long tms_sequence",
-		.usage = "<short | long>",
+		.help = "Display or change what style TMS sequences to use "
+			"for JTAG state transitions:  short (default) or "
+			"long.  Only for working around JTAG bugs.",
+			/* Specifically for working around DRIVER bugs... */
+		.usage = "['short'|'long']",
 	},
 	{
 		.name = "jtag",

commit 5cb1dcfad34aab7de64ef85f6227f28f3711dd85
Author: David Brownell <dbr...@us...>
Date:   Sat Jan 9 22:14:08 2010 -0800

    ZY1000 help/usage fixups
    
    The usual:  same EBNF as in the User's Guide, full sentence helptext,
    function names *are* their addresses.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c
index 7c5f440..e66a8b5 100644
--- a/src/jtag/zy1000/zy1000.c
+++ b/src/jtag/zy1000/zy1000.c
@@ -832,29 +832,32 @@ void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, uint8_t *buffer,
 static const struct command_registration zy1000_commands[] = {
 	{
 		.name = "power",
-		.handler = &handle_power_command,
+		.handler = handle_power_command,
 		.mode = COMMAND_ANY,
-		.help = "turn power switch to target on/off. No arguments - print status.",
-		.usage = "power <on/off>",
+		.help = "Turn power switch to target on/off. "
+			"With no arguments, prints status.",
+		.usage = "('on'|'off)",
 	},
 	{
 		.name = "zy1000_version",
 		.mode = COMMAND_ANY,
-		.jim_handler = &jim_zy1000_version,
-		.help = "print version info for zy1000",
+		.jim_handler = jim_zy1000_version,
+		.help = "Print version info for zy1000.",
+		.usage = "['openocd'|'zy1000'|'date'|'time'|'pcb'|'fpga']",
 	},
 	{
 		.name = "powerstatus",
 		.mode = COMMAND_ANY,
-		.jim_handler = & zylinjtag_Jim_Command_powerstatus,
-		.help = "print power status of target",
+		.jim_handler = zylinjtag_Jim_Command_powerstatus,
+		.help = "Returns power status of target",
 	},
 #ifdef CYGPKG_HAL_NIOS2
 	{
 		.name = "updatezy1000firmware",
 		.mode = COMMAND_ANY,
-		.jim_handler = &jim_zy1000_writefirmware,
+		.jim_handler = jim_zy1000_writefirmware,
 		.help = "writes firmware to flash",
+		/* .usage = "some_string", */
 	},
 #endif
 	COMMAND_REGISTRATION_DONE

commit 0811f6b192674788a00e02fbbfe29e0a2a138ea2
Author: David Brownell <dbr...@us...>
Date:   Sat Jan 9 22:09:08 2010 -0800

    jtag: presto, parport help/usage updates
    
    Presto: add doxygen file comment.
    
    Parport: note a couple gaps in layout config.
    
    Both: use the uniform EBNF for usage, bugfix helptexts, use function
    name as its address not "&name".
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/jtag/drivers/parport.c b/src/jtag/drivers/parport.c
index b280d04..a38ccfd 100644
--- a/src/jtag/drivers/parport.c
+++ b/src/jtag/drivers/parport.c
@@ -437,10 +437,13 @@ COMMAND_HANDLER(parport_handle_parport_cable_command)
 	/* only if the cable name wasn't overwritten by cmdline */
 	if (parport_cable == 0)
 	{
+		/* REVISIT first verify that it's listed in cables[] ... */
 		parport_cable = malloc(strlen(CMD_ARGV[0]) + sizeof(char));
 		strcpy(parport_cable, CMD_ARGV[0]);
 	}
 
+	/* REVISIT it's probably worth returning the current value ... */
+
 	return ERROR_OK;
 }
 
@@ -484,34 +487,37 @@ COMMAND_HANDLER(parport_handle_parport_toggling_time_command)
 static const struct command_registration parport_command_handlers[] = {
 	{
 		.name = "parport_port",
-		.handler = &parport_handle_parport_port_command,
+		.handler = parport_handle_parport_port_command,
 		.mode = COMMAND_CONFIG,
-		.help = "either the address of the I/O port "
-			"or the number of the '/dev/parport' device",
-		.usage = "[<port|devname>]",
+		.help = "Display the address of the I/O port (e.g. 0x378) "
+			"or the number of the '/dev/parport' device used.  "
+			"If a parameter is provided, first change that port.",
+		.usage = "[port_number]",
 	},
 	{
 		.name = "parport_cable",
-		.handler = &parport_handle_parport_cable_command,
+		.handler = parport_handle_parport_cable_command,
 		.mode = COMMAND_CONFIG,
-		.help = "the layout of the parallel port cable "
-			"used to connect to the target",
-		.usage = "[<layout>]",
+		.help = "Set the layout of the parallel port cable "
+			"used to connect to the target.",
+		/* REVISIT there's no way to list layouts we know ... */
+		.usage = "[layout]",
 	},
 	{
 		.name = "parport_write_on_exit",
-		.handler = &parport_handle_write_on_exit_command,
+		.handler = parport_handle_write_on_exit_command,
 		.mode = COMMAND_CONFIG,
-		.help = "configure the parallel driver to write "
-			"a known value to the parallel interface",
-		.usage = "[<on|off>]",
+		.help = "Configure the parallel driver to write "
+			"a known value to the parallel interface on exit.",
+		.usage = "('on'|'off')",
 	},
 	{
 		.name = "parport_toggling_time",
-		.handler = &parport_handle_parport_toggling_time_command,
+		.handler = parport_handle_parport_toggling_time_command,
 		.mode = COMMAND_CONFIG,
-		.help = "time <ns> it takes for the hardware to toggle TCK",
-		.usage = "[<ns>]",
+		.help = "Displays or assigns how many nanoseconds it "
+			"takes for the hardware to toggle TCK.",
+		.usage = "[nanoseconds]",
 	},
 	COMMAND_REGISTRATION_DONE
 };
diff --git a/src/jtag/drivers/presto.c b/src/jtag/drivers/presto.c
index 0baf561..ababf09 100644
--- a/src/jtag/drivers/presto.c
+++ b/src/jtag/drivers/presto.c
@@ -17,6 +17,11 @@
  *   Free Software Foundation, Inc.,                                       *
  *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
  ***************************************************************************/
+
+/**
+ * @file Holds driver for PRESTO programmer from ASIX.
+ * http://tools.asix.net/prg_presto.htm
+ */
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
@@ -742,10 +747,10 @@ COMMAND_HANDLER(presto_handle_serial_command)
 static const struct command_registration presto_command_handlers[] = {
 	{
 		.name = "presto_serial",
-		.handler = &presto_handle_serial_command,
+		.handler = presto_handle_serial_command,
 		.mode = COMMAND_CONFIG,
-		.help = "configure serial port",
-		.usage = "<devname>",
+		.help = "Configure USB serial number of Presto device.",
+		.usage = "serial_string",
 	},
 	COMMAND_REGISTRATION_DONE
 };

commit ad5fd390634799ecabddc32d0ce415ef72036b4a
Author: David Brownell <dbr...@us...>
Date:   Sat Jan 9 22:05:55 2010 -0800

    jtag/gw16012 usage/help updates
    
    Use standard BNF.  Improve/correct helptext for its "parport_port"
    command.  Function address is just its name.

diff --git a/src/jtag/drivers/gw16012.c b/src/jtag/drivers/gw16012.c
index 38e5dd7..0e9f3fe 100644
--- a/src/jtag/drivers/gw16012.c
+++ b/src/jtag/drivers/gw16012.c
@@ -565,10 +565,12 @@ COMMAND_HANDLER(gw16012_handle_parport_port_command)
 static const struct command_registration gw16012_command_handlers[] = {
 	{
 		.name = "parport_port",
-		.handler = &gw16012_handle_parport_port_command,
+		.handler = gw16012_handle_parport_port_command,
 		.mode = COMMAND_CONFIG,
-		.help = "configure the parallel port to use",
-		.usage = "<port_num>",
+		.help = "Display the address of the I/O port (e.g. 0x378) "
+			"or the number of the '/dev/parport' device used.  "
+			"If a parameter is provided, first change that port.",
+		.usage = "[port_number]",
 	},
 	COMMAND_REGISTRATION_DONE
 };

commit ff647e6bb4180a7c376b61caeb14951ba84d5717
Author: David Brownell <dbr...@us...>
Date:   Sat Jan 9 21:56:11 2010 -0800

    parport (mostly) doc fixes
    
    The "parport_port" commands generally don't *require* a port_number;
    they're of the "apply any parameter, then print result" variety.  Update
    the User's Guide accordingly.
    
    Some of those commands are intended to be write-once: parport_port,
    and parport_cable.  Say so.
    
    Use proper EBNF for the parport_write_on_exit parameter.
    
    Parport address 0xc8b8 is evidently mutant.  Say so in the "parport.cfg"
    file, to avoid breaking anyone with that mutant config.  But update the
    User's Guide to include a sane example for the LP2 port.
    
    Finally document the "presto_serial" command.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index f8956a3..6466d6d 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2073,9 +2073,11 @@ $_TARGETNAME configure -event reset-assert \
 Gateworks GW16012 JTAG programmer.
 This has one driver-specific command:
 
-@deffn {Config Command} {parport_port} number
-Specifies either the address of the I/O port (default: 0x378 for LPT1) or
-the number of the @file{/dev/parport} device.
+@deffn {Config Command} {parport_port} [port_number]
+Display either the address of the I/O port
+(default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
+If a parameter is provided, first switch to use that port.
+This is a write-once setting.
 @end deffn
 @end deffn
 
@@ -2094,7 +2096,8 @@ These interfaces have several commands, used to configure the driver
 before initializing the JTAG scan chain:
 
 @deffn {Config Command} {parport_cable} name
-The layout of the parallel port cable used to connect to the target.
+Set the layout of the parallel port cable used to connect to the target.
+This is a write-once setting.
 Currently valid cable @var{name} values include:
 
 @itemize @minus
@@ -2122,9 +2125,11 @@ several clones, such as the Olimex ARM-JTAG
 @end itemize
 @end deffn
 
-@deffn {Config Command} {parport_port} number
-Either the address of the I/O port (default: 0x378 for LPT1) or the number of
-the @file{/dev/parport} device
+@deffn {Config Command} {parport_port} [port_number]
+Display either the address of the I/O port
+(default: 0x378 for LPT1) or the number of the @file{/dev/parport} device.
+If a parameter is provided, first switch to use that port.
+This is a write-once setting.
 
 When using PPDEV to access the parallel port, use the number of the parallel port:
 @option{parport_port 0} (the default). If @option{parport_port 0x378} is specified
@@ -2167,25 +2172,26 @@ match for the jtag_khz rate you specified; be conservative.
 @end quotation
 @end deffn
 
-@deffn {Config Command} {parport_write_on_exit} (on|off)
+@deffn {Config Command} {parport_write_on_exit} (@option{on}|@option{off})
 This will configure the parallel driver to write a known
-cable-specific value to the parallel interface on exiting OpenOCD
+cable-specific value to the parallel interface on exiting OpenOCD.
 @end deffn
 
 For example, the interface configuration file for a
-classic ``Wiggler'' cable might look something like this:
+classic ``Wiggler'' cable on LPT2 might look something like this:
 
 @example
 interface parport
-parport_port 0xc8b8
+parport_port 0x278
 parport_cable wiggler
 @end example
 @end deffn
 
 @deffn {Interface Driver} {presto}
 ASIX PRESTO USB JTAG programmer.
-@c command:	presto_serial str
-@c     sets serial number
+@deffn {Config Command} {presto_serial} serial_string
+Configures the USB serial number of the Presto device to use.
+@end deffn
 @end deffn
 
 @deffn {Interface Driver} {rlink}
diff --git a/tcl/interface/parport.cfg b/tcl/interface/parport.cfg
index 2a2668d..22be8f3 100644
--- a/tcl/interface/parport.cfg
+++ b/tcl/interface/parport.cfg
@@ -1,6 +1,8 @@
 #
 # Parallel port wiggler (many clones available) on port 0xc8b8
 #
+# REVISIT this address seems very wrong.
+# Surely 0x378/LPT1 or 0x278/LPT2 ...
 
 interface parport
 parport_port 0xc8b8

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi           |   32 +++++---
 src/jtag/drivers/gw16012.c |    8 +-
 src/jtag/drivers/parport.c |   36 +++++----
 src/jtag/drivers/presto.c  |   11 ++-
 src/jtag/tcl.c             |  189 +++++++++++++++++++++++++++-----------------
 src/jtag/zy1000/zy1000.c   |   19 +++--
 tcl/interface/parport.cfg  |    2 +
 7 files changed, 181 insertions(+), 116 deletions(-)


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