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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-180-g3ea9e62

From: David B. <dbr...@us...> - 2010-02-04 20:11:39

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- Log -----------------------------------------------------------------
commit 3ea9e62189205cfa84a04ec6955aaf1f5184a937
Author: David Brownell <dbr...@us...>
Date:   Thu Feb 4 11:10:15 2010 -0800

    Documentation: mention bug database
    
    Have the User's Guide and BUG handling notes both reference
    the fact that we now have a bug database at SourceForge.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/BUGS b/BUGS
index 36a7da3..5e640e7 100644
--- a/BUGS
+++ b/BUGS
@@ -6,6 +6,12 @@ posting a message with your report:
 
 	ope...@li...
 
+Also, please check the Trac bug database to see if a ticket for
+the bug has already been opened.  You might be asked to open
+such a ticket, or to update an existing ticket with more data.
+
+	https://sourceforge.net/apps/trac/openocd/
+
 To minimize work for OpenOCD developers, you should try to include
 all of the information listed below.  If you feel that some of the
 items below are unnecessary for a clear bug report, you may leave
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 957c79c..d4e60a8 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -60,7 +60,7 @@ Free Documentation License''.
 
 @menu
 * About::                            About OpenOCD
-* Developers::                       OpenOCD Developers
+* Developers::                       OpenOCD Developer Resources
 * JTAG Hardware Dongles::            JTAG Hardware Dongles
 * About JIM-Tcl::                    About JIM-Tcl
 * Running::                          Running OpenOCD
@@ -226,6 +226,13 @@ Discuss and submit patches to this list.
 The @file{PATCHES.txt} file contains basic information about how
 to prepare patches.
 
+@section OpenOCD Bug Database
+
+During the 0.4.x release cycle the OpenOCD project team began
+using Trac for its bug database:
+
+@uref{https://sourceforge.net/apps/trac/openocd}
+
 
 @node JTAG Hardware Dongles
 @chapter JTAG Hardware Dongles

commit e380930478a45cc78de6b807dc6f17d0a61298b4
Author: David Brownell <dbr...@us...>
Date:   Thu Feb 4 10:50:24 2010 -0800

    JLink: reference protocol documentation
    
    Segger publishes some documentation on this protocol;
    reference it, so future maintainers can know it exists.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/jtag/drivers/jlink.c b/src/jtag/drivers/jlink.c
index 6596849..f22ad7c 100644
--- a/src/jtag/drivers/jlink.c
+++ b/src/jtag/drivers/jlink.c
@@ -29,6 +29,10 @@
 #include <jtag/commands.h>
 #include "usb_common.h"
 
+/* See Segger's public documentation:
+ *	Reference manual for J-Link USB Protocol
+ *	Document RM08001-R6 Date: June 16, 2009
+ */
 
 #define VID 0x1366
 #define PID 0x0101

-----------------------------------------------------------------------

Summary of changes:
 BUGS                     |    6 ++++++
 doc/openocd.texi         |    9 ++++++++-
 src/jtag/drivers/jlink.c |    4 ++++
 3 files changed, 18 insertions(+), 1 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-178-g709f08f

From: Spencer O. <nt...@us...> - 2010-02-04 12:14:47

This is an automated email from the git hooks/post-receive script. It was
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- Log -----------------------------------------------------------------
commit 709f08f17ad5128b86966365510dbe8f67736304
Author: Spencer Oliver <nt...@us...>
Date:   Thu Feb 4 10:33:33 2010 +0000

    CMD: duplicate cmd error msg
    
    When registering cmds we report duplicate attempts to register a cmd
    as a LOG_ERROR.
    Some situations need this, such as when registering dual flash banks.
    http://www.mail-archive.com/ope...@li.../msg11152.html
    
    Signed-off-by: Spencer Oliver <nt...@us...>

diff --git a/src/helper/command.c b/src/helper/command.c
index ebd9aa6..3625508 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -375,7 +375,10 @@ struct command* register_command(struct command_context *context,
 	struct command *c = command_find(*head, name);
 	if (NULL != c)
 	{
-		LOG_ERROR("command '%s' is already registered in '%s' context",
+		/* TODO: originally we treated attempting to register a cmd twice as an error
+		 * Sometimes we need this behaviour, such as with flash banks.
+		 * http://www.mail-archive.com/ope...@li.../msg11152.html */
+		LOG_DEBUG("command '%s' is already registered in '%s' context",
 				name, parent ? parent->name : "<global>");
 		return c;
 	}

-----------------------------------------------------------------------

Summary of changes:
 src/helper/command.c |    5 ++++-
 1 files changed, 4 insertions(+), 1 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-177-g8b049fd

From: Øyvind H. <go...@us...> - 2010-02-04 10:24:52

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commit 8b049fdba52459d54f63d39ae7b30abeef911e2b
Author: Ethan Eade <et...@ev...>
Date:   Thu Feb 4 10:25:44 2010 +0100

    scripts: Phytec/LPC2350 config scripts
    
    Signed-off-by: Ãyvind Harboe <oyv...@zy...>

diff --git a/tcl/board/phytec_lpc3250.cfg b/tcl/board/phytec_lpc3250.cfg
new file mode 100644
index 0000000..78cb90d
--- /dev/null
+++ b/tcl/board/phytec_lpc3250.cfg
@@ -0,0 +1,88 @@
+source [find target/lpc3250.cfg]
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 1
+jtag_khz 200
+reset_config trst_and_srst separate
+
+arm7_9 dcc_downloads enable
+
+$_TARGETNAME configure -event gdb-attach { reset init }
+
+$_TARGETNAME configure -event reset-start {
+             arm7_9 fast_memory_access disable
+             jtag_khz 200
+}
+
+$_TARGETNAME configure -event reset-end {
+             jtag_khz 6000
+             arm7_9 fast_memory_access enable
+}
+
+$_TARGETNAME configure -event reset-init { phytec_lpc3250_init }
+
+# Bare-bones initialization of core clocks and SDRAM
+proc phytec_lpc3250_init { } {
+        # Set clock dividers 
+        #   ARMCLK = 266.5 MHz
+        #   HCLK   = 133.25 MHz
+        #   PERIPHCLK = 13.325 MHz
+        mww 0x400040BC 0
+        mww 0x40004050 0x140        
+        mww 0x40004040 0x4D
+        mww 0x40004058 0x16250
+
+        # Init PLLs
+        mww 0x40004044 0x006
+        sleep 1 busy
+        mww 0x40004044 0x106
+        sleep 1 busy
+        mww 0x40004044 0x006        
+        sleep 1 busy
+        mww 0x40004048 0x2
+
+        # Init SDRAM with 133 MHz timings
+        mww 0x40028134 0x00FFFFFF
+        mww 0x4002802C 0x00000008
+
+        mww 0x31080000 1
+        mww 0x31080008 0
+        mww 0x40004068 0x1C000
+        mww 0x31080028 0x11
+        
+        mww 0x31080400 0
+        mww 0x31080440 0
+        mww 0x31080460 0
+        mww 0x31080480 0
+
+        # Delays
+        mww 0x31080030 1
+        mww 0x31080034 6
+        mww 0x31080038 10
+        mww 0x31080044 1
+        mww 0x31080048 9
+        mww 0x3108004C 12
+        mww 0x31080050 10
+        mww 0x31080054 1
+        mww 0x31080058 1
+        mww 0x3108005C 0
+        
+        mww 0x31080100 0x5680
+        mww 0x31080104 0x302
+
+        # Init sequence
+        mww 0x31080020 0x193
+        sleep 1 busy
+        mww 0x31080024 1
+        mww 0x31080020 0x113
+        sleep 1 busy
+        mww 0x31080020 0x013
+        sleep 1 busy
+        mww 0x31080024 65
+        mww 0x31080020 0x093
+        mdw 0x80020000
+        mww 0x31080020 0x013
+
+        # SYS_CTRL remapping
+        mww 0x40004014 1
+}
diff --git a/tcl/target/lpc3250.cfg b/tcl/target/lpc3250.cfg
new file mode 100644
index 0000000..e902fb4
--- /dev/null
+++ b/tcl/target/lpc3250.cfg
@@ -0,0 +1,36 @@
+# lpc3250 config
+#
+
+if { [info exists CHIPNAME] } {
+   set  _CHIPNAME $CHIPNAME
+} else {
+   set  _CHIPNAME lpc3250
+}
+
+if { [info exists ENDIAN] } {
+   set  _ENDIAN $ENDIAN
+} else {
+   set  _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   set _CPUTAPID 0x17900f0f
+}
+
+if { [info exists SJCTAPID ] } {
+   set _SJCTAPID $SJCTAPID
+} else {
+   set _SJCTAPID 0x1b900f0f
+}
+
+jtag newtap $_CHIPNAME sjc -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_SJCTAPID
+
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME arm926ejs -endian little -chain-position $_TARGETNAME -work-area-phys 0x00000000 -work-area-size 0x7d0000 -work-area-backup 0
+
+proc power_restore {} { puts "Sensed power restore. No action." }
+proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/phytec_lpc3250.cfg |   88 ++++++++++++++++++++++++++++++++++++++++++
 tcl/target/lpc3250.cfg       |   36 +++++++++++++++++
 2 files changed, 124 insertions(+), 0 deletions(-)
 create mode 100644 tcl/board/phytec_lpc3250.cfg
 create mode 100644 tcl/target/lpc3250.cfg


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-176-g95ed9c4

From: Spencer O. <nt...@us...> - 2010-02-03 14:10:18

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  95ed9c43936d0d41c5b298fc4efaba4dc2e20f18 (commit)
      from  18969466c91e75102f76be60d00a11cb93ed329d (commit)

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- Log -----------------------------------------------------------------
commit 95ed9c43936d0d41c5b298fc4efaba4dc2e20f18
Author: Spencer Oliver <nt...@us...>
Date:   Wed Feb 3 13:08:42 2010 +0000

    JTAG: fix bug when no interface connected
    
     - fix coredump when OpenOCD is started without a jtag interface connected.
    
    Signed-off-by: Spencer Oliver <nt...@us...>

diff --git a/src/jtag/core.c b/src/jtag/core.c
index 8a580e9..4f517c0 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -1623,6 +1623,13 @@ bool jtag_will_verify_capture_ir()
 
 int jtag_power_dropout(int *dropout)
 {
+	if (jtag == NULL)
+	{
+		/* TODO: as the jtag interface is not valid all
+		 * we can do at the moment is exit OpenOCD */
+		LOG_ERROR("No Valid JTAG Interface Configured.");
+		exit(-1);
+	}
 	return jtag->power_dropout(dropout);
 }
 

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/core.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-175-g1896946

From: David B. <dbr...@us...> - 2010-02-02 20:10:23

This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
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      from  5750e899e03aa3312202be3ff217645c5f69304d (commit)

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- Log -----------------------------------------------------------------
commit 18969466c91e75102f76be60d00a11cb93ed329d
Author: Harald Kipp <har...@eg...>
Date:   Tue Feb 2 11:09:53 2010 -0800

    AT91R40008/Ethernut 3 configuration
    
    Moved board specific settings from target/at91r40008.cfg to a new
    file board/ethernut3.cfg.
    
    Set correct CPUTAPID.  Reset delay increased, see MIC2775 data sheet.
    Increased work area size from 16k to 128k.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/tcl/board/ethernut3.cfg b/tcl/board/ethernut3.cfg
new file mode 100644
index 0000000..f22e688
--- /dev/null
+++ b/tcl/board/ethernut3.cfg
@@ -0,0 +1,86 @@
+#
+# Ethernut 3 board configuration file
+#
+# http://www.ethernut.de/en/hardware/enut3/
+
+
+# AT91R40008-66AU ARM7TDMI Microcontroller
+# 256kB internal RAM
+source [find target/at91r40008.cfg]
+
+
+# AT49BV322A-70TU NOR Flash
+# 2M x 16 mode at address 0x10000000
+# Common flash interface supported
+#
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME cfi 0x10000000 0x400000 2 2 $_TARGETNAME
+
+
+# Micrel MIC2775-29YM5 Supervisor
+# Reset output will remain active for 280ms (maximum)
+#
+jtag_nsrst_delay 300
+jtag_ntrst_delay 300
+
+
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+jtag_khz 16000
+
+
+# Target events
+#
+$_TARGETNAME configure -event reset-init { board_init }
+
+# Initialize board hardware
+#
+proc board_init { } {
+	board_remap
+	flash probe 0
+}
+
+# Memory remap
+#
+proc board_remap {{VERBOSE 0}} {
+	# CS0: NOR flash
+	#      16MB @ 0x10000000
+	#      16-bit data bus
+	#      4 wait states
+	#
+	mww 0xffe00000 0x1000212d
+
+	# CS1: Ethernet controller
+	#      1MB @ 0x20000000
+	#      16-bit data bus
+	#      2 wait states
+	#      Byte select access
+	#
+	mww 0xffe00004 0x20003025
+
+	# CS2: CPLD registers
+	#      1MB @ 0x21000000
+	#      8-bit data bus
+	#      2 wait states
+	#
+	mww 0xffe00008 0x21002026
+
+	# CS3: Expansion bus
+	#      1MB @ 0x22000000
+	#      8-bit data bus
+	#      8 wait states
+	#
+	mww 0xffe00010 0x22002e3e
+
+	# Remap command
+	#
+	mww 0xffe00020 0x00000001
+
+	if {$VERBOSE != 0} {
+		puts "0x00000000 RAM"
+		puts "0x10000000 Flash"
+		puts "0x20000000 Ethernet"
+		puts "0x21000000 CPLD"
+		puts "0x22000000 Expansion"
+	}
+}
diff --git a/tcl/target/at91r40008.cfg b/tcl/target/at91r40008.cfg
index 9069ae5..9c0c483 100644
--- a/tcl/target/at91r40008.cfg
+++ b/tcl/target/at91r40008.cfg
@@ -1,9 +1,13 @@
+# AT91R40008 target configuration file
+
+# TRST is tied to SRST on the AT91X40 family.
+reset_config srst_only srst_pulls_trst
 
 
-if { [info exists CHIPNAME] } {
+if {[info exists CHIPNAME]} {
    set  _CHIPNAME $CHIPNAME
 } else {
-   set  _CHIPNAME at9r40008
+   set  _CHIPNAME at91r40008
 }
 
 if { [info exists ENDIAN] } {
@@ -12,41 +16,14 @@ if { [info exists ENDIAN] } {
    set  _ENDIAN little
 }
 
+# Setup the JTAG scan chain.
 if { [info exists CPUTAPID ] } {
    set _CPUTAPID $CPUTAPID
 } else {
-  # force an error till we get a good number
-   set _CPUTAPID 0xffffffff
+   set _CPUTAPID 0x1f0f0f0f
 }
-
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only srst_pulls_trst
-
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
 
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
-
-
-$_TARGETNAME configure -event gdb-flash-erase-start {
-	wait_halt
-	sleep 10
-	poll
-	# Ethernut 3 remapping is required to access external flash memory.
-	mww 0xffe00000 0x1000213d
-	mww 0xffe00004 0x20003e3d
-	mww 0xffe00020 0x00000001
-}
-
-$_TARGETNAME configure -work-area-phys 0x3C000 -work-area-size 0x4000 -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME cfi 0x10000000 0x400000 2 2 $_TARGETNAME
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
+$_TARGETNAME configure -work-area-phys 0x20000 -work-area-size 0x20000 -work-area-backup 0

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/ethernut3.cfg   |   86 +++++++++++++++++++++++++++++++++++++++++++++
 tcl/target/at91r40008.cfg |   41 +++++-----------------
 2 files changed, 95 insertions(+), 32 deletions(-)
 create mode 100644 tcl/board/ethernut3.cfg


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-174-g5750e89

From: David B. <dbr...@us...> - 2010-02-02 19:53:30

This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 5750e899e03aa3312202be3ff217645c5f69304d
Author: David Brownell <dbr...@us...>
Date:   Tue Feb 2 10:53:13 2010 -0800

    NOR: User's Guide updates
    
    Remove long-obsolete text about "erase_check" affecting "flash info" output.
    Move parts of that text to "protect_check", where it's still relevant; and
    update the "flash info" description to mention the issue.
    
    (This is still awkward.  It might be best to make "protect_check" mirror
    "erase_check" by dumping what it finds, so "flash info" doesn't dump any
    potentially-stale cache info.)
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 38fa92f..957c79c 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4033,17 +4033,14 @@ it has been removed by the @option{unlock} flag.
 Check erase state of sectors in flash bank @var{num},
 and display that status.
 The @var{num} parameter is a value shown by @command{flash banks}.
-This is the only operation that
-updates the erase state information displayed by @option{flash info}. That means you have
-to issue a @command{flash erase_check} command after erasing or programming the device
-to get updated information.
-(Code execution may have invalidated any state records kept by OpenOCD.)
 @end deffn
 
 @deffn Command {flash info} num
 Print info about flash bank @var{num}
 The @var{num} parameter is a value shown by @command{flash banks}.
-The information includes per-sector protect status.
+The information includes per-sector protect status, which may be
+incorrect (outdated) unless you first issue a
+@command{flash protect_check num} command.
 @end deffn
 
 @anchor{flash protect}
@@ -4060,6 +4057,8 @@ The @var{num} parameter is a value shown by @command{flash banks}.
 Check protection state of sectors in flash bank @var{num}.
 The @var{num} parameter is a value shown by @command{flash banks}.
 @comment @option{flash erase_sector} using the same syntax.
+This updates the protection information displayed by @option{flash info}.
+(Code execution may have invalidated any state records kept by OpenOCD.)
 @end deffn
 
 @anchor{Flash Driver List}

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi |   11 +++++------
 1 files changed, 5 insertions(+), 6 deletions(-)


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From: David B. <dbr...@us...> - 2010-02-02 18:31:20

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The branch, master has been updated
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       via  503f6139c7ed05339daea8c4984d32840d795222 (commit)
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- Log -----------------------------------------------------------------
commit cc440ca1d44f0aaaf34daa365966b7b092126913
Author: Edgar Grimberg <edg...@zy...>
Date:   Tue Feb 2 13:17:26 2010 +0100

    tcl/str7x: Reset init unlocks the flash
    
    For STR7x flash, the device cannot be queried for the protect status.
    The solution is to remove the protection on reset init. The driver
    also initialises the sector protect field to unprotected.
    
    [dbr...@us...: line length shrinkage]
    
    Signed-off-by: Edgar Grimberg <edg...@zy...>
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/tcl/target/str730.cfg b/tcl/target/str730.cfg
index 381fa5f..cab2338 100644
--- a/tcl/target/str730.cfg
+++ b/tcl/target/str730.cfg
@@ -34,7 +34,14 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
 
 $_TARGETNAME configure -event reset-start { jtag_khz 10 }
-$_TARGETNAME configure -event reset-init { jtag_khz 3000 }
+$_TARGETNAME configure -event reset-init {
+	jtag_khz 3000
+
+# Because the hardware cannot be interrogated for the protection state
+# of sectors, initialize all the sectors to be unprotected. The initial
+# state is reflected by the driver, too.
+	flash protect 0 0 last off
+}
 $_TARGETNAME configure -event gdb-flash-erase-start {
 	flash protect 0 0 7 off
 }
diff --git a/tcl/target/str750.cfg b/tcl/target/str750.cfg
index 5df968b..c467ae2 100644
--- a/tcl/target/str750.cfg
+++ b/tcl/target/str750.cfg
@@ -36,7 +36,15 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
 
 $_TARGETNAME configure -event reset-start  { jtag_khz 10 }
-$_TARGETNAME configure -event reset-init { jtag_khz 3000 }
+$_TARGETNAME configure -event reset-init {
+	jtag_khz 3000
+
+# Because the hardware cannot be interrogated for the protection state
+# of sectors, initialize all the sectors to be unprotected. The initial
+# state is reflected by the driver, too.
+	flash protect 0 0 last off
+	flash protect 1 0 last off
+}
 $_TARGETNAME configure -event gdb-flash-erase-start {
 	flash protect 0 0 7 off
 	flash protect 1 0 1 off

commit 503f6139c7ed05339daea8c4984d32840d795222
Author: Edgar Grimberg <edg...@zy...>
Date:   Tue Feb 2 10:39:52 2010 +0100

    flash/str7x: After reset init the flash is unlocked
    
    The default state of the STR7 flash after a reset init is unlocked.
    The information in the flash driver now reflects this.
    
    The information about the lock status cannot be read from the
    flash chip, so the user is informed that flash info might not
    contain accurate information.
    
    [dbr...@us...: line length shrinkage]
    
    Signed-off-by: Edgar Grimberg <edg...@zy...>
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/flash/nor/str7x.c b/src/flash/nor/str7x.c
index a2e27da..3bf07c9 100644
--- a/src/flash/nor/str7x.c
+++ b/src/flash/nor/str7x.c
@@ -93,7 +93,10 @@ static int str7x_build_block_list(struct flash_bank *bank)
 		bank->sectors[num_sectors].offset = mem_layout_str7bank0[i].sector_start;
 		bank->sectors[num_sectors].size = mem_layout_str7bank0[i].sector_size;
 		bank->sectors[num_sectors].is_erased = -1;
-		bank->sectors[num_sectors].is_protected = 1;
+		/* the reset_init handler marks all the sectors unprotected,
+		 * matching hardware after reset; keep the driver in sync
+		 */
+		bank->sectors[num_sectors].is_protected = 0;
 		str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank0[i].sector_bit;
 	}
 
@@ -102,7 +105,10 @@ static int str7x_build_block_list(struct flash_bank *bank)
 		bank->sectors[num_sectors].offset = mem_layout_str7bank1[i].sector_start;
 		bank->sectors[num_sectors].size = mem_layout_str7bank1[i].sector_size;
 		bank->sectors[num_sectors].is_erased = -1;
-		bank->sectors[num_sectors].is_protected = 1;
+		/* the reset_init handler marks all the sectors unprotected,
+		 * matching hardware after reset; keep the driver in sync
+		 */
+		bank->sectors[num_sectors].is_protected = 0;
 		str7x_info->sector_bits[num_sectors++] = mem_layout_str7bank1[i].sector_bit;
 	}
 
@@ -600,6 +606,12 @@ COMMAND_HANDLER(str7x_handle_part_id_command)
 static int str7x_info(struct flash_bank *bank, char *buf, int buf_size)
 {
 	snprintf(buf, buf_size, "str7x flash driver info");
+	/* STR7x flash doesn't support sector protection interrogation.
+	 * FLASH_NVWPAR acts as a write only register; its read value
+	 * doesn't reflect the actual protection state of the sectors.
+	 */
+	LOG_WARNING("STR7x flash lock information might not be correct "
+			"due to hardware limitations.");
 	return ERROR_OK;
 }
 
diff --git a/tcl/target/str710.cfg b/tcl/target/str710.cfg
index 9da69ac..028c604 100644
--- a/tcl/target/str710.cfg
+++ b/tcl/target/str710.cfg
@@ -30,7 +30,15 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi
 
 $_TARGETNAME configure -event reset-start { jtag_khz 10 }
-$_TARGETNAME configure -event reset-init { jtag_khz 6000 }
+$_TARGETNAME configure -event reset-init {
+	jtag_khz 6000
+
+# Because the hardware cannot be interrogated for the protection state
+# of sectors, initialize all the sectors to be unprotected. The initial
+# state is reflected by the driver, too.
+	flash protect 0 0 last off
+	flash protect 1 0 last off
+}
 $_TARGETNAME configure -event gdb-flash-erase-start {
 	flash protect 0 0 7 off
 	flash protect 1 0 1 off

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/str7x.c |   16 ++++++++++++++--
 tcl/target/str710.cfg |   10 +++++++++-
 tcl/target/str730.cfg |    9 ++++++++-
 tcl/target/str750.cfg |   10 +++++++++-
 4 files changed, 40 insertions(+), 5 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-171-g3d2d5dc

From: Nicolas P. <np...@us...> - 2010-02-02 06:12:20

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  3d2d5dcc9c27b84dc2e5e9ed53be0f784a450042 (commit)
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- Log -----------------------------------------------------------------
commit 3d2d5dcc9c27b84dc2e5e9ed53be0f784a450042
Author: Nicolas Pitre <ni...@fl...>
Date:   Tue Feb 2 00:05:42 2010 -0500

    ARM semihosting: fix EOF handling with SYS_READ
    
    The semihosting interface has a strange convention for read/write where
    the unused amount of buffer must be returned.  We failed to return the
    total buffer size when the local read() call returned 0.
    
    Signed-off-by: Nicolas Pitre <ni...@ma...>

diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index c41c5a0..9b853d9 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -190,7 +190,7 @@ static int do_semihosting(struct target *target)
 			} else {
 				result = read(fd, buf, l);
 				armv4_5->semihosting_errno = errno;
-				if (result > 0) {
+				if (result >= 0) {
 					retval = target_write_buffer(target, a, result, buf);
 					if (retval != ERROR_OK) {
 						free(buf);

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_semihosting.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


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From: Øyvind H. <go...@us...> - 2010-02-01 15:43:38

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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit bef37ceba2bde6a34d003762bced007bed894bc7
Author: Edgar Grimberg <edg...@zy...>
Date:   Fri Jan 29 09:46:11 2010 +0100

    Test cases ran on v0.4.0-rc1
    
    Test cases ran on v0.4.0-rc1 for a number of targets:
    AT91FR40162
    LPC2148
    SAM7
    STR710
    STR912
    
    The goal of the testing session was to prove basic functionality of OpenOCD for different targets.
    
    Signed-off-by: Edgar Grimberg <edg...@zy...>

diff --git a/testing/results/v0.4.0-rc1/AT91FR40162.html b/testing/results/v0.4.0-rc1/AT91FR40162.html
new file mode 100755
index 0000000..0baa31e
--- /dev/null
+++ b/testing/results/v0.4.0-rc1/AT91FR40162.html
@@ -0,0 +1,856 @@
+<html>
+<head>
+<title>Test results for revision 1.62</title>
+</head>
+
+<body>
+
+<H1>SAM7</H1>
+
+<H2>Connectivity</H2>
+<table border=1>
+	<tr>
+		<td>ID</td>
+		<td>Target</td>
+		<td>Interface</td>
+		<td>Description</td>
+		<td>Initial state</td>
+		<td>Input</td>
+		<td>Expected output</td>
+		<td>Actual output</td>
+		<td>Pass/Fail</td>
+	</tr>
+	<tr>
+		<td><a name="CON001"/>CON001</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>Telnet connection</td>
+		<td>Power on, jtag target attached</td>
+		<td>On console, type<br><code>telnet ip port</code></td>
+		<td><code>Open On-Chip Debugger<br>></code></td>
+		<td><code>Open On-Chip Debugger<br>></code></td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="CON002"/>CON002</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>GDB server connection</td>
+		<td>Power on, jtag target attached</td>
+		<td>On GDB console, type<br><code>target remote ip:port</code></td>
+		<td><code>Remote debugging using 10.0.0.73:3333</code></td>
+		<td><code>
+			(gdb) tar remo 10.0.0.138:3333<br>
+			Remote debugging using 10.0.0.138:3333<br>
+			0x000155b8 in ?? ()<br>
+		</code></td>
+		<td>PASS</td>	
+	</tr>
+</table>
+
+<H2>Reset</H2>
+<table border=1>
+	<tr>
+		<td>ID</td>
+		<td>Target</td>
+		<td>Interface</td>
+		<td>Description</td>
+		<td>Initial state</td>
+		<td>Input</td>
+		<td>Expected output</td>
+		<td>Actual output</td>
+		<td>Pass/Fail</td>
+	</tr>
+	<tr>
+		<td><a name="RES001"/>RES001</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>Reset halt on a blank target</td>
+		<td>Erase all the content of the flash</td>
+		<td>Connect via the telnet interface and type <br><code>reset halt</code></td>
+		<td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
+		<td>
+			<code>
+				> mdw  0x01000000 32<br>                    
+				0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br> 
+				0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+				0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br> 
+				0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br> 
+				> reset halt<br>
+				JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)<br>
+				srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+				target state: halted<br>
+				target halted in ARM state due to debug-request, current mode: Supervisor<br>
+				cpsr: 0x600000d3 pc: 0x00008a70<br>
+				> <br>
+			</code>
+		</td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="RES002"/>RES002</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>Reset init on a blank target</td>
+		<td>Erase all the content of the flash</td>
+		<td>Connect via the telnet interface and type <br><code>reset init</code></td>
+		<td>Reset should return without error and the output should contain <br><code>executing reset script 'name_of_the_script'</code></td>
+		<td>
+			<code>
+				> reset init<br>
+				JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)<br>
+				srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+				target state: halted<br>
+				target halted in ARM state due to debug-request, current mode: Supervisor<br>
+				cpsr: 0x600000d3 pc: 0x00008ea4<br>
+				> <br>
+			</code>
+		</td>
+		<td>PASS<br>
+		NOTE! Even if there is no message, the reset script is being executed (proved by side effects)</td>	
+	</tr>
+	<tr>
+		<td><a name="RES003"/>RES003</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>Reset after a power cycle of the target</td>
+		<td>Reset the target then power cycle the target</td>
+		<td>Connect via the telnet interface and type <br><code>reset halt</code> after the power was detected</td>
+		<td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
+		<td>
+			<code>
+				Sensed nSRST asserted<br>
+				Sensed power dropout.<br>
+				target state: halted<br>
+				target halted in ARM state due to debug request, current mode: Supervisor<br>
+				cpsr: 0xf00000d3 pc: 0xd5dff7e6<br>
+				Sensed power restore.<br>
+				Sensed nSRST deasserted<br>
+				> reset halt<br>
+				JTAG device found: 0x3f0f0f0f (Manufacturer: 0x787, Part: 0xf0f0, Version: 0x3)<br>
+				srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+				target state: halted<br>
+				target halted in ARM state due to debug request, current mode: Supervisor<br>
+				cpsr: 0xf00000d3 pc: 0x0000072c<br>
+				><br>
+			</code>
+		</td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="RES004"/>RES004</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>Reset halt on a blank target where reset halt is supported</td>
+		<td>Erase all the content of the flash</td>
+		<td>Connect via the telnet interface and type <br><code>reset halt</code></td>
+		<td>Reset should return without error and the output should contain<br><code>target state: halted<br>pc = 0</code></td>
+		<td>
+			> reset halt<br>
+			JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)<br>
+			srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+			target state: halted<br>
+			target halted in ARM state due to debug-request, current mode: Supervisor<br>
+			cpsr: 0xf00000d3 pc: 0x00008b38<br>
+			> <br>
+		</td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="RES005"/>RES005</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>Reset halt on a blank target using return clock</td>
+		<td>Erase all the content of the flash, set the configuration script to use RCLK</td>
+		<td>Connect via the telnet interface and type <br><code>reset halt</code></td>
+		<td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
+		<td>
+			<code>
+				N/A, At91EB40A does <bold>NOT</bold> have support for RCLK
+			</code>	
+		</td>
+		<td>N/A</td>	
+	</tr>
+</table>
+
+<H2>JTAG Speed</H2>
+<table border=1>
+	<tr>
+		<td>ID</td>
+		<td>Target</td>
+		<td>ZY1000</td>
+		<td>Description</td>
+		<td>Initial state</td>
+		<td>Input</td>
+		<td>Expected output</td>
+		<td>Actual output</td>
+		<td>Pass/Fail</td>
+	</tr>
+	<tr>
+		<td><a name="SPD001"/>SPD001</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>16MHz on normal operation</td>
+		<td>Reset init the target according to RES002 </td>
+		<td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
+		<td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
+		<td>
+			<code>
+				> reset halt<br>
+				JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)<br>
+				srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+				target state: halted<br>
+				target halted in ARM state due to debug-request, current mode: Supervisor<br>
+				cpsr: 0xf00000d3 pc: 0x00008ae8<br>
+				> jtag_khz 16000  <br>
+				jtag_speed 4 => JTAG clk=16.000000<br>
+				16000 kHz<br>
+				> mdw 0 32   <br>   
+				0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br> 
+				0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+				0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+				0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+			</code>
+		</td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="SPD002"/>SPD002</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>8MHz on normal operation</td>
+		<td>Reset init the target according to RES002 </td>
+		<td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
+		<td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
+		<td>
+			<code>
+				> reset halt    <br>
+				JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)<br>
+				srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+				target state: halted<br>
+				target halted in ARM state due to debug-request, current mode: Supervisor<br>
+				cpsr: 0xf00000d3 pc: 0x00008c14<br>
+				> jtag_khz 8000 <br>
+				jtag_speed 8 => JTAG clk=8.000000<br>
+				8000 kHz<br>
+				> mdw 0 32  <br>   
+				0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br> 
+				0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+				0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+				0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+				> <br>
+			</code>
+		</td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="SPD003"/>SPD003</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>4MHz on normal operation</td>
+		<td>Reset init the target according to RES002 </td>
+		<td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
+		<td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
+		<td>
+			<code>
+				> reset halt   <br>
+				JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)<br>
+				srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+				target state: halted<br>
+				target halted in ARM state due to debug-request, current mode: Supervisor<br>
+				cpsr: 0xf00000d3 pc: 0x00008bc4<br>
+				> jtag_khz 4000<br>
+				jtag_speed 16 => JTAG clk=4.000000<br>
+				4000 kHz<br>
+				> mdw 0 32  <br>   
+				0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br> 
+				0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+				0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+				0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+				> <br>
+			</code>
+		</td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="SPD004"/>SPD004</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>2MHz on normal operation</td>
+		<td>Reset init the target according to RES002 </td>
+		<td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
+		<td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
+		<td>
+			<code>
+				> reset halt<br>
+				JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)<br>
+				srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+				target state: halted<br>
+				target halted in ARM state due to debug-request, current mode: Supervisor<br>
+				cpsr: 0xf00000d3 pc: 0x00009678<br>
+				> jtag_khz 2000<br>
+				jtag_speed 32 => JTAG clk=2.000000<br>
+				2000 kHz<br>
+				> mdw 0 32     <br>
+				0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+				0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+				0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+				0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+				> <br>
+			</code>
+		</td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="SPD005"/>SPD005</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>RCLK on normal operation</td>
+		<td>Reset init the target according to RES002 </td>
+		<td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
+		<td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
+		<td>
+			<code>
+				> jtag_khz 0<br>
+				RCLK - adaptive<br>
+				RCLK timeout<br>
+			</code>
+			N/A for this target
+		</td>
+		<td>N/A for this target</td>	
+	</tr>
+</table>
+
+<H2>Debugging</H2>
+<table border=1>
+	<tr>
+		<td>ID</td>
+		<td>Target</td>
+		<td>Interface</td>
+		<td>Description</td>
+		<td>Initial state</td>
+		<td>Input</td>
+		<td>Expected output</td>
+		<td>Actual output</td>
+		<td>Pass/Fail</td>
+	</tr>
+	<tr>
+		<td><a name="DBG001"/>DBG001</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>Load is working</td>
+		<td>Reset init is working, RAM is accesible, GDB server is started</td>
+		<td>On the console of the OS: <br>
+			<code>$ arm-none-eabi-gdb redboot_ram.elf</code><br>
+			<code>(gdb) target remote ip:port</code><br>
+			<code>(gdb) load</load>
+		</td>
+		<td>Load should return without error, typical output looks like:<br>
+			<code>
+				Loading section .text, size 0x14c lma 0x0<br>
+				Start address 0x40, load size 332<br>
+				Transfer rate: 180 bytes/sec, 332 bytes/write.<br>
+			</code>
+		</td>
+		<td><code>
+			(gdb) load<br>
+			Loading section .rom_vectors, size 0x40 lma 0xc000<br>
+			Loading section .text, size 0x103e8 lma 0xc040<br>
+			Loading section .rodata, size 0x1a84 lma 0x1c428<br>
+			Loading section .data, size 0x3ec lma 0x1deac<br>
+			Start address 0xc040, load size 74392<br>
+			Transfer rate: 572 KB/sec, 9299 bytes/write.<br>
+			(gdb)
+		</code></td>
+		<td>PASS</td>	
+	</tr>
+	
+	<tr>
+		<td><a name="DBG002"/>DBG002</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>Software breakpoint</td>
+		<td>Load the redboot_ram.elf application, use instructions from GDB001</td>
+		<td>In the GDB console:<br>
+			<code>
+				(gdb) monitor arm7_9 dbgrq enable<br>
+				software breakpoints enabled<br>
+				(gdb) break cyg_start<br>
+				Breakpoint 1 at 0xec: file src/main.c, line 71.<br>
+				(gdb) continue<br>
+				Continuing.
+			</code>
+		</td>
+		<td>The software breakpoint should be reached, a typical output looks like:<br>
+			<code>
+				Breakpoint 1, main () at src/main.c:69<br>
+				69	  DWORD a = 1;<br>
+			</code>
+		</td>
+		<td>
+			<code>
+				(gdb) monitor arm7_9 dbgrq enable<br>
+				use of EmbeddedICE dbgrq instead of breakpoint for target halt enabled<br>
+				(gdb) break cyg_start<br>
+				<br>
+				Breakpoint 1 at 0x155b8: file /home/edgar/temp/ecosboard/packages/redboot/current/src/main.c, line 264.<br>
+				(gdb) continue<br>
+				Continuing.<br>
+				<br>
+				Breakpoint 1, cyg_start ()<br>
+				    at /home/edgar/temp/ecosboard/packages/redboot/current/src/main.c:264<br>
+				264	    CYGACC_CALL_IF_MONITOR_VERSION_SET(RedBoot_version);<br>
+				(gdb) <br>
+			</code>
+		</td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="DBG003"/>DBG003</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>Single step in a RAM application</td>
+		<td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
+		<td>In GDB, type <br><code>(gdb) step</code></td>
+		<td>The next instruction should be reached, typical output:<br>
+			<code>
+				(gdb) step<br>
+				70	  DWORD b = 2;
+
+			</code>
+		</td>
+		<td>
+			<code>
+				(gdb) step<br>
+				266	    CYGACC_CALL_IF_MONITOR_RETURN_SET(return_to_redboot);<br>
+				(gdb)<br>
+			</code>
+		</td>
+		<td>PASS</td>
+	</tr>
+	<tr>
+		<td><a name="DBG004"/>DBG004</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>Software break points are working after a reset</td>
+		<td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
+		<td>In GDB, type <br><code>
+			(gdb) monitor reset init<br>
+			(gdb) load<br>
+			(gdb) continue<br>
+			</code></td>
+		<td>The breakpoint should be reached, typical output:<br>
+			<code>
+				Breakpoint 1, main () at src/main.c:69<br>
+				69	  DWORD a = 1;
+			</code>
+		</td>
+		<td><code>
+			(gdb) moni reset init<br>
+			JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)<br>
+			srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+			target state: halted<br>
+			target halted in ARM state due to debug-request, current mode: Supervisor<br>
+			cpsr: 0x600000d3 pc: 0x00008ae8<br>
+			(gdb) load<br>
+			Loading section .rom_vectors, size 0x40 lma 0xc000<br>
+			Loading section .text, size 0x103e8 lma 0xc040<br>
+			Loading section .rodata, size 0x1a84 lma 0x1c428<br>
+			Loading section .data, size 0x3ec lma 0x1deac<br>
+			Start address 0xc040, load size 74392<br>
+			Transfer rate: 576 KB/sec, 9299 bytes/write.<br>
+			(gdb) c<br>
+			Continuing.<br>
+			<br>
+			Breakpoint 1, cyg_start ()<br>
+			    at /home/edgar/temp/ecosboard/packages/redboot/current/src/main.c:264<br>
+			264	    CYGACC_CALL_IF_MONITOR_VERSION_SET(RedBoot_version);<br>
+			(gdb) <br>
+		</code></td>
+		<td>PASS</td>
+	</tr>
+	<tr>
+		<td><a name="DBG005"/>DBG005</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>Hardware breakpoint</td>
+		<td>Flash the redboot_rom.elf application. Make this test after FLA004 has passed</td>
+		<td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
+			<code>
+				(gdb) monitor reset init<br>
+				(gdb) load<br>
+				Loading section .text, size 0x194 lma 0x100000<br>
+				Start address 0x100040, load size 404<br>
+				Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
+				(gdb) monitor arm7_9  force_hw_bkpts enable<br>
+				force hardware breakpoints enabled<br>
+				(gdb) break main<br>
+				Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
+				(gdb) continue<br>
+			</code>
+		</td>
+		<td>The breakpoint should be reached, typical output:<br>
+			<code>
+				Continuing.<br>
+				<br>
+				Breakpoint 1, main () at src/main.c:69<br>
+				69        DWORD a = 1;<br>
+			</code>
+		</td>
+		<td>
+		<code>
+			(gdb) load<br>
+			Loading section .rom_vectors, size 0x40 lma 0x1000000<br>
+			Loading section .text, size 0x10638 lma 0x1000040<br>
+			Loading section .rodata, size 0x1a84 lma 0x1010678<br>
+			Loading section .data, size 0x428 lma 0x10120fc<br>
+			Start address 0x1000040, load size 75044<br>
+			Transfer rate: 33 KB/sec, 9380 bytes/write.<br>
+			(gdb) break cyg_start<br>
+			Breakpoint 1 at 0x100979c: file /home/edgar/temp/ecosboard/packages/redboot/current/src/main.c, line 264.<br>
+			(gdb) c<br>
+			Continuing.<br>
+			Note: automatically using hardware breakpoints for read-only addresses.<br>
+			<br>
+			Breakpoint 1, cyg_start () at /home/edgar/temp/ecosboard/packages/redboot/current/src/main.c:264<br>
+			264	    CYGACC_CALL_IF_MONITOR_VERSION_SET(RedBoot_version);<br>
+			(gdb) <br>
+		</code>
+		</td>
+		<td>PASS</td>
+	</tr>
+	<tr>
+		<td><a name="DBG006"/>DBG006</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>Hardware breakpoint is set after a reset</td>
+		<td>Follow the instructions to flash and insert a hardware breakpoint from DBG005</td>
+		<td>In GDB, type <br>
+			<code>
+				(gdb) monitor reset<br>
+				(gdb) monitor reg pc 0x100000<br>
+				pc (/32): 0x00100000<br>
+				(gdb) continue
+			</code><br>
+			where the value inserted in PC is the start address of the application
+		</td>
+		<td>The breakpoint should be reached, typical output:<br>
+			<code>
+				Continuing.<br>
+				<br>
+				Breakpoint 1, main () at src/main.c:69<br>
+				69        DWORD a = 1;<br>
+			</code>
+		</td>
+		<td>
+		<code>
+			(gdb) moni reset init<br>
+			JTAG tap: zy1000.cpu tap/device found: 0x1f0f0f0f (mfg: 0x787, part: 0xf0f0, ver: 0x1)<br>
+			srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+			target state: halted<br>
+			target halted in ARM state due to debug-request, current mode: Supervisor<br>
+			cpsr: 0x200000d3 pc: 0x01000200<br>
+			(gdb) moni reg pc 0x1000000<br>
+			pc (/32): 0x01000000<br>
+			(gdb) c<br>
+			Continuing.<br>
+			<br>
+			Breakpoint 1, cyg_start () at /home/edgar/temp/ecosboard/packages/redboot/current/src/main.c:264<br>
+			264	    CYGACC_CALL_IF_MONITOR_VERSION_SET(RedBoot_version);<br>
+			(gdb) <br>
+		</code>
+		</td>
+		<td>PASS</td>
+	</tr>
+	<tr>
+		<td><a name="DBG007"/>DBG007</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>Single step in ROM</td>
+		<td>Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed</td>
+		<td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
+			<code>
+				(gdb) monitor reset<br>
+				(gdb) load<br>
+				Loading section .text, size 0x194 lma 0x100000<br>
+				Start address 0x100040, load size 404<br>
+				Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
+				(gdb) monitor arm7_9  force_hw_bkpts enable<br>
+				force hardware breakpoints enabled<br>
+				(gdb) break main<br>
+				Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
+				(gdb) continue<br>
+				Continuing.<br>
+				<br>
+				Breakpoint 1, main () at src/main.c:69<br>
+				69        DWORD a = 1;<br>
+				(gdb) step
+			</code>
+		</td>
+		<td>The breakpoint should be reached, typical output:<br>
+			<code>
+				target state: halted<br>
+				target halted in ARM state due to single step, current mode: Supervisor<br>
+				cpsr: 0x60000013 pc: 0x0010013c<br>
+				70        DWORD b = 2;<br>
+			</code>
+		</td>
+		<td><code>
+			Breakpoint 1, cyg_start () at /home/edgar/temp/ecosboard/packages/redboot/current/src/main.c:264<br>
+			264	    CYGACC_CALL_IF_MONITOR_VERSION_SET(RedBoot_version);<br>
+			(gdb) step<br>
+			266	    CYGACC_CALL_IF_MONITOR_RETURN_SET(return_to_redboot);<br>
+		</code></td>
+		<td>PASS</td>
+	</tr>
+</table>
+
+<H2>RAM access</H2>
+Note: these tests are not designed to test/debug the target, but to test functionalities!
+<table border=1>
+	<tr>
+		<td>ID</td>
+		<td>Target</td>
+		<td>Interface</td>
+		<td>Description</td>
+		<td>Initial state</td>
+		<td>Input</td>
+		<td>Expected output</td>
+		<td>Actual output</td>
+		<td>Pass/Fail</td>
+	</tr>
+	<tr>
+		<td><a name="RAM001"/>RAM001</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>32 bit Write/read RAM</td>
+		<td>Reset init is working</td>
+		<td>On the telnet interface<br>
+			<code>	> mww ram_address 0xdeadbeef 16<br>
+					> mdw ram_address 32
+			</code>
+		</td>
+		<td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.<br>
+			<code>
+				> mww 0x0 0xdeadbeef 16<br>
+				> mdw 0x0 32<br>
+				0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+				0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+				0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388<br>
+				0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388<br>
+			</code>
+		</td>
+		<td><code>
+			> mww 0 0xdeadbeef 16<br>
+			> mdw 0x0 32         <br>
+			0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br> 
+			0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef <br>
+			0x00000040: 15aadc6d 425b6f33 e789f955 d390dcc2 00080017 010067b4 010067b4 010067b4 <br>
+			0x00000060: 010067b4 00006e74 00006e74 010067b4 010067b4 010067b4 010067b4 010067b4 <br>
+		</code></td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="RAM002"/>RAM002</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>16 bit Write/read RAM</td>
+		<td>Reset init is working</td>
+		<td>On the telnet interface<br>
+			<code>	> mwh ram_address 0xbeef 16<br>
+					> mdh ram_address 32
+			</code>
+		</td>
+		<td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.<br>
+			<code>
+				> mwh 0x0 0xbeef 16<br>
+				> mdh 0x0 32<br>
+				0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
+				0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000<br>
+				>
+			</code>
+		</td>
+		<td><code>
+				> mwh 0 0xbeef 16<br>    
+				> mdh 0x0 32<br>
+				0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br> 
+				0x00000020:   00   00   00   00   00   00   00   00   00   00   00   00   00   00   00   00 <br>
+			</code></td>
+		<td>PASS<br>There is a problem with the formatting of the output</td>	
+	</tr>
+	<tr>
+		<td><a name="RAM003"/>RAM003</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>8 bit Write/read RAM</td>
+		<td>Reset init is working</td>
+		<td>On the telnet interface<br>
+			<code>	> mwb ram_address 0xab 16<br>
+					> mdb ram_address 32
+			</code>
+		</td>
+		<td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.<br>
+			<code>
+				> mwb ram_address 0xab 16<br>
+				> mdb ram_address 32<br>
+				0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
+				>
+			</code>
+		</td>
+		<td><code>
+			> mwb 0x0 0xab 16<br>
+			> mdb 0x0 32     <br>
+			0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br> 
+		</code></td>
+		<td>PASS</td>	
+	</tr>
+</table>
+
+
+
+<H2>Flash access</H2>
+<table border=1>
+	<tr>
+		<td>ID</td>
+		<td>Target</td>
+		<td>Interface</td>
+		<td>Description</td>
+		<td>Initial state</td>
+		<td>Input</td>
+		<td>Expected output</td>
+		<td>Actual output</td>
+		<td>Pass/Fail</td>
+	</tr>
+	<tr>
+		<td><a name="FLA001"/>FLA001</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>Flash probe</td>
+		<td>Reset init is working</td>
+		<td>On the telnet interface:<br>
+			<code>	> flash probe 0</code>
+		</td>
+		<td>The command should execute without error. The output should state the name of the flash and the starting address. An example of output:<br>
+			<code>flash 'ecosflash' found at 0x01000000</code>
+		</td>
+		<td>
+		<code>
+			> flash probe 0
+			flash 'ecosflash' found at 0x01000000
+		</code>
+		</td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="FLA002"/>FLA002</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>flash fillw</td>
+		<td>Reset init is working, flash is probed</td>
+		<td>On the telnet interface<br>
+			<code>	> flash fillw 0x100000 0xdeadbeef 16
+			</code>
+		</td>
+		<td>The commands should execute without error. The output looks like:<br>
+			<code>
+				wrote 64 bytes to 0x0100000 in 11.610000s (0.091516 kb/s)
+			</code><br>
+			To verify the contents of the flash:<br>
+			<code>
+				> mdw 0x100000 32<br>
+				0x0100000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+				0x0100020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+				0x0100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+				0x0100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+			</code>
+		</td>
+		<td><code>
+				> flash fillw 0x01000000 0xdeadbeef 16 <br>  
+				wrote 64 bytes to 0x01000000 in 0.010000s (6.250 kb/s)<br>
+				> mdw 0x1000000 32<br>
+				0x01000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br> 
+				0x01000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef <br>
+				0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+				0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+				>
+			</code></td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="FLA003"/>FLA003</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>Flash erase</td>
+		<td>Reset init is working, flash is probed</td>
+		<td>On the telnet interface<br>
+			<code>	>  flash erase_address 0x100000 0x2000
+			</code>
+		</td>
+		<td>The commands should execute without error.<br>
+			<code>
+				erased address 0x0100000 length 8192 in 4.970000s
+			</code>
+			To check that the flash has been erased, read at different addresses. The result should always be 0xff. 
+			<code>
+				> mdw 0x100000 32<br>
+				0x0100000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+				0x0100020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+				0x0100040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+				0x0100060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff
+			</code>
+		</td>
+		<td><code>
+			> flash erase_address 0x1000000 0x10000<br>
+			erased address 0x01000000 (length 65536) in 0.840000s (76.190 kb/s)<br>
+			> mdw 0x1000000 32                     <br>
+			0x01000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br> 
+			0x01000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+			0x01000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+			0x01000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff <br>
+		</code></td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="FLA004"/>FLA004</td>
+		<td>AT91FR40162</td>
+		<td>ZY1000</td>
+		<td>Loading to flash from GDB</td>
+		<td>Reset init is working, flash is probed, connectivity to GDB server is working</td>
+		<td>Start GDB using a ROM elf image, eg: arm-elf-gdb test_rom.elf. <br>
+				<code>
+					(gdb) target remote ip:port<br>
+					(gdb) monitor reset halt<br>
+					(gdb) load<br>
+					Loading section .text, size 0x194 lma 0x100000<br>
+					Start address 0x100040, load size 404<br>
+					Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
+					(gdb) monitor verify_image path_to_elf_file		
+				</code>
+		</td>
+		<td>The output should look like:<br>
+			<code>
+				verified 404 bytes in 5.060000s
+			</code><br>
+			The failure message is something like:<br>
+			<code>Verify operation failed address 0x00200000. Was 0x00 instead of 0x18</code>
+		</td>
+		<td>
+			<code>
+				(gdb) load<br>
+				Loading section .rom_vectors, size 0x40 lma 0x1000000<br>
+				Loading section .text, size 0x10638 lma 0x1000040<br>
+				Loading section .rodata, size 0x1a84 lma 0x1010678<br>
+				Loading section .data, size 0x428 lma 0x10120fc<br>
+				Start address 0x1000040, load size 75044<br>
+				Transfer rate: 34 KB/sec, 9380 bytes/write.<br>
+				(gdb) moni verify_image /tftp/10.0.0.190/redboot_rom.elf<br>
+				keep_alive() was not invoked in the 1000ms timelimit. GDB alive packet not sent! (1820). Workaround: increase "set remotetimeout" in GDB<br>
+				verified 75044 bytes in 1.960000s (37.390 kb/s)<br>
+			</code>
+		</td>
+		<td>PASS</td>	
+	</tr>	
+</table>
+
+</body>
+</html>
\ No newline at end of file
diff --git a/testing/results/v0.4.0-rc1/LPC2148.html b/testing/results/v0.4.0-rc1/LPC2148.html
new file mode 100755
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--- /dev/null
+++ b/testing/results/v0.4.0-rc1/LPC2148.html
@@ -0,0 +1,933 @@
+<html>
+<head>
+<title>Test results for revision 1.62</title>
+</head>
+
+<body>
+
+<H1>LPC2148</H1>
+
+<H2>Connectivity</H2>
+<table border=1>
+	<tr>
+		<td>ID</td>
+		<td>Target</td>
+		<td>Interface</td>
+		<td>Description</td>
+		<td>Initial state</td>
+		<td>Input</td>
+		<td>Expected output</td>
+		<td>Actual output</td>
+		<td>Pass/Fail</td>
+	</tr>
+	<tr>
+		<td><a name="CON001"/>CON001</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>Telnet connection</td>
+		<td>Power on, jtag target attached</td>
+		<td>On console, type<br><code>telnet ip port</code></td>
+		<td><code>Open On-Chip Debugger<br>></code></td>
+		<td><code>Open On-Chip Debugger<br>></code></td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="CON002"/>CON002</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>GDB server connection</td>
+		<td>Power on, jtag target attached</td>
+		<td>On GDB console, type<br><code>target remote ip:port</code></td>
+		<td><code>Remote debugging using 10.0.0.73:3333</code></td>
+		<td><code>
+			(gdb) tar remo 10.0.0.73:3333<br>
+			Remote debugging using 10.0.0.73:3333<br>
+			0x00000000 in ?? ()<br>
+		</code></td>
+		<td>PASS</td>	
+	</tr>
+</table>
+
+<H2>Reset</H2>
+<table border=1>
+	<tr>
+		<td>ID</td>
+		<td>Target</td>
+		<td>Interface</td>
+		<td>Description</td>
+		<td>Initial state</td>
+		<td>Input</td>
+		<td>Expected output</td>
+		<td>Actual output</td>
+		<td>Pass/Fail</td>
+	</tr>
+	<tr>
+		<td><a name="RES001"/>RES001</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>Reset halt on a blank target</td>
+		<td>Erase all the content of the flash</td>
+		<td>Connect via the telnet interface and type <br><code>reset halt</code></td>
+		<td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
+		<td>
+			<code>
+				> mdw 0 32<br>
+				0x00000000: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+				0x00000020: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+				0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+				0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br>
+				> reset halt<br>
+				JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
+				srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+				target state: halted<br>
+				target halted in Thumb state due to debug-request, current mode: Supervisor<br>
+				cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
+				> 
+			</code>
+		</td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="RES002"/>RES002</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>Reset init on a blank target</td>
+		<td>Erase all the content of the flash</td>
+		<td>Connect via the telnet interface and type <br><code>reset init</code></td>
+		<td>Reset should return without error and the output should contain <br><code>executing reset script 'name_of_the_script'</code></td>
+		<td>
+			<code>
+				> reset init<br>
+				JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
+				srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+				target state: halted<br>
+				target halted in Thumb state due to debug-request, current mode: Supervisor<br>
+				cpsr: 0xa00000f3 pc: 0x7fffd2da<br>
+				core state: ARM<br>
+				>
+			</code>
+		</td>
+		<td>PASS<br>
+		NOTE! Even if there is no message, the reset script is being executed (proved by side effects)</td>	
+	</tr>
+	<tr>
+		<td><a name="RES003"/>RES003</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>Reset after a power cycle of the target</td>
+		<td>Reset the target then power cycle the target</td>
+		<td>Connect via the telnet interface and type <br><code>reset halt</code> after the power was detected</td>
+		<td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
+		<td>
+			<code>
+				nsed nSRST asserted.<br>
+				nsed power dropout.<br>
+				nsed power restore.<br>
+				SRST took 186ms to deassert<br>
+				JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
+				srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+				target state: halted<br>
+				target halted in Thumb state due to debug-request, current mode: Supervisor<br>
+				cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
+				core state: ARM<br>
+				> reset halt<br>
+				JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
+				srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+				target state: halted<br>
+				target halted in Thumb state due to debug-request, current mode: Supervisor<br>
+				cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
+				>
+			</code>
+		</td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="RES004"/>RES004</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>Reset halt on a blank target where reset halt is supported</td>
+		<td>Erase all the content of the flash</td>
+		<td>Connect via the telnet interface and type <br><code>reset halt</code></td>
+		<td>Reset should return without error and the output should contain<br><code>target state: halted<br>pc = 0</code></td>
+		<td>
+			<code>
+			> reset halt<br>
+			JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
+			srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+			target state: halted<br>
+			target halted in Thumb state due to debug-request, current mode: Supervisor<br>
+			cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
+			> 
+			</code>
+		</td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="RES005"/>RES005</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>Reset halt on a blank target using return clock</td>
+		<td>Erase all the content of the flash, set the configuration script to use RCLK</td>
+		<td>Connect via the telnet interface and type <br><code>reset halt</code></td>
+		<td>Reset should return without error and the output should contain<br><code>target state: halted</code></td>
+		<td>
+			<code>
+			> jtag_khz 0<br>
+			RCLK - adaptive<br>
+			> reset init<br>
+			JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
+			srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+			target state: halted<br>
+			target halted in Thumb state due to debug-request, current mode: Supervisor<br>
+			cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
+			core state: ARM<br>
+			> 
+			</code>
+		</td>
+		<td>PASS</td>	
+	</tr>
+</table>
+
+<H2>JTAG Speed</H2>
+<table border=1>
+	<tr>
+		<td>ID</td>
+		<td>Target</td>
+		<td>ZY1000</td>
+		<td>Description</td>
+		<td>Initial state</td>
+		<td>Input</td>
+		<td>Expected output</td>
+		<td>Actual output</td>
+		<td>Pass/Fail</td>
+	</tr>
+	<tr>
+		<td><a name="SPD001"/>SPD001</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>16MHz on normal operation</td>
+		<td>Reset init the target according to RES002 </td>
+		<td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
+		<td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
+		<td>
+			<code>
+				> jtag_khz 16000<br>
+				jtag_speed 4 => JTAG clk=16.000000<br>
+				16000 kHz<br>
+				> reset halt<br>    
+				JTAG scan chain interrogation failed: all zeroes<br>
+				Check JTAG interface, timings, target power, etc.<br>
+				error: -100<br>
+				Command handler execution failed<br>
+				in procedure 'reset' called at file "command.c", line 638<br>
+				called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352<br>
+				invalid mode value encountered 0<br>
+				cpsr contains invalid mode value - communication failure<br>
+				ThumbEE -- incomplete support<br>
+				target state: halted<br>
+				target halted in ThumbEE state due to debug-request, current mode: System<br>
+				cpsr: 0x1fffffff pc: 0xfffffffa<br>
+				invalid mode value encountered 0<br>
+				cpsr contains invalid mode value - communication failure<br>
+				target state: halted<br>
+				target halted in Thumb state due to debug-request, current mode: System<br>
+				cpsr: 0xc00003ff pc: 0xfffffff0<br>
+				invalid mode value encountered 0<br>
+				cpsr contains invalid mode value - communication failure<br>
+				invalid mode value encountered 0<br>
+				cpsr contains invalid mode value - communication failure<br>
+				invalid mode value encountered 0<br>
+				cpsr contains invalid mode value - communication failure<br>
+				invalid mode value encountered 0<br>
+				cpsr contains invalid mode value - communication failure<br>
+				ThumbEE -- incomplete support<br>
+				target state: halted<br>
+				target halted in ThumbEE state due to debug-request, current mode: System<br>
+				cpsr: 0xffffffff pc: 0xfffffffa<br>
+				>
+			</code>
+		</td>
+		<td><font color=red><b>FAIL</b></font></td>	
+	</tr>
+	<tr>
+		<td><a name="SPD002"/>SPD002</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>8MHz on normal operation</td>
+		<td>Reset init the target according to RES002 </td>
+		<td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
+		<td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
+		<td>
+			<code>
+				> jtag_khz 8000<br> 
+				jtag_speed 8 => JTAG clk=8.000000<br>
+				8000 kHz<br>
+				> reset halt<br>   
+				JTAG scan chain interrogation failed: all zeroes<br>
+				Check JTAG interface, timings, target power, etc.<br>
+				error: -100<br>
+				Command handler execution failed<br>
+				in procedure 'reset' called at file "command.c", line 638<br>
+				called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352<br>
+				invalid mode value encountered 0<br>
+				cpsr contains invalid mode value - communication failure<br>
+				invalid mode value encountered 0<br>
+				cpsr contains invalid mode value - communication failure<br>
+				>
+			</code>
+		</td>
+		<td><font color=red><b>FAIL</b></font></td>	
+	</tr>
+	<tr>
+		<td><a name="SPD003"/>SPD003</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>4MHz on normal operation</td>
+		<td>Reset init the target according to RES002 </td>
+		<td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
+		<td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
+		<td>
+			<code>
+				> jtag_khz 4000<br>
+				jtag_speed 16 => JTAG clk=4.000000<br>
+				4000 kHz<br>
+				> reset halt<br>   
+				JTAG tap: lpc2148.cpu tap/device found: 0xc79f0f87 (mfg: 0x7c3, part: 0x79f0, ver: 0xc)<br>
+				JTAG tap: lpc2148.cpu       UNEXPECTED: 0xc79f0f87 (mfg: 0x7c3, part: 0x79f0, ver: 0xc)<br>
+				JTAG tap: lpc2148.cpu  expected 1 of 1: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
+				Unexpected idcode after end of chain: 64 0x0000007f<br>
+				Unexpected idcode after end of chain: 160 0x0000007f<br>
+				Unexpected idcode after end of chain: 192 0x0000007f<br>
+				Unexpected idcode after end of chain: 320 0x0000007f<br>
+				Unexpected idcode after end of chain: 352 0x0000007f<br>
+				Unexpected idcode after end of chain: 384 0x0000007f<br>
+				Unexpected idcode after end of chain: 480 0x0000007f<br>
+				Unexpected idcode after end of chain: 512 0x0000007f<br>
+				Unexpected idcode after end of chain: 544 0x0000007f<br>
+				double-check your JTAG setup (interface, speed, missing TAPs, ...)<br>
+				error: -100<br>
+				Command handler execution failed<br>
+				in procedure 'reset' called at file "command.c", line 638<br>
+				called at file "/home/laurentiu/workspace/zy1000/build/../openocd/src/helper/command.c", line 352<br>
+				> 
+			</code>
+		</td>
+		<td><font color=red><b>FAIL</b></font></td>	
+	</tr>
+	<tr>
+		<td><a name="SPD004"/>SPD004</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>2MHz on normal operation</td>
+		<td>Reset init the target according to RES002 </td>
+		<td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
+		<td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
+		<td>
+			<code>
+				> jtag_khz 2000<br>
+				jtag_speed 32 => JTAG clk=2.000000<br>
+				2000 kHz<br>
+				> reset halt<br>
+				JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
+				srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+				target state: halted<br>
+				target halted in Thumb state due to debug-request, current mode: Supervisor<br>
+				cpsr: 0xa00000f3 pc: 0x7fffd2da<br>
+				> mdw 0 32<br>
+				0x00000000: e59f4034 e3a05002 e5845000 e3a05003 e5845004 e59f201c e3a03000 e1020093<br> 
+				0x00000020: e2822028 e1021093 e3c03007 e5023028 e51ff004 7fffd1c4 e002c014 e01fc000<br>
+				0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br> 
+				0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br> 
+				> 
+			</code>
+		</td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="SPD005"/>SPD005</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>RCLK on normal operation</td>
+		<td>Reset init the target according to RES002 </td>
+		<td>Change speed and exercise a memory access over the JTAG, for example <br><code>mdw 0x0 32</code></td>
+		<td>The command should run without any errors. If any JTAG checking errors happen, the test failed</td>
+		<td>
+			<code>
+				> jtag_khz 0<br>
+				RCLK - adaptive<br>
+				> mdw 0 32<br>
+				0x00000000: e59f4034 e3a05002 e5845000 e3a05003 e5845004 e59f201c e3a03000 e1020093<br> 
+				0x00000020: e2822028 e1021093 e3c03007 e5023028 e51ff004 7fffd1c4 e002c014 e01fc000<br> 
+				0x00000040: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br> 
+				0x00000060: ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff ffffffff<br> 
+				> 
+			</code>
+		</td>
+		<td>PASS</td>	
+	</tr>
+</table>
+
+<H2>Debugging</H2>
+<table border=1>
+	<tr>
+		<td>ID</td>
+		<td>Target</td>
+		<td>Interface</td>
+		<td>Description</td>
+		<td>Initial state</td>
+		<td>Input</td>
+		<td>Expected output</td>
+		<td>Actual output</td>
+		<td>Pass/Fail</td>
+	</tr>
+	<tr>
+		<td><a name="DBG001"/>DBG001</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>Load is working</td>
+		<td>Reset init is working, RAM is accesible, GDB server is started</td>
+		<td>On the console of the OS: <br>
+			<code>arm-elf-gdb test_ram.elf</code><br>
+			<code>(gdb) target remote ip:port</code><br>
+			<code>(gdb) load</load>
+		</td>
+		<td>Load should return without error, typical output looks like:<br>
+			<code>
+				Loading section .text, size 0x14c lma 0x0<br>
+				Start address 0x40, load size 332<br>
+				Transfer rate: 180 bytes/sec, 332 bytes/write.<br>
+			</code>
+		</td>
+		<td><code>
+			(gdb) load<br>
+			Loading section .text, size 0x16c lma 0x40000000<br>
+			Start address 0x40000040, load size 364<br>
+			Transfer rate: 32 KB/sec, 364 bytes/write.<br>
+			(gdb) 
+		</code></td>
+		<td>PASS</td>	
+	</tr>
+	
+	<tr>
+		<td><a name="DBG002"/>DBG002</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>Software breakpoint</td>
+		<td>Load the test_ram.elf application, use instructions from GDB001</td>
+		<td>In the GDB console:<br>
+			<code>
+				(gdb) monitor gdb_breakpoint_override soft<br>
+				software breakpoints enabled<br>
+				(gdb) break main<br>
+				Breakpoint 1 at 0xec: file src/main.c, line 71.<br>
+				(gdb) continue<br>
+				Continuing.
+			</code>
+		</td>
+		<td>The software breakpoint should be reached, a typical output looks like:<br>
+			<code>
+				target state: halted<br>
+				target halted in ARM state due to breakpoint, current mode: Supervisor<br>
+				cpsr: 0x000000d3 pc: 0x000000ec<br>
+				<br>
+				Breakpoint 1, main () at src/main.c:71<br>
+				71        DWORD a = 1;
+			</code>
+		</td>
+		<td>
+			<code>
+				(gdb) monitor gdb_breakpoint_override soft<br>
+				force soft breakpoints<br>
+				Current language:  auto<br>
+				The current source language is "auto; currently asm".<br>
+				(gdb) break main<br>
+				Breakpoint 1 at 0x4000010c: file src/main.c, line 71.<br>
+				(gdb) c<br>
+				Continuing.<br>
+				<br>
+				Breakpoint 1, main () at src/main.c:71<br>
+				71	  DWORD a = 1;<br>
+				Current language:  auto<br>
+				The current source language is "auto; currently c".<br>
+				(gdb) 
+			</code>
+		</td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="DBG003"/>DBG003</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>Single step in a RAM application</td>
+		<td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
+		<td>In GDB, type <br><code>(gdb) step</code></td>
+		<td>The next instruction should be reached, typical output:<br>
+			<code>
+				(gdb) step<br>
+				target state: halted<br>
+				target halted in ARM state due to single step, current mode: Abort<br>
+				cpsr: 0x20000097 pc: 0x000000f0<br>
+				target state: halted<br>
+				target halted in ARM state due to single step, current mode: Abort<br>
+				cpsr: 0x20000097 pc: 0x000000f4<br>
+				72        DWORD b = 2;
+			</code>
+		</td>
+		<td>
+			<code>
+				(gdb) step<br>
+				72	  DWORD b = 2;<br>
+				(gdb) 
+			</code>
+		</td>
+		<td>PASS</td>
+	</tr>
+	<tr>
+		<td><a name="DBG004"/>DBG004</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>Software break points are working after a reset</td>
+		<td>Load the test_ram.elf application, use instructions from GDB001, break in main using the instructions from GDB002</td>
+		<td>In GDB, type <br><code>
+			(gdb) monitor reset init<br>
+			(gdb) load<br>
+			(gdb) continue<br>
+			</code></td>
+		<td>The breakpoint should be reached, typical output:<br>
+			<code>
+				target state: halted<br>
+				target halted in ARM state due to breakpoint, current mode: Supervisor<br>
+				cpsr: 0x000000d3 pc: 0x000000ec<br>
+				<br>
+				Breakpoint 1, main () at src/main.c:71<br>
+				71        DWORD a = 1;
+			</code>
+		</td>
+		<td><code>
+			(gdb) moni reset init<br>
+			JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
+			srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+			target state: halted<br>
+			target halted in Thumb state due to debug-request, current mode: Supervisor<br>
+			cpsr: 0xa00000f3 pc: 0x7fffd2d6<br>
+			core state: ARM<br>
+			(gdb) load<br>
+			Loading section .text, size 0x16c lma 0x40000000<br>
+			Start address 0x40000040, load size 364<br>
+			Transfer rate: 27 KB/sec, 364 bytes/write.<br>
+			(gdb) c<br>
+			Continuing.<br>
+			<br>
+			Breakpoint 1, main () at src/main.c:71<br>
+			71	  DWORD a = 1;<br>
+			(gdb) 
+		</code></td>
+		<td>PASS</td>
+	</tr>
+	<tr>
+		<td><a name="DBG005"/>DBG005</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>Hardware breakpoint</td>
+		<td>Flash the test_rom.elf application. Make this test after FLA004 has passed</td>
+		<td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
+			<code>
+				(gdb) monitor reset init<br>
+				(gdb) load<br>
+				Loading section .text, size 0x194 lma 0x100000<br>
+				Start address 0x100040, load size 404<br>
+				Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
+				(gdb) monitor gdb_breakpoint_override hard<br>
+				force hard breakpoints<br>
+				(gdb) break main<br>
+				Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
+				(gdb) continue<br>
+			</code>
+		</td>
+		<td>The breakpoint should be reached, typical output:<br>
+			<code>
+				Continuing.<br>
+				<br>
+				Breakpoint 1, main () at src/main.c:69<br>
+				69        DWORD a = 1;<br>
+			</code>
+		</td>
+		<td>
+		<code>
+			(gdb) monitor gdb_breakpoint_override hard<br>
+			force hard breakpoints<br>
+			(gdb) break main<br>
+			Breakpoint 1 at 0x10c: file src/main.c, line 71.<br>
+			(gdb) continue<br>
+			Continuing.<br>
+			Note: automatically using hardware breakpoints for read-only addresses.<br>
+			<br>
+			Breakpoint 1, main () at src/main.c:71<br>
+			71	  DWORD a = 1;<br>
+			Current language:  auto<br>
+			The current source language is "auto; currently c".<br>
+			(gdb) 
+		</code>
+		</td>
+		<td>PASS <font color=red>NOTE: This test is failing from time to time, not able to describe a cause</font></td>
+	</tr>
+	<tr>
+		<td><a name="DBG006"/>DBG006</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>Hardware breakpoint is set after a reset</td>
+		<td>Follow the instructions to flash and insert a hardware breakpoint from DBG005</td>
+		<td>In GDB, type <br>
+			<code>
+				(gdb) monitor reset<br>
+				(gdb) monitor reg pc 0x100000<br>
+				pc (/32): 0x00100000<br>
+				(gdb) continue
+			</code><br>
+			where the value inserted in PC is the start address of the application
+		</td>
+		<td>The breakpoint should be reached, typical output:<br>
+			<code>
+				Continuing.<br>
+				<br>
+				Breakpoint 1, main () at src/main.c:69<br>
+				69        DWORD a = 1;<br>
+			</code>
+		</td>
+		<td>
+		<code>
+			(gdb) monitor reset init<br>
+			JTAG tap: lpc2148.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787, part: 0xf1f0, ver: 0x4)<br>
+			srst pulls trst - can not reset into halted mode. Issuing halt after reset.<br>
+			target state: halted<br>
+			target halted in ARM state due to debug-request, current mode: Supervisor<br>
+			cpsr: 0x60000013 pc: 0x00000160<br>
+			core state: ARM<br>
+			(gdb) monitor reg pc 0x40<br>
+			pc (/32): 0x00000040<br>
+			(gdb) continue<br>
+			Continuing.<br>
+			<br>
+			Breakpoint 1, main () at src/main.c:71<br>
+			71	  DWORD a = 1;<br>
+			(gdb) 
+		</code>
+		</td>
+		<td>PASS</td>
+	</tr>
+	<tr>
+		<td><a name="DBG007"/>DBG007</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>Single step in ROM</td>
+		<td>Flash the test_rom.elf application and set a breakpoint in main, use DBG005. Make this test after FLA004 has passed</td>
+		<td>Be sure that <code>gdb_memory_map</code> and <code>gdb_flash_program</code> are enabled. In GDB, type <br>
+			<code>
+				(gdb) monitor reset<br>
+				(gdb) load<br>
+				Loading section .text, size 0x194 lma 0x100000<br>
+				Start address 0x100040, load size 404<br>
+				Transfer rate: 179 bytes/sec, 404 bytes/write.<br>
+				(gdb) monitor gdb_breakpoint_override hard<br>
+				force hard breakpoints<br>
+				(gdb) break main<br>
+				Breakpoint 1 at 0x100134: file src/main.c, line 69.<br>
+				(gdb) continue<br>
+				Continuing.<br>
+				<br>
+				Breakpoint 1, main () at src/main.c:69<br>
+				69        DWORD a = 1;<br>
+				(gdb) step
+			</code>
+		</td>
+		<td>The breakpoint should be reached, typical output:<br>
+			<code>
+				target state: halted<br>
+				target halted in ARM state due to single step, current mode: Supervisor<br>
+				cpsr: 0x60000013 pc: 0x0010013c<br>
+				70        DWORD b = 2;<br>
+			</code>
+		</td>
+		<td><code>
+				(gdb) load<br>
+				Loading section .text, size 0x16c lma 0x0<br>
+				Start address 0x40, load size 364<br>
+				Transfer rate: 637 bytes/sec, 364 bytes/write.<br>
+				(gdb)  monitor gdb_breakpoint_override hard<br>
+				force hard breakpoints<br>
+				Current language:  auto<br>
+				The current source language is "auto; currently asm".<br>
+				(gdb) break main<br>
+				Breakpoint 1 at 0x10c: file src/main.c, line 71.<br>
+				(gdb) continue<br>
+				Continuing.<br>
+				Note: automatically using hardware breakpoints for read-only addresses.<br>
+				<br>
+				Breakpoint 1, main () at src/main.c:71<br>
+				71	  DWORD a = 1;<br>
+				Current language:  auto<br>
+				The current source language is "auto; currently c".<br>
+				(gdb) step<br>
+				72	  DWORD b = 2;<br>
+				(gdb)
+			
+		</code></td>
+		<td>PASS</td>
+	</tr>
+</table>
+
+<H2>RAM access</H2>
+Note: these tests are not designed to test/debug the target, but to test functionalities!
+<table border=1>
+	<tr>
+		<td>ID</td>
+		<td>Target</td>
+		<td>Interface</td>
+		<td>Description</td>
+		<td>Initial state</td>
+		<td>Input</td>
+		<td>Expected output</td>
+		<td>Actual output</td>
+		<td>Pass/Fail</td>
+	</tr>
+	<tr>
+		<td><a name="RAM001"/>RAM001</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>32 bit Write/read RAM</td>
+		<td>Reset init is working</td>
+		<td>On the telnet interface<br>
+			<code>	> mww ram_address 0xdeadbeef 16<br>
+					> mdw ram_address 32
+			</code>
+		</td>
+		<td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 32bit long containing 0xdeadbeef.<br>
+			<code>
+				> mww 0x0 0xdeadbeef 16<br>
+				> mdw 0x0 32<br>
+				0x00000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+				0x00000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+				0x00000040: e1a00000 e59fa51c e59f051c e04aa000 00080017 00009388 00009388 00009388<br>
+				0x00000060: 00009388 0002c2c0 0002c2c0 000094f8 000094f4 00009388 00009388 00009388<br>
+			</code>
+		</td>
+		<td><code>
+			> mww 0x40000000 0xdeadbeef 16<br>
+			> mdw 0x40000000 32<br>
+			0x40000000: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br> 
+			0x40000020: deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef deadbeef<br>
+			0x40000040: e1a00000 e1a00000 e1a00000 e1a00000 e1a00000 e1a00000 e1a00000 e1a00000<br> 
+			0x40000060: e321f0db e59fd07c e321f0d7 e59fd078 e321f0d1 e59fd074 e321f0d2 e59fd070<br> 
+			> 
+		</code></td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="RAM002"/>RAM002</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>16 bit Write/read RAM</td>
+		<td>Reset init is working</td>
+		<td>On the telnet interface<br>
+			<code>	> mwh ram_address 0xbeef 16<br>
+					> mdh ram_address 32
+			</code>
+		</td>
+		<td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 16bit long containing 0xbeef.<br>
+			<code>
+				> mwh 0x0 0xbeef 16<br>
+				> mdh 0x0 32<br>
+				0x00000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br>
+				0x00000020: 00e0 0000 021c 0000 0240 0000 026c 0000 0288 0000 0000 0000 0388 0000 0350 0000<br>
+				>
+			</code>
+		</td>
+		<td><code>
+			> mwh 0x40000000 0xbeef 16<br>
+			> mdh 0x40000000 32<br>       
+			0x40000000: beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef beef<br> 
+			0x40000020: beef dead beef dead beef dead beef dead beef dead beef dead beef dead beef dead<br> 
+			> 
+		</code></td>
+		<td>PASS</td>	
+	</tr>
+	<tr>
+		<td><a name="RAM003"/>RAM003</td>
+		<td>LPC2148</td>
+		<td>ZY1000</td>
+		<td>8 bit Write/read RAM</td>
+		<td>Reset init is working</td>
+		<td>On the telnet interface<br>
+			<code>	> mwb ram_address 0xab 16<br>
+					> mdb ram_address 32
+			</code>
+		</td>
+		<td>The commands should execute without error. A clear failure is a memory access exception. The result of running the commands should be a list of 16 locations 8bit long containing 0xab.<br>
+			<code>
+				> mwb ram_address 0xab 16<br>
+				> mdb ram_address 32<br>
+				0x00000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00<br>
+				>
+			</code>
+		</td>
+		<td><code>
+			> mwb 0x40000000 0xab 16
+			> mdb 0x40000000 32     
+			0x40000000: ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ab ef be ef be ef be ef be ef be ef be ef be ef be 
+			>
+
+		</code></td>
+		<td>PASS</td>	
+	</tr>
+</table>
+
+
+
+<H2>Flash access</H2>
+<table border=1>
+	<tr>
+		<td>ID</td>
+		<td>Target</td>
+		<td>Interface</td>
+		<td>Description</td>
+		<td>Initial state</td>
+		<td>Input</td>
+		<td>Expected output</td>
+		<td>Actual output</td>
+		<td>Pass/...
 
[truncated message content]

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-169-g91e3268

From: Øyvind H. <go...@us...> - 2010-02-01 13:44:47

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  91e3268737b578a182cb661d60551657f799ab3c (commit)
      from  82f2492138e053d5e3577e83b80cab8d41c0d08b (commit)

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not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 91e3268737b578a182cb661d60551657f799ab3c
Author: Ãyvind Harboe <oyv...@zy...>
Date:   Sun Jan 31 21:02:06 2010 +0100

    gdb: restore behavior from 0.3.1 for srst_asserted and power_restore
    
    srst_asserted and power_restore can now be overriden to do
    nothing. By default they will "reset init" the targets and
    halt gdb.
    
    Signed-off-by: Ãyvind Harboe <oyv...@zy...>

diff --git a/src/jtag/startup.tcl b/src/jtag/startup.tcl
index ab215ba..4e6d5fc 100644
--- a/src/jtag/startup.tcl
+++ b/src/jtag/startup.tcl
@@ -30,8 +30,18 @@ proc init_reset { mode } {
 # documented nor supported except on ZY1000.
 
 proc power_restore {} {
-	puts "Sensed power restore."
+	puts "Sensed power restore, running reset init and halting GDB."
 	reset init
+	
+	# Halt GDB so user can deal with a detected power restore.
+	#
+	# After GDB is halted, then output is no longer forwarded
+	# to the GDB console.
+	set targets [target names]	
+	foreach t $targets {
+		# New event script.
+		$t invoke-event arp_halt_gdb
+	}	
 }
 
 add_help_text power_restore "Overridable procedure run when power restore is detected. Runs 'reset init' by default."
@@ -46,9 +56,20 @@ proc power_dropout {} {
 # documented nor supported except on ZY1000.
 
 proc srst_deasserted {} {
-	puts "Sensed nSRST deasserted."
+	puts "Sensed nSRST deasserted, running reset init and halting GDB."
 	reset init
+
+	# Halt GDB so user can deal with a detected reset.
+	#
+	# After GDB is halted, then output is no longer forwarded
+	# to the GDB console.
+	set targets [target names]	
+	foreach t $targets {
+		# New event script.
+		$t invoke-event arp_halt_gdb
+	}		
 }
+
 add_help_text srst_deasserted "Overridable procedure run when srst deassert is detected. Runs 'reset init' by default."
 
 proc srst_asserted {} {
diff --git a/src/target/target.c b/src/target/target.c
index 1eb65a6..2522408 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -1739,15 +1739,6 @@ static int sense_handler(void)
 	return ERROR_OK;
 }
 
-static void target_call_event_callbacks_all(enum target_event e) {
-	struct target *target;
-	target = all_targets;
-	while (target) {
-		target_call_event_callbacks(target, e);
-		target = target->next;
-	}
-}
-
 /* process target state changes */
 static int handle_target(void *priv)
 {
@@ -1767,8 +1758,7 @@ static int handle_target(void *priv)
 		int did_something = 0;
 		if (runSrstAsserted)
 		{
-			LOG_INFO("Waking up GDB, srst asserted detected.");
-			target_call_event_callbacks_all(TARGET_EVENT_GDB_HALT);
+			LOG_INFO("srst asserted detected, running srst_asserted proc.");
 			Jim_Eval(interp, "srst_asserted");
 			did_something = 1;
 		}
@@ -1779,8 +1769,7 @@ static int handle_target(void *priv)
 		}
 		if (runPowerDropout)
 		{
-			LOG_INFO("Waking up GDB, power dropout detected.");
-			target_call_event_callbacks_all(TARGET_EVENT_GDB_HALT);
+			LOG_INFO("Power dropout detected, running power_dropout proc.");
 			Jim_Eval(interp, "power_dropout");
 			did_something = 1;
 		}
@@ -4065,6 +4054,21 @@ static int jim_target_examine(Jim_Interp *interp, int argc, Jim_Obj *const *argv
 	return JIM_OK;
 }
 
+static int jim_target_halt_gdb(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
+{
+	if (argc != 1)
+	{
+		Jim_WrongNumArgs(interp, 1, argv, "[no parameters]");
+		return JIM_ERR;
+	}
+	struct target *target = Jim_CmdPrivData(interp);
+
+	if (target_call_event_callbacks(target, TARGET_EVENT_GDB_HALT) != ERROR_OK)
+		return JIM_ERR;
+
+	return JIM_OK;
+}
+
 static int jim_target_poll(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 {
 	if (argc != 1)
@@ -4346,6 +4350,12 @@ static const struct command_registration target_instance_command_handlers[] = {
 		.help = "used internally for reset processing",
 	},
 	{
+		.name = "arp_halt_gdb",
+		.mode = COMMAND_EXEC,
+		.jim_handler = jim_target_halt_gdb,
+		.help = "used internally for reset processing to halt GDB",
+	},
+	{
 		.name = "arp_poll",
 		.mode = COMMAND_EXEC,
 		.jim_handler = jim_target_poll,

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/startup.tcl |   25 +++++++++++++++++++++++--
 src/target/target.c  |   36 +++++++++++++++++++++++-------------
 2 files changed, 46 insertions(+), 15 deletions(-)


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From: David B. <dbr...@us...> - 2010-02-01 01:55:33

This is an automated email from the git hooks/post-receive script. It was
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- Log -----------------------------------------------------------------
commit 82f2492138e053d5e3577e83b80cab8d41c0d08b
Author: David Brownell <dbr...@us...>
Date:   Sun Jan 31 14:16:53 2010 -0800

    ADIv5: more messaging cleanup, docs
    
    When the TAR cache was explicitly invalidated, don't bother
    printing it; the actual hardware status is more informative.
    
    Provide some doxygen for the MEM-AP setup routine.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index bfa5cb4..4089567 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -334,7 +334,10 @@ int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
 		{
 			uint32_t mem_ap_csw, mem_ap_tar;
 
-			/* Maybe print information about last MEM-AP access */
+			/* Maybe print information about last intended
+			 * MEM-AP access; but not if autoincrementing.
+			 * *Real* CSW and TAR values are always shown.
+			 */
 			if (swjdp->ap_tar_value != (uint32_t) -1)
 				LOG_DEBUG("MEM-AP Cached values: "
 					"ap_bank 0x%" PRIx32
@@ -343,8 +346,6 @@ int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
 					swjdp->dp_select_value,
 					swjdp->ap_csw_value,
 					swjdp->ap_tar_value);
-			else
-				LOG_ERROR("Invalid MEM-AP TAR cache!");
 
 			if (ctrlstat & SSTICKYORUN)
 				LOG_ERROR("JTAG-DP OVERRUN - check clock, "
@@ -463,12 +464,21 @@ int dap_ap_read_reg_u32(struct swjdp_common *swjdp, uint32_t reg_addr, uint32_t
 	return ERROR_OK;
 }
 
-/***************************************************************************
- *                                                                         *
- * AHB-AP access to memory and system registers on AHB bus                 *
- *                                                                         *
-***************************************************************************/
-
+/**
+ * Set up transfer parameters for the currently selected MEM-AP.
+ * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
+ * initiate data reads or writes using memory or peripheral addresses.
+ * If the CSW is configured for it, the TAR may be automatically
+ * incremented after each transfer.
+ *
+ * @todo Rename to reflect it being specifically a MEM-AP function.
+ *
+ * @param swjdp The DAP connected to the MEM-AP.
+ * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
+ *	matches the cached value, the register is not changed.
+ * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
+ *	matches the cached address, the register is not changed.
+ */
 int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 {
 	csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
@@ -484,11 +494,9 @@ int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 		dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
 		swjdp->ap_tar_value = tar;
 	}
+	/* Disable TAR cache when autoincrementing */
 	if (csw & CSW_ADDRINC_MASK)
-	{
-		/* Do not cache TAR value when autoincrementing */
 		swjdp->ap_tar_value = -1;
-	}
 	return ERROR_OK;
 }
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_adi_v5.c |   32 ++++++++++++++++++++------------
 1 files changed, 20 insertions(+), 12 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-167-g02731cf

From: Øyvind H. <go...@us...> - 2010-01-31 19:31:26

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
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      from  f68dff66904321392c3137db7eb40e8633c2e507 (commit)

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- Log -----------------------------------------------------------------
commit 02731cf78b3663739e3755295a4239f2658a3fdc
Author: Ãyvind Harboe <oyv...@zy...>
Date:   Sun Jan 31 15:48:14 2010 +0100

    build: fix problems with "struct stat" not being defined under eCos
    
    Include <sys/stat.h> according to
    http://www.opengroup.org/onlinepubs/000095399/functions/stat.html
    
    Signed-off-by: Ãyvind Harboe <oyv...@zy...>

diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index 8db60a5..c41c5a0 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -43,6 +43,7 @@
 #include "arm_semihosting.h"
 #include <helper/binarybuffer.h>
 #include <helper/log.h>
+#include <sys/stat.h>
 
 static int open_modeflags[12] = {
 	O_RDONLY,

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_semihosting.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)


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From: Øyvind H. <go...@us...> - 2010-01-31 15:18:13

This is an automated email from the git hooks/post-receive script. It was
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- Log -----------------------------------------------------------------
commit f68dff66904321392c3137db7eb40e8633c2e507
Author: Ãyvind Harboe <oyv...@zy...>
Date:   Thu Jan 21 16:41:54 2010 +0100

    telnet: fix strage blank spaces at beginning of telnet lines
    
    Sometimes we saw two strange blank spaces at the beginning
    of the telnet lines.
    
    progress
      ogress
    >
    
    This patch fixes this problem:
    
    progress
    progress
    >
    
    The code changes are *reasonably* clean, but perhaps it could be
    made a bit more elegant, but I didn't want to change things after
    I finished diagnosis/testing & submitting the patch.
    
    The problem was that logging can send the text and the newline
    separately in two different requests and the telnet code would
    incorrectly remove the prompt from the end of a line.
    
    Signed-off-by: Ãyvind Harboe <oyv...@zy...>

diff --git a/src/server/telnet_server.c b/src/server/telnet_server.c
index 6f26f0a..94c8943 100644
--- a/src/server/telnet_server.c
+++ b/src/server/telnet_server.c
@@ -62,7 +62,6 @@ int telnet_prompt(struct connection *connection)
 {
 	struct telnet_connection *t_con = connection->priv;
 
-	telnet_write(connection, "\r", 1); /* the prompt is always placed at the line beginning */
 	return telnet_write(connection, t_con->prompt, strlen(t_con->prompt));
 }
 
@@ -116,10 +115,12 @@ void telnet_log_callback(void *priv, const char *file, unsigned line,
 	}
 
 	/* clear the command line */
-	telnet_write(connection, "\r", 1);
+	for (i = strlen(t_con->prompt) + t_con->line_size; i > 0; i -= 16)
+		telnet_write(connection, "\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b", i > 16 ? 16 : i);
 	for (i = strlen(t_con->prompt) + t_con->line_size; i > 0; i -= 16)
 		telnet_write(connection, "                ", i > 16 ? 16 : i);
-	telnet_write(connection, "\r", 1);
+	for (i = strlen(t_con->prompt) + t_con->line_size; i > 0; i -= 16)
+		telnet_write(connection, "\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b\b", i > 16 ? 16 : i);
 
 	/* output the message */
 	telnet_outputline(connection, string);
@@ -160,6 +161,7 @@ int telnet_new_connection(struct connection *connection)
 		telnet_write(connection, "\r\n", 2);
 	}
 
+	telnet_write(connection, "\r", 1); /* the prompt is always placed at the line beginning */
 	telnet_prompt(connection);
 
 	/* initialize history */
@@ -331,6 +333,7 @@ int telnet_input(struct connection *connection)
 							if (retval == ERROR_COMMAND_CLOSE_CONNECTION)
 								return ERROR_SERVER_REMOTE_CLOSED;
 
+							telnet_write(connection, "\r", 1); /* the prompt is always placed at the line beginning */
 							retval = telnet_prompt(connection);
 							if (retval == ERROR_SERVER_REMOTE_CLOSED)
 								return ERROR_SERVER_REMOTE_CLOSED;

-----------------------------------------------------------------------

Summary of changes:
 src/server/telnet_server.c |    9 ++++++---
 1 files changed, 6 insertions(+), 3 deletions(-)


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From: David B. <dbr...@us...> - 2010-01-31 09:59:48

This is an automated email from the git hooks/post-receive script. It was
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       via  695666d294e7d572bc5799e0cef4fc384b28c733 (commit)
       via  46b6d5bfe644b5f6a1fe50930c850f09a78b5bad (commit)
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- Log -----------------------------------------------------------------
commit e11ce3e6b00f02eba9a15673a54f5345eba8398b
Author: David Brownell <dbr...@us...>
Date:   Sun Jan 31 00:26:21 2010 -0800

    Subject: ADIv5: fix more diagnostics
    
    If the MEM-AP cache is invalid, don't display it; just report that
    invalidity as an error.  (This bug has been observed with "mdw 0 32"
    after just a "reset halt".  Some code is being wrongly bypassed...)
    
    If it's valid, display that cache at DEBUG level, not ERROR.  Also,
    don't assume it's an AHB-AP; it could be another flavor of MEM-AP.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 0e3b349..bfa5cb4 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -321,27 +321,34 @@ int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
 		}
 	}
 
+	/* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
+
 	/* Check for STICKYERR and STICKYORUN */
 	if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
 	{
 		LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
 		/* Check power to debug regions */
 		if ((ctrlstat & 0xf0000000) != 0xf0000000)
-		{
 			 ahbap_debugport_init(swjdp);
-		}
 		else
 		{
 			uint32_t mem_ap_csw, mem_ap_tar;
 
-			/* Print information about last AHBAP access */
-			LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32
-				", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32,
-				swjdp->dp_select_value, swjdp->ap_csw_value,
-				swjdp->ap_tar_value);
+			/* Maybe print information about last MEM-AP access */
+			if (swjdp->ap_tar_value != (uint32_t) -1)
+				LOG_DEBUG("MEM-AP Cached values: "
+					"ap_bank 0x%" PRIx32
+					", ap_csw 0x%" PRIx32
+					", ap_tar 0x%" PRIx32,
+					swjdp->dp_select_value,
+					swjdp->ap_csw_value,
+					swjdp->ap_tar_value);
+			else
+				LOG_ERROR("Invalid MEM-AP TAR cache!");
+
 			if (ctrlstat & SSTICKYORUN)
-				LOG_ERROR("JTAG-DP OVERRUN - "
-					"check clock or reduce jtag speed");
+				LOG_ERROR("JTAG-DP OVERRUN - check clock, "
+					"memaccess, or reduce jtag speed");
 
 			if (ctrlstat & SSTICKYERR)
 				LOG_ERROR("JTAG-DP STICKY ERROR");

commit 695666d294e7d572bc5799e0cef4fc384b28c733
Author: David Brownell <dbr...@us...>
Date:   Sat Jan 30 22:40:50 2010 -0800

    ADIv5 error checking for Tcl commands
    
    Reject invalid AP numbers (256+) as Tcl operation parameters.
    Shrink one of the overlong lines.
    
    Add my copyright to the ADIv5 code (multiple contributions).
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 0a6a7ef..0e3b349 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -8,6 +8,8 @@
  *   Copyright (C) 2009 by Oyvind Harboe                                   *
  *   oyv...@zy...                                               *
  *                                                                         *
+ *   Copyright (C) 2009-2010 by David Brownell                             *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -1164,7 +1166,8 @@ is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
 			&& ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
 }
 
-int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp, int apsel)
+int dap_info_command(struct command_context *cmd_ctx,
+		struct swjdp_common *swjdp, int apsel)
 {
 
 	uint32_t dbgbase, apid;
@@ -1172,6 +1175,10 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp
 	uint8_t mem_ap;
 	uint32_t apselold;
 
+	/* AP address is in bits 31:24 of DP_SELECT */
+	if (apsel >= 256)
+		return ERROR_INVALID_ARGUMENTS;
+
 	apselold = swjdp->apsel;
 	dap_ap_select(swjdp, apsel);
 	dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
@@ -1524,6 +1531,9 @@ DAP_COMMAND_HANDLER(dap_baseaddr_command)
 		break;
 	case 1:
 		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
+		/* AP address is in bits 31:24 of DP_SELECT */
+		if (apsel >= 256)
+			return ERROR_INVALID_ARGUMENTS;
 		break;
 	default:
 		return ERROR_COMMAND_SYNTAX_ERROR;
@@ -1580,6 +1590,9 @@ DAP_COMMAND_HANDLER(dap_apsel_command)
 		break;
 	case 1:
 		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
+		/* AP address is in bits 31:24 of DP_SELECT */
+		if (apsel >= 256)
+			return ERROR_INVALID_ARGUMENTS;
 		break;
 	default:
 		return ERROR_COMMAND_SYNTAX_ERROR;
@@ -1606,6 +1619,9 @@ DAP_COMMAND_HANDLER(dap_apid_command)
 		break;
 	case 1:
 		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
+		/* AP address is in bits 31:24 of DP_SELECT */
+		if (apsel >= 256)
+			return ERROR_INVALID_ARGUMENTS;
 		break;
 	default:
 		return ERROR_COMMAND_SYNTAX_ERROR;

commit 46b6d5bfe644b5f6a1fe50930c850f09a78b5bad
Author: David Brownell <dbr...@us...>
Date:   Sat Jan 30 18:08:19 2010 -0800

    ARM ADIv5: fix diagnostics for block writes
    
    They were reporting "read" errors, not "write" errors.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index b8744d5..0a6a7ef 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -641,9 +641,12 @@ static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
 
 			if (nbytes < 4)
 			{
-				if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
+				if (mem_ap_write_buf_u16(swjdp, buffer,
+						nbytes, address) != ERROR_OK)
 				{
-					LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
+					LOG_WARNING("Block write error address "
+						"0x%" PRIx32 ", count 0x%x",
+						address, count);
 					return ERROR_JTAG_DEVICE_ERROR;
 				}
 
@@ -665,7 +668,9 @@ static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
 				dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 				if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 				{
-					LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
+					LOG_WARNING("Block write error address "
+						"0x%" PRIx32 ", count 0x%x",
+						address, count);
 					return ERROR_JTAG_DEVICE_ERROR;
 				}
 			}
@@ -736,7 +741,9 @@ static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
 			{
 				if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
 				{
-					LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
+					LOG_WARNING("Block write error address "
+						"0x%" PRIx32 ", count 0x%x",
+						address, count);
 					return ERROR_JTAG_DEVICE_ERROR;
 				}
 
@@ -758,7 +765,9 @@ static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
 				dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 				if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 				{
-					LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
+					LOG_WARNING("Block write error address "
+						"0x%" PRIx32 ", count 0x%x",
+						address, count);
 					return ERROR_JTAG_DEVICE_ERROR;
 				}
 			}

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_adi_v5.c |   62 +++++++++++++++++++++++++++++++++++-----------
 1 files changed, 47 insertions(+), 15 deletions(-)


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From: David B. <dbr...@us...> - 2010-01-30 00:25:20

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- Log -----------------------------------------------------------------
commit 3d3128a8f5bb15f1d05ac5eb7ecc5e692ae290ce
Author: David Brownell <dbr...@us...>
Date:   Fri Jan 29 14:31:19 2010 -0800

    ADIv5: cleanup, rename swjdp_transaction_endcheck()
    
    Make messages reference "DAP" if they're actually transport-agnostic, or
    "JTAG-DP" when they're JTAG-specific.  Saying SWJ-DP is often wrong (on
    most Cortex-A8 chips) and is confusing even if correct (since we don't
    yet support SWD).
    
    Rename a JTAG-specific routine to jtagdp_transaction_endcheck() to highlight
    that it's JTAG-specific, and that identify DAP clients undesirably depending
    on JTAG.  (They will all need to change for SWD support.)
    
    Shrink a few overlong lines of code.  Copy a comment from code removed
    in a previous patch (for the ARMv7-M "dap baseaddr" command).
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 2ba89e5..b8744d5 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -220,7 +220,7 @@ static int scan_inout_check(struct swjdp_common *swjdp,
 	 */
 	if ((instr == JTAG_DP_APACC)
 			&& (swjdp->trans_mode == TRANS_MODE_ATOMIC))
-		return swjdp_transaction_endcheck(swjdp);
+		return jtagdp_transaction_endcheck(swjdp);
 
 	return ERROR_OK;
 }
@@ -244,12 +244,12 @@ static int scan_inout_check_u32(struct swjdp_common *swjdp,
 	 */
 	if ((instr == JTAG_DP_APACC)
 			&& (swjdp->trans_mode == TRANS_MODE_ATOMIC))
-		return swjdp_transaction_endcheck(swjdp);
+		return jtagdp_transaction_endcheck(swjdp);
 
 	return ERROR_OK;
 }
 
-int swjdp_transaction_endcheck(struct swjdp_common *swjdp)
+int jtagdp_transaction_endcheck(struct swjdp_common *swjdp)
 {
 	int retval;
 	uint32_t ctrlstat;
@@ -322,7 +322,7 @@ int swjdp_transaction_endcheck(struct swjdp_common *swjdp)
 	/* Check for STICKYERR and STICKYORUN */
 	if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
 	{
-		LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat);
+		LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
 		/* Check power to debug regions */
 		if ((ctrlstat & 0xf0000000) != 0xf0000000)
 		{
@@ -333,7 +333,10 @@ int swjdp_transaction_endcheck(struct swjdp_common *swjdp)
 			uint32_t mem_ap_csw, mem_ap_tar;
 
 			/* Print information about last AHBAP access */
-			LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
+			LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32
+				", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32,
+				swjdp->dp_select_value, swjdp->ap_csw_value,
+				swjdp->ap_tar_value);
 			if (ctrlstat & SSTICKYORUN)
 				LOG_ERROR("JTAG-DP OVERRUN - "
 					"check clock or reduce jtag speed");
@@ -351,13 +354,14 @@ int swjdp_transaction_endcheck(struct swjdp_common *swjdp)
 			if ((retval = jtag_execute_queue()) != ERROR_OK)
 				return retval;
 
-			LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
+			LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
 
 			dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
 			dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
 			if ((retval = jtag_execute_queue()) != ERROR_OK)
 				return retval;
-			LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
+			LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
+					PRIx32, mem_ap_csw, mem_ap_tar);
 
 		}
 		if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -461,13 +465,13 @@ int dap_setup_accessport(struct swjdp_common *swjdp, uint32_t csw, uint32_t tar)
 	csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
 	if (csw != swjdp->ap_csw_value)
 	{
-		/* LOG_DEBUG("swjdp : Set CSW %x",csw); */
+		/* LOG_DEBUG("DAP: Set CSW %x",csw); */
 		dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw);
 		swjdp->ap_csw_value = csw;
 	}
 	if (tar != swjdp->ap_tar_value)
 	{
-		/* LOG_DEBUG("swjdp : Set TAR %x",tar); */
+		/* LOG_DEBUG("DAP: Set TAR %x",tar); */
 		dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar);
 		swjdp->ap_tar_value = tar;
 	}
@@ -501,7 +505,7 @@ int mem_ap_read_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32_
 {
 	mem_ap_read_u32(swjdp, address, value);
 
-	return swjdp_transaction_endcheck(swjdp);
+	return jtagdp_transaction_endcheck(swjdp);
 }
 
 /*****************************************************************************
@@ -525,7 +529,7 @@ int mem_ap_write_atomic_u32(struct swjdp_common *swjdp, uint32_t address, uint32
 {
 	mem_ap_write_u32(swjdp, address, value);
 
-	return swjdp_transaction_endcheck(swjdp);
+	return jtagdp_transaction_endcheck(swjdp);
 }
 
 /*****************************************************************************
@@ -583,7 +587,7 @@ int mem_ap_write_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count,
 			dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount);
 		}
 
-		if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
+		if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
 		{
 			wcount = wcount - blocksize;
 			address = address + 4 * blocksize;
@@ -659,7 +663,7 @@ static int mem_ap_write_buf_packed_u16(struct swjdp_common *swjdp,
 
 				memcpy(&outvalue, buffer, sizeof(uint32_t));
 				dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
-				if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+				if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 				{
 					LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 					return ERROR_JTAG_DEVICE_ERROR;
@@ -692,7 +696,7 @@ int mem_ap_write_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count,
 		memcpy(&svalue, buffer, sizeof(uint16_t));
 		uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
 		dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
-		retval = swjdp_transaction_endcheck(swjdp);
+		retval = jtagdp_transaction_endcheck(swjdp);
 		count -= 2;
 		address += 2;
 		buffer += 2;
@@ -752,7 +756,7 @@ static int mem_ap_write_buf_packed_u8(struct swjdp_common *swjdp,
 
 				memcpy(&outvalue, buffer, sizeof(uint32_t));
 				dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
-				if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+				if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 				{
 					LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 					return ERROR_JTAG_DEVICE_ERROR;
@@ -783,7 +787,7 @@ int mem_ap_write_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count,
 		dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 		uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
 		dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
-		retval = swjdp_transaction_endcheck(swjdp);
+		retval = jtagdp_transaction_endcheck(swjdp);
 		count--;
 		address++;
 		buffer++;
@@ -843,7 +847,7 @@ int mem_ap_read_buf_u32(struct swjdp_common *swjdp, uint8_t *buffer, int count,
 		adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
 				DPAP_READ, 0, buffer + 4 * readcount,
 				&swjdp->ack);
-		if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
+		if (jtagdp_transaction_endcheck(swjdp) == ERROR_OK)
 		{
 			wcount = wcount - blocksize;
 			address += 4 * blocksize;
@@ -912,7 +916,7 @@ static int mem_ap_read_buf_packed_u16(struct swjdp_common *swjdp,
 		do
 		{
 			dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
-			if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+			if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 			{
 				LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 				return ERROR_JTAG_DEVICE_ERROR;
@@ -949,7 +953,7 @@ int mem_ap_read_buf_u16(struct swjdp_common *swjdp, uint8_t *buffer, int count,
 	{
 		dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 		dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
-		retval = swjdp_transaction_endcheck(swjdp);
+		retval = jtagdp_transaction_endcheck(swjdp);
 		if (address & 0x1)
 		{
 			for (i = 0; i < 2; i++)
@@ -1005,7 +1009,7 @@ static int mem_ap_read_buf_packed_u8(struct swjdp_common *swjdp,
 		do
 		{
 			dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
-			if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+			if (jtagdp_transaction_endcheck(swjdp) != ERROR_OK)
 			{
 				LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 				return ERROR_JTAG_DEVICE_ERROR;
@@ -1042,7 +1046,7 @@ int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, u
 	{
 		dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 		dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue);
-		retval = swjdp_transaction_endcheck(swjdp);
+		retval = jtagdp_transaction_endcheck(swjdp);
 		*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
 		count--;
 		address++;
@@ -1095,7 +1099,7 @@ int ahbap_debugport_init(struct swjdp_common *swjdp)
 	/* Check that we have debug power domains activated */
 	while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
 	{
-		LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
+		LOG_DEBUG("DAP: wait CDBGPWRUPACK");
 		dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
 		if ((retval = jtag_execute_queue()) != ERROR_OK)
 			return retval;
@@ -1104,7 +1108,7 @@ int ahbap_debugport_init(struct swjdp_common *swjdp)
 
 	while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
 	{
-		LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
+		LOG_DEBUG("DAP: wait CSYSPWRUPACK");
 		dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
 		if ((retval = jtag_execute_queue()) != ERROR_OK)
 			return retval;
@@ -1163,7 +1167,7 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp
 	dap_ap_select(swjdp, apsel);
 	dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &dbgbase);
 	dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
-	swjdp_transaction_endcheck(swjdp);
+	jtagdp_transaction_endcheck(swjdp);
 	/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
 	mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
 	command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
@@ -1215,7 +1219,7 @@ int dap_info_command(struct command_context *cmd_ctx, struct swjdp_common *swjdp
 		mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
 		mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
 		mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
-		swjdp_transaction_endcheck(swjdp);
+		jtagdp_transaction_endcheck(swjdp);
 		if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
 			command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
 					", CID2 0x%2.2" PRIx32
@@ -1519,8 +1523,13 @@ DAP_COMMAND_HANDLER(dap_baseaddr_command)
 	if (apselsave != apsel)
 		dap_ap_select(swjdp, apsel);
 
+	/* NOTE:  assumes we're talking to a MEM-AP, which
+	 * has a base address.  There are other kinds of AP,
+	 * though they're not common for now.  This should
+	 * use the ID register to verify it's a MEM-AP.
+	 */
 	dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
-	retval = swjdp_transaction_endcheck(swjdp);
+	retval = jtagdp_transaction_endcheck(swjdp);
 	command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
 
 	if (apselsave != apsel)
@@ -1569,7 +1578,7 @@ DAP_COMMAND_HANDLER(dap_apsel_command)
 
 	dap_ap_select(swjdp, apsel);
 	dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
-	retval = swjdp_transaction_endcheck(swjdp);
+	retval = jtagdp_transaction_endcheck(swjdp);
 	command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
 			apsel, apid);
 
@@ -1597,7 +1606,7 @@ DAP_COMMAND_HANDLER(dap_apid_command)
 		dap_ap_select(swjdp, apsel);
 
 	dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &apid);
-	retval = swjdp_transaction_endcheck(swjdp);
+	retval = jtagdp_transaction_endcheck(swjdp);
 	command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
 	if (apselsave != apsel)
 		dap_ap_select(swjdp, apselsave);
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 861a13d..a807027 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -170,8 +170,8 @@ int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
 int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
 		uint32_t addr, uint32_t *value);
 
-/* Queued transactions must be completed with swjdp_transaction_endcheck() */
-int swjdp_transaction_endcheck(struct swjdp_common *swjdp);
+/* Queued JTAG ops must be completed with jtagdp_transaction_endcheck() */
+int jtagdp_transaction_endcheck(struct swjdp_common *swjdp);
 
 /* MEM-AP memory mapped bus single uint32_t register transfers, without endcheck */
 int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value);
diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index 3bbe42c..3f34769 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -80,7 +80,7 @@ static int cortexm3_dap_read_coreregister_u32(struct swjdp_common *swjdp,
 	dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
 	dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value);
 
-	retval = swjdp_transaction_endcheck(swjdp);
+	retval = jtagdp_transaction_endcheck(swjdp);
 
 	/* restore DCB_DCRDR - this needs to be in a seperate
 	 * transaction otherwise the emulated DCC channel breaks */
@@ -111,7 +111,7 @@ static int cortexm3_dap_write_coreregister_u32(struct swjdp_common *swjdp,
 	dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
 	dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR);
 
-	retval = swjdp_transaction_endcheck(swjdp);
+	retval = jtagdp_transaction_endcheck(swjdp);
 
 	/* restore DCB_DCRDR - this needs to be in a seperate
 	 * transaction otherwise the emulated DCC channel breaks */
@@ -238,7 +238,7 @@ static int cortex_m3_endreset_event(struct target *target)
 		target_write_u32(target, dwt_list[i].dwt_comparator_address + 8,
 				dwt_list[i].function);
 	}
-	swjdp_transaction_endcheck(swjdp);
+	jtagdp_transaction_endcheck(swjdp);
 
 	register_cache_invalidate(cortex_m3->armv7m.core_cache);
 
@@ -317,7 +317,7 @@ static int cortex_m3_examine_exception_reason(struct target *target)
 			except_sr = 0;
 			break;
 	}
-	swjdp_transaction_endcheck(swjdp);
+	jtagdp_transaction_endcheck(swjdp);
 	LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
 		shcsr, except_sr, cfsr, except_ar);
 	return ERROR_OK;

commit 2248c387f2c413c89d0f175b464a6e60ea20e75b
Author: David Brownell <dbr...@us...>
Date:   Fri Jan 29 14:16:14 2010 -0800

    ARMv7-M: use command handler for "dap baseaddr".
    
    Make the ARMv7-M DAP code reuse the command handler for "dap baseaddr".
    For some reason, this DAP command wasn't converted earlier.
    
    This is a code shrink and simplification; it also removes a needless
    transport dependency on JTAG.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index c172a27..edfcdf9 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -751,37 +751,8 @@ COMMAND_HANDLER(handle_dap_baseaddr_command)
 	struct target *target = get_current_target(CMD_CTX);
 	struct armv7m_common *armv7m = target_to_armv7m(target);
 	struct swjdp_common *swjdp = &armv7m->swjdp_info;
-	uint32_t apsel, apselsave, baseaddr;
-	int retval;
 
-	apselsave = swjdp->apsel;
-	switch (CMD_ARGC) {
-	case 0:
-		apsel = swjdp->apsel;
-		break;
-	case 1:
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
-		break;
-	default:
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	if (apselsave != apsel)
-		dap_ap_select(swjdp, apsel);
-
-	/* NOTE:  assumes we're talking to a MEM-AP, which
-	 * has a base address.  There are other kinds of AP,
-	 * though they're not common for now.  This should
-	 * use the ID register to verify it's a MEM-AP.
-	 */
-	dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &baseaddr);
-	retval = swjdp_transaction_endcheck(swjdp);
-	command_print(CMD_CTX, "0x%8.8" PRIx32 "", baseaddr);
-
-	if (apselsave != apsel)
-		dap_ap_select(swjdp, apselsave);
-
-	return retval;
+	return CALL_COMMAND_HANDLER(dap_baseaddr_command, swjdp);
 }
 
 /*

commit 303b493c229475df26d69d102bbaf5ae5e5e7a3f
Author: David Brownell <dbr...@us...>
Date:   Fri Jan 29 13:52:08 2010 -0800

    NOR: cleanup driver decls
    
    Fix goofy struct indents.  Function names *are* their addresses.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/flash/nor/aduc702x.c b/src/flash/nor/aduc702x.c
index 211b54e..7e81b32 100644
--- a/src/flash/nor/aduc702x.c
+++ b/src/flash/nor/aduc702x.c
@@ -412,14 +412,14 @@ static int aduc702x_check_flash_completion(struct target* target, unsigned int t
 }
 
 struct flash_driver aduc702x_flash = {
-		.name = "aduc702x",
-		.flash_bank_command = &aduc702x_flash_bank_command,
-		.erase = &aduc702x_erase,
-		.protect = &aduc702x_protect,
-		.write = &aduc702x_write,
-		.probe = &aduc702x_probe,
-		.auto_probe = &aduc702x_probe,
-		.erase_check = &default_flash_blank_check,
-		.protect_check = &aduc702x_protect_check,
-		.info = &aduc702x_info
-	};
+	.name = "aduc702x",
+	.flash_bank_command = aduc702x_flash_bank_command,
+	.erase = aduc702x_erase,
+	.protect = aduc702x_protect,
+	.write = aduc702x_write,
+	.probe = aduc702x_probe,
+	.auto_probe = aduc702x_probe,
+	.erase_check = default_flash_blank_check,
+	.protect_check = aduc702x_protect_check,
+	.info = aduc702x_info
+};
diff --git a/src/flash/nor/at91sam3.c b/src/flash/nor/at91sam3.c
index 5dacf6f..1b2f27c 100644
--- a/src/flash/nor/at91sam3.c
+++ b/src/flash/nor/at91sam3.c
@@ -2501,15 +2501,15 @@ static const struct command_registration at91sam3_command_handlers[] = {
 };
 
 struct flash_driver at91sam3_flash = {
-		.name = "at91sam3",
-		.commands = at91sam3_command_handlers,
-		.flash_bank_command = &sam3_flash_bank_command,
-		.erase = &sam3_erase,
-		.protect = &sam3_protect,
-		.write = &sam3_write,
-		.probe = &sam3_probe,
-		.auto_probe = &sam3_auto_probe,
-		.erase_check = &sam3_erase_check,
-		.protect_check = &sam3_protect_check,
-		.info = &sam3_info,
-	};
+	.name = "at91sam3",
+	.commands = at91sam3_command_handlers,
+	.flash_bank_command = sam3_flash_bank_command,
+	.erase = sam3_erase,
+	.protect = sam3_protect,
+	.write = sam3_write,
+	.probe = sam3_probe,
+	.auto_probe = sam3_auto_probe,
+	.erase_check = sam3_erase_check,
+	.protect_check = sam3_protect_check,
+	.info = sam3_info,
+};
diff --git a/src/flash/nor/avrf.c b/src/flash/nor/avrf.c
index 6c2d17f..c072419 100644
--- a/src/flash/nor/avrf.c
+++ b/src/flash/nor/avrf.c
@@ -452,7 +452,7 @@ COMMAND_HANDLER(avrf_handle_mass_erase_command)
 static const struct command_registration avrf_exec_command_handlers[] = {
 	{
 		.name = "mass_erase",
-		.handler = &avrf_handle_mass_erase_command,
+		.handler = avrf_handle_mass_erase_command,
 		.mode = COMMAND_EXEC,
 		.help = "erase entire device",
 	},
@@ -469,15 +469,15 @@ static const struct command_registration avrf_command_handlers[] = {
 };
 
 struct flash_driver avr_flash = {
-		.name = "avr",
-		.commands = avrf_command_handlers,
-		.flash_bank_command = &avrf_flash_bank_command,
-		.erase = &avrf_erase,
-		.protect = &avrf_protect,
-		.write = &avrf_write,
-		.probe = &avrf_probe,
-		.auto_probe = &avrf_auto_probe,
-		.erase_check = &default_flash_mem_blank_check,
-		.protect_check = &avrf_protect_check,
-		.info = &avrf_info,
-	};
+	.name = "avr",
+	.commands = avrf_command_handlers,
+	.flash_bank_command = avrf_flash_bank_command,
+	.erase = avrf_erase,
+	.protect = avrf_protect,
+	.write = avrf_write,
+	.probe = avrf_probe,
+	.auto_probe = avrf_auto_probe,
+	.erase_check = default_flash_mem_blank_check,
+	.protect_check = avrf_protect_check,
+	.info = avrf_info,
+};
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 71270b9..42aa294 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -2618,14 +2618,14 @@ static int cfi_info(struct flash_bank *bank, char *buf, int buf_size)
 }
 
 struct flash_driver cfi_flash = {
-		.name = "cfi",
-		.flash_bank_command = &cfi_flash_bank_command,
-		.erase = &cfi_erase,
-		.protect = &cfi_protect,
-		.write = &cfi_write,
-		.probe = &cfi_probe,
-		.auto_probe = &cfi_auto_probe,
-		.erase_check = &default_flash_blank_check,
-		.protect_check = &cfi_protect_check,
-		.info = &cfi_info,
-	};
+	.name = "cfi",
+	.flash_bank_command = cfi_flash_bank_command,
+	.erase = cfi_erase,
+	.protect = cfi_protect,
+	.write = cfi_write,
+	.probe = cfi_probe,
+	.auto_probe = cfi_auto_probe,
+	.erase_check = default_flash_blank_check,
+	.protect_check = cfi_protect_check,
+	.info = cfi_info,
+};
diff --git a/src/flash/nor/ecos.c b/src/flash/nor/ecos.c
index b51e0a0..783a40c 100644
--- a/src/flash/nor/ecos.c
+++ b/src/flash/nor/ecos.c
@@ -431,14 +431,14 @@ static int ecosflash_handle_gpnvm_command(struct command_context *cmd_ctx, char
 #endif
 
 struct flash_driver ecosflash_flash = {
-		.name = "ecosflash",
-		.flash_bank_command = &ecosflash_flash_bank_command,
-		.erase = &ecosflash_erase,
-		.protect = &ecosflash_protect,
-		.write = &ecosflash_write,
-		.probe = &ecosflash_probe,
-		.auto_probe = &ecosflash_probe,
-		.erase_check = &default_flash_blank_check,
-		.protect_check = &ecosflash_protect_check,
-		.info = &ecosflash_info
-	};
+	.name = "ecosflash",
+	.flash_bank_command = ecosflash_flash_bank_command,
+	.erase = ecosflash_erase,
+	.protect = ecosflash_protect,
+	.write = ecosflash_write,
+	.probe = ecosflash_probe,
+	.auto_probe = ecosflash_probe,
+	.erase_check = default_flash_blank_check,
+	.protect_check = ecosflash_protect_check,
+	.info = ecosflash_info
+};
diff --git a/src/flash/nor/faux.c b/src/flash/nor/faux.c
index 948f305..e1e77ea 100644
--- a/src/flash/nor/faux.c
+++ b/src/flash/nor/faux.c
@@ -135,15 +135,15 @@ static const struct command_registration faux_command_handlers[] = {
 };
 
 struct flash_driver faux_flash = {
-		.name = "faux",
-		.commands = faux_command_handlers,
-		.flash_bank_command = &faux_flash_bank_command,
-		.erase = &faux_erase,
-		.protect = &faux_protect,
-		.write = &faux_write,
-		.probe = &faux_probe,
-		.auto_probe = &faux_probe,
-		.erase_check = &default_flash_blank_check,
-		.protect_check = &faux_protect_check,
-		.info = &faux_info
-	};
+	.name = "faux",
+	.commands = faux_command_handlers,
+	.flash_bank_command = faux_flash_bank_command,
+	.erase = faux_erase,
+	.protect = faux_protect,
+	.write = faux_write,
+	.probe = faux_probe,
+	.auto_probe = faux_probe,
+	.erase_check = default_flash_blank_check,
+	.protect_check = faux_protect_check,
+	.info = faux_info
+};
diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c
index ae0a384..fc2b1cf 100644
--- a/src/flash/nor/lpc2000.c
+++ b/src/flash/nor/lpc2000.c
@@ -783,7 +783,7 @@ COMMAND_HANDLER(lpc2000_handle_part_id_command)
 static const struct command_registration lpc2000_exec_command_handlers[] = {
 	{
 		.name = "part_id",
-		.handler = &lpc2000_handle_part_id_command,
+		.handler = lpc2000_handle_part_id_command,
 		.mode = COMMAND_EXEC,
 		.help = "print part id of lpc2000 flash bank <num>",
 	},
@@ -800,17 +800,15 @@ static const struct command_registration lpc2000_command_handlers[] = {
 };
 
 struct flash_driver lpc2000_flash = {
-		.name = "lpc2000",
-		.commands = lpc2000_command_handlers,
-		.flash_bank_command = &lpc2000_flash_bank_command,
-		.erase = &lpc2000_erase,
-		.protect = &lpc2000_protect,
-		.write = &lpc2000_write,
-		.probe = &lpc2000_probe,
-		.auto_probe = &lpc2000_probe,
-		.erase_check = &lpc2000_erase_check,
-		.protect_check = &lpc2000_protect_check,
-		.info = &lpc2000_info,
-	};
-
-
+	.name = "lpc2000",
+	.commands = lpc2000_command_handlers,
+	.flash_bank_command = lpc2000_flash_bank_command,
+	.erase = lpc2000_erase,
+	.protect = lpc2000_protect,
+	.write = lpc2000_write,
+	.probe = lpc2000_probe,
+	.auto_probe = lpc2000_probe,
+	.erase_check = lpc2000_erase_check,
+	.protect_check = lpc2000_protect_check,
+	.info = lpc2000_info,
+};
diff --git a/src/flash/nor/lpc288x.c b/src/flash/nor/lpc288x.c
index 5cb36d0..5ab4e9c 100644
--- a/src/flash/nor/lpc288x.c
+++ b/src/flash/nor/lpc288x.c
@@ -473,14 +473,14 @@ static int lpc288x_protect(struct flash_bank *bank, int set, int first, int last
 }
 
 struct flash_driver lpc288x_flash = {
-		.name = "lpc288x",
-		.flash_bank_command = &lpc288x_flash_bank_command,
-		.erase = &lpc288x_erase,
-		.protect = &lpc288x_protect,
-		.write = &lpc288x_write,
-		.probe = &lpc288x_probe,
-		.auto_probe = &lpc288x_probe,
-		.erase_check = &lpc288x_erase_check,
-		.protect_check = &lpc288x_protect_check,
-		.info = &lpc288x_info,
-	};
+	.name = "lpc288x",
+	.flash_bank_command = lpc288x_flash_bank_command,
+	.erase = lpc288x_erase,
+	.protect = lpc288x_protect,
+	.write = lpc288x_write,
+	.probe = lpc288x_probe,
+	.auto_probe = lpc288x_probe,
+	.erase_check = lpc288x_erase_check,
+	.protect_check = lpc288x_protect_check,
+	.info = lpc288x_info,
+};
diff --git a/src/flash/nor/lpc2900.c b/src/flash/nor/lpc2900.c
index d39b2dd..360c14d 100644
--- a/src/flash/nor/lpc2900.c
+++ b/src/flash/nor/lpc2900.c
@@ -951,14 +951,14 @@ COMMAND_HANDLER(lpc2900_handle_secure_jtag_command)
 static const struct command_registration lpc2900_exec_command_handlers[] = {
 	{
 		.name = "signature",
-		.handler = &lpc2900_handle_signature_command,
+		.handler = lpc2900_handle_signature_command,
 		.mode = COMMAND_EXEC,
 		.usage = "bank_id",
 		.help = "Calculate and display signature of flash bank.",
 	},
 	{
 		.name = "read_custom",
-		.handler = &lpc2900_handle_read_custom_command,
+		.handler = lpc2900_handle_read_custom_command,
 		.mode = COMMAND_EXEC,
 		.usage = "bank_id filename",
 		.help = "Copies 912 bytes of customer information "
@@ -966,14 +966,14 @@ static const struct command_registration lpc2900_exec_command_handlers[] = {
 	},
 	{
 		.name = "password",
-		.handler = &lpc2900_handle_password_command,
+		.handler = lpc2900_handle_password_command,
 		.mode = COMMAND_EXEC,
 		.usage = "bank_id password",
 		.help = "Enter fixed password to enable 'dangerous' options.",
 	},
 	{
 		.name = "write_custom",
-		.handler = &lpc2900_handle_write_custom_command,
+		.handler = lpc2900_handle_write_custom_command,
 		.mode = COMMAND_EXEC,
 		.usage = "bank_id filename ('bin'|'ihex'|'elf'|'s19')",
 		.help = "Copies 912 bytes of customer info from file "
@@ -981,7 +981,7 @@ static const struct command_registration lpc2900_exec_command_handlers[] = {
 	},
 	{
 		.name = "secure_sector",
-		.handler = &lpc2900_handle_secure_sector_command,
+		.handler = lpc2900_handle_secure_sector_command,
 		.mode = COMMAND_EXEC,
 		.usage = "bank_id first_sector last_sector",
 		.help = "Activate sector security for a range of sectors.  "
@@ -989,7 +989,7 @@ static const struct command_registration lpc2900_exec_command_handlers[] = {
 	},
 	{
 		.name = "secure_jtag",
-		.handler = &lpc2900_handle_secure_jtag_command,
+		.handler = lpc2900_handle_secure_jtag_command,
 		.mode = COMMAND_EXEC,
 		.usage = "bank_id",
 		.help = "Disable the JTAG port.  "
diff --git a/src/flash/nor/ocl.c b/src/flash/nor/ocl.c
index 961537e..5d93724 100644
--- a/src/flash/nor/ocl.c
+++ b/src/flash/nor/ocl.c
@@ -348,14 +348,14 @@ static int ocl_auto_probe(struct flash_bank *bank)
 }
 
 struct flash_driver ocl_flash = {
-		.name = "ocl",
-		.flash_bank_command = &ocl_flash_bank_command,
-		.erase = &ocl_erase,
-		.protect = &ocl_protect,
-		.write = &ocl_write,
-		.probe = &ocl_probe,
-		.erase_check = &ocl_erase_check,
-		.protect_check = &ocl_protect_check,
-		.info = &ocl_info,
-		.auto_probe = &ocl_auto_probe,
-	};
+	.name = "ocl",
+	.flash_bank_command = ocl_flash_bank_command,
+	.erase = ocl_erase,
+	.protect = ocl_protect,
+	.write = ocl_write,
+	.probe = ocl_probe,
+	.erase_check = ocl_erase_check,
+	.protect_check = ocl_protect_check,
+	.info = ocl_info,
+	.auto_probe = ocl_auto_probe,
+};
diff --git a/src/flash/nor/pic32mx.c b/src/flash/nor/pic32mx.c
index 7d98af3..1f66346 100644
--- a/src/flash/nor/pic32mx.c
+++ b/src/flash/nor/pic32mx.c
@@ -886,13 +886,13 @@ COMMAND_HANDLER(pic32mx_handle_pgm_word_command)
 static const struct command_registration pic32mx_exec_command_handlers[] = {
 	{
 		.name = "chip_erase",
-		.handler = &pic32mx_handle_chip_erase_command,
+		.handler = pic32mx_handle_chip_erase_command,
 		.mode = COMMAND_EXEC,
 		.help = "erase device",
 	},
 	{
 		.name = "pgm_word",
-		.handler = &pic32mx_handle_pgm_word_command,
+		.handler = pic32mx_handle_pgm_word_command,
 		.mode = COMMAND_EXEC,
 		.help = "program a word",
 	},
@@ -909,15 +909,15 @@ static const struct command_registration pic32mx_command_handlers[] = {
 };
 
 struct flash_driver pic32mx_flash = {
-		.name = "pic32mx",
-		.commands = pic32mx_command_handlers,
-		.flash_bank_command = &pic32mx_flash_bank_command,
-		.erase = &pic32mx_erase,
-		.protect = &pic32mx_protect,
-		.write = &pic32mx_write,
-		.probe = &pic32mx_probe,
-		.auto_probe = &pic32mx_auto_probe,
-		.erase_check = &default_flash_mem_blank_check,
-		.protect_check = &pic32mx_protect_check,
-		.info = &pic32mx_info,
-	};
+	.name = "pic32mx",
+	.commands = pic32mx_command_handlers,
+	.flash_bank_command = pic32mx_flash_bank_command,
+	.erase = pic32mx_erase,
+	.protect = pic32mx_protect,
+	.write = pic32mx_write,
+	.probe = pic32mx_probe,
+	.auto_probe = pic32mx_auto_probe,
+	.erase_check = default_flash_mem_blank_check,
+	.protect_check = pic32mx_protect_check,
+	.info = pic32mx_info,
+};
diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c
index 8d35f9b..107b1c6 100644
--- a/src/flash/nor/stellaris.c
+++ b/src/flash/nor/stellaris.c
@@ -1173,7 +1173,7 @@ COMMAND_HANDLER(stellaris_handle_mass_erase_command)
 static const struct command_registration stellaris_exec_command_handlers[] = {
 	{
 		.name = "mass_erase",
-		.handler = &stellaris_handle_mass_erase_command,
+		.handler = stellaris_handle_mass_erase_command,
 		.mode = COMMAND_EXEC,
 		.help = "erase entire device",
 	},
diff --git a/src/flash/nor/stm32x.c b/src/flash/nor/stm32x.c
index 75dcf3b..eaa3a0e 100644
--- a/src/flash/nor/stm32x.c
+++ b/src/flash/nor/stm32x.c
@@ -1193,35 +1193,35 @@ COMMAND_HANDLER(stm32x_handle_mass_erase_command)
 static const struct command_registration stm32x_exec_command_handlers[] = {
 	{
 		.name = "lock",
-		.handler = &stm32x_handle_lock_command,
+		.handler = stm32x_handle_lock_command,
 		.mode = COMMAND_EXEC,
 		.usage = "bank_id",
 		.help = "Lock entire flash device.",
 	},
 	{
 		.name = "unlock",
-		.handler = &stm32x_handle_unlock_command,
+		.handler = stm32x_handle_unlock_command,
 		.mode = COMMAND_EXEC,
 		.usage = "bank_id",
 		.help = "Unlock entire protected flash device.",
 	},
 	{
 		.name = "mass_erase",
-		.handler = &stm32x_handle_mass_erase_command,
+		.handler = stm32x_handle_mass_erase_command,
 		.mode = COMMAND_EXEC,
 		.usage = "bank_id",
 		.help = "Erase entire flash device.",
 	},
 	{
 		.name = "options_read",
-		.handler = &stm32x_handle_options_read_command,
+		.handler = stm32x_handle_options_read_command,
 		.mode = COMMAND_EXEC,
 		.usage = "bank_id",
 		.help = "Read and display device option byte.",
 	},
 	{
 		.name = "options_write",
-		.handler = &stm32x_handle_options_write_command,
+		.handler = stm32x_handle_options_write_command,
 		.mode = COMMAND_EXEC,
 		.usage = "bank_id ('SWWDG'|'HWWDG') "
 			"('RSTSTNDBY'|'NORSTSTNDBY') "
@@ -1241,15 +1241,15 @@ static const struct command_registration stm32x_command_handlers[] = {
 };
 
 struct flash_driver stm32x_flash = {
-		.name = "stm32x",
-		.commands = stm32x_command_handlers,
-		.flash_bank_command = &stm32x_flash_bank_command,
-		.erase = &stm32x_erase,
-		.protect = &stm32x_protect,
-		.write = &stm32x_write,
-		.probe = &stm32x_probe,
-		.auto_probe = &stm32x_auto_probe,
-		.erase_check = &default_flash_mem_blank_check,
-		.protect_check = &stm32x_protect_check,
-		.info = &stm32x_info,
-	};
+	.name = "stm32x",
+	.commands = stm32x_command_handlers,
+	.flash_bank_command = stm32x_flash_bank_command,
+	.erase = stm32x_erase,
+	.protect = stm32x_protect,
+	.write = stm32x_write,
+	.probe = stm32x_probe,
+	.auto_probe = stm32x_auto_probe,
+	.erase_check = default_flash_mem_blank_check,
+	.protect_check = stm32x_protect_check,
+	.info = stm32x_info,
+};
diff --git a/src/flash/nor/str7x.c b/src/flash/nor/str7x.c
index 040097a..a2e27da 100644
--- a/src/flash/nor/str7x.c
+++ b/src/flash/nor/str7x.c
@@ -676,7 +676,7 @@ COMMAND_HANDLER(str7x_handle_disable_jtag_command)
 static const struct command_registration str7x_exec_command_handlers[] = {
 	{
 		.name = "disable_jtag",
-		.handler = &str7x_handle_disable_jtag_command,
+		.handler = str7x_handle_disable_jtag_command,
 		.mode = COMMAND_EXEC,
 		.help = "disable jtag access",
 	},
@@ -693,15 +693,15 @@ static const struct command_registration str7x_command_handlers[] = {
 };
 
 struct flash_driver str7x_flash = {
-		.name = "str7x",
-		.commands = str7x_command_handlers,
-		.flash_bank_command = &str7x_flash_bank_command,
-		.erase = &str7x_erase,
-		.protect = &str7x_protect,
-		.write = &str7x_write,
-		.probe = &str7x_probe,
-		.auto_probe = &str7x_probe,
-		.erase_check = &default_flash_blank_check,
-		.protect_check = &str7x_protect_check,
-		.info = &str7x_info,
-	};
+	.name = "str7x",
+	.commands = str7x_command_handlers,
+	.flash_bank_command = str7x_flash_bank_command,
+	.erase = str7x_erase,
+	.protect = str7x_protect,
+	.write = str7x_write,
+	.probe = str7x_probe,
+	.auto_probe = str7x_probe,
+	.erase_check = default_flash_blank_check,
+	.protect_check = str7x_protect_check,
+	.info = str7x_info,
+};
diff --git a/src/flash/nor/str9x.c b/src/flash/nor/str9x.c
index d0c1278..0875851 100644
--- a/src/flash/nor/str9x.c
+++ b/src/flash/nor/str9x.c
@@ -668,7 +668,7 @@ COMMAND_HANDLER(str9x_handle_flash_config_command)
 static const struct command_registration str9x_config_command_handlers[] = {
 	{
 		.name = "flash_config",
-		.handler = &str9x_handle_flash_config_command,
+		.handler = str9x_handle_flash_config_command,
 		.mode = COMMAND_EXEC,
 		.help = "Configure str9x flash controller, prior to "
 			"programming the flash.",
@@ -687,15 +687,15 @@ static const struct command_registration str9x_command_handlers[] = {
 };
 
 struct flash_driver str9x_flash = {
-		.name = "str9x",
-		.commands = str9x_command_handlers,
-		.flash_bank_command = &str9x_flash_bank_command,
-		.erase = &str9x_erase,
-		.protect = &str9x_protect,
-		.write = &str9x_write,
-		.probe = &str9x_probe,
-		.auto_probe = &str9x_probe,
-		.erase_check = &default_flash_blank_check,
-		.protect_check = &str9x_protect_check,
-		.info = &str9x_info,
-	};
+	.name = "str9x",
+	.commands = str9x_command_handlers,
+	.flash_bank_command = str9x_flash_bank_command,
+	.erase = str9x_erase,
+	.protect = str9x_protect,
+	.write = str9x_write,
+	.probe = str9x_probe,
+	.auto_probe = str9x_probe,
+	.erase_check = default_flash_blank_check,
+	.protect_check = str9x_protect_check,
+	.info = str9x_info,
+};
diff --git a/src/flash/nor/str9xpec.c b/src/flash/nor/str9xpec.c
index 734f2d1..f0e11a5 100644
--- a/src/flash/nor/str9xpec.c
+++ b/src/flash/nor/str9xpec.c
@@ -1244,15 +1244,15 @@ static const struct command_registration str9xpec_command_handlers[] = {
 };
 
 struct flash_driver str9xpec_flash = {
-		.name = "str9xpec",
-		.commands = str9xpec_command_handlers,
-		.flash_bank_command = &str9xpec_flash_bank_command,
-		.erase = &str9xpec_erase,
-		.protect = &str9xpec_protect,
-		.write = &str9xpec_write,
-		.probe = &str9xpec_probe,
-		.auto_probe = &str9xpec_probe,
-		.erase_check = &str9xpec_erase_check,
-		.protect_check = &str9xpec_protect_check,
-		.info = &str9xpec_info,
-	};
+	.name = "str9xpec",
+	.commands = str9xpec_command_handlers,
+	.flash_bank_command = str9xpec_flash_bank_command,
+	.erase = str9xpec_erase,
+	.protect = str9xpec_protect,
+	.write = str9xpec_write,
+	.probe = str9xpec_probe,
+	.auto_probe = str9xpec_probe,
+	.erase_check = str9xpec_erase_check,
+	.protect_check = str9xpec_protect_check,
+	.info = str9xpec_info,
+};
diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
index cf40a81..a40230b 100644
--- a/src/flash/nor/tcl.c
+++ b/src/flash/nor/tcl.c
@@ -924,7 +924,7 @@ COMMAND_HANDLER(handle_flash_init_command)
 static const struct command_registration flash_config_command_handlers[] = {
 	{
 		.name = "bank",
-		.handler = &handle_flash_bank_command,
+		.handler = handle_flash_bank_command,
 		.mode = COMMAND_CONFIG,
 		.usage = "bank_id driver_name base_address size_bytes "
 			"chip_width_bytes bus_width_bytes target "
@@ -935,19 +935,19 @@ static const struct command_registration flash_config_command_handlers[] = {
 	{
 		.name = "init",
 		.mode = COMMAND_CONFIG,
-		.handler = &handle_flash_init_command,
+		.handler = handle_flash_init_command,
 		.help = "Initialize flash devices.",
 	},
 	{
 		.name = "banks",
 		.mode = COMMAND_ANY,
-		.handler = &handle_flash_banks_command,
+		.handler = handle_flash_banks_command,
 		.help = "Display table with information about flash banks.",
 	},
 	{
 		.name = "list",
 		.mode = COMMAND_ANY,
-		.jim_handler = &jim_flash_list,
+		.jim_handler = jim_flash_list,
 		.help = "Returns a list of details about the flash banks.",
 	},
 	COMMAND_REGISTRATION_DONE
diff --git a/src/flash/nor/tms470.c b/src/flash/nor/tms470.c
index 7efcbd4..af635d4 100644
--- a/src/flash/nor/tms470.c
+++ b/src/flash/nor/tms470.c
@@ -821,19 +821,19 @@ static int tms470_erase_sector(struct flash_bank *bank, int sector)
 static const struct command_registration tms470_any_command_handlers[] = {
 	{
 		.name = "flash_keyset",
-		.handler = &tms470_handle_flash_keyset_command,
+		.handler = tms470_handle_flash_keyset_command,
 		.mode = COMMAND_ANY,
 		.help = "tms470 flash_keyset <key0> <key1> <key2> <key3>",
 	},
 	{
 		.name = "osc_megahertz",
-		.handler = &tms470_handle_osc_megahertz_command,
+		.handler = tms470_handle_osc_megahertz_command,
 		.mode = COMMAND_ANY,
 		.help = "tms470 osc_megahertz <MHz>",
 	},
 	{
 		.name = "plldis",
-		.handler = &tms470_handle_plldis_command,
+		.handler = tms470_handle_plldis_command,
 		.mode = COMMAND_ANY,
 		.help = "tms470 plldis <0/1>",
 	},
@@ -1258,15 +1258,15 @@ FLASH_BANK_COMMAND_HANDLER(tms470_flash_bank_command)
 }
 
 struct flash_driver tms470_flash = {
-		.name = "tms470",
-		.commands = tms470_command_handlers,
-		.flash_bank_command = &tms470_flash_bank_command,
-		.erase = &tms470_erase,
-		.protect = &tms470_protect,
-		.write = &tms470_write,
-		.probe = &tms470_probe,
-		.auto_probe = &tms470_auto_probe,
-		.erase_check = &tms470_erase_check,
-		.protect_check = &tms470_protect_check,
-		.info = &tms470_info,
-	};
+	.name = "tms470",
+	.commands = tms470_command_handlers,
+	.flash_bank_command = tms470_flash_bank_command,
+	.erase = tms470_erase,
+	.protect = tms470_protect,
+	.write = tms470_write,
+	.probe = tms470_probe,
+	.auto_probe = tms470_auto_probe,
+	.erase_check = tms470_erase_check,
+	.protect_check = tms470_protect_check,
+	.info = tms470_info,
+};

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/aduc702x.c  |   22 +++++++-------
 src/flash/nor/at91sam3.c  |   24 ++++++++--------
 src/flash/nor/avrf.c      |   26 +++++++++---------
 src/flash/nor/cfi.c       |   22 +++++++-------
 src/flash/nor/ecos.c      |   22 +++++++-------
 src/flash/nor/faux.c      |   24 ++++++++--------
 src/flash/nor/lpc2000.c   |   28 +++++++++----------
 src/flash/nor/lpc288x.c   |   22 +++++++-------
 src/flash/nor/lpc2900.c   |   12 ++++----
 src/flash/nor/ocl.c       |   22 +++++++-------
 src/flash/nor/pic32mx.c   |   28 +++++++++---------
 src/flash/nor/stellaris.c |    2 +-
 src/flash/nor/stm32x.c    |   34 ++++++++++++------------
 src/flash/nor/str7x.c     |   26 +++++++++---------
 src/flash/nor/str9x.c     |   26 +++++++++---------
 src/flash/nor/str9xpec.c  |   24 ++++++++--------
 src/flash/nor/tcl.c       |    8 +++---
 src/flash/nor/tms470.c    |   30 ++++++++++----------
 src/target/arm_adi_v5.c   |   65 +++++++++++++++++++++++++-------------------
 src/target/arm_adi_v5.h   |    4 +-
 src/target/armv7m.c       |   31 +--------------------
 src/target/cortex_m3.c    |    8 +++---
 22 files changed, 244 insertions(+), 266 deletions(-)


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commit cd3017cffa68e6f56419177e66332f86ab45675b
Author: Alex Austin <ale...@sp...>
Date:   Fri Jan 29 00:41:44 2010 -0600

    Clang buildfixes
    
    Building with clang took a few very small changes. The change to
    helper/log.h is because clang doesn't like an expression where the
    result is unused. In helper/system.h, I just defined true and false
    since clang doesn't have them builtin.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/helper/log.h b/src/helper/log.h
index ebcb8a1..b936fee 100644
--- a/src/helper/log.h
+++ b/src/helper/log.h
@@ -111,7 +111,12 @@ extern int debug_level;
 #define LOG_LEVEL_IS(FOO)  ((debug_level) >= (FOO))
 
 #define LOG_DEBUG(expr ...) \
-		((debug_level >= LOG_LVL_DEBUG) ? log_printf_lf (LOG_LVL_DEBUG, __FILE__, __LINE__, __FUNCTION__, expr) , 0 : 0)
+		do { \
+			if (debug_level >= LOG_LVL_DEBUG) \
+				log_printf_lf(LOG_LVL_DEBUG, \
+					__FILE__, __LINE__, __func__, \
+					expr); \
+		} while (0)
 
 #define LOG_INFO(expr ...) \
 		log_printf_lf (LOG_LVL_INFO, __FILE__, __LINE__, __FUNCTION__, expr)
diff --git a/src/helper/system.h b/src/helper/system.h
index af19d01..8ff3532 100644
--- a/src/helper/system.h
+++ b/src/helper/system.h
@@ -85,4 +85,9 @@
 #include <fcntl.h>
 #endif
 
+#ifndef true
+#define true	1
+#define false	0
+#endif
+
 #endif // SYSTEM_H

-----------------------------------------------------------------------

Summary of changes:
 src/helper/log.h    |    7 ++++++-
 src/helper/system.h |    5 +++++
 2 files changed, 11 insertions(+), 1 deletions(-)


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commit 804c0b2ad321247e50910511f691d987d8141081
Author: David Brownell <dbr...@us...>
Date:   Thu Jan 28 14:03:29 2010 -0800

    doc clarifications for server flags
    
    The "-f" is a shortcut for "-c" ... and providing any "-c" options
    means the "openocd.cfg" file isn't implicitly used.  Both the User's
    Guide and the manual page were weak on these points, which has led
    to some confusion.
    
    Also update the manual page to include highlights of the search path
    mechanism, including the facts that it exists and that "-s" adds to it.
    Stop saying only the current directory is involved; the OpenOCD
    script library is quite significant.
    
    (Missing: complete manpage coverage of the search path, including a
    FILES section listing all components and saying where the script
    library is found.)
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/doc/openocd.1 b/doc/openocd.1
index 68b6957..3720d42 100644
--- a/doc/openocd.1
+++ b/doc/openocd.1
@@ -22,19 +22,23 @@ please check the \fIopenocd\fR info page for the complete list.
 .SH "OPTIONS"
 .TP
 .B "\-f, \-\-file <filename>"
-Use configuration file
-.BR <filename> .
+This is a shortcut for a \fB\-c "[script \fI<filename>\fB]"\fR
+command, using a search path to load the configuration file
+.IR <filename> .
 In order to specify multiple config files, you can use multiple
 .B \-\-file
-arguments. If this option is omitted, the config file
+arguments. If no such \fB\-c\fR
+options are included, the first config file
 .B openocd.cfg
-in the current working directory will be used.
+in the search path will be used.
 .TP
 .B "\-s, \-\-search <dirname>"
-Search for config files and scripts in the directory
-.BR <dirname> .
-If this option is omitted, OpenOCD searches for config files and scripts
-in the current directory.
+Add
+.I <dirname>
+to the search path used for config files and scripts.
+The search path begins with the current directory,
+then includes these additional directories before other
+components such as the standard OpenOCD script libraries.
 .TP
 .B "\-d, \-\-debug <debuglevel>"
 Set debug level. Possible values are:
@@ -52,13 +56,17 @@ The default level is
 .TP
 .B "\-l, \-\-log_output <filename>"
 Redirect log output to the file
-.BR <filename> .
+.IR <filename> .
 Per default the log output is printed on
 .BR stderr .
 .TP
 .B "\-c, \-\-command <cmd>"
-Run the command
-.BR <cmd> .
+Add the command
+.I <cmd>
+to a list of commands executed on server startup.
+Note that you will need to explicitly invoke
+.I init
+if the command requires access to a target or flash.
 .TP
 .B "\-p, \-\-pipe"
 Use pipes when talking to gdb.
diff --git a/doc/openocd.texi b/doc/openocd.texi
index ee5c723..38fa92f 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -513,9 +513,10 @@ bash$ openocd --help
 --pipe       | -p       use pipes when talking to gdb
 @end verbatim
 
-By default OpenOCD reads the configuration file @file{openocd.cfg}.
-To specify a different (or multiple)
-configuration file, you can use the @option{-f} option. For example:
+If you don't give any @option{-f} or @option{-c} options,
+OpenOCD tries to read the configuration file @file{openocd.cfg}.
+To specify one or more different
+configuration files, use @option{-f} options. For example:
 
 @example
 openocd -f config1.cfg -f config2.cfg -f config3.cfg

commit 5dcf7898f6144266c814306003c1e0a5ee067011
Author: David Brownell <dbr...@us...>
Date:   Thu Jan 28 13:58:20 2010 -0800

    ARM: reference DPM defn from v6/v7 arch spec
    
    The term "DPM" is probably not well known ("Device Power Management"?),
    so identify its source in the current ARM architecture specification.
    It's relevant to ARMv6, ARMv7-A, and ARMv7-R ... but not "M" profiles.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 4bd22ff..3c18e63 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -35,6 +35,12 @@
  * Implements various ARM DPM operations using architectural debug registers.
  * These routines layer over core-specific communication methods to cope with
  * implementation differences between cores like ARM1136 and Cortex-A8.
+ *
+ * The "Debug Programmers' Model" (DPM) for ARMv6 and ARMv7 is defined by
+ * Part C (Debug Architecture) of the ARM Architecture Reference Manual,
+ * ARMv7-A and ARMv7-R edition (ARM DDI 0406B).  In OpenOCD, DPM operations
+ * are abstracted through internal programming interfaces to share code and
+ * to minimize needless differences in debug behavior between cores.
  */
 
 /*----------------------------------------------------------------------*/

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.1        |   30 +++++++++++++++++++-----------
 doc/openocd.texi     |    7 ++++---
 src/target/arm_dpm.c |    6 ++++++
 3 files changed, 29 insertions(+), 14 deletions(-)


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From: Spencer O. <nt...@us...> - 2010-01-28 22:07:37

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- Log -----------------------------------------------------------------
commit 75cfda4cd1fe057f0557bd86963a71e530edd584
Author: Spencer Oliver <nt...@us...>
Date:   Thu Jan 28 21:05:09 2010 +0000

    ARM semihosting: win32 and cygwin fixes
    
    Cygwin would fail to reopen a previously written file if the mode is
    not given.
    
    Simplified converting the open flags and made sure the win32 O_BINARY
    bit is set.
    
    Added define for systems that do not support O_BINARY.
    
    Signed-off-by: Spencer Oliver <nt...@us...>

diff --git a/src/helper/replacements.h b/src/helper/replacements.h
index 2b3ea73..3598dd9 100644
--- a/src/helper/replacements.h
+++ b/src/helper/replacements.h
@@ -40,6 +40,12 @@
 #define ENOTSUP 134		/* Not supported */
 #endif
 
+/* for systems that do not support O_BINARY
+ * linux being one of them */
+#ifndef O_BINARY
+#define O_BINARY 0
+#endif
+
 #ifndef HAVE_SYS_TIME_H
 
 #ifndef _TIMEVAL_DEFINED
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index 1d0acd6..8db60a5 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -2,6 +2,9 @@
  *   Copyright (C) 2009 by Marvell Technology Group Ltd.                   *
  *   Written by Nicolas Pitre <ni...@ma...>                           *
  *                                                                         *
+ *   Copyright (C) 2010 by Spencer Oliver                                  *
+ *   sp...@sp...                                                  *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -41,6 +44,20 @@
 #include <helper/binarybuffer.h>
 #include <helper/log.h>
 
+static int open_modeflags[12] = {
+	O_RDONLY,
+	O_RDONLY | O_BINARY,
+	O_RDWR,
+	O_RDWR | O_BINARY,
+	O_WRONLY | O_CREAT | O_TRUNC,
+	O_WRONLY | O_CREAT | O_TRUNC | O_BINARY,
+	O_RDWR | O_CREAT | O_TRUNC,
+	O_RDWR | O_CREAT | O_TRUNC | O_BINARY,
+	O_WRONLY | O_CREAT | O_APPEND,
+	O_WRONLY | O_CREAT | O_APPEND | O_BINARY,
+	O_RDWR | O_CREAT | O_APPEND,
+	O_RDWR | O_CREAT | O_APPEND | O_BINARY
+};
 
 static int do_semihosting(struct target *target)
 {
@@ -72,28 +89,21 @@ static int do_semihosting(struct target *target)
 			uint32_t l = target_buffer_get_u32(target, params+8);
 			if (l <= 255 && m <= 11) {
 				uint8_t fn[256];
-				int mode;
 				retval = target_read_memory(target, a, 1, l, fn);
 				if (retval != ERROR_OK)
 					return retval;
 				fn[l] = 0;
-				if (m & 0x2)
-					mode = O_RDWR;
-				else if (m & 0xc)
-					mode = O_WRONLY;
-				else
-					mode = O_RDONLY;
-				if (m >= 8)
-					mode |= O_CREAT|O_APPEND;
-				else if (m >= 4)
-					mode |= O_CREAT|O_TRUNC;
 				if (strcmp((char *)fn, ":tt") == 0) {
-					if ((mode & 3) == 0)
-						result = dup(0);
+					if (m < 4)
+						result = dup(STDIN_FILENO);
 					else
-						result = dup(1);
-				} else
-					result = open((char *)fn, mode);
+						result = dup(STDOUT_FILENO);
+				} else {
+					/* cygwin requires the permission setting
+					 * otherwise it will fail to reopen a previously
+					 * written file */
+					result = open((char *)fn, open_modeflags[m], 0644);
+				}
 				armv4_5->semihosting_errno =  errno;
 			} else {
 				result = -1;

commit 465a06dfdc6c5d4af377dac7b9d71845cb0dc034
Author: Spencer Oliver <nt...@us...>
Date:   Wed Jan 27 21:20:18 2010 +0000

    ARM semihosting: fix writing to stdout
    
    SYS_FLEN would be called before a write on a descriptor to check its size.
    Currently lseek would fail with -1 when given the stdout/stderr descriptor.
    Changing to use fstat seems to be the standard way of handling this.
    
    Signed-off-by: Spencer Oliver <nt...@us...>

diff --git a/src/helper/system.h b/src/helper/system.h
index 169df1c..af19d01 100644
--- a/src/helper/system.h
+++ b/src/helper/system.h
@@ -50,6 +50,8 @@
 #ifdef _WIN32
 #include <winsock2.h>
 #include <ws2tcpip.h>
+#include <sys/types.h>
+#include <sys/stat.h>
 #endif
 // --- platform specific headers ---
 
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index f4244c8..1d0acd6 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -230,18 +230,14 @@ static int do_semihosting(struct target *target)
 			return retval;
 		else {
 			int fd = target_buffer_get_u32(target, params+0);
-			off_t cur = lseek(fd, 0, SEEK_CUR);
-			if (cur == (off_t)-1) {
+			struct stat buf;
+			result = fstat(fd, &buf);
+			if (result == -1) {
 				armv4_5->semihosting_errno = errno;
 				result = -1;
 				break;
 			}
-			result = lseek(fd, 0, SEEK_END);
-			armv4_5->semihosting_errno = errno;
-			if (lseek(fd, cur, SEEK_SET) == (off_t)-1) {
-				armv4_5->semihosting_errno = errno;
-				result = -1;
-			}
+			result = buf.st_size;
 		}
 		break;
 

-----------------------------------------------------------------------

Summary of changes:
 src/helper/replacements.h    |    6 ++++
 src/helper/system.h          |    2 +
 src/target/arm_semihosting.c |   54 +++++++++++++++++++++++------------------
 3 files changed, 38 insertions(+), 24 deletions(-)


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From: David B. <dbr...@us...> - 2010-01-27 22:51:36

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commit 3172be80a3e14f4c8c3628a37db348c04fd60fc4
Author: David Brownell <dbr...@us...>
Date:   Wed Jan 27 13:47:48 2010 -0800

    Cortex-M3: report lockup, and recover
    
    ARMv7-M defines a "lockup" state that's entered in certain double
    fault sequences which can't be recovered from without external help.
    OpenOCD has previously ignored this.
    
    Issue a diagnostic saying the chip has locked up, and force exit
    from this state by halting the core.  It's not clear this is the
    best way to handle lockup; but there should now be less confusion.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/cortex_m3.c b/src/target/cortex_m3.c
index adce4d9..3bbe42c 100644
--- a/src/target/cortex_m3.c
+++ b/src/target/cortex_m3.c
@@ -416,6 +416,21 @@ static int cortex_m3_poll(struct target *target)
 		return retval;
 	}
 
+	/* Recover from lockup.  See ARMv7-M architecture spec,
+	 * section B1.5.15 "Unrecoverable exception cases".
+	 *
+	 * REVISIT Is there a better way to report and handle this?
+	 */
+	if (cortex_m3->dcb_dhcsr & S_LOCKUP) {
+		LOG_WARNING("%s -- clearing lockup after double fault",
+				target_name(target));
+		cortex_m3_write_debug_halt_mask(target, C_HALT, 0);
+		target->debug_reason = DBG_REASON_DBGRQ;
+
+		/* refresh status bits */
+		mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+	}
+
 	if (cortex_m3->dcb_dhcsr & S_RESET_ST)
 	{
 		/* check if still in reset */

commit d44f1aaeff45d26348826bdff07caf3d097eca15
Author: David Brownell <dbr...@us...>
Date:   Wed Jan 27 13:40:05 2010 -0800

    ARM ADIv5: messaging tweaks
    
    Add space missing after the invalid ACK value.  On init, say
    which AP is being used, and don't assume it's an AHP-AP.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index ba5db3b..2ba89e5 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -305,7 +305,7 @@ int swjdp_transaction_endcheck(struct swjdp_common *swjdp)
 			}
 			else
 			{
-				LOG_WARNING("Invalid ACK %#x"
+				LOG_WARNING("Invalid ACK %#x "
 						"in JTAG-DP transaction",
 						swjdp->ack);
 				return ERROR_JTAG_DEVICE_ERROR;
@@ -1058,6 +1058,7 @@ int mem_ap_read_buf_u8(struct swjdp_common *swjdp, uint8_t *buffer, int count, u
  * @todo Rename this.  We also need an initialization scheme which account
  * for SWD transports not just JTAG; that will need to address differences
  * in layering.  (JTAG is useful without any debug target; but not SWD.)
+ * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
  */
 int ahbap_debugport_init(struct swjdp_common *swjdp)
 {
@@ -1125,7 +1126,9 @@ int ahbap_debugport_init(struct swjdp_common *swjdp)
 	dap_ap_read_reg_u32(swjdp, AP_REG_IDR, &idreg);
 	dap_ap_read_reg_u32(swjdp, AP_REG_BASE, &romaddr);
 
-	LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr);
+	LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
+		", Debug ROM Address 0x%" PRIx32,
+		swjdp->apsel, idreg, romaddr);
 
 	return ERROR_OK;
 }

commit 2b5c444a32725dd75833348e04620bd7b1bda2ad
Author: David Brownell <dbr...@us...>
Date:   Wed Jan 27 13:24:21 2010 -0800

    Cortex-A8: debug messaging tweaks
    
    Make that "TODO" message say what needs to be done.
    Say what part of examining failed.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/cortex_a8.c b/src/target/cortex_a8.c
index 18edd95..bcdb526 100644
--- a/src/target/cortex_a8.c
+++ b/src/target/cortex_a8.c
@@ -1461,7 +1461,8 @@ static int cortex_a8_examine_first(struct target *target)
 	int retval = ERROR_OK;
 	uint32_t didr, ctypr, ttypr, cpuid;
 
-	LOG_DEBUG("TODO");
+	/* stop assuming this is an OMAP! */
+	LOG_DEBUG("TODO - autoconfigure");
 
 	/* Here we shall insert a proper ROM Table scan */
 	armv7a->debug_base = OMAP3530_DEBUG_BASE;
@@ -1474,28 +1475,28 @@ static int cortex_a8_examine_first(struct target *target)
 	if ((retval = mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_CPUID, &cpuid)) != ERROR_OK)
 	{
-		LOG_DEBUG("Examine failed");
+		LOG_DEBUG("Examine %s failed", "CPUID");
 		return retval;
 	}
 
 	if ((retval = mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_CTYPR, &ctypr)) != ERROR_OK)
 	{
-		LOG_DEBUG("Examine failed");
+		LOG_DEBUG("Examine %s failed", "CTYPR");
 		return retval;
 	}
 
 	if ((retval = mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_TTYPR, &ttypr)) != ERROR_OK)
 	{
-		LOG_DEBUG("Examine failed");
+		LOG_DEBUG("Examine %s failed", "TTYPR");
 		return retval;
 	}
 
 	if ((retval = mem_ap_read_atomic_u32(swjdp,
 			armv7a->debug_base + CPUDBG_DIDR, &didr)) != ERROR_OK)
 	{
-		LOG_DEBUG("Examine failed");
+		LOG_DEBUG("Examine %s failed", "DIDR");
 		return retval;
 	}
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_adi_v5.c |    7 +++++--
 src/target/cortex_a8.c  |   11 ++++++-----
 src/target/cortex_m3.c  |   15 +++++++++++++++
 3 files changed, 26 insertions(+), 7 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-150-g9e52957

From: David B. <dbr...@us...> - 2010-01-27 04:19:42

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  9e52957efc93734f70295a489481f4f9f3944242 (commit)
      from  33fc60befc808b83ab4ef6b1c7a7130c7ccedfc8 (commit)

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- Log -----------------------------------------------------------------
commit 9e52957efc93734f70295a489481f4f9f3944242
Author: David Brownell <dbr...@us...>
Date:   Tue Jan 26 17:54:49 2010 -0800

    cygwin buildfix
    
    isspace() parameter must be an integer, else a 'char' gets
    used as an array index (sigh).
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/svf/svf.c b/src/svf/svf.c
index ea56a88..f46d698 100644
--- a/src/svf/svf.c
+++ b/src/svf/svf.c
@@ -585,7 +585,7 @@ static int svf_parse_cmd_string(char *str, int len, char **argus, int *num_of_ar
 			goto parse_char;
 		default:
 parse_char:
-			if (!in_bracket && isspace(str[pos]))
+			if (!in_bracket && isspace((int) str[pos]))
 			{
 				space_found = 1;
 				str[pos] = '\0';
@@ -710,7 +710,7 @@ static int svf_copy_hexstring_to_binary(char *str, uint8_t **bin, int orig_bit_l
 
 	/* consume optional leading '0' MSBs or whitespace */
 	while (str_len > 0 && ((str[str_len - 1] == '0')
-				|| isspace(str[str_len - 1])))
+				|| isspace((int) str[str_len - 1])))
 		str_len--;
 
 	/* check validity: we must have consumed everything */

-----------------------------------------------------------------------

Summary of changes:
 src/svf/svf.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-151-g3036588

From: David B. <dbr...@us...> - 2010-01-27 03:14:39

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- Log -----------------------------------------------------------------
commit 30365886dab87f20c014d9ad1500c70edef48b00
Author: David Brownell <dbr...@us...>
Date:   Tue Jan 26 18:09:27 2010 -0800

    various: don't mention wiki
    
    The openfacts.berlios wiki isn't particularly current, and isn't
    publicly editable.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/doc/openocd.1 b/doc/openocd.1
index d9f8a7c..68b6957 100644
--- a/doc/openocd.1
+++ b/doc/openocd.1
@@ -88,9 +88,6 @@ and
 programs are properly installed at your site, the command
 .B info openocd
 should give you access to the complete manual.
-.PP
-Also, the OpenOCD wiki contains some more information and examples:
-.B http://openfacts.berlios.de/index-en.phtml?title=Open_On-Chip_Debugger
 .SH "AUTHORS"
 Please see the file AUTHORS.
 .PP
diff --git a/testing/examples/AT91R40008Test/prj/at91r40008_turtle.cfg b/testing/examples/AT91R40008Test/prj/at91r40008_turtle.cfg
index bf760b2..d72980e 100644
--- a/testing/examples/AT91R40008Test/prj/at91r40008_turtle.cfg
+++ b/testing/examples/AT91R40008Test/prj/at91r40008_turtle.cfg
@@ -30,8 +30,8 @@ target_script 0 reset .\prj\at91r40008_reset.script
 
 flash bank cfi 0x10000000 0x400000 2 2 0
 
-# For more information about the configuration files, take a look at:
-# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger
+# For more information about the configuration files,
+# look at the OpenOCD User's Guide.
 
 init
 reset halt
diff --git a/testing/examples/LPC2148Test/prj/lpc2148_jtagkey.cfg b/testing/examples/LPC2148Test/prj/lpc2148_jtagkey.cfg
index d491d7d..e6b1e9e 100644
--- a/testing/examples/LPC2148Test/prj/lpc2148_jtagkey.cfg
+++ b/testing/examples/LPC2148Test/prj/lpc2148_jtagkey.cfg
@@ -27,8 +27,8 @@ target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdm
 #flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
 flash bank lpc2000 0x0 0x7d000 0 0 0 lpc2000_v2 14765 calc_checksum
 
-# For more information about the configuration files, take a look at:
-# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger
+# For more information about the configuration files,
+# look at the OpenOCD User's Guide.
 
 init
 reset halt
diff --git a/testing/examples/LPC2294Test/prj/lpc2294_jtagkey.cfg b/testing/examples/LPC2294Test/prj/lpc2294_jtagkey.cfg
index e8d3051..958b8a5 100644
--- a/testing/examples/LPC2294Test/prj/lpc2294_jtagkey.cfg
+++ b/testing/examples/LPC2294Test/prj/lpc2294_jtagkey.cfg
@@ -28,8 +28,8 @@ target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdm
 #flash bank lpc2000 <base> <size> 0 0 <target#> <variant>
 flash bank lpc2000 0x0 0x40000 0 0 0 lpc2000_v1 14765 calc_checksum
 
-# For more information about the configuration files, take a look at:
-# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger
+# For more information about the configuration files,
+# look at the OpenOCD User's Guide.
 
 init
 reset halt
diff --git a/testing/examples/SAM7S256Test/prj/sam7s256_jtagkey.cfg b/testing/examples/SAM7S256Test/prj/sam7s256_jtagkey.cfg
index 4fd729e..92c1e30 100644
--- a/testing/examples/SAM7S256Test/prj/sam7s256_jtagkey.cfg
+++ b/testing/examples/SAM7S256Test/prj/sam7s256_jtagkey.cfg
@@ -32,8 +32,8 @@ target_script 0 reset .\prj\sam7s256_reset.script
 #flash bank <driver> <base> <size> <chip_width> <bus_width>
 flash bank at91sam7 0 0 0 0 0
 
-# For more information about the configuration files, take a look at:
-# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger
+# For more information about the configuration files,
+# look at the OpenOCD User's Guide.
 
 init
 reset halt
diff --git a/testing/examples/SAM7X256Test/prj/sam7x256_jtagkey.cfg b/testing/examples/SAM7X256Test/prj/sam7x256_jtagkey.cfg
index 930a1b6..32a5254 100644
--- a/testing/examples/SAM7X256Test/prj/sam7x256_jtagkey.cfg
+++ b/testing/examples/SAM7X256Test/prj/sam7x256_jtagkey.cfg
@@ -32,8 +32,8 @@ target_script 0 reset .\prj\sam7x256_reset.script
 #flash bank <driver> <base> <size> <chip_width> <bus_width>
 flash bank at91sam7 0 0 0 0 0
 
-# For more information about the configuration files, take a look at:
-# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger
+# For more information about the configuration files,
+# look at the OpenOCD User's Guide.
 
 init
 reset halt
diff --git a/testing/examples/STR710JtagSpeed/prj/str710_jtagkey.cfg b/testing/examples/STR710JtagSpeed/prj/str710_jtagkey.cfg
index 0e0cff5..f2e50dc 100644
--- a/testing/examples/STR710JtagSpeed/prj/str710_jtagkey.cfg
+++ b/testing/examples/STR710JtagSpeed/prj/str710_jtagkey.cfg
@@ -27,8 +27,8 @@ target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdm
 #flash bank str7x <base> <size> 0 0 <target#> <variant>
 flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
 
-# For more information about the configuration files, take a look at:
-# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger
+# For more information about the configuration files,
+# look at the OpenOCD User's Guide.
 
 init
 reset halt
diff --git a/testing/examples/STR710Test/prj/str710_jtagkey.cfg b/testing/examples/STR710Test/prj/str710_jtagkey.cfg
index 31240cc..14ec3f1 100644
--- a/testing/examples/STR710Test/prj/str710_jtagkey.cfg
+++ b/testing/examples/STR710Test/prj/str710_jtagkey.cfg
@@ -29,8 +29,8 @@ target_script 0 gdb_program_config .\prj\str710_program.script
 #flash bank str7x <base> <size> 0 0 <target#> <variant>
 flash bank str7x 0x40000000 0x00040000 0 0 0 STR71x
 
-# For more information about the configuration files, take a look at:
-# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger
+# For more information about the configuration files,
+# look at the OpenOCD User's Guide.
 
 init
 reset halt
diff --git a/testing/examples/STR912Test/prj/str912_jtagkey.cfg b/testing/examples/STR912Test/prj/str912_jtagkey.cfg
index d4577f3..8a3f281 100644
--- a/testing/examples/STR912Test/prj/str912_jtagkey.cfg
+++ b/testing/examples/STR912Test/prj/str912_jtagkey.cfg
@@ -34,8 +34,8 @@ target_script 0 gdb_program_config .\prj\str912_program.script
 #flash bank str7x <base> <size> 0 0 <target#> <variant>
 flash bank str9x 0x00000000 0x00080000 0 0 0
 
-# For more information about the configuration files, take a look at:
-# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger
+# For more information about the configuration files,
+# look at the OpenOCD User's Guide.
 
 init
 reset halt

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.1                                      |    3 ---
 .../AT91R40008Test/prj/at91r40008_turtle.cfg       |    4 ++--
 .../examples/LPC2148Test/prj/lpc2148_jtagkey.cfg   |    4 ++--
 .../examples/LPC2294Test/prj/lpc2294_jtagkey.cfg   |    4 ++--
 .../examples/SAM7S256Test/prj/sam7s256_jtagkey.cfg |    4 ++--
 .../examples/SAM7X256Test/prj/sam7x256_jtagkey.cfg |    4 ++--
 .../STR710JtagSpeed/prj/str710_jtagkey.cfg         |    4 ++--
 testing/examples/STR710Test/prj/str710_jtagkey.cfg |    4 ++--
 testing/examples/STR912Test/prj/str912_jtagkey.cfg |    4 ++--
 9 files changed, 16 insertions(+), 19 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-149-g33fc60b

From: David B. <dbr...@us...> - 2010-01-25 22:07:04

This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
       via  33fc60befc808b83ab4ef6b1c7a7130c7ccedfc8 (commit)
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- Log -----------------------------------------------------------------
commit 33fc60befc808b83ab4ef6b1c7a7130c7ccedfc8
Author: simon qian <sim...@gm...>
Date:   Sun Jan 24 04:08:47 2010 +0800

    SVF: all content between parentheses is one parameter
    
    More SVF fixes:
    
     * Treat all content between parentheses as part of the same
       parameter; don't (wrongly) treat whitespace as a delimiter.
    
     * Use isspace() to catch that whitespace; it's not all single
       spaces, newlines etc are also valid.
    
     * When parsing bitstrings, strip leading whitespace too.
    
    So for example, these are equivalent and should (now) be OK:
    
      "TDI( 1234 )"
      "TDI( 1 2 3 4 )"
      "TDI(00 12 34 )"
      "TDI(
      	00 12
    	34)"
    
    [dbr...@us...: comment updates; trivial cleanup]
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/svf/svf.c b/src/svf/svf.c
index 275bced..ea56a88 100644
--- a/src/svf/svf.c
+++ b/src/svf/svf.c
@@ -500,7 +500,9 @@ static int svf_read_command_from_file(int fd)
 		case '\r':
 			slash = 0;
 			comment = 0;
-			break;
+			/* Don't save '\r' and '\n' if no data is parsed */
+			if (!cmd_pos)
+				break;
 		default:
 			if (!comment)
 			{
@@ -565,25 +567,30 @@ static int svf_read_command_from_file(int fd)
 
 static int svf_parse_cmd_string(char *str, int len, char **argus, int *num_of_argu)
 {
-	int pos = 0, num = 0, space_found = 1;
+	int pos = 0, num = 0, space_found = 1, in_bracket = 0;
 
 	while (pos < len)
 	{
 		switch (str[pos])
 		{
-		case '\n':
-		case '\r':
 		case '!':
 		case '/':
 			LOG_ERROR("fail to parse svf command");
 			return ERROR_FAIL;
-			break;
-		case ' ':
-			space_found = 1;
-			str[pos] = '\0';
-			break;
+		case '(':
+			in_bracket = 1;
+			goto parse_char;
+		case ')':
+			in_bracket = 0;
+			goto parse_char;
 		default:
-			if (space_found)
+parse_char:
+			if (!in_bracket && isspace(str[pos]))
+			{
+				space_found = 1;
+				str[pos] = '\0';
+			}
+			else if (space_found)
 			{
 				argus[num++] = &str[pos];
 				space_found = 0;
@@ -651,6 +658,7 @@ static int svf_copy_hexstring_to_binary(char *str, uint8_t **bin, int orig_bit_l
 		return ERROR_FAIL;
 	}
 
+	/* fill from LSB (end of str) to MSB (beginning of str) */
 	for (i = 0; i < str_hbyte_len; i++)
 	{
 		ch = 0;
@@ -658,7 +666,13 @@ static int svf_copy_hexstring_to_binary(char *str, uint8_t **bin, int orig_bit_l
 		{
 			ch = str[--str_len];
 
-			if (!isblank(ch))
+			/* Skip whitespace.  The SVF specification (rev E) is
+			 * deficient in terms of basic lexical issues like
+			 * where whitespace is allowed.  Long bitstrings may
+			 * require line ends for correctness, since there is
+			 * a hard limit on line length.
+			 */
+			if (!isspace(ch))
 			{
 				if ((ch >= '0') && (ch <= '9'))
 				{
@@ -694,11 +708,12 @@ static int svf_copy_hexstring_to_binary(char *str, uint8_t **bin, int orig_bit_l
 		}
 	}
 
-	// consume optional leading '0' characters
-	while (str_len > 0 && str[str_len - 1] == '0')
+	/* consume optional leading '0' MSBs or whitespace */
+	while (str_len > 0 && ((str[str_len - 1] == '0')
+				|| isspace(str[str_len - 1])))
 		str_len--;
 
-	// check valid
+	/* check validity: we must have consumed everything */
 	if (str_len > 0 || (ch & ~((2 << ((bit_len - 1) % 4)) - 1)) != 0)
 	{
 		LOG_ERROR("value execeeds length");

-----------------------------------------------------------------------

Summary of changes:
 src/svf/svf.c |   43 +++++++++++++++++++++++++++++--------------
 1 files changed, 29 insertions(+), 14 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-148-g1dad2ee

From: David B. <dbr...@us...> - 2010-01-25 21:20:35

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  1dad2ee602674de1b97548913dba2d53267d35a3 (commit)
      from  9ff16575d2838527afa635058c4cb95d641533ba (commit)

Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 1dad2ee602674de1b97548913dba2d53267d35a3
Author: Edgar Grimberg <edg...@zy...>
Date:   Mon Jan 25 16:34:27 2010 +0100

    core arm11: Silence logs at level 3 if there is no activity
    
    If the target and openocd are idling, the log should normally
    be silent at level 3.  (Given no verbose logging options.)
    
    Signed-off-by: Edgar Grimberg <edg...@zy...>
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/jtag/core.c b/src/jtag/core.c
index e311bfb..8a580e9 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -530,10 +530,12 @@ int jtag_add_statemove(tap_state_t goal_state)
 {
 	tap_state_t cur_state = cmd_queue_cur_state;
 
-	LOG_DEBUG("cur_state=%s goal_state=%s",
-		tap_state_name(cur_state),
-		tap_state_name(goal_state));
-
+	if (goal_state != cur_state)
+	{
+		LOG_DEBUG("cur_state=%s goal_state=%s",
+			tap_state_name(cur_state),
+			tap_state_name(goal_state));
+	}
 
 	/* If goal is RESET, be paranoid and force that that transition
 	 * (e.g. five TCK cycles, TMS high).  Else trust "cur_state".
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 8b7b69c..671943f 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -64,10 +64,10 @@ static int arm11_step(struct target *target, int current,
 static int arm11_check_init(struct arm11_common *arm11)
 {
 	CHECK_RETVAL(arm11_read_DSCR(arm11));
-	LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
 
 	if (!(arm11->dscr & DSCR_HALT_DBG_MODE))
 	{
+		LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
 		LOG_DEBUG("Bringing target into debug mode");
 
 		arm11->dscr |= DSCR_HALT_DBG_MODE;

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/core.c    |   10 ++++++----
 src/target/arm11.c |    2 +-
 2 files changed, 7 insertions(+), 5 deletions(-)


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From: David B. <dbr...@us...> - 2010-01-23 23:24:28

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- Log -----------------------------------------------------------------
commit 9ff16575d2838527afa635058c4cb95d641533ba
Author: simon qian <sim...@gm...>
Date:   Mon Jan 18 04:56:08 2010 +0800

    SVF: insert space before '(' and after ')'
    
    See http://forum.sparkfun.com/viewtopic.php?p=90983#90983 for discussion;
    basically, the SVF parser wrongly expects "TDI (123)" but the space is
    optional and it should accept "TDI(123)" too.
    
    In the same way, "TDI(123)TDO(456)" should work too.
    
    Rather than update the command parsing, this just makes sure the expected
    spaces are present.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/svf/svf.c b/src/svf/svf.c
index 7cb2200..275bced 100644
--- a/src/svf/svf.c
+++ b/src/svf/svf.c
@@ -504,27 +504,49 @@ static int svf_read_command_from_file(int fd)
 		default:
 			if (!comment)
 			{
-				if (cmd_pos >= svf_command_buffer_size - 1)
+				/* The parsing code currently expects a space
+				 * before parentheses -- "TDI (123)".  Also a
+				 * space afterwards -- "TDI (123) TDO(456)".
+				 * But such spaces are optional... instead of
+				 * parser updates, cope with that by adding the
+				 * spaces as needed.
+				 *
+				 * Ensure there are 3 bytes available, for:
+				 *  - current character
+				 *  - added space.
+				 *  - terminating NUL ('\0')
+				 */
+				if ((cmd_pos + 2) >= svf_command_buffer_size)
 				{
-					tmp_buffer = (char*)malloc(svf_command_buffer_size + SVFP_CMD_INC_CNT);		// 1 more byte for '\0'
+					/* REVISIT use realloc(); simpler */
+					tmp_buffer = malloc(
+							svf_command_buffer_size
+							+ SVFP_CMD_INC_CNT);
 					if (NULL == tmp_buffer)
 					{
 						LOG_ERROR("not enough memory");
 						return ERROR_FAIL;
 					}
 					if (svf_command_buffer_size > 0)
-					{
-						memcpy(tmp_buffer, svf_command_buffer, svf_command_buffer_size);
-					}
+						memcpy(tmp_buffer,
+							svf_command_buffer,
+							svf_command_buffer_size);
 					if (svf_command_buffer != NULL)
-					{
 						free(svf_command_buffer);
-					}
 					svf_command_buffer = tmp_buffer;
 					svf_command_buffer_size += SVFP_CMD_INC_CNT;
 					tmp_buffer = NULL;
 				}
+
+				/* insert a space before '(' */
+				if ('(' == ch)
+					svf_command_buffer[cmd_pos++] = ' ';
+
 				svf_command_buffer[cmd_pos++] = (char)toupper(ch);
+
+				/* insert a space after ')' */
+				if (')' == ch)
+					svf_command_buffer[cmd_pos++] = ' ';
 			}
 			break;
 		}

-----------------------------------------------------------------------

Summary of changes:
 src/svf/svf.c |   36 +++++++++++++++++++++++++++++-------
 1 files changed, 29 insertions(+), 7 deletions(-)


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[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-rc1-146-g718ee76

From: David B. <dbr...@us...> - 2010-01-23 07:57:24

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  718ee762e7d6a81037670612a2f3d21da4784f56 (commit)
      from  82c3c47825b25012fef60df0a8a89110337cd40d (commit)

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- Log -----------------------------------------------------------------
commit 718ee762e7d6a81037670612a2f3d21da4784f56
Author: David Brownell <dbr...@us...>
Date:   Fri Jan 22 22:54:39 2010 -0800

    EmbeddedICE - fix Feroceon/Dragonite message
    
    The breakpoint/watchpoint message was wrong for Feroceon and
    Dragonite, which have only one working watchpoint unit.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index a705d7d..bf22036 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -192,6 +192,11 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
 	reg_cache->reg_list = reg_list;
 	reg_cache->num_regs = num_regs;
 
+	/* FIXME the second watchpoint unit on Feroceon and Dragonite
+	 * seems not to work ... we should have a way to not set up
+	 * its four registers here!
+	 */
+
 	/* set up registers */
 	for (i = 0; i < num_regs; i++)
 	{
@@ -290,8 +295,10 @@ embeddedice_build_reg_cache(struct target *target, struct arm7_9_common *arm7_9)
 				buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 	}
 
-	LOG_INFO("%s: hardware has 2 breakpoints or watchpoints",
-			target_name(target));
+	/* On Feroceon and Dragonite the second unit is seemingly missing. */
+	LOG_INFO("%s: hardware has %d breakpoint/watchpoint unit%s",
+			target_name(target), arm7_9->wp_available_max,
+			(arm7_9->wp_available_max != 1) ? "s" : "");
 
 	return reg_cache;
 }

-----------------------------------------------------------------------

Summary of changes:
 src/target/embeddedice.c |   11 +++++++++--
 1 files changed, 9 insertions(+), 2 deletions(-)


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